projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Implement WM8350 headphone jack detection
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
14 * - Mic detect.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
25#include <linux/platform_device.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33
34#include "wm8903.h"
35
f1c0a02f
MB		 36/* Register defaults at reset */
37static u16 wm8903_reg_defaults[] = {
38 0x8903, /* R0 - SW Reset and ID */
39 0x0000, /* R1 - Revision Number */
40 0x0000, /* R2 */
41 0x0000, /* R3 */
42 0x0018, /* R4 - Bias Control 0 */
43 0x0000, /* R5 - VMID Control 0 */
44 0x0000, /* R6 - Mic Bias Control 0 */
45 0x0000, /* R7 */
46 0x0001, /* R8 - Analogue DAC 0 */
47 0x0000, /* R9 */
48 0x0001, /* R10 - Analogue ADC 0 */
49 0x0000, /* R11 */
50 0x0000, /* R12 - Power Management 0 */
51 0x0000, /* R13 - Power Management 1 */
52 0x0000, /* R14 - Power Management 2 */
53 0x0000, /* R15 - Power Management 3 */
54 0x0000, /* R16 - Power Management 4 */
55 0x0000, /* R17 - Power Management 5 */
56 0x0000, /* R18 - Power Management 6 */
57 0x0000, /* R19 */
58 0x0400, /* R20 - Clock Rates 0 */
59 0x0D07, /* R21 - Clock Rates 1 */
60 0x0000, /* R22 - Clock Rates 2 */
61 0x0000, /* R23 */
62 0x0050, /* R24 - Audio Interface 0 */
63 0x0242, /* R25 - Audio Interface 1 */
64 0x0008, /* R26 - Audio Interface 2 */
65 0x0022, /* R27 - Audio Interface 3 */
66 0x0000, /* R28 */
67 0x0000, /* R29 */
68 0x00C0, /* R30 - DAC Digital Volume Left */
69 0x00C0, /* R31 - DAC Digital Volume Right */
70 0x0000, /* R32 - DAC Digital 0 */
71 0x0000, /* R33 - DAC Digital 1 */
72 0x0000, /* R34 */
73 0x0000, /* R35 */
74 0x00C0, /* R36 - ADC Digital Volume Left */
75 0x00C0, /* R37 - ADC Digital Volume Right */
76 0x0000, /* R38 - ADC Digital 0 */
77 0x0073, /* R39 - Digital Microphone 0 */
78 0x09BF, /* R40 - DRC 0 */
79 0x3241, /* R41 - DRC 1 */
80 0x0020, /* R42 - DRC 2 */
81 0x0000, /* R43 - DRC 3 */
82 0x0085, /* R44 - Analogue Left Input 0 */
83 0x0085, /* R45 - Analogue Right Input 0 */
84 0x0044, /* R46 - Analogue Left Input 1 */
85 0x0044, /* R47 - Analogue Right Input 1 */
86 0x0000, /* R48 */
87 0x0000, /* R49 */
88 0x0008, /* R50 - Analogue Left Mix 0 */
89 0x0004, /* R51 - Analogue Right Mix 0 */
90 0x0000, /* R52 - Analogue Spk Mix Left 0 */
91 0x0000, /* R53 - Analogue Spk Mix Left 1 */
92 0x0000, /* R54 - Analogue Spk Mix Right 0 */
93 0x0000, /* R55 - Analogue Spk Mix Right 1 */
94 0x0000, /* R56 */
95 0x002D, /* R57 - Analogue OUT1 Left */
96 0x002D, /* R58 - Analogue OUT1 Right */
97 0x0039, /* R59 - Analogue OUT2 Left */
98 0x0039, /* R60 - Analogue OUT2 Right */
99 0x0100, /* R61 */
100 0x0139, /* R62 - Analogue OUT3 Left */
101 0x0139, /* R63 - Analogue OUT3 Right */
102 0x0000, /* R64 */
103 0x0000, /* R65 - Analogue SPK Output Control 0 */
104 0x0000, /* R66 */
105 0x0010, /* R67 - DC Servo 0 */
106 0x0100, /* R68 */
107 0x00A4, /* R69 - DC Servo 2 */
108 0x0807, /* R70 */
109 0x0000, /* R71 */
110 0x0000, /* R72 */
111 0x0000, /* R73 */
112 0x0000, /* R74 */
113 0x0000, /* R75 */
114 0x0000, /* R76 */
115 0x0000, /* R77 */
116 0x0000, /* R78 */
117 0x000E, /* R79 */
118 0x0000, /* R80 */
119 0x0000, /* R81 */
120 0x0000, /* R82 */
121 0x0000, /* R83 */
122 0x0000, /* R84 */
123 0x0000, /* R85 */
124 0x0000, /* R86 */
125 0x0006, /* R87 */
126 0x0000, /* R88 */
127 0x0000, /* R89 */
128 0x0000, /* R90 - Analogue HP 0 */
129 0x0060, /* R91 */
130 0x0000, /* R92 */
131 0x0000, /* R93 */
132 0x0000, /* R94 - Analogue Lineout 0 */
133 0x0060, /* R95 */
134 0x0000, /* R96 */
135 0x0000, /* R97 */
136 0x0000, /* R98 - Charge Pump 0 */
137 0x1F25, /* R99 */
138 0x2B19, /* R100 */
139 0x01C0, /* R101 */
140 0x01EF, /* R102 */
141 0x2B00, /* R103 */
142 0x0000, /* R104 - Class W 0 */
143 0x01C0, /* R105 */
144 0x1C10, /* R106 */
145 0x0000, /* R107 */
146 0x0000, /* R108 - Write Sequencer 0 */
147 0x0000, /* R109 - Write Sequencer 1 */
148 0x0000, /* R110 - Write Sequencer 2 */
149 0x0000, /* R111 - Write Sequencer 3 */
150 0x0000, /* R112 - Write Sequencer 4 */
151 0x0000, /* R113 */
152 0x0000, /* R114 - Control Interface */
153 0x0000, /* R115 */
154 0x00A8, /* R116 - GPIO Control 1 */
155 0x00A8, /* R117 - GPIO Control 2 */
156 0x00A8, /* R118 - GPIO Control 3 */
157 0x0220, /* R119 - GPIO Control 4 */
158 0x01A0, /* R120 - GPIO Control 5 */
159 0x0000, /* R121 - Interrupt Status 1 */
160 0xFFFF, /* R122 - Interrupt Status 1 Mask */
161 0x0000, /* R123 - Interrupt Polarity 1 */
162 0x0000, /* R124 */
163 0x0003, /* R125 */
164 0x0000, /* R126 - Interrupt Control */
165 0x0000, /* R127 */
166 0x0005, /* R128 */
167 0x0000, /* R129 - Control Interface Test 1 */
168 0x0000, /* R130 */
169 0x0000, /* R131 */
170 0x0000, /* R132 */
171 0x0000, /* R133 */
172 0x0000, /* R134 */
173 0x03FF, /* R135 */
174 0x0007, /* R136 */
175 0x0040, /* R137 */
176 0x0000, /* R138 */
177 0x0000, /* R139 */
178 0x0000, /* R140 */
179 0x0000, /* R141 */
180 0x0000, /* R142 */
181 0x0000, /* R143 */
182 0x0000, /* R144 */
183 0x0000, /* R145 */
184 0x0000, /* R146 */
185 0x0000, /* R147 */
186 0x4000, /* R148 */
187 0x6810, /* R149 - Charge Pump Test 1 */
188 0x0004, /* R150 */
189 0x0000, /* R151 */
190 0x0000, /* R152 */
191 0x0000, /* R153 */
192 0x0000, /* R154 */
193 0x0000, /* R155 */
194 0x0000, /* R156 */
195 0x0000, /* R157 */
196 0x0000, /* R158 */
197 0x0000, /* R159 */
198 0x0000, /* R160 */
199 0x0000, /* R161 */
200 0x0000, /* R162 */
201 0x0000, /* R163 */
202 0x0028, /* R164 - Clock Rate Test 4 */
203 0x0004, /* R165 */
204 0x0000, /* R166 */
205 0x0060, /* R167 */
206 0x0000, /* R168 */
207 0x0000, /* R169 */
208 0x0000, /* R170 */
209 0x0000, /* R171 */
210 0x0000, /* R172 - Analogue Output Bias 0 */
211};
212
d58d5d55
MB		 213struct wm8903_priv {
214 struct snd_soc_codec codec;
215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
216
217 int sysclk;
218
219 /* Reference counts */
220 int charge_pump_users;
221 int class_w_users;
222 int playback_active;
223 int capture_active;
224
225 struct snd_pcm_substream *master_substream;
226 struct snd_pcm_substream *slave_substream;
227};
228
229
f1c0a02f
MB		 230static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
231 unsigned int reg)
232{
233 u16 *cache = codec->reg_cache;
234
235 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
236
237 return cache[reg];
238}
239
240static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
241{
242 struct i2c_msg xfer[2];
243 u16 data;
244 int ret;
245 struct i2c_client *client = codec->control_data;
246
247 /* Write register */
248 xfer[0].addr = client->addr;
249 xfer[0].flags = 0;
250 xfer[0].len = 1;
251 xfer[0].buf = &reg;
252
253 /* Read data */
254 xfer[1].addr = client->addr;
255 xfer[1].flags = I2C_M_RD;
256 xfer[1].len = 2;
257 xfer[1].buf = (u8 *)&data;
258
259 ret = i2c_transfer(client->adapter, xfer, 2);
260 if (ret != 2) {
261 pr_err("i2c_transfer returned %d\n", ret);
262 return 0;
263 }
264
265 return (data >> 8) | ((data & 0xff) << 8);
266}
267
268static unsigned int wm8903_read(struct snd_soc_codec *codec,
269 unsigned int reg)
270{
271 switch (reg) {
272 case WM8903_SW_RESET_AND_ID:
273 case WM8903_REVISION_NUMBER:
274 case WM8903_INTERRUPT_STATUS_1:
275 case WM8903_WRITE_SEQUENCER_4:
276 return wm8903_hw_read(codec, reg);
277
278 default:
279 return wm8903_read_reg_cache(codec, reg);
280 }
281}
282
283static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
284 u16 reg, unsigned int value)
285{
286 u16 *cache = codec->reg_cache;
287
288 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
289
290 switch (reg) {
291 case WM8903_SW_RESET_AND_ID:
292 case WM8903_REVISION_NUMBER:
293 break;
294
295 default:
296 cache[reg] = value;
297 break;
298 }
299}
300
301static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
302 unsigned int value)
303{
304 u8 data[3];
305
306 wm8903_write_reg_cache(codec, reg, value);
307
308 /* Data format is 1 byte of address followed by 2 bytes of data */
309 data[0] = reg;
310 data[1] = (value >> 8) & 0xff;
311 data[2] = value & 0xff;
312
313 if (codec->hw_write(codec->control_data, data, 3) == 2)
314 return 0;
315 else
316 return -EIO;
317}
318
319static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
320{
321 u16 reg[5];
322 struct i2c_client *i2c = codec->control_data;
323
324 BUG_ON(start > 48);
325
326 /* Enable the sequencer */
327 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
328 reg[0] |= WM8903_WSEQ_ENA;
329 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
330
331 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
332
333 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
334 start | WM8903_WSEQ_START);
335
336 /* Wait for it to complete. If we have the interrupt wired up then
337 * we could block waiting for an interrupt, though polling may still
338 * be desirable for diagnostic purposes.
339 */
340 do {
341 msleep(10);
342
343 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
344 } while (reg[4] & WM8903_WSEQ_BUSY);
345
346 dev_dbg(&i2c->dev, "Sequence complete\n");
347
348 /* Disable the sequencer again */
349 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
350 reg[0] & ~WM8903_WSEQ_ENA);
351
352 return 0;
353}
354
355static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
356{
357 int i;
358
359 /* There really ought to be something better we can do here :/ */
360 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
361 cache[i] = wm8903_hw_read(codec, i);
362}
363
364static void wm8903_reset(struct snd_soc_codec *codec)
365{
366 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 367 memcpy(codec->reg_cache, wm8903_reg_defaults,
368 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 369}
370
371#define WM8903_OUTPUT_SHORT 0x8
372#define WM8903_OUTPUT_OUT 0x4
373#define WM8903_OUTPUT_INT 0x2
374#define WM8903_OUTPUT_IN 0x1
375
376/*
377 * Event for headphone and line out amplifier power changes. Special
378 * power up/down sequences are required in order to maximise pop/click
379 * performance.
380 */
381static int wm8903_output_event(struct snd_soc_dapm_widget *w,
382 struct snd_kcontrol *kcontrol, int event)
383{
384 struct snd_soc_codec *codec = w->codec;
385 struct wm8903_priv *wm8903 = codec->private_data;
386 struct i2c_client *i2c = codec->control_data;
387 u16 val;
0bc286e2
TI		 388 u16 reg;
389 int shift;
f1c0a02f
MB		 390 u16 cp_reg = wm8903_read(codec, WM8903_CHARGE_PUMP_0);
391
392 switch (w->reg) {
393 case WM8903_POWER_MANAGEMENT_2:
394 reg = WM8903_ANALOGUE_HP_0;
395 break;
396 case WM8903_POWER_MANAGEMENT_3:
397 reg = WM8903_ANALOGUE_LINEOUT_0;
398 break;
399 default:
400 BUG();
1e297a19 401 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 402 }
403
404 switch (w->shift) {
405 case 0:
406 shift = 0;
407 break;
408 case 1:
409 shift = 4;
410 break;
411 default:
412 BUG();
1e297a19 413 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 414 }
415
416 if (event & SND_SOC_DAPM_PRE_PMU) {
417 val = wm8903_read(codec, reg);
418
419 /* Short the output */
420 val &= ~(WM8903_OUTPUT_SHORT << shift);
421 wm8903_write(codec, reg, val);
422
423 wm8903->charge_pump_users++;
424
425 dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
426 wm8903->charge_pump_users);
427
428 if (wm8903->charge_pump_users == 1) {
429 dev_dbg(&i2c->dev, "Enabling charge pump\n");
430 wm8903_write(codec, WM8903_CHARGE_PUMP_0,
431 cp_reg | WM8903_CP_ENA);
432 mdelay(4);
433 }
434 }
435
436 if (event & SND_SOC_DAPM_POST_PMU) {
437 val = wm8903_read(codec, reg);
438
439 val |= (WM8903_OUTPUT_IN << shift);
440 wm8903_write(codec, reg, val);
441
442 val |= (WM8903_OUTPUT_INT << shift);
443 wm8903_write(codec, reg, val);
444
445 /* Turn on the output ENA_OUTP */
446 val |= (WM8903_OUTPUT_OUT << shift);
447 wm8903_write(codec, reg, val);
448
449 /* Remove the short */
450 val |= (WM8903_OUTPUT_SHORT << shift);
451 wm8903_write(codec, reg, val);
452 }
453
454 if (event & SND_SOC_DAPM_PRE_PMD) {
455 val = wm8903_read(codec, reg);
456
457 /* Short the output */
458 val &= ~(WM8903_OUTPUT_SHORT << shift);
459 wm8903_write(codec, reg, val);
460
461 /* Then disable the intermediate and output stages */
462 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
463 WM8903_OUTPUT_IN) << shift);
464 wm8903_write(codec, reg, val);
465 }
466
467 if (event & SND_SOC_DAPM_POST_PMD) {
468 wm8903->charge_pump_users--;
469
470 dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
471 wm8903->charge_pump_users);
472
473 if (wm8903->charge_pump_users == 0) {
474 dev_dbg(&i2c->dev, "Disabling charge pump\n");
475 wm8903_write(codec, WM8903_CHARGE_PUMP_0,
476 cp_reg & ~WM8903_CP_ENA);
477 }
478 }
479
480 return 0;
481}
482
483/*
484 * When used with DAC outputs only the WM8903 charge pump supports
485 * operation in class W mode, providing very low power consumption
486 * when used with digital sources. Enable and disable this mode
487 * automatically depending on the mixer configuration.
488 *
489 * All the relevant controls are simple switches.
490 */
491static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
492 struct snd_ctl_elem_value *ucontrol)
493{
494 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
495 struct snd_soc_codec *codec = widget->codec;
496 struct wm8903_priv *wm8903 = codec->private_data;
497 struct i2c_client *i2c = codec->control_data;
498 u16 reg;
499 int ret;
500
501 reg = wm8903_read(codec, WM8903_CLASS_W_0);
502
503 /* Turn it off if we're about to enable bypass */
504 if (ucontrol->value.integer.value[0]) {
505 if (wm8903->class_w_users == 0) {
506 dev_dbg(&i2c->dev, "Disabling Class W\n");
507 wm8903_write(codec, WM8903_CLASS_W_0, reg &
508 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
509 }
510 wm8903->class_w_users++;
511 }
512
513 /* Implement the change */
514 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
515
516 /* If we've just disabled the last bypass path turn Class W on */
517 if (!ucontrol->value.integer.value[0]) {
518 if (wm8903->class_w_users == 1) {
519 dev_dbg(&i2c->dev, "Enabling Class W\n");
520 wm8903_write(codec, WM8903_CLASS_W_0, reg |
521 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
522 }
523 wm8903->class_w_users--;
524 }
525
526 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
527 wm8903->class_w_users);
528
529 return ret;
530}
531
532#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
533{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
534 .info = snd_soc_info_volsw, \
535 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
536 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
537
538
539/* ALSA can only do steps of .01dB */
540static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
541
542static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
543
544static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
545static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
546static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
547static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
548static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
549
550static const char *drc_slope_text[] = {
551 "1", "1/2", "1/4", "1/8", "1/16", "0"
552};
553
554static const struct soc_enum drc_slope_r0 =
555 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
556
557static const struct soc_enum drc_slope_r1 =
558 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
559
560static const char *drc_attack_text[] = {
561 "instantaneous",
562 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
563 "46.4ms", "92.8ms", "185.6ms"
564};
565
566static const struct soc_enum drc_attack =
567 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
568
569static const char *drc_decay_text[] = {
570 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
571 "23.87s", "47.56s"
572};
573
574static const struct soc_enum drc_decay =
575 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
576
577static const char *drc_ff_delay_text[] = {
578 "5 samples", "9 samples"
579};
580
581static const struct soc_enum drc_ff_delay =
582 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
583
584static const char *drc_qr_decay_text[] = {
585 "0.725ms", "1.45ms", "5.8ms"
586};
587
588static const struct soc_enum drc_qr_decay =
589 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
590
591static const char *drc_smoothing_text[] = {
592 "Low", "Medium", "High"
593};
594
595static const struct soc_enum drc_smoothing =
596 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
597
598static const char *soft_mute_text[] = {
599 "Fast (fs/2)", "Slow (fs/32)"
600};
601
602static const struct soc_enum soft_mute =
603 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
604
605static const char *mute_mode_text[] = {
606 "Hard", "Soft"
607};
608
609static const struct soc_enum mute_mode =
610 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
611
612static const char *dac_deemphasis_text[] = {
613 "Disabled", "32kHz", "44.1kHz", "48kHz"
614};
615
616static const struct soc_enum dac_deemphasis =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
618
619static const char *companding_text[] = {
620 "ulaw", "alaw"
621};
622
623static const struct soc_enum dac_companding =
624 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
625
626static const struct soc_enum adc_companding =
627 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
628
629static const char *input_mode_text[] = {
630 "Single-Ended", "Differential Line", "Differential Mic"
631};
632
633static const struct soc_enum linput_mode_enum =
634 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
635
636static const struct soc_enum rinput_mode_enum =
637 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
638
639static const char *linput_mux_text[] = {
640 "IN1L", "IN2L", "IN3L"
641};
642
643static const struct soc_enum linput_enum =
644 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
645
646static const struct soc_enum linput_inv_enum =
647 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
648
649static const char *rinput_mux_text[] = {
650 "IN1R", "IN2R", "IN3R"
651};
652
653static const struct soc_enum rinput_enum =
654 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
655
656static const struct soc_enum rinput_inv_enum =
657 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
658
659
660static const struct snd_kcontrol_new wm8903_snd_controls[] = {
661
662/* Input PGAs - No TLV since the scale depends on PGA mode */
663SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 664 7, 1, 1),
f1c0a02f
MB		 665SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
666 0, 31, 0),
667SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
668 6, 1, 0),
669
670SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 671 7, 1, 1),
f1c0a02f
MB		 672SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
673 0, 31, 0),
674SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
675 6, 1, 0),
676
677/* ADCs */
678SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
679SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
680SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
681SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
682 drc_tlv_thresh),
683SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
684SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
685SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
686SOC_ENUM("DRC Attack Rate", drc_attack),
687SOC_ENUM("DRC Decay Rate", drc_decay),
688SOC_ENUM("DRC FF Delay", drc_ff_delay),
689SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
690SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
691SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
692SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
693SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
694SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
695SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
696SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
697
698SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
699 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
700SOC_ENUM("ADC Companding Mode", adc_companding),
701SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
702
703/* DAC */
704SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
705 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
706SOC_ENUM("DAC Soft Mute Rate", soft_mute),
707SOC_ENUM("DAC Mute Mode", mute_mode),
708SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
709SOC_ENUM("DAC De-emphasis", dac_deemphasis),
710SOC_SINGLE("DAC Sloping Stopband Filter Switch",
711 WM8903_DAC_DIGITAL_1, 11, 1, 0),
712SOC_ENUM("DAC Companding Mode", dac_companding),
713SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
714
715/* Headphones */
716SOC_DOUBLE_R("Headphone Switch",
717 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
718 8, 1, 1),
719SOC_DOUBLE_R("Headphone ZC Switch",
720 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
721 6, 1, 0),
722SOC_DOUBLE_R_TLV("Headphone Volume",
723 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
724 0, 63, 0, out_tlv),
725
726/* Line out */
727SOC_DOUBLE_R("Line Out Switch",
728 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
729 8, 1, 1),
730SOC_DOUBLE_R("Line Out ZC Switch",
731 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
732 6, 1, 0),
733SOC_DOUBLE_R_TLV("Line Out Volume",
734 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
735 0, 63, 0, out_tlv),
736
737/* Speaker */
738SOC_DOUBLE_R("Speaker Switch",
739 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
740SOC_DOUBLE_R("Speaker ZC Switch",
741 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
742SOC_DOUBLE_R_TLV("Speaker Volume",
743 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
744 0, 63, 0, out_tlv),
745};
746
747static int wm8903_add_controls(struct snd_soc_codec *codec)
748{
749 int err, i;
750
751 for (i = 0; i < ARRAY_SIZE(wm8903_snd_controls); i++) {
752 err = snd_ctl_add(codec->card,
753 snd_soc_cnew(&wm8903_snd_controls[i],
754 codec, NULL));
755 if (err < 0)
756 return err;
757 }
758
759 return 0;
760}
761
762static const struct snd_kcontrol_new linput_mode_mux =
763 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
764
765static const struct snd_kcontrol_new rinput_mode_mux =
766 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
767
768static const struct snd_kcontrol_new linput_mux =
769 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
770
771static const struct snd_kcontrol_new linput_inv_mux =
772 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
773
774static const struct snd_kcontrol_new rinput_mux =
775 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
776
777static const struct snd_kcontrol_new rinput_inv_mux =
778 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
779
780static const struct snd_kcontrol_new left_output_mixer[] = {
781SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
782SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
783SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 784SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 785};
786
787static const struct snd_kcontrol_new right_output_mixer[] = {
788SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
789SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
790SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 791SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 792};
793
794static const struct snd_kcontrol_new left_speaker_mixer[] = {
795SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
796SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
797SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
798SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 799 0, 1, 0),
f1c0a02f
MB		 800};
801
802static const struct snd_kcontrol_new right_speaker_mixer[] = {
803SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
804SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
805SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
806 1, 1, 0),
807SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 808 0, 1, 0),
f1c0a02f
MB		 809};
810
811static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
812SND_SOC_DAPM_INPUT("IN1L"),
813SND_SOC_DAPM_INPUT("IN1R"),
814SND_SOC_DAPM_INPUT("IN2L"),
815SND_SOC_DAPM_INPUT("IN2R"),
816SND_SOC_DAPM_INPUT("IN3L"),
817SND_SOC_DAPM_INPUT("IN3R"),
818
819SND_SOC_DAPM_OUTPUT("HPOUTL"),
820SND_SOC_DAPM_OUTPUT("HPOUTR"),
821SND_SOC_DAPM_OUTPUT("LINEOUTL"),
822SND_SOC_DAPM_OUTPUT("LINEOUTR"),
823SND_SOC_DAPM_OUTPUT("LOP"),
824SND_SOC_DAPM_OUTPUT("LON"),
825SND_SOC_DAPM_OUTPUT("ROP"),
826SND_SOC_DAPM_OUTPUT("RON"),
827
828SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
829
830SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
831SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
832 &linput_inv_mux),
833SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
834
835SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
836SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
837 &rinput_inv_mux),
838SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
839
840SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
841SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
842
843SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
844SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
845
846SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
847SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
848
849SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
850 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
851SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
852 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
853
854SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
855 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
856SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
857 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
858
859SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
860 1, 0, NULL, 0, wm8903_output_event,
861 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
862 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
863SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
864 0, 0, NULL, 0, wm8903_output_event,
865 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
866 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
867
868SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
869 NULL, 0, wm8903_output_event,
870 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
871 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
872SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
873 NULL, 0, wm8903_output_event,
874 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
875 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
876
877SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
878 NULL, 0),
879SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
880 NULL, 0),
881
882};
883
884static const struct snd_soc_dapm_route intercon[] = {
885
886 { "Left Input Mux", "IN1L", "IN1L" },
887 { "Left Input Mux", "IN2L", "IN2L" },
888 { "Left Input Mux", "IN3L", "IN3L" },
889
890 { "Left Input Inverting Mux", "IN1L", "IN1L" },
891 { "Left Input Inverting Mux", "IN2L", "IN2L" },
892 { "Left Input Inverting Mux", "IN3L", "IN3L" },
893
894 { "Right Input Mux", "IN1R", "IN1R" },
895 { "Right Input Mux", "IN2R", "IN2R" },
896 { "Right Input Mux", "IN3R", "IN3R" },
897
898 { "Right Input Inverting Mux", "IN1R", "IN1R" },
899 { "Right Input Inverting Mux", "IN2R", "IN2R" },
900 { "Right Input Inverting Mux", "IN3R", "IN3R" },
901
902 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
903 { "Left Input Mode Mux", "Differential Line",
904 "Left Input Mux" },
905 { "Left Input Mode Mux", "Differential Line",
906 "Left Input Inverting Mux" },
907 { "Left Input Mode Mux", "Differential Mic",
908 "Left Input Mux" },
909 { "Left Input Mode Mux", "Differential Mic",
910 "Left Input Inverting Mux" },
911
912 { "Right Input Mode Mux", "Single-Ended",
913 "Right Input Inverting Mux" },
914 { "Right Input Mode Mux", "Differential Line",
915 "Right Input Mux" },
916 { "Right Input Mode Mux", "Differential Line",
917 "Right Input Inverting Mux" },
918 { "Right Input Mode Mux", "Differential Mic",
919 "Right Input Mux" },
920 { "Right Input Mode Mux", "Differential Mic",
921 "Right Input Inverting Mux" },
922
923 { "Left Input PGA", NULL, "Left Input Mode Mux" },
924 { "Right Input PGA", NULL, "Right Input Mode Mux" },
925
926 { "ADCL", NULL, "Left Input PGA" },
927 { "ADCR", NULL, "Right Input PGA" },
928
929 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
930 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
931 { "Left Output Mixer", "DACL Switch", "DACL" },
932 { "Left Output Mixer", "DACR Switch", "DACR" },
933
934 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
935 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
936 { "Right Output Mixer", "DACL Switch", "DACL" },
937 { "Right Output Mixer", "DACR Switch", "DACR" },
938
939 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
940 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
941 { "Left Speaker Mixer", "DACL Switch", "DACL" },
942 { "Left Speaker Mixer", "DACR Switch", "DACR" },
943
944 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
945 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
946 { "Right Speaker Mixer", "DACL Switch", "DACL" },
947 { "Right Speaker Mixer", "DACR Switch", "DACR" },
948
949 { "Left Line Output PGA", NULL, "Left Output Mixer" },
950 { "Right Line Output PGA", NULL, "Right Output Mixer" },
951
952 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
953 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
954
955 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
956 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
957
958 { "HPOUTL", NULL, "Left Headphone Output PGA" },
959 { "HPOUTR", NULL, "Right Headphone Output PGA" },
960
961 { "LINEOUTL", NULL, "Left Line Output PGA" },
962 { "LINEOUTR", NULL, "Right Line Output PGA" },
963
964 { "LOP", NULL, "Left Speaker PGA" },
965 { "LON", NULL, "Left Speaker PGA" },
966
967 { "ROP", NULL, "Right Speaker PGA" },
968 { "RON", NULL, "Right Speaker PGA" },
969};
970
971static int wm8903_add_widgets(struct snd_soc_codec *codec)
972{
973 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
974 ARRAY_SIZE(wm8903_dapm_widgets));
975
976 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
977
978 snd_soc_dapm_new_widgets(codec);
979
980 return 0;
981}
982
983static int wm8903_set_bias_level(struct snd_soc_codec *codec,
984 enum snd_soc_bias_level level)
985{
986 struct i2c_client *i2c = codec->control_data;
987 u16 reg, reg2;
988
989 switch (level) {
990 case SND_SOC_BIAS_ON:
991 case SND_SOC_BIAS_PREPARE:
992 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
993 reg &= ~(WM8903_VMID_RES_MASK);
994 reg |= WM8903_VMID_RES_50K;
995 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
996 break;
997
998 case SND_SOC_BIAS_STANDBY:
999 if (codec->bias_level == SND_SOC_BIAS_OFF) {
3b1228ab
MB		 1000 wm8903_write(codec, WM8903_CLOCK_RATES_2,
1001 WM8903_CLK_SYS_ENA);
1002
f1c0a02f
MB		 1003 wm8903_run_sequence(codec, 0);
1004 wm8903_sync_reg_cache(codec, codec->reg_cache);
1005
1006 /* Enable low impedence charge pump output */
1007 reg = wm8903_read(codec,
1008 WM8903_CONTROL_INTERFACE_TEST_1);
1009 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1010 reg | WM8903_TEST_KEY);
1011 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1012 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1013 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1014 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1015 reg);
1016
1017 /* By default no bypass paths are enabled so
1018 * enable Class W support.
1019 */
1020 dev_dbg(&i2c->dev, "Enabling Class W\n");
1021 wm8903_write(codec, WM8903_CLASS_W_0, reg |
1022 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1023 }
1024
1025 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1026 reg &= ~(WM8903_VMID_RES_MASK);
1027 reg |= WM8903_VMID_RES_250K;
1028 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1029 break;
1030
1031 case SND_SOC_BIAS_OFF:
1032 wm8903_run_sequence(codec, 32);
3b1228ab
MB		 1033 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2);
1034 reg &= ~WM8903_CLK_SYS_ENA;
1035 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1036 break;
1037 }
1038
1039 codec->bias_level = level;
1040
1041 return 0;
1042}
1043
1044static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1045 int clk_id, unsigned int freq, int dir)
1046{
1047 struct snd_soc_codec *codec = codec_dai->codec;
1048 struct wm8903_priv *wm8903 = codec->private_data;
1049
1050 wm8903->sysclk = freq;
1051
1052 return 0;
1053}
1054
1055static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1056 unsigned int fmt)
1057{
1058 struct snd_soc_codec *codec = codec_dai->codec;
1059 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1060
1061 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1062 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1063
1064 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1065 case SND_SOC_DAIFMT_CBS_CFS:
1066 break;
1067 case SND_SOC_DAIFMT_CBS_CFM:
1068 aif1 |= WM8903_LRCLK_DIR;
1069 break;
1070 case SND_SOC_DAIFMT_CBM_CFM:
1071 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1072 break;
1073 case SND_SOC_DAIFMT_CBM_CFS:
1074 aif1 |= WM8903_BCLK_DIR;
1075 break;
1076 default:
1077 return -EINVAL;
1078 }
1079
1080 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1081 case SND_SOC_DAIFMT_DSP_A:
1082 aif1 |= 0x3;
1083 break;
1084 case SND_SOC_DAIFMT_DSP_B:
1085 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1086 break;
1087 case SND_SOC_DAIFMT_I2S:
1088 aif1 |= 0x2;
1089 break;
1090 case SND_SOC_DAIFMT_RIGHT_J:
1091 aif1 |= 0x1;
1092 break;
1093 case SND_SOC_DAIFMT_LEFT_J:
1094 break;
1095 default:
1096 return -EINVAL;
1097 }
1098
1099 /* Clock inversion */
1100 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1101 case SND_SOC_DAIFMT_DSP_A:
1102 case SND_SOC_DAIFMT_DSP_B:
1103 /* frame inversion not valid for DSP modes */
1104 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1105 case SND_SOC_DAIFMT_NB_NF:
1106 break;
1107 case SND_SOC_DAIFMT_IB_NF:
1108 aif1 |= WM8903_AIF_BCLK_INV;
1109 break;
1110 default:
1111 return -EINVAL;
1112 }
1113 break;
1114 case SND_SOC_DAIFMT_I2S:
1115 case SND_SOC_DAIFMT_RIGHT_J:
1116 case SND_SOC_DAIFMT_LEFT_J:
1117 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1118 case SND_SOC_DAIFMT_NB_NF:
1119 break;
1120 case SND_SOC_DAIFMT_IB_IF:
1121 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1122 break;
1123 case SND_SOC_DAIFMT_IB_NF:
1124 aif1 |= WM8903_AIF_BCLK_INV;
1125 break;
1126 case SND_SOC_DAIFMT_NB_IF:
1127 aif1 |= WM8903_AIF_LRCLK_INV;
1128 break;
1129 default:
1130 return -EINVAL;
1131 }
1132 break;
1133 default:
1134 return -EINVAL;
1135 }
1136
1137 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1138
1139 return 0;
1140}
1141
1142static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1143{
1144 struct snd_soc_codec *codec = codec_dai->codec;
1145 u16 reg;
1146
1147 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1148
1149 if (mute)
1150 reg |= WM8903_DAC_MUTE;
1151 else
1152 reg &= ~WM8903_DAC_MUTE;
1153
1154 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1155
1156 return 0;
1157}
1158
1159/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1160 * for optimal performance so we list the lower rates first and match
1161 * on the last match we find. */
1162static struct {
1163 int div;
1164 int rate;
1165 int mode;
1166 int mclk_div;
1167} clk_sys_ratios[] = {
1168 { 64, 0x0, 0x0, 1 },
1169 { 68, 0x0, 0x1, 1 },
1170 { 125, 0x0, 0x2, 1 },
1171 { 128, 0x1, 0x0, 1 },
1172 { 136, 0x1, 0x1, 1 },
1173 { 192, 0x2, 0x0, 1 },
1174 { 204, 0x2, 0x1, 1 },
1175
1176 { 64, 0x0, 0x0, 2 },
1177 { 68, 0x0, 0x1, 2 },
1178 { 125, 0x0, 0x2, 2 },
1179 { 128, 0x1, 0x0, 2 },
1180 { 136, 0x1, 0x1, 2 },
1181 { 192, 0x2, 0x0, 2 },
1182 { 204, 0x2, 0x1, 2 },
1183
1184 { 250, 0x2, 0x2, 1 },
1185 { 256, 0x3, 0x0, 1 },
1186 { 272, 0x3, 0x1, 1 },
1187 { 384, 0x4, 0x0, 1 },
1188 { 408, 0x4, 0x1, 1 },
1189 { 375, 0x4, 0x2, 1 },
1190 { 512, 0x5, 0x0, 1 },
1191 { 544, 0x5, 0x1, 1 },
1192 { 500, 0x5, 0x2, 1 },
1193 { 768, 0x6, 0x0, 1 },
1194 { 816, 0x6, 0x1, 1 },
1195 { 750, 0x6, 0x2, 1 },
1196 { 1024, 0x7, 0x0, 1 },
1197 { 1088, 0x7, 0x1, 1 },
1198 { 1000, 0x7, 0x2, 1 },
1199 { 1408, 0x8, 0x0, 1 },
1200 { 1496, 0x8, 0x1, 1 },
1201 { 1536, 0x9, 0x0, 1 },
1202 { 1632, 0x9, 0x1, 1 },
1203 { 1500, 0x9, 0x2, 1 },
1204
1205 { 250, 0x2, 0x2, 2 },
1206 { 256, 0x3, 0x0, 2 },
1207 { 272, 0x3, 0x1, 2 },
1208 { 384, 0x4, 0x0, 2 },
1209 { 408, 0x4, 0x1, 2 },
1210 { 375, 0x4, 0x2, 2 },
1211 { 512, 0x5, 0x0, 2 },
1212 { 544, 0x5, 0x1, 2 },
1213 { 500, 0x5, 0x2, 2 },
1214 { 768, 0x6, 0x0, 2 },
1215 { 816, 0x6, 0x1, 2 },
1216 { 750, 0x6, 0x2, 2 },
1217 { 1024, 0x7, 0x0, 2 },
1218 { 1088, 0x7, 0x1, 2 },
1219 { 1000, 0x7, 0x2, 2 },
1220 { 1408, 0x8, 0x0, 2 },
1221 { 1496, 0x8, 0x1, 2 },
1222 { 1536, 0x9, 0x0, 2 },
1223 { 1632, 0x9, 0x1, 2 },
1224 { 1500, 0x9, 0x2, 2 },
1225};
1226
1227/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1228static struct {
1229 int ratio;
1230 int div;
1231} bclk_divs[] = {
1232 { 10, 0 },
1233 { 15, 1 },
1234 { 20, 2 },
1235 { 30, 3 },
1236 { 40, 4 },
1237 { 50, 5 },
1238 { 55, 6 },
1239 { 60, 7 },
1240 { 80, 8 },
1241 { 100, 9 },
1242 { 110, 10 },
1243 { 120, 11 },
1244 { 160, 12 },
1245 { 200, 13 },
1246 { 220, 14 },
1247 { 240, 15 },
1248 { 250, 16 },
1249 { 300, 17 },
1250 { 320, 18 },
1251 { 440, 19 },
1252 { 480, 20 },
1253};
1254
1255/* Sample rates for DSP */
1256static struct {
1257 int rate;
1258 int value;
1259} sample_rates[] = {
1260 { 8000, 0 },
1261 { 11025, 1 },
1262 { 12000, 2 },
1263 { 16000, 3 },
1264 { 22050, 4 },
1265 { 24000, 5 },
1266 { 32000, 6 },
1267 { 44100, 7 },
1268 { 48000, 8 },
1269 { 88200, 9 },
1270 { 96000, 10 },
1271 { 0, 0 },
1272};
1273
dee89c4d
MB		 1274static int wm8903_startup(struct snd_pcm_substream *substream,
1275 struct snd_soc_dai *dai)
f1c0a02f
MB		 1276{
1277 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1278 struct snd_soc_device *socdev = rtd->socdev;
1279 struct snd_soc_codec *codec = socdev->codec;
1280 struct wm8903_priv *wm8903 = codec->private_data;
1281 struct i2c_client *i2c = codec->control_data;
1282 struct snd_pcm_runtime *master_runtime;
1283
1284 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1285 wm8903->playback_active++;
1286 else
1287 wm8903->capture_active++;
1288
1289 /* The DAI has shared clocks so if we already have a playback or
1290 * capture going then constrain this substream to match it.
1291 */
1292 if (wm8903->master_substream) {
1293 master_runtime = wm8903->master_substream->runtime;
1294
1295 dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
1296 master_runtime->sample_bits,
1297 master_runtime->rate);
1298
1299 snd_pcm_hw_constraint_minmax(substream->runtime,
1300 SNDRV_PCM_HW_PARAM_RATE,
1301 master_runtime->rate,
1302 master_runtime->rate);
1303
1304 snd_pcm_hw_constraint_minmax(substream->runtime,
1305 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1306 master_runtime->sample_bits,
1307 master_runtime->sample_bits);
1308
1309 wm8903->slave_substream = substream;
1310 } else
1311 wm8903->master_substream = substream;
1312
1313 return 0;
1314}
1315
dee89c4d
MB		 1316static void wm8903_shutdown(struct snd_pcm_substream *substream,
1317 struct snd_soc_dai *dai)
f1c0a02f
MB		 1318{
1319 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1320 struct snd_soc_device *socdev = rtd->socdev;
1321 struct snd_soc_codec *codec = socdev->codec;
1322 struct wm8903_priv *wm8903 = codec->private_data;
1323
1324 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1325 wm8903->playback_active--;
1326 else
1327 wm8903->capture_active--;
1328
1329 if (wm8903->master_substream == substream)
1330 wm8903->master_substream = wm8903->slave_substream;
1331
1332 wm8903->slave_substream = NULL;
1333}
1334
1335static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1336 struct snd_pcm_hw_params *params,
1337 struct snd_soc_dai *dai)
f1c0a02f
MB		 1338{
1339 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1340 struct snd_soc_device *socdev = rtd->socdev;
1341 struct snd_soc_codec *codec = socdev->codec;
1342 struct wm8903_priv *wm8903 = codec->private_data;
1343 struct i2c_client *i2c = codec->control_data;
1344 int fs = params_rate(params);
1345 int bclk;
1346 int bclk_div;
1347 int i;
1348 int dsp_config;
1349 int clk_config;
1350 int best_val;
1351 int cur_val;
1352 int clk_sys;
1353
1354 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1355 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1356 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1357 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1358 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
1359
1360 if (substream == wm8903->slave_substream) {
1361 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1362 return 0;
1363 }
1364
1365 /* Configure sample rate logic for DSP - choose nearest rate */
1366 dsp_config = 0;
1367 best_val = abs(sample_rates[dsp_config].rate - fs);
1368 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1369 cur_val = abs(sample_rates[i].rate - fs);
1370 if (cur_val <= best_val) {
1371 dsp_config = i;
1372 best_val = cur_val;
1373 }
1374 }
1375
1376 /* Constraints should stop us hitting this but let's make sure */
1377 if (wm8903->capture_active)
1378 switch (sample_rates[dsp_config].rate) {
1379 case 88200:
1380 case 96000:
1381 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1382 fs);
1383 return -EINVAL;
1384
1385 default:
1386 break;
1387 }
1388
1389 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1390 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1391 clock1 |= sample_rates[dsp_config].value;
1392
1393 aif1 &= ~WM8903_AIF_WL_MASK;
1394 bclk = 2 * fs;
1395 switch (params_format(params)) {
1396 case SNDRV_PCM_FORMAT_S16_LE:
1397 bclk *= 16;
1398 break;
1399 case SNDRV_PCM_FORMAT_S20_3LE:
1400 bclk *= 20;
1401 aif1 |= 0x4;
1402 break;
1403 case SNDRV_PCM_FORMAT_S24_LE:
1404 bclk *= 24;
1405 aif1 |= 0x8;
1406 break;
1407 case SNDRV_PCM_FORMAT_S32_LE:
1408 bclk *= 32;
1409 aif1 |= 0xc;
1410 break;
1411 default:
1412 return -EINVAL;
1413 }
1414
1415 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1416 wm8903->sysclk, fs);
1417
1418 /* We may not have an MCLK which allows us to generate exactly
1419 * the clock we want, particularly with USB derived inputs, so
1420 * approximate.
1421 */
1422 clk_config = 0;
1423 best_val = abs((wm8903->sysclk /
1424 (clk_sys_ratios[0].mclk_div *
1425 clk_sys_ratios[0].div)) - fs);
1426 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1427 cur_val = abs((wm8903->sysclk /
1428 (clk_sys_ratios[i].mclk_div *
1429 clk_sys_ratios[i].div)) - fs);
1430
1431 if (cur_val <= best_val) {
1432 clk_config = i;
1433 best_val = cur_val;
1434 }
1435 }
1436
1437 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1438 clock0 |= WM8903_MCLKDIV2;
1439 clk_sys = wm8903->sysclk / 2;
1440 } else {
1441 clock0 &= ~WM8903_MCLKDIV2;
1442 clk_sys = wm8903->sysclk;
1443 }
1444
1445 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1446 WM8903_CLK_SYS_MODE_MASK);
1447 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1448 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1449
1450 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1451 clk_sys_ratios[clk_config].rate,
1452 clk_sys_ratios[clk_config].mode,
1453 clk_sys_ratios[clk_config].div);
1454
1455 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1456
1457 /* We may not get quite the right frequency if using
1458 * approximate clocks so look for the closest match that is
1459 * higher than the target (we need to ensure that there enough
1460 * BCLKs to clock out the samples).
1461 */
1462 bclk_div = 0;
1463 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1464 i = 1;
1465 while (i < ARRAY_SIZE(bclk_divs)) {
1466 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1467 if (cur_val < 0) /* BCLK table is sorted */
1468 break;
1469 bclk_div = i;
1470 best_val = cur_val;
1471 i++;
1472 }
1473
1474 aif2 &= ~WM8903_BCLK_DIV_MASK;
1475 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1476
1477 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1478 bclk_divs[bclk_div].ratio / 10, bclk,
1479 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1480
1481 aif2 |= bclk_divs[bclk_div].div;
1482 aif3 |= bclk / fs;
1483
1484 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1485 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1486 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1487 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1488 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1489
1490 return 0;
1491}
1492
1493#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1494 SNDRV_PCM_RATE_11025 | \
1495 SNDRV_PCM_RATE_16000 | \
1496 SNDRV_PCM_RATE_22050 | \
1497 SNDRV_PCM_RATE_32000 | \
1498 SNDRV_PCM_RATE_44100 | \
1499 SNDRV_PCM_RATE_48000 | \
1500 SNDRV_PCM_RATE_88200 | \
1501 SNDRV_PCM_RATE_96000)
1502
1503#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1504 SNDRV_PCM_RATE_11025 | \
1505 SNDRV_PCM_RATE_16000 | \
1506 SNDRV_PCM_RATE_22050 | \
1507 SNDRV_PCM_RATE_32000 | \
1508 SNDRV_PCM_RATE_44100 | \
1509 SNDRV_PCM_RATE_48000)
1510
1511#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1512 SNDRV_PCM_FMTBIT_S20_3LE |\
1513 SNDRV_PCM_FMTBIT_S24_LE)
1514
1515struct snd_soc_dai wm8903_dai = {
1516 .name = "WM8903",
1517 .playback = {
1518 .stream_name = "Playback",
1519 .channels_min = 2,
1520 .channels_max = 2,
1521 .rates = WM8903_PLAYBACK_RATES,
1522 .formats = WM8903_FORMATS,
1523 },
1524 .capture = {
1525 .stream_name = "Capture",
1526 .channels_min = 2,
1527 .channels_max = 2,
1528 .rates = WM8903_CAPTURE_RATES,
1529 .formats = WM8903_FORMATS,
1530 },
1531 .ops = {
1532 .startup = wm8903_startup,
1533 .shutdown = wm8903_shutdown,
1534 .hw_params = wm8903_hw_params,
f1c0a02f
MB		 1535 .digital_mute = wm8903_digital_mute,
1536 .set_fmt = wm8903_set_dai_fmt,
1537 .set_sysclk = wm8903_set_dai_sysclk
1538 }
1539};
1540EXPORT_SYMBOL_GPL(wm8903_dai);
1541
1542static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1543{
1544 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1545 struct snd_soc_codec *codec = socdev->codec;
1546
1547 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1548
1549 return 0;
1550}
1551
1552static int wm8903_resume(struct platform_device *pdev)
1553{
1554 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1555 struct snd_soc_codec *codec = socdev->codec;
1556 struct i2c_client *i2c = codec->control_data;
1557 int i;
1558 u16 *reg_cache = codec->reg_cache;
1559 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1560 GFP_KERNEL);
1561
1562 /* Bring the codec back up to standby first to minimise pop/clicks */
1563 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1564 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1565
1566 /* Sync back everything else */
1567 if (tmp_cache) {
1568 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1569 if (tmp_cache[i] != reg_cache[i])
1570 wm8903_write(codec, i, tmp_cache[i]);
1571 } else {
1572 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1573 }
1574
1575 return 0;
1576}
1577
d58d5d55
MB		 1578static struct snd_soc_codec *wm8903_codec;
1579
1580static int wm8903_i2c_probe(struct i2c_client *i2c,
1581 const struct i2c_device_id *id)
f1c0a02f 1582{
d58d5d55
MB		 1583 struct wm8903_priv *wm8903;
1584 struct snd_soc_codec *codec;
1585 int ret;
f1c0a02f
MB		 1586 u16 val;
1587
d58d5d55
MB		 1588 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1589 if (wm8903 == NULL)
1590 return -ENOMEM;
f1c0a02f 1591
d58d5d55
MB		 1592 codec = &wm8903->codec;
1593
1594 mutex_init(&codec->mutex);
1595 INIT_LIST_HEAD(&codec->dapm_widgets);
1596 INIT_LIST_HEAD(&codec->dapm_paths);
1597
1598 codec->dev = &i2c->dev;
f1c0a02f
MB		 1599 codec->name = "WM8903";
1600 codec->owner = THIS_MODULE;
1601 codec->read = wm8903_read;
1602 codec->write = wm8903_write;
d58d5d55 1603 codec->hw_write = (hw_write_t)i2c_master_send;
f1c0a02f
MB		 1604 codec->bias_level = SND_SOC_BIAS_OFF;
1605 codec->set_bias_level = wm8903_set_bias_level;
1606 codec->dai = &wm8903_dai;
1607 codec->num_dai = 1;
d58d5d55
MB		 1608 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1609 codec->reg_cache = &wm8903->reg_cache[0];
1610 codec->private_data = wm8903;
1611
1612 i2c_set_clientdata(i2c, codec);
1613 codec->control_data = i2c;
1614
1615 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1616 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1617 dev_err(&i2c->dev,
1618 "Device with ID register %x is not a WM8903\n", val);
1619 return -ENODEV;
f1c0a02f
MB		 1620 }
1621
1622 val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1623 dev_info(&i2c->dev, "WM8903 revision %d\n",
1624 val & WM8903_CHIP_REV_MASK);
1625
1626 wm8903_reset(codec);
1627
f1c0a02f
MB		 1628 /* power on device */
1629 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1630
1631 /* Latch volume update bits */
1632 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1633 val |= WM8903_ADCVU;
1634 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1635 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1636
1637 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1638 val |= WM8903_DACVU;
1639 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1640 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1641
1642 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1643 val |= WM8903_HPOUTVU;
1644 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1645 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1646
1647 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1648 val |= WM8903_LINEOUTVU;
1649 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1650 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1651
1652 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1653 val |= WM8903_SPKVU;
1654 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1655 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1656
1657 /* Enable DAC soft mute by default */
1658 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1659 val |= WM8903_DAC_MUTEMODE;
1660 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1661
d58d5d55
MB		 1662 wm8903_dai.dev = &i2c->dev;
1663 wm8903_codec = codec;
1664
1665 ret = snd_soc_register_codec(codec);
1666 if (ret != 0) {
1667 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1668 goto err;
1669 }
1670
1671 ret = snd_soc_register_dai(&wm8903_dai);
1672 if (ret != 0) {
1673 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1674 goto err_codec;
f1c0a02f
MB		 1675 }
1676
1677 return ret;
1678
d58d5d55
MB		 1679err_codec:
1680 snd_soc_unregister_codec(codec);
1681err:
1682 wm8903_codec = NULL;
1683 kfree(wm8903);
f1c0a02f
MB		 1684 return ret;
1685}
1686
d58d5d55 1687static int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1688{
d58d5d55 1689 struct snd_soc_codec *codec = i2c_get_clientdata(client);
f1c0a02f 1690
d58d5d55
MB		 1691 snd_soc_unregister_dai(&wm8903_dai);
1692 snd_soc_unregister_codec(codec);
f1c0a02f 1693
d58d5d55 1694 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1695
d58d5d55
MB		 1696 kfree(codec->private_data);
1697
1698 wm8903_codec = NULL;
1699 wm8903_dai.dev = NULL;
f1c0a02f 1700
f1c0a02f
MB		 1701 return 0;
1702}
1703
1704/* i2c codec control layer */
1705static const struct i2c_device_id wm8903_i2c_id[] = {
1706 { "wm8903", 0 },
1707 { }
1708};
1709MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1710
1711static struct i2c_driver wm8903_i2c_driver = {
1712 .driver = {
1713 .name = "WM8903",
1714 .owner = THIS_MODULE,
1715 },
1716 .probe = wm8903_i2c_probe,
1717 .remove = wm8903_i2c_remove,
1718 .id_table = wm8903_i2c_id,
1719};
1720
f1c0a02f
MB		 1721static int wm8903_probe(struct platform_device *pdev)
1722{
1723 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1724 int ret = 0;
1725
d58d5d55
MB		 1726 if (!wm8903_codec) {
1727 dev_err(&pdev->dev, "I2C device not yet probed\n");
1728 goto err;
f1c0a02f
MB		 1729 }
1730
d58d5d55 1731 socdev->codec = wm8903_codec;
f1c0a02f 1732
d58d5d55
MB		 1733 /* register pcms */
1734 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1735 if (ret < 0) {
1736 dev_err(&pdev->dev, "failed to create pcms\n");
1737 goto err;
f1c0a02f
MB		 1738 }
1739
d58d5d55
MB		 1740 wm8903_add_controls(socdev->codec);
1741 wm8903_add_widgets(socdev->codec);
f1c0a02f 1742
d58d5d55
MB		 1743 ret = snd_soc_init_card(socdev);
1744 if (ret < 0) {
1745 dev_err(&pdev->dev, "wm8903: failed to register card\n");
1746 goto card_err;
f1c0a02f
MB		 1747 }
1748
1749 return ret;
1750
d58d5d55
MB		 1751card_err:
1752 snd_soc_free_pcms(socdev);
1753 snd_soc_dapm_free(socdev);
1754err:
f1c0a02f
MB		 1755 return ret;
1756}
1757
1758/* power down chip */
1759static int wm8903_remove(struct platform_device *pdev)
1760{
1761 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1762 struct snd_soc_codec *codec = socdev->codec;
1763
1764 if (codec->control_data)
1765 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1766
1767 snd_soc_free_pcms(socdev);
1768 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1769
1770 return 0;
1771}
1772
1773struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1774 .probe = wm8903_probe,
1775 .remove = wm8903_remove,
1776 .suspend = wm8903_suspend,
1777 .resume = wm8903_resume,
1778};
1779EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1780
c9b3a40f 1781static int __init wm8903_modinit(void)
64089b84 1782{
d58d5d55 1783 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1784}
1785module_init(wm8903_modinit);
1786
1787static void __exit wm8903_exit(void)
1788{
d58d5d55 1789 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1790}
1791module_exit(wm8903_exit);
1792
f1c0a02f
MB		 1793MODULE_DESCRIPTION("ASoC WM8903 driver");
1794MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1795MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.103252 seconds and 5 git commands to generate.