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ASoC: Add suspend and resume callbacks to Wolfson CODEC drivers
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
14 * - Mic detect.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
25#include <linux/platform_device.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33
34#include "wm8903.h"
35
f1c0a02f
MB		 36/* Register defaults at reset */
37static u16 wm8903_reg_defaults[] = {
38 0x8903, /* R0 - SW Reset and ID */
39 0x0000, /* R1 - Revision Number */
40 0x0000, /* R2 */
41 0x0000, /* R3 */
42 0x0018, /* R4 - Bias Control 0 */
43 0x0000, /* R5 - VMID Control 0 */
44 0x0000, /* R6 - Mic Bias Control 0 */
45 0x0000, /* R7 */
46 0x0001, /* R8 - Analogue DAC 0 */
47 0x0000, /* R9 */
48 0x0001, /* R10 - Analogue ADC 0 */
49 0x0000, /* R11 */
50 0x0000, /* R12 - Power Management 0 */
51 0x0000, /* R13 - Power Management 1 */
52 0x0000, /* R14 - Power Management 2 */
53 0x0000, /* R15 - Power Management 3 */
54 0x0000, /* R16 - Power Management 4 */
55 0x0000, /* R17 - Power Management 5 */
56 0x0000, /* R18 - Power Management 6 */
57 0x0000, /* R19 */
58 0x0400, /* R20 - Clock Rates 0 */
59 0x0D07, /* R21 - Clock Rates 1 */
60 0x0000, /* R22 - Clock Rates 2 */
61 0x0000, /* R23 */
62 0x0050, /* R24 - Audio Interface 0 */
63 0x0242, /* R25 - Audio Interface 1 */
64 0x0008, /* R26 - Audio Interface 2 */
65 0x0022, /* R27 - Audio Interface 3 */
66 0x0000, /* R28 */
67 0x0000, /* R29 */
68 0x00C0, /* R30 - DAC Digital Volume Left */
69 0x00C0, /* R31 - DAC Digital Volume Right */
70 0x0000, /* R32 - DAC Digital 0 */
71 0x0000, /* R33 - DAC Digital 1 */
72 0x0000, /* R34 */
73 0x0000, /* R35 */
74 0x00C0, /* R36 - ADC Digital Volume Left */
75 0x00C0, /* R37 - ADC Digital Volume Right */
76 0x0000, /* R38 - ADC Digital 0 */
77 0x0073, /* R39 - Digital Microphone 0 */
78 0x09BF, /* R40 - DRC 0 */
79 0x3241, /* R41 - DRC 1 */
80 0x0020, /* R42 - DRC 2 */
81 0x0000, /* R43 - DRC 3 */
82 0x0085, /* R44 - Analogue Left Input 0 */
83 0x0085, /* R45 - Analogue Right Input 0 */
84 0x0044, /* R46 - Analogue Left Input 1 */
85 0x0044, /* R47 - Analogue Right Input 1 */
86 0x0000, /* R48 */
87 0x0000, /* R49 */
88 0x0008, /* R50 - Analogue Left Mix 0 */
89 0x0004, /* R51 - Analogue Right Mix 0 */
90 0x0000, /* R52 - Analogue Spk Mix Left 0 */
91 0x0000, /* R53 - Analogue Spk Mix Left 1 */
92 0x0000, /* R54 - Analogue Spk Mix Right 0 */
93 0x0000, /* R55 - Analogue Spk Mix Right 1 */
94 0x0000, /* R56 */
95 0x002D, /* R57 - Analogue OUT1 Left */
96 0x002D, /* R58 - Analogue OUT1 Right */
97 0x0039, /* R59 - Analogue OUT2 Left */
98 0x0039, /* R60 - Analogue OUT2 Right */
99 0x0100, /* R61 */
100 0x0139, /* R62 - Analogue OUT3 Left */
101 0x0139, /* R63 - Analogue OUT3 Right */
102 0x0000, /* R64 */
103 0x0000, /* R65 - Analogue SPK Output Control 0 */
104 0x0000, /* R66 */
105 0x0010, /* R67 - DC Servo 0 */
106 0x0100, /* R68 */
107 0x00A4, /* R69 - DC Servo 2 */
108 0x0807, /* R70 */
109 0x0000, /* R71 */
110 0x0000, /* R72 */
111 0x0000, /* R73 */
112 0x0000, /* R74 */
113 0x0000, /* R75 */
114 0x0000, /* R76 */
115 0x0000, /* R77 */
116 0x0000, /* R78 */
117 0x000E, /* R79 */
118 0x0000, /* R80 */
119 0x0000, /* R81 */
120 0x0000, /* R82 */
121 0x0000, /* R83 */
122 0x0000, /* R84 */
123 0x0000, /* R85 */
124 0x0000, /* R86 */
125 0x0006, /* R87 */
126 0x0000, /* R88 */
127 0x0000, /* R89 */
128 0x0000, /* R90 - Analogue HP 0 */
129 0x0060, /* R91 */
130 0x0000, /* R92 */
131 0x0000, /* R93 */
132 0x0000, /* R94 - Analogue Lineout 0 */
133 0x0060, /* R95 */
134 0x0000, /* R96 */
135 0x0000, /* R97 */
136 0x0000, /* R98 - Charge Pump 0 */
137 0x1F25, /* R99 */
138 0x2B19, /* R100 */
139 0x01C0, /* R101 */
140 0x01EF, /* R102 */
141 0x2B00, /* R103 */
142 0x0000, /* R104 - Class W 0 */
143 0x01C0, /* R105 */
144 0x1C10, /* R106 */
145 0x0000, /* R107 */
146 0x0000, /* R108 - Write Sequencer 0 */
147 0x0000, /* R109 - Write Sequencer 1 */
148 0x0000, /* R110 - Write Sequencer 2 */
149 0x0000, /* R111 - Write Sequencer 3 */
150 0x0000, /* R112 - Write Sequencer 4 */
151 0x0000, /* R113 */
152 0x0000, /* R114 - Control Interface */
153 0x0000, /* R115 */
154 0x00A8, /* R116 - GPIO Control 1 */
155 0x00A8, /* R117 - GPIO Control 2 */
156 0x00A8, /* R118 - GPIO Control 3 */
157 0x0220, /* R119 - GPIO Control 4 */
158 0x01A0, /* R120 - GPIO Control 5 */
159 0x0000, /* R121 - Interrupt Status 1 */
160 0xFFFF, /* R122 - Interrupt Status 1 Mask */
161 0x0000, /* R123 - Interrupt Polarity 1 */
162 0x0000, /* R124 */
163 0x0003, /* R125 */
164 0x0000, /* R126 - Interrupt Control */
165 0x0000, /* R127 */
166 0x0005, /* R128 */
167 0x0000, /* R129 - Control Interface Test 1 */
168 0x0000, /* R130 */
169 0x0000, /* R131 */
170 0x0000, /* R132 */
171 0x0000, /* R133 */
172 0x0000, /* R134 */
173 0x03FF, /* R135 */
174 0x0007, /* R136 */
175 0x0040, /* R137 */
176 0x0000, /* R138 */
177 0x0000, /* R139 */
178 0x0000, /* R140 */
179 0x0000, /* R141 */
180 0x0000, /* R142 */
181 0x0000, /* R143 */
182 0x0000, /* R144 */
183 0x0000, /* R145 */
184 0x0000, /* R146 */
185 0x0000, /* R147 */
186 0x4000, /* R148 */
187 0x6810, /* R149 - Charge Pump Test 1 */
188 0x0004, /* R150 */
189 0x0000, /* R151 */
190 0x0000, /* R152 */
191 0x0000, /* R153 */
192 0x0000, /* R154 */
193 0x0000, /* R155 */
194 0x0000, /* R156 */
195 0x0000, /* R157 */
196 0x0000, /* R158 */
197 0x0000, /* R159 */
198 0x0000, /* R160 */
199 0x0000, /* R161 */
200 0x0000, /* R162 */
201 0x0000, /* R163 */
202 0x0028, /* R164 - Clock Rate Test 4 */
203 0x0004, /* R165 */
204 0x0000, /* R166 */
205 0x0060, /* R167 */
206 0x0000, /* R168 */
207 0x0000, /* R169 */
208 0x0000, /* R170 */
209 0x0000, /* R171 */
210 0x0000, /* R172 - Analogue Output Bias 0 */
211};
212
d58d5d55
MB		 213struct wm8903_priv {
214 struct snd_soc_codec codec;
215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
216
217 int sysclk;
218
219 /* Reference counts */
d58d5d55
MB		 220 int class_w_users;
221 int playback_active;
222 int capture_active;
223
224 struct snd_pcm_substream *master_substream;
225 struct snd_pcm_substream *slave_substream;
226};
227
228
f1c0a02f
MB		 229static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
230 unsigned int reg)
231{
232 u16 *cache = codec->reg_cache;
233
234 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
235
236 return cache[reg];
237}
238
239static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
240{
241 struct i2c_msg xfer[2];
242 u16 data;
243 int ret;
244 struct i2c_client *client = codec->control_data;
245
246 /* Write register */
247 xfer[0].addr = client->addr;
248 xfer[0].flags = 0;
249 xfer[0].len = 1;
250 xfer[0].buf = &reg;
251
252 /* Read data */
253 xfer[1].addr = client->addr;
254 xfer[1].flags = I2C_M_RD;
255 xfer[1].len = 2;
256 xfer[1].buf = (u8 *)&data;
257
258 ret = i2c_transfer(client->adapter, xfer, 2);
259 if (ret != 2) {
260 pr_err("i2c_transfer returned %d\n", ret);
261 return 0;
262 }
263
264 return (data >> 8) | ((data & 0xff) << 8);
265}
266
267static unsigned int wm8903_read(struct snd_soc_codec *codec,
268 unsigned int reg)
269{
270 switch (reg) {
271 case WM8903_SW_RESET_AND_ID:
272 case WM8903_REVISION_NUMBER:
273 case WM8903_INTERRUPT_STATUS_1:
274 case WM8903_WRITE_SEQUENCER_4:
275 return wm8903_hw_read(codec, reg);
276
277 default:
278 return wm8903_read_reg_cache(codec, reg);
279 }
280}
281
282static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
283 u16 reg, unsigned int value)
284{
285 u16 *cache = codec->reg_cache;
286
287 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
288
289 switch (reg) {
290 case WM8903_SW_RESET_AND_ID:
291 case WM8903_REVISION_NUMBER:
292 break;
293
294 default:
295 cache[reg] = value;
296 break;
297 }
298}
299
300static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
301 unsigned int value)
302{
303 u8 data[3];
304
305 wm8903_write_reg_cache(codec, reg, value);
306
307 /* Data format is 1 byte of address followed by 2 bytes of data */
308 data[0] = reg;
309 data[1] = (value >> 8) & 0xff;
310 data[2] = value & 0xff;
311
312 if (codec->hw_write(codec->control_data, data, 3) == 2)
313 return 0;
314 else
315 return -EIO;
316}
317
318static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
319{
320 u16 reg[5];
321 struct i2c_client *i2c = codec->control_data;
322
323 BUG_ON(start > 48);
324
325 /* Enable the sequencer */
326 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
327 reg[0] |= WM8903_WSEQ_ENA;
328 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
329
330 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
331
332 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
333 start | WM8903_WSEQ_START);
334
335 /* Wait for it to complete. If we have the interrupt wired up then
336 * we could block waiting for an interrupt, though polling may still
337 * be desirable for diagnostic purposes.
338 */
339 do {
340 msleep(10);
341
342 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
343 } while (reg[4] & WM8903_WSEQ_BUSY);
344
345 dev_dbg(&i2c->dev, "Sequence complete\n");
346
347 /* Disable the sequencer again */
348 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
349 reg[0] & ~WM8903_WSEQ_ENA);
350
351 return 0;
352}
353
354static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
355{
356 int i;
357
358 /* There really ought to be something better we can do here :/ */
359 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
360 cache[i] = wm8903_hw_read(codec, i);
361}
362
363static void wm8903_reset(struct snd_soc_codec *codec)
364{
365 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 366 memcpy(codec->reg_cache, wm8903_reg_defaults,
367 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 368}
369
370#define WM8903_OUTPUT_SHORT 0x8
371#define WM8903_OUTPUT_OUT 0x4
372#define WM8903_OUTPUT_INT 0x2
373#define WM8903_OUTPUT_IN 0x1
374
42768a12
MB		 375static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377{
378 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
379 mdelay(4);
380
381 return 0;
382}
383
f1c0a02f
MB		 384/*
385 * Event for headphone and line out amplifier power changes. Special
386 * power up/down sequences are required in order to maximise pop/click
387 * performance.
388 */
389static int wm8903_output_event(struct snd_soc_dapm_widget *w,
390 struct snd_kcontrol *kcontrol, int event)
391{
392 struct snd_soc_codec *codec = w->codec;
f1c0a02f 393 u16 val;
0bc286e2 394 u16 reg;
d7d5c547
MB		 395 u16 dcs_reg;
396 u16 dcs_bit;
0bc286e2 397 int shift;
f1c0a02f
MB		 398
399 switch (w->reg) {
400 case WM8903_POWER_MANAGEMENT_2:
401 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 402 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 403 break;
404 case WM8903_POWER_MANAGEMENT_3:
405 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 406 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 407 break;
408 default:
409 BUG();
1e297a19 410 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 411 }
412
413 switch (w->shift) {
414 case 0:
415 shift = 0;
416 break;
417 case 1:
418 shift = 4;
419 break;
420 default:
421 BUG();
1e297a19 422 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 423 }
424
425 if (event & SND_SOC_DAPM_PRE_PMU) {
426 val = wm8903_read(codec, reg);
427
428 /* Short the output */
429 val &= ~(WM8903_OUTPUT_SHORT << shift);
430 wm8903_write(codec, reg, val);
f1c0a02f
MB		 431 }
432
433 if (event & SND_SOC_DAPM_POST_PMU) {
434 val = wm8903_read(codec, reg);
435
436 val |= (WM8903_OUTPUT_IN << shift);
437 wm8903_write(codec, reg, val);
438
439 val |= (WM8903_OUTPUT_INT << shift);
440 wm8903_write(codec, reg, val);
441
442 /* Turn on the output ENA_OUTP */
443 val |= (WM8903_OUTPUT_OUT << shift);
444 wm8903_write(codec, reg, val);
445
d7d5c547
MB		 446 /* Enable the DC servo */
447 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0);
448 dcs_reg |= dcs_bit;
449 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg);
450
f1c0a02f
MB		 451 /* Remove the short */
452 val |= (WM8903_OUTPUT_SHORT << shift);
453 wm8903_write(codec, reg, val);
454 }
455
456 if (event & SND_SOC_DAPM_PRE_PMD) {
457 val = wm8903_read(codec, reg);
458
459 /* Short the output */
460 val &= ~(WM8903_OUTPUT_SHORT << shift);
461 wm8903_write(codec, reg, val);
462
d7d5c547
MB		 463 /* Disable the DC servo */
464 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0);
465 dcs_reg &= ~dcs_bit;
466 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg);
467
f1c0a02f
MB		 468 /* Then disable the intermediate and output stages */
469 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
470 WM8903_OUTPUT_IN) << shift);
471 wm8903_write(codec, reg, val);
472 }
473
f1c0a02f
MB		 474 return 0;
475}
476
477/*
478 * When used with DAC outputs only the WM8903 charge pump supports
479 * operation in class W mode, providing very low power consumption
480 * when used with digital sources. Enable and disable this mode
481 * automatically depending on the mixer configuration.
482 *
483 * All the relevant controls are simple switches.
484 */
485static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
489 struct snd_soc_codec *codec = widget->codec;
490 struct wm8903_priv *wm8903 = codec->private_data;
491 struct i2c_client *i2c = codec->control_data;
492 u16 reg;
493 int ret;
494
495 reg = wm8903_read(codec, WM8903_CLASS_W_0);
496
497 /* Turn it off if we're about to enable bypass */
498 if (ucontrol->value.integer.value[0]) {
499 if (wm8903->class_w_users == 0) {
500 dev_dbg(&i2c->dev, "Disabling Class W\n");
501 wm8903_write(codec, WM8903_CLASS_W_0, reg &
502 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
503 }
504 wm8903->class_w_users++;
505 }
506
507 /* Implement the change */
508 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
509
510 /* If we've just disabled the last bypass path turn Class W on */
511 if (!ucontrol->value.integer.value[0]) {
512 if (wm8903->class_w_users == 1) {
513 dev_dbg(&i2c->dev, "Enabling Class W\n");
514 wm8903_write(codec, WM8903_CLASS_W_0, reg |
515 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
516 }
517 wm8903->class_w_users--;
518 }
519
520 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
521 wm8903->class_w_users);
522
523 return ret;
524}
525
526#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
527{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
528 .info = snd_soc_info_volsw, \
529 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
530 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
531
532
533/* ALSA can only do steps of .01dB */
534static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
535
291ce18c 536static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 537static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
538
539static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
540static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
541static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
542static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
543static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
544
545static const char *drc_slope_text[] = {
546 "1", "1/2", "1/4", "1/8", "1/16", "0"
547};
548
549static const struct soc_enum drc_slope_r0 =
550 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
551
552static const struct soc_enum drc_slope_r1 =
553 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
554
555static const char *drc_attack_text[] = {
556 "instantaneous",
557 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
558 "46.4ms", "92.8ms", "185.6ms"
559};
560
561static const struct soc_enum drc_attack =
562 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
563
564static const char *drc_decay_text[] = {
565 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
566 "23.87s", "47.56s"
567};
568
569static const struct soc_enum drc_decay =
570 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
571
572static const char *drc_ff_delay_text[] = {
573 "5 samples", "9 samples"
574};
575
576static const struct soc_enum drc_ff_delay =
577 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
578
579static const char *drc_qr_decay_text[] = {
580 "0.725ms", "1.45ms", "5.8ms"
581};
582
583static const struct soc_enum drc_qr_decay =
584 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
585
586static const char *drc_smoothing_text[] = {
587 "Low", "Medium", "High"
588};
589
590static const struct soc_enum drc_smoothing =
591 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
592
593static const char *soft_mute_text[] = {
594 "Fast (fs/2)", "Slow (fs/32)"
595};
596
597static const struct soc_enum soft_mute =
598 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
599
600static const char *mute_mode_text[] = {
601 "Hard", "Soft"
602};
603
604static const struct soc_enum mute_mode =
605 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
606
607static const char *dac_deemphasis_text[] = {
608 "Disabled", "32kHz", "44.1kHz", "48kHz"
609};
610
611static const struct soc_enum dac_deemphasis =
612 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
613
614static const char *companding_text[] = {
615 "ulaw", "alaw"
616};
617
618static const struct soc_enum dac_companding =
619 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
620
621static const struct soc_enum adc_companding =
622 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
623
624static const char *input_mode_text[] = {
625 "Single-Ended", "Differential Line", "Differential Mic"
626};
627
628static const struct soc_enum linput_mode_enum =
629 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
630
631static const struct soc_enum rinput_mode_enum =
632 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
633
634static const char *linput_mux_text[] = {
635 "IN1L", "IN2L", "IN3L"
636};
637
638static const struct soc_enum linput_enum =
639 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
640
641static const struct soc_enum linput_inv_enum =
642 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
643
644static const char *rinput_mux_text[] = {
645 "IN1R", "IN2R", "IN3R"
646};
647
648static const struct soc_enum rinput_enum =
649 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
650
651static const struct soc_enum rinput_inv_enum =
652 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
653
654
291ce18c
MB		 655static const char *sidetone_text[] = {
656 "None", "Left", "Right"
657};
658
659static const struct soc_enum lsidetone_enum =
660 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
661
662static const struct soc_enum rsidetone_enum =
663 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
664
f1c0a02f
MB		 665static const struct snd_kcontrol_new wm8903_snd_controls[] = {
666
667/* Input PGAs - No TLV since the scale depends on PGA mode */
668SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 669 7, 1, 1),
f1c0a02f
MB		 670SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
671 0, 31, 0),
672SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
673 6, 1, 0),
674
675SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 676 7, 1, 1),
f1c0a02f
MB		 677SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
678 0, 31, 0),
679SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
680 6, 1, 0),
681
682/* ADCs */
683SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
684SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
685SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
686SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
687 drc_tlv_thresh),
688SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
689SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
690SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
691SOC_ENUM("DRC Attack Rate", drc_attack),
692SOC_ENUM("DRC Decay Rate", drc_decay),
693SOC_ENUM("DRC FF Delay", drc_ff_delay),
694SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
695SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
696SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
697SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
698SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
699SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
700SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
701SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
702
703SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
704 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
705SOC_ENUM("ADC Companding Mode", adc_companding),
706SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
707
291ce18c
MB		 708SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
709 12, 0, digital_sidetone_tlv),
710
f1c0a02f
MB		 711/* DAC */
712SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
713 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
714SOC_ENUM("DAC Soft Mute Rate", soft_mute),
715SOC_ENUM("DAC Mute Mode", mute_mode),
716SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
717SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 718SOC_ENUM("DAC Companding Mode", dac_companding),
719SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
720
721/* Headphones */
722SOC_DOUBLE_R("Headphone Switch",
723 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
724 8, 1, 1),
725SOC_DOUBLE_R("Headphone ZC Switch",
726 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
727 6, 1, 0),
728SOC_DOUBLE_R_TLV("Headphone Volume",
729 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
730 0, 63, 0, out_tlv),
731
732/* Line out */
733SOC_DOUBLE_R("Line Out Switch",
734 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
735 8, 1, 1),
736SOC_DOUBLE_R("Line Out ZC Switch",
737 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
738 6, 1, 0),
739SOC_DOUBLE_R_TLV("Line Out Volume",
740 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
741 0, 63, 0, out_tlv),
742
743/* Speaker */
744SOC_DOUBLE_R("Speaker Switch",
745 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
746SOC_DOUBLE_R("Speaker ZC Switch",
747 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
748SOC_DOUBLE_R_TLV("Speaker Volume",
749 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
750 0, 63, 0, out_tlv),
751};
752
f1c0a02f
MB		 753static const struct snd_kcontrol_new linput_mode_mux =
754 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
755
756static const struct snd_kcontrol_new rinput_mode_mux =
757 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
758
759static const struct snd_kcontrol_new linput_mux =
760 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
761
762static const struct snd_kcontrol_new linput_inv_mux =
763 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
764
765static const struct snd_kcontrol_new rinput_mux =
766 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
767
768static const struct snd_kcontrol_new rinput_inv_mux =
769 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
770
291ce18c
MB		 771static const struct snd_kcontrol_new lsidetone_mux =
772 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
773
774static const struct snd_kcontrol_new rsidetone_mux =
775 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
776
f1c0a02f
MB		 777static const struct snd_kcontrol_new left_output_mixer[] = {
778SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
779SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
780SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 781SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 782};
783
784static const struct snd_kcontrol_new right_output_mixer[] = {
785SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
786SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
787SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 788SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 789};
790
791static const struct snd_kcontrol_new left_speaker_mixer[] = {
792SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
793SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
794SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
795SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 796 0, 1, 0),
f1c0a02f
MB		 797};
798
799static const struct snd_kcontrol_new right_speaker_mixer[] = {
800SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
801SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
802SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
803 1, 1, 0),
804SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 805 0, 1, 0),
f1c0a02f
MB		 806};
807
808static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
809SND_SOC_DAPM_INPUT("IN1L"),
810SND_SOC_DAPM_INPUT("IN1R"),
811SND_SOC_DAPM_INPUT("IN2L"),
812SND_SOC_DAPM_INPUT("IN2R"),
813SND_SOC_DAPM_INPUT("IN3L"),
814SND_SOC_DAPM_INPUT("IN3R"),
815
816SND_SOC_DAPM_OUTPUT("HPOUTL"),
817SND_SOC_DAPM_OUTPUT("HPOUTR"),
818SND_SOC_DAPM_OUTPUT("LINEOUTL"),
819SND_SOC_DAPM_OUTPUT("LINEOUTR"),
820SND_SOC_DAPM_OUTPUT("LOP"),
821SND_SOC_DAPM_OUTPUT("LON"),
822SND_SOC_DAPM_OUTPUT("ROP"),
823SND_SOC_DAPM_OUTPUT("RON"),
824
825SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
826
827SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
828SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
829 &linput_inv_mux),
830SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
831
832SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
833SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
834 &rinput_inv_mux),
835SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
836
837SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
838SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
839
840SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
841SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
842
291ce18c
MB		 843SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
844SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
845
f1c0a02f
MB		 846SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
847SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
848
849SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
850 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
851SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
852 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
853
854SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
855 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
856SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
857 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
858
859SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
860 1, 0, NULL, 0, wm8903_output_event,
861 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 862 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 863SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
864 0, 0, NULL, 0, wm8903_output_event,
865 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 866 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 867
868SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
869 NULL, 0, wm8903_output_event,
870 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 871 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 872SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
873 NULL, 0, wm8903_output_event,
874 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 875 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 876
877SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
878 NULL, 0),
879SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
880 NULL, 0),
881
42768a12
MB		 882SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
883 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 884SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 885};
886
887static const struct snd_soc_dapm_route intercon[] = {
888
889 { "Left Input Mux", "IN1L", "IN1L" },
890 { "Left Input Mux", "IN2L", "IN2L" },
891 { "Left Input Mux", "IN3L", "IN3L" },
892
893 { "Left Input Inverting Mux", "IN1L", "IN1L" },
894 { "Left Input Inverting Mux", "IN2L", "IN2L" },
895 { "Left Input Inverting Mux", "IN3L", "IN3L" },
896
897 { "Right Input Mux", "IN1R", "IN1R" },
898 { "Right Input Mux", "IN2R", "IN2R" },
899 { "Right Input Mux", "IN3R", "IN3R" },
900
901 { "Right Input Inverting Mux", "IN1R", "IN1R" },
902 { "Right Input Inverting Mux", "IN2R", "IN2R" },
903 { "Right Input Inverting Mux", "IN3R", "IN3R" },
904
905 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
906 { "Left Input Mode Mux", "Differential Line",
907 "Left Input Mux" },
908 { "Left Input Mode Mux", "Differential Line",
909 "Left Input Inverting Mux" },
910 { "Left Input Mode Mux", "Differential Mic",
911 "Left Input Mux" },
912 { "Left Input Mode Mux", "Differential Mic",
913 "Left Input Inverting Mux" },
914
915 { "Right Input Mode Mux", "Single-Ended",
916 "Right Input Inverting Mux" },
917 { "Right Input Mode Mux", "Differential Line",
918 "Right Input Mux" },
919 { "Right Input Mode Mux", "Differential Line",
920 "Right Input Inverting Mux" },
921 { "Right Input Mode Mux", "Differential Mic",
922 "Right Input Mux" },
923 { "Right Input Mode Mux", "Differential Mic",
924 "Right Input Inverting Mux" },
925
926 { "Left Input PGA", NULL, "Left Input Mode Mux" },
927 { "Right Input PGA", NULL, "Right Input Mode Mux" },
928
929 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 930 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 931 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 932 { "ADCR", NULL, "CLK_DSP" },
933
291ce18c
MB		 934 { "DACL Sidetone", "Left", "ADCL" },
935 { "DACL Sidetone", "Right", "ADCR" },
936 { "DACR Sidetone", "Left", "ADCL" },
937 { "DACR Sidetone", "Right", "ADCR" },
938
939 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 940 { "DACL", NULL, "CLK_DSP" },
291ce18c 941 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 942 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 943
944 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
945 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
946 { "Left Output Mixer", "DACL Switch", "DACL" },
947 { "Left Output Mixer", "DACR Switch", "DACR" },
948
949 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
950 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
951 { "Right Output Mixer", "DACL Switch", "DACL" },
952 { "Right Output Mixer", "DACR Switch", "DACR" },
953
954 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
955 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
956 { "Left Speaker Mixer", "DACL Switch", "DACL" },
957 { "Left Speaker Mixer", "DACR Switch", "DACR" },
958
959 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
960 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
961 { "Right Speaker Mixer", "DACL Switch", "DACL" },
962 { "Right Speaker Mixer", "DACR Switch", "DACR" },
963
964 { "Left Line Output PGA", NULL, "Left Output Mixer" },
965 { "Right Line Output PGA", NULL, "Right Output Mixer" },
966
967 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
968 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
969
970 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
971 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
972
973 { "HPOUTL", NULL, "Left Headphone Output PGA" },
974 { "HPOUTR", NULL, "Right Headphone Output PGA" },
975
976 { "LINEOUTL", NULL, "Left Line Output PGA" },
977 { "LINEOUTR", NULL, "Right Line Output PGA" },
978
979 { "LOP", NULL, "Left Speaker PGA" },
980 { "LON", NULL, "Left Speaker PGA" },
981
982 { "ROP", NULL, "Right Speaker PGA" },
983 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 984
985 { "Left Headphone Output PGA", NULL, "Charge Pump" },
986 { "Right Headphone Output PGA", NULL, "Charge Pump" },
987 { "Left Line Output PGA", NULL, "Charge Pump" },
988 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 989};
990
991static int wm8903_add_widgets(struct snd_soc_codec *codec)
992{
993 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
994 ARRAY_SIZE(wm8903_dapm_widgets));
995
996 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
997
998 snd_soc_dapm_new_widgets(codec);
999
1000 return 0;
1001}
1002
1003static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1004 enum snd_soc_bias_level level)
1005{
1006 struct i2c_client *i2c = codec->control_data;
1007 u16 reg, reg2;
1008
1009 switch (level) {
1010 case SND_SOC_BIAS_ON:
1011 case SND_SOC_BIAS_PREPARE:
1012 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1013 reg &= ~(WM8903_VMID_RES_MASK);
1014 reg |= WM8903_VMID_RES_50K;
1015 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1016 break;
1017
1018 case SND_SOC_BIAS_STANDBY:
1019 if (codec->bias_level == SND_SOC_BIAS_OFF) {
3b1228ab
MB		 1020 wm8903_write(codec, WM8903_CLOCK_RATES_2,
1021 WM8903_CLK_SYS_ENA);
1022
4dbfe809
MB		 1023 /* Change DC servo dither level in startup sequence */
1024 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1025 wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1026 wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
1027
f1c0a02f
MB		 1028 wm8903_run_sequence(codec, 0);
1029 wm8903_sync_reg_cache(codec, codec->reg_cache);
1030
1031 /* Enable low impedence charge pump output */
1032 reg = wm8903_read(codec,
1033 WM8903_CONTROL_INTERFACE_TEST_1);
1034 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1035 reg | WM8903_TEST_KEY);
1036 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1037 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1038 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1039 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1040 reg);
1041
1042 /* By default no bypass paths are enabled so
1043 * enable Class W support.
1044 */
1045 dev_dbg(&i2c->dev, "Enabling Class W\n");
1046 wm8903_write(codec, WM8903_CLASS_W_0, reg |
1047 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1048 }
1049
1050 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1051 reg &= ~(WM8903_VMID_RES_MASK);
1052 reg |= WM8903_VMID_RES_250K;
1053 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1054 break;
1055
1056 case SND_SOC_BIAS_OFF:
1057 wm8903_run_sequence(codec, 32);
3b1228ab
MB		 1058 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2);
1059 reg &= ~WM8903_CLK_SYS_ENA;
1060 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1061 break;
1062 }
1063
1064 codec->bias_level = level;
1065
1066 return 0;
1067}
1068
1069static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1070 int clk_id, unsigned int freq, int dir)
1071{
1072 struct snd_soc_codec *codec = codec_dai->codec;
1073 struct wm8903_priv *wm8903 = codec->private_data;
1074
1075 wm8903->sysclk = freq;
1076
1077 return 0;
1078}
1079
1080static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1081 unsigned int fmt)
1082{
1083 struct snd_soc_codec *codec = codec_dai->codec;
1084 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1085
1086 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1087 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1088
1089 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1090 case SND_SOC_DAIFMT_CBS_CFS:
1091 break;
1092 case SND_SOC_DAIFMT_CBS_CFM:
1093 aif1 |= WM8903_LRCLK_DIR;
1094 break;
1095 case SND_SOC_DAIFMT_CBM_CFM:
1096 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1097 break;
1098 case SND_SOC_DAIFMT_CBM_CFS:
1099 aif1 |= WM8903_BCLK_DIR;
1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104
1105 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1106 case SND_SOC_DAIFMT_DSP_A:
1107 aif1 |= 0x3;
1108 break;
1109 case SND_SOC_DAIFMT_DSP_B:
1110 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1111 break;
1112 case SND_SOC_DAIFMT_I2S:
1113 aif1 |= 0x2;
1114 break;
1115 case SND_SOC_DAIFMT_RIGHT_J:
1116 aif1 |= 0x1;
1117 break;
1118 case SND_SOC_DAIFMT_LEFT_J:
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123
1124 /* Clock inversion */
1125 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1126 case SND_SOC_DAIFMT_DSP_A:
1127 case SND_SOC_DAIFMT_DSP_B:
1128 /* frame inversion not valid for DSP modes */
1129 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1130 case SND_SOC_DAIFMT_NB_NF:
1131 break;
1132 case SND_SOC_DAIFMT_IB_NF:
1133 aif1 |= WM8903_AIF_BCLK_INV;
1134 break;
1135 default:
1136 return -EINVAL;
1137 }
1138 break;
1139 case SND_SOC_DAIFMT_I2S:
1140 case SND_SOC_DAIFMT_RIGHT_J:
1141 case SND_SOC_DAIFMT_LEFT_J:
1142 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1143 case SND_SOC_DAIFMT_NB_NF:
1144 break;
1145 case SND_SOC_DAIFMT_IB_IF:
1146 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1147 break;
1148 case SND_SOC_DAIFMT_IB_NF:
1149 aif1 |= WM8903_AIF_BCLK_INV;
1150 break;
1151 case SND_SOC_DAIFMT_NB_IF:
1152 aif1 |= WM8903_AIF_LRCLK_INV;
1153 break;
1154 default:
1155 return -EINVAL;
1156 }
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
1162 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1163
1164 return 0;
1165}
1166
1167static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1168{
1169 struct snd_soc_codec *codec = codec_dai->codec;
1170 u16 reg;
1171
1172 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1173
1174 if (mute)
1175 reg |= WM8903_DAC_MUTE;
1176 else
1177 reg &= ~WM8903_DAC_MUTE;
1178
1179 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1180
1181 return 0;
1182}
1183
1184/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1185 * for optimal performance so we list the lower rates first and match
1186 * on the last match we find. */
1187static struct {
1188 int div;
1189 int rate;
1190 int mode;
1191 int mclk_div;
1192} clk_sys_ratios[] = {
1193 { 64, 0x0, 0x0, 1 },
1194 { 68, 0x0, 0x1, 1 },
1195 { 125, 0x0, 0x2, 1 },
1196 { 128, 0x1, 0x0, 1 },
1197 { 136, 0x1, 0x1, 1 },
1198 { 192, 0x2, 0x0, 1 },
1199 { 204, 0x2, 0x1, 1 },
1200
1201 { 64, 0x0, 0x0, 2 },
1202 { 68, 0x0, 0x1, 2 },
1203 { 125, 0x0, 0x2, 2 },
1204 { 128, 0x1, 0x0, 2 },
1205 { 136, 0x1, 0x1, 2 },
1206 { 192, 0x2, 0x0, 2 },
1207 { 204, 0x2, 0x1, 2 },
1208
1209 { 250, 0x2, 0x2, 1 },
1210 { 256, 0x3, 0x0, 1 },
1211 { 272, 0x3, 0x1, 1 },
1212 { 384, 0x4, 0x0, 1 },
1213 { 408, 0x4, 0x1, 1 },
1214 { 375, 0x4, 0x2, 1 },
1215 { 512, 0x5, 0x0, 1 },
1216 { 544, 0x5, 0x1, 1 },
1217 { 500, 0x5, 0x2, 1 },
1218 { 768, 0x6, 0x0, 1 },
1219 { 816, 0x6, 0x1, 1 },
1220 { 750, 0x6, 0x2, 1 },
1221 { 1024, 0x7, 0x0, 1 },
1222 { 1088, 0x7, 0x1, 1 },
1223 { 1000, 0x7, 0x2, 1 },
1224 { 1408, 0x8, 0x0, 1 },
1225 { 1496, 0x8, 0x1, 1 },
1226 { 1536, 0x9, 0x0, 1 },
1227 { 1632, 0x9, 0x1, 1 },
1228 { 1500, 0x9, 0x2, 1 },
1229
1230 { 250, 0x2, 0x2, 2 },
1231 { 256, 0x3, 0x0, 2 },
1232 { 272, 0x3, 0x1, 2 },
1233 { 384, 0x4, 0x0, 2 },
1234 { 408, 0x4, 0x1, 2 },
1235 { 375, 0x4, 0x2, 2 },
1236 { 512, 0x5, 0x0, 2 },
1237 { 544, 0x5, 0x1, 2 },
1238 { 500, 0x5, 0x2, 2 },
1239 { 768, 0x6, 0x0, 2 },
1240 { 816, 0x6, 0x1, 2 },
1241 { 750, 0x6, 0x2, 2 },
1242 { 1024, 0x7, 0x0, 2 },
1243 { 1088, 0x7, 0x1, 2 },
1244 { 1000, 0x7, 0x2, 2 },
1245 { 1408, 0x8, 0x0, 2 },
1246 { 1496, 0x8, 0x1, 2 },
1247 { 1536, 0x9, 0x0, 2 },
1248 { 1632, 0x9, 0x1, 2 },
1249 { 1500, 0x9, 0x2, 2 },
1250};
1251
1252/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1253static struct {
1254 int ratio;
1255 int div;
1256} bclk_divs[] = {
1257 { 10, 0 },
1258 { 15, 1 },
1259 { 20, 2 },
1260 { 30, 3 },
1261 { 40, 4 },
1262 { 50, 5 },
1263 { 55, 6 },
1264 { 60, 7 },
1265 { 80, 8 },
1266 { 100, 9 },
1267 { 110, 10 },
1268 { 120, 11 },
1269 { 160, 12 },
1270 { 200, 13 },
1271 { 220, 14 },
1272 { 240, 15 },
1273 { 250, 16 },
1274 { 300, 17 },
1275 { 320, 18 },
1276 { 440, 19 },
1277 { 480, 20 },
1278};
1279
1280/* Sample rates for DSP */
1281static struct {
1282 int rate;
1283 int value;
1284} sample_rates[] = {
1285 { 8000, 0 },
1286 { 11025, 1 },
1287 { 12000, 2 },
1288 { 16000, 3 },
1289 { 22050, 4 },
1290 { 24000, 5 },
1291 { 32000, 6 },
1292 { 44100, 7 },
1293 { 48000, 8 },
1294 { 88200, 9 },
1295 { 96000, 10 },
1296 { 0, 0 },
1297};
1298
dee89c4d
MB		 1299static int wm8903_startup(struct snd_pcm_substream *substream,
1300 struct snd_soc_dai *dai)
f1c0a02f
MB		 1301{
1302 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1303 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1304 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1305 struct wm8903_priv *wm8903 = codec->private_data;
1306 struct i2c_client *i2c = codec->control_data;
1307 struct snd_pcm_runtime *master_runtime;
1308
1309 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1310 wm8903->playback_active++;
1311 else
1312 wm8903->capture_active++;
1313
1314 /* The DAI has shared clocks so if we already have a playback or
1315 * capture going then constrain this substream to match it.
1316 */
1317 if (wm8903->master_substream) {
1318 master_runtime = wm8903->master_substream->runtime;
1319
727fb909
MB		 1320 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1321 master_runtime->sample_bits);
f1c0a02f
MB		 1322
1323 snd_pcm_hw_constraint_minmax(substream->runtime,
1324 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1325 master_runtime->sample_bits,
1326 master_runtime->sample_bits);
1327
1328 wm8903->slave_substream = substream;
1329 } else
1330 wm8903->master_substream = substream;
1331
1332 return 0;
1333}
1334
dee89c4d
MB		 1335static void wm8903_shutdown(struct snd_pcm_substream *substream,
1336 struct snd_soc_dai *dai)
f1c0a02f
MB		 1337{
1338 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1339 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1340 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1341 struct wm8903_priv *wm8903 = codec->private_data;
1342
1343 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1344 wm8903->playback_active--;
1345 else
1346 wm8903->capture_active--;
1347
1348 if (wm8903->master_substream == substream)
1349 wm8903->master_substream = wm8903->slave_substream;
1350
1351 wm8903->slave_substream = NULL;
1352}
1353
1354static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1355 struct snd_pcm_hw_params *params,
1356 struct snd_soc_dai *dai)
f1c0a02f
MB		 1357{
1358 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1359 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1360 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1361 struct wm8903_priv *wm8903 = codec->private_data;
1362 struct i2c_client *i2c = codec->control_data;
1363 int fs = params_rate(params);
1364 int bclk;
1365 int bclk_div;
1366 int i;
1367 int dsp_config;
1368 int clk_config;
1369 int best_val;
1370 int cur_val;
1371 int clk_sys;
1372
1373 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1374 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1375 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1376 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1377 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
9e79261f 1378 u16 dac_digital1 = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1379
1380 if (substream == wm8903->slave_substream) {
1381 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1382 return 0;
1383 }
1384
9e79261f
MB		 1385 /* Enable sloping stopband filter for low sample rates */
1386 if (fs <= 24000)
1387 dac_digital1 |= WM8903_DAC_SB_FILT;
1388 else
1389 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1390
f1c0a02f
MB		 1391 /* Configure sample rate logic for DSP - choose nearest rate */
1392 dsp_config = 0;
1393 best_val = abs(sample_rates[dsp_config].rate - fs);
1394 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1395 cur_val = abs(sample_rates[i].rate - fs);
1396 if (cur_val <= best_val) {
1397 dsp_config = i;
1398 best_val = cur_val;
1399 }
1400 }
1401
1402 /* Constraints should stop us hitting this but let's make sure */
1403 if (wm8903->capture_active)
1404 switch (sample_rates[dsp_config].rate) {
1405 case 88200:
1406 case 96000:
1407 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1408 fs);
1409 return -EINVAL;
1410
1411 default:
1412 break;
1413 }
1414
1415 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1416 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1417 clock1 |= sample_rates[dsp_config].value;
1418
1419 aif1 &= ~WM8903_AIF_WL_MASK;
1420 bclk = 2 * fs;
1421 switch (params_format(params)) {
1422 case SNDRV_PCM_FORMAT_S16_LE:
1423 bclk *= 16;
1424 break;
1425 case SNDRV_PCM_FORMAT_S20_3LE:
1426 bclk *= 20;
1427 aif1 |= 0x4;
1428 break;
1429 case SNDRV_PCM_FORMAT_S24_LE:
1430 bclk *= 24;
1431 aif1 |= 0x8;
1432 break;
1433 case SNDRV_PCM_FORMAT_S32_LE:
1434 bclk *= 32;
1435 aif1 |= 0xc;
1436 break;
1437 default:
1438 return -EINVAL;
1439 }
1440
1441 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1442 wm8903->sysclk, fs);
1443
1444 /* We may not have an MCLK which allows us to generate exactly
1445 * the clock we want, particularly with USB derived inputs, so
1446 * approximate.
1447 */
1448 clk_config = 0;
1449 best_val = abs((wm8903->sysclk /
1450 (clk_sys_ratios[0].mclk_div *
1451 clk_sys_ratios[0].div)) - fs);
1452 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1453 cur_val = abs((wm8903->sysclk /
1454 (clk_sys_ratios[i].mclk_div *
1455 clk_sys_ratios[i].div)) - fs);
1456
1457 if (cur_val <= best_val) {
1458 clk_config = i;
1459 best_val = cur_val;
1460 }
1461 }
1462
1463 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1464 clock0 |= WM8903_MCLKDIV2;
1465 clk_sys = wm8903->sysclk / 2;
1466 } else {
1467 clock0 &= ~WM8903_MCLKDIV2;
1468 clk_sys = wm8903->sysclk;
1469 }
1470
1471 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1472 WM8903_CLK_SYS_MODE_MASK);
1473 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1474 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1475
1476 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1477 clk_sys_ratios[clk_config].rate,
1478 clk_sys_ratios[clk_config].mode,
1479 clk_sys_ratios[clk_config].div);
1480
1481 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1482
1483 /* We may not get quite the right frequency if using
1484 * approximate clocks so look for the closest match that is
1485 * higher than the target (we need to ensure that there enough
1486 * BCLKs to clock out the samples).
1487 */
1488 bclk_div = 0;
1489 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1490 i = 1;
1491 while (i < ARRAY_SIZE(bclk_divs)) {
1492 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1493 if (cur_val < 0) /* BCLK table is sorted */
1494 break;
1495 bclk_div = i;
1496 best_val = cur_val;
1497 i++;
1498 }
1499
1500 aif2 &= ~WM8903_BCLK_DIV_MASK;
1501 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1502
1503 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1504 bclk_divs[bclk_div].ratio / 10, bclk,
1505 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1506
1507 aif2 |= bclk_divs[bclk_div].div;
1508 aif3 |= bclk / fs;
1509
1510 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1511 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1512 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1513 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1514 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
9e79261f 1515 wm8903_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1516
1517 return 0;
1518}
1519
1520#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1521 SNDRV_PCM_RATE_11025 | \
1522 SNDRV_PCM_RATE_16000 | \
1523 SNDRV_PCM_RATE_22050 | \
1524 SNDRV_PCM_RATE_32000 | \
1525 SNDRV_PCM_RATE_44100 | \
1526 SNDRV_PCM_RATE_48000 | \
1527 SNDRV_PCM_RATE_88200 | \
1528 SNDRV_PCM_RATE_96000)
1529
1530#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1531 SNDRV_PCM_RATE_11025 | \
1532 SNDRV_PCM_RATE_16000 | \
1533 SNDRV_PCM_RATE_22050 | \
1534 SNDRV_PCM_RATE_32000 | \
1535 SNDRV_PCM_RATE_44100 | \
1536 SNDRV_PCM_RATE_48000)
1537
1538#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1539 SNDRV_PCM_FMTBIT_S20_3LE |\
1540 SNDRV_PCM_FMTBIT_S24_LE)
1541
6335d055
EM		 1542static struct snd_soc_dai_ops wm8903_dai_ops = {
1543 .startup = wm8903_startup,
1544 .shutdown = wm8903_shutdown,
1545 .hw_params = wm8903_hw_params,
1546 .digital_mute = wm8903_digital_mute,
1547 .set_fmt = wm8903_set_dai_fmt,
1548 .set_sysclk = wm8903_set_dai_sysclk,
1549};
1550
f1c0a02f
MB		 1551struct snd_soc_dai wm8903_dai = {
1552 .name = "WM8903",
1553 .playback = {
1554 .stream_name = "Playback",
1555 .channels_min = 2,
1556 .channels_max = 2,
1557 .rates = WM8903_PLAYBACK_RATES,
1558 .formats = WM8903_FORMATS,
1559 },
1560 .capture = {
1561 .stream_name = "Capture",
1562 .channels_min = 2,
1563 .channels_max = 2,
1564 .rates = WM8903_CAPTURE_RATES,
1565 .formats = WM8903_FORMATS,
1566 },
6335d055 1567 .ops = &wm8903_dai_ops,
0d960e88 1568 .symmetric_rates = 1,
f1c0a02f
MB		 1569};
1570EXPORT_SYMBOL_GPL(wm8903_dai);
1571
1572static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1573{
1574 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1575 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1576
1577 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1578
1579 return 0;
1580}
1581
1582static int wm8903_resume(struct platform_device *pdev)
1583{
1584 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1585 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1586 struct i2c_client *i2c = codec->control_data;
1587 int i;
1588 u16 *reg_cache = codec->reg_cache;
1589 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1590 GFP_KERNEL);
1591
1592 /* Bring the codec back up to standby first to minimise pop/clicks */
1593 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1594 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1595
1596 /* Sync back everything else */
1597 if (tmp_cache) {
1598 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1599 if (tmp_cache[i] != reg_cache[i])
1600 wm8903_write(codec, i, tmp_cache[i]);
1601 } else {
1602 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1603 }
1604
1605 return 0;
1606}
1607
d58d5d55
MB		 1608static struct snd_soc_codec *wm8903_codec;
1609
c6f29811
MB		 1610static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1611 const struct i2c_device_id *id)
f1c0a02f 1612{
d58d5d55
MB		 1613 struct wm8903_priv *wm8903;
1614 struct snd_soc_codec *codec;
1615 int ret;
f1c0a02f
MB		 1616 u16 val;
1617
d58d5d55
MB		 1618 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1619 if (wm8903 == NULL)
1620 return -ENOMEM;
f1c0a02f 1621
d58d5d55
MB		 1622 codec = &wm8903->codec;
1623
1624 mutex_init(&codec->mutex);
1625 INIT_LIST_HEAD(&codec->dapm_widgets);
1626 INIT_LIST_HEAD(&codec->dapm_paths);
1627
1628 codec->dev = &i2c->dev;
f1c0a02f
MB		 1629 codec->name = "WM8903";
1630 codec->owner = THIS_MODULE;
1631 codec->read = wm8903_read;
1632 codec->write = wm8903_write;
d58d5d55 1633 codec->hw_write = (hw_write_t)i2c_master_send;
f1c0a02f
MB		 1634 codec->bias_level = SND_SOC_BIAS_OFF;
1635 codec->set_bias_level = wm8903_set_bias_level;
1636 codec->dai = &wm8903_dai;
1637 codec->num_dai = 1;
d58d5d55
MB		 1638 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1639 codec->reg_cache = &wm8903->reg_cache[0];
1640 codec->private_data = wm8903;
1641
1642 i2c_set_clientdata(i2c, codec);
1643 codec->control_data = i2c;
1644
1645 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1646 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1647 dev_err(&i2c->dev,
1648 "Device with ID register %x is not a WM8903\n", val);
1649 return -ENODEV;
f1c0a02f
MB		 1650 }
1651
1652 val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1653 dev_info(&i2c->dev, "WM8903 revision %d\n",
1654 val & WM8903_CHIP_REV_MASK);
1655
1656 wm8903_reset(codec);
1657
f1c0a02f
MB		 1658 /* power on device */
1659 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1660
1661 /* Latch volume update bits */
1662 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1663 val |= WM8903_ADCVU;
1664 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1665 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1666
1667 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1668 val |= WM8903_DACVU;
1669 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1670 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1671
1672 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1673 val |= WM8903_HPOUTVU;
1674 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1675 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1676
1677 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1678 val |= WM8903_LINEOUTVU;
1679 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1680 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1681
1682 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1683 val |= WM8903_SPKVU;
1684 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1685 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1686
1687 /* Enable DAC soft mute by default */
1688 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1689 val |= WM8903_DAC_MUTEMODE;
1690 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1691
d58d5d55
MB		 1692 wm8903_dai.dev = &i2c->dev;
1693 wm8903_codec = codec;
1694
1695 ret = snd_soc_register_codec(codec);
1696 if (ret != 0) {
1697 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1698 goto err;
1699 }
1700
1701 ret = snd_soc_register_dai(&wm8903_dai);
1702 if (ret != 0) {
1703 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1704 goto err_codec;
f1c0a02f
MB		 1705 }
1706
1707 return ret;
1708
d58d5d55
MB		 1709err_codec:
1710 snd_soc_unregister_codec(codec);
1711err:
1712 wm8903_codec = NULL;
1713 kfree(wm8903);
f1c0a02f
MB		 1714 return ret;
1715}
1716
c6f29811 1717static __devexit int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1718{
d58d5d55 1719 struct snd_soc_codec *codec = i2c_get_clientdata(client);
f1c0a02f 1720
d58d5d55
MB		 1721 snd_soc_unregister_dai(&wm8903_dai);
1722 snd_soc_unregister_codec(codec);
f1c0a02f 1723
d58d5d55 1724 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1725
d58d5d55
MB		 1726 kfree(codec->private_data);
1727
1728 wm8903_codec = NULL;
1729 wm8903_dai.dev = NULL;
f1c0a02f 1730
f1c0a02f
MB		 1731 return 0;
1732}
1733
b3b50b3f
MB		 1734#ifdef CONFIG_PM
1735static int wm8903_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1736{
1737 return snd_soc_suspend_device(&client->dev);
1738}
1739
1740static int wm8903_i2c_resume(struct i2c_client *client)
1741{
1742 return snd_soc_resume_device(&client->dev);
1743}
1744#else
1745#define wm8903_i2c_suspend NULL
1746#define wm8903_i2c_resume NULL
1747#endif
1748
f1c0a02f
MB		 1749/* i2c codec control layer */
1750static const struct i2c_device_id wm8903_i2c_id[] = {
1751 { "wm8903", 0 },
1752 { }
1753};
1754MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1755
1756static struct i2c_driver wm8903_i2c_driver = {
1757 .driver = {
1758 .name = "WM8903",
1759 .owner = THIS_MODULE,
1760 },
1761 .probe = wm8903_i2c_probe,
c6f29811 1762 .remove = __devexit_p(wm8903_i2c_remove),
b3b50b3f
MB		 1763 .suspend = wm8903_i2c_suspend,
1764 .resume = wm8903_i2c_resume,
f1c0a02f
MB		 1765 .id_table = wm8903_i2c_id,
1766};
1767
f1c0a02f
MB		 1768static int wm8903_probe(struct platform_device *pdev)
1769{
1770 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1771 int ret = 0;
1772
d58d5d55
MB		 1773 if (!wm8903_codec) {
1774 dev_err(&pdev->dev, "I2C device not yet probed\n");
1775 goto err;
f1c0a02f
MB		 1776 }
1777
6627a653 1778 socdev->card->codec = wm8903_codec;
f1c0a02f 1779
d58d5d55
MB		 1780 /* register pcms */
1781 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1782 if (ret < 0) {
1783 dev_err(&pdev->dev, "failed to create pcms\n");
1784 goto err;
f1c0a02f
MB		 1785 }
1786
6627a653 1787 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
3e8e1952 1788 ARRAY_SIZE(wm8903_snd_controls));
6627a653 1789 wm8903_add_widgets(socdev->card->codec);
f1c0a02f 1790
d58d5d55
MB		 1791 ret = snd_soc_init_card(socdev);
1792 if (ret < 0) {
1793 dev_err(&pdev->dev, "wm8903: failed to register card\n");
1794 goto card_err;
f1c0a02f
MB		 1795 }
1796
1797 return ret;
1798
d58d5d55
MB		 1799card_err:
1800 snd_soc_free_pcms(socdev);
1801 snd_soc_dapm_free(socdev);
1802err:
f1c0a02f
MB		 1803 return ret;
1804}
1805
1806/* power down chip */
1807static int wm8903_remove(struct platform_device *pdev)
1808{
1809 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1810 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1811
1812 if (codec->control_data)
1813 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1814
1815 snd_soc_free_pcms(socdev);
1816 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1817
1818 return 0;
1819}
1820
1821struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1822 .probe = wm8903_probe,
1823 .remove = wm8903_remove,
1824 .suspend = wm8903_suspend,
1825 .resume = wm8903_resume,
1826};
1827EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1828
c9b3a40f 1829static int __init wm8903_modinit(void)
64089b84 1830{
d58d5d55 1831 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1832}
1833module_init(wm8903_modinit);
1834
1835static void __exit wm8903_exit(void)
1836{
d58d5d55 1837 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1838}
1839module_exit(wm8903_exit);
1840
f1c0a02f
MB		 1841MODULE_DESCRIPTION("ASoC WM8903 driver");
1842MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1843MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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