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ASoC: Add EQ and filter to max98095 CODEC driver
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
c5b6a9fe
MB		 226 int dcs_pending;
227 int dcs_cache[4];
228
f2c1fe09 229 /* Reference count */
d58d5d55 230 int class_w_users;
d58d5d55 231
7245387e
MB		 232 struct snd_soc_jack *mic_jack;
233 int mic_det;
234 int mic_short;
235 int mic_last_report;
236 int mic_delay;
7cfe5617
SW		 237
238#ifdef CONFIG_GPIOLIB
239 struct gpio_chip gpio_chip;
240#endif
d58d5d55
MB		 241};
242
d4754ec9 243static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 244{
245 switch (reg) {
246 case WM8903_SW_RESET_AND_ID:
247 case WM8903_REVISION_NUMBER:
248 case WM8903_INTERRUPT_STATUS_1:
249 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 250 case WM8903_DC_SERVO_READBACK_1:
251 case WM8903_DC_SERVO_READBACK_2:
252 case WM8903_DC_SERVO_READBACK_3:
253 case WM8903_DC_SERVO_READBACK_4:
8d50e447 254 return 1;
f1c0a02f
MB		 255
256 default:
f1c0a02f 257 return 0;
8d50e447 258 }
f1c0a02f
MB		 259}
260
f1c0a02f
MB		 261static void wm8903_reset(struct snd_soc_codec *codec)
262{
8d50e447 263 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 264 memcpy(codec->reg_cache, wm8903_reg_defaults,
265 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 266}
267
42768a12
MB		 268static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
269 struct snd_kcontrol *kcontrol, int event)
270{
271 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
272 mdelay(4);
273
274 return 0;
275}
276
c5b6a9fe
MB		 277static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
278 struct snd_kcontrol *kcontrol, int event)
279{
280 struct snd_soc_codec *codec = w->codec;
281 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
282
283 switch (event) {
284 case SND_SOC_DAPM_POST_PMU:
285 wm8903->dcs_pending |= 1 << w->shift;
286 break;
287 case SND_SOC_DAPM_PRE_PMD:
288 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
289 1 << w->shift, 0);
290 break;
291 }
292
293 return 0;
294}
295
296#define WM8903_DCS_MODE_WRITE_STOP 0
297#define WM8903_DCS_MODE_START_STOP 2
298
299static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
300 enum snd_soc_dapm_type event, int subseq)
301{
302 struct snd_soc_codec *codec = container_of(dapm,
303 struct snd_soc_codec, dapm);
304 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
305 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
306 int i, val;
307
308 /* Complete any pending DC servo starts */
309 if (wm8903->dcs_pending) {
310 dev_dbg(codec->dev, "Starting DC servo for %x\n",
311 wm8903->dcs_pending);
312
313 /* If we've no cached values then we need to do startup */
314 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
315 if (!(wm8903->dcs_pending & (1 << i)))
316 continue;
317
318 if (wm8903->dcs_cache[i]) {
319 dev_dbg(codec->dev,
320 "Restore DC servo %d value %x\n",
321 3 - i, wm8903->dcs_cache[i]);
322
323 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
324 wm8903->dcs_cache[i] & 0xff);
325 } else {
326 dev_dbg(codec->dev,
327 "Calibrate DC servo %d\n", 3 - i);
328 dcs_mode = WM8903_DCS_MODE_START_STOP;
329 }
330 }
331
332 /* Don't trust the cache for analogue */
333 if (wm8903->class_w_users)
334 dcs_mode = WM8903_DCS_MODE_START_STOP;
335
336 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
337 WM8903_DCS_MODE_MASK, dcs_mode);
338
339 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
340 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
341
342 switch (dcs_mode) {
343 case WM8903_DCS_MODE_WRITE_STOP:
344 break;
345
346 case WM8903_DCS_MODE_START_STOP:
347 msleep(270);
348
349 /* Cache the measured offsets for digital */
350 if (wm8903->class_w_users)
351 break;
352
353 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
354 if (!(wm8903->dcs_pending & (1 << i)))
355 continue;
356
357 val = snd_soc_read(codec,
358 WM8903_DC_SERVO_READBACK_1 + i);
359 dev_dbg(codec->dev, "DC servo %d: %x\n",
360 3 - i, val);
361 wm8903->dcs_cache[i] = val;
362 }
363 break;
364
365 default:
366 pr_warn("DCS mode %d delay not set\n", dcs_mode);
367 break;
368 }
369
370 wm8903->dcs_pending = 0;
371 }
372}
373
f1c0a02f
MB		 374/*
375 * When used with DAC outputs only the WM8903 charge pump supports
376 * operation in class W mode, providing very low power consumption
377 * when used with digital sources. Enable and disable this mode
378 * automatically depending on the mixer configuration.
379 *
380 * All the relevant controls are simple switches.
381 */
382static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384{
385 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
386 struct snd_soc_codec *codec = widget->codec;
b2c812e2 387 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 388 u16 reg;
389 int ret;
390
8d50e447 391 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 392
393 /* Turn it off if we're about to enable bypass */
394 if (ucontrol->value.integer.value[0]) {
395 if (wm8903->class_w_users == 0) {
f0fba2ad 396 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 397 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 398 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
399 }
400 wm8903->class_w_users++;
401 }
402
403 /* Implement the change */
404 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
405
406 /* If we've just disabled the last bypass path turn Class W on */
407 if (!ucontrol->value.integer.value[0]) {
408 if (wm8903->class_w_users == 1) {
f0fba2ad 409 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 410 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 411 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
412 }
413 wm8903->class_w_users--;
414 }
415
f0fba2ad 416 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 417 wm8903->class_w_users);
418
419 return ret;
420}
421
422#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
423{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
424 .info = snd_soc_info_volsw, \
425 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
426 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
427
428
69fff9bb
MB		 429static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
430
431static int wm8903_set_deemph(struct snd_soc_codec *codec)
432{
433 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
434 int val, i, best;
435
436 /* If we're using deemphasis select the nearest available sample
437 * rate.
438 */
439 if (wm8903->deemph) {
440 best = 1;
441 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
442 if (abs(wm8903_deemph[i] - wm8903->fs) <
443 abs(wm8903_deemph[best] - wm8903->fs))
444 best = i;
445 }
446
447 val = best << WM8903_DEEMPH_SHIFT;
448 } else {
449 best = 0;
450 val = 0;
451 }
452
453 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
454 best, wm8903_deemph[best]);
455
456 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
457 WM8903_DEEMPH_MASK, val);
458}
459
460static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
461 struct snd_ctl_elem_value *ucontrol)
462{
463 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
464 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
465
466 ucontrol->value.enumerated.item[0] = wm8903->deemph;
467
468 return 0;
469}
470
471static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473{
474 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
475 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
476 int deemph = ucontrol->value.enumerated.item[0];
477 int ret = 0;
478
479 if (deemph > 1)
480 return -EINVAL;
481
482 mutex_lock(&codec->mutex);
483 if (wm8903->deemph != deemph) {
484 wm8903->deemph = deemph;
485
486 wm8903_set_deemph(codec);
487
488 ret = 1;
489 }
490 mutex_unlock(&codec->mutex);
491
492 return ret;
493}
494
f1c0a02f
MB		 495/* ALSA can only do steps of .01dB */
496static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
497
291ce18c 498static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 499static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
500
501static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
502static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
503static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
504static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
505static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
506
460f4aae
MB		 507static const char *hpf_mode_text[] = {
508 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
509};
510
511static const struct soc_enum hpf_mode =
512 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
513
dcf9ada3
MB		 514static const char *osr_text[] = {
515 "Low power", "High performance"
516};
517
518static const struct soc_enum adc_osr =
519 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
520
521static const struct soc_enum dac_osr =
522 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
523
f1c0a02f
MB		 524static const char *drc_slope_text[] = {
525 "1", "1/2", "1/4", "1/8", "1/16", "0"
526};
527
528static const struct soc_enum drc_slope_r0 =
529 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
530
531static const struct soc_enum drc_slope_r1 =
532 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
533
534static const char *drc_attack_text[] = {
535 "instantaneous",
536 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
537 "46.4ms", "92.8ms", "185.6ms"
538};
539
540static const struct soc_enum drc_attack =
541 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
542
543static const char *drc_decay_text[] = {
544 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
545 "23.87s", "47.56s"
546};
547
548static const struct soc_enum drc_decay =
549 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
550
551static const char *drc_ff_delay_text[] = {
552 "5 samples", "9 samples"
553};
554
555static const struct soc_enum drc_ff_delay =
556 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
557
558static const char *drc_qr_decay_text[] = {
559 "0.725ms", "1.45ms", "5.8ms"
560};
561
562static const struct soc_enum drc_qr_decay =
563 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
564
565static const char *drc_smoothing_text[] = {
566 "Low", "Medium", "High"
567};
568
569static const struct soc_enum drc_smoothing =
570 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
571
572static const char *soft_mute_text[] = {
573 "Fast (fs/2)", "Slow (fs/32)"
574};
575
576static const struct soc_enum soft_mute =
577 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
578
579static const char *mute_mode_text[] = {
580 "Hard", "Soft"
581};
582
583static const struct soc_enum mute_mode =
584 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
585
f1c0a02f
MB		 586static const char *companding_text[] = {
587 "ulaw", "alaw"
588};
589
590static const struct soc_enum dac_companding =
591 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
592
593static const struct soc_enum adc_companding =
594 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
595
596static const char *input_mode_text[] = {
597 "Single-Ended", "Differential Line", "Differential Mic"
598};
599
600static const struct soc_enum linput_mode_enum =
601 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
602
603static const struct soc_enum rinput_mode_enum =
604 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
605
606static const char *linput_mux_text[] = {
607 "IN1L", "IN2L", "IN3L"
608};
609
610static const struct soc_enum linput_enum =
611 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
612
613static const struct soc_enum linput_inv_enum =
614 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
615
616static const char *rinput_mux_text[] = {
617 "IN1R", "IN2R", "IN3R"
618};
619
620static const struct soc_enum rinput_enum =
621 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
622
623static const struct soc_enum rinput_inv_enum =
624 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
625
626
291ce18c
MB		 627static const char *sidetone_text[] = {
628 "None", "Left", "Right"
629};
630
631static const struct soc_enum lsidetone_enum =
632 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
633
634static const struct soc_enum rsidetone_enum =
635 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
636
1e113bf9
MB		 637static const char *aif_text[] = {
638 "Left", "Right"
639};
640
641static const struct soc_enum lcapture_enum =
642 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
643
644static const struct soc_enum rcapture_enum =
645 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
646
647static const struct soc_enum lplay_enum =
648 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
649
650static const struct soc_enum rplay_enum =
651 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
652
f1c0a02f
MB		 653static const struct snd_kcontrol_new wm8903_snd_controls[] = {
654
655/* Input PGAs - No TLV since the scale depends on PGA mode */
656SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 657 7, 1, 1),
f1c0a02f
MB		 658SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
659 0, 31, 0),
660SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
661 6, 1, 0),
662
663SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 664 7, 1, 1),
f1c0a02f
MB		 665SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
666 0, 31, 0),
667SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
668 6, 1, 0),
669
670/* ADCs */
dcf9ada3 671SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 672SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
673SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 674SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
675SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
676SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 677SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 678 drc_tlv_thresh),
679SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
680SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
681SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
682SOC_ENUM("DRC Attack Rate", drc_attack),
683SOC_ENUM("DRC Decay Rate", drc_decay),
684SOC_ENUM("DRC FF Delay", drc_ff_delay),
685SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
686SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 687SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 688SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
689SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
690SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 691SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 692SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
693
694SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
695 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
696SOC_ENUM("ADC Companding Mode", adc_companding),
697SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
698
291ce18c
MB		 699SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
700 12, 0, digital_sidetone_tlv),
701
f1c0a02f 702/* DAC */
dcf9ada3 703SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 704SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
705 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
706SOC_ENUM("DAC Soft Mute Rate", soft_mute),
707SOC_ENUM("DAC Mute Mode", mute_mode),
708SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 709SOC_ENUM("DAC Companding Mode", dac_companding),
710SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 711SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
712 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 713
714/* Headphones */
715SOC_DOUBLE_R("Headphone Switch",
716 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
717 8, 1, 1),
718SOC_DOUBLE_R("Headphone ZC Switch",
719 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
720 6, 1, 0),
721SOC_DOUBLE_R_TLV("Headphone Volume",
722 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
723 0, 63, 0, out_tlv),
724
725/* Line out */
726SOC_DOUBLE_R("Line Out Switch",
727 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
728 8, 1, 1),
729SOC_DOUBLE_R("Line Out ZC Switch",
730 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
731 6, 1, 0),
732SOC_DOUBLE_R_TLV("Line Out Volume",
733 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
734 0, 63, 0, out_tlv),
735
736/* Speaker */
737SOC_DOUBLE_R("Speaker Switch",
738 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
739SOC_DOUBLE_R("Speaker ZC Switch",
740 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
741SOC_DOUBLE_R_TLV("Speaker Volume",
742 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
743 0, 63, 0, out_tlv),
744};
745
f1c0a02f
MB		 746static const struct snd_kcontrol_new linput_mode_mux =
747 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
748
749static const struct snd_kcontrol_new rinput_mode_mux =
750 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
751
752static const struct snd_kcontrol_new linput_mux =
753 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
754
755static const struct snd_kcontrol_new linput_inv_mux =
756 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
757
758static const struct snd_kcontrol_new rinput_mux =
759 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
760
761static const struct snd_kcontrol_new rinput_inv_mux =
762 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
763
291ce18c
MB		 764static const struct snd_kcontrol_new lsidetone_mux =
765 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
766
767static const struct snd_kcontrol_new rsidetone_mux =
768 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
769
1e113bf9
MB		 770static const struct snd_kcontrol_new lcapture_mux =
771 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
772
773static const struct snd_kcontrol_new rcapture_mux =
774 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
775
776static const struct snd_kcontrol_new lplay_mux =
777 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
778
779static const struct snd_kcontrol_new rplay_mux =
780 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
781
f1c0a02f
MB		 782static const struct snd_kcontrol_new left_output_mixer[] = {
783SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
784SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
785SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 786SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 787};
788
789static const struct snd_kcontrol_new right_output_mixer[] = {
790SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
791SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
792SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 793SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 794};
795
796static const struct snd_kcontrol_new left_speaker_mixer[] = {
797SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
798SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
799SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
800SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 801 0, 1, 0),
f1c0a02f
MB		 802};
803
804static const struct snd_kcontrol_new right_speaker_mixer[] = {
805SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
806SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
807SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
808 1, 1, 0),
809SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 810 0, 1, 0),
f1c0a02f
MB		 811};
812
813static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
814SND_SOC_DAPM_INPUT("IN1L"),
815SND_SOC_DAPM_INPUT("IN1R"),
816SND_SOC_DAPM_INPUT("IN2L"),
817SND_SOC_DAPM_INPUT("IN2R"),
818SND_SOC_DAPM_INPUT("IN3L"),
819SND_SOC_DAPM_INPUT("IN3R"),
820
821SND_SOC_DAPM_OUTPUT("HPOUTL"),
822SND_SOC_DAPM_OUTPUT("HPOUTR"),
823SND_SOC_DAPM_OUTPUT("LINEOUTL"),
824SND_SOC_DAPM_OUTPUT("LINEOUTR"),
825SND_SOC_DAPM_OUTPUT("LOP"),
826SND_SOC_DAPM_OUTPUT("LON"),
827SND_SOC_DAPM_OUTPUT("ROP"),
828SND_SOC_DAPM_OUTPUT("RON"),
829
830SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
831
832SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
833SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
834 &linput_inv_mux),
835SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
836
837SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
838SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
839 &rinput_inv_mux),
840SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
841
842SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
843SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
844
1e113bf9
MB		 845SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
846SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
847
848SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
849SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
850
851SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
852SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 853
291ce18c
MB		 854SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
855SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
856
1e113bf9
MB		 857SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
858SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
859
860SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
861SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
862
863SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
864SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 865
866SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
867 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
868SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
869 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
870
871SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
872 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
873SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
874 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
875
1b877cb5
DL		 876SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
877 1, 0, NULL, 0),
878SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 879 0, 0, NULL, 0),
880
1b877cb5 881SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 882 NULL, 0),
1b877cb5 883SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 884 NULL, 0),
885
886SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
887SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 888SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
889SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 890SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
891SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 892SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
893SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 894
895SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
896 NULL, 0),
897SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
898 NULL, 0),
1b877cb5
DL		 899SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
900 NULL, 0),
901SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 902 NULL, 0),
903SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
904 NULL, 0),
905SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
906 NULL, 0),
1b877cb5
DL		 907SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
908 NULL, 0),
909SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 910 NULL, 0),
911
c5b6a9fe
MB		 912SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
913SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
915SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
917SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
918 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
919SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
920 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 921
922SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
923 NULL, 0),
924SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
925 NULL, 0),
926
42768a12
MB		 927SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
928 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 929SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 930SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 931};
932
ecd01512 933static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 934
2c8be5a2
MB		 935 { "CLK_DSP", NULL, "CLK_SYS" },
936 { "Mic Bias", NULL, "CLK_SYS" },
937 { "HPL_DCS", NULL, "CLK_SYS" },
938 { "HPR_DCS", NULL, "CLK_SYS" },
939 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
940 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
941
f1c0a02f
MB		 942 { "Left Input Mux", "IN1L", "IN1L" },
943 { "Left Input Mux", "IN2L", "IN2L" },
944 { "Left Input Mux", "IN3L", "IN3L" },
945
946 { "Left Input Inverting Mux", "IN1L", "IN1L" },
947 { "Left Input Inverting Mux", "IN2L", "IN2L" },
948 { "Left Input Inverting Mux", "IN3L", "IN3L" },
949
950 { "Right Input Mux", "IN1R", "IN1R" },
951 { "Right Input Mux", "IN2R", "IN2R" },
952 { "Right Input Mux", "IN3R", "IN3R" },
953
954 { "Right Input Inverting Mux", "IN1R", "IN1R" },
955 { "Right Input Inverting Mux", "IN2R", "IN2R" },
956 { "Right Input Inverting Mux", "IN3R", "IN3R" },
957
958 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
959 { "Left Input Mode Mux", "Differential Line",
960 "Left Input Mux" },
961 { "Left Input Mode Mux", "Differential Line",
962 "Left Input Inverting Mux" },
963 { "Left Input Mode Mux", "Differential Mic",
964 "Left Input Mux" },
965 { "Left Input Mode Mux", "Differential Mic",
966 "Left Input Inverting Mux" },
967
968 { "Right Input Mode Mux", "Single-Ended",
969 "Right Input Inverting Mux" },
970 { "Right Input Mode Mux", "Differential Line",
971 "Right Input Mux" },
972 { "Right Input Mode Mux", "Differential Line",
973 "Right Input Inverting Mux" },
974 { "Right Input Mode Mux", "Differential Mic",
975 "Right Input Mux" },
976 { "Right Input Mode Mux", "Differential Mic",
977 "Right Input Inverting Mux" },
978
979 { "Left Input PGA", NULL, "Left Input Mode Mux" },
980 { "Right Input PGA", NULL, "Right Input Mode Mux" },
981
1e113bf9
MB		 982 { "Left Capture Mux", "Left", "ADCL" },
983 { "Left Capture Mux", "Right", "ADCR" },
984
985 { "Right Capture Mux", "Left", "ADCL" },
986 { "Right Capture Mux", "Right", "ADCR" },
987
988 { "AIFTXL", NULL, "Left Capture Mux" },
989 { "AIFTXR", NULL, "Right Capture Mux" },
990
f1c0a02f 991 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 992 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 993 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 994 { "ADCR", NULL, "CLK_DSP" },
995
1e113bf9
MB		 996 { "Left Playback Mux", "Left", "AIFRXL" },
997 { "Left Playback Mux", "Right", "AIFRXR" },
998
999 { "Right Playback Mux", "Left", "AIFRXL" },
1000 { "Right Playback Mux", "Right", "AIFRXR" },
1001
291ce18c
MB		 1002 { "DACL Sidetone", "Left", "ADCL" },
1003 { "DACL Sidetone", "Right", "ADCR" },
1004 { "DACR Sidetone", "Left", "ADCL" },
1005 { "DACR Sidetone", "Right", "ADCR" },
1006
1e113bf9 1007 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1008 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1009 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1010
1011 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1012 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1013 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1014
1015 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1016 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1017 { "Left Output Mixer", "DACL Switch", "DACL" },
1018 { "Left Output Mixer", "DACR Switch", "DACR" },
1019
1020 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1021 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1022 { "Right Output Mixer", "DACL Switch", "DACL" },
1023 { "Right Output Mixer", "DACR Switch", "DACR" },
1024
1025 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1026 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1027 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1028 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1029
1030 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1031 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1032 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1033 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1034
1035 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1036 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1037
1038 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1039 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1040
1041 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1042 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1043
1b877cb5
DL		 1044 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1045 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1046 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1047 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1048 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1049 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1050 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1051 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1052
c5b6a9fe
MB		 1053 { "HPL_DCS", NULL, "DCS Master" },
1054 { "HPR_DCS", NULL, "DCS Master" },
1055 { "LINEOUTL_DCS", NULL, "DCS Master" },
1056 { "LINEOUTR_DCS", NULL, "DCS Master" },
1057
13a9983e
MB		 1058 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1059 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1060 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1061 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1062
1063 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1064 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1065 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1066 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1067
1068 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1069 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1070 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1071 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1072
1073 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1074 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1075 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1076 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1077
1078 { "LOP", NULL, "Left Speaker PGA" },
1079 { "LON", NULL, "Left Speaker PGA" },
1080
1081 { "ROP", NULL, "Right Speaker PGA" },
1082 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1083
1084 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1085 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1086 { "Left Line Output PGA", NULL, "Charge Pump" },
1087 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1088};
1089
f1c0a02f
MB		 1090static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1091 enum snd_soc_bias_level level)
1092{
f1c0a02f
MB		 1093 switch (level) {
1094 case SND_SOC_BIAS_ON:
66daaa59 1095 break;
22f226dd 1096
f1c0a02f 1097 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1098 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1099 WM8903_VMID_RES_MASK,
1100 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1101 break;
1102
1103 case SND_SOC_BIAS_STANDBY:
ce6120cc 1104 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1105 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1106 WM8903_POBCTRL | WM8903_ISEL_MASK |
1107 WM8903_STARTUP_BIAS_ENA |
1108 WM8903_BIAS_ENA,
1109 WM8903_POBCTRL |
1110 (2 << WM8903_ISEL_SHIFT) |
1111 WM8903_STARTUP_BIAS_ENA);
1112
1113 snd_soc_update_bits(codec,
1114 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1115 WM8903_SPK_DISCHARGE,
1116 WM8903_SPK_DISCHARGE);
1117
1118 msleep(33);
1119
1120 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1121 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1122 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1123
1124 snd_soc_update_bits(codec,
1125 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1126 WM8903_SPK_DISCHARGE, 0);
1127
1128 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1129 WM8903_VMID_TIE_ENA |
1130 WM8903_BUFIO_ENA |
1131 WM8903_VMID_IO_ENA |
1132 WM8903_VMID_SOFT_MASK |
1133 WM8903_VMID_RES_MASK |
1134 WM8903_VMID_BUF_ENA,
1135 WM8903_VMID_TIE_ENA |
1136 WM8903_BUFIO_ENA |
1137 WM8903_VMID_IO_ENA |
1138 (2 << WM8903_VMID_SOFT_SHIFT) |
1139 WM8903_VMID_RES_250K |
1140 WM8903_VMID_BUF_ENA);
1141
1142 msleep(129);
1143
1144 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1145 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1146 0);
1147
1148 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1149 WM8903_VMID_SOFT_MASK, 0);
1150
1151 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1152 WM8903_VMID_RES_MASK,
1153 WM8903_VMID_RES_50K);
1154
1155 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1156 WM8903_BIAS_ENA | WM8903_POBCTRL,
1157 WM8903_BIAS_ENA);
f1c0a02f 1158
f1c0a02f
MB		 1159 /* By default no bypass paths are enabled so
1160 * enable Class W support.
1161 */
f0fba2ad 1162 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1163 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1164 WM8903_CP_DYN_FREQ |
1165 WM8903_CP_DYN_V,
1166 WM8903_CP_DYN_FREQ |
1167 WM8903_CP_DYN_V);
f1c0a02f
MB		 1168 }
1169
66daaa59
MB		 1170 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1171 WM8903_VMID_RES_MASK,
1172 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1173 break;
1174
1175 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1176 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1177 WM8903_BIAS_ENA, 0);
1178
1179 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1180 WM8903_VMID_SOFT_MASK,
1181 2 << WM8903_VMID_SOFT_SHIFT);
1182
1183 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1184 WM8903_VMID_BUF_ENA, 0);
1185
1186 msleep(290);
1187
1188 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1189 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1190 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1191 WM8903_VMID_SOFT_MASK |
1192 WM8903_VMID_BUF_ENA, 0);
1193
1194 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1195 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1196 break;
1197 }
1198
ce6120cc 1199 codec->dapm.bias_level = level;
f1c0a02f
MB		 1200
1201 return 0;
1202}
1203
1204static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1205 int clk_id, unsigned int freq, int dir)
1206{
1207 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1208 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1209
1210 wm8903->sysclk = freq;
1211
1212 return 0;
1213}
1214
1215static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1216 unsigned int fmt)
1217{
1218 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1219 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1220
1221 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1222 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1223
1224 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1225 case SND_SOC_DAIFMT_CBS_CFS:
1226 break;
1227 case SND_SOC_DAIFMT_CBS_CFM:
1228 aif1 |= WM8903_LRCLK_DIR;
1229 break;
1230 case SND_SOC_DAIFMT_CBM_CFM:
1231 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1232 break;
1233 case SND_SOC_DAIFMT_CBM_CFS:
1234 aif1 |= WM8903_BCLK_DIR;
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1241 case SND_SOC_DAIFMT_DSP_A:
1242 aif1 |= 0x3;
1243 break;
1244 case SND_SOC_DAIFMT_DSP_B:
1245 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1246 break;
1247 case SND_SOC_DAIFMT_I2S:
1248 aif1 |= 0x2;
1249 break;
1250 case SND_SOC_DAIFMT_RIGHT_J:
1251 aif1 |= 0x1;
1252 break;
1253 case SND_SOC_DAIFMT_LEFT_J:
1254 break;
1255 default:
1256 return -EINVAL;
1257 }
1258
1259 /* Clock inversion */
1260 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1261 case SND_SOC_DAIFMT_DSP_A:
1262 case SND_SOC_DAIFMT_DSP_B:
1263 /* frame inversion not valid for DSP modes */
1264 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1265 case SND_SOC_DAIFMT_NB_NF:
1266 break;
1267 case SND_SOC_DAIFMT_IB_NF:
1268 aif1 |= WM8903_AIF_BCLK_INV;
1269 break;
1270 default:
1271 return -EINVAL;
1272 }
1273 break;
1274 case SND_SOC_DAIFMT_I2S:
1275 case SND_SOC_DAIFMT_RIGHT_J:
1276 case SND_SOC_DAIFMT_LEFT_J:
1277 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1278 case SND_SOC_DAIFMT_NB_NF:
1279 break;
1280 case SND_SOC_DAIFMT_IB_IF:
1281 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1282 break;
1283 case SND_SOC_DAIFMT_IB_NF:
1284 aif1 |= WM8903_AIF_BCLK_INV;
1285 break;
1286 case SND_SOC_DAIFMT_NB_IF:
1287 aif1 |= WM8903_AIF_LRCLK_INV;
1288 break;
1289 default:
1290 return -EINVAL;
1291 }
1292 break;
1293 default:
1294 return -EINVAL;
1295 }
1296
8d50e447 1297 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1298
1299 return 0;
1300}
1301
1302static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1303{
1304 struct snd_soc_codec *codec = codec_dai->codec;
1305 u16 reg;
1306
8d50e447 1307 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1308
1309 if (mute)
1310 reg |= WM8903_DAC_MUTE;
1311 else
1312 reg &= ~WM8903_DAC_MUTE;
1313
8d50e447 1314 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1315
1316 return 0;
1317}
1318
1319/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1320 * for optimal performance so we list the lower rates first and match
1321 * on the last match we find. */
1322static struct {
1323 int div;
1324 int rate;
1325 int mode;
1326 int mclk_div;
1327} clk_sys_ratios[] = {
1328 { 64, 0x0, 0x0, 1 },
1329 { 68, 0x0, 0x1, 1 },
1330 { 125, 0x0, 0x2, 1 },
1331 { 128, 0x1, 0x0, 1 },
1332 { 136, 0x1, 0x1, 1 },
1333 { 192, 0x2, 0x0, 1 },
1334 { 204, 0x2, 0x1, 1 },
1335
1336 { 64, 0x0, 0x0, 2 },
1337 { 68, 0x0, 0x1, 2 },
1338 { 125, 0x0, 0x2, 2 },
1339 { 128, 0x1, 0x0, 2 },
1340 { 136, 0x1, 0x1, 2 },
1341 { 192, 0x2, 0x0, 2 },
1342 { 204, 0x2, 0x1, 2 },
1343
1344 { 250, 0x2, 0x2, 1 },
1345 { 256, 0x3, 0x0, 1 },
1346 { 272, 0x3, 0x1, 1 },
1347 { 384, 0x4, 0x0, 1 },
1348 { 408, 0x4, 0x1, 1 },
1349 { 375, 0x4, 0x2, 1 },
1350 { 512, 0x5, 0x0, 1 },
1351 { 544, 0x5, 0x1, 1 },
1352 { 500, 0x5, 0x2, 1 },
1353 { 768, 0x6, 0x0, 1 },
1354 { 816, 0x6, 0x1, 1 },
1355 { 750, 0x6, 0x2, 1 },
1356 { 1024, 0x7, 0x0, 1 },
1357 { 1088, 0x7, 0x1, 1 },
1358 { 1000, 0x7, 0x2, 1 },
1359 { 1408, 0x8, 0x0, 1 },
1360 { 1496, 0x8, 0x1, 1 },
1361 { 1536, 0x9, 0x0, 1 },
1362 { 1632, 0x9, 0x1, 1 },
1363 { 1500, 0x9, 0x2, 1 },
1364
1365 { 250, 0x2, 0x2, 2 },
1366 { 256, 0x3, 0x0, 2 },
1367 { 272, 0x3, 0x1, 2 },
1368 { 384, 0x4, 0x0, 2 },
1369 { 408, 0x4, 0x1, 2 },
1370 { 375, 0x4, 0x2, 2 },
1371 { 512, 0x5, 0x0, 2 },
1372 { 544, 0x5, 0x1, 2 },
1373 { 500, 0x5, 0x2, 2 },
1374 { 768, 0x6, 0x0, 2 },
1375 { 816, 0x6, 0x1, 2 },
1376 { 750, 0x6, 0x2, 2 },
1377 { 1024, 0x7, 0x0, 2 },
1378 { 1088, 0x7, 0x1, 2 },
1379 { 1000, 0x7, 0x2, 2 },
1380 { 1408, 0x8, 0x0, 2 },
1381 { 1496, 0x8, 0x1, 2 },
1382 { 1536, 0x9, 0x0, 2 },
1383 { 1632, 0x9, 0x1, 2 },
1384 { 1500, 0x9, 0x2, 2 },
1385};
1386
1387/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1388static struct {
1389 int ratio;
1390 int div;
1391} bclk_divs[] = {
1392 { 10, 0 },
f1c0a02f
MB		 1393 { 20, 2 },
1394 { 30, 3 },
1395 { 40, 4 },
1396 { 50, 5 },
f1c0a02f
MB		 1397 { 60, 7 },
1398 { 80, 8 },
1399 { 100, 9 },
f1c0a02f
MB		 1400 { 120, 11 },
1401 { 160, 12 },
1402 { 200, 13 },
1403 { 220, 14 },
1404 { 240, 15 },
f1c0a02f
MB		 1405 { 300, 17 },
1406 { 320, 18 },
1407 { 440, 19 },
1408 { 480, 20 },
1409};
1410
1411/* Sample rates for DSP */
1412static struct {
1413 int rate;
1414 int value;
1415} sample_rates[] = {
1416 { 8000, 0 },
1417 { 11025, 1 },
1418 { 12000, 2 },
1419 { 16000, 3 },
1420 { 22050, 4 },
1421 { 24000, 5 },
1422 { 32000, 6 },
1423 { 44100, 7 },
1424 { 48000, 8 },
1425 { 88200, 9 },
1426 { 96000, 10 },
1427 { 0, 0 },
1428};
1429
f1c0a02f 1430static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1431 struct snd_pcm_hw_params *params,
1432 struct snd_soc_dai *dai)
f1c0a02f
MB		 1433{
1434 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1435 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1436 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1437 int fs = params_rate(params);
1438 int bclk;
1439 int bclk_div;
1440 int i;
1441 int dsp_config;
1442 int clk_config;
1443 int best_val;
1444 int cur_val;
1445 int clk_sys;
1446
8d50e447
MB		 1447 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1448 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1449 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1450 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1451 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1452 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1453
9e79261f
MB		 1454 /* Enable sloping stopband filter for low sample rates */
1455 if (fs <= 24000)
1456 dac_digital1 |= WM8903_DAC_SB_FILT;
1457 else
1458 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1459
f1c0a02f
MB		 1460 /* Configure sample rate logic for DSP - choose nearest rate */
1461 dsp_config = 0;
1462 best_val = abs(sample_rates[dsp_config].rate - fs);
1463 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1464 cur_val = abs(sample_rates[i].rate - fs);
1465 if (cur_val <= best_val) {
1466 dsp_config = i;
1467 best_val = cur_val;
1468 }
1469 }
1470
f0fba2ad 1471 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1472 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1473 clock1 |= sample_rates[dsp_config].value;
1474
1475 aif1 &= ~WM8903_AIF_WL_MASK;
1476 bclk = 2 * fs;
1477 switch (params_format(params)) {
1478 case SNDRV_PCM_FORMAT_S16_LE:
1479 bclk *= 16;
1480 break;
1481 case SNDRV_PCM_FORMAT_S20_3LE:
1482 bclk *= 20;
1483 aif1 |= 0x4;
1484 break;
1485 case SNDRV_PCM_FORMAT_S24_LE:
1486 bclk *= 24;
1487 aif1 |= 0x8;
1488 break;
1489 case SNDRV_PCM_FORMAT_S32_LE:
1490 bclk *= 32;
1491 aif1 |= 0xc;
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496
f0fba2ad 1497 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1498 wm8903->sysclk, fs);
1499
1500 /* We may not have an MCLK which allows us to generate exactly
1501 * the clock we want, particularly with USB derived inputs, so
1502 * approximate.
1503 */
1504 clk_config = 0;
1505 best_val = abs((wm8903->sysclk /
1506 (clk_sys_ratios[0].mclk_div *
1507 clk_sys_ratios[0].div)) - fs);
1508 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1509 cur_val = abs((wm8903->sysclk /
1510 (clk_sys_ratios[i].mclk_div *
1511 clk_sys_ratios[i].div)) - fs);
1512
1513 if (cur_val <= best_val) {
1514 clk_config = i;
1515 best_val = cur_val;
1516 }
1517 }
1518
1519 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1520 clock0 |= WM8903_MCLKDIV2;
1521 clk_sys = wm8903->sysclk / 2;
1522 } else {
1523 clock0 &= ~WM8903_MCLKDIV2;
1524 clk_sys = wm8903->sysclk;
1525 }
1526
1527 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1528 WM8903_CLK_SYS_MODE_MASK);
1529 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1530 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1531
f0fba2ad 1532 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1533 clk_sys_ratios[clk_config].rate,
1534 clk_sys_ratios[clk_config].mode,
1535 clk_sys_ratios[clk_config].div);
1536
f0fba2ad 1537 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1538
1539 /* We may not get quite the right frequency if using
1540 * approximate clocks so look for the closest match that is
1541 * higher than the target (we need to ensure that there enough
1542 * BCLKs to clock out the samples).
1543 */
1544 bclk_div = 0;
1545 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1546 i = 1;
1547 while (i < ARRAY_SIZE(bclk_divs)) {
1548 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1549 if (cur_val < 0) /* BCLK table is sorted */
1550 break;
1551 bclk_div = i;
1552 best_val = cur_val;
1553 i++;
1554 }
1555
1556 aif2 &= ~WM8903_BCLK_DIV_MASK;
1557 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1558
f0fba2ad 1559 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1560 bclk_divs[bclk_div].ratio / 10, bclk,
1561 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1562
1563 aif2 |= bclk_divs[bclk_div].div;
1564 aif3 |= bclk / fs;
1565
69fff9bb
MB		 1566 wm8903->fs = params_rate(params);
1567 wm8903_set_deemph(codec);
1568
8d50e447
MB		 1569 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1570 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1571 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1572 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1573 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1574 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1575
1576 return 0;
1577}
1578
7245387e
MB		 1579/**
1580 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1581 *
1582 * @codec: WM8903 codec
1583 * @jack: jack to report detection events on
1584 * @det: value to report for presence detection
1585 * @shrt: value to report for short detection
1586 *
1587 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1588 * being used to bring out signals to the processor then only platform
1589 * data configuration is needed for WM8903 and processor GPIOs should
1590 * be configured using snd_soc_jack_add_gpios() instead.
1591 *
1592 * The current threasholds for detection should be configured using
1593 * micdet_cfg in the platform data. Using this function will force on
1594 * the microphone bias for the device.
1595 */
1596int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1597 int det, int shrt)
1598{
b2c812e2 1599 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1600 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1601
1602 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1603 det, shrt);
1604
1605 /* Store the configuration */
1606 wm8903->mic_jack = jack;
1607 wm8903->mic_det = det;
1608 wm8903->mic_short = shrt;
1609
1610 /* Enable interrupts we've got a report configured for */
1611 if (det)
1612 irq_mask &= ~WM8903_MICDET_EINT;
1613 if (shrt)
1614 irq_mask &= ~WM8903_MICSHRT_EINT;
1615
1616 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1617 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1618 irq_mask);
1619
3088e3b4 1620 if (det || shrt) {
69266866
MB		 1621 /* Enable mic detection, this may not have been set through
1622 * platform data (eg, if the defaults are OK). */
1623 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1624 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1625 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1626 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1627 } else {
1628 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1629 WM8903_MICDET_ENA, 0);
1630 }
7245387e
MB		 1631
1632 return 0;
1633}
1634EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1635
8abd16a6
MB		 1636static irqreturn_t wm8903_irq(int irq, void *data)
1637{
f0fba2ad
LG		 1638 struct snd_soc_codec *codec = data;
1639 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1640 int mic_report;
1641 int int_pol;
1642 int int_val = 0;
1643 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1644
7245387e 1645 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1646
7245387e 1647 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1648 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1649 }
1650
7245387e
MB		 1651 /*
1652 * The rest is microphone jack detection. We need to manually
1653 * invert the polarity of the interrupt after each event - to
1654 * simplify the code keep track of the last state we reported
1655 * and just invert the relevant bits in both the report and
1656 * the polarity register.
1657 */
1658 mic_report = wm8903->mic_last_report;
1659 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1660
1435b940 1661#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1662 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1663 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1664#endif
2bbb5d66 1665
7245387e
MB		 1666 if (int_val & WM8903_MICSHRT_EINT) {
1667 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1668
1669 mic_report ^= wm8903->mic_short;
1670 int_pol ^= WM8903_MICSHRT_INV;
1671 }
1672
1673 if (int_val & WM8903_MICDET_EINT) {
1674 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1675
1676 mic_report ^= wm8903->mic_det;
1677 int_pol ^= WM8903_MICDET_INV;
1678
1679 msleep(wm8903->mic_delay);
1680 }
1681
1682 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1683 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1684
1685 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1686 wm8903->mic_short | wm8903->mic_det);
1687
1688 wm8903->mic_last_report = mic_report;
1689
8abd16a6
MB		 1690 return IRQ_HANDLED;
1691}
1692
f1c0a02f
MB		 1693#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1694 SNDRV_PCM_RATE_11025 | \
1695 SNDRV_PCM_RATE_16000 | \
1696 SNDRV_PCM_RATE_22050 | \
1697 SNDRV_PCM_RATE_32000 | \
1698 SNDRV_PCM_RATE_44100 | \
1699 SNDRV_PCM_RATE_48000 | \
1700 SNDRV_PCM_RATE_88200 | \
1701 SNDRV_PCM_RATE_96000)
1702
1703#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1704 SNDRV_PCM_RATE_11025 | \
1705 SNDRV_PCM_RATE_16000 | \
1706 SNDRV_PCM_RATE_22050 | \
1707 SNDRV_PCM_RATE_32000 | \
1708 SNDRV_PCM_RATE_44100 | \
1709 SNDRV_PCM_RATE_48000)
1710
1711#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1712 SNDRV_PCM_FMTBIT_S20_3LE |\
1713 SNDRV_PCM_FMTBIT_S24_LE)
1714
6335d055 1715static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1716 .hw_params = wm8903_hw_params,
1717 .digital_mute = wm8903_digital_mute,
1718 .set_fmt = wm8903_set_dai_fmt,
1719 .set_sysclk = wm8903_set_dai_sysclk,
1720};
1721
f0fba2ad
LG		 1722static struct snd_soc_dai_driver wm8903_dai = {
1723 .name = "wm8903-hifi",
f1c0a02f
MB		 1724 .playback = {
1725 .stream_name = "Playback",
1726 .channels_min = 2,
1727 .channels_max = 2,
1728 .rates = WM8903_PLAYBACK_RATES,
1729 .formats = WM8903_FORMATS,
1730 },
1731 .capture = {
1732 .stream_name = "Capture",
1733 .channels_min = 2,
1734 .channels_max = 2,
1735 .rates = WM8903_CAPTURE_RATES,
1736 .formats = WM8903_FORMATS,
1737 },
6335d055 1738 .ops = &wm8903_dai_ops,
0d960e88 1739 .symmetric_rates = 1,
f1c0a02f 1740};
f1c0a02f 1741
f0fba2ad 1742static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1743{
f1c0a02f
MB		 1744 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1745
1746 return 0;
1747}
1748
f0fba2ad 1749static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1750{
f1c0a02f
MB		 1751 int i;
1752 u16 *reg_cache = codec->reg_cache;
40aa7030 1753 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1754 GFP_KERNEL);
1755
1756 /* Bring the codec back up to standby first to minimise pop/clicks */
1757 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1758
1759 /* Sync back everything else */
1760 if (tmp_cache) {
1761 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1762 if (tmp_cache[i] != reg_cache[i])
8d50e447 1763 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1764 kfree(tmp_cache);
f1c0a02f 1765 } else {
f0fba2ad 1766 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1767 }
1768
1769 return 0;
1770}
1771
7cfe5617
SW		 1772#ifdef CONFIG_GPIOLIB
1773static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1774{
1775 return container_of(chip, struct wm8903_priv, gpio_chip);
1776}
1777
1778static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1779{
1780 if (offset >= WM8903_NUM_GPIO)
1781 return -EINVAL;
1782
1783 return 0;
1784}
1785
1786static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1787{
1788 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1789 struct snd_soc_codec *codec = wm8903->codec;
1790 unsigned int mask, val;
1791
1792 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1793 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1794 WM8903_GP1_DIR;
1795
1796 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1797 mask, val);
1798}
1799
1800static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1801{
1802 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1803 struct snd_soc_codec *codec = wm8903->codec;
1804 int reg;
1805
1806 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1807
1808 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1809}
1810
1811static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1812 unsigned offset, int value)
1813{
1814 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1815 struct snd_soc_codec *codec = wm8903->codec;
1816 unsigned int mask, val;
1817
1818 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1819 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1820 (value << WM8903_GP2_LVL_SHIFT);
1821
1822 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1823 mask, val);
1824}
1825
1826static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1827{
1828 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1829 struct snd_soc_codec *codec = wm8903->codec;
1830
1831 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1832 WM8903_GP1_LVL_MASK,
1833 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1834}
1835
1836static struct gpio_chip wm8903_template_chip = {
1837 .label = "wm8903",
1838 .owner = THIS_MODULE,
1839 .request = wm8903_gpio_request,
1840 .direction_input = wm8903_gpio_direction_in,
1841 .get = wm8903_gpio_get,
1842 .direction_output = wm8903_gpio_direction_out,
1843 .set = wm8903_gpio_set,
1844 .can_sleep = 1,
1845};
1846
1847static void wm8903_init_gpio(struct snd_soc_codec *codec)
1848{
1849 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1850 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1851 int ret;
1852
1853 wm8903->gpio_chip = wm8903_template_chip;
1854 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1855 wm8903->gpio_chip.dev = codec->dev;
1856
1857 if (pdata && pdata->gpio_base)
1858 wm8903->gpio_chip.base = pdata->gpio_base;
1859 else
1860 wm8903->gpio_chip.base = -1;
1861
1862 ret = gpiochip_add(&wm8903->gpio_chip);
1863 if (ret != 0)
1864 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1865}
1866
1867static void wm8903_free_gpio(struct snd_soc_codec *codec)
1868{
1869 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1870 int ret;
1871
1872 ret = gpiochip_remove(&wm8903->gpio_chip);
1873 if (ret != 0)
1874 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1875}
1876#else
1877static void wm8903_init_gpio(struct snd_soc_codec *codec)
1878{
1879}
1880
1881static void wm8903_free_gpio(struct snd_soc_codec *codec)
1882{
1883}
1884#endif
1885
f0fba2ad 1886static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1887{
f0fba2ad
LG		 1888 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1889 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1890 int ret, i;
8abd16a6 1891 int trigger, irq_pol;
f1c0a02f
MB		 1892 u16 val;
1893
7cfe5617 1894 wm8903->codec = codec;
d58d5d55 1895
8d50e447
MB		 1896 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1897 if (ret != 0) {
f0fba2ad
LG		 1898 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1899 return ret;
8d50e447
MB		 1900 }
1901
1902 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1903 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1904 dev_err(codec->dev,
d58d5d55
MB		 1905 "Device with ID register %x is not a WM8903\n", val);
1906 return -ENODEV;
f1c0a02f
MB		 1907 }
1908
8d50e447 1909 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1910 dev_info(codec->dev, "WM8903 revision %c\n",
1911 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1912
1913 wm8903_reset(codec);
1914
37f88e84 1915 /* Set up GPIOs and microphone detection */
73b34ead 1916 if (pdata) {
905f6952
MB		 1917 bool mic_gpio = false;
1918
73b34ead 1919 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1920 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1921 continue;
1922
1923 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1924 pdata->gpio_cfg[i] & 0xffff);
905f6952
MB		 1925
1926 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1927 >> WM8903_GP1_FN_SHIFT;
1928
1929 switch (val) {
1930 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1931 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1932 mic_gpio = true;
1933 break;
1934 default:
1935 break;
1936 }
73b34ead 1937 }
37f88e84
MB		 1938
1939 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1940 pdata->micdet_cfg);
1941
1942 /* Microphone detection needs the WSEQ clock */
1943 if (pdata->micdet_cfg)
1944 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1945 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1946
905f6952
MB		 1947 /* If microphone detection is enabled by pdata but
1948 * detected via IRQ then interrupts can be lost before
1949 * the machine driver has set up microphone detection
1950 * IRQs as the IRQs are clear on read. The detection
1951 * will be enabled when the machine driver configures.
1952 */
1953 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
1954
37f88e84 1955 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1956 }
8abd16a6 1957
f0fba2ad 1958 if (wm8903->irq) {
8abd16a6
MB		 1959 if (pdata && pdata->irq_active_low) {
1960 trigger = IRQF_TRIGGER_LOW;
1961 irq_pol = WM8903_IRQ_POL;
1962 } else {
1963 trigger = IRQF_TRIGGER_HIGH;
1964 irq_pol = 0;
1965 }
1966
1967 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1968 WM8903_IRQ_POL, irq_pol);
1969
f0fba2ad 1970 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1971 trigger | IRQF_ONESHOT,
f0fba2ad 1972 "wm8903", codec);
8abd16a6 1973 if (ret != 0) {
f0fba2ad 1974 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1975 ret);
f0fba2ad 1976 return ret;
8abd16a6
MB		 1977 }
1978
1979 /* Enable write sequencer interrupts */
1980 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1981 WM8903_IM_WSEQ_BUSY_EINT, 0);
1982 }
73b34ead 1983
f1c0a02f
MB		 1984 /* power on device */
1985 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1986
1987 /* Latch volume update bits */
8d50e447 1988 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1989 val |= WM8903_ADCVU;
8d50e447
MB		 1990 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1991 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1992
8d50e447 1993 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1994 val |= WM8903_DACVU;
8d50e447
MB		 1995 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1996 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1997
8d50e447 1998 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1999 val |= WM8903_HPOUTVU;
8d50e447
MB		 2000 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
2001 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 2002
8d50e447 2003 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 2004 val |= WM8903_LINEOUTVU;
8d50e447
MB		 2005 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
2006 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 2007
8d50e447 2008 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 2009 val |= WM8903_SPKVU;
8d50e447
MB		 2010 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
2011 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 2012
2013 /* Enable DAC soft mute by default */
e12adab0
MB		 2014 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
2015 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2016 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 2017
f0fba2ad
LG		 2018 snd_soc_add_controls(codec, wm8903_snd_controls,
2019 ARRAY_SIZE(wm8903_snd_controls));
f1c0a02f 2020
7cfe5617
SW		 2021 wm8903_init_gpio(codec);
2022
f1c0a02f
MB		 2023 return ret;
2024}
2025
f0fba2ad
LG		 2026/* power down chip */
2027static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2028{
7cfe5617 2029 wm8903_free_gpio(codec);
f0fba2ad
LG		 2030 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
2031 return 0;
2032}
f1c0a02f 2033
f0fba2ad
LG		 2034static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2035 .probe = wm8903_probe,
2036 .remove = wm8903_remove,
2037 .suspend = wm8903_suspend,
2038 .resume = wm8903_resume,
2039 .set_bias_level = wm8903_set_bias_level,
2040 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2041 .reg_word_size = sizeof(u16),
2042 .reg_cache_default = wm8903_reg_defaults,
2043 .volatile_register = wm8903_volatile_register,
c5b6a9fe 2044 .seq_notifier = wm8903_seq_notifier,
ecd01512
MB		 2045 .dapm_widgets = wm8903_dapm_widgets,
2046 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2047 .dapm_routes = wm8903_intercon,
2048 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2049};
f1c0a02f 2050
f0fba2ad
LG		 2051#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2052static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2053 const struct i2c_device_id *id)
2054{
2055 struct wm8903_priv *wm8903;
2056 int ret;
f1c0a02f 2057
f0fba2ad
LG		 2058 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
2059 if (wm8903 == NULL)
2060 return -ENOMEM;
8abd16a6 2061
f0fba2ad 2062 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2063 wm8903->irq = i2c->irq;
d58d5d55 2064
f0fba2ad
LG		 2065 ret = snd_soc_register_codec(&i2c->dev,
2066 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2067 if (ret < 0)
2068 kfree(wm8903);
2069 return ret;
2070}
f1c0a02f 2071
f0fba2ad
LG		 2072static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2073{
2074 snd_soc_unregister_codec(&client->dev);
2075 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 2076 return 0;
2077}
2078
f1c0a02f 2079static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2080 { "wm8903", 0 },
2081 { }
f1c0a02f
MB		 2082};
2083MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2084
2085static struct i2c_driver wm8903_i2c_driver = {
2086 .driver = {
4b592c91 2087 .name = "wm8903",
f1c0a02f
MB		 2088 .owner = THIS_MODULE,
2089 },
f0fba2ad
LG		 2090 .probe = wm8903_i2c_probe,
2091 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2092 .id_table = wm8903_i2c_id,
2093};
f0fba2ad 2094#endif
f1c0a02f 2095
f0fba2ad 2096static int __init wm8903_modinit(void)
f1c0a02f 2097{
f1c0a02f 2098 int ret = 0;
f0fba2ad
LG		 2099#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2100 ret = i2c_add_driver(&wm8903_i2c_driver);
2101 if (ret != 0) {
2102 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2103 ret);
f1c0a02f 2104 }
f0fba2ad 2105#endif
f1c0a02f 2106 return ret;
64089b84
MB		 2107}
2108module_init(wm8903_modinit);
2109
2110static void __exit wm8903_exit(void)
2111{
f0fba2ad 2112#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 2113 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 2114#endif
64089b84
MB		 2115}
2116module_exit(wm8903_exit);
2117
f1c0a02f
MB		 2118MODULE_DESCRIPTION("ASoC WM8903 driver");
2119MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2120MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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