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ASoC: WM8903: Remove conditionals checking pdata != NULL
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
ee244ce4 26#include <linux/regmap.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f 40/* Register defaults at reset */
ee244ce4
MB		 41static const struct reg_default wm8903_reg_defaults[] = {
42 { 4, 0x0018 }, /* R4 - Bias Control 0 */
43 { 5, 0x0000 }, /* R5 - VMID Control 0 */
44 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
45 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
46 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
47 { 12, 0x0000 }, /* R12 - Power Management 0 */
48 { 13, 0x0000 }, /* R13 - Power Management 1 */
49 { 14, 0x0000 }, /* R14 - Power Management 2 */
50 { 15, 0x0000 }, /* R15 - Power Management 3 */
51 { 16, 0x0000 }, /* R16 - Power Management 4 */
52 { 17, 0x0000 }, /* R17 - Power Management 5 */
53 { 18, 0x0000 }, /* R18 - Power Management 6 */
54 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
55 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
56 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
57 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
58 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
59 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
60 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
61 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
62 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
63 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
64 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
65 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
66 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
67 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
68 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
69 { 40, 0x09BF }, /* R40 - DRC 0 */
70 { 41, 0x3241 }, /* R41 - DRC 1 */
71 { 42, 0x0020 }, /* R42 - DRC 2 */
72 { 43, 0x0000 }, /* R43 - DRC 3 */
73 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
74 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
75 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
76 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
77 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
78 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
79 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
80 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
81 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
82 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
83 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
84 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
85 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
86 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
87 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
88 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
89 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
90 { 67, 0x0010 }, /* R67 - DC Servo 0 */
91 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
92 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
93 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
94 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
95 { 104, 0x0000 }, /* R104 - Class W 0 */
96 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
97 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
98 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
99 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
100 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
101 { 114, 0x0000 }, /* R114 - Control Interface */
102 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
103 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
104 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
105 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
106 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
107 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
108 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
109 { 126, 0x0000 }, /* R126 - Interrupt Control */
110 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
111 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
112 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
113 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
f1c0a02f
MB		 114};
115
d58d5d55 116struct wm8903_priv {
c0eb27cf 117 struct wm8903_platform_data *pdata;
7cfe5617 118 struct snd_soc_codec *codec;
ee244ce4 119 struct regmap *regmap;
f0fba2ad 120
d58d5d55 121 int sysclk;
f0fba2ad 122 int irq;
d58d5d55 123
69fff9bb
MB		 124 int fs;
125 int deemph;
126
c5b6a9fe
MB		 127 int dcs_pending;
128 int dcs_cache[4];
129
f2c1fe09 130 /* Reference count */
d58d5d55 131 int class_w_users;
d58d5d55 132
7245387e
MB		 133 struct snd_soc_jack *mic_jack;
134 int mic_det;
135 int mic_short;
136 int mic_last_report;
137 int mic_delay;
7cfe5617
SW		 138
139#ifdef CONFIG_GPIOLIB
140 struct gpio_chip gpio_chip;
141#endif
d58d5d55
MB		 142};
143
ee244ce4
MB		 144static bool wm8903_readable_register(struct device *dev, unsigned int reg)
145{
146 switch (reg) {
147 case WM8903_SW_RESET_AND_ID:
148 case WM8903_REVISION_NUMBER:
149 case WM8903_BIAS_CONTROL_0:
150 case WM8903_VMID_CONTROL_0:
151 case WM8903_MIC_BIAS_CONTROL_0:
152 case WM8903_ANALOGUE_DAC_0:
153 case WM8903_ANALOGUE_ADC_0:
154 case WM8903_POWER_MANAGEMENT_0:
155 case WM8903_POWER_MANAGEMENT_1:
156 case WM8903_POWER_MANAGEMENT_2:
157 case WM8903_POWER_MANAGEMENT_3:
158 case WM8903_POWER_MANAGEMENT_4:
159 case WM8903_POWER_MANAGEMENT_5:
160 case WM8903_POWER_MANAGEMENT_6:
161 case WM8903_CLOCK_RATES_0:
162 case WM8903_CLOCK_RATES_1:
163 case WM8903_CLOCK_RATES_2:
164 case WM8903_AUDIO_INTERFACE_0:
165 case WM8903_AUDIO_INTERFACE_1:
166 case WM8903_AUDIO_INTERFACE_2:
167 case WM8903_AUDIO_INTERFACE_3:
168 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
169 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
170 case WM8903_DAC_DIGITAL_0:
171 case WM8903_DAC_DIGITAL_1:
172 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
173 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
174 case WM8903_ADC_DIGITAL_0:
175 case WM8903_DIGITAL_MICROPHONE_0:
176 case WM8903_DRC_0:
177 case WM8903_DRC_1:
178 case WM8903_DRC_2:
179 case WM8903_DRC_3:
180 case WM8903_ANALOGUE_LEFT_INPUT_0:
181 case WM8903_ANALOGUE_RIGHT_INPUT_0:
182 case WM8903_ANALOGUE_LEFT_INPUT_1:
183 case WM8903_ANALOGUE_RIGHT_INPUT_1:
184 case WM8903_ANALOGUE_LEFT_MIX_0:
185 case WM8903_ANALOGUE_RIGHT_MIX_0:
186 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
187 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
188 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
189 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
190 case WM8903_ANALOGUE_OUT1_LEFT:
191 case WM8903_ANALOGUE_OUT1_RIGHT:
192 case WM8903_ANALOGUE_OUT2_LEFT:
193 case WM8903_ANALOGUE_OUT2_RIGHT:
194 case WM8903_ANALOGUE_OUT3_LEFT:
195 case WM8903_ANALOGUE_OUT3_RIGHT:
196 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
197 case WM8903_DC_SERVO_0:
198 case WM8903_DC_SERVO_2:
199 case WM8903_DC_SERVO_READBACK_1:
200 case WM8903_DC_SERVO_READBACK_2:
201 case WM8903_DC_SERVO_READBACK_3:
202 case WM8903_DC_SERVO_READBACK_4:
203 case WM8903_ANALOGUE_HP_0:
204 case WM8903_ANALOGUE_LINEOUT_0:
205 case WM8903_CHARGE_PUMP_0:
206 case WM8903_CLASS_W_0:
207 case WM8903_WRITE_SEQUENCER_0:
208 case WM8903_WRITE_SEQUENCER_1:
209 case WM8903_WRITE_SEQUENCER_2:
210 case WM8903_WRITE_SEQUENCER_3:
211 case WM8903_WRITE_SEQUENCER_4:
212 case WM8903_CONTROL_INTERFACE:
213 case WM8903_GPIO_CONTROL_1:
214 case WM8903_GPIO_CONTROL_2:
215 case WM8903_GPIO_CONTROL_3:
216 case WM8903_GPIO_CONTROL_4:
217 case WM8903_GPIO_CONTROL_5:
218 case WM8903_INTERRUPT_STATUS_1:
219 case WM8903_INTERRUPT_STATUS_1_MASK:
220 case WM8903_INTERRUPT_POLARITY_1:
221 case WM8903_INTERRUPT_CONTROL:
222 case WM8903_CLOCK_RATE_TEST_4:
223 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
224 return true;
225 default:
226 return false;
227 }
228}
229
230static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
f1c0a02f
MB		 231{
232 switch (reg) {
233 case WM8903_SW_RESET_AND_ID:
234 case WM8903_REVISION_NUMBER:
235 case WM8903_INTERRUPT_STATUS_1:
236 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 237 case WM8903_DC_SERVO_READBACK_1:
238 case WM8903_DC_SERVO_READBACK_2:
239 case WM8903_DC_SERVO_READBACK_3:
240 case WM8903_DC_SERVO_READBACK_4:
8d50e447 241 return 1;
f1c0a02f
MB		 242
243 default:
f1c0a02f 244 return 0;
8d50e447 245 }
f1c0a02f
MB		 246}
247
42768a12
MB		 248static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
249 struct snd_kcontrol *kcontrol, int event)
250{
251 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
252 mdelay(4);
253
254 return 0;
255}
256
c5b6a9fe
MB		 257static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
258 struct snd_kcontrol *kcontrol, int event)
259{
260 struct snd_soc_codec *codec = w->codec;
261 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
262
263 switch (event) {
264 case SND_SOC_DAPM_POST_PMU:
265 wm8903->dcs_pending |= 1 << w->shift;
266 break;
267 case SND_SOC_DAPM_PRE_PMD:
268 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
269 1 << w->shift, 0);
270 break;
271 }
272
273 return 0;
274}
275
276#define WM8903_DCS_MODE_WRITE_STOP 0
277#define WM8903_DCS_MODE_START_STOP 2
278
279static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
280 enum snd_soc_dapm_type event, int subseq)
281{
282 struct snd_soc_codec *codec = container_of(dapm,
283 struct snd_soc_codec, dapm);
284 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
285 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
286 int i, val;
287
288 /* Complete any pending DC servo starts */
289 if (wm8903->dcs_pending) {
290 dev_dbg(codec->dev, "Starting DC servo for %x\n",
291 wm8903->dcs_pending);
292
293 /* If we've no cached values then we need to do startup */
294 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
295 if (!(wm8903->dcs_pending & (1 << i)))
296 continue;
297
298 if (wm8903->dcs_cache[i]) {
299 dev_dbg(codec->dev,
300 "Restore DC servo %d value %x\n",
301 3 - i, wm8903->dcs_cache[i]);
302
303 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
304 wm8903->dcs_cache[i] & 0xff);
305 } else {
306 dev_dbg(codec->dev,
307 "Calibrate DC servo %d\n", 3 - i);
308 dcs_mode = WM8903_DCS_MODE_START_STOP;
309 }
310 }
311
312 /* Don't trust the cache for analogue */
313 if (wm8903->class_w_users)
314 dcs_mode = WM8903_DCS_MODE_START_STOP;
315
316 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
317 WM8903_DCS_MODE_MASK, dcs_mode);
318
319 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
320 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
321
322 switch (dcs_mode) {
323 case WM8903_DCS_MODE_WRITE_STOP:
324 break;
325
326 case WM8903_DCS_MODE_START_STOP:
327 msleep(270);
328
329 /* Cache the measured offsets for digital */
330 if (wm8903->class_w_users)
331 break;
332
333 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
334 if (!(wm8903->dcs_pending & (1 << i)))
335 continue;
336
337 val = snd_soc_read(codec,
338 WM8903_DC_SERVO_READBACK_1 + i);
339 dev_dbg(codec->dev, "DC servo %d: %x\n",
340 3 - i, val);
341 wm8903->dcs_cache[i] = val;
342 }
343 break;
344
345 default:
346 pr_warn("DCS mode %d delay not set\n", dcs_mode);
347 break;
348 }
349
350 wm8903->dcs_pending = 0;
351 }
352}
353
f1c0a02f
MB		 354/*
355 * When used with DAC outputs only the WM8903 charge pump supports
356 * operation in class W mode, providing very low power consumption
357 * when used with digital sources. Enable and disable this mode
358 * automatically depending on the mixer configuration.
359 *
360 * All the relevant controls are simple switches.
361 */
362static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_value *ucontrol)
364{
9d03545d
JN		 365 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
366 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 367 struct snd_soc_codec *codec = widget->codec;
b2c812e2 368 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 369 u16 reg;
370 int ret;
371
8d50e447 372 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 373
374 /* Turn it off if we're about to enable bypass */
375 if (ucontrol->value.integer.value[0]) {
376 if (wm8903->class_w_users == 0) {
f0fba2ad 377 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 378 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 379 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
380 }
381 wm8903->class_w_users++;
382 }
383
384 /* Implement the change */
385 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
386
387 /* If we've just disabled the last bypass path turn Class W on */
388 if (!ucontrol->value.integer.value[0]) {
389 if (wm8903->class_w_users == 1) {
f0fba2ad 390 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 391 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 392 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
393 }
394 wm8903->class_w_users--;
395 }
396
f0fba2ad 397 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 398 wm8903->class_w_users);
399
400 return ret;
401}
402
403#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
404{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
405 .info = snd_soc_info_volsw, \
406 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
407 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
408
409
69fff9bb
MB		 410static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
411
412static int wm8903_set_deemph(struct snd_soc_codec *codec)
413{
414 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
415 int val, i, best;
416
417 /* If we're using deemphasis select the nearest available sample
418 * rate.
419 */
420 if (wm8903->deemph) {
421 best = 1;
422 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
423 if (abs(wm8903_deemph[i] - wm8903->fs) <
424 abs(wm8903_deemph[best] - wm8903->fs))
425 best = i;
426 }
427
428 val = best << WM8903_DEEMPH_SHIFT;
429 } else {
430 best = 0;
431 val = 0;
432 }
433
434 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
435 best, wm8903_deemph[best]);
436
437 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
438 WM8903_DEEMPH_MASK, val);
439}
440
441static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
442 struct snd_ctl_elem_value *ucontrol)
443{
444 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
445 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
446
447 ucontrol->value.enumerated.item[0] = wm8903->deemph;
448
449 return 0;
450}
451
452static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
454{
455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
456 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
457 int deemph = ucontrol->value.enumerated.item[0];
458 int ret = 0;
459
460 if (deemph > 1)
461 return -EINVAL;
462
463 mutex_lock(&codec->mutex);
464 if (wm8903->deemph != deemph) {
465 wm8903->deemph = deemph;
466
467 wm8903_set_deemph(codec);
468
469 ret = 1;
470 }
471 mutex_unlock(&codec->mutex);
472
473 return ret;
474}
475
f1c0a02f
MB		 476/* ALSA can only do steps of .01dB */
477static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
478
291ce18c 479static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 480static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
481
482static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
483static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
484static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
485static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
486static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
487
460f4aae
MB		 488static const char *hpf_mode_text[] = {
489 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
490};
491
492static const struct soc_enum hpf_mode =
493 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
494
dcf9ada3
MB		 495static const char *osr_text[] = {
496 "Low power", "High performance"
497};
498
499static const struct soc_enum adc_osr =
500 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
501
502static const struct soc_enum dac_osr =
503 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
504
f1c0a02f
MB		 505static const char *drc_slope_text[] = {
506 "1", "1/2", "1/4", "1/8", "1/16", "0"
507};
508
509static const struct soc_enum drc_slope_r0 =
510 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
511
512static const struct soc_enum drc_slope_r1 =
513 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
514
515static const char *drc_attack_text[] = {
516 "instantaneous",
517 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
518 "46.4ms", "92.8ms", "185.6ms"
519};
520
521static const struct soc_enum drc_attack =
522 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
523
524static const char *drc_decay_text[] = {
525 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
526 "23.87s", "47.56s"
527};
528
529static const struct soc_enum drc_decay =
530 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
531
532static const char *drc_ff_delay_text[] = {
533 "5 samples", "9 samples"
534};
535
536static const struct soc_enum drc_ff_delay =
537 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
538
539static const char *drc_qr_decay_text[] = {
540 "0.725ms", "1.45ms", "5.8ms"
541};
542
543static const struct soc_enum drc_qr_decay =
544 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
545
546static const char *drc_smoothing_text[] = {
547 "Low", "Medium", "High"
548};
549
550static const struct soc_enum drc_smoothing =
551 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
552
553static const char *soft_mute_text[] = {
554 "Fast (fs/2)", "Slow (fs/32)"
555};
556
557static const struct soc_enum soft_mute =
558 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
559
560static const char *mute_mode_text[] = {
561 "Hard", "Soft"
562};
563
564static const struct soc_enum mute_mode =
565 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
566
f1c0a02f
MB		 567static const char *companding_text[] = {
568 "ulaw", "alaw"
569};
570
571static const struct soc_enum dac_companding =
572 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
573
574static const struct soc_enum adc_companding =
575 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
576
577static const char *input_mode_text[] = {
578 "Single-Ended", "Differential Line", "Differential Mic"
579};
580
581static const struct soc_enum linput_mode_enum =
582 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
583
584static const struct soc_enum rinput_mode_enum =
585 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
586
587static const char *linput_mux_text[] = {
588 "IN1L", "IN2L", "IN3L"
589};
590
591static const struct soc_enum linput_enum =
592 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
593
594static const struct soc_enum linput_inv_enum =
595 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
596
597static const char *rinput_mux_text[] = {
598 "IN1R", "IN2R", "IN3R"
599};
600
601static const struct soc_enum rinput_enum =
602 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
603
604static const struct soc_enum rinput_inv_enum =
605 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
606
607
291ce18c
MB		 608static const char *sidetone_text[] = {
609 "None", "Left", "Right"
610};
611
612static const struct soc_enum lsidetone_enum =
613 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
614
615static const struct soc_enum rsidetone_enum =
616 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
617
97945c46
SW		 618static const char *adcinput_text[] = {
619 "ADC", "DMIC"
620};
621
622static const struct soc_enum adcinput_enum =
623 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
624
1e113bf9
MB		 625static const char *aif_text[] = {
626 "Left", "Right"
627};
628
629static const struct soc_enum lcapture_enum =
630 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
631
632static const struct soc_enum rcapture_enum =
633 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
634
635static const struct soc_enum lplay_enum =
636 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
637
638static const struct soc_enum rplay_enum =
639 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
640
f1c0a02f
MB		 641static const struct snd_kcontrol_new wm8903_snd_controls[] = {
642
643/* Input PGAs - No TLV since the scale depends on PGA mode */
644SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 645 7, 1, 1),
f1c0a02f
MB		 646SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
647 0, 31, 0),
648SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
649 6, 1, 0),
650
651SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 652 7, 1, 1),
f1c0a02f
MB		 653SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
654 0, 31, 0),
655SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
656 6, 1, 0),
657
658/* ADCs */
dcf9ada3 659SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 660SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
661SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 662SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
663SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
664SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 665SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 666 drc_tlv_thresh),
667SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
668SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
669SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
670SOC_ENUM("DRC Attack Rate", drc_attack),
671SOC_ENUM("DRC Decay Rate", drc_decay),
672SOC_ENUM("DRC FF Delay", drc_ff_delay),
673SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
674SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 675SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 676SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
677SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
678SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 679SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 680SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
681
682SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 683 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 684SOC_ENUM("ADC Companding Mode", adc_companding),
685SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
686
291ce18c
MB		 687SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
688 12, 0, digital_sidetone_tlv),
689
f1c0a02f 690/* DAC */
dcf9ada3 691SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 692SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
693 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
694SOC_ENUM("DAC Soft Mute Rate", soft_mute),
695SOC_ENUM("DAC Mute Mode", mute_mode),
696SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 697SOC_ENUM("DAC Companding Mode", dac_companding),
698SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 699SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
700 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 701
702/* Headphones */
703SOC_DOUBLE_R("Headphone Switch",
704 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
705 8, 1, 1),
706SOC_DOUBLE_R("Headphone ZC Switch",
707 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
708 6, 1, 0),
709SOC_DOUBLE_R_TLV("Headphone Volume",
710 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
711 0, 63, 0, out_tlv),
712
713/* Line out */
714SOC_DOUBLE_R("Line Out Switch",
715 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
716 8, 1, 1),
717SOC_DOUBLE_R("Line Out ZC Switch",
718 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
719 6, 1, 0),
720SOC_DOUBLE_R_TLV("Line Out Volume",
721 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
722 0, 63, 0, out_tlv),
723
724/* Speaker */
725SOC_DOUBLE_R("Speaker Switch",
726 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
727SOC_DOUBLE_R("Speaker ZC Switch",
728 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
729SOC_DOUBLE_R_TLV("Speaker Volume",
730 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
731 0, 63, 0, out_tlv),
732};
733
f1c0a02f
MB		 734static const struct snd_kcontrol_new linput_mode_mux =
735 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
736
737static const struct snd_kcontrol_new rinput_mode_mux =
738 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
739
740static const struct snd_kcontrol_new linput_mux =
741 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
742
743static const struct snd_kcontrol_new linput_inv_mux =
744 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
745
746static const struct snd_kcontrol_new rinput_mux =
747 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
748
749static const struct snd_kcontrol_new rinput_inv_mux =
750 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
751
291ce18c
MB		 752static const struct snd_kcontrol_new lsidetone_mux =
753 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
754
755static const struct snd_kcontrol_new rsidetone_mux =
756 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
757
97945c46
SW		 758static const struct snd_kcontrol_new adcinput_mux =
759 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
760
1e113bf9
MB		 761static const struct snd_kcontrol_new lcapture_mux =
762 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
763
764static const struct snd_kcontrol_new rcapture_mux =
765 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
766
767static const struct snd_kcontrol_new lplay_mux =
768 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
769
770static const struct snd_kcontrol_new rplay_mux =
771 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
772
f1c0a02f
MB		 773static const struct snd_kcontrol_new left_output_mixer[] = {
774SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
775SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
776SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 777SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 778};
779
780static const struct snd_kcontrol_new right_output_mixer[] = {
781SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
782SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
783SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 784SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 785};
786
787static const struct snd_kcontrol_new left_speaker_mixer[] = {
788SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
789SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
790SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
791SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 792 0, 1, 0),
f1c0a02f
MB		 793};
794
795static const struct snd_kcontrol_new right_speaker_mixer[] = {
796SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
797SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
798SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
799 1, 1, 0),
800SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 801 0, 1, 0),
f1c0a02f
MB		 802};
803
804static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
805SND_SOC_DAPM_INPUT("IN1L"),
806SND_SOC_DAPM_INPUT("IN1R"),
807SND_SOC_DAPM_INPUT("IN2L"),
808SND_SOC_DAPM_INPUT("IN2R"),
809SND_SOC_DAPM_INPUT("IN3L"),
810SND_SOC_DAPM_INPUT("IN3R"),
97945c46 811SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 812
813SND_SOC_DAPM_OUTPUT("HPOUTL"),
814SND_SOC_DAPM_OUTPUT("HPOUTR"),
815SND_SOC_DAPM_OUTPUT("LINEOUTL"),
816SND_SOC_DAPM_OUTPUT("LINEOUTR"),
817SND_SOC_DAPM_OUTPUT("LOP"),
818SND_SOC_DAPM_OUTPUT("LON"),
819SND_SOC_DAPM_OUTPUT("ROP"),
820SND_SOC_DAPM_OUTPUT("RON"),
821
5032dc34 822SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 823
824SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
825SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
826 &linput_inv_mux),
827SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
828
829SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
830SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
831 &rinput_inv_mux),
832SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
833
834SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
835SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
836
97945c46
SW		 837SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
838SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
839
1e113bf9
MB		 840SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
841SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
842
843SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
844SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
845
846SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
847SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 848
291ce18c
MB		 849SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
850SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
851
1e113bf9
MB		 852SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
853SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
854
855SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
856SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
857
858SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
859SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 860
861SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
862 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
863SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
864 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
865
866SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
867 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
868SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
869 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
870
1b877cb5
DL		 871SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
872 1, 0, NULL, 0),
873SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 874 0, 0, NULL, 0),
875
1b877cb5 876SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 877 NULL, 0),
1b877cb5 878SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 879 NULL, 0),
880
881SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
882SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 883SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
884SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 885SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
886SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 887SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
888SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 889
890SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
891 NULL, 0),
892SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
893 NULL, 0),
1b877cb5
DL		 894SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
895 NULL, 0),
896SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 897 NULL, 0),
898SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
899 NULL, 0),
900SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
901 NULL, 0),
1b877cb5
DL		 902SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
903 NULL, 0),
904SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 905 NULL, 0),
906
c5b6a9fe
MB		 907SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
908SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
909 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
910SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
911 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
912SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
913 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
914SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
915 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 916
917SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
918 NULL, 0),
919SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
920 NULL, 0),
921
42768a12
MB		 922SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
923 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 924SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 925SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 926};
927
ecd01512 928static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 929
2c8be5a2 930 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 931 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 932 { "HPL_DCS", NULL, "CLK_SYS" },
933 { "HPR_DCS", NULL, "CLK_SYS" },
934 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
935 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
936
f1c0a02f
MB		 937 { "Left Input Mux", "IN1L", "IN1L" },
938 { "Left Input Mux", "IN2L", "IN2L" },
939 { "Left Input Mux", "IN3L", "IN3L" },
940
941 { "Left Input Inverting Mux", "IN1L", "IN1L" },
942 { "Left Input Inverting Mux", "IN2L", "IN2L" },
943 { "Left Input Inverting Mux", "IN3L", "IN3L" },
944
945 { "Right Input Mux", "IN1R", "IN1R" },
946 { "Right Input Mux", "IN2R", "IN2R" },
947 { "Right Input Mux", "IN3R", "IN3R" },
948
949 { "Right Input Inverting Mux", "IN1R", "IN1R" },
950 { "Right Input Inverting Mux", "IN2R", "IN2R" },
951 { "Right Input Inverting Mux", "IN3R", "IN3R" },
952
953 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
954 { "Left Input Mode Mux", "Differential Line",
955 "Left Input Mux" },
956 { "Left Input Mode Mux", "Differential Line",
957 "Left Input Inverting Mux" },
958 { "Left Input Mode Mux", "Differential Mic",
959 "Left Input Mux" },
960 { "Left Input Mode Mux", "Differential Mic",
961 "Left Input Inverting Mux" },
962
963 { "Right Input Mode Mux", "Single-Ended",
964 "Right Input Inverting Mux" },
965 { "Right Input Mode Mux", "Differential Line",
966 "Right Input Mux" },
967 { "Right Input Mode Mux", "Differential Line",
968 "Right Input Inverting Mux" },
969 { "Right Input Mode Mux", "Differential Mic",
970 "Right Input Mux" },
971 { "Right Input Mode Mux", "Differential Mic",
972 "Right Input Inverting Mux" },
973
974 { "Left Input PGA", NULL, "Left Input Mode Mux" },
975 { "Right Input PGA", NULL, "Right Input Mode Mux" },
976
97945c46
SW		 977 { "Left ADC Input", "ADC", "Left Input PGA" },
978 { "Left ADC Input", "DMIC", "DMICDAT" },
979 { "Right ADC Input", "ADC", "Right Input PGA" },
980 { "Right ADC Input", "DMIC", "DMICDAT" },
981
1e113bf9
MB		 982 { "Left Capture Mux", "Left", "ADCL" },
983 { "Left Capture Mux", "Right", "ADCR" },
984
985 { "Right Capture Mux", "Left", "ADCL" },
986 { "Right Capture Mux", "Right", "ADCR" },
987
988 { "AIFTXL", NULL, "Left Capture Mux" },
989 { "AIFTXR", NULL, "Right Capture Mux" },
990
97945c46 991 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 992 { "ADCL", NULL, "CLK_DSP" },
97945c46 993 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 994 { "ADCR", NULL, "CLK_DSP" },
995
1e113bf9
MB		 996 { "Left Playback Mux", "Left", "AIFRXL" },
997 { "Left Playback Mux", "Right", "AIFRXR" },
998
999 { "Right Playback Mux", "Left", "AIFRXL" },
1000 { "Right Playback Mux", "Right", "AIFRXR" },
1001
291ce18c
MB		 1002 { "DACL Sidetone", "Left", "ADCL" },
1003 { "DACL Sidetone", "Right", "ADCR" },
1004 { "DACR Sidetone", "Left", "ADCL" },
1005 { "DACR Sidetone", "Right", "ADCR" },
1006
1e113bf9 1007 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1008 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1009 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1010
1011 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1012 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1013 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1014
1015 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1016 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1017 { "Left Output Mixer", "DACL Switch", "DACL" },
1018 { "Left Output Mixer", "DACR Switch", "DACR" },
1019
1020 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1021 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1022 { "Right Output Mixer", "DACL Switch", "DACL" },
1023 { "Right Output Mixer", "DACR Switch", "DACR" },
1024
1025 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1026 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1027 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1028 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1029
1030 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1031 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1032 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1033 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1034
1035 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1036 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1037
1038 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1039 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1040
1041 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1042 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1043
1b877cb5
DL		 1044 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1045 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1046 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1047 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1048 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1049 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1050 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1051 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1052
c5b6a9fe
MB		 1053 { "HPL_DCS", NULL, "DCS Master" },
1054 { "HPR_DCS", NULL, "DCS Master" },
1055 { "LINEOUTL_DCS", NULL, "DCS Master" },
1056 { "LINEOUTR_DCS", NULL, "DCS Master" },
1057
13a9983e
MB		 1058 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1059 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1060 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1061 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1062
1063 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1064 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1065 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1066 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1067
1068 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1069 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1070 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1071 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1072
1073 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1074 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1075 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1076 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1077
1078 { "LOP", NULL, "Left Speaker PGA" },
1079 { "LON", NULL, "Left Speaker PGA" },
1080
1081 { "ROP", NULL, "Right Speaker PGA" },
1082 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1083
1084 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1085 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1086 { "Left Line Output PGA", NULL, "Charge Pump" },
1087 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1088};
1089
f1c0a02f
MB		 1090static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1091 enum snd_soc_bias_level level)
1092{
f1c0a02f
MB		 1093 switch (level) {
1094 case SND_SOC_BIAS_ON:
66daaa59 1095 break;
22f226dd 1096
f1c0a02f 1097 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1098 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1099 WM8903_VMID_RES_MASK,
1100 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1101 break;
1102
1103 case SND_SOC_BIAS_STANDBY:
ce6120cc 1104 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1105 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1106 WM8903_POBCTRL | WM8903_ISEL_MASK |
1107 WM8903_STARTUP_BIAS_ENA |
1108 WM8903_BIAS_ENA,
1109 WM8903_POBCTRL |
1110 (2 << WM8903_ISEL_SHIFT) |
1111 WM8903_STARTUP_BIAS_ENA);
1112
1113 snd_soc_update_bits(codec,
1114 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1115 WM8903_SPK_DISCHARGE,
1116 WM8903_SPK_DISCHARGE);
1117
1118 msleep(33);
1119
1120 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1121 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1122 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1123
1124 snd_soc_update_bits(codec,
1125 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1126 WM8903_SPK_DISCHARGE, 0);
1127
1128 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1129 WM8903_VMID_TIE_ENA |
1130 WM8903_BUFIO_ENA |
1131 WM8903_VMID_IO_ENA |
1132 WM8903_VMID_SOFT_MASK |
1133 WM8903_VMID_RES_MASK |
1134 WM8903_VMID_BUF_ENA,
1135 WM8903_VMID_TIE_ENA |
1136 WM8903_BUFIO_ENA |
1137 WM8903_VMID_IO_ENA |
1138 (2 << WM8903_VMID_SOFT_SHIFT) |
1139 WM8903_VMID_RES_250K |
1140 WM8903_VMID_BUF_ENA);
1141
1142 msleep(129);
1143
1144 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1145 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1146 0);
1147
1148 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1149 WM8903_VMID_SOFT_MASK, 0);
1150
1151 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1152 WM8903_VMID_RES_MASK,
1153 WM8903_VMID_RES_50K);
1154
1155 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1156 WM8903_BIAS_ENA | WM8903_POBCTRL,
1157 WM8903_BIAS_ENA);
f1c0a02f 1158
f1c0a02f
MB		 1159 /* By default no bypass paths are enabled so
1160 * enable Class W support.
1161 */
f0fba2ad 1162 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1163 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1164 WM8903_CP_DYN_FREQ |
1165 WM8903_CP_DYN_V,
1166 WM8903_CP_DYN_FREQ |
1167 WM8903_CP_DYN_V);
f1c0a02f
MB		 1168 }
1169
66daaa59
MB		 1170 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1171 WM8903_VMID_RES_MASK,
1172 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1173 break;
1174
1175 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1176 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1177 WM8903_BIAS_ENA, 0);
1178
1179 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1180 WM8903_VMID_SOFT_MASK,
1181 2 << WM8903_VMID_SOFT_SHIFT);
1182
1183 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1184 WM8903_VMID_BUF_ENA, 0);
1185
1186 msleep(290);
1187
1188 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1189 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1190 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1191 WM8903_VMID_SOFT_MASK |
1192 WM8903_VMID_BUF_ENA, 0);
1193
1194 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1195 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1196 break;
1197 }
1198
ce6120cc 1199 codec->dapm.bias_level = level;
f1c0a02f
MB		 1200
1201 return 0;
1202}
1203
1204static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1205 int clk_id, unsigned int freq, int dir)
1206{
1207 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1208 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1209
1210 wm8903->sysclk = freq;
1211
1212 return 0;
1213}
1214
1215static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1216 unsigned int fmt)
1217{
1218 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1219 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1220
1221 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1222 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1223
1224 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1225 case SND_SOC_DAIFMT_CBS_CFS:
1226 break;
1227 case SND_SOC_DAIFMT_CBS_CFM:
1228 aif1 |= WM8903_LRCLK_DIR;
1229 break;
1230 case SND_SOC_DAIFMT_CBM_CFM:
1231 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1232 break;
1233 case SND_SOC_DAIFMT_CBM_CFS:
1234 aif1 |= WM8903_BCLK_DIR;
1235 break;
1236 default:
1237 return -EINVAL;
1238 }
1239
1240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1241 case SND_SOC_DAIFMT_DSP_A:
1242 aif1 |= 0x3;
1243 break;
1244 case SND_SOC_DAIFMT_DSP_B:
1245 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1246 break;
1247 case SND_SOC_DAIFMT_I2S:
1248 aif1 |= 0x2;
1249 break;
1250 case SND_SOC_DAIFMT_RIGHT_J:
1251 aif1 |= 0x1;
1252 break;
1253 case SND_SOC_DAIFMT_LEFT_J:
1254 break;
1255 default:
1256 return -EINVAL;
1257 }
1258
1259 /* Clock inversion */
1260 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1261 case SND_SOC_DAIFMT_DSP_A:
1262 case SND_SOC_DAIFMT_DSP_B:
1263 /* frame inversion not valid for DSP modes */
1264 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1265 case SND_SOC_DAIFMT_NB_NF:
1266 break;
1267 case SND_SOC_DAIFMT_IB_NF:
1268 aif1 |= WM8903_AIF_BCLK_INV;
1269 break;
1270 default:
1271 return -EINVAL;
1272 }
1273 break;
1274 case SND_SOC_DAIFMT_I2S:
1275 case SND_SOC_DAIFMT_RIGHT_J:
1276 case SND_SOC_DAIFMT_LEFT_J:
1277 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1278 case SND_SOC_DAIFMT_NB_NF:
1279 break;
1280 case SND_SOC_DAIFMT_IB_IF:
1281 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1282 break;
1283 case SND_SOC_DAIFMT_IB_NF:
1284 aif1 |= WM8903_AIF_BCLK_INV;
1285 break;
1286 case SND_SOC_DAIFMT_NB_IF:
1287 aif1 |= WM8903_AIF_LRCLK_INV;
1288 break;
1289 default:
1290 return -EINVAL;
1291 }
1292 break;
1293 default:
1294 return -EINVAL;
1295 }
1296
8d50e447 1297 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1298
1299 return 0;
1300}
1301
1302static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1303{
1304 struct snd_soc_codec *codec = codec_dai->codec;
1305 u16 reg;
1306
8d50e447 1307 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1308
1309 if (mute)
1310 reg |= WM8903_DAC_MUTE;
1311 else
1312 reg &= ~WM8903_DAC_MUTE;
1313
8d50e447 1314 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1315
1316 return 0;
1317}
1318
1319/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1320 * for optimal performance so we list the lower rates first and match
1321 * on the last match we find. */
1322static struct {
1323 int div;
1324 int rate;
1325 int mode;
1326 int mclk_div;
1327} clk_sys_ratios[] = {
1328 { 64, 0x0, 0x0, 1 },
1329 { 68, 0x0, 0x1, 1 },
1330 { 125, 0x0, 0x2, 1 },
1331 { 128, 0x1, 0x0, 1 },
1332 { 136, 0x1, 0x1, 1 },
1333 { 192, 0x2, 0x0, 1 },
1334 { 204, 0x2, 0x1, 1 },
1335
1336 { 64, 0x0, 0x0, 2 },
1337 { 68, 0x0, 0x1, 2 },
1338 { 125, 0x0, 0x2, 2 },
1339 { 128, 0x1, 0x0, 2 },
1340 { 136, 0x1, 0x1, 2 },
1341 { 192, 0x2, 0x0, 2 },
1342 { 204, 0x2, 0x1, 2 },
1343
1344 { 250, 0x2, 0x2, 1 },
1345 { 256, 0x3, 0x0, 1 },
1346 { 272, 0x3, 0x1, 1 },
1347 { 384, 0x4, 0x0, 1 },
1348 { 408, 0x4, 0x1, 1 },
1349 { 375, 0x4, 0x2, 1 },
1350 { 512, 0x5, 0x0, 1 },
1351 { 544, 0x5, 0x1, 1 },
1352 { 500, 0x5, 0x2, 1 },
1353 { 768, 0x6, 0x0, 1 },
1354 { 816, 0x6, 0x1, 1 },
1355 { 750, 0x6, 0x2, 1 },
1356 { 1024, 0x7, 0x0, 1 },
1357 { 1088, 0x7, 0x1, 1 },
1358 { 1000, 0x7, 0x2, 1 },
1359 { 1408, 0x8, 0x0, 1 },
1360 { 1496, 0x8, 0x1, 1 },
1361 { 1536, 0x9, 0x0, 1 },
1362 { 1632, 0x9, 0x1, 1 },
1363 { 1500, 0x9, 0x2, 1 },
1364
1365 { 250, 0x2, 0x2, 2 },
1366 { 256, 0x3, 0x0, 2 },
1367 { 272, 0x3, 0x1, 2 },
1368 { 384, 0x4, 0x0, 2 },
1369 { 408, 0x4, 0x1, 2 },
1370 { 375, 0x4, 0x2, 2 },
1371 { 512, 0x5, 0x0, 2 },
1372 { 544, 0x5, 0x1, 2 },
1373 { 500, 0x5, 0x2, 2 },
1374 { 768, 0x6, 0x0, 2 },
1375 { 816, 0x6, 0x1, 2 },
1376 { 750, 0x6, 0x2, 2 },
1377 { 1024, 0x7, 0x0, 2 },
1378 { 1088, 0x7, 0x1, 2 },
1379 { 1000, 0x7, 0x2, 2 },
1380 { 1408, 0x8, 0x0, 2 },
1381 { 1496, 0x8, 0x1, 2 },
1382 { 1536, 0x9, 0x0, 2 },
1383 { 1632, 0x9, 0x1, 2 },
1384 { 1500, 0x9, 0x2, 2 },
1385};
1386
1387/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1388static struct {
1389 int ratio;
1390 int div;
1391} bclk_divs[] = {
1392 { 10, 0 },
f1c0a02f
MB		 1393 { 20, 2 },
1394 { 30, 3 },
1395 { 40, 4 },
1396 { 50, 5 },
f1c0a02f
MB		 1397 { 60, 7 },
1398 { 80, 8 },
1399 { 100, 9 },
f1c0a02f
MB		 1400 { 120, 11 },
1401 { 160, 12 },
1402 { 200, 13 },
1403 { 220, 14 },
1404 { 240, 15 },
f1c0a02f
MB		 1405 { 300, 17 },
1406 { 320, 18 },
1407 { 440, 19 },
1408 { 480, 20 },
1409};
1410
1411/* Sample rates for DSP */
1412static struct {
1413 int rate;
1414 int value;
1415} sample_rates[] = {
1416 { 8000, 0 },
1417 { 11025, 1 },
1418 { 12000, 2 },
1419 { 16000, 3 },
1420 { 22050, 4 },
1421 { 24000, 5 },
1422 { 32000, 6 },
1423 { 44100, 7 },
1424 { 48000, 8 },
1425 { 88200, 9 },
1426 { 96000, 10 },
1427 { 0, 0 },
1428};
1429
f1c0a02f 1430static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1431 struct snd_pcm_hw_params *params,
1432 struct snd_soc_dai *dai)
f1c0a02f
MB		 1433{
1434 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1435 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1436 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1437 int fs = params_rate(params);
1438 int bclk;
1439 int bclk_div;
1440 int i;
1441 int dsp_config;
1442 int clk_config;
1443 int best_val;
1444 int cur_val;
1445 int clk_sys;
1446
8d50e447
MB		 1447 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1448 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1449 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1450 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1451 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1452 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1453
9e79261f
MB		 1454 /* Enable sloping stopband filter for low sample rates */
1455 if (fs <= 24000)
1456 dac_digital1 |= WM8903_DAC_SB_FILT;
1457 else
1458 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1459
f1c0a02f
MB		 1460 /* Configure sample rate logic for DSP - choose nearest rate */
1461 dsp_config = 0;
1462 best_val = abs(sample_rates[dsp_config].rate - fs);
1463 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1464 cur_val = abs(sample_rates[i].rate - fs);
1465 if (cur_val <= best_val) {
1466 dsp_config = i;
1467 best_val = cur_val;
1468 }
1469 }
1470
f0fba2ad 1471 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1472 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1473 clock1 |= sample_rates[dsp_config].value;
1474
1475 aif1 &= ~WM8903_AIF_WL_MASK;
1476 bclk = 2 * fs;
1477 switch (params_format(params)) {
1478 case SNDRV_PCM_FORMAT_S16_LE:
1479 bclk *= 16;
1480 break;
1481 case SNDRV_PCM_FORMAT_S20_3LE:
1482 bclk *= 20;
1483 aif1 |= 0x4;
1484 break;
1485 case SNDRV_PCM_FORMAT_S24_LE:
1486 bclk *= 24;
1487 aif1 |= 0x8;
1488 break;
1489 case SNDRV_PCM_FORMAT_S32_LE:
1490 bclk *= 32;
1491 aif1 |= 0xc;
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496
f0fba2ad 1497 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1498 wm8903->sysclk, fs);
1499
1500 /* We may not have an MCLK which allows us to generate exactly
1501 * the clock we want, particularly with USB derived inputs, so
1502 * approximate.
1503 */
1504 clk_config = 0;
1505 best_val = abs((wm8903->sysclk /
1506 (clk_sys_ratios[0].mclk_div *
1507 clk_sys_ratios[0].div)) - fs);
1508 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1509 cur_val = abs((wm8903->sysclk /
1510 (clk_sys_ratios[i].mclk_div *
1511 clk_sys_ratios[i].div)) - fs);
1512
1513 if (cur_val <= best_val) {
1514 clk_config = i;
1515 best_val = cur_val;
1516 }
1517 }
1518
1519 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1520 clock0 |= WM8903_MCLKDIV2;
1521 clk_sys = wm8903->sysclk / 2;
1522 } else {
1523 clock0 &= ~WM8903_MCLKDIV2;
1524 clk_sys = wm8903->sysclk;
1525 }
1526
1527 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1528 WM8903_CLK_SYS_MODE_MASK);
1529 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1530 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1531
f0fba2ad 1532 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1533 clk_sys_ratios[clk_config].rate,
1534 clk_sys_ratios[clk_config].mode,
1535 clk_sys_ratios[clk_config].div);
1536
f0fba2ad 1537 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1538
1539 /* We may not get quite the right frequency if using
1540 * approximate clocks so look for the closest match that is
1541 * higher than the target (we need to ensure that there enough
1542 * BCLKs to clock out the samples).
1543 */
1544 bclk_div = 0;
1545 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1546 i = 1;
1547 while (i < ARRAY_SIZE(bclk_divs)) {
1548 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1549 if (cur_val < 0) /* BCLK table is sorted */
1550 break;
1551 bclk_div = i;
1552 best_val = cur_val;
1553 i++;
1554 }
1555
1556 aif2 &= ~WM8903_BCLK_DIV_MASK;
1557 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1558
f0fba2ad 1559 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1560 bclk_divs[bclk_div].ratio / 10, bclk,
1561 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1562
1563 aif2 |= bclk_divs[bclk_div].div;
1564 aif3 |= bclk / fs;
1565
69fff9bb
MB		 1566 wm8903->fs = params_rate(params);
1567 wm8903_set_deemph(codec);
1568
8d50e447
MB		 1569 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1570 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1571 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1572 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1573 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1574 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1575
1576 return 0;
1577}
1578
7245387e
MB		 1579/**
1580 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1581 *
1582 * @codec: WM8903 codec
1583 * @jack: jack to report detection events on
1584 * @det: value to report for presence detection
1585 * @shrt: value to report for short detection
1586 *
1587 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1588 * being used to bring out signals to the processor then only platform
1589 * data configuration is needed for WM8903 and processor GPIOs should
1590 * be configured using snd_soc_jack_add_gpios() instead.
1591 *
1592 * The current threasholds for detection should be configured using
1593 * micdet_cfg in the platform data. Using this function will force on
1594 * the microphone bias for the device.
1595 */
1596int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1597 int det, int shrt)
1598{
b2c812e2 1599 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1600 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1601
1602 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1603 det, shrt);
1604
1605 /* Store the configuration */
1606 wm8903->mic_jack = jack;
1607 wm8903->mic_det = det;
1608 wm8903->mic_short = shrt;
1609
1610 /* Enable interrupts we've got a report configured for */
1611 if (det)
1612 irq_mask &= ~WM8903_MICDET_EINT;
1613 if (shrt)
1614 irq_mask &= ~WM8903_MICSHRT_EINT;
1615
1616 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1617 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1618 irq_mask);
1619
3088e3b4 1620 if (det || shrt) {
69266866
MB		 1621 /* Enable mic detection, this may not have been set through
1622 * platform data (eg, if the defaults are OK). */
1623 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1624 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1625 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1626 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1627 } else {
1628 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1629 WM8903_MICDET_ENA, 0);
1630 }
7245387e
MB		 1631
1632 return 0;
1633}
1634EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1635
8abd16a6
MB		 1636static irqreturn_t wm8903_irq(int irq, void *data)
1637{
f0fba2ad
LG		 1638 struct snd_soc_codec *codec = data;
1639 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1640 int mic_report;
1641 int int_pol;
1642 int int_val = 0;
1643 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1644
7245387e 1645 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1646
7245387e 1647 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1648 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1649 }
1650
7245387e
MB		 1651 /*
1652 * The rest is microphone jack detection. We need to manually
1653 * invert the polarity of the interrupt after each event - to
1654 * simplify the code keep track of the last state we reported
1655 * and just invert the relevant bits in both the report and
1656 * the polarity register.
1657 */
1658 mic_report = wm8903->mic_last_report;
1659 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1660
1435b940 1661#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1662 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1663 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1664#endif
2bbb5d66 1665
7245387e
MB		 1666 if (int_val & WM8903_MICSHRT_EINT) {
1667 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1668
1669 mic_report ^= wm8903->mic_short;
1670 int_pol ^= WM8903_MICSHRT_INV;
1671 }
1672
1673 if (int_val & WM8903_MICDET_EINT) {
1674 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1675
1676 mic_report ^= wm8903->mic_det;
1677 int_pol ^= WM8903_MICDET_INV;
1678
1679 msleep(wm8903->mic_delay);
1680 }
1681
1682 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1683 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1684
1685 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1686 wm8903->mic_short | wm8903->mic_det);
1687
1688 wm8903->mic_last_report = mic_report;
1689
8abd16a6
MB		 1690 return IRQ_HANDLED;
1691}
1692
f1c0a02f
MB		 1693#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1694 SNDRV_PCM_RATE_11025 | \
1695 SNDRV_PCM_RATE_16000 | \
1696 SNDRV_PCM_RATE_22050 | \
1697 SNDRV_PCM_RATE_32000 | \
1698 SNDRV_PCM_RATE_44100 | \
1699 SNDRV_PCM_RATE_48000 | \
1700 SNDRV_PCM_RATE_88200 | \
1701 SNDRV_PCM_RATE_96000)
1702
1703#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1704 SNDRV_PCM_RATE_11025 | \
1705 SNDRV_PCM_RATE_16000 | \
1706 SNDRV_PCM_RATE_22050 | \
1707 SNDRV_PCM_RATE_32000 | \
1708 SNDRV_PCM_RATE_44100 | \
1709 SNDRV_PCM_RATE_48000)
1710
1711#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1712 SNDRV_PCM_FMTBIT_S20_3LE |\
1713 SNDRV_PCM_FMTBIT_S24_LE)
1714
85e7652d 1715static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1716 .hw_params = wm8903_hw_params,
1717 .digital_mute = wm8903_digital_mute,
1718 .set_fmt = wm8903_set_dai_fmt,
1719 .set_sysclk = wm8903_set_dai_sysclk,
1720};
1721
f0fba2ad
LG		 1722static struct snd_soc_dai_driver wm8903_dai = {
1723 .name = "wm8903-hifi",
f1c0a02f
MB		 1724 .playback = {
1725 .stream_name = "Playback",
1726 .channels_min = 2,
1727 .channels_max = 2,
1728 .rates = WM8903_PLAYBACK_RATES,
1729 .formats = WM8903_FORMATS,
1730 },
1731 .capture = {
1732 .stream_name = "Capture",
1733 .channels_min = 2,
1734 .channels_max = 2,
1735 .rates = WM8903_CAPTURE_RATES,
1736 .formats = WM8903_FORMATS,
1737 },
6335d055 1738 .ops = &wm8903_dai_ops,
0d960e88 1739 .symmetric_rates = 1,
f1c0a02f 1740};
f1c0a02f 1741
84b315ee 1742static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1743{
f1c0a02f
MB		 1744 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1745
1746 return 0;
1747}
1748
f0fba2ad 1749static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1750{
45e96755 1751 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1752
ee244ce4 1753 regcache_sync(wm8903->regmap);
f1c0a02f 1754
45e96755 1755 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1756
1757 return 0;
1758}
1759
7cfe5617
SW		 1760#ifdef CONFIG_GPIOLIB
1761static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1762{
1763 return container_of(chip, struct wm8903_priv, gpio_chip);
1764}
1765
1766static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1767{
1768 if (offset >= WM8903_NUM_GPIO)
1769 return -EINVAL;
1770
1771 return 0;
1772}
1773
1774static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1775{
1776 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1777 struct snd_soc_codec *codec = wm8903->codec;
1778 unsigned int mask, val;
1779
1780 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1781 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1782 WM8903_GP1_DIR;
1783
1784 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1785 mask, val);
1786}
1787
1788static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1789{
1790 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1791 struct snd_soc_codec *codec = wm8903->codec;
1792 int reg;
1793
1794 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1795
1796 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1797}
1798
1799static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1800 unsigned offset, int value)
1801{
1802 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1803 struct snd_soc_codec *codec = wm8903->codec;
1804 unsigned int mask, val;
1805
1806 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1807 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1808 (value << WM8903_GP2_LVL_SHIFT);
1809
1810 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1811 mask, val);
1812}
1813
1814static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1815{
1816 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1817 struct snd_soc_codec *codec = wm8903->codec;
1818
1819 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1820 WM8903_GP1_LVL_MASK,
1821 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1822}
1823
1824static struct gpio_chip wm8903_template_chip = {
1825 .label = "wm8903",
1826 .owner = THIS_MODULE,
1827 .request = wm8903_gpio_request,
1828 .direction_input = wm8903_gpio_direction_in,
1829 .get = wm8903_gpio_get,
1830 .direction_output = wm8903_gpio_direction_out,
1831 .set = wm8903_gpio_set,
1832 .can_sleep = 1,
1833};
1834
1835static void wm8903_init_gpio(struct snd_soc_codec *codec)
1836{
1837 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
c0eb27cf 1838 struct wm8903_platform_data *pdata = wm8903->pdata;
7cfe5617
SW		 1839 int ret;
1840
1841 wm8903->gpio_chip = wm8903_template_chip;
1842 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1843 wm8903->gpio_chip.dev = codec->dev;
1844
db817784 1845 if (pdata->gpio_base)
7cfe5617
SW		 1846 wm8903->gpio_chip.base = pdata->gpio_base;
1847 else
1848 wm8903->gpio_chip.base = -1;
1849
1850 ret = gpiochip_add(&wm8903->gpio_chip);
1851 if (ret != 0)
1852 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1853}
1854
1855static void wm8903_free_gpio(struct snd_soc_codec *codec)
1856{
1857 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1858 int ret;
1859
1860 ret = gpiochip_remove(&wm8903->gpio_chip);
1861 if (ret != 0)
1862 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1863}
1864#else
1865static void wm8903_init_gpio(struct snd_soc_codec *codec)
1866{
1867}
1868
1869static void wm8903_free_gpio(struct snd_soc_codec *codec)
1870{
1871}
1872#endif
1873
f0fba2ad 1874static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1875{
f0fba2ad 1876 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
c0eb27cf 1877 struct wm8903_platform_data *pdata = wm8903->pdata;
73b34ead 1878 int ret, i;
8abd16a6 1879 int trigger, irq_pol;
f1c0a02f 1880 u16 val;
db817784 1881 bool mic_gpio = false;
f1c0a02f 1882
7cfe5617 1883 wm8903->codec = codec;
ee244ce4 1884 codec->control_data = wm8903->regmap;
d58d5d55 1885
ee244ce4 1886 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
8d50e447 1887 if (ret != 0) {
f0fba2ad
LG		 1888 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1889 return ret;
8d50e447
MB		 1890 }
1891
db817784
SW		 1892 /* Set up GPIOs, detect if any are MIC detect outputs */
1893 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1894 if ((!pdata->gpio_cfg[i]) ||
1895 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
1896 continue;
905f6952 1897
db817784
SW		 1898 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1899 pdata->gpio_cfg[i] & 0x7fff);
905f6952 1900
db817784
SW		 1901 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1902 >> WM8903_GP1_FN_SHIFT;
905f6952 1903
db817784
SW		 1904 switch (val) {
1905 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1906 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1907 mic_gpio = true;
1908 break;
1909 default:
1910 break;
73b34ead 1911 }
db817784
SW		 1912 }
1913
1914 /* Set up microphone detection */
1915 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1916 pdata->micdet_cfg);
37f88e84 1917
db817784
SW		 1918 /* Microphone detection needs the WSEQ clock */
1919 if (pdata->micdet_cfg)
1920 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1921 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
37f88e84 1922
db817784
SW		 1923 /* If microphone detection is enabled by pdata but
1924 * detected via IRQ then interrupts can be lost before
1925 * the machine driver has set up microphone detection
1926 * IRQs as the IRQs are clear on read. The detection
1927 * will be enabled when the machine driver configures.
1928 */
1929 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
37f88e84 1930
db817784 1931 wm8903->mic_delay = pdata->micdet_delay;
905f6952 1932
f0fba2ad 1933 if (wm8903->irq) {
db817784 1934 if (pdata->irq_active_low) {
8abd16a6
MB		 1935 trigger = IRQF_TRIGGER_LOW;
1936 irq_pol = WM8903_IRQ_POL;
1937 } else {
1938 trigger = IRQF_TRIGGER_HIGH;
1939 irq_pol = 0;
1940 }
1941
1942 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1943 WM8903_IRQ_POL, irq_pol);
1944
f0fba2ad 1945 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1946 trigger | IRQF_ONESHOT,
f0fba2ad 1947 "wm8903", codec);
8abd16a6 1948 if (ret != 0) {
f0fba2ad 1949 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1950 ret);
f0fba2ad 1951 return ret;
8abd16a6
MB		 1952 }
1953
1954 /* Enable write sequencer interrupts */
1955 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1956 WM8903_IM_WSEQ_BUSY_EINT, 0);
1957 }
73b34ead 1958
f1c0a02f
MB		 1959 /* power on device */
1960 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1961
1962 /* Latch volume update bits */
8d50e447 1963 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1964 val |= WM8903_ADCVU;
8d50e447
MB		 1965 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1966 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1967
8d50e447 1968 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1969 val |= WM8903_DACVU;
8d50e447
MB		 1970 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1971 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1972
8d50e447 1973 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1974 val |= WM8903_HPOUTVU;
8d50e447
MB		 1975 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1976 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1977
8d50e447 1978 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1979 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1980 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1981 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1982
8d50e447 1983 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1984 val |= WM8903_SPKVU;
8d50e447
MB		 1985 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1986 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1987
1988 /* Enable DAC soft mute by default */
e12adab0
MB		 1989 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
1990 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
1991 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 1992
7cfe5617
SW		 1993 wm8903_init_gpio(codec);
1994
f1c0a02f
MB		 1995 return ret;
1996}
1997
f0fba2ad
LG		 1998/* power down chip */
1999static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2000{
f99847a6
SW		 2001 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2002
7cfe5617 2003 wm8903_free_gpio(codec);
f0fba2ad 2004 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6
SW		 2005 if (wm8903->irq)
2006 free_irq(wm8903->irq, codec);
2007
f0fba2ad
LG		 2008 return 0;
2009}
f1c0a02f 2010
f0fba2ad
LG		 2011static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2012 .probe = wm8903_probe,
2013 .remove = wm8903_remove,
2014 .suspend = wm8903_suspend,
2015 .resume = wm8903_resume,
2016 .set_bias_level = wm8903_set_bias_level,
c5b6a9fe 2017 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 2018 .controls = wm8903_snd_controls,
2019 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 2020 .dapm_widgets = wm8903_dapm_widgets,
2021 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2022 .dapm_routes = wm8903_intercon,
2023 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2024};
f1c0a02f 2025
ee244ce4
MB		 2026static const struct regmap_config wm8903_regmap = {
2027 .reg_bits = 8,
2028 .val_bits = 16,
2029
2030 .max_register = WM8903_MAX_REGISTER,
2031 .volatile_reg = wm8903_volatile_register,
2032 .readable_reg = wm8903_readable_register,
2033
2034 .cache_type = REGCACHE_RBTREE,
2035 .reg_defaults = wm8903_reg_defaults,
2036 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
2037};
2038
f0fba2ad
LG		 2039static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2040 const struct i2c_device_id *id)
2041{
c0eb27cf 2042 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
f0fba2ad 2043 struct wm8903_priv *wm8903;
7d46a528 2044 unsigned int val;
f0fba2ad 2045 int ret;
f1c0a02f 2046
2950cd22
MB		 2047 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2048 GFP_KERNEL);
f0fba2ad
LG		 2049 if (wm8903 == NULL)
2050 return -ENOMEM;
8abd16a6 2051
ee244ce4
MB		 2052 wm8903->regmap = regmap_init_i2c(i2c, &wm8903_regmap);
2053 if (IS_ERR(wm8903->regmap)) {
2054 ret = PTR_ERR(wm8903->regmap);
2055 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2056 ret);
2057 return ret;
2058 }
2059
f0fba2ad 2060 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2061 wm8903->irq = i2c->irq;
d58d5d55 2062
c0eb27cf
SW		 2063 /* If no platform data was supplied, create storage for defaults */
2064 if (pdata) {
2065 wm8903->pdata = pdata;
2066 } else {
2067 wm8903->pdata = devm_kzalloc(&i2c->dev,
2068 sizeof(struct wm8903_platform_data),
2069 GFP_KERNEL);
2070 if (wm8903->pdata == NULL) {
2071 dev_err(&i2c->dev, "Failed to allocate pdata\n");
2072 return -ENOMEM;
2073 }
2074 }
2075
7d46a528
MB		 2076 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2077 if (ret != 0) {
2078 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2079 goto err;
2080 }
2081 if (val != 0x8903) {
2082 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2083 ret = -ENODEV;
2084 goto err;
2085 }
2086
2087 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2088 if (ret != 0) {
2089 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2090 goto err;
2091 }
2092 dev_info(&i2c->dev, "WM8903 revision %c\n",
2093 (val & WM8903_CHIP_REV_MASK) + 'A');
2094
2095 /* Reset the device */
2096 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2097
f0fba2ad
LG		 2098 ret = snd_soc_register_codec(&i2c->dev,
2099 &soc_codec_dev_wm8903, &wm8903_dai, 1);
ee244ce4
MB		 2100 if (ret != 0)
2101 goto err;
2950cd22 2102
ee244ce4
MB		 2103 return 0;
2104err:
2105 regmap_exit(wm8903->regmap);
f0fba2ad
LG		 2106 return ret;
2107}
f1c0a02f 2108
f0fba2ad
LG		 2109static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2110{
ee244ce4
MB		 2111 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2112
2113 regmap_exit(wm8903->regmap);
f0fba2ad 2114 snd_soc_unregister_codec(&client->dev);
ee244ce4 2115
f1c0a02f
MB		 2116 return 0;
2117}
2118
f1c0a02f 2119static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2120 { "wm8903", 0 },
2121 { }
f1c0a02f
MB		 2122};
2123MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2124
2125static struct i2c_driver wm8903_i2c_driver = {
2126 .driver = {
4b592c91 2127 .name = "wm8903",
f1c0a02f
MB		 2128 .owner = THIS_MODULE,
2129 },
f0fba2ad
LG		 2130 .probe = wm8903_i2c_probe,
2131 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2132 .id_table = wm8903_i2c_id,
2133};
2134
f0fba2ad 2135static int __init wm8903_modinit(void)
f1c0a02f 2136{
f1c0a02f 2137 int ret = 0;
f0fba2ad
LG		 2138 ret = i2c_add_driver(&wm8903_i2c_driver);
2139 if (ret != 0) {
2140 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2141 ret);
f1c0a02f 2142 }
f1c0a02f 2143 return ret;
64089b84
MB		 2144}
2145module_init(wm8903_modinit);
2146
2147static void __exit wm8903_exit(void)
2148{
d58d5d55 2149 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 2150}
2151module_exit(wm8903_exit);
2152
f1c0a02f
MB		 2153MODULE_DESCRIPTION("ASoC WM8903 driver");
2154MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2155MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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