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ASoC: Implement WM8903 oversampling rate controls
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
5a0e3ad6 25#include <linux/slab.h>
f1c0a02f 26#include <sound/core.h>
7245387e 27#include <sound/jack.h>
f1c0a02f
MB		 28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
f1c0a02f 32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
f1c0a02f
MB		 34
35#include "wm8903.h"
36
f1c0a02f
MB		 37/* Register defaults at reset */
38static u16 wm8903_reg_defaults[] = {
39 0x8903, /* R0 - SW Reset and ID */
40 0x0000, /* R1 - Revision Number */
41 0x0000, /* R2 */
42 0x0000, /* R3 */
43 0x0018, /* R4 - Bias Control 0 */
44 0x0000, /* R5 - VMID Control 0 */
45 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0000, /* R7 */
47 0x0001, /* R8 - Analogue DAC 0 */
48 0x0000, /* R9 */
49 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R11 */
51 0x0000, /* R12 - Power Management 0 */
52 0x0000, /* R13 - Power Management 1 */
53 0x0000, /* R14 - Power Management 2 */
54 0x0000, /* R15 - Power Management 3 */
55 0x0000, /* R16 - Power Management 4 */
56 0x0000, /* R17 - Power Management 5 */
57 0x0000, /* R18 - Power Management 6 */
58 0x0000, /* R19 */
59 0x0400, /* R20 - Clock Rates 0 */
60 0x0D07, /* R21 - Clock Rates 1 */
61 0x0000, /* R22 - Clock Rates 2 */
62 0x0000, /* R23 */
63 0x0050, /* R24 - Audio Interface 0 */
64 0x0242, /* R25 - Audio Interface 1 */
65 0x0008, /* R26 - Audio Interface 2 */
66 0x0022, /* R27 - Audio Interface 3 */
67 0x0000, /* R28 */
68 0x0000, /* R29 */
69 0x00C0, /* R30 - DAC Digital Volume Left */
70 0x00C0, /* R31 - DAC Digital Volume Right */
71 0x0000, /* R32 - DAC Digital 0 */
72 0x0000, /* R33 - DAC Digital 1 */
73 0x0000, /* R34 */
74 0x0000, /* R35 */
75 0x00C0, /* R36 - ADC Digital Volume Left */
76 0x00C0, /* R37 - ADC Digital Volume Right */
77 0x0000, /* R38 - ADC Digital 0 */
78 0x0073, /* R39 - Digital Microphone 0 */
79 0x09BF, /* R40 - DRC 0 */
80 0x3241, /* R41 - DRC 1 */
81 0x0020, /* R42 - DRC 2 */
82 0x0000, /* R43 - DRC 3 */
83 0x0085, /* R44 - Analogue Left Input 0 */
84 0x0085, /* R45 - Analogue Right Input 0 */
85 0x0044, /* R46 - Analogue Left Input 1 */
86 0x0044, /* R47 - Analogue Right Input 1 */
87 0x0000, /* R48 */
88 0x0000, /* R49 */
89 0x0008, /* R50 - Analogue Left Mix 0 */
90 0x0004, /* R51 - Analogue Right Mix 0 */
91 0x0000, /* R52 - Analogue Spk Mix Left 0 */
92 0x0000, /* R53 - Analogue Spk Mix Left 1 */
93 0x0000, /* R54 - Analogue Spk Mix Right 0 */
94 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x0000, /* R56 */
96 0x002D, /* R57 - Analogue OUT1 Left */
97 0x002D, /* R58 - Analogue OUT1 Right */
98 0x0039, /* R59 - Analogue OUT2 Left */
99 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0100, /* R61 */
101 0x0139, /* R62 - Analogue OUT3 Left */
102 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R64 */
104 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0000, /* R66 */
106 0x0010, /* R67 - DC Servo 0 */
107 0x0100, /* R68 */
108 0x00A4, /* R69 - DC Servo 2 */
109 0x0807, /* R70 */
110 0x0000, /* R71 */
111 0x0000, /* R72 */
112 0x0000, /* R73 */
113 0x0000, /* R74 */
114 0x0000, /* R75 */
115 0x0000, /* R76 */
116 0x0000, /* R77 */
117 0x0000, /* R78 */
118 0x000E, /* R79 */
119 0x0000, /* R80 */
120 0x0000, /* R81 */
121 0x0000, /* R82 */
122 0x0000, /* R83 */
123 0x0000, /* R84 */
124 0x0000, /* R85 */
125 0x0000, /* R86 */
126 0x0006, /* R87 */
127 0x0000, /* R88 */
128 0x0000, /* R89 */
129 0x0000, /* R90 - Analogue HP 0 */
130 0x0060, /* R91 */
131 0x0000, /* R92 */
132 0x0000, /* R93 */
133 0x0000, /* R94 - Analogue Lineout 0 */
134 0x0060, /* R95 */
135 0x0000, /* R96 */
136 0x0000, /* R97 */
137 0x0000, /* R98 - Charge Pump 0 */
138 0x1F25, /* R99 */
139 0x2B19, /* R100 */
140 0x01C0, /* R101 */
141 0x01EF, /* R102 */
142 0x2B00, /* R103 */
143 0x0000, /* R104 - Class W 0 */
144 0x01C0, /* R105 */
145 0x1C10, /* R106 */
146 0x0000, /* R107 */
147 0x0000, /* R108 - Write Sequencer 0 */
148 0x0000, /* R109 - Write Sequencer 1 */
149 0x0000, /* R110 - Write Sequencer 2 */
150 0x0000, /* R111 - Write Sequencer 3 */
151 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R113 */
153 0x0000, /* R114 - Control Interface */
154 0x0000, /* R115 */
155 0x00A8, /* R116 - GPIO Control 1 */
156 0x00A8, /* R117 - GPIO Control 2 */
157 0x00A8, /* R118 - GPIO Control 3 */
158 0x0220, /* R119 - GPIO Control 4 */
159 0x01A0, /* R120 - GPIO Control 5 */
160 0x0000, /* R121 - Interrupt Status 1 */
161 0xFFFF, /* R122 - Interrupt Status 1 Mask */
162 0x0000, /* R123 - Interrupt Polarity 1 */
163 0x0000, /* R124 */
164 0x0003, /* R125 */
165 0x0000, /* R126 - Interrupt Control */
166 0x0000, /* R127 */
167 0x0005, /* R128 */
168 0x0000, /* R129 - Control Interface Test 1 */
169 0x0000, /* R130 */
170 0x0000, /* R131 */
171 0x0000, /* R132 */
172 0x0000, /* R133 */
173 0x0000, /* R134 */
174 0x03FF, /* R135 */
175 0x0007, /* R136 */
176 0x0040, /* R137 */
177 0x0000, /* R138 */
178 0x0000, /* R139 */
179 0x0000, /* R140 */
180 0x0000, /* R141 */
181 0x0000, /* R142 */
182 0x0000, /* R143 */
183 0x0000, /* R144 */
184 0x0000, /* R145 */
185 0x0000, /* R146 */
186 0x0000, /* R147 */
187 0x4000, /* R148 */
188 0x6810, /* R149 - Charge Pump Test 1 */
189 0x0004, /* R150 */
190 0x0000, /* R151 */
191 0x0000, /* R152 */
192 0x0000, /* R153 */
193 0x0000, /* R154 */
194 0x0000, /* R155 */
195 0x0000, /* R156 */
196 0x0000, /* R157 */
197 0x0000, /* R158 */
198 0x0000, /* R159 */
199 0x0000, /* R160 */
200 0x0000, /* R161 */
201 0x0000, /* R162 */
202 0x0000, /* R163 */
203 0x0028, /* R164 - Clock Rate Test 4 */
204 0x0004, /* R165 */
205 0x0000, /* R166 */
206 0x0060, /* R167 */
207 0x0000, /* R168 */
208 0x0000, /* R169 */
209 0x0000, /* R170 */
210 0x0000, /* R171 */
211 0x0000, /* R172 - Analogue Output Bias 0 */
212};
213
d58d5d55 214struct wm8903_priv {
f0fba2ad 215
d58d5d55
MB		 216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk;
f0fba2ad 219 int irq;
d58d5d55
MB		 220
221 /* Reference counts */
d58d5d55
MB		 222 int class_w_users;
223 int playback_active;
224 int capture_active;
225
8abd16a6
MB		 226 struct completion wseq;
227
7245387e
MB		 228 struct snd_soc_jack *mic_jack;
229 int mic_det;
230 int mic_short;
231 int mic_last_report;
232 int mic_delay;
233
d58d5d55
MB		 234 struct snd_pcm_substream *master_substream;
235 struct snd_pcm_substream *slave_substream;
236};
237
8d50e447 238static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 239{
240 switch (reg) {
241 case WM8903_SW_RESET_AND_ID:
242 case WM8903_REVISION_NUMBER:
243 case WM8903_INTERRUPT_STATUS_1:
244 case WM8903_WRITE_SEQUENCER_4:
8d50e447 245 return 1;
f1c0a02f
MB		 246
247 default:
f1c0a02f 248 return 0;
8d50e447 249 }
f1c0a02f
MB		 250}
251
252static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
253{
254 u16 reg[5];
b2c812e2 255 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 256
257 BUG_ON(start > 48);
258
37f88e84 259 /* Enable the sequencer if it's not already on */
8d50e447 260 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 261 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
262 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 263
f0fba2ad 264 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 265
8d50e447 266 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 267 start | WM8903_WSEQ_START);
268
269 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 270 * that will break us out of the poll early.
f1c0a02f
MB		 271 */
272 do {
8abd16a6
MB		 273 wait_for_completion_timeout(&wm8903->wseq,
274 msecs_to_jiffies(10));
f1c0a02f 275
8d50e447 276 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 277 } while (reg[4] & WM8903_WSEQ_BUSY);
278
f0fba2ad 279 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 280
37f88e84
MB		 281 /* Disable the sequencer again if we enabled it */
282 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 283
284 return 0;
285}
286
287static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
288{
289 int i;
290
291 /* There really ought to be something better we can do here :/ */
292 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 293 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 294}
295
296static void wm8903_reset(struct snd_soc_codec *codec)
297{
8d50e447 298 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 299 memcpy(codec->reg_cache, wm8903_reg_defaults,
300 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 301}
302
303#define WM8903_OUTPUT_SHORT 0x8
304#define WM8903_OUTPUT_OUT 0x4
305#define WM8903_OUTPUT_INT 0x2
306#define WM8903_OUTPUT_IN 0x1
307
42768a12
MB		 308static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
309 struct snd_kcontrol *kcontrol, int event)
310{
311 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
312 mdelay(4);
313
314 return 0;
315}
316
f1c0a02f
MB		 317/*
318 * Event for headphone and line out amplifier power changes. Special
319 * power up/down sequences are required in order to maximise pop/click
320 * performance.
321 */
322static int wm8903_output_event(struct snd_soc_dapm_widget *w,
323 struct snd_kcontrol *kcontrol, int event)
324{
325 struct snd_soc_codec *codec = w->codec;
f1c0a02f 326 u16 val;
0bc286e2 327 u16 reg;
d7d5c547
MB		 328 u16 dcs_reg;
329 u16 dcs_bit;
0bc286e2 330 int shift;
f1c0a02f
MB		 331
332 switch (w->reg) {
333 case WM8903_POWER_MANAGEMENT_2:
334 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 335 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 336 break;
337 case WM8903_POWER_MANAGEMENT_3:
338 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 339 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 340 break;
341 default:
342 BUG();
1e297a19 343 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 344 }
345
346 switch (w->shift) {
347 case 0:
348 shift = 0;
349 break;
350 case 1:
351 shift = 4;
352 break;
353 default:
354 BUG();
1e297a19 355 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 356 }
357
358 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 359 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 360
361 /* Short the output */
362 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 363 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 364 }
365
366 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 367 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 368
369 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 370 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 371
372 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 373 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 374
375 /* Turn on the output ENA_OUTP */
376 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 377 snd_soc_write(codec, reg, val);
f1c0a02f 378
d7d5c547 379 /* Enable the DC servo */
8d50e447 380 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 381 dcs_reg |= dcs_bit;
8d50e447 382 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 383
f1c0a02f
MB		 384 /* Remove the short */
385 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 386 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 387 }
388
389 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 390 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 391
392 /* Short the output */
393 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 394 snd_soc_write(codec, reg, val);
f1c0a02f 395
d7d5c547 396 /* Disable the DC servo */
8d50e447 397 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 398 dcs_reg &= ~dcs_bit;
8d50e447 399 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 400
f1c0a02f
MB		 401 /* Then disable the intermediate and output stages */
402 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
403 WM8903_OUTPUT_IN) << shift);
8d50e447 404 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 405 }
406
f1c0a02f
MB		 407 return 0;
408}
409
410/*
411 * When used with DAC outputs only the WM8903 charge pump supports
412 * operation in class W mode, providing very low power consumption
413 * when used with digital sources. Enable and disable this mode
414 * automatically depending on the mixer configuration.
415 *
416 * All the relevant controls are simple switches.
417 */
418static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
422 struct snd_soc_codec *codec = widget->codec;
b2c812e2 423 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 424 u16 reg;
425 int ret;
426
8d50e447 427 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 428
429 /* Turn it off if we're about to enable bypass */
430 if (ucontrol->value.integer.value[0]) {
431 if (wm8903->class_w_users == 0) {
f0fba2ad 432 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 433 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 434 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
435 }
436 wm8903->class_w_users++;
437 }
438
439 /* Implement the change */
440 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
441
442 /* If we've just disabled the last bypass path turn Class W on */
443 if (!ucontrol->value.integer.value[0]) {
444 if (wm8903->class_w_users == 1) {
f0fba2ad 445 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 446 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 447 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
448 }
449 wm8903->class_w_users--;
450 }
451
f0fba2ad 452 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 453 wm8903->class_w_users);
454
455 return ret;
456}
457
458#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
459{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
460 .info = snd_soc_info_volsw, \
461 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
462 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
463
464
465/* ALSA can only do steps of .01dB */
466static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
467
291ce18c 468static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 469static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
470
471static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
472static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
473static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
474static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
475static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
476
460f4aae
MB		 477static const char *hpf_mode_text[] = {
478 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
479};
480
481static const struct soc_enum hpf_mode =
482 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
483
dcf9ada3
MB		 484static const char *osr_text[] = {
485 "Low power", "High performance"
486};
487
488static const struct soc_enum adc_osr =
489 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
493
f1c0a02f
MB		 494static const char *drc_slope_text[] = {
495 "1", "1/2", "1/4", "1/8", "1/16", "0"
496};
497
498static const struct soc_enum drc_slope_r0 =
499 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
500
501static const struct soc_enum drc_slope_r1 =
502 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
503
504static const char *drc_attack_text[] = {
505 "instantaneous",
506 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
507 "46.4ms", "92.8ms", "185.6ms"
508};
509
510static const struct soc_enum drc_attack =
511 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
512
513static const char *drc_decay_text[] = {
514 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
515 "23.87s", "47.56s"
516};
517
518static const struct soc_enum drc_decay =
519 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
520
521static const char *drc_ff_delay_text[] = {
522 "5 samples", "9 samples"
523};
524
525static const struct soc_enum drc_ff_delay =
526 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
527
528static const char *drc_qr_decay_text[] = {
529 "0.725ms", "1.45ms", "5.8ms"
530};
531
532static const struct soc_enum drc_qr_decay =
533 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
534
535static const char *drc_smoothing_text[] = {
536 "Low", "Medium", "High"
537};
538
539static const struct soc_enum drc_smoothing =
540 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
541
542static const char *soft_mute_text[] = {
543 "Fast (fs/2)", "Slow (fs/32)"
544};
545
546static const struct soc_enum soft_mute =
547 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
548
549static const char *mute_mode_text[] = {
550 "Hard", "Soft"
551};
552
553static const struct soc_enum mute_mode =
554 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
555
556static const char *dac_deemphasis_text[] = {
557 "Disabled", "32kHz", "44.1kHz", "48kHz"
558};
559
560static const struct soc_enum dac_deemphasis =
561 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
562
563static const char *companding_text[] = {
564 "ulaw", "alaw"
565};
566
567static const struct soc_enum dac_companding =
568 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
569
570static const struct soc_enum adc_companding =
571 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
572
573static const char *input_mode_text[] = {
574 "Single-Ended", "Differential Line", "Differential Mic"
575};
576
577static const struct soc_enum linput_mode_enum =
578 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
579
580static const struct soc_enum rinput_mode_enum =
581 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
582
583static const char *linput_mux_text[] = {
584 "IN1L", "IN2L", "IN3L"
585};
586
587static const struct soc_enum linput_enum =
588 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
589
590static const struct soc_enum linput_inv_enum =
591 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
592
593static const char *rinput_mux_text[] = {
594 "IN1R", "IN2R", "IN3R"
595};
596
597static const struct soc_enum rinput_enum =
598 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
599
600static const struct soc_enum rinput_inv_enum =
601 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
602
603
291ce18c
MB		 604static const char *sidetone_text[] = {
605 "None", "Left", "Right"
606};
607
608static const struct soc_enum lsidetone_enum =
609 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
610
611static const struct soc_enum rsidetone_enum =
612 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
613
f1c0a02f
MB		 614static const struct snd_kcontrol_new wm8903_snd_controls[] = {
615
616/* Input PGAs - No TLV since the scale depends on PGA mode */
617SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 618 7, 1, 1),
f1c0a02f
MB		 619SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
620 0, 31, 0),
621SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
622 6, 1, 0),
623
624SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 625 7, 1, 1),
f1c0a02f
MB		 626SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
627 0, 31, 0),
628SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
629 6, 1, 0),
630
631/* ADCs */
dcf9ada3 632SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 633SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
634SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 635SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
636SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
637SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 638SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 639 drc_tlv_thresh),
640SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
641SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
642SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
643SOC_ENUM("DRC Attack Rate", drc_attack),
644SOC_ENUM("DRC Decay Rate", drc_decay),
645SOC_ENUM("DRC FF Delay", drc_ff_delay),
646SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
647SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 648SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 649SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
650SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
651SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 652SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 653SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
654
655SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
656 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
657SOC_ENUM("ADC Companding Mode", adc_companding),
658SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
659
291ce18c
MB		 660SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
661 12, 0, digital_sidetone_tlv),
662
f1c0a02f 663/* DAC */
dcf9ada3 664SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 665SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
666 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
667SOC_ENUM("DAC Soft Mute Rate", soft_mute),
668SOC_ENUM("DAC Mute Mode", mute_mode),
669SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
670SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 671SOC_ENUM("DAC Companding Mode", dac_companding),
672SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
673
674/* Headphones */
675SOC_DOUBLE_R("Headphone Switch",
676 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
677 8, 1, 1),
678SOC_DOUBLE_R("Headphone ZC Switch",
679 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
680 6, 1, 0),
681SOC_DOUBLE_R_TLV("Headphone Volume",
682 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
683 0, 63, 0, out_tlv),
684
685/* Line out */
686SOC_DOUBLE_R("Line Out Switch",
687 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
688 8, 1, 1),
689SOC_DOUBLE_R("Line Out ZC Switch",
690 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
691 6, 1, 0),
692SOC_DOUBLE_R_TLV("Line Out Volume",
693 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
694 0, 63, 0, out_tlv),
695
696/* Speaker */
697SOC_DOUBLE_R("Speaker Switch",
698 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
699SOC_DOUBLE_R("Speaker ZC Switch",
700 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
701SOC_DOUBLE_R_TLV("Speaker Volume",
702 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
703 0, 63, 0, out_tlv),
704};
705
f1c0a02f
MB		 706static const struct snd_kcontrol_new linput_mode_mux =
707 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
708
709static const struct snd_kcontrol_new rinput_mode_mux =
710 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
711
712static const struct snd_kcontrol_new linput_mux =
713 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
714
715static const struct snd_kcontrol_new linput_inv_mux =
716 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
717
718static const struct snd_kcontrol_new rinput_mux =
719 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
720
721static const struct snd_kcontrol_new rinput_inv_mux =
722 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
723
291ce18c
MB		 724static const struct snd_kcontrol_new lsidetone_mux =
725 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
726
727static const struct snd_kcontrol_new rsidetone_mux =
728 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
729
f1c0a02f
MB		 730static const struct snd_kcontrol_new left_output_mixer[] = {
731SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
732SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
733SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 734SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 735};
736
737static const struct snd_kcontrol_new right_output_mixer[] = {
738SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
739SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
740SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 741SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 742};
743
744static const struct snd_kcontrol_new left_speaker_mixer[] = {
745SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
746SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
747SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
748SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 749 0, 1, 0),
f1c0a02f
MB		 750};
751
752static const struct snd_kcontrol_new right_speaker_mixer[] = {
753SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
754SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
755SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
756 1, 1, 0),
757SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 758 0, 1, 0),
f1c0a02f
MB		 759};
760
761static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
762SND_SOC_DAPM_INPUT("IN1L"),
763SND_SOC_DAPM_INPUT("IN1R"),
764SND_SOC_DAPM_INPUT("IN2L"),
765SND_SOC_DAPM_INPUT("IN2R"),
766SND_SOC_DAPM_INPUT("IN3L"),
767SND_SOC_DAPM_INPUT("IN3R"),
768
769SND_SOC_DAPM_OUTPUT("HPOUTL"),
770SND_SOC_DAPM_OUTPUT("HPOUTR"),
771SND_SOC_DAPM_OUTPUT("LINEOUTL"),
772SND_SOC_DAPM_OUTPUT("LINEOUTR"),
773SND_SOC_DAPM_OUTPUT("LOP"),
774SND_SOC_DAPM_OUTPUT("LON"),
775SND_SOC_DAPM_OUTPUT("ROP"),
776SND_SOC_DAPM_OUTPUT("RON"),
777
778SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
779
780SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
781SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
782 &linput_inv_mux),
783SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
784
785SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
786SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
787 &rinput_inv_mux),
788SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
789
790SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
791SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
792
793SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
794SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
795
291ce18c
MB		 796SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
797SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
798
f1c0a02f
MB		 799SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
800SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
801
802SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
803 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
804SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
805 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
806
807SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
808 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
809SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
810 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
811
812SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
813 1, 0, NULL, 0, wm8903_output_event,
814 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 815 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 816SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
817 0, 0, NULL, 0, wm8903_output_event,
818 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 819 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 820
821SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
822 NULL, 0, wm8903_output_event,
823 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 824 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 825SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
826 NULL, 0, wm8903_output_event,
827 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 828 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 829
830SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
831 NULL, 0),
832SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
833 NULL, 0),
834
42768a12
MB		 835SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
836 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 837SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 838};
839
840static const struct snd_soc_dapm_route intercon[] = {
841
842 { "Left Input Mux", "IN1L", "IN1L" },
843 { "Left Input Mux", "IN2L", "IN2L" },
844 { "Left Input Mux", "IN3L", "IN3L" },
845
846 { "Left Input Inverting Mux", "IN1L", "IN1L" },
847 { "Left Input Inverting Mux", "IN2L", "IN2L" },
848 { "Left Input Inverting Mux", "IN3L", "IN3L" },
849
850 { "Right Input Mux", "IN1R", "IN1R" },
851 { "Right Input Mux", "IN2R", "IN2R" },
852 { "Right Input Mux", "IN3R", "IN3R" },
853
854 { "Right Input Inverting Mux", "IN1R", "IN1R" },
855 { "Right Input Inverting Mux", "IN2R", "IN2R" },
856 { "Right Input Inverting Mux", "IN3R", "IN3R" },
857
858 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
859 { "Left Input Mode Mux", "Differential Line",
860 "Left Input Mux" },
861 { "Left Input Mode Mux", "Differential Line",
862 "Left Input Inverting Mux" },
863 { "Left Input Mode Mux", "Differential Mic",
864 "Left Input Mux" },
865 { "Left Input Mode Mux", "Differential Mic",
866 "Left Input Inverting Mux" },
867
868 { "Right Input Mode Mux", "Single-Ended",
869 "Right Input Inverting Mux" },
870 { "Right Input Mode Mux", "Differential Line",
871 "Right Input Mux" },
872 { "Right Input Mode Mux", "Differential Line",
873 "Right Input Inverting Mux" },
874 { "Right Input Mode Mux", "Differential Mic",
875 "Right Input Mux" },
876 { "Right Input Mode Mux", "Differential Mic",
877 "Right Input Inverting Mux" },
878
879 { "Left Input PGA", NULL, "Left Input Mode Mux" },
880 { "Right Input PGA", NULL, "Right Input Mode Mux" },
881
882 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 883 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 884 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 885 { "ADCR", NULL, "CLK_DSP" },
886
291ce18c
MB		 887 { "DACL Sidetone", "Left", "ADCL" },
888 { "DACL Sidetone", "Right", "ADCR" },
889 { "DACR Sidetone", "Left", "ADCL" },
890 { "DACR Sidetone", "Right", "ADCR" },
891
892 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 893 { "DACL", NULL, "CLK_DSP" },
291ce18c 894 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 895 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 896
897 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
898 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
899 { "Left Output Mixer", "DACL Switch", "DACL" },
900 { "Left Output Mixer", "DACR Switch", "DACR" },
901
902 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
903 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
904 { "Right Output Mixer", "DACL Switch", "DACL" },
905 { "Right Output Mixer", "DACR Switch", "DACR" },
906
907 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
908 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
909 { "Left Speaker Mixer", "DACL Switch", "DACL" },
910 { "Left Speaker Mixer", "DACR Switch", "DACR" },
911
912 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
913 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
914 { "Right Speaker Mixer", "DACL Switch", "DACL" },
915 { "Right Speaker Mixer", "DACR Switch", "DACR" },
916
917 { "Left Line Output PGA", NULL, "Left Output Mixer" },
918 { "Right Line Output PGA", NULL, "Right Output Mixer" },
919
920 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
921 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
922
923 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
924 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
925
926 { "HPOUTL", NULL, "Left Headphone Output PGA" },
927 { "HPOUTR", NULL, "Right Headphone Output PGA" },
928
929 { "LINEOUTL", NULL, "Left Line Output PGA" },
930 { "LINEOUTR", NULL, "Right Line Output PGA" },
931
932 { "LOP", NULL, "Left Speaker PGA" },
933 { "LON", NULL, "Left Speaker PGA" },
934
935 { "ROP", NULL, "Right Speaker PGA" },
936 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 937
938 { "Left Headphone Output PGA", NULL, "Charge Pump" },
939 { "Right Headphone Output PGA", NULL, "Charge Pump" },
940 { "Left Line Output PGA", NULL, "Charge Pump" },
941 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 942};
943
944static int wm8903_add_widgets(struct snd_soc_codec *codec)
945{
ce6120cc 946 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 947
ce6120cc
LG		 948 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
949 ARRAY_SIZE(wm8903_dapm_widgets));
950 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 951
f1c0a02f
MB		 952 return 0;
953}
954
955static int wm8903_set_bias_level(struct snd_soc_codec *codec,
956 enum snd_soc_bias_level level)
957{
f1c0a02f
MB		 958 u16 reg, reg2;
959
960 switch (level) {
961 case SND_SOC_BIAS_ON:
962 case SND_SOC_BIAS_PREPARE:
8d50e447 963 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 964 reg &= ~(WM8903_VMID_RES_MASK);
965 reg |= WM8903_VMID_RES_50K;
8d50e447 966 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 967 break;
968
969 case SND_SOC_BIAS_STANDBY:
ce6120cc 970 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 971 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 972 WM8903_CLK_SYS_ENA);
973
4dbfe809 974 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 975 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
976 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
977 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 978
f1c0a02f
MB		 979 wm8903_run_sequence(codec, 0);
980 wm8903_sync_reg_cache(codec, codec->reg_cache);
981
982 /* Enable low impedence charge pump output */
8d50e447 983 reg = snd_soc_read(codec,
f1c0a02f 984 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 985 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 986 reg | WM8903_TEST_KEY);
8d50e447
MB		 987 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
988 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 989 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 990 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 991 reg);
992
993 /* By default no bypass paths are enabled so
994 * enable Class W support.
995 */
f0fba2ad 996 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 997 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 998 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
999 }
1000
8d50e447 1001 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1002 reg &= ~(WM8903_VMID_RES_MASK);
1003 reg |= WM8903_VMID_RES_250K;
8d50e447 1004 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1005 break;
1006
1007 case SND_SOC_BIAS_OFF:
1008 wm8903_run_sequence(codec, 32);
8d50e447 1009 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1010 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1011 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1012 break;
1013 }
1014
ce6120cc 1015 codec->dapm.bias_level = level;
f1c0a02f
MB		 1016
1017 return 0;
1018}
1019
1020static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1021 int clk_id, unsigned int freq, int dir)
1022{
1023 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1024 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1025
1026 wm8903->sysclk = freq;
1027
1028 return 0;
1029}
1030
1031static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1032 unsigned int fmt)
1033{
1034 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1035 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1036
1037 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1038 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1039
1040 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1041 case SND_SOC_DAIFMT_CBS_CFS:
1042 break;
1043 case SND_SOC_DAIFMT_CBS_CFM:
1044 aif1 |= WM8903_LRCLK_DIR;
1045 break;
1046 case SND_SOC_DAIFMT_CBM_CFM:
1047 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1048 break;
1049 case SND_SOC_DAIFMT_CBM_CFS:
1050 aif1 |= WM8903_BCLK_DIR;
1051 break;
1052 default:
1053 return -EINVAL;
1054 }
1055
1056 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1057 case SND_SOC_DAIFMT_DSP_A:
1058 aif1 |= 0x3;
1059 break;
1060 case SND_SOC_DAIFMT_DSP_B:
1061 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1062 break;
1063 case SND_SOC_DAIFMT_I2S:
1064 aif1 |= 0x2;
1065 break;
1066 case SND_SOC_DAIFMT_RIGHT_J:
1067 aif1 |= 0x1;
1068 break;
1069 case SND_SOC_DAIFMT_LEFT_J:
1070 break;
1071 default:
1072 return -EINVAL;
1073 }
1074
1075 /* Clock inversion */
1076 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1077 case SND_SOC_DAIFMT_DSP_A:
1078 case SND_SOC_DAIFMT_DSP_B:
1079 /* frame inversion not valid for DSP modes */
1080 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1081 case SND_SOC_DAIFMT_NB_NF:
1082 break;
1083 case SND_SOC_DAIFMT_IB_NF:
1084 aif1 |= WM8903_AIF_BCLK_INV;
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089 break;
1090 case SND_SOC_DAIFMT_I2S:
1091 case SND_SOC_DAIFMT_RIGHT_J:
1092 case SND_SOC_DAIFMT_LEFT_J:
1093 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1094 case SND_SOC_DAIFMT_NB_NF:
1095 break;
1096 case SND_SOC_DAIFMT_IB_IF:
1097 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1098 break;
1099 case SND_SOC_DAIFMT_IB_NF:
1100 aif1 |= WM8903_AIF_BCLK_INV;
1101 break;
1102 case SND_SOC_DAIFMT_NB_IF:
1103 aif1 |= WM8903_AIF_LRCLK_INV;
1104 break;
1105 default:
1106 return -EINVAL;
1107 }
1108 break;
1109 default:
1110 return -EINVAL;
1111 }
1112
8d50e447 1113 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1114
1115 return 0;
1116}
1117
1118static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1119{
1120 struct snd_soc_codec *codec = codec_dai->codec;
1121 u16 reg;
1122
8d50e447 1123 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1124
1125 if (mute)
1126 reg |= WM8903_DAC_MUTE;
1127 else
1128 reg &= ~WM8903_DAC_MUTE;
1129
8d50e447 1130 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1131
1132 return 0;
1133}
1134
1135/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1136 * for optimal performance so we list the lower rates first and match
1137 * on the last match we find. */
1138static struct {
1139 int div;
1140 int rate;
1141 int mode;
1142 int mclk_div;
1143} clk_sys_ratios[] = {
1144 { 64, 0x0, 0x0, 1 },
1145 { 68, 0x0, 0x1, 1 },
1146 { 125, 0x0, 0x2, 1 },
1147 { 128, 0x1, 0x0, 1 },
1148 { 136, 0x1, 0x1, 1 },
1149 { 192, 0x2, 0x0, 1 },
1150 { 204, 0x2, 0x1, 1 },
1151
1152 { 64, 0x0, 0x0, 2 },
1153 { 68, 0x0, 0x1, 2 },
1154 { 125, 0x0, 0x2, 2 },
1155 { 128, 0x1, 0x0, 2 },
1156 { 136, 0x1, 0x1, 2 },
1157 { 192, 0x2, 0x0, 2 },
1158 { 204, 0x2, 0x1, 2 },
1159
1160 { 250, 0x2, 0x2, 1 },
1161 { 256, 0x3, 0x0, 1 },
1162 { 272, 0x3, 0x1, 1 },
1163 { 384, 0x4, 0x0, 1 },
1164 { 408, 0x4, 0x1, 1 },
1165 { 375, 0x4, 0x2, 1 },
1166 { 512, 0x5, 0x0, 1 },
1167 { 544, 0x5, 0x1, 1 },
1168 { 500, 0x5, 0x2, 1 },
1169 { 768, 0x6, 0x0, 1 },
1170 { 816, 0x6, 0x1, 1 },
1171 { 750, 0x6, 0x2, 1 },
1172 { 1024, 0x7, 0x0, 1 },
1173 { 1088, 0x7, 0x1, 1 },
1174 { 1000, 0x7, 0x2, 1 },
1175 { 1408, 0x8, 0x0, 1 },
1176 { 1496, 0x8, 0x1, 1 },
1177 { 1536, 0x9, 0x0, 1 },
1178 { 1632, 0x9, 0x1, 1 },
1179 { 1500, 0x9, 0x2, 1 },
1180
1181 { 250, 0x2, 0x2, 2 },
1182 { 256, 0x3, 0x0, 2 },
1183 { 272, 0x3, 0x1, 2 },
1184 { 384, 0x4, 0x0, 2 },
1185 { 408, 0x4, 0x1, 2 },
1186 { 375, 0x4, 0x2, 2 },
1187 { 512, 0x5, 0x0, 2 },
1188 { 544, 0x5, 0x1, 2 },
1189 { 500, 0x5, 0x2, 2 },
1190 { 768, 0x6, 0x0, 2 },
1191 { 816, 0x6, 0x1, 2 },
1192 { 750, 0x6, 0x2, 2 },
1193 { 1024, 0x7, 0x0, 2 },
1194 { 1088, 0x7, 0x1, 2 },
1195 { 1000, 0x7, 0x2, 2 },
1196 { 1408, 0x8, 0x0, 2 },
1197 { 1496, 0x8, 0x1, 2 },
1198 { 1536, 0x9, 0x0, 2 },
1199 { 1632, 0x9, 0x1, 2 },
1200 { 1500, 0x9, 0x2, 2 },
1201};
1202
1203/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1204static struct {
1205 int ratio;
1206 int div;
1207} bclk_divs[] = {
1208 { 10, 0 },
f1c0a02f
MB		 1209 { 20, 2 },
1210 { 30, 3 },
1211 { 40, 4 },
1212 { 50, 5 },
f1c0a02f
MB		 1213 { 60, 7 },
1214 { 80, 8 },
1215 { 100, 9 },
f1c0a02f
MB		 1216 { 120, 11 },
1217 { 160, 12 },
1218 { 200, 13 },
1219 { 220, 14 },
1220 { 240, 15 },
f1c0a02f
MB		 1221 { 300, 17 },
1222 { 320, 18 },
1223 { 440, 19 },
1224 { 480, 20 },
1225};
1226
1227/* Sample rates for DSP */
1228static struct {
1229 int rate;
1230 int value;
1231} sample_rates[] = {
1232 { 8000, 0 },
1233 { 11025, 1 },
1234 { 12000, 2 },
1235 { 16000, 3 },
1236 { 22050, 4 },
1237 { 24000, 5 },
1238 { 32000, 6 },
1239 { 44100, 7 },
1240 { 48000, 8 },
1241 { 88200, 9 },
1242 { 96000, 10 },
1243 { 0, 0 },
1244};
1245
dee89c4d
MB		 1246static int wm8903_startup(struct snd_pcm_substream *substream,
1247 struct snd_soc_dai *dai)
f1c0a02f
MB		 1248{
1249 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1250 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1251 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1252 struct snd_pcm_runtime *master_runtime;
1253
1254 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1255 wm8903->playback_active++;
1256 else
1257 wm8903->capture_active++;
1258
1259 /* The DAI has shared clocks so if we already have a playback or
1260 * capture going then constrain this substream to match it.
1261 */
1262 if (wm8903->master_substream) {
1263 master_runtime = wm8903->master_substream->runtime;
1264
f0fba2ad 1265 dev_dbg(codec->dev, "Constraining to %d bits\n",
727fb909 1266 master_runtime->sample_bits);
f1c0a02f
MB		 1267
1268 snd_pcm_hw_constraint_minmax(substream->runtime,
1269 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1270 master_runtime->sample_bits,
1271 master_runtime->sample_bits);
1272
1273 wm8903->slave_substream = substream;
1274 } else
1275 wm8903->master_substream = substream;
1276
1277 return 0;
1278}
1279
dee89c4d
MB		 1280static void wm8903_shutdown(struct snd_pcm_substream *substream,
1281 struct snd_soc_dai *dai)
f1c0a02f
MB		 1282{
1283 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1284 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1285 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1286
1287 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1288 wm8903->playback_active--;
1289 else
1290 wm8903->capture_active--;
1291
1292 if (wm8903->master_substream == substream)
1293 wm8903->master_substream = wm8903->slave_substream;
1294
1295 wm8903->slave_substream = NULL;
1296}
1297
1298static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1299 struct snd_pcm_hw_params *params,
1300 struct snd_soc_dai *dai)
f1c0a02f
MB		 1301{
1302 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1303 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1304 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1305 int fs = params_rate(params);
1306 int bclk;
1307 int bclk_div;
1308 int i;
1309 int dsp_config;
1310 int clk_config;
1311 int best_val;
1312 int cur_val;
1313 int clk_sys;
1314
8d50e447
MB		 1315 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1316 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1317 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1318 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1319 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1320 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1321
1322 if (substream == wm8903->slave_substream) {
f0fba2ad 1323 dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n");
f1c0a02f
MB		 1324 return 0;
1325 }
1326
9e79261f
MB		 1327 /* Enable sloping stopband filter for low sample rates */
1328 if (fs <= 24000)
1329 dac_digital1 |= WM8903_DAC_SB_FILT;
1330 else
1331 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1332
f1c0a02f
MB		 1333 /* Configure sample rate logic for DSP - choose nearest rate */
1334 dsp_config = 0;
1335 best_val = abs(sample_rates[dsp_config].rate - fs);
1336 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1337 cur_val = abs(sample_rates[i].rate - fs);
1338 if (cur_val <= best_val) {
1339 dsp_config = i;
1340 best_val = cur_val;
1341 }
1342 }
1343
1344 /* Constraints should stop us hitting this but let's make sure */
1345 if (wm8903->capture_active)
1346 switch (sample_rates[dsp_config].rate) {
1347 case 88200:
1348 case 96000:
f0fba2ad 1349 dev_err(codec->dev, "%dHz unsupported by ADC\n",
f1c0a02f
MB		 1350 fs);
1351 return -EINVAL;
1352
1353 default:
1354 break;
1355 }
1356
f0fba2ad 1357 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1358 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1359 clock1 |= sample_rates[dsp_config].value;
1360
1361 aif1 &= ~WM8903_AIF_WL_MASK;
1362 bclk = 2 * fs;
1363 switch (params_format(params)) {
1364 case SNDRV_PCM_FORMAT_S16_LE:
1365 bclk *= 16;
1366 break;
1367 case SNDRV_PCM_FORMAT_S20_3LE:
1368 bclk *= 20;
1369 aif1 |= 0x4;
1370 break;
1371 case SNDRV_PCM_FORMAT_S24_LE:
1372 bclk *= 24;
1373 aif1 |= 0x8;
1374 break;
1375 case SNDRV_PCM_FORMAT_S32_LE:
1376 bclk *= 32;
1377 aif1 |= 0xc;
1378 break;
1379 default:
1380 return -EINVAL;
1381 }
1382
f0fba2ad 1383 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1384 wm8903->sysclk, fs);
1385
1386 /* We may not have an MCLK which allows us to generate exactly
1387 * the clock we want, particularly with USB derived inputs, so
1388 * approximate.
1389 */
1390 clk_config = 0;
1391 best_val = abs((wm8903->sysclk /
1392 (clk_sys_ratios[0].mclk_div *
1393 clk_sys_ratios[0].div)) - fs);
1394 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1395 cur_val = abs((wm8903->sysclk /
1396 (clk_sys_ratios[i].mclk_div *
1397 clk_sys_ratios[i].div)) - fs);
1398
1399 if (cur_val <= best_val) {
1400 clk_config = i;
1401 best_val = cur_val;
1402 }
1403 }
1404
1405 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1406 clock0 |= WM8903_MCLKDIV2;
1407 clk_sys = wm8903->sysclk / 2;
1408 } else {
1409 clock0 &= ~WM8903_MCLKDIV2;
1410 clk_sys = wm8903->sysclk;
1411 }
1412
1413 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1414 WM8903_CLK_SYS_MODE_MASK);
1415 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1416 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1417
f0fba2ad 1418 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1419 clk_sys_ratios[clk_config].rate,
1420 clk_sys_ratios[clk_config].mode,
1421 clk_sys_ratios[clk_config].div);
1422
f0fba2ad 1423 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1424
1425 /* We may not get quite the right frequency if using
1426 * approximate clocks so look for the closest match that is
1427 * higher than the target (we need to ensure that there enough
1428 * BCLKs to clock out the samples).
1429 */
1430 bclk_div = 0;
1431 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1432 i = 1;
1433 while (i < ARRAY_SIZE(bclk_divs)) {
1434 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1435 if (cur_val < 0) /* BCLK table is sorted */
1436 break;
1437 bclk_div = i;
1438 best_val = cur_val;
1439 i++;
1440 }
1441
1442 aif2 &= ~WM8903_BCLK_DIV_MASK;
1443 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1444
f0fba2ad 1445 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1446 bclk_divs[bclk_div].ratio / 10, bclk,
1447 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1448
1449 aif2 |= bclk_divs[bclk_div].div;
1450 aif3 |= bclk / fs;
1451
8d50e447
MB		 1452 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1453 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1454 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1455 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1456 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1457 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1458
1459 return 0;
1460}
1461
7245387e
MB		 1462/**
1463 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1464 *
1465 * @codec: WM8903 codec
1466 * @jack: jack to report detection events on
1467 * @det: value to report for presence detection
1468 * @shrt: value to report for short detection
1469 *
1470 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1471 * being used to bring out signals to the processor then only platform
1472 * data configuration is needed for WM8903 and processor GPIOs should
1473 * be configured using snd_soc_jack_add_gpios() instead.
1474 *
1475 * The current threasholds for detection should be configured using
1476 * micdet_cfg in the platform data. Using this function will force on
1477 * the microphone bias for the device.
1478 */
1479int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1480 int det, int shrt)
1481{
b2c812e2 1482 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1483 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1484
1485 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1486 det, shrt);
1487
1488 /* Store the configuration */
1489 wm8903->mic_jack = jack;
1490 wm8903->mic_det = det;
1491 wm8903->mic_short = shrt;
1492
1493 /* Enable interrupts we've got a report configured for */
1494 if (det)
1495 irq_mask &= ~WM8903_MICDET_EINT;
1496 if (shrt)
1497 irq_mask &= ~WM8903_MICSHRT_EINT;
1498
1499 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1500 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1501 irq_mask);
1502
69266866
MB		 1503 if (det && shrt) {
1504 /* Enable mic detection, this may not have been set through
1505 * platform data (eg, if the defaults are OK). */
1506 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1507 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1508 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1509 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1510 } else {
1511 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1512 WM8903_MICDET_ENA, 0);
1513 }
7245387e
MB		 1514
1515 return 0;
1516}
1517EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1518
8abd16a6
MB		 1519static irqreturn_t wm8903_irq(int irq, void *data)
1520{
f0fba2ad
LG		 1521 struct snd_soc_codec *codec = data;
1522 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1523 int mic_report;
1524 int int_pol;
1525 int int_val = 0;
1526 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1527
7245387e 1528 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1529
7245387e 1530 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1531 dev_dbg(codec->dev, "Write sequencer done\n");
1532 complete(&wm8903->wseq);
1533 }
1534
7245387e
MB		 1535 /*
1536 * The rest is microphone jack detection. We need to manually
1537 * invert the polarity of the interrupt after each event - to
1538 * simplify the code keep track of the last state we reported
1539 * and just invert the relevant bits in both the report and
1540 * the polarity register.
1541 */
1542 mic_report = wm8903->mic_last_report;
1543 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1544
1545 if (int_val & WM8903_MICSHRT_EINT) {
1546 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1547
1548 mic_report ^= wm8903->mic_short;
1549 int_pol ^= WM8903_MICSHRT_INV;
1550 }
1551
1552 if (int_val & WM8903_MICDET_EINT) {
1553 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1554
1555 mic_report ^= wm8903->mic_det;
1556 int_pol ^= WM8903_MICDET_INV;
1557
1558 msleep(wm8903->mic_delay);
1559 }
1560
1561 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1562 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1563
1564 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1565 wm8903->mic_short | wm8903->mic_det);
1566
1567 wm8903->mic_last_report = mic_report;
1568
8abd16a6
MB		 1569 return IRQ_HANDLED;
1570}
1571
f1c0a02f
MB		 1572#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1573 SNDRV_PCM_RATE_11025 | \
1574 SNDRV_PCM_RATE_16000 | \
1575 SNDRV_PCM_RATE_22050 | \
1576 SNDRV_PCM_RATE_32000 | \
1577 SNDRV_PCM_RATE_44100 | \
1578 SNDRV_PCM_RATE_48000 | \
1579 SNDRV_PCM_RATE_88200 | \
1580 SNDRV_PCM_RATE_96000)
1581
1582#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1583 SNDRV_PCM_RATE_11025 | \
1584 SNDRV_PCM_RATE_16000 | \
1585 SNDRV_PCM_RATE_22050 | \
1586 SNDRV_PCM_RATE_32000 | \
1587 SNDRV_PCM_RATE_44100 | \
1588 SNDRV_PCM_RATE_48000)
1589
1590#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1591 SNDRV_PCM_FMTBIT_S20_3LE |\
1592 SNDRV_PCM_FMTBIT_S24_LE)
1593
6335d055
EM		 1594static struct snd_soc_dai_ops wm8903_dai_ops = {
1595 .startup = wm8903_startup,
1596 .shutdown = wm8903_shutdown,
1597 .hw_params = wm8903_hw_params,
1598 .digital_mute = wm8903_digital_mute,
1599 .set_fmt = wm8903_set_dai_fmt,
1600 .set_sysclk = wm8903_set_dai_sysclk,
1601};
1602
f0fba2ad
LG		 1603static struct snd_soc_dai_driver wm8903_dai = {
1604 .name = "wm8903-hifi",
f1c0a02f
MB		 1605 .playback = {
1606 .stream_name = "Playback",
1607 .channels_min = 2,
1608 .channels_max = 2,
1609 .rates = WM8903_PLAYBACK_RATES,
1610 .formats = WM8903_FORMATS,
1611 },
1612 .capture = {
1613 .stream_name = "Capture",
1614 .channels_min = 2,
1615 .channels_max = 2,
1616 .rates = WM8903_CAPTURE_RATES,
1617 .formats = WM8903_FORMATS,
1618 },
6335d055 1619 .ops = &wm8903_dai_ops,
0d960e88 1620 .symmetric_rates = 1,
f1c0a02f 1621};
f1c0a02f 1622
f0fba2ad 1623static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1624{
f1c0a02f
MB		 1625 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1626
1627 return 0;
1628}
1629
f0fba2ad 1630static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1631{
f1c0a02f
MB		 1632 int i;
1633 u16 *reg_cache = codec->reg_cache;
40aa7030 1634 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1635 GFP_KERNEL);
1636
1637 /* Bring the codec back up to standby first to minimise pop/clicks */
1638 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1639
1640 /* Sync back everything else */
1641 if (tmp_cache) {
1642 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1643 if (tmp_cache[i] != reg_cache[i])
8d50e447 1644 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1645 kfree(tmp_cache);
f1c0a02f 1646 } else {
f0fba2ad 1647 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1648 }
1649
1650 return 0;
1651}
1652
f0fba2ad 1653static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1654{
f0fba2ad
LG		 1655 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1656 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1657 int ret, i;
8abd16a6 1658 int trigger, irq_pol;
f1c0a02f
MB		 1659 u16 val;
1660
8abd16a6 1661 init_completion(&wm8903->wseq);
d58d5d55 1662
8d50e447
MB		 1663 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1664 if (ret != 0) {
f0fba2ad
LG		 1665 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1666 return ret;
8d50e447
MB		 1667 }
1668
1669 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1670 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1671 dev_err(codec->dev,
d58d5d55
MB		 1672 "Device with ID register %x is not a WM8903\n", val);
1673 return -ENODEV;
f1c0a02f
MB		 1674 }
1675
8d50e447 1676 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f0fba2ad 1677 dev_info(codec->dev, "WM8903 revision %d\n",
f1c0a02f
MB		 1678 val & WM8903_CHIP_REV_MASK);
1679
1680 wm8903_reset(codec);
1681
37f88e84 1682 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1683 if (pdata) {
1684 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1685 if (!pdata->gpio_cfg[i])
1686 continue;
1687
1688 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1689 pdata->gpio_cfg[i] & 0xffff);
1690 }
37f88e84
MB		 1691
1692 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1693 pdata->micdet_cfg);
1694
1695 /* Microphone detection needs the WSEQ clock */
1696 if (pdata->micdet_cfg)
1697 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1698 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1699
1700 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1701 }
8abd16a6 1702
f0fba2ad 1703 if (wm8903->irq) {
8abd16a6
MB		 1704 if (pdata && pdata->irq_active_low) {
1705 trigger = IRQF_TRIGGER_LOW;
1706 irq_pol = WM8903_IRQ_POL;
1707 } else {
1708 trigger = IRQF_TRIGGER_HIGH;
1709 irq_pol = 0;
1710 }
1711
1712 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1713 WM8903_IRQ_POL, irq_pol);
1714
f0fba2ad 1715 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1716 trigger | IRQF_ONESHOT,
f0fba2ad 1717 "wm8903", codec);
8abd16a6 1718 if (ret != 0) {
f0fba2ad 1719 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1720 ret);
f0fba2ad 1721 return ret;
8abd16a6
MB		 1722 }
1723
1724 /* Enable write sequencer interrupts */
1725 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1726 WM8903_IM_WSEQ_BUSY_EINT, 0);
1727 }
73b34ead 1728
f1c0a02f
MB		 1729 /* power on device */
1730 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1731
1732 /* Latch volume update bits */
8d50e447 1733 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1734 val |= WM8903_ADCVU;
8d50e447
MB		 1735 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1736 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1737
8d50e447 1738 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1739 val |= WM8903_DACVU;
8d50e447
MB		 1740 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1741 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1742
8d50e447 1743 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1744 val |= WM8903_HPOUTVU;
8d50e447
MB		 1745 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1746 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1747
8d50e447 1748 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1749 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1750 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1751 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1752
8d50e447 1753 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1754 val |= WM8903_SPKVU;
8d50e447
MB		 1755 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1756 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1757
1758 /* Enable DAC soft mute by default */
8d50e447 1759 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1760 val |= WM8903_DAC_MUTEMODE;
8d50e447 1761 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1762
f0fba2ad
LG		 1763 snd_soc_add_controls(codec, wm8903_snd_controls,
1764 ARRAY_SIZE(wm8903_snd_controls));
1765 wm8903_add_widgets(codec);
f1c0a02f 1766
f1c0a02f
MB		 1767 return ret;
1768}
1769
f0fba2ad
LG		 1770/* power down chip */
1771static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1772{
f0fba2ad
LG		 1773 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1774 return 0;
1775}
f1c0a02f 1776
f0fba2ad
LG		 1777static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1778 .probe = wm8903_probe,
1779 .remove = wm8903_remove,
1780 .suspend = wm8903_suspend,
1781 .resume = wm8903_resume,
1782 .set_bias_level = wm8903_set_bias_level,
1783 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1784 .reg_word_size = sizeof(u16),
1785 .reg_cache_default = wm8903_reg_defaults,
1786 .volatile_register = wm8903_volatile_register,
1787};
f1c0a02f 1788
f0fba2ad
LG		 1789#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1790static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1791 const struct i2c_device_id *id)
1792{
1793 struct wm8903_priv *wm8903;
1794 int ret;
f1c0a02f 1795
f0fba2ad
LG		 1796 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1797 if (wm8903 == NULL)
1798 return -ENOMEM;
8abd16a6 1799
f0fba2ad 1800 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1801 wm8903->irq = i2c->irq;
d58d5d55 1802
f0fba2ad
LG		 1803 ret = snd_soc_register_codec(&i2c->dev,
1804 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1805 if (ret < 0)
1806 kfree(wm8903);
1807 return ret;
1808}
f1c0a02f 1809
f0fba2ad
LG		 1810static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1811{
1812 snd_soc_unregister_codec(&client->dev);
1813 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1814 return 0;
1815}
1816
f1c0a02f 1817static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1818 { "wm8903", 0 },
1819 { }
f1c0a02f
MB		 1820};
1821MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1822
1823static struct i2c_driver wm8903_i2c_driver = {
1824 .driver = {
f0fba2ad 1825 .name = "wm8903-codec",
f1c0a02f
MB		 1826 .owner = THIS_MODULE,
1827 },
f0fba2ad
LG		 1828 .probe = wm8903_i2c_probe,
1829 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1830 .id_table = wm8903_i2c_id,
1831};
f0fba2ad 1832#endif
f1c0a02f 1833
f0fba2ad 1834static int __init wm8903_modinit(void)
f1c0a02f 1835{
f1c0a02f 1836 int ret = 0;
f0fba2ad
LG		 1837#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1838 ret = i2c_add_driver(&wm8903_i2c_driver);
1839 if (ret != 0) {
1840 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1841 ret);
f1c0a02f 1842 }
f0fba2ad 1843#endif
f1c0a02f 1844 return ret;
64089b84
MB		 1845}
1846module_init(wm8903_modinit);
1847
1848static void __exit wm8903_exit(void)
1849{
f0fba2ad 1850#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1851 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1852#endif
64089b84
MB		 1853}
1854module_exit(wm8903_exit);
1855
f1c0a02f
MB		 1856MODULE_DESCRIPTION("ASoC WM8903 driver");
1857MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1858MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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