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ASoC: Allow disabling of WM835x jack detection
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
25#include <sound/core.h>
7245387e 26#include <sound/jack.h>
f1c0a02f
MB		 27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
f1c0a02f
MB		 34
35#include "wm8903.h"
36
f1c0a02f
MB		 37/* Register defaults at reset */
38static u16 wm8903_reg_defaults[] = {
39 0x8903, /* R0 - SW Reset and ID */
40 0x0000, /* R1 - Revision Number */
41 0x0000, /* R2 */
42 0x0000, /* R3 */
43 0x0018, /* R4 - Bias Control 0 */
44 0x0000, /* R5 - VMID Control 0 */
45 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0000, /* R7 */
47 0x0001, /* R8 - Analogue DAC 0 */
48 0x0000, /* R9 */
49 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R11 */
51 0x0000, /* R12 - Power Management 0 */
52 0x0000, /* R13 - Power Management 1 */
53 0x0000, /* R14 - Power Management 2 */
54 0x0000, /* R15 - Power Management 3 */
55 0x0000, /* R16 - Power Management 4 */
56 0x0000, /* R17 - Power Management 5 */
57 0x0000, /* R18 - Power Management 6 */
58 0x0000, /* R19 */
59 0x0400, /* R20 - Clock Rates 0 */
60 0x0D07, /* R21 - Clock Rates 1 */
61 0x0000, /* R22 - Clock Rates 2 */
62 0x0000, /* R23 */
63 0x0050, /* R24 - Audio Interface 0 */
64 0x0242, /* R25 - Audio Interface 1 */
65 0x0008, /* R26 - Audio Interface 2 */
66 0x0022, /* R27 - Audio Interface 3 */
67 0x0000, /* R28 */
68 0x0000, /* R29 */
69 0x00C0, /* R30 - DAC Digital Volume Left */
70 0x00C0, /* R31 - DAC Digital Volume Right */
71 0x0000, /* R32 - DAC Digital 0 */
72 0x0000, /* R33 - DAC Digital 1 */
73 0x0000, /* R34 */
74 0x0000, /* R35 */
75 0x00C0, /* R36 - ADC Digital Volume Left */
76 0x00C0, /* R37 - ADC Digital Volume Right */
77 0x0000, /* R38 - ADC Digital 0 */
78 0x0073, /* R39 - Digital Microphone 0 */
79 0x09BF, /* R40 - DRC 0 */
80 0x3241, /* R41 - DRC 1 */
81 0x0020, /* R42 - DRC 2 */
82 0x0000, /* R43 - DRC 3 */
83 0x0085, /* R44 - Analogue Left Input 0 */
84 0x0085, /* R45 - Analogue Right Input 0 */
85 0x0044, /* R46 - Analogue Left Input 1 */
86 0x0044, /* R47 - Analogue Right Input 1 */
87 0x0000, /* R48 */
88 0x0000, /* R49 */
89 0x0008, /* R50 - Analogue Left Mix 0 */
90 0x0004, /* R51 - Analogue Right Mix 0 */
91 0x0000, /* R52 - Analogue Spk Mix Left 0 */
92 0x0000, /* R53 - Analogue Spk Mix Left 1 */
93 0x0000, /* R54 - Analogue Spk Mix Right 0 */
94 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x0000, /* R56 */
96 0x002D, /* R57 - Analogue OUT1 Left */
97 0x002D, /* R58 - Analogue OUT1 Right */
98 0x0039, /* R59 - Analogue OUT2 Left */
99 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0100, /* R61 */
101 0x0139, /* R62 - Analogue OUT3 Left */
102 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R64 */
104 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0000, /* R66 */
106 0x0010, /* R67 - DC Servo 0 */
107 0x0100, /* R68 */
108 0x00A4, /* R69 - DC Servo 2 */
109 0x0807, /* R70 */
110 0x0000, /* R71 */
111 0x0000, /* R72 */
112 0x0000, /* R73 */
113 0x0000, /* R74 */
114 0x0000, /* R75 */
115 0x0000, /* R76 */
116 0x0000, /* R77 */
117 0x0000, /* R78 */
118 0x000E, /* R79 */
119 0x0000, /* R80 */
120 0x0000, /* R81 */
121 0x0000, /* R82 */
122 0x0000, /* R83 */
123 0x0000, /* R84 */
124 0x0000, /* R85 */
125 0x0000, /* R86 */
126 0x0006, /* R87 */
127 0x0000, /* R88 */
128 0x0000, /* R89 */
129 0x0000, /* R90 - Analogue HP 0 */
130 0x0060, /* R91 */
131 0x0000, /* R92 */
132 0x0000, /* R93 */
133 0x0000, /* R94 - Analogue Lineout 0 */
134 0x0060, /* R95 */
135 0x0000, /* R96 */
136 0x0000, /* R97 */
137 0x0000, /* R98 - Charge Pump 0 */
138 0x1F25, /* R99 */
139 0x2B19, /* R100 */
140 0x01C0, /* R101 */
141 0x01EF, /* R102 */
142 0x2B00, /* R103 */
143 0x0000, /* R104 - Class W 0 */
144 0x01C0, /* R105 */
145 0x1C10, /* R106 */
146 0x0000, /* R107 */
147 0x0000, /* R108 - Write Sequencer 0 */
148 0x0000, /* R109 - Write Sequencer 1 */
149 0x0000, /* R110 - Write Sequencer 2 */
150 0x0000, /* R111 - Write Sequencer 3 */
151 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R113 */
153 0x0000, /* R114 - Control Interface */
154 0x0000, /* R115 */
155 0x00A8, /* R116 - GPIO Control 1 */
156 0x00A8, /* R117 - GPIO Control 2 */
157 0x00A8, /* R118 - GPIO Control 3 */
158 0x0220, /* R119 - GPIO Control 4 */
159 0x01A0, /* R120 - GPIO Control 5 */
160 0x0000, /* R121 - Interrupt Status 1 */
161 0xFFFF, /* R122 - Interrupt Status 1 Mask */
162 0x0000, /* R123 - Interrupt Polarity 1 */
163 0x0000, /* R124 */
164 0x0003, /* R125 */
165 0x0000, /* R126 - Interrupt Control */
166 0x0000, /* R127 */
167 0x0005, /* R128 */
168 0x0000, /* R129 - Control Interface Test 1 */
169 0x0000, /* R130 */
170 0x0000, /* R131 */
171 0x0000, /* R132 */
172 0x0000, /* R133 */
173 0x0000, /* R134 */
174 0x03FF, /* R135 */
175 0x0007, /* R136 */
176 0x0040, /* R137 */
177 0x0000, /* R138 */
178 0x0000, /* R139 */
179 0x0000, /* R140 */
180 0x0000, /* R141 */
181 0x0000, /* R142 */
182 0x0000, /* R143 */
183 0x0000, /* R144 */
184 0x0000, /* R145 */
185 0x0000, /* R146 */
186 0x0000, /* R147 */
187 0x4000, /* R148 */
188 0x6810, /* R149 - Charge Pump Test 1 */
189 0x0004, /* R150 */
190 0x0000, /* R151 */
191 0x0000, /* R152 */
192 0x0000, /* R153 */
193 0x0000, /* R154 */
194 0x0000, /* R155 */
195 0x0000, /* R156 */
196 0x0000, /* R157 */
197 0x0000, /* R158 */
198 0x0000, /* R159 */
199 0x0000, /* R160 */
200 0x0000, /* R161 */
201 0x0000, /* R162 */
202 0x0000, /* R163 */
203 0x0028, /* R164 - Clock Rate Test 4 */
204 0x0004, /* R165 */
205 0x0000, /* R166 */
206 0x0060, /* R167 */
207 0x0000, /* R168 */
208 0x0000, /* R169 */
209 0x0000, /* R170 */
210 0x0000, /* R171 */
211 0x0000, /* R172 - Analogue Output Bias 0 */
212};
213
d58d5d55
MB		 214struct wm8903_priv {
215 struct snd_soc_codec codec;
216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk;
219
220 /* Reference counts */
d58d5d55
MB		 221 int class_w_users;
222 int playback_active;
223 int capture_active;
224
8abd16a6
MB		 225 struct completion wseq;
226
7245387e
MB		 227 struct snd_soc_jack *mic_jack;
228 int mic_det;
229 int mic_short;
230 int mic_last_report;
231 int mic_delay;
232
d58d5d55
MB		 233 struct snd_pcm_substream *master_substream;
234 struct snd_pcm_substream *slave_substream;
235};
236
8d50e447 237static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 238{
239 switch (reg) {
240 case WM8903_SW_RESET_AND_ID:
241 case WM8903_REVISION_NUMBER:
242 case WM8903_INTERRUPT_STATUS_1:
243 case WM8903_WRITE_SEQUENCER_4:
8d50e447 244 return 1;
f1c0a02f
MB		 245
246 default:
f1c0a02f 247 return 0;
8d50e447 248 }
f1c0a02f
MB		 249}
250
251static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
252{
253 u16 reg[5];
254 struct i2c_client *i2c = codec->control_data;
8abd16a6 255 struct wm8903_priv *wm8903 = codec->private_data;
f1c0a02f
MB		 256
257 BUG_ON(start > 48);
258
37f88e84 259 /* Enable the sequencer if it's not already on */
8d50e447 260 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 261 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
262 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f
MB		 263
264 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
265
8d50e447 266 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 267 start | WM8903_WSEQ_START);
268
269 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 270 * that will break us out of the poll early.
f1c0a02f
MB		 271 */
272 do {
8abd16a6
MB		 273 wait_for_completion_timeout(&wm8903->wseq,
274 msecs_to_jiffies(10));
f1c0a02f 275
8d50e447 276 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 277 } while (reg[4] & WM8903_WSEQ_BUSY);
278
279 dev_dbg(&i2c->dev, "Sequence complete\n");
280
37f88e84
MB		 281 /* Disable the sequencer again if we enabled it */
282 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 283
284 return 0;
285}
286
287static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
288{
289 int i;
290
291 /* There really ought to be something better we can do here :/ */
292 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 293 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 294}
295
296static void wm8903_reset(struct snd_soc_codec *codec)
297{
8d50e447 298 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 299 memcpy(codec->reg_cache, wm8903_reg_defaults,
300 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 301}
302
303#define WM8903_OUTPUT_SHORT 0x8
304#define WM8903_OUTPUT_OUT 0x4
305#define WM8903_OUTPUT_INT 0x2
306#define WM8903_OUTPUT_IN 0x1
307
42768a12
MB		 308static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
309 struct snd_kcontrol *kcontrol, int event)
310{
311 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
312 mdelay(4);
313
314 return 0;
315}
316
f1c0a02f
MB		 317/*
318 * Event for headphone and line out amplifier power changes. Special
319 * power up/down sequences are required in order to maximise pop/click
320 * performance.
321 */
322static int wm8903_output_event(struct snd_soc_dapm_widget *w,
323 struct snd_kcontrol *kcontrol, int event)
324{
325 struct snd_soc_codec *codec = w->codec;
f1c0a02f 326 u16 val;
0bc286e2 327 u16 reg;
d7d5c547
MB		 328 u16 dcs_reg;
329 u16 dcs_bit;
0bc286e2 330 int shift;
f1c0a02f
MB		 331
332 switch (w->reg) {
333 case WM8903_POWER_MANAGEMENT_2:
334 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 335 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 336 break;
337 case WM8903_POWER_MANAGEMENT_3:
338 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 339 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 340 break;
341 default:
342 BUG();
1e297a19 343 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 344 }
345
346 switch (w->shift) {
347 case 0:
348 shift = 0;
349 break;
350 case 1:
351 shift = 4;
352 break;
353 default:
354 BUG();
1e297a19 355 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 356 }
357
358 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 359 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 360
361 /* Short the output */
362 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 363 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 364 }
365
366 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 367 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 368
369 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 370 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 371
372 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 373 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 374
375 /* Turn on the output ENA_OUTP */
376 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 377 snd_soc_write(codec, reg, val);
f1c0a02f 378
d7d5c547 379 /* Enable the DC servo */
8d50e447 380 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 381 dcs_reg |= dcs_bit;
8d50e447 382 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 383
f1c0a02f
MB		 384 /* Remove the short */
385 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 386 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 387 }
388
389 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 390 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 391
392 /* Short the output */
393 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 394 snd_soc_write(codec, reg, val);
f1c0a02f 395
d7d5c547 396 /* Disable the DC servo */
8d50e447 397 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 398 dcs_reg &= ~dcs_bit;
8d50e447 399 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 400
f1c0a02f
MB		 401 /* Then disable the intermediate and output stages */
402 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
403 WM8903_OUTPUT_IN) << shift);
8d50e447 404 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 405 }
406
f1c0a02f
MB		 407 return 0;
408}
409
410/*
411 * When used with DAC outputs only the WM8903 charge pump supports
412 * operation in class W mode, providing very low power consumption
413 * when used with digital sources. Enable and disable this mode
414 * automatically depending on the mixer configuration.
415 *
416 * All the relevant controls are simple switches.
417 */
418static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
422 struct snd_soc_codec *codec = widget->codec;
423 struct wm8903_priv *wm8903 = codec->private_data;
424 struct i2c_client *i2c = codec->control_data;
425 u16 reg;
426 int ret;
427
8d50e447 428 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 429
430 /* Turn it off if we're about to enable bypass */
431 if (ucontrol->value.integer.value[0]) {
432 if (wm8903->class_w_users == 0) {
433 dev_dbg(&i2c->dev, "Disabling Class W\n");
8d50e447 434 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 435 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
436 }
437 wm8903->class_w_users++;
438 }
439
440 /* Implement the change */
441 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
442
443 /* If we've just disabled the last bypass path turn Class W on */
444 if (!ucontrol->value.integer.value[0]) {
445 if (wm8903->class_w_users == 1) {
446 dev_dbg(&i2c->dev, "Enabling Class W\n");
8d50e447 447 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 448 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
449 }
450 wm8903->class_w_users--;
451 }
452
453 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
454 wm8903->class_w_users);
455
456 return ret;
457}
458
459#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
460{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
461 .info = snd_soc_info_volsw, \
462 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
463 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
464
465
466/* ALSA can only do steps of .01dB */
467static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
468
291ce18c 469static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 470static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
471
472static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
473static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
474static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
475static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
476static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
477
478static const char *drc_slope_text[] = {
479 "1", "1/2", "1/4", "1/8", "1/16", "0"
480};
481
482static const struct soc_enum drc_slope_r0 =
483 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
484
485static const struct soc_enum drc_slope_r1 =
486 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
487
488static const char *drc_attack_text[] = {
489 "instantaneous",
490 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
491 "46.4ms", "92.8ms", "185.6ms"
492};
493
494static const struct soc_enum drc_attack =
495 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
496
497static const char *drc_decay_text[] = {
498 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
499 "23.87s", "47.56s"
500};
501
502static const struct soc_enum drc_decay =
503 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
504
505static const char *drc_ff_delay_text[] = {
506 "5 samples", "9 samples"
507};
508
509static const struct soc_enum drc_ff_delay =
510 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
511
512static const char *drc_qr_decay_text[] = {
513 "0.725ms", "1.45ms", "5.8ms"
514};
515
516static const struct soc_enum drc_qr_decay =
517 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
518
519static const char *drc_smoothing_text[] = {
520 "Low", "Medium", "High"
521};
522
523static const struct soc_enum drc_smoothing =
524 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
525
526static const char *soft_mute_text[] = {
527 "Fast (fs/2)", "Slow (fs/32)"
528};
529
530static const struct soc_enum soft_mute =
531 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
532
533static const char *mute_mode_text[] = {
534 "Hard", "Soft"
535};
536
537static const struct soc_enum mute_mode =
538 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
539
540static const char *dac_deemphasis_text[] = {
541 "Disabled", "32kHz", "44.1kHz", "48kHz"
542};
543
544static const struct soc_enum dac_deemphasis =
545 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
546
547static const char *companding_text[] = {
548 "ulaw", "alaw"
549};
550
551static const struct soc_enum dac_companding =
552 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
553
554static const struct soc_enum adc_companding =
555 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
556
557static const char *input_mode_text[] = {
558 "Single-Ended", "Differential Line", "Differential Mic"
559};
560
561static const struct soc_enum linput_mode_enum =
562 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
563
564static const struct soc_enum rinput_mode_enum =
565 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
566
567static const char *linput_mux_text[] = {
568 "IN1L", "IN2L", "IN3L"
569};
570
571static const struct soc_enum linput_enum =
572 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
573
574static const struct soc_enum linput_inv_enum =
575 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
576
577static const char *rinput_mux_text[] = {
578 "IN1R", "IN2R", "IN3R"
579};
580
581static const struct soc_enum rinput_enum =
582 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
583
584static const struct soc_enum rinput_inv_enum =
585 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
586
587
291ce18c
MB		 588static const char *sidetone_text[] = {
589 "None", "Left", "Right"
590};
591
592static const struct soc_enum lsidetone_enum =
593 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
594
595static const struct soc_enum rsidetone_enum =
596 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
597
f1c0a02f
MB		 598static const struct snd_kcontrol_new wm8903_snd_controls[] = {
599
600/* Input PGAs - No TLV since the scale depends on PGA mode */
601SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 602 7, 1, 1),
f1c0a02f
MB		 603SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
604 0, 31, 0),
605SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
606 6, 1, 0),
607
608SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 609 7, 1, 1),
f1c0a02f
MB		 610SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
611 0, 31, 0),
612SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
613 6, 1, 0),
614
615/* ADCs */
616SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
617SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
618SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 619SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 620 drc_tlv_thresh),
621SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
622SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
623SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
624SOC_ENUM("DRC Attack Rate", drc_attack),
625SOC_ENUM("DRC Decay Rate", drc_decay),
626SOC_ENUM("DRC FF Delay", drc_ff_delay),
627SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
628SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 629SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 630SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
631SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
632SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 633SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 634SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
635
636SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
637 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
638SOC_ENUM("ADC Companding Mode", adc_companding),
639SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
640
291ce18c
MB		 641SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
642 12, 0, digital_sidetone_tlv),
643
f1c0a02f
MB		 644/* DAC */
645SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
646 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
647SOC_ENUM("DAC Soft Mute Rate", soft_mute),
648SOC_ENUM("DAC Mute Mode", mute_mode),
649SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
650SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 651SOC_ENUM("DAC Companding Mode", dac_companding),
652SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
653
654/* Headphones */
655SOC_DOUBLE_R("Headphone Switch",
656 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
657 8, 1, 1),
658SOC_DOUBLE_R("Headphone ZC Switch",
659 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
660 6, 1, 0),
661SOC_DOUBLE_R_TLV("Headphone Volume",
662 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
663 0, 63, 0, out_tlv),
664
665/* Line out */
666SOC_DOUBLE_R("Line Out Switch",
667 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
668 8, 1, 1),
669SOC_DOUBLE_R("Line Out ZC Switch",
670 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
671 6, 1, 0),
672SOC_DOUBLE_R_TLV("Line Out Volume",
673 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
674 0, 63, 0, out_tlv),
675
676/* Speaker */
677SOC_DOUBLE_R("Speaker Switch",
678 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
679SOC_DOUBLE_R("Speaker ZC Switch",
680 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
681SOC_DOUBLE_R_TLV("Speaker Volume",
682 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
683 0, 63, 0, out_tlv),
684};
685
f1c0a02f
MB		 686static const struct snd_kcontrol_new linput_mode_mux =
687 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
688
689static const struct snd_kcontrol_new rinput_mode_mux =
690 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
691
692static const struct snd_kcontrol_new linput_mux =
693 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
694
695static const struct snd_kcontrol_new linput_inv_mux =
696 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
697
698static const struct snd_kcontrol_new rinput_mux =
699 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
700
701static const struct snd_kcontrol_new rinput_inv_mux =
702 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
703
291ce18c
MB		 704static const struct snd_kcontrol_new lsidetone_mux =
705 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
706
707static const struct snd_kcontrol_new rsidetone_mux =
708 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
709
f1c0a02f
MB		 710static const struct snd_kcontrol_new left_output_mixer[] = {
711SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
712SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
713SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 714SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 715};
716
717static const struct snd_kcontrol_new right_output_mixer[] = {
718SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
719SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
720SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 721SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 722};
723
724static const struct snd_kcontrol_new left_speaker_mixer[] = {
725SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
726SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
727SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
728SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 729 0, 1, 0),
f1c0a02f
MB		 730};
731
732static const struct snd_kcontrol_new right_speaker_mixer[] = {
733SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
734SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
735SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
736 1, 1, 0),
737SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 738 0, 1, 0),
f1c0a02f
MB		 739};
740
741static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
742SND_SOC_DAPM_INPUT("IN1L"),
743SND_SOC_DAPM_INPUT("IN1R"),
744SND_SOC_DAPM_INPUT("IN2L"),
745SND_SOC_DAPM_INPUT("IN2R"),
746SND_SOC_DAPM_INPUT("IN3L"),
747SND_SOC_DAPM_INPUT("IN3R"),
748
749SND_SOC_DAPM_OUTPUT("HPOUTL"),
750SND_SOC_DAPM_OUTPUT("HPOUTR"),
751SND_SOC_DAPM_OUTPUT("LINEOUTL"),
752SND_SOC_DAPM_OUTPUT("LINEOUTR"),
753SND_SOC_DAPM_OUTPUT("LOP"),
754SND_SOC_DAPM_OUTPUT("LON"),
755SND_SOC_DAPM_OUTPUT("ROP"),
756SND_SOC_DAPM_OUTPUT("RON"),
757
758SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
759
760SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
761SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
762 &linput_inv_mux),
763SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
764
765SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
766SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
767 &rinput_inv_mux),
768SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
769
770SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
771SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
772
773SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
774SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
775
291ce18c
MB		 776SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
777SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
778
f1c0a02f
MB		 779SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
780SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
781
782SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
783 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
784SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
785 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
786
787SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
788 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
789SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
790 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
791
792SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
793 1, 0, NULL, 0, wm8903_output_event,
794 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 795 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 796SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
797 0, 0, NULL, 0, wm8903_output_event,
798 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 799 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 800
801SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
802 NULL, 0, wm8903_output_event,
803 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 804 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 805SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
806 NULL, 0, wm8903_output_event,
807 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 808 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 809
810SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
811 NULL, 0),
812SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
813 NULL, 0),
814
42768a12
MB		 815SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
816 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 817SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 818};
819
820static const struct snd_soc_dapm_route intercon[] = {
821
822 { "Left Input Mux", "IN1L", "IN1L" },
823 { "Left Input Mux", "IN2L", "IN2L" },
824 { "Left Input Mux", "IN3L", "IN3L" },
825
826 { "Left Input Inverting Mux", "IN1L", "IN1L" },
827 { "Left Input Inverting Mux", "IN2L", "IN2L" },
828 { "Left Input Inverting Mux", "IN3L", "IN3L" },
829
830 { "Right Input Mux", "IN1R", "IN1R" },
831 { "Right Input Mux", "IN2R", "IN2R" },
832 { "Right Input Mux", "IN3R", "IN3R" },
833
834 { "Right Input Inverting Mux", "IN1R", "IN1R" },
835 { "Right Input Inverting Mux", "IN2R", "IN2R" },
836 { "Right Input Inverting Mux", "IN3R", "IN3R" },
837
838 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
839 { "Left Input Mode Mux", "Differential Line",
840 "Left Input Mux" },
841 { "Left Input Mode Mux", "Differential Line",
842 "Left Input Inverting Mux" },
843 { "Left Input Mode Mux", "Differential Mic",
844 "Left Input Mux" },
845 { "Left Input Mode Mux", "Differential Mic",
846 "Left Input Inverting Mux" },
847
848 { "Right Input Mode Mux", "Single-Ended",
849 "Right Input Inverting Mux" },
850 { "Right Input Mode Mux", "Differential Line",
851 "Right Input Mux" },
852 { "Right Input Mode Mux", "Differential Line",
853 "Right Input Inverting Mux" },
854 { "Right Input Mode Mux", "Differential Mic",
855 "Right Input Mux" },
856 { "Right Input Mode Mux", "Differential Mic",
857 "Right Input Inverting Mux" },
858
859 { "Left Input PGA", NULL, "Left Input Mode Mux" },
860 { "Right Input PGA", NULL, "Right Input Mode Mux" },
861
862 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 863 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 864 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 865 { "ADCR", NULL, "CLK_DSP" },
866
291ce18c
MB		 867 { "DACL Sidetone", "Left", "ADCL" },
868 { "DACL Sidetone", "Right", "ADCR" },
869 { "DACR Sidetone", "Left", "ADCL" },
870 { "DACR Sidetone", "Right", "ADCR" },
871
872 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 873 { "DACL", NULL, "CLK_DSP" },
291ce18c 874 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 875 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 876
877 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
878 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
879 { "Left Output Mixer", "DACL Switch", "DACL" },
880 { "Left Output Mixer", "DACR Switch", "DACR" },
881
882 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
883 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
884 { "Right Output Mixer", "DACL Switch", "DACL" },
885 { "Right Output Mixer", "DACR Switch", "DACR" },
886
887 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
888 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
889 { "Left Speaker Mixer", "DACL Switch", "DACL" },
890 { "Left Speaker Mixer", "DACR Switch", "DACR" },
891
892 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
893 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
894 { "Right Speaker Mixer", "DACL Switch", "DACL" },
895 { "Right Speaker Mixer", "DACR Switch", "DACR" },
896
897 { "Left Line Output PGA", NULL, "Left Output Mixer" },
898 { "Right Line Output PGA", NULL, "Right Output Mixer" },
899
900 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
901 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
902
903 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
904 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
905
906 { "HPOUTL", NULL, "Left Headphone Output PGA" },
907 { "HPOUTR", NULL, "Right Headphone Output PGA" },
908
909 { "LINEOUTL", NULL, "Left Line Output PGA" },
910 { "LINEOUTR", NULL, "Right Line Output PGA" },
911
912 { "LOP", NULL, "Left Speaker PGA" },
913 { "LON", NULL, "Left Speaker PGA" },
914
915 { "ROP", NULL, "Right Speaker PGA" },
916 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 917
918 { "Left Headphone Output PGA", NULL, "Charge Pump" },
919 { "Right Headphone Output PGA", NULL, "Charge Pump" },
920 { "Left Line Output PGA", NULL, "Charge Pump" },
921 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 922};
923
924static int wm8903_add_widgets(struct snd_soc_codec *codec)
925{
926 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
927 ARRAY_SIZE(wm8903_dapm_widgets));
928
929 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
930
f1c0a02f
MB		 931 return 0;
932}
933
934static int wm8903_set_bias_level(struct snd_soc_codec *codec,
935 enum snd_soc_bias_level level)
936{
937 struct i2c_client *i2c = codec->control_data;
938 u16 reg, reg2;
939
940 switch (level) {
941 case SND_SOC_BIAS_ON:
942 case SND_SOC_BIAS_PREPARE:
8d50e447 943 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 944 reg &= ~(WM8903_VMID_RES_MASK);
945 reg |= WM8903_VMID_RES_50K;
8d50e447 946 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 947 break;
948
949 case SND_SOC_BIAS_STANDBY:
950 if (codec->bias_level == SND_SOC_BIAS_OFF) {
8d50e447 951 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 952 WM8903_CLK_SYS_ENA);
953
4dbfe809 954 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 955 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
956 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
957 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 958
f1c0a02f
MB		 959 wm8903_run_sequence(codec, 0);
960 wm8903_sync_reg_cache(codec, codec->reg_cache);
961
962 /* Enable low impedence charge pump output */
8d50e447 963 reg = snd_soc_read(codec,
f1c0a02f 964 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 965 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 966 reg | WM8903_TEST_KEY);
8d50e447
MB		 967 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
968 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 969 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 970 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 971 reg);
972
973 /* By default no bypass paths are enabled so
974 * enable Class W support.
975 */
976 dev_dbg(&i2c->dev, "Enabling Class W\n");
8d50e447 977 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 978 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
979 }
980
8d50e447 981 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 982 reg &= ~(WM8903_VMID_RES_MASK);
983 reg |= WM8903_VMID_RES_250K;
8d50e447 984 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 985 break;
986
987 case SND_SOC_BIAS_OFF:
988 wm8903_run_sequence(codec, 32);
8d50e447 989 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 990 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 991 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 992 break;
993 }
994
995 codec->bias_level = level;
996
997 return 0;
998}
999
1000static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1001 int clk_id, unsigned int freq, int dir)
1002{
1003 struct snd_soc_codec *codec = codec_dai->codec;
1004 struct wm8903_priv *wm8903 = codec->private_data;
1005
1006 wm8903->sysclk = freq;
1007
1008 return 0;
1009}
1010
1011static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1012 unsigned int fmt)
1013{
1014 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1015 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1016
1017 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1018 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1019
1020 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1021 case SND_SOC_DAIFMT_CBS_CFS:
1022 break;
1023 case SND_SOC_DAIFMT_CBS_CFM:
1024 aif1 |= WM8903_LRCLK_DIR;
1025 break;
1026 case SND_SOC_DAIFMT_CBM_CFM:
1027 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1028 break;
1029 case SND_SOC_DAIFMT_CBM_CFS:
1030 aif1 |= WM8903_BCLK_DIR;
1031 break;
1032 default:
1033 return -EINVAL;
1034 }
1035
1036 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1037 case SND_SOC_DAIFMT_DSP_A:
1038 aif1 |= 0x3;
1039 break;
1040 case SND_SOC_DAIFMT_DSP_B:
1041 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1042 break;
1043 case SND_SOC_DAIFMT_I2S:
1044 aif1 |= 0x2;
1045 break;
1046 case SND_SOC_DAIFMT_RIGHT_J:
1047 aif1 |= 0x1;
1048 break;
1049 case SND_SOC_DAIFMT_LEFT_J:
1050 break;
1051 default:
1052 return -EINVAL;
1053 }
1054
1055 /* Clock inversion */
1056 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1057 case SND_SOC_DAIFMT_DSP_A:
1058 case SND_SOC_DAIFMT_DSP_B:
1059 /* frame inversion not valid for DSP modes */
1060 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1061 case SND_SOC_DAIFMT_NB_NF:
1062 break;
1063 case SND_SOC_DAIFMT_IB_NF:
1064 aif1 |= WM8903_AIF_BCLK_INV;
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069 break;
1070 case SND_SOC_DAIFMT_I2S:
1071 case SND_SOC_DAIFMT_RIGHT_J:
1072 case SND_SOC_DAIFMT_LEFT_J:
1073 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1074 case SND_SOC_DAIFMT_NB_NF:
1075 break;
1076 case SND_SOC_DAIFMT_IB_IF:
1077 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1078 break;
1079 case SND_SOC_DAIFMT_IB_NF:
1080 aif1 |= WM8903_AIF_BCLK_INV;
1081 break;
1082 case SND_SOC_DAIFMT_NB_IF:
1083 aif1 |= WM8903_AIF_LRCLK_INV;
1084 break;
1085 default:
1086 return -EINVAL;
1087 }
1088 break;
1089 default:
1090 return -EINVAL;
1091 }
1092
8d50e447 1093 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1094
1095 return 0;
1096}
1097
1098static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1099{
1100 struct snd_soc_codec *codec = codec_dai->codec;
1101 u16 reg;
1102
8d50e447 1103 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1104
1105 if (mute)
1106 reg |= WM8903_DAC_MUTE;
1107 else
1108 reg &= ~WM8903_DAC_MUTE;
1109
8d50e447 1110 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1111
1112 return 0;
1113}
1114
1115/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1116 * for optimal performance so we list the lower rates first and match
1117 * on the last match we find. */
1118static struct {
1119 int div;
1120 int rate;
1121 int mode;
1122 int mclk_div;
1123} clk_sys_ratios[] = {
1124 { 64, 0x0, 0x0, 1 },
1125 { 68, 0x0, 0x1, 1 },
1126 { 125, 0x0, 0x2, 1 },
1127 { 128, 0x1, 0x0, 1 },
1128 { 136, 0x1, 0x1, 1 },
1129 { 192, 0x2, 0x0, 1 },
1130 { 204, 0x2, 0x1, 1 },
1131
1132 { 64, 0x0, 0x0, 2 },
1133 { 68, 0x0, 0x1, 2 },
1134 { 125, 0x0, 0x2, 2 },
1135 { 128, 0x1, 0x0, 2 },
1136 { 136, 0x1, 0x1, 2 },
1137 { 192, 0x2, 0x0, 2 },
1138 { 204, 0x2, 0x1, 2 },
1139
1140 { 250, 0x2, 0x2, 1 },
1141 { 256, 0x3, 0x0, 1 },
1142 { 272, 0x3, 0x1, 1 },
1143 { 384, 0x4, 0x0, 1 },
1144 { 408, 0x4, 0x1, 1 },
1145 { 375, 0x4, 0x2, 1 },
1146 { 512, 0x5, 0x0, 1 },
1147 { 544, 0x5, 0x1, 1 },
1148 { 500, 0x5, 0x2, 1 },
1149 { 768, 0x6, 0x0, 1 },
1150 { 816, 0x6, 0x1, 1 },
1151 { 750, 0x6, 0x2, 1 },
1152 { 1024, 0x7, 0x0, 1 },
1153 { 1088, 0x7, 0x1, 1 },
1154 { 1000, 0x7, 0x2, 1 },
1155 { 1408, 0x8, 0x0, 1 },
1156 { 1496, 0x8, 0x1, 1 },
1157 { 1536, 0x9, 0x0, 1 },
1158 { 1632, 0x9, 0x1, 1 },
1159 { 1500, 0x9, 0x2, 1 },
1160
1161 { 250, 0x2, 0x2, 2 },
1162 { 256, 0x3, 0x0, 2 },
1163 { 272, 0x3, 0x1, 2 },
1164 { 384, 0x4, 0x0, 2 },
1165 { 408, 0x4, 0x1, 2 },
1166 { 375, 0x4, 0x2, 2 },
1167 { 512, 0x5, 0x0, 2 },
1168 { 544, 0x5, 0x1, 2 },
1169 { 500, 0x5, 0x2, 2 },
1170 { 768, 0x6, 0x0, 2 },
1171 { 816, 0x6, 0x1, 2 },
1172 { 750, 0x6, 0x2, 2 },
1173 { 1024, 0x7, 0x0, 2 },
1174 { 1088, 0x7, 0x1, 2 },
1175 { 1000, 0x7, 0x2, 2 },
1176 { 1408, 0x8, 0x0, 2 },
1177 { 1496, 0x8, 0x1, 2 },
1178 { 1536, 0x9, 0x0, 2 },
1179 { 1632, 0x9, 0x1, 2 },
1180 { 1500, 0x9, 0x2, 2 },
1181};
1182
1183/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1184static struct {
1185 int ratio;
1186 int div;
1187} bclk_divs[] = {
1188 { 10, 0 },
f1c0a02f
MB		 1189 { 20, 2 },
1190 { 30, 3 },
1191 { 40, 4 },
1192 { 50, 5 },
f1c0a02f
MB		 1193 { 60, 7 },
1194 { 80, 8 },
1195 { 100, 9 },
f1c0a02f
MB		 1196 { 120, 11 },
1197 { 160, 12 },
1198 { 200, 13 },
1199 { 220, 14 },
1200 { 240, 15 },
f1c0a02f
MB		 1201 { 300, 17 },
1202 { 320, 18 },
1203 { 440, 19 },
1204 { 480, 20 },
1205};
1206
1207/* Sample rates for DSP */
1208static struct {
1209 int rate;
1210 int value;
1211} sample_rates[] = {
1212 { 8000, 0 },
1213 { 11025, 1 },
1214 { 12000, 2 },
1215 { 16000, 3 },
1216 { 22050, 4 },
1217 { 24000, 5 },
1218 { 32000, 6 },
1219 { 44100, 7 },
1220 { 48000, 8 },
1221 { 88200, 9 },
1222 { 96000, 10 },
1223 { 0, 0 },
1224};
1225
dee89c4d
MB		 1226static int wm8903_startup(struct snd_pcm_substream *substream,
1227 struct snd_soc_dai *dai)
f1c0a02f
MB		 1228{
1229 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1230 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1231 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1232 struct wm8903_priv *wm8903 = codec->private_data;
1233 struct i2c_client *i2c = codec->control_data;
1234 struct snd_pcm_runtime *master_runtime;
1235
1236 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1237 wm8903->playback_active++;
1238 else
1239 wm8903->capture_active++;
1240
1241 /* The DAI has shared clocks so if we already have a playback or
1242 * capture going then constrain this substream to match it.
1243 */
1244 if (wm8903->master_substream) {
1245 master_runtime = wm8903->master_substream->runtime;
1246
727fb909
MB		 1247 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1248 master_runtime->sample_bits);
f1c0a02f
MB		 1249
1250 snd_pcm_hw_constraint_minmax(substream->runtime,
1251 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1252 master_runtime->sample_bits,
1253 master_runtime->sample_bits);
1254
1255 wm8903->slave_substream = substream;
1256 } else
1257 wm8903->master_substream = substream;
1258
1259 return 0;
1260}
1261
dee89c4d
MB		 1262static void wm8903_shutdown(struct snd_pcm_substream *substream,
1263 struct snd_soc_dai *dai)
f1c0a02f
MB		 1264{
1265 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1266 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1267 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1268 struct wm8903_priv *wm8903 = codec->private_data;
1269
1270 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1271 wm8903->playback_active--;
1272 else
1273 wm8903->capture_active--;
1274
1275 if (wm8903->master_substream == substream)
1276 wm8903->master_substream = wm8903->slave_substream;
1277
1278 wm8903->slave_substream = NULL;
1279}
1280
1281static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1282 struct snd_pcm_hw_params *params,
1283 struct snd_soc_dai *dai)
f1c0a02f
MB		 1284{
1285 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1286 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1287 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1288 struct wm8903_priv *wm8903 = codec->private_data;
1289 struct i2c_client *i2c = codec->control_data;
1290 int fs = params_rate(params);
1291 int bclk;
1292 int bclk_div;
1293 int i;
1294 int dsp_config;
1295 int clk_config;
1296 int best_val;
1297 int cur_val;
1298 int clk_sys;
1299
8d50e447
MB		 1300 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1301 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1302 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1303 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1304 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1305 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1306
1307 if (substream == wm8903->slave_substream) {
1308 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1309 return 0;
1310 }
1311
9e79261f
MB		 1312 /* Enable sloping stopband filter for low sample rates */
1313 if (fs <= 24000)
1314 dac_digital1 |= WM8903_DAC_SB_FILT;
1315 else
1316 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1317
f1c0a02f
MB		 1318 /* Configure sample rate logic for DSP - choose nearest rate */
1319 dsp_config = 0;
1320 best_val = abs(sample_rates[dsp_config].rate - fs);
1321 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1322 cur_val = abs(sample_rates[i].rate - fs);
1323 if (cur_val <= best_val) {
1324 dsp_config = i;
1325 best_val = cur_val;
1326 }
1327 }
1328
1329 /* Constraints should stop us hitting this but let's make sure */
1330 if (wm8903->capture_active)
1331 switch (sample_rates[dsp_config].rate) {
1332 case 88200:
1333 case 96000:
1334 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1335 fs);
1336 return -EINVAL;
1337
1338 default:
1339 break;
1340 }
1341
1342 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1343 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1344 clock1 |= sample_rates[dsp_config].value;
1345
1346 aif1 &= ~WM8903_AIF_WL_MASK;
1347 bclk = 2 * fs;
1348 switch (params_format(params)) {
1349 case SNDRV_PCM_FORMAT_S16_LE:
1350 bclk *= 16;
1351 break;
1352 case SNDRV_PCM_FORMAT_S20_3LE:
1353 bclk *= 20;
1354 aif1 |= 0x4;
1355 break;
1356 case SNDRV_PCM_FORMAT_S24_LE:
1357 bclk *= 24;
1358 aif1 |= 0x8;
1359 break;
1360 case SNDRV_PCM_FORMAT_S32_LE:
1361 bclk *= 32;
1362 aif1 |= 0xc;
1363 break;
1364 default:
1365 return -EINVAL;
1366 }
1367
1368 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1369 wm8903->sysclk, fs);
1370
1371 /* We may not have an MCLK which allows us to generate exactly
1372 * the clock we want, particularly with USB derived inputs, so
1373 * approximate.
1374 */
1375 clk_config = 0;
1376 best_val = abs((wm8903->sysclk /
1377 (clk_sys_ratios[0].mclk_div *
1378 clk_sys_ratios[0].div)) - fs);
1379 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1380 cur_val = abs((wm8903->sysclk /
1381 (clk_sys_ratios[i].mclk_div *
1382 clk_sys_ratios[i].div)) - fs);
1383
1384 if (cur_val <= best_val) {
1385 clk_config = i;
1386 best_val = cur_val;
1387 }
1388 }
1389
1390 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1391 clock0 |= WM8903_MCLKDIV2;
1392 clk_sys = wm8903->sysclk / 2;
1393 } else {
1394 clock0 &= ~WM8903_MCLKDIV2;
1395 clk_sys = wm8903->sysclk;
1396 }
1397
1398 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1399 WM8903_CLK_SYS_MODE_MASK);
1400 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1401 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1402
1403 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1404 clk_sys_ratios[clk_config].rate,
1405 clk_sys_ratios[clk_config].mode,
1406 clk_sys_ratios[clk_config].div);
1407
1408 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1409
1410 /* We may not get quite the right frequency if using
1411 * approximate clocks so look for the closest match that is
1412 * higher than the target (we need to ensure that there enough
1413 * BCLKs to clock out the samples).
1414 */
1415 bclk_div = 0;
1416 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1417 i = 1;
1418 while (i < ARRAY_SIZE(bclk_divs)) {
1419 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1420 if (cur_val < 0) /* BCLK table is sorted */
1421 break;
1422 bclk_div = i;
1423 best_val = cur_val;
1424 i++;
1425 }
1426
1427 aif2 &= ~WM8903_BCLK_DIV_MASK;
1428 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1429
1430 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1431 bclk_divs[bclk_div].ratio / 10, bclk,
1432 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1433
1434 aif2 |= bclk_divs[bclk_div].div;
1435 aif3 |= bclk / fs;
1436
8d50e447
MB		 1437 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1438 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1439 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1440 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1441 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1442 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1443
1444 return 0;
1445}
1446
7245387e
MB		 1447/**
1448 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1449 *
1450 * @codec: WM8903 codec
1451 * @jack: jack to report detection events on
1452 * @det: value to report for presence detection
1453 * @shrt: value to report for short detection
1454 *
1455 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1456 * being used to bring out signals to the processor then only platform
1457 * data configuration is needed for WM8903 and processor GPIOs should
1458 * be configured using snd_soc_jack_add_gpios() instead.
1459 *
1460 * The current threasholds for detection should be configured using
1461 * micdet_cfg in the platform data. Using this function will force on
1462 * the microphone bias for the device.
1463 */
1464int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1465 int det, int shrt)
1466{
1467 struct wm8903_priv *wm8903 = codec->private_data;
1468 int irq_mask = 0;
1469
1470 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1471 det, shrt);
1472
1473 /* Store the configuration */
1474 wm8903->mic_jack = jack;
1475 wm8903->mic_det = det;
1476 wm8903->mic_short = shrt;
1477
1478 /* Enable interrupts we've got a report configured for */
1479 if (det)
1480 irq_mask &= ~WM8903_MICDET_EINT;
1481 if (shrt)
1482 irq_mask &= ~WM8903_MICSHRT_EINT;
1483
1484 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1485 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1486 irq_mask);
1487
1488 /* Enable mic detection, this may not have been set through
1489 * platform data (eg, if the defaults are OK). */
1490 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1491 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1492 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1493 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1494
1495 /* Force the microphone bias on; this will trigger an initial
1496 * detection. */
1497 snd_soc_dapm_force_enable_pin(codec, "Mic Bias");
1498
1499 return 0;
1500}
1501EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1502
8abd16a6
MB		 1503static irqreturn_t wm8903_irq(int irq, void *data)
1504{
1505 struct wm8903_priv *wm8903 = data;
1506 struct snd_soc_codec *codec = &wm8903->codec;
7245387e
MB		 1507 int mic_report;
1508 int int_pol;
1509 int int_val = 0;
1510 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1511
7245387e 1512 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1513
7245387e 1514 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1515 dev_dbg(codec->dev, "Write sequencer done\n");
1516 complete(&wm8903->wseq);
1517 }
1518
7245387e
MB		 1519 /*
1520 * The rest is microphone jack detection. We need to manually
1521 * invert the polarity of the interrupt after each event - to
1522 * simplify the code keep track of the last state we reported
1523 * and just invert the relevant bits in both the report and
1524 * the polarity register.
1525 */
1526 mic_report = wm8903->mic_last_report;
1527 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1528
1529 if (int_val & WM8903_MICSHRT_EINT) {
1530 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1531
1532 mic_report ^= wm8903->mic_short;
1533 int_pol ^= WM8903_MICSHRT_INV;
1534 }
1535
1536 if (int_val & WM8903_MICDET_EINT) {
1537 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1538
1539 mic_report ^= wm8903->mic_det;
1540 int_pol ^= WM8903_MICDET_INV;
1541
1542 msleep(wm8903->mic_delay);
1543 }
1544
1545 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1546 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1547
1548 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1549 wm8903->mic_short | wm8903->mic_det);
1550
1551 wm8903->mic_last_report = mic_report;
1552
8abd16a6
MB		 1553 return IRQ_HANDLED;
1554}
1555
f1c0a02f
MB		 1556#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1557 SNDRV_PCM_RATE_11025 | \
1558 SNDRV_PCM_RATE_16000 | \
1559 SNDRV_PCM_RATE_22050 | \
1560 SNDRV_PCM_RATE_32000 | \
1561 SNDRV_PCM_RATE_44100 | \
1562 SNDRV_PCM_RATE_48000 | \
1563 SNDRV_PCM_RATE_88200 | \
1564 SNDRV_PCM_RATE_96000)
1565
1566#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1567 SNDRV_PCM_RATE_11025 | \
1568 SNDRV_PCM_RATE_16000 | \
1569 SNDRV_PCM_RATE_22050 | \
1570 SNDRV_PCM_RATE_32000 | \
1571 SNDRV_PCM_RATE_44100 | \
1572 SNDRV_PCM_RATE_48000)
1573
1574#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1575 SNDRV_PCM_FMTBIT_S20_3LE |\
1576 SNDRV_PCM_FMTBIT_S24_LE)
1577
6335d055
EM		 1578static struct snd_soc_dai_ops wm8903_dai_ops = {
1579 .startup = wm8903_startup,
1580 .shutdown = wm8903_shutdown,
1581 .hw_params = wm8903_hw_params,
1582 .digital_mute = wm8903_digital_mute,
1583 .set_fmt = wm8903_set_dai_fmt,
1584 .set_sysclk = wm8903_set_dai_sysclk,
1585};
1586
f1c0a02f
MB		 1587struct snd_soc_dai wm8903_dai = {
1588 .name = "WM8903",
1589 .playback = {
1590 .stream_name = "Playback",
1591 .channels_min = 2,
1592 .channels_max = 2,
1593 .rates = WM8903_PLAYBACK_RATES,
1594 .formats = WM8903_FORMATS,
1595 },
1596 .capture = {
1597 .stream_name = "Capture",
1598 .channels_min = 2,
1599 .channels_max = 2,
1600 .rates = WM8903_CAPTURE_RATES,
1601 .formats = WM8903_FORMATS,
1602 },
6335d055 1603 .ops = &wm8903_dai_ops,
0d960e88 1604 .symmetric_rates = 1,
f1c0a02f
MB		 1605};
1606EXPORT_SYMBOL_GPL(wm8903_dai);
1607
1608static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1609{
1610 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1611 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1612
1613 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1614
1615 return 0;
1616}
1617
1618static int wm8903_resume(struct platform_device *pdev)
1619{
1620 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1621 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1622 struct i2c_client *i2c = codec->control_data;
1623 int i;
1624 u16 *reg_cache = codec->reg_cache;
40aa7030 1625 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1626 GFP_KERNEL);
1627
1628 /* Bring the codec back up to standby first to minimise pop/clicks */
1629 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1630 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1631
1632 /* Sync back everything else */
1633 if (tmp_cache) {
1634 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1635 if (tmp_cache[i] != reg_cache[i])
8d50e447 1636 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1637 kfree(tmp_cache);
f1c0a02f
MB		 1638 } else {
1639 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1640 }
1641
1642 return 0;
1643}
1644
d58d5d55
MB		 1645static struct snd_soc_codec *wm8903_codec;
1646
c6f29811
MB		 1647static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1648 const struct i2c_device_id *id)
f1c0a02f 1649{
8abd16a6 1650 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
d58d5d55
MB		 1651 struct wm8903_priv *wm8903;
1652 struct snd_soc_codec *codec;
73b34ead 1653 int ret, i;
8abd16a6 1654 int trigger, irq_pol;
f1c0a02f
MB		 1655 u16 val;
1656
d58d5d55
MB		 1657 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1658 if (wm8903 == NULL)
1659 return -ENOMEM;
f1c0a02f 1660
d58d5d55
MB		 1661 codec = &wm8903->codec;
1662
1663 mutex_init(&codec->mutex);
1664 INIT_LIST_HEAD(&codec->dapm_widgets);
1665 INIT_LIST_HEAD(&codec->dapm_paths);
1666
1667 codec->dev = &i2c->dev;
f1c0a02f
MB		 1668 codec->name = "WM8903";
1669 codec->owner = THIS_MODULE;
f1c0a02f
MB		 1670 codec->bias_level = SND_SOC_BIAS_OFF;
1671 codec->set_bias_level = wm8903_set_bias_level;
1672 codec->dai = &wm8903_dai;
1673 codec->num_dai = 1;
d58d5d55
MB		 1674 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1675 codec->reg_cache = &wm8903->reg_cache[0];
1676 codec->private_data = wm8903;
8d50e447 1677 codec->volatile_register = wm8903_volatile_register;
8abd16a6 1678 init_completion(&wm8903->wseq);
d58d5d55
MB		 1679
1680 i2c_set_clientdata(i2c, codec);
1681 codec->control_data = i2c;
1682
8d50e447
MB		 1683 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1684 if (ret != 0) {
1685 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1686 goto err;
1687 }
1688
1689 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55
MB		 1690 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1691 dev_err(&i2c->dev,
1692 "Device with ID register %x is not a WM8903\n", val);
1693 return -ENODEV;
f1c0a02f
MB		 1694 }
1695
8d50e447 1696 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f1c0a02f
MB		 1697 dev_info(&i2c->dev, "WM8903 revision %d\n",
1698 val & WM8903_CHIP_REV_MASK);
1699
1700 wm8903_reset(codec);
1701
37f88e84 1702 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1703 if (pdata) {
1704 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1705 if (!pdata->gpio_cfg[i])
1706 continue;
1707
1708 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1709 pdata->gpio_cfg[i] & 0xffff);
1710 }
37f88e84
MB		 1711
1712 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1713 pdata->micdet_cfg);
1714
1715 /* Microphone detection needs the WSEQ clock */
1716 if (pdata->micdet_cfg)
1717 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1718 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1719
1720 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1721 }
8abd16a6
MB		 1722
1723 if (i2c->irq) {
1724 if (pdata && pdata->irq_active_low) {
1725 trigger = IRQF_TRIGGER_LOW;
1726 irq_pol = WM8903_IRQ_POL;
1727 } else {
1728 trigger = IRQF_TRIGGER_HIGH;
1729 irq_pol = 0;
1730 }
1731
1732 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1733 WM8903_IRQ_POL, irq_pol);
1734
1735 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
1736 trigger | IRQF_ONESHOT,
1737 "wm8903", wm8903);
1738 if (ret != 0) {
1739 dev_err(&i2c->dev, "Failed to request IRQ: %d\n",
1740 ret);
1741 goto err;
1742 }
1743
1744 /* Enable write sequencer interrupts */
1745 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1746 WM8903_IM_WSEQ_BUSY_EINT, 0);
1747 }
73b34ead 1748
f1c0a02f
MB		 1749 /* power on device */
1750 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1751
1752 /* Latch volume update bits */
8d50e447 1753 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1754 val |= WM8903_ADCVU;
8d50e447
MB		 1755 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1756 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1757
8d50e447 1758 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1759 val |= WM8903_DACVU;
8d50e447
MB		 1760 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1761 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1762
8d50e447 1763 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1764 val |= WM8903_HPOUTVU;
8d50e447
MB		 1765 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1766 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1767
8d50e447 1768 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1769 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1770 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1771 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1772
8d50e447 1773 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1774 val |= WM8903_SPKVU;
8d50e447
MB		 1775 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1776 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1777
1778 /* Enable DAC soft mute by default */
8d50e447 1779 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1780 val |= WM8903_DAC_MUTEMODE;
8d50e447 1781 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1782
d58d5d55
MB		 1783 wm8903_dai.dev = &i2c->dev;
1784 wm8903_codec = codec;
1785
1786 ret = snd_soc_register_codec(codec);
1787 if (ret != 0) {
1788 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
8abd16a6 1789 goto err_irq;
d58d5d55
MB		 1790 }
1791
1792 ret = snd_soc_register_dai(&wm8903_dai);
1793 if (ret != 0) {
1794 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1795 goto err_codec;
f1c0a02f
MB		 1796 }
1797
1798 return ret;
1799
d58d5d55
MB		 1800err_codec:
1801 snd_soc_unregister_codec(codec);
8abd16a6
MB		 1802err_irq:
1803 if (i2c->irq)
1804 free_irq(i2c->irq, wm8903);
d58d5d55
MB		 1805err:
1806 wm8903_codec = NULL;
1807 kfree(wm8903);
f1c0a02f
MB		 1808 return ret;
1809}
1810
c6f29811 1811static __devexit int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1812{
d58d5d55 1813 struct snd_soc_codec *codec = i2c_get_clientdata(client);
8abd16a6 1814 struct wm8903_priv *priv = codec->private_data;
f1c0a02f 1815
d58d5d55
MB		 1816 snd_soc_unregister_dai(&wm8903_dai);
1817 snd_soc_unregister_codec(codec);
f1c0a02f 1818
d58d5d55 1819 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1820
8abd16a6
MB		 1821 if (client->irq)
1822 free_irq(client->irq, priv);
1823
d58d5d55
MB		 1824 kfree(codec->private_data);
1825
1826 wm8903_codec = NULL;
1827 wm8903_dai.dev = NULL;
f1c0a02f 1828
f1c0a02f
MB		 1829 return 0;
1830}
1831
1832/* i2c codec control layer */
1833static const struct i2c_device_id wm8903_i2c_id[] = {
1834 { "wm8903", 0 },
1835 { }
1836};
1837MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1838
1839static struct i2c_driver wm8903_i2c_driver = {
1840 .driver = {
1841 .name = "WM8903",
1842 .owner = THIS_MODULE,
1843 },
1844 .probe = wm8903_i2c_probe,
c6f29811 1845 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1846 .id_table = wm8903_i2c_id,
1847};
1848
f1c0a02f
MB		 1849static int wm8903_probe(struct platform_device *pdev)
1850{
1851 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1852 int ret = 0;
1853
d58d5d55
MB		 1854 if (!wm8903_codec) {
1855 dev_err(&pdev->dev, "I2C device not yet probed\n");
1856 goto err;
f1c0a02f
MB		 1857 }
1858
6627a653 1859 socdev->card->codec = wm8903_codec;
f1c0a02f 1860
d58d5d55
MB		 1861 /* register pcms */
1862 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1863 if (ret < 0) {
1864 dev_err(&pdev->dev, "failed to create pcms\n");
1865 goto err;
f1c0a02f
MB		 1866 }
1867
6627a653 1868 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
3e8e1952 1869 ARRAY_SIZE(wm8903_snd_controls));
6627a653 1870 wm8903_add_widgets(socdev->card->codec);
f1c0a02f 1871
f1c0a02f
MB		 1872 return ret;
1873
d58d5d55 1874err:
f1c0a02f
MB		 1875 return ret;
1876}
1877
1878/* power down chip */
1879static int wm8903_remove(struct platform_device *pdev)
1880{
1881 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1882 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1883
1884 if (codec->control_data)
1885 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1886
1887 snd_soc_free_pcms(socdev);
1888 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1889
1890 return 0;
1891}
1892
1893struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1894 .probe = wm8903_probe,
1895 .remove = wm8903_remove,
1896 .suspend = wm8903_suspend,
1897 .resume = wm8903_resume,
1898};
1899EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1900
c9b3a40f 1901static int __init wm8903_modinit(void)
64089b84 1902{
d58d5d55 1903 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1904}
1905module_init(wm8903_modinit);
1906
1907static void __exit wm8903_exit(void)
1908{
d58d5d55 1909 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1910}
1911module_exit(wm8903_exit);
1912
f1c0a02f
MB		 1913MODULE_DESCRIPTION("ASoC WM8903 driver");
1914MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1915MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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