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ASoC: Remove open coded symmetry implementation from WM8903
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
5a0e3ad6 25#include <linux/slab.h>
f1c0a02f 26#include <sound/core.h>
7245387e 27#include <sound/jack.h>
f1c0a02f
MB		 28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
f1c0a02f 32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
f1c0a02f
MB		 34
35#include "wm8903.h"
36
f1c0a02f
MB		 37/* Register defaults at reset */
38static u16 wm8903_reg_defaults[] = {
39 0x8903, /* R0 - SW Reset and ID */
40 0x0000, /* R1 - Revision Number */
41 0x0000, /* R2 */
42 0x0000, /* R3 */
43 0x0018, /* R4 - Bias Control 0 */
44 0x0000, /* R5 - VMID Control 0 */
45 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0000, /* R7 */
47 0x0001, /* R8 - Analogue DAC 0 */
48 0x0000, /* R9 */
49 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R11 */
51 0x0000, /* R12 - Power Management 0 */
52 0x0000, /* R13 - Power Management 1 */
53 0x0000, /* R14 - Power Management 2 */
54 0x0000, /* R15 - Power Management 3 */
55 0x0000, /* R16 - Power Management 4 */
56 0x0000, /* R17 - Power Management 5 */
57 0x0000, /* R18 - Power Management 6 */
58 0x0000, /* R19 */
59 0x0400, /* R20 - Clock Rates 0 */
60 0x0D07, /* R21 - Clock Rates 1 */
61 0x0000, /* R22 - Clock Rates 2 */
62 0x0000, /* R23 */
63 0x0050, /* R24 - Audio Interface 0 */
64 0x0242, /* R25 - Audio Interface 1 */
65 0x0008, /* R26 - Audio Interface 2 */
66 0x0022, /* R27 - Audio Interface 3 */
67 0x0000, /* R28 */
68 0x0000, /* R29 */
69 0x00C0, /* R30 - DAC Digital Volume Left */
70 0x00C0, /* R31 - DAC Digital Volume Right */
71 0x0000, /* R32 - DAC Digital 0 */
72 0x0000, /* R33 - DAC Digital 1 */
73 0x0000, /* R34 */
74 0x0000, /* R35 */
75 0x00C0, /* R36 - ADC Digital Volume Left */
76 0x00C0, /* R37 - ADC Digital Volume Right */
77 0x0000, /* R38 - ADC Digital 0 */
78 0x0073, /* R39 - Digital Microphone 0 */
79 0x09BF, /* R40 - DRC 0 */
80 0x3241, /* R41 - DRC 1 */
81 0x0020, /* R42 - DRC 2 */
82 0x0000, /* R43 - DRC 3 */
83 0x0085, /* R44 - Analogue Left Input 0 */
84 0x0085, /* R45 - Analogue Right Input 0 */
85 0x0044, /* R46 - Analogue Left Input 1 */
86 0x0044, /* R47 - Analogue Right Input 1 */
87 0x0000, /* R48 */
88 0x0000, /* R49 */
89 0x0008, /* R50 - Analogue Left Mix 0 */
90 0x0004, /* R51 - Analogue Right Mix 0 */
91 0x0000, /* R52 - Analogue Spk Mix Left 0 */
92 0x0000, /* R53 - Analogue Spk Mix Left 1 */
93 0x0000, /* R54 - Analogue Spk Mix Right 0 */
94 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x0000, /* R56 */
96 0x002D, /* R57 - Analogue OUT1 Left */
97 0x002D, /* R58 - Analogue OUT1 Right */
98 0x0039, /* R59 - Analogue OUT2 Left */
99 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0100, /* R61 */
101 0x0139, /* R62 - Analogue OUT3 Left */
102 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R64 */
104 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0000, /* R66 */
106 0x0010, /* R67 - DC Servo 0 */
107 0x0100, /* R68 */
108 0x00A4, /* R69 - DC Servo 2 */
109 0x0807, /* R70 */
110 0x0000, /* R71 */
111 0x0000, /* R72 */
112 0x0000, /* R73 */
113 0x0000, /* R74 */
114 0x0000, /* R75 */
115 0x0000, /* R76 */
116 0x0000, /* R77 */
117 0x0000, /* R78 */
118 0x000E, /* R79 */
119 0x0000, /* R80 */
120 0x0000, /* R81 */
121 0x0000, /* R82 */
122 0x0000, /* R83 */
123 0x0000, /* R84 */
124 0x0000, /* R85 */
125 0x0000, /* R86 */
126 0x0006, /* R87 */
127 0x0000, /* R88 */
128 0x0000, /* R89 */
129 0x0000, /* R90 - Analogue HP 0 */
130 0x0060, /* R91 */
131 0x0000, /* R92 */
132 0x0000, /* R93 */
133 0x0000, /* R94 - Analogue Lineout 0 */
134 0x0060, /* R95 */
135 0x0000, /* R96 */
136 0x0000, /* R97 */
137 0x0000, /* R98 - Charge Pump 0 */
138 0x1F25, /* R99 */
139 0x2B19, /* R100 */
140 0x01C0, /* R101 */
141 0x01EF, /* R102 */
142 0x2B00, /* R103 */
143 0x0000, /* R104 - Class W 0 */
144 0x01C0, /* R105 */
145 0x1C10, /* R106 */
146 0x0000, /* R107 */
147 0x0000, /* R108 - Write Sequencer 0 */
148 0x0000, /* R109 - Write Sequencer 1 */
149 0x0000, /* R110 - Write Sequencer 2 */
150 0x0000, /* R111 - Write Sequencer 3 */
151 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R113 */
153 0x0000, /* R114 - Control Interface */
154 0x0000, /* R115 */
155 0x00A8, /* R116 - GPIO Control 1 */
156 0x00A8, /* R117 - GPIO Control 2 */
157 0x00A8, /* R118 - GPIO Control 3 */
158 0x0220, /* R119 - GPIO Control 4 */
159 0x01A0, /* R120 - GPIO Control 5 */
160 0x0000, /* R121 - Interrupt Status 1 */
161 0xFFFF, /* R122 - Interrupt Status 1 Mask */
162 0x0000, /* R123 - Interrupt Polarity 1 */
163 0x0000, /* R124 */
164 0x0003, /* R125 */
165 0x0000, /* R126 - Interrupt Control */
166 0x0000, /* R127 */
167 0x0005, /* R128 */
168 0x0000, /* R129 - Control Interface Test 1 */
169 0x0000, /* R130 */
170 0x0000, /* R131 */
171 0x0000, /* R132 */
172 0x0000, /* R133 */
173 0x0000, /* R134 */
174 0x03FF, /* R135 */
175 0x0007, /* R136 */
176 0x0040, /* R137 */
177 0x0000, /* R138 */
178 0x0000, /* R139 */
179 0x0000, /* R140 */
180 0x0000, /* R141 */
181 0x0000, /* R142 */
182 0x0000, /* R143 */
183 0x0000, /* R144 */
184 0x0000, /* R145 */
185 0x0000, /* R146 */
186 0x0000, /* R147 */
187 0x4000, /* R148 */
188 0x6810, /* R149 - Charge Pump Test 1 */
189 0x0004, /* R150 */
190 0x0000, /* R151 */
191 0x0000, /* R152 */
192 0x0000, /* R153 */
193 0x0000, /* R154 */
194 0x0000, /* R155 */
195 0x0000, /* R156 */
196 0x0000, /* R157 */
197 0x0000, /* R158 */
198 0x0000, /* R159 */
199 0x0000, /* R160 */
200 0x0000, /* R161 */
201 0x0000, /* R162 */
202 0x0000, /* R163 */
203 0x0028, /* R164 - Clock Rate Test 4 */
204 0x0004, /* R165 */
205 0x0000, /* R166 */
206 0x0060, /* R167 */
207 0x0000, /* R168 */
208 0x0000, /* R169 */
209 0x0000, /* R170 */
210 0x0000, /* R171 */
211 0x0000, /* R172 - Analogue Output Bias 0 */
212};
213
d58d5d55 214struct wm8903_priv {
f0fba2ad 215
d58d5d55
MB		 216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk;
f0fba2ad 219 int irq;
d58d5d55 220
f2c1fe09 221 /* Reference count */
d58d5d55 222 int class_w_users;
d58d5d55 223
8abd16a6
MB		 224 struct completion wseq;
225
7245387e
MB		 226 struct snd_soc_jack *mic_jack;
227 int mic_det;
228 int mic_short;
229 int mic_last_report;
230 int mic_delay;
d58d5d55
MB		 231};
232
8d50e447 233static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 234{
235 switch (reg) {
236 case WM8903_SW_RESET_AND_ID:
237 case WM8903_REVISION_NUMBER:
238 case WM8903_INTERRUPT_STATUS_1:
239 case WM8903_WRITE_SEQUENCER_4:
8d50e447 240 return 1;
f1c0a02f
MB		 241
242 default:
f1c0a02f 243 return 0;
8d50e447 244 }
f1c0a02f
MB		 245}
246
247static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
248{
249 u16 reg[5];
b2c812e2 250 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 251
252 BUG_ON(start > 48);
253
37f88e84 254 /* Enable the sequencer if it's not already on */
8d50e447 255 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 256 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
257 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 258
f0fba2ad 259 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 260
8d50e447 261 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 262 start | WM8903_WSEQ_START);
263
264 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 265 * that will break us out of the poll early.
f1c0a02f
MB		 266 */
267 do {
8abd16a6
MB		 268 wait_for_completion_timeout(&wm8903->wseq,
269 msecs_to_jiffies(10));
f1c0a02f 270
8d50e447 271 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 272 } while (reg[4] & WM8903_WSEQ_BUSY);
273
f0fba2ad 274 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 275
37f88e84
MB		 276 /* Disable the sequencer again if we enabled it */
277 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 278
279 return 0;
280}
281
282static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
283{
284 int i;
285
286 /* There really ought to be something better we can do here :/ */
287 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 288 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 289}
290
291static void wm8903_reset(struct snd_soc_codec *codec)
292{
8d50e447 293 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 294 memcpy(codec->reg_cache, wm8903_reg_defaults,
295 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 296}
297
298#define WM8903_OUTPUT_SHORT 0x8
299#define WM8903_OUTPUT_OUT 0x4
300#define WM8903_OUTPUT_INT 0x2
301#define WM8903_OUTPUT_IN 0x1
302
42768a12
MB		 303static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
304 struct snd_kcontrol *kcontrol, int event)
305{
306 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
307 mdelay(4);
308
309 return 0;
310}
311
f1c0a02f
MB		 312/*
313 * Event for headphone and line out amplifier power changes. Special
314 * power up/down sequences are required in order to maximise pop/click
315 * performance.
316 */
317static int wm8903_output_event(struct snd_soc_dapm_widget *w,
318 struct snd_kcontrol *kcontrol, int event)
319{
320 struct snd_soc_codec *codec = w->codec;
f1c0a02f 321 u16 val;
0bc286e2 322 u16 reg;
d7d5c547
MB		 323 u16 dcs_reg;
324 u16 dcs_bit;
0bc286e2 325 int shift;
f1c0a02f
MB		 326
327 switch (w->reg) {
328 case WM8903_POWER_MANAGEMENT_2:
329 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 330 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 331 break;
332 case WM8903_POWER_MANAGEMENT_3:
333 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 334 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 335 break;
336 default:
337 BUG();
1e297a19 338 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 339 }
340
341 switch (w->shift) {
342 case 0:
343 shift = 0;
344 break;
345 case 1:
346 shift = 4;
347 break;
348 default:
349 BUG();
1e297a19 350 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 351 }
352
353 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 354 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 355
356 /* Short the output */
357 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 358 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 359 }
360
361 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 362 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 363
364 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 365 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 366
367 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 368 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 369
370 /* Turn on the output ENA_OUTP */
371 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 372 snd_soc_write(codec, reg, val);
f1c0a02f 373
d7d5c547 374 /* Enable the DC servo */
8d50e447 375 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 376 dcs_reg |= dcs_bit;
8d50e447 377 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 378
f1c0a02f
MB		 379 /* Remove the short */
380 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 381 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 382 }
383
384 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 385 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 386
387 /* Short the output */
388 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 389 snd_soc_write(codec, reg, val);
f1c0a02f 390
d7d5c547 391 /* Disable the DC servo */
8d50e447 392 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 393 dcs_reg &= ~dcs_bit;
8d50e447 394 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 395
f1c0a02f
MB		 396 /* Then disable the intermediate and output stages */
397 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
398 WM8903_OUTPUT_IN) << shift);
8d50e447 399 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 400 }
401
f1c0a02f
MB		 402 return 0;
403}
404
405/*
406 * When used with DAC outputs only the WM8903 charge pump supports
407 * operation in class W mode, providing very low power consumption
408 * when used with digital sources. Enable and disable this mode
409 * automatically depending on the mixer configuration.
410 *
411 * All the relevant controls are simple switches.
412 */
413static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
414 struct snd_ctl_elem_value *ucontrol)
415{
416 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
417 struct snd_soc_codec *codec = widget->codec;
b2c812e2 418 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 419 u16 reg;
420 int ret;
421
8d50e447 422 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 423
424 /* Turn it off if we're about to enable bypass */
425 if (ucontrol->value.integer.value[0]) {
426 if (wm8903->class_w_users == 0) {
f0fba2ad 427 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 428 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 429 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
430 }
431 wm8903->class_w_users++;
432 }
433
434 /* Implement the change */
435 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
436
437 /* If we've just disabled the last bypass path turn Class W on */
438 if (!ucontrol->value.integer.value[0]) {
439 if (wm8903->class_w_users == 1) {
f0fba2ad 440 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 441 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 442 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
443 }
444 wm8903->class_w_users--;
445 }
446
f0fba2ad 447 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 448 wm8903->class_w_users);
449
450 return ret;
451}
452
453#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
454{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
455 .info = snd_soc_info_volsw, \
456 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
457 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
458
459
460/* ALSA can only do steps of .01dB */
461static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
462
291ce18c 463static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 464static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
465
466static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
467static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
468static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
469static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
470static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
471
460f4aae
MB		 472static const char *hpf_mode_text[] = {
473 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
474};
475
476static const struct soc_enum hpf_mode =
477 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
478
dcf9ada3
MB		 479static const char *osr_text[] = {
480 "Low power", "High performance"
481};
482
483static const struct soc_enum adc_osr =
484 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
485
486static const struct soc_enum dac_osr =
487 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
488
f1c0a02f
MB		 489static const char *drc_slope_text[] = {
490 "1", "1/2", "1/4", "1/8", "1/16", "0"
491};
492
493static const struct soc_enum drc_slope_r0 =
494 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
495
496static const struct soc_enum drc_slope_r1 =
497 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
498
499static const char *drc_attack_text[] = {
500 "instantaneous",
501 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
502 "46.4ms", "92.8ms", "185.6ms"
503};
504
505static const struct soc_enum drc_attack =
506 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
507
508static const char *drc_decay_text[] = {
509 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
510 "23.87s", "47.56s"
511};
512
513static const struct soc_enum drc_decay =
514 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
515
516static const char *drc_ff_delay_text[] = {
517 "5 samples", "9 samples"
518};
519
520static const struct soc_enum drc_ff_delay =
521 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
522
523static const char *drc_qr_decay_text[] = {
524 "0.725ms", "1.45ms", "5.8ms"
525};
526
527static const struct soc_enum drc_qr_decay =
528 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
529
530static const char *drc_smoothing_text[] = {
531 "Low", "Medium", "High"
532};
533
534static const struct soc_enum drc_smoothing =
535 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
536
537static const char *soft_mute_text[] = {
538 "Fast (fs/2)", "Slow (fs/32)"
539};
540
541static const struct soc_enum soft_mute =
542 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
543
544static const char *mute_mode_text[] = {
545 "Hard", "Soft"
546};
547
548static const struct soc_enum mute_mode =
549 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
550
551static const char *dac_deemphasis_text[] = {
552 "Disabled", "32kHz", "44.1kHz", "48kHz"
553};
554
555static const struct soc_enum dac_deemphasis =
556 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
557
558static const char *companding_text[] = {
559 "ulaw", "alaw"
560};
561
562static const struct soc_enum dac_companding =
563 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
564
565static const struct soc_enum adc_companding =
566 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
567
568static const char *input_mode_text[] = {
569 "Single-Ended", "Differential Line", "Differential Mic"
570};
571
572static const struct soc_enum linput_mode_enum =
573 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
574
575static const struct soc_enum rinput_mode_enum =
576 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
577
578static const char *linput_mux_text[] = {
579 "IN1L", "IN2L", "IN3L"
580};
581
582static const struct soc_enum linput_enum =
583 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
584
585static const struct soc_enum linput_inv_enum =
586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
587
588static const char *rinput_mux_text[] = {
589 "IN1R", "IN2R", "IN3R"
590};
591
592static const struct soc_enum rinput_enum =
593 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
594
595static const struct soc_enum rinput_inv_enum =
596 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
597
598
291ce18c
MB		 599static const char *sidetone_text[] = {
600 "None", "Left", "Right"
601};
602
603static const struct soc_enum lsidetone_enum =
604 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
605
606static const struct soc_enum rsidetone_enum =
607 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
608
f1c0a02f
MB		 609static const struct snd_kcontrol_new wm8903_snd_controls[] = {
610
611/* Input PGAs - No TLV since the scale depends on PGA mode */
612SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 613 7, 1, 1),
f1c0a02f
MB		 614SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
615 0, 31, 0),
616SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
617 6, 1, 0),
618
619SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 620 7, 1, 1),
f1c0a02f
MB		 621SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
622 0, 31, 0),
623SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
624 6, 1, 0),
625
626/* ADCs */
dcf9ada3 627SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 628SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
629SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 630SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
631SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
632SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 633SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 634 drc_tlv_thresh),
635SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
636SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
637SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
638SOC_ENUM("DRC Attack Rate", drc_attack),
639SOC_ENUM("DRC Decay Rate", drc_decay),
640SOC_ENUM("DRC FF Delay", drc_ff_delay),
641SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
642SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 643SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 644SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
645SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
646SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 647SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 648SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
649
650SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
651 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
652SOC_ENUM("ADC Companding Mode", adc_companding),
653SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
654
291ce18c
MB		 655SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
656 12, 0, digital_sidetone_tlv),
657
f1c0a02f 658/* DAC */
dcf9ada3 659SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 660SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
661 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
662SOC_ENUM("DAC Soft Mute Rate", soft_mute),
663SOC_ENUM("DAC Mute Mode", mute_mode),
664SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
665SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 666SOC_ENUM("DAC Companding Mode", dac_companding),
667SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
668
669/* Headphones */
670SOC_DOUBLE_R("Headphone Switch",
671 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
672 8, 1, 1),
673SOC_DOUBLE_R("Headphone ZC Switch",
674 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
675 6, 1, 0),
676SOC_DOUBLE_R_TLV("Headphone Volume",
677 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
678 0, 63, 0, out_tlv),
679
680/* Line out */
681SOC_DOUBLE_R("Line Out Switch",
682 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
683 8, 1, 1),
684SOC_DOUBLE_R("Line Out ZC Switch",
685 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
686 6, 1, 0),
687SOC_DOUBLE_R_TLV("Line Out Volume",
688 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
689 0, 63, 0, out_tlv),
690
691/* Speaker */
692SOC_DOUBLE_R("Speaker Switch",
693 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
694SOC_DOUBLE_R("Speaker ZC Switch",
695 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
696SOC_DOUBLE_R_TLV("Speaker Volume",
697 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
698 0, 63, 0, out_tlv),
699};
700
f1c0a02f
MB		 701static const struct snd_kcontrol_new linput_mode_mux =
702 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
703
704static const struct snd_kcontrol_new rinput_mode_mux =
705 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
706
707static const struct snd_kcontrol_new linput_mux =
708 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
709
710static const struct snd_kcontrol_new linput_inv_mux =
711 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
712
713static const struct snd_kcontrol_new rinput_mux =
714 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
715
716static const struct snd_kcontrol_new rinput_inv_mux =
717 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
718
291ce18c
MB		 719static const struct snd_kcontrol_new lsidetone_mux =
720 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
721
722static const struct snd_kcontrol_new rsidetone_mux =
723 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
724
f1c0a02f
MB		 725static const struct snd_kcontrol_new left_output_mixer[] = {
726SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
727SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
728SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 729SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 730};
731
732static const struct snd_kcontrol_new right_output_mixer[] = {
733SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
734SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
735SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 736SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 737};
738
739static const struct snd_kcontrol_new left_speaker_mixer[] = {
740SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
741SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
742SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
743SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 744 0, 1, 0),
f1c0a02f
MB		 745};
746
747static const struct snd_kcontrol_new right_speaker_mixer[] = {
748SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
749SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
750SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
751 1, 1, 0),
752SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 753 0, 1, 0),
f1c0a02f
MB		 754};
755
756static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
757SND_SOC_DAPM_INPUT("IN1L"),
758SND_SOC_DAPM_INPUT("IN1R"),
759SND_SOC_DAPM_INPUT("IN2L"),
760SND_SOC_DAPM_INPUT("IN2R"),
761SND_SOC_DAPM_INPUT("IN3L"),
762SND_SOC_DAPM_INPUT("IN3R"),
763
764SND_SOC_DAPM_OUTPUT("HPOUTL"),
765SND_SOC_DAPM_OUTPUT("HPOUTR"),
766SND_SOC_DAPM_OUTPUT("LINEOUTL"),
767SND_SOC_DAPM_OUTPUT("LINEOUTR"),
768SND_SOC_DAPM_OUTPUT("LOP"),
769SND_SOC_DAPM_OUTPUT("LON"),
770SND_SOC_DAPM_OUTPUT("ROP"),
771SND_SOC_DAPM_OUTPUT("RON"),
772
773SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
774
775SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
776SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
777 &linput_inv_mux),
778SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
779
780SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
781SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
782 &rinput_inv_mux),
783SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
784
785SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
786SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
787
788SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
789SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
790
291ce18c
MB		 791SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
792SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
793
f1c0a02f
MB		 794SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
795SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
796
797SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
798 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
799SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
800 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
801
802SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
803 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
804SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
805 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
806
807SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
808 1, 0, NULL, 0, wm8903_output_event,
809 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 810 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 811SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
812 0, 0, NULL, 0, wm8903_output_event,
813 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 814 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 815
816SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
817 NULL, 0, wm8903_output_event,
818 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 819 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 820SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
821 NULL, 0, wm8903_output_event,
822 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 823 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 824
825SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
826 NULL, 0),
827SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
828 NULL, 0),
829
42768a12
MB		 830SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
831 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 832SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 833};
834
835static const struct snd_soc_dapm_route intercon[] = {
836
837 { "Left Input Mux", "IN1L", "IN1L" },
838 { "Left Input Mux", "IN2L", "IN2L" },
839 { "Left Input Mux", "IN3L", "IN3L" },
840
841 { "Left Input Inverting Mux", "IN1L", "IN1L" },
842 { "Left Input Inverting Mux", "IN2L", "IN2L" },
843 { "Left Input Inverting Mux", "IN3L", "IN3L" },
844
845 { "Right Input Mux", "IN1R", "IN1R" },
846 { "Right Input Mux", "IN2R", "IN2R" },
847 { "Right Input Mux", "IN3R", "IN3R" },
848
849 { "Right Input Inverting Mux", "IN1R", "IN1R" },
850 { "Right Input Inverting Mux", "IN2R", "IN2R" },
851 { "Right Input Inverting Mux", "IN3R", "IN3R" },
852
853 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
854 { "Left Input Mode Mux", "Differential Line",
855 "Left Input Mux" },
856 { "Left Input Mode Mux", "Differential Line",
857 "Left Input Inverting Mux" },
858 { "Left Input Mode Mux", "Differential Mic",
859 "Left Input Mux" },
860 { "Left Input Mode Mux", "Differential Mic",
861 "Left Input Inverting Mux" },
862
863 { "Right Input Mode Mux", "Single-Ended",
864 "Right Input Inverting Mux" },
865 { "Right Input Mode Mux", "Differential Line",
866 "Right Input Mux" },
867 { "Right Input Mode Mux", "Differential Line",
868 "Right Input Inverting Mux" },
869 { "Right Input Mode Mux", "Differential Mic",
870 "Right Input Mux" },
871 { "Right Input Mode Mux", "Differential Mic",
872 "Right Input Inverting Mux" },
873
874 { "Left Input PGA", NULL, "Left Input Mode Mux" },
875 { "Right Input PGA", NULL, "Right Input Mode Mux" },
876
877 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 878 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 879 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 880 { "ADCR", NULL, "CLK_DSP" },
881
291ce18c
MB		 882 { "DACL Sidetone", "Left", "ADCL" },
883 { "DACL Sidetone", "Right", "ADCR" },
884 { "DACR Sidetone", "Left", "ADCL" },
885 { "DACR Sidetone", "Right", "ADCR" },
886
887 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 888 { "DACL", NULL, "CLK_DSP" },
291ce18c 889 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 890 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 891
892 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
893 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
894 { "Left Output Mixer", "DACL Switch", "DACL" },
895 { "Left Output Mixer", "DACR Switch", "DACR" },
896
897 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
898 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
899 { "Right Output Mixer", "DACL Switch", "DACL" },
900 { "Right Output Mixer", "DACR Switch", "DACR" },
901
902 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
903 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
904 { "Left Speaker Mixer", "DACL Switch", "DACL" },
905 { "Left Speaker Mixer", "DACR Switch", "DACR" },
906
907 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
908 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
909 { "Right Speaker Mixer", "DACL Switch", "DACL" },
910 { "Right Speaker Mixer", "DACR Switch", "DACR" },
911
912 { "Left Line Output PGA", NULL, "Left Output Mixer" },
913 { "Right Line Output PGA", NULL, "Right Output Mixer" },
914
915 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
916 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
917
918 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
919 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
920
921 { "HPOUTL", NULL, "Left Headphone Output PGA" },
922 { "HPOUTR", NULL, "Right Headphone Output PGA" },
923
924 { "LINEOUTL", NULL, "Left Line Output PGA" },
925 { "LINEOUTR", NULL, "Right Line Output PGA" },
926
927 { "LOP", NULL, "Left Speaker PGA" },
928 { "LON", NULL, "Left Speaker PGA" },
929
930 { "ROP", NULL, "Right Speaker PGA" },
931 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 932
933 { "Left Headphone Output PGA", NULL, "Charge Pump" },
934 { "Right Headphone Output PGA", NULL, "Charge Pump" },
935 { "Left Line Output PGA", NULL, "Charge Pump" },
936 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 937};
938
939static int wm8903_add_widgets(struct snd_soc_codec *codec)
940{
ce6120cc 941 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 942
ce6120cc
LG		 943 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
944 ARRAY_SIZE(wm8903_dapm_widgets));
945 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 946
f1c0a02f
MB		 947 return 0;
948}
949
950static int wm8903_set_bias_level(struct snd_soc_codec *codec,
951 enum snd_soc_bias_level level)
952{
f1c0a02f
MB		 953 u16 reg, reg2;
954
955 switch (level) {
956 case SND_SOC_BIAS_ON:
957 case SND_SOC_BIAS_PREPARE:
8d50e447 958 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 959 reg &= ~(WM8903_VMID_RES_MASK);
960 reg |= WM8903_VMID_RES_50K;
8d50e447 961 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 962 break;
963
964 case SND_SOC_BIAS_STANDBY:
ce6120cc 965 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 966 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 967 WM8903_CLK_SYS_ENA);
968
4dbfe809 969 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 970 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
971 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
972 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 973
f1c0a02f
MB		 974 wm8903_run_sequence(codec, 0);
975 wm8903_sync_reg_cache(codec, codec->reg_cache);
976
977 /* Enable low impedence charge pump output */
8d50e447 978 reg = snd_soc_read(codec,
f1c0a02f 979 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 980 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 981 reg | WM8903_TEST_KEY);
8d50e447
MB		 982 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
983 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 984 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 985 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 986 reg);
987
988 /* By default no bypass paths are enabled so
989 * enable Class W support.
990 */
f0fba2ad 991 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 992 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 993 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
994 }
995
8d50e447 996 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 997 reg &= ~(WM8903_VMID_RES_MASK);
998 reg |= WM8903_VMID_RES_250K;
8d50e447 999 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1000 break;
1001
1002 case SND_SOC_BIAS_OFF:
1003 wm8903_run_sequence(codec, 32);
8d50e447 1004 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1005 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1006 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1007 break;
1008 }
1009
ce6120cc 1010 codec->dapm.bias_level = level;
f1c0a02f
MB		 1011
1012 return 0;
1013}
1014
1015static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1016 int clk_id, unsigned int freq, int dir)
1017{
1018 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1019 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1020
1021 wm8903->sysclk = freq;
1022
1023 return 0;
1024}
1025
1026static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1027 unsigned int fmt)
1028{
1029 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1030 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1031
1032 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1033 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1034
1035 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1036 case SND_SOC_DAIFMT_CBS_CFS:
1037 break;
1038 case SND_SOC_DAIFMT_CBS_CFM:
1039 aif1 |= WM8903_LRCLK_DIR;
1040 break;
1041 case SND_SOC_DAIFMT_CBM_CFM:
1042 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1043 break;
1044 case SND_SOC_DAIFMT_CBM_CFS:
1045 aif1 |= WM8903_BCLK_DIR;
1046 break;
1047 default:
1048 return -EINVAL;
1049 }
1050
1051 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1052 case SND_SOC_DAIFMT_DSP_A:
1053 aif1 |= 0x3;
1054 break;
1055 case SND_SOC_DAIFMT_DSP_B:
1056 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1057 break;
1058 case SND_SOC_DAIFMT_I2S:
1059 aif1 |= 0x2;
1060 break;
1061 case SND_SOC_DAIFMT_RIGHT_J:
1062 aif1 |= 0x1;
1063 break;
1064 case SND_SOC_DAIFMT_LEFT_J:
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069
1070 /* Clock inversion */
1071 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1072 case SND_SOC_DAIFMT_DSP_A:
1073 case SND_SOC_DAIFMT_DSP_B:
1074 /* frame inversion not valid for DSP modes */
1075 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1076 case SND_SOC_DAIFMT_NB_NF:
1077 break;
1078 case SND_SOC_DAIFMT_IB_NF:
1079 aif1 |= WM8903_AIF_BCLK_INV;
1080 break;
1081 default:
1082 return -EINVAL;
1083 }
1084 break;
1085 case SND_SOC_DAIFMT_I2S:
1086 case SND_SOC_DAIFMT_RIGHT_J:
1087 case SND_SOC_DAIFMT_LEFT_J:
1088 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1089 case SND_SOC_DAIFMT_NB_NF:
1090 break;
1091 case SND_SOC_DAIFMT_IB_IF:
1092 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1093 break;
1094 case SND_SOC_DAIFMT_IB_NF:
1095 aif1 |= WM8903_AIF_BCLK_INV;
1096 break;
1097 case SND_SOC_DAIFMT_NB_IF:
1098 aif1 |= WM8903_AIF_LRCLK_INV;
1099 break;
1100 default:
1101 return -EINVAL;
1102 }
1103 break;
1104 default:
1105 return -EINVAL;
1106 }
1107
8d50e447 1108 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1109
1110 return 0;
1111}
1112
1113static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1114{
1115 struct snd_soc_codec *codec = codec_dai->codec;
1116 u16 reg;
1117
8d50e447 1118 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1119
1120 if (mute)
1121 reg |= WM8903_DAC_MUTE;
1122 else
1123 reg &= ~WM8903_DAC_MUTE;
1124
8d50e447 1125 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1126
1127 return 0;
1128}
1129
1130/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1131 * for optimal performance so we list the lower rates first and match
1132 * on the last match we find. */
1133static struct {
1134 int div;
1135 int rate;
1136 int mode;
1137 int mclk_div;
1138} clk_sys_ratios[] = {
1139 { 64, 0x0, 0x0, 1 },
1140 { 68, 0x0, 0x1, 1 },
1141 { 125, 0x0, 0x2, 1 },
1142 { 128, 0x1, 0x0, 1 },
1143 { 136, 0x1, 0x1, 1 },
1144 { 192, 0x2, 0x0, 1 },
1145 { 204, 0x2, 0x1, 1 },
1146
1147 { 64, 0x0, 0x0, 2 },
1148 { 68, 0x0, 0x1, 2 },
1149 { 125, 0x0, 0x2, 2 },
1150 { 128, 0x1, 0x0, 2 },
1151 { 136, 0x1, 0x1, 2 },
1152 { 192, 0x2, 0x0, 2 },
1153 { 204, 0x2, 0x1, 2 },
1154
1155 { 250, 0x2, 0x2, 1 },
1156 { 256, 0x3, 0x0, 1 },
1157 { 272, 0x3, 0x1, 1 },
1158 { 384, 0x4, 0x0, 1 },
1159 { 408, 0x4, 0x1, 1 },
1160 { 375, 0x4, 0x2, 1 },
1161 { 512, 0x5, 0x0, 1 },
1162 { 544, 0x5, 0x1, 1 },
1163 { 500, 0x5, 0x2, 1 },
1164 { 768, 0x6, 0x0, 1 },
1165 { 816, 0x6, 0x1, 1 },
1166 { 750, 0x6, 0x2, 1 },
1167 { 1024, 0x7, 0x0, 1 },
1168 { 1088, 0x7, 0x1, 1 },
1169 { 1000, 0x7, 0x2, 1 },
1170 { 1408, 0x8, 0x0, 1 },
1171 { 1496, 0x8, 0x1, 1 },
1172 { 1536, 0x9, 0x0, 1 },
1173 { 1632, 0x9, 0x1, 1 },
1174 { 1500, 0x9, 0x2, 1 },
1175
1176 { 250, 0x2, 0x2, 2 },
1177 { 256, 0x3, 0x0, 2 },
1178 { 272, 0x3, 0x1, 2 },
1179 { 384, 0x4, 0x0, 2 },
1180 { 408, 0x4, 0x1, 2 },
1181 { 375, 0x4, 0x2, 2 },
1182 { 512, 0x5, 0x0, 2 },
1183 { 544, 0x5, 0x1, 2 },
1184 { 500, 0x5, 0x2, 2 },
1185 { 768, 0x6, 0x0, 2 },
1186 { 816, 0x6, 0x1, 2 },
1187 { 750, 0x6, 0x2, 2 },
1188 { 1024, 0x7, 0x0, 2 },
1189 { 1088, 0x7, 0x1, 2 },
1190 { 1000, 0x7, 0x2, 2 },
1191 { 1408, 0x8, 0x0, 2 },
1192 { 1496, 0x8, 0x1, 2 },
1193 { 1536, 0x9, 0x0, 2 },
1194 { 1632, 0x9, 0x1, 2 },
1195 { 1500, 0x9, 0x2, 2 },
1196};
1197
1198/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1199static struct {
1200 int ratio;
1201 int div;
1202} bclk_divs[] = {
1203 { 10, 0 },
f1c0a02f
MB		 1204 { 20, 2 },
1205 { 30, 3 },
1206 { 40, 4 },
1207 { 50, 5 },
f1c0a02f
MB		 1208 { 60, 7 },
1209 { 80, 8 },
1210 { 100, 9 },
f1c0a02f
MB		 1211 { 120, 11 },
1212 { 160, 12 },
1213 { 200, 13 },
1214 { 220, 14 },
1215 { 240, 15 },
f1c0a02f
MB		 1216 { 300, 17 },
1217 { 320, 18 },
1218 { 440, 19 },
1219 { 480, 20 },
1220};
1221
1222/* Sample rates for DSP */
1223static struct {
1224 int rate;
1225 int value;
1226} sample_rates[] = {
1227 { 8000, 0 },
1228 { 11025, 1 },
1229 { 12000, 2 },
1230 { 16000, 3 },
1231 { 22050, 4 },
1232 { 24000, 5 },
1233 { 32000, 6 },
1234 { 44100, 7 },
1235 { 48000, 8 },
1236 { 88200, 9 },
1237 { 96000, 10 },
1238 { 0, 0 },
1239};
1240
f1c0a02f 1241static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1242 struct snd_pcm_hw_params *params,
1243 struct snd_soc_dai *dai)
f1c0a02f
MB		 1244{
1245 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1246 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1247 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1248 int fs = params_rate(params);
1249 int bclk;
1250 int bclk_div;
1251 int i;
1252 int dsp_config;
1253 int clk_config;
1254 int best_val;
1255 int cur_val;
1256 int clk_sys;
1257
8d50e447
MB		 1258 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1259 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1260 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1261 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1262 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1263 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1264
9e79261f
MB		 1265 /* Enable sloping stopband filter for low sample rates */
1266 if (fs <= 24000)
1267 dac_digital1 |= WM8903_DAC_SB_FILT;
1268 else
1269 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1270
f1c0a02f
MB		 1271 /* Configure sample rate logic for DSP - choose nearest rate */
1272 dsp_config = 0;
1273 best_val = abs(sample_rates[dsp_config].rate - fs);
1274 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1275 cur_val = abs(sample_rates[i].rate - fs);
1276 if (cur_val <= best_val) {
1277 dsp_config = i;
1278 best_val = cur_val;
1279 }
1280 }
1281
f0fba2ad 1282 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1283 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1284 clock1 |= sample_rates[dsp_config].value;
1285
1286 aif1 &= ~WM8903_AIF_WL_MASK;
1287 bclk = 2 * fs;
1288 switch (params_format(params)) {
1289 case SNDRV_PCM_FORMAT_S16_LE:
1290 bclk *= 16;
1291 break;
1292 case SNDRV_PCM_FORMAT_S20_3LE:
1293 bclk *= 20;
1294 aif1 |= 0x4;
1295 break;
1296 case SNDRV_PCM_FORMAT_S24_LE:
1297 bclk *= 24;
1298 aif1 |= 0x8;
1299 break;
1300 case SNDRV_PCM_FORMAT_S32_LE:
1301 bclk *= 32;
1302 aif1 |= 0xc;
1303 break;
1304 default:
1305 return -EINVAL;
1306 }
1307
f0fba2ad 1308 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1309 wm8903->sysclk, fs);
1310
1311 /* We may not have an MCLK which allows us to generate exactly
1312 * the clock we want, particularly with USB derived inputs, so
1313 * approximate.
1314 */
1315 clk_config = 0;
1316 best_val = abs((wm8903->sysclk /
1317 (clk_sys_ratios[0].mclk_div *
1318 clk_sys_ratios[0].div)) - fs);
1319 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1320 cur_val = abs((wm8903->sysclk /
1321 (clk_sys_ratios[i].mclk_div *
1322 clk_sys_ratios[i].div)) - fs);
1323
1324 if (cur_val <= best_val) {
1325 clk_config = i;
1326 best_val = cur_val;
1327 }
1328 }
1329
1330 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1331 clock0 |= WM8903_MCLKDIV2;
1332 clk_sys = wm8903->sysclk / 2;
1333 } else {
1334 clock0 &= ~WM8903_MCLKDIV2;
1335 clk_sys = wm8903->sysclk;
1336 }
1337
1338 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1339 WM8903_CLK_SYS_MODE_MASK);
1340 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1341 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1342
f0fba2ad 1343 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1344 clk_sys_ratios[clk_config].rate,
1345 clk_sys_ratios[clk_config].mode,
1346 clk_sys_ratios[clk_config].div);
1347
f0fba2ad 1348 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1349
1350 /* We may not get quite the right frequency if using
1351 * approximate clocks so look for the closest match that is
1352 * higher than the target (we need to ensure that there enough
1353 * BCLKs to clock out the samples).
1354 */
1355 bclk_div = 0;
1356 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1357 i = 1;
1358 while (i < ARRAY_SIZE(bclk_divs)) {
1359 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1360 if (cur_val < 0) /* BCLK table is sorted */
1361 break;
1362 bclk_div = i;
1363 best_val = cur_val;
1364 i++;
1365 }
1366
1367 aif2 &= ~WM8903_BCLK_DIV_MASK;
1368 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1369
f0fba2ad 1370 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1371 bclk_divs[bclk_div].ratio / 10, bclk,
1372 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1373
1374 aif2 |= bclk_divs[bclk_div].div;
1375 aif3 |= bclk / fs;
1376
8d50e447
MB		 1377 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1378 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1379 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1380 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1381 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1382 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1383
1384 return 0;
1385}
1386
7245387e
MB		 1387/**
1388 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1389 *
1390 * @codec: WM8903 codec
1391 * @jack: jack to report detection events on
1392 * @det: value to report for presence detection
1393 * @shrt: value to report for short detection
1394 *
1395 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1396 * being used to bring out signals to the processor then only platform
1397 * data configuration is needed for WM8903 and processor GPIOs should
1398 * be configured using snd_soc_jack_add_gpios() instead.
1399 *
1400 * The current threasholds for detection should be configured using
1401 * micdet_cfg in the platform data. Using this function will force on
1402 * the microphone bias for the device.
1403 */
1404int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1405 int det, int shrt)
1406{
b2c812e2 1407 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1408 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1409
1410 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1411 det, shrt);
1412
1413 /* Store the configuration */
1414 wm8903->mic_jack = jack;
1415 wm8903->mic_det = det;
1416 wm8903->mic_short = shrt;
1417
1418 /* Enable interrupts we've got a report configured for */
1419 if (det)
1420 irq_mask &= ~WM8903_MICDET_EINT;
1421 if (shrt)
1422 irq_mask &= ~WM8903_MICSHRT_EINT;
1423
1424 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1425 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1426 irq_mask);
1427
69266866
MB		 1428 if (det && shrt) {
1429 /* Enable mic detection, this may not have been set through
1430 * platform data (eg, if the defaults are OK). */
1431 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1432 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1433 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1434 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1435 } else {
1436 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1437 WM8903_MICDET_ENA, 0);
1438 }
7245387e
MB		 1439
1440 return 0;
1441}
1442EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1443
8abd16a6
MB		 1444static irqreturn_t wm8903_irq(int irq, void *data)
1445{
f0fba2ad
LG		 1446 struct snd_soc_codec *codec = data;
1447 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1448 int mic_report;
1449 int int_pol;
1450 int int_val = 0;
1451 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1452
7245387e 1453 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1454
7245387e 1455 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1456 dev_dbg(codec->dev, "Write sequencer done\n");
1457 complete(&wm8903->wseq);
1458 }
1459
7245387e
MB		 1460 /*
1461 * The rest is microphone jack detection. We need to manually
1462 * invert the polarity of the interrupt after each event - to
1463 * simplify the code keep track of the last state we reported
1464 * and just invert the relevant bits in both the report and
1465 * the polarity register.
1466 */
1467 mic_report = wm8903->mic_last_report;
1468 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1469
1470 if (int_val & WM8903_MICSHRT_EINT) {
1471 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1472
1473 mic_report ^= wm8903->mic_short;
1474 int_pol ^= WM8903_MICSHRT_INV;
1475 }
1476
1477 if (int_val & WM8903_MICDET_EINT) {
1478 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1479
1480 mic_report ^= wm8903->mic_det;
1481 int_pol ^= WM8903_MICDET_INV;
1482
1483 msleep(wm8903->mic_delay);
1484 }
1485
1486 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1487 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1488
1489 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1490 wm8903->mic_short | wm8903->mic_det);
1491
1492 wm8903->mic_last_report = mic_report;
1493
8abd16a6
MB		 1494 return IRQ_HANDLED;
1495}
1496
f1c0a02f
MB		 1497#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1498 SNDRV_PCM_RATE_11025 | \
1499 SNDRV_PCM_RATE_16000 | \
1500 SNDRV_PCM_RATE_22050 | \
1501 SNDRV_PCM_RATE_32000 | \
1502 SNDRV_PCM_RATE_44100 | \
1503 SNDRV_PCM_RATE_48000 | \
1504 SNDRV_PCM_RATE_88200 | \
1505 SNDRV_PCM_RATE_96000)
1506
1507#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1508 SNDRV_PCM_RATE_11025 | \
1509 SNDRV_PCM_RATE_16000 | \
1510 SNDRV_PCM_RATE_22050 | \
1511 SNDRV_PCM_RATE_32000 | \
1512 SNDRV_PCM_RATE_44100 | \
1513 SNDRV_PCM_RATE_48000)
1514
1515#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1516 SNDRV_PCM_FMTBIT_S20_3LE |\
1517 SNDRV_PCM_FMTBIT_S24_LE)
1518
6335d055 1519static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1520 .hw_params = wm8903_hw_params,
1521 .digital_mute = wm8903_digital_mute,
1522 .set_fmt = wm8903_set_dai_fmt,
1523 .set_sysclk = wm8903_set_dai_sysclk,
1524};
1525
f0fba2ad
LG		 1526static struct snd_soc_dai_driver wm8903_dai = {
1527 .name = "wm8903-hifi",
f1c0a02f
MB		 1528 .playback = {
1529 .stream_name = "Playback",
1530 .channels_min = 2,
1531 .channels_max = 2,
1532 .rates = WM8903_PLAYBACK_RATES,
1533 .formats = WM8903_FORMATS,
1534 },
1535 .capture = {
1536 .stream_name = "Capture",
1537 .channels_min = 2,
1538 .channels_max = 2,
1539 .rates = WM8903_CAPTURE_RATES,
1540 .formats = WM8903_FORMATS,
1541 },
6335d055 1542 .ops = &wm8903_dai_ops,
0d960e88 1543 .symmetric_rates = 1,
f1c0a02f 1544};
f1c0a02f 1545
f0fba2ad 1546static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1547{
f1c0a02f
MB		 1548 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1549
1550 return 0;
1551}
1552
f0fba2ad 1553static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1554{
f1c0a02f
MB		 1555 int i;
1556 u16 *reg_cache = codec->reg_cache;
40aa7030 1557 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1558 GFP_KERNEL);
1559
1560 /* Bring the codec back up to standby first to minimise pop/clicks */
1561 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1562
1563 /* Sync back everything else */
1564 if (tmp_cache) {
1565 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1566 if (tmp_cache[i] != reg_cache[i])
8d50e447 1567 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1568 kfree(tmp_cache);
f1c0a02f 1569 } else {
f0fba2ad 1570 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1571 }
1572
1573 return 0;
1574}
1575
f0fba2ad 1576static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1577{
f0fba2ad
LG		 1578 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1579 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1580 int ret, i;
8abd16a6 1581 int trigger, irq_pol;
f1c0a02f
MB		 1582 u16 val;
1583
8abd16a6 1584 init_completion(&wm8903->wseq);
d58d5d55 1585
8d50e447
MB		 1586 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1587 if (ret != 0) {
f0fba2ad
LG		 1588 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1589 return ret;
8d50e447
MB		 1590 }
1591
1592 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1593 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1594 dev_err(codec->dev,
d58d5d55
MB		 1595 "Device with ID register %x is not a WM8903\n", val);
1596 return -ENODEV;
f1c0a02f
MB		 1597 }
1598
8d50e447 1599 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f0fba2ad 1600 dev_info(codec->dev, "WM8903 revision %d\n",
f1c0a02f
MB		 1601 val & WM8903_CHIP_REV_MASK);
1602
1603 wm8903_reset(codec);
1604
37f88e84 1605 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1606 if (pdata) {
1607 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1608 if (!pdata->gpio_cfg[i])
1609 continue;
1610
1611 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1612 pdata->gpio_cfg[i] & 0xffff);
1613 }
37f88e84
MB		 1614
1615 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1616 pdata->micdet_cfg);
1617
1618 /* Microphone detection needs the WSEQ clock */
1619 if (pdata->micdet_cfg)
1620 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1621 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1622
1623 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1624 }
8abd16a6 1625
f0fba2ad 1626 if (wm8903->irq) {
8abd16a6
MB		 1627 if (pdata && pdata->irq_active_low) {
1628 trigger = IRQF_TRIGGER_LOW;
1629 irq_pol = WM8903_IRQ_POL;
1630 } else {
1631 trigger = IRQF_TRIGGER_HIGH;
1632 irq_pol = 0;
1633 }
1634
1635 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1636 WM8903_IRQ_POL, irq_pol);
1637
f0fba2ad 1638 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1639 trigger | IRQF_ONESHOT,
f0fba2ad 1640 "wm8903", codec);
8abd16a6 1641 if (ret != 0) {
f0fba2ad 1642 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1643 ret);
f0fba2ad 1644 return ret;
8abd16a6
MB		 1645 }
1646
1647 /* Enable write sequencer interrupts */
1648 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1649 WM8903_IM_WSEQ_BUSY_EINT, 0);
1650 }
73b34ead 1651
f1c0a02f
MB		 1652 /* power on device */
1653 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1654
1655 /* Latch volume update bits */
8d50e447 1656 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1657 val |= WM8903_ADCVU;
8d50e447
MB		 1658 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1659 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1660
8d50e447 1661 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1662 val |= WM8903_DACVU;
8d50e447
MB		 1663 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1664 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1665
8d50e447 1666 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1667 val |= WM8903_HPOUTVU;
8d50e447
MB		 1668 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1669 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1670
8d50e447 1671 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1672 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1673 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1674 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1675
8d50e447 1676 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1677 val |= WM8903_SPKVU;
8d50e447
MB		 1678 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1679 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1680
1681 /* Enable DAC soft mute by default */
8d50e447 1682 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1683 val |= WM8903_DAC_MUTEMODE;
8d50e447 1684 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1685
f0fba2ad
LG		 1686 snd_soc_add_controls(codec, wm8903_snd_controls,
1687 ARRAY_SIZE(wm8903_snd_controls));
1688 wm8903_add_widgets(codec);
f1c0a02f 1689
f1c0a02f
MB		 1690 return ret;
1691}
1692
f0fba2ad
LG		 1693/* power down chip */
1694static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1695{
f0fba2ad
LG		 1696 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1697 return 0;
1698}
f1c0a02f 1699
f0fba2ad
LG		 1700static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1701 .probe = wm8903_probe,
1702 .remove = wm8903_remove,
1703 .suspend = wm8903_suspend,
1704 .resume = wm8903_resume,
1705 .set_bias_level = wm8903_set_bias_level,
1706 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1707 .reg_word_size = sizeof(u16),
1708 .reg_cache_default = wm8903_reg_defaults,
1709 .volatile_register = wm8903_volatile_register,
1710};
f1c0a02f 1711
f0fba2ad
LG		 1712#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1713static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1714 const struct i2c_device_id *id)
1715{
1716 struct wm8903_priv *wm8903;
1717 int ret;
f1c0a02f 1718
f0fba2ad
LG		 1719 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1720 if (wm8903 == NULL)
1721 return -ENOMEM;
8abd16a6 1722
f0fba2ad 1723 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1724 wm8903->irq = i2c->irq;
d58d5d55 1725
f0fba2ad
LG		 1726 ret = snd_soc_register_codec(&i2c->dev,
1727 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1728 if (ret < 0)
1729 kfree(wm8903);
1730 return ret;
1731}
f1c0a02f 1732
f0fba2ad
LG		 1733static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1734{
1735 snd_soc_unregister_codec(&client->dev);
1736 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1737 return 0;
1738}
1739
f1c0a02f 1740static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1741 { "wm8903", 0 },
1742 { }
f1c0a02f
MB		 1743};
1744MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1745
1746static struct i2c_driver wm8903_i2c_driver = {
1747 .driver = {
f0fba2ad 1748 .name = "wm8903-codec",
f1c0a02f
MB		 1749 .owner = THIS_MODULE,
1750 },
f0fba2ad
LG		 1751 .probe = wm8903_i2c_probe,
1752 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1753 .id_table = wm8903_i2c_id,
1754};
f0fba2ad 1755#endif
f1c0a02f 1756
f0fba2ad 1757static int __init wm8903_modinit(void)
f1c0a02f 1758{
f1c0a02f 1759 int ret = 0;
f0fba2ad
LG		 1760#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1761 ret = i2c_add_driver(&wm8903_i2c_driver);
1762 if (ret != 0) {
1763 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1764 ret);
f1c0a02f 1765 }
f0fba2ad 1766#endif
f1c0a02f 1767 return ret;
64089b84
MB		 1768}
1769module_init(wm8903_modinit);
1770
1771static void __exit wm8903_exit(void)
1772{
f0fba2ad 1773#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1774 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1775#endif
64089b84
MB		 1776}
1777module_exit(wm8903_exit);
1778
f1c0a02f
MB		 1779MODULE_DESCRIPTION("ASoC WM8903 driver");
1780MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1781MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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