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ASoC: add support for multiple jack types
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
f2c1fe09 226 /* Reference count */
d58d5d55 227 int class_w_users;
d58d5d55 228
8abd16a6
MB		 229 struct completion wseq;
230
7245387e
MB		 231 struct snd_soc_jack *mic_jack;
232 int mic_det;
233 int mic_short;
234 int mic_last_report;
235 int mic_delay;
7cfe5617
SW		 236
237#ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip;
239#endif
d58d5d55
MB		 240};
241
d4754ec9 242static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 243{
244 switch (reg) {
245 case WM8903_SW_RESET_AND_ID:
246 case WM8903_REVISION_NUMBER:
247 case WM8903_INTERRUPT_STATUS_1:
248 case WM8903_WRITE_SEQUENCER_4:
13a9983e
MB		 249 case WM8903_POWER_MANAGEMENT_3:
250 case WM8903_POWER_MANAGEMENT_2:
8d50e447 251 return 1;
f1c0a02f
MB		 252
253 default:
f1c0a02f 254 return 0;
8d50e447 255 }
f1c0a02f
MB		 256}
257
258static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
259{
260 u16 reg[5];
b2c812e2 261 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 262
263 BUG_ON(start > 48);
264
37f88e84 265 /* Enable the sequencer if it's not already on */
8d50e447 266 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 267 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
268 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 269
f0fba2ad 270 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 271
8d50e447 272 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 273 start | WM8903_WSEQ_START);
274
275 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 276 * that will break us out of the poll early.
f1c0a02f
MB		 277 */
278 do {
8abd16a6
MB		 279 wait_for_completion_timeout(&wm8903->wseq,
280 msecs_to_jiffies(10));
f1c0a02f 281
8d50e447 282 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 283 } while (reg[4] & WM8903_WSEQ_BUSY);
284
f0fba2ad 285 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 286
37f88e84
MB		 287 /* Disable the sequencer again if we enabled it */
288 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 289
290 return 0;
291}
292
293static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
294{
295 int i;
296
297 /* There really ought to be something better we can do here :/ */
298 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 299 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 300}
301
302static void wm8903_reset(struct snd_soc_codec *codec)
303{
8d50e447 304 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 305 memcpy(codec->reg_cache, wm8903_reg_defaults,
306 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 307}
308
42768a12
MB		 309static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
310 struct snd_kcontrol *kcontrol, int event)
311{
312 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
313 mdelay(4);
314
315 return 0;
316}
317
f1c0a02f
MB		 318/*
319 * When used with DAC outputs only the WM8903 charge pump supports
320 * operation in class W mode, providing very low power consumption
321 * when used with digital sources. Enable and disable this mode
322 * automatically depending on the mixer configuration.
323 *
324 * All the relevant controls are simple switches.
325 */
326static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
327 struct snd_ctl_elem_value *ucontrol)
328{
329 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
330 struct snd_soc_codec *codec = widget->codec;
b2c812e2 331 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 332 u16 reg;
333 int ret;
334
8d50e447 335 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 336
337 /* Turn it off if we're about to enable bypass */
338 if (ucontrol->value.integer.value[0]) {
339 if (wm8903->class_w_users == 0) {
f0fba2ad 340 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 341 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 342 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
343 }
344 wm8903->class_w_users++;
345 }
346
347 /* Implement the change */
348 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
349
350 /* If we've just disabled the last bypass path turn Class W on */
351 if (!ucontrol->value.integer.value[0]) {
352 if (wm8903->class_w_users == 1) {
f0fba2ad 353 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 354 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 355 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
356 }
357 wm8903->class_w_users--;
358 }
359
f0fba2ad 360 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 361 wm8903->class_w_users);
362
363 return ret;
364}
365
366#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
367{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
368 .info = snd_soc_info_volsw, \
369 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
370 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
371
372
69fff9bb
MB		 373static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
374
375static int wm8903_set_deemph(struct snd_soc_codec *codec)
376{
377 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
378 int val, i, best;
379
380 /* If we're using deemphasis select the nearest available sample
381 * rate.
382 */
383 if (wm8903->deemph) {
384 best = 1;
385 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
386 if (abs(wm8903_deemph[i] - wm8903->fs) <
387 abs(wm8903_deemph[best] - wm8903->fs))
388 best = i;
389 }
390
391 val = best << WM8903_DEEMPH_SHIFT;
392 } else {
393 best = 0;
394 val = 0;
395 }
396
397 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
398 best, wm8903_deemph[best]);
399
400 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
401 WM8903_DEEMPH_MASK, val);
402}
403
404static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
405 struct snd_ctl_elem_value *ucontrol)
406{
407 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
408 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
409
410 ucontrol->value.enumerated.item[0] = wm8903->deemph;
411
412 return 0;
413}
414
415static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_value *ucontrol)
417{
418 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
419 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
420 int deemph = ucontrol->value.enumerated.item[0];
421 int ret = 0;
422
423 if (deemph > 1)
424 return -EINVAL;
425
426 mutex_lock(&codec->mutex);
427 if (wm8903->deemph != deemph) {
428 wm8903->deemph = deemph;
429
430 wm8903_set_deemph(codec);
431
432 ret = 1;
433 }
434 mutex_unlock(&codec->mutex);
435
436 return ret;
437}
438
f1c0a02f
MB		 439/* ALSA can only do steps of .01dB */
440static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
441
291ce18c 442static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 443static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
444
445static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
446static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
447static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
448static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
449static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
450
460f4aae
MB		 451static const char *hpf_mode_text[] = {
452 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
453};
454
455static const struct soc_enum hpf_mode =
456 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
457
dcf9ada3
MB		 458static const char *osr_text[] = {
459 "Low power", "High performance"
460};
461
462static const struct soc_enum adc_osr =
463 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
464
465static const struct soc_enum dac_osr =
466 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
467
f1c0a02f
MB		 468static const char *drc_slope_text[] = {
469 "1", "1/2", "1/4", "1/8", "1/16", "0"
470};
471
472static const struct soc_enum drc_slope_r0 =
473 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
474
475static const struct soc_enum drc_slope_r1 =
476 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
477
478static const char *drc_attack_text[] = {
479 "instantaneous",
480 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
481 "46.4ms", "92.8ms", "185.6ms"
482};
483
484static const struct soc_enum drc_attack =
485 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
486
487static const char *drc_decay_text[] = {
488 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
489 "23.87s", "47.56s"
490};
491
492static const struct soc_enum drc_decay =
493 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
494
495static const char *drc_ff_delay_text[] = {
496 "5 samples", "9 samples"
497};
498
499static const struct soc_enum drc_ff_delay =
500 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
501
502static const char *drc_qr_decay_text[] = {
503 "0.725ms", "1.45ms", "5.8ms"
504};
505
506static const struct soc_enum drc_qr_decay =
507 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
508
509static const char *drc_smoothing_text[] = {
510 "Low", "Medium", "High"
511};
512
513static const struct soc_enum drc_smoothing =
514 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
515
516static const char *soft_mute_text[] = {
517 "Fast (fs/2)", "Slow (fs/32)"
518};
519
520static const struct soc_enum soft_mute =
521 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
522
523static const char *mute_mode_text[] = {
524 "Hard", "Soft"
525};
526
527static const struct soc_enum mute_mode =
528 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
529
f1c0a02f
MB		 530static const char *companding_text[] = {
531 "ulaw", "alaw"
532};
533
534static const struct soc_enum dac_companding =
535 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
536
537static const struct soc_enum adc_companding =
538 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
539
540static const char *input_mode_text[] = {
541 "Single-Ended", "Differential Line", "Differential Mic"
542};
543
544static const struct soc_enum linput_mode_enum =
545 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
546
547static const struct soc_enum rinput_mode_enum =
548 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
549
550static const char *linput_mux_text[] = {
551 "IN1L", "IN2L", "IN3L"
552};
553
554static const struct soc_enum linput_enum =
555 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
556
557static const struct soc_enum linput_inv_enum =
558 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
559
560static const char *rinput_mux_text[] = {
561 "IN1R", "IN2R", "IN3R"
562};
563
564static const struct soc_enum rinput_enum =
565 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
566
567static const struct soc_enum rinput_inv_enum =
568 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
569
570
291ce18c
MB		 571static const char *sidetone_text[] = {
572 "None", "Left", "Right"
573};
574
575static const struct soc_enum lsidetone_enum =
576 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
577
578static const struct soc_enum rsidetone_enum =
579 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
580
1e113bf9
MB		 581static const char *aif_text[] = {
582 "Left", "Right"
583};
584
585static const struct soc_enum lcapture_enum =
586 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
587
588static const struct soc_enum rcapture_enum =
589 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
590
591static const struct soc_enum lplay_enum =
592 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
593
594static const struct soc_enum rplay_enum =
595 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
596
f1c0a02f
MB		 597static const struct snd_kcontrol_new wm8903_snd_controls[] = {
598
599/* Input PGAs - No TLV since the scale depends on PGA mode */
600SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 601 7, 1, 1),
f1c0a02f
MB		 602SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
603 0, 31, 0),
604SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
605 6, 1, 0),
606
607SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 608 7, 1, 1),
f1c0a02f
MB		 609SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
610 0, 31, 0),
611SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
612 6, 1, 0),
613
614/* ADCs */
dcf9ada3 615SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 616SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
617SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 618SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
619SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
620SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 621SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 622 drc_tlv_thresh),
623SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
624SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
625SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
626SOC_ENUM("DRC Attack Rate", drc_attack),
627SOC_ENUM("DRC Decay Rate", drc_decay),
628SOC_ENUM("DRC FF Delay", drc_ff_delay),
629SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
630SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 631SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 632SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
633SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
634SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 635SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 636SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
637
638SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
639 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
640SOC_ENUM("ADC Companding Mode", adc_companding),
641SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
642
291ce18c
MB		 643SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
644 12, 0, digital_sidetone_tlv),
645
f1c0a02f 646/* DAC */
dcf9ada3 647SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 648SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
649 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
650SOC_ENUM("DAC Soft Mute Rate", soft_mute),
651SOC_ENUM("DAC Mute Mode", mute_mode),
652SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 653SOC_ENUM("DAC Companding Mode", dac_companding),
654SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 655SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
656 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 657
658/* Headphones */
659SOC_DOUBLE_R("Headphone Switch",
660 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
661 8, 1, 1),
662SOC_DOUBLE_R("Headphone ZC Switch",
663 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
664 6, 1, 0),
665SOC_DOUBLE_R_TLV("Headphone Volume",
666 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
667 0, 63, 0, out_tlv),
668
669/* Line out */
670SOC_DOUBLE_R("Line Out Switch",
671 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
672 8, 1, 1),
673SOC_DOUBLE_R("Line Out ZC Switch",
674 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
675 6, 1, 0),
676SOC_DOUBLE_R_TLV("Line Out Volume",
677 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
678 0, 63, 0, out_tlv),
679
680/* Speaker */
681SOC_DOUBLE_R("Speaker Switch",
682 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
683SOC_DOUBLE_R("Speaker ZC Switch",
684 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
685SOC_DOUBLE_R_TLV("Speaker Volume",
686 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
687 0, 63, 0, out_tlv),
688};
689
f1c0a02f
MB		 690static const struct snd_kcontrol_new linput_mode_mux =
691 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
692
693static const struct snd_kcontrol_new rinput_mode_mux =
694 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
695
696static const struct snd_kcontrol_new linput_mux =
697 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
698
699static const struct snd_kcontrol_new linput_inv_mux =
700 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
701
702static const struct snd_kcontrol_new rinput_mux =
703 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
704
705static const struct snd_kcontrol_new rinput_inv_mux =
706 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
707
291ce18c
MB		 708static const struct snd_kcontrol_new lsidetone_mux =
709 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
710
711static const struct snd_kcontrol_new rsidetone_mux =
712 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
713
1e113bf9
MB		 714static const struct snd_kcontrol_new lcapture_mux =
715 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
716
717static const struct snd_kcontrol_new rcapture_mux =
718 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
719
720static const struct snd_kcontrol_new lplay_mux =
721 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
722
723static const struct snd_kcontrol_new rplay_mux =
724 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
725
f1c0a02f
MB		 726static const struct snd_kcontrol_new left_output_mixer[] = {
727SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
728SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
729SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 730SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 731};
732
733static const struct snd_kcontrol_new right_output_mixer[] = {
734SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
735SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
736SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 737SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 738};
739
740static const struct snd_kcontrol_new left_speaker_mixer[] = {
741SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
742SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
743SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
744SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 745 0, 1, 0),
f1c0a02f
MB		 746};
747
748static const struct snd_kcontrol_new right_speaker_mixer[] = {
749SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
750SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
751SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
752 1, 1, 0),
753SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 754 0, 1, 0),
f1c0a02f
MB		 755};
756
757static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
758SND_SOC_DAPM_INPUT("IN1L"),
759SND_SOC_DAPM_INPUT("IN1R"),
760SND_SOC_DAPM_INPUT("IN2L"),
761SND_SOC_DAPM_INPUT("IN2R"),
762SND_SOC_DAPM_INPUT("IN3L"),
763SND_SOC_DAPM_INPUT("IN3R"),
764
765SND_SOC_DAPM_OUTPUT("HPOUTL"),
766SND_SOC_DAPM_OUTPUT("HPOUTR"),
767SND_SOC_DAPM_OUTPUT("LINEOUTL"),
768SND_SOC_DAPM_OUTPUT("LINEOUTR"),
769SND_SOC_DAPM_OUTPUT("LOP"),
770SND_SOC_DAPM_OUTPUT("LON"),
771SND_SOC_DAPM_OUTPUT("ROP"),
772SND_SOC_DAPM_OUTPUT("RON"),
773
774SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
775
776SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
777SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
778 &linput_inv_mux),
779SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
780
781SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
782SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
783 &rinput_inv_mux),
784SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
785
786SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
787SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
788
1e113bf9
MB		 789SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
790SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
791
792SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
793SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
794
795SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
796SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 797
291ce18c
MB		 798SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
799SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
800
1e113bf9
MB		 801SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
802SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
803
804SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
805SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
806
807SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
808SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 809
810SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
811 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
812SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
813 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
814
815SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
816 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
817SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
818 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
819
13a9983e
MB		 820SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
821 4, 0, NULL, 0),
822SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
823 0, 0, NULL, 0),
824
825SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
826 NULL, 0),
827SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
828 NULL, 0),
829
830SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
831SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
832SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
833SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
834SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
835SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
836
837SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
838 NULL, 0),
839SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
840 NULL, 0),
841SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
842 NULL, 0),
843SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
844 NULL, 0),
845SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
846 NULL, 0),
847SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
848 NULL, 0),
849
850SND_SOC_DAPM_PGA_S("HPL_DCS", 3, WM8903_DC_SERVO_0, 3, 0, NULL, 0),
851SND_SOC_DAPM_PGA_S("HPR_DCS", 3, WM8903_DC_SERVO_0, 2, 0, NULL, 0),
852SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, WM8903_DC_SERVO_0, 1, 0, NULL, 0),
853SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, WM8903_DC_SERVO_0, 0, 0, NULL, 0),
f1c0a02f
MB		 854
855SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
856 NULL, 0),
857SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
858 NULL, 0),
859
42768a12
MB		 860SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
861 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 862SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 863SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 864};
865
866static const struct snd_soc_dapm_route intercon[] = {
867
2c8be5a2
MB		 868 { "CLK_DSP", NULL, "CLK_SYS" },
869 { "Mic Bias", NULL, "CLK_SYS" },
870 { "HPL_DCS", NULL, "CLK_SYS" },
871 { "HPR_DCS", NULL, "CLK_SYS" },
872 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
873 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
874
f1c0a02f
MB		 875 { "Left Input Mux", "IN1L", "IN1L" },
876 { "Left Input Mux", "IN2L", "IN2L" },
877 { "Left Input Mux", "IN3L", "IN3L" },
878
879 { "Left Input Inverting Mux", "IN1L", "IN1L" },
880 { "Left Input Inverting Mux", "IN2L", "IN2L" },
881 { "Left Input Inverting Mux", "IN3L", "IN3L" },
882
883 { "Right Input Mux", "IN1R", "IN1R" },
884 { "Right Input Mux", "IN2R", "IN2R" },
885 { "Right Input Mux", "IN3R", "IN3R" },
886
887 { "Right Input Inverting Mux", "IN1R", "IN1R" },
888 { "Right Input Inverting Mux", "IN2R", "IN2R" },
889 { "Right Input Inverting Mux", "IN3R", "IN3R" },
890
891 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
892 { "Left Input Mode Mux", "Differential Line",
893 "Left Input Mux" },
894 { "Left Input Mode Mux", "Differential Line",
895 "Left Input Inverting Mux" },
896 { "Left Input Mode Mux", "Differential Mic",
897 "Left Input Mux" },
898 { "Left Input Mode Mux", "Differential Mic",
899 "Left Input Inverting Mux" },
900
901 { "Right Input Mode Mux", "Single-Ended",
902 "Right Input Inverting Mux" },
903 { "Right Input Mode Mux", "Differential Line",
904 "Right Input Mux" },
905 { "Right Input Mode Mux", "Differential Line",
906 "Right Input Inverting Mux" },
907 { "Right Input Mode Mux", "Differential Mic",
908 "Right Input Mux" },
909 { "Right Input Mode Mux", "Differential Mic",
910 "Right Input Inverting Mux" },
911
912 { "Left Input PGA", NULL, "Left Input Mode Mux" },
913 { "Right Input PGA", NULL, "Right Input Mode Mux" },
914
1e113bf9
MB		 915 { "Left Capture Mux", "Left", "ADCL" },
916 { "Left Capture Mux", "Right", "ADCR" },
917
918 { "Right Capture Mux", "Left", "ADCL" },
919 { "Right Capture Mux", "Right", "ADCR" },
920
921 { "AIFTXL", NULL, "Left Capture Mux" },
922 { "AIFTXR", NULL, "Right Capture Mux" },
923
f1c0a02f 924 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 925 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 926 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 927 { "ADCR", NULL, "CLK_DSP" },
928
1e113bf9
MB		 929 { "Left Playback Mux", "Left", "AIFRXL" },
930 { "Left Playback Mux", "Right", "AIFRXR" },
931
932 { "Right Playback Mux", "Left", "AIFRXL" },
933 { "Right Playback Mux", "Right", "AIFRXR" },
934
291ce18c
MB		 935 { "DACL Sidetone", "Left", "ADCL" },
936 { "DACL Sidetone", "Right", "ADCR" },
937 { "DACR Sidetone", "Left", "ADCL" },
938 { "DACR Sidetone", "Right", "ADCR" },
939
1e113bf9 940 { "DACL", NULL, "Left Playback Mux" },
291ce18c 941 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 942 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 943
944 { "DACR", NULL, "Right Playback Mux" },
291ce18c 945 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 946 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 947
948 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
949 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
950 { "Left Output Mixer", "DACL Switch", "DACL" },
951 { "Left Output Mixer", "DACR Switch", "DACR" },
952
953 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
954 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
955 { "Right Output Mixer", "DACL Switch", "DACL" },
956 { "Right Output Mixer", "DACR Switch", "DACR" },
957
958 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
959 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
960 { "Left Speaker Mixer", "DACL Switch", "DACL" },
961 { "Left Speaker Mixer", "DACR Switch", "DACR" },
962
963 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
964 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
965 { "Right Speaker Mixer", "DACL Switch", "DACL" },
966 { "Right Speaker Mixer", "DACR Switch", "DACR" },
967
968 { "Left Line Output PGA", NULL, "Left Output Mixer" },
969 { "Right Line Output PGA", NULL, "Right Output Mixer" },
970
971 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
972 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
973
974 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
975 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
976
13a9983e
MB		 977 { "HPL_ENA_DLY", NULL, "Left Headphone Output PGA" },
978 { "HPR_ENA_DLY", NULL, "Right Headphone Output PGA" },
979 { "LINEOUTL_ENA_DLY", NULL, "Left Line Output PGA" },
980 { "LINEOUTR_ENA_DLY", NULL, "Right Line Output PGA" },
981
982 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
983 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
984 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
985 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
986
987 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
988 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
989 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
990 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
991
992 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
993 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
994 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
995 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
996
997 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
998 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
999 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1000 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1001
1002 { "LOP", NULL, "Left Speaker PGA" },
1003 { "LON", NULL, "Left Speaker PGA" },
1004
1005 { "ROP", NULL, "Right Speaker PGA" },
1006 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1007
1008 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1009 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1010 { "Left Line Output PGA", NULL, "Charge Pump" },
1011 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1012};
1013
1014static int wm8903_add_widgets(struct snd_soc_codec *codec)
1015{
ce6120cc 1016 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1017
ce6120cc
LG		 1018 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1019 ARRAY_SIZE(wm8903_dapm_widgets));
1020 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1021
f1c0a02f
MB		 1022 return 0;
1023}
1024
1025static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1026 enum snd_soc_bias_level level)
1027{
524d7692 1028 u16 reg;
f1c0a02f
MB		 1029
1030 switch (level) {
1031 case SND_SOC_BIAS_ON:
1032 case SND_SOC_BIAS_PREPARE:
8d50e447 1033 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1034 reg &= ~(WM8903_VMID_RES_MASK);
1035 reg |= WM8903_VMID_RES_50K;
8d50e447 1036 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1037 break;
1038
1039 case SND_SOC_BIAS_STANDBY:
ce6120cc 1040 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1041 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1042 WM8903_CLK_SYS_ENA);
1043
4dbfe809 1044 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1045 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1046 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1047 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1048
f1c0a02f
MB		 1049 wm8903_run_sequence(codec, 0);
1050 wm8903_sync_reg_cache(codec, codec->reg_cache);
1051
f1c0a02f
MB		 1052 /* By default no bypass paths are enabled so
1053 * enable Class W support.
1054 */
f0fba2ad 1055 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1056 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1057 WM8903_CP_DYN_FREQ |
1058 WM8903_CP_DYN_V,
1059 WM8903_CP_DYN_FREQ |
1060 WM8903_CP_DYN_V);
f1c0a02f
MB		 1061 }
1062
8d50e447 1063 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1064 reg &= ~(WM8903_VMID_RES_MASK);
1065 reg |= WM8903_VMID_RES_250K;
8d50e447 1066 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1067 break;
1068
1069 case SND_SOC_BIAS_OFF:
2c8be5a2
MB		 1070 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1071 WM8903_CLK_SYS_ENA, WM8903_CLK_SYS_ENA);
f1c0a02f 1072 wm8903_run_sequence(codec, 32);
2c8be5a2
MB		 1073 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1074 WM8903_CLK_SYS_ENA, 0);
f1c0a02f
MB		 1075 break;
1076 }
1077
ce6120cc 1078 codec->dapm.bias_level = level;
f1c0a02f
MB		 1079
1080 return 0;
1081}
1082
1083static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1084 int clk_id, unsigned int freq, int dir)
1085{
1086 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1087 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1088
1089 wm8903->sysclk = freq;
1090
1091 return 0;
1092}
1093
1094static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1095 unsigned int fmt)
1096{
1097 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1098 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1099
1100 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1101 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1102
1103 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1104 case SND_SOC_DAIFMT_CBS_CFS:
1105 break;
1106 case SND_SOC_DAIFMT_CBS_CFM:
1107 aif1 |= WM8903_LRCLK_DIR;
1108 break;
1109 case SND_SOC_DAIFMT_CBM_CFM:
1110 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1111 break;
1112 case SND_SOC_DAIFMT_CBM_CFS:
1113 aif1 |= WM8903_BCLK_DIR;
1114 break;
1115 default:
1116 return -EINVAL;
1117 }
1118
1119 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1120 case SND_SOC_DAIFMT_DSP_A:
1121 aif1 |= 0x3;
1122 break;
1123 case SND_SOC_DAIFMT_DSP_B:
1124 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1125 break;
1126 case SND_SOC_DAIFMT_I2S:
1127 aif1 |= 0x2;
1128 break;
1129 case SND_SOC_DAIFMT_RIGHT_J:
1130 aif1 |= 0x1;
1131 break;
1132 case SND_SOC_DAIFMT_LEFT_J:
1133 break;
1134 default:
1135 return -EINVAL;
1136 }
1137
1138 /* Clock inversion */
1139 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1140 case SND_SOC_DAIFMT_DSP_A:
1141 case SND_SOC_DAIFMT_DSP_B:
1142 /* frame inversion not valid for DSP modes */
1143 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1144 case SND_SOC_DAIFMT_NB_NF:
1145 break;
1146 case SND_SOC_DAIFMT_IB_NF:
1147 aif1 |= WM8903_AIF_BCLK_INV;
1148 break;
1149 default:
1150 return -EINVAL;
1151 }
1152 break;
1153 case SND_SOC_DAIFMT_I2S:
1154 case SND_SOC_DAIFMT_RIGHT_J:
1155 case SND_SOC_DAIFMT_LEFT_J:
1156 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1157 case SND_SOC_DAIFMT_NB_NF:
1158 break;
1159 case SND_SOC_DAIFMT_IB_IF:
1160 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1161 break;
1162 case SND_SOC_DAIFMT_IB_NF:
1163 aif1 |= WM8903_AIF_BCLK_INV;
1164 break;
1165 case SND_SOC_DAIFMT_NB_IF:
1166 aif1 |= WM8903_AIF_LRCLK_INV;
1167 break;
1168 default:
1169 return -EINVAL;
1170 }
1171 break;
1172 default:
1173 return -EINVAL;
1174 }
1175
8d50e447 1176 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1177
1178 return 0;
1179}
1180
1181static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1182{
1183 struct snd_soc_codec *codec = codec_dai->codec;
1184 u16 reg;
1185
8d50e447 1186 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1187
1188 if (mute)
1189 reg |= WM8903_DAC_MUTE;
1190 else
1191 reg &= ~WM8903_DAC_MUTE;
1192
8d50e447 1193 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1194
1195 return 0;
1196}
1197
1198/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1199 * for optimal performance so we list the lower rates first and match
1200 * on the last match we find. */
1201static struct {
1202 int div;
1203 int rate;
1204 int mode;
1205 int mclk_div;
1206} clk_sys_ratios[] = {
1207 { 64, 0x0, 0x0, 1 },
1208 { 68, 0x0, 0x1, 1 },
1209 { 125, 0x0, 0x2, 1 },
1210 { 128, 0x1, 0x0, 1 },
1211 { 136, 0x1, 0x1, 1 },
1212 { 192, 0x2, 0x0, 1 },
1213 { 204, 0x2, 0x1, 1 },
1214
1215 { 64, 0x0, 0x0, 2 },
1216 { 68, 0x0, 0x1, 2 },
1217 { 125, 0x0, 0x2, 2 },
1218 { 128, 0x1, 0x0, 2 },
1219 { 136, 0x1, 0x1, 2 },
1220 { 192, 0x2, 0x0, 2 },
1221 { 204, 0x2, 0x1, 2 },
1222
1223 { 250, 0x2, 0x2, 1 },
1224 { 256, 0x3, 0x0, 1 },
1225 { 272, 0x3, 0x1, 1 },
1226 { 384, 0x4, 0x0, 1 },
1227 { 408, 0x4, 0x1, 1 },
1228 { 375, 0x4, 0x2, 1 },
1229 { 512, 0x5, 0x0, 1 },
1230 { 544, 0x5, 0x1, 1 },
1231 { 500, 0x5, 0x2, 1 },
1232 { 768, 0x6, 0x0, 1 },
1233 { 816, 0x6, 0x1, 1 },
1234 { 750, 0x6, 0x2, 1 },
1235 { 1024, 0x7, 0x0, 1 },
1236 { 1088, 0x7, 0x1, 1 },
1237 { 1000, 0x7, 0x2, 1 },
1238 { 1408, 0x8, 0x0, 1 },
1239 { 1496, 0x8, 0x1, 1 },
1240 { 1536, 0x9, 0x0, 1 },
1241 { 1632, 0x9, 0x1, 1 },
1242 { 1500, 0x9, 0x2, 1 },
1243
1244 { 250, 0x2, 0x2, 2 },
1245 { 256, 0x3, 0x0, 2 },
1246 { 272, 0x3, 0x1, 2 },
1247 { 384, 0x4, 0x0, 2 },
1248 { 408, 0x4, 0x1, 2 },
1249 { 375, 0x4, 0x2, 2 },
1250 { 512, 0x5, 0x0, 2 },
1251 { 544, 0x5, 0x1, 2 },
1252 { 500, 0x5, 0x2, 2 },
1253 { 768, 0x6, 0x0, 2 },
1254 { 816, 0x6, 0x1, 2 },
1255 { 750, 0x6, 0x2, 2 },
1256 { 1024, 0x7, 0x0, 2 },
1257 { 1088, 0x7, 0x1, 2 },
1258 { 1000, 0x7, 0x2, 2 },
1259 { 1408, 0x8, 0x0, 2 },
1260 { 1496, 0x8, 0x1, 2 },
1261 { 1536, 0x9, 0x0, 2 },
1262 { 1632, 0x9, 0x1, 2 },
1263 { 1500, 0x9, 0x2, 2 },
1264};
1265
1266/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1267static struct {
1268 int ratio;
1269 int div;
1270} bclk_divs[] = {
1271 { 10, 0 },
f1c0a02f
MB		 1272 { 20, 2 },
1273 { 30, 3 },
1274 { 40, 4 },
1275 { 50, 5 },
f1c0a02f
MB		 1276 { 60, 7 },
1277 { 80, 8 },
1278 { 100, 9 },
f1c0a02f
MB		 1279 { 120, 11 },
1280 { 160, 12 },
1281 { 200, 13 },
1282 { 220, 14 },
1283 { 240, 15 },
f1c0a02f
MB		 1284 { 300, 17 },
1285 { 320, 18 },
1286 { 440, 19 },
1287 { 480, 20 },
1288};
1289
1290/* Sample rates for DSP */
1291static struct {
1292 int rate;
1293 int value;
1294} sample_rates[] = {
1295 { 8000, 0 },
1296 { 11025, 1 },
1297 { 12000, 2 },
1298 { 16000, 3 },
1299 { 22050, 4 },
1300 { 24000, 5 },
1301 { 32000, 6 },
1302 { 44100, 7 },
1303 { 48000, 8 },
1304 { 88200, 9 },
1305 { 96000, 10 },
1306 { 0, 0 },
1307};
1308
f1c0a02f 1309static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1310 struct snd_pcm_hw_params *params,
1311 struct snd_soc_dai *dai)
f1c0a02f
MB		 1312{
1313 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1314 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1315 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1316 int fs = params_rate(params);
1317 int bclk;
1318 int bclk_div;
1319 int i;
1320 int dsp_config;
1321 int clk_config;
1322 int best_val;
1323 int cur_val;
1324 int clk_sys;
1325
8d50e447
MB		 1326 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1327 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1328 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1329 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1330 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1331 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1332
9e79261f
MB		 1333 /* Enable sloping stopband filter for low sample rates */
1334 if (fs <= 24000)
1335 dac_digital1 |= WM8903_DAC_SB_FILT;
1336 else
1337 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1338
f1c0a02f
MB		 1339 /* Configure sample rate logic for DSP - choose nearest rate */
1340 dsp_config = 0;
1341 best_val = abs(sample_rates[dsp_config].rate - fs);
1342 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1343 cur_val = abs(sample_rates[i].rate - fs);
1344 if (cur_val <= best_val) {
1345 dsp_config = i;
1346 best_val = cur_val;
1347 }
1348 }
1349
f0fba2ad 1350 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1351 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1352 clock1 |= sample_rates[dsp_config].value;
1353
1354 aif1 &= ~WM8903_AIF_WL_MASK;
1355 bclk = 2 * fs;
1356 switch (params_format(params)) {
1357 case SNDRV_PCM_FORMAT_S16_LE:
1358 bclk *= 16;
1359 break;
1360 case SNDRV_PCM_FORMAT_S20_3LE:
1361 bclk *= 20;
1362 aif1 |= 0x4;
1363 break;
1364 case SNDRV_PCM_FORMAT_S24_LE:
1365 bclk *= 24;
1366 aif1 |= 0x8;
1367 break;
1368 case SNDRV_PCM_FORMAT_S32_LE:
1369 bclk *= 32;
1370 aif1 |= 0xc;
1371 break;
1372 default:
1373 return -EINVAL;
1374 }
1375
f0fba2ad 1376 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1377 wm8903->sysclk, fs);
1378
1379 /* We may not have an MCLK which allows us to generate exactly
1380 * the clock we want, particularly with USB derived inputs, so
1381 * approximate.
1382 */
1383 clk_config = 0;
1384 best_val = abs((wm8903->sysclk /
1385 (clk_sys_ratios[0].mclk_div *
1386 clk_sys_ratios[0].div)) - fs);
1387 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1388 cur_val = abs((wm8903->sysclk /
1389 (clk_sys_ratios[i].mclk_div *
1390 clk_sys_ratios[i].div)) - fs);
1391
1392 if (cur_val <= best_val) {
1393 clk_config = i;
1394 best_val = cur_val;
1395 }
1396 }
1397
1398 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1399 clock0 |= WM8903_MCLKDIV2;
1400 clk_sys = wm8903->sysclk / 2;
1401 } else {
1402 clock0 &= ~WM8903_MCLKDIV2;
1403 clk_sys = wm8903->sysclk;
1404 }
1405
1406 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1407 WM8903_CLK_SYS_MODE_MASK);
1408 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1409 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1410
f0fba2ad 1411 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1412 clk_sys_ratios[clk_config].rate,
1413 clk_sys_ratios[clk_config].mode,
1414 clk_sys_ratios[clk_config].div);
1415
f0fba2ad 1416 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1417
1418 /* We may not get quite the right frequency if using
1419 * approximate clocks so look for the closest match that is
1420 * higher than the target (we need to ensure that there enough
1421 * BCLKs to clock out the samples).
1422 */
1423 bclk_div = 0;
1424 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1425 i = 1;
1426 while (i < ARRAY_SIZE(bclk_divs)) {
1427 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1428 if (cur_val < 0) /* BCLK table is sorted */
1429 break;
1430 bclk_div = i;
1431 best_val = cur_val;
1432 i++;
1433 }
1434
1435 aif2 &= ~WM8903_BCLK_DIV_MASK;
1436 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1437
f0fba2ad 1438 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1439 bclk_divs[bclk_div].ratio / 10, bclk,
1440 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1441
1442 aif2 |= bclk_divs[bclk_div].div;
1443 aif3 |= bclk / fs;
1444
69fff9bb
MB		 1445 wm8903->fs = params_rate(params);
1446 wm8903_set_deemph(codec);
1447
8d50e447
MB		 1448 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1449 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1450 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1451 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1452 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1453 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1454
1455 return 0;
1456}
1457
7245387e
MB		 1458/**
1459 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1460 *
1461 * @codec: WM8903 codec
1462 * @jack: jack to report detection events on
1463 * @det: value to report for presence detection
1464 * @shrt: value to report for short detection
1465 *
1466 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1467 * being used to bring out signals to the processor then only platform
1468 * data configuration is needed for WM8903 and processor GPIOs should
1469 * be configured using snd_soc_jack_add_gpios() instead.
1470 *
1471 * The current threasholds for detection should be configured using
1472 * micdet_cfg in the platform data. Using this function will force on
1473 * the microphone bias for the device.
1474 */
1475int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1476 int det, int shrt)
1477{
b2c812e2 1478 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1479 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1480
1481 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1482 det, shrt);
1483
1484 /* Store the configuration */
1485 wm8903->mic_jack = jack;
1486 wm8903->mic_det = det;
1487 wm8903->mic_short = shrt;
1488
1489 /* Enable interrupts we've got a report configured for */
1490 if (det)
1491 irq_mask &= ~WM8903_MICDET_EINT;
1492 if (shrt)
1493 irq_mask &= ~WM8903_MICSHRT_EINT;
1494
1495 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1496 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1497 irq_mask);
1498
69266866
MB		 1499 if (det && shrt) {
1500 /* Enable mic detection, this may not have been set through
1501 * platform data (eg, if the defaults are OK). */
1502 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1503 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1504 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1505 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1506 } else {
1507 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1508 WM8903_MICDET_ENA, 0);
1509 }
7245387e
MB		 1510
1511 return 0;
1512}
1513EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1514
8abd16a6
MB		 1515static irqreturn_t wm8903_irq(int irq, void *data)
1516{
f0fba2ad
LG		 1517 struct snd_soc_codec *codec = data;
1518 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1519 int mic_report;
1520 int int_pol;
1521 int int_val = 0;
1522 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1523
7245387e 1524 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1525
7245387e 1526 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1527 dev_dbg(codec->dev, "Write sequencer done\n");
1528 complete(&wm8903->wseq);
1529 }
1530
7245387e
MB		 1531 /*
1532 * The rest is microphone jack detection. We need to manually
1533 * invert the polarity of the interrupt after each event - to
1534 * simplify the code keep track of the last state we reported
1535 * and just invert the relevant bits in both the report and
1536 * the polarity register.
1537 */
1538 mic_report = wm8903->mic_last_report;
1539 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1540
1435b940 1541#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1542 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1543 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1544#endif
2bbb5d66 1545
7245387e
MB		 1546 if (int_val & WM8903_MICSHRT_EINT) {
1547 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1548
1549 mic_report ^= wm8903->mic_short;
1550 int_pol ^= WM8903_MICSHRT_INV;
1551 }
1552
1553 if (int_val & WM8903_MICDET_EINT) {
1554 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1555
1556 mic_report ^= wm8903->mic_det;
1557 int_pol ^= WM8903_MICDET_INV;
1558
1559 msleep(wm8903->mic_delay);
1560 }
1561
1562 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1563 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1564
1565 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1566 wm8903->mic_short | wm8903->mic_det);
1567
1568 wm8903->mic_last_report = mic_report;
1569
8abd16a6
MB		 1570 return IRQ_HANDLED;
1571}
1572
f1c0a02f
MB		 1573#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1574 SNDRV_PCM_RATE_11025 | \
1575 SNDRV_PCM_RATE_16000 | \
1576 SNDRV_PCM_RATE_22050 | \
1577 SNDRV_PCM_RATE_32000 | \
1578 SNDRV_PCM_RATE_44100 | \
1579 SNDRV_PCM_RATE_48000 | \
1580 SNDRV_PCM_RATE_88200 | \
1581 SNDRV_PCM_RATE_96000)
1582
1583#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1584 SNDRV_PCM_RATE_11025 | \
1585 SNDRV_PCM_RATE_16000 | \
1586 SNDRV_PCM_RATE_22050 | \
1587 SNDRV_PCM_RATE_32000 | \
1588 SNDRV_PCM_RATE_44100 | \
1589 SNDRV_PCM_RATE_48000)
1590
1591#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1592 SNDRV_PCM_FMTBIT_S20_3LE |\
1593 SNDRV_PCM_FMTBIT_S24_LE)
1594
6335d055 1595static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1596 .hw_params = wm8903_hw_params,
1597 .digital_mute = wm8903_digital_mute,
1598 .set_fmt = wm8903_set_dai_fmt,
1599 .set_sysclk = wm8903_set_dai_sysclk,
1600};
1601
f0fba2ad
LG		 1602static struct snd_soc_dai_driver wm8903_dai = {
1603 .name = "wm8903-hifi",
f1c0a02f
MB		 1604 .playback = {
1605 .stream_name = "Playback",
1606 .channels_min = 2,
1607 .channels_max = 2,
1608 .rates = WM8903_PLAYBACK_RATES,
1609 .formats = WM8903_FORMATS,
1610 },
1611 .capture = {
1612 .stream_name = "Capture",
1613 .channels_min = 2,
1614 .channels_max = 2,
1615 .rates = WM8903_CAPTURE_RATES,
1616 .formats = WM8903_FORMATS,
1617 },
6335d055 1618 .ops = &wm8903_dai_ops,
0d960e88 1619 .symmetric_rates = 1,
f1c0a02f 1620};
f1c0a02f 1621
f0fba2ad 1622static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1623{
f1c0a02f
MB		 1624 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1625
1626 return 0;
1627}
1628
f0fba2ad 1629static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1630{
f1c0a02f
MB		 1631 int i;
1632 u16 *reg_cache = codec->reg_cache;
40aa7030 1633 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1634 GFP_KERNEL);
1635
1636 /* Bring the codec back up to standby first to minimise pop/clicks */
1637 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1638
1639 /* Sync back everything else */
1640 if (tmp_cache) {
1641 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1642 if (tmp_cache[i] != reg_cache[i])
8d50e447 1643 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1644 kfree(tmp_cache);
f1c0a02f 1645 } else {
f0fba2ad 1646 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1647 }
1648
1649 return 0;
1650}
1651
7cfe5617
SW		 1652#ifdef CONFIG_GPIOLIB
1653static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1654{
1655 return container_of(chip, struct wm8903_priv, gpio_chip);
1656}
1657
1658static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1659{
1660 if (offset >= WM8903_NUM_GPIO)
1661 return -EINVAL;
1662
1663 return 0;
1664}
1665
1666static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1667{
1668 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1669 struct snd_soc_codec *codec = wm8903->codec;
1670 unsigned int mask, val;
1671
1672 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1673 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1674 WM8903_GP1_DIR;
1675
1676 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1677 mask, val);
1678}
1679
1680static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1681{
1682 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1683 struct snd_soc_codec *codec = wm8903->codec;
1684 int reg;
1685
1686 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1687
1688 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1689}
1690
1691static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1692 unsigned offset, int value)
1693{
1694 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1695 struct snd_soc_codec *codec = wm8903->codec;
1696 unsigned int mask, val;
1697
1698 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1699 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1700 (value << WM8903_GP2_LVL_SHIFT);
1701
1702 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1703 mask, val);
1704}
1705
1706static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1707{
1708 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1709 struct snd_soc_codec *codec = wm8903->codec;
1710
1711 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1712 WM8903_GP1_LVL_MASK,
1713 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1714}
1715
1716static struct gpio_chip wm8903_template_chip = {
1717 .label = "wm8903",
1718 .owner = THIS_MODULE,
1719 .request = wm8903_gpio_request,
1720 .direction_input = wm8903_gpio_direction_in,
1721 .get = wm8903_gpio_get,
1722 .direction_output = wm8903_gpio_direction_out,
1723 .set = wm8903_gpio_set,
1724 .can_sleep = 1,
1725};
1726
1727static void wm8903_init_gpio(struct snd_soc_codec *codec)
1728{
1729 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1730 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1731 int ret;
1732
1733 wm8903->gpio_chip = wm8903_template_chip;
1734 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1735 wm8903->gpio_chip.dev = codec->dev;
1736
1737 if (pdata && pdata->gpio_base)
1738 wm8903->gpio_chip.base = pdata->gpio_base;
1739 else
1740 wm8903->gpio_chip.base = -1;
1741
1742 ret = gpiochip_add(&wm8903->gpio_chip);
1743 if (ret != 0)
1744 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1745}
1746
1747static void wm8903_free_gpio(struct snd_soc_codec *codec)
1748{
1749 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1750 int ret;
1751
1752 ret = gpiochip_remove(&wm8903->gpio_chip);
1753 if (ret != 0)
1754 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1755}
1756#else
1757static void wm8903_init_gpio(struct snd_soc_codec *codec)
1758{
1759}
1760
1761static void wm8903_free_gpio(struct snd_soc_codec *codec)
1762{
1763}
1764#endif
1765
f0fba2ad 1766static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1767{
f0fba2ad
LG		 1768 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1769 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1770 int ret, i;
8abd16a6 1771 int trigger, irq_pol;
f1c0a02f
MB		 1772 u16 val;
1773
7cfe5617 1774 wm8903->codec = codec;
8abd16a6 1775 init_completion(&wm8903->wseq);
d58d5d55 1776
8d50e447
MB		 1777 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1778 if (ret != 0) {
f0fba2ad
LG		 1779 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1780 return ret;
8d50e447
MB		 1781 }
1782
1783 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1784 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1785 dev_err(codec->dev,
d58d5d55
MB		 1786 "Device with ID register %x is not a WM8903\n", val);
1787 return -ENODEV;
f1c0a02f
MB		 1788 }
1789
8d50e447 1790 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1791 dev_info(codec->dev, "WM8903 revision %c\n",
1792 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1793
1794 wm8903_reset(codec);
1795
37f88e84 1796 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1797 if (pdata) {
1798 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1799 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1800 continue;
1801
1802 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1803 pdata->gpio_cfg[i] & 0xffff);
1804 }
37f88e84
MB		 1805
1806 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1807 pdata->micdet_cfg);
1808
1809 /* Microphone detection needs the WSEQ clock */
1810 if (pdata->micdet_cfg)
1811 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1812 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1813
1814 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1815 }
8abd16a6 1816
f0fba2ad 1817 if (wm8903->irq) {
8abd16a6
MB		 1818 if (pdata && pdata->irq_active_low) {
1819 trigger = IRQF_TRIGGER_LOW;
1820 irq_pol = WM8903_IRQ_POL;
1821 } else {
1822 trigger = IRQF_TRIGGER_HIGH;
1823 irq_pol = 0;
1824 }
1825
1826 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1827 WM8903_IRQ_POL, irq_pol);
1828
f0fba2ad 1829 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1830 trigger | IRQF_ONESHOT,
f0fba2ad 1831 "wm8903", codec);
8abd16a6 1832 if (ret != 0) {
f0fba2ad 1833 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1834 ret);
f0fba2ad 1835 return ret;
8abd16a6
MB		 1836 }
1837
1838 /* Enable write sequencer interrupts */
1839 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1840 WM8903_IM_WSEQ_BUSY_EINT, 0);
1841 }
73b34ead 1842
f1c0a02f
MB		 1843 /* power on device */
1844 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1845
1846 /* Latch volume update bits */
8d50e447 1847 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1848 val |= WM8903_ADCVU;
8d50e447
MB		 1849 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1850 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1851
8d50e447 1852 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1853 val |= WM8903_DACVU;
8d50e447
MB		 1854 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1855 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1856
8d50e447 1857 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1858 val |= WM8903_HPOUTVU;
8d50e447
MB		 1859 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1860 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1861
8d50e447 1862 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1863 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1864 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1865 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1866
8d50e447 1867 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1868 val |= WM8903_SPKVU;
8d50e447
MB		 1869 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1870 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1871
1872 /* Enable DAC soft mute by default */
e12adab0
MB		 1873 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
1874 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
1875 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 1876
f0fba2ad
LG		 1877 snd_soc_add_controls(codec, wm8903_snd_controls,
1878 ARRAY_SIZE(wm8903_snd_controls));
1879 wm8903_add_widgets(codec);
f1c0a02f 1880
7cfe5617
SW		 1881 wm8903_init_gpio(codec);
1882
f1c0a02f
MB		 1883 return ret;
1884}
1885
f0fba2ad
LG		 1886/* power down chip */
1887static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1888{
7cfe5617 1889 wm8903_free_gpio(codec);
f0fba2ad
LG		 1890 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1891 return 0;
1892}
f1c0a02f 1893
f0fba2ad
LG		 1894static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1895 .probe = wm8903_probe,
1896 .remove = wm8903_remove,
1897 .suspend = wm8903_suspend,
1898 .resume = wm8903_resume,
1899 .set_bias_level = wm8903_set_bias_level,
1900 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1901 .reg_word_size = sizeof(u16),
1902 .reg_cache_default = wm8903_reg_defaults,
1903 .volatile_register = wm8903_volatile_register,
1904};
f1c0a02f 1905
f0fba2ad
LG		 1906#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1907static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1908 const struct i2c_device_id *id)
1909{
1910 struct wm8903_priv *wm8903;
1911 int ret;
f1c0a02f 1912
f0fba2ad
LG		 1913 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1914 if (wm8903 == NULL)
1915 return -ENOMEM;
8abd16a6 1916
f0fba2ad 1917 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1918 wm8903->irq = i2c->irq;
d58d5d55 1919
f0fba2ad
LG		 1920 ret = snd_soc_register_codec(&i2c->dev,
1921 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1922 if (ret < 0)
1923 kfree(wm8903);
1924 return ret;
1925}
f1c0a02f 1926
f0fba2ad
LG		 1927static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1928{
1929 snd_soc_unregister_codec(&client->dev);
1930 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1931 return 0;
1932}
1933
f1c0a02f 1934static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1935 { "wm8903", 0 },
1936 { }
f1c0a02f
MB		 1937};
1938MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1939
1940static struct i2c_driver wm8903_i2c_driver = {
1941 .driver = {
4b592c91 1942 .name = "wm8903",
f1c0a02f
MB		 1943 .owner = THIS_MODULE,
1944 },
f0fba2ad
LG		 1945 .probe = wm8903_i2c_probe,
1946 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1947 .id_table = wm8903_i2c_id,
1948};
f0fba2ad 1949#endif
f1c0a02f 1950
f0fba2ad 1951static int __init wm8903_modinit(void)
f1c0a02f 1952{
f1c0a02f 1953 int ret = 0;
f0fba2ad
LG		 1954#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1955 ret = i2c_add_driver(&wm8903_i2c_driver);
1956 if (ret != 0) {
1957 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1958 ret);
f1c0a02f 1959 }
f0fba2ad 1960#endif
f1c0a02f 1961 return ret;
64089b84
MB		 1962}
1963module_init(wm8903_modinit);
1964
1965static void __exit wm8903_exit(void)
1966{
f0fba2ad 1967#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1968 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1969#endif
64089b84
MB		 1970}
1971module_exit(wm8903_exit);
1972
f1c0a02f
MB		 1973MODULE_DESCRIPTION("ASoC WM8903 driver");
1974MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1975MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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