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1 | /* |
2 | * wm8904.c -- WM8904 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/regulator/consumer.h> | |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/soc-dapm.h> | |
27 | #include <sound/initval.h> | |
28 | #include <sound/tlv.h> | |
29 | #include <sound/wm8904.h> | |
30 | ||
31 | #include "wm8904.h" | |
32 | ||
33 | static struct snd_soc_codec *wm8904_codec; | |
34 | struct snd_soc_codec_device soc_codec_dev_wm8904; | |
35 | ||
8c126474 MB |
36 | enum wm8904_type { |
37 | WM8904, | |
38 | WM8912, | |
39 | }; | |
40 | ||
a91eb199 MB |
41 | #define WM8904_NUM_DCS_CHANNELS 4 |
42 | ||
43 | #define WM8904_NUM_SUPPLIES 5 | |
44 | static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { | |
45 | "DCVDD", | |
46 | "DBVDD", | |
47 | "AVDD", | |
48 | "CPVDD", | |
49 | "MICVDD", | |
50 | }; | |
51 | ||
52 | /* codec private data */ | |
53 | struct wm8904_priv { | |
54 | struct snd_soc_codec codec; | |
55 | u16 reg_cache[WM8904_MAX_REGISTER + 1]; | |
56 | ||
8c126474 MB |
57 | enum wm8904_type devtype; |
58 | ||
a91eb199 MB |
59 | struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; |
60 | ||
61 | struct wm8904_pdata *pdata; | |
62 | ||
63 | int deemph; | |
64 | ||
65 | /* Platform provided DRC configuration */ | |
66 | const char **drc_texts; | |
67 | int drc_cfg; | |
68 | struct soc_enum drc_enum; | |
69 | ||
70 | /* Platform provided ReTune mobile configuration */ | |
71 | int num_retune_mobile_texts; | |
72 | const char **retune_mobile_texts; | |
73 | int retune_mobile_cfg; | |
74 | struct soc_enum retune_mobile_enum; | |
75 | ||
76 | /* FLL setup */ | |
77 | int fll_src; | |
78 | int fll_fref; | |
79 | int fll_fout; | |
80 | ||
81 | /* Clocking configuration */ | |
82 | unsigned int mclk_rate; | |
83 | int sysclk_src; | |
84 | unsigned int sysclk_rate; | |
85 | ||
86 | int tdm_width; | |
87 | int tdm_slots; | |
88 | int bclk; | |
89 | int fs; | |
90 | ||
91 | /* DC servo configuration - cached offset values */ | |
92 | int dcs_state[WM8904_NUM_DCS_CHANNELS]; | |
93 | }; | |
94 | ||
95 | static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = { | |
96 | 0x8904, /* R0 - SW Reset and ID */ | |
97 | 0x0000, /* R1 - Revision */ | |
98 | 0x0000, /* R2 */ | |
99 | 0x0000, /* R3 */ | |
100 | 0x0018, /* R4 - Bias Control 0 */ | |
101 | 0x0000, /* R5 - VMID Control 0 */ | |
102 | 0x0000, /* R6 - Mic Bias Control 0 */ | |
103 | 0x0000, /* R7 - Mic Bias Control 1 */ | |
104 | 0x0001, /* R8 - Analogue DAC 0 */ | |
105 | 0x9696, /* R9 - mic Filter Control */ | |
106 | 0x0001, /* R10 - Analogue ADC 0 */ | |
107 | 0x0000, /* R11 */ | |
108 | 0x0000, /* R12 - Power Management 0 */ | |
109 | 0x0000, /* R13 */ | |
110 | 0x0000, /* R14 - Power Management 2 */ | |
111 | 0x0000, /* R15 - Power Management 3 */ | |
112 | 0x0000, /* R16 */ | |
113 | 0x0000, /* R17 */ | |
114 | 0x0000, /* R18 - Power Management 6 */ | |
115 | 0x0000, /* R19 */ | |
116 | 0x945E, /* R20 - Clock Rates 0 */ | |
117 | 0x0C05, /* R21 - Clock Rates 1 */ | |
118 | 0x0006, /* R22 - Clock Rates 2 */ | |
119 | 0x0000, /* R23 */ | |
120 | 0x0050, /* R24 - Audio Interface 0 */ | |
121 | 0x000A, /* R25 - Audio Interface 1 */ | |
122 | 0x00E4, /* R26 - Audio Interface 2 */ | |
123 | 0x0040, /* R27 - Audio Interface 3 */ | |
124 | 0x0000, /* R28 */ | |
125 | 0x0000, /* R29 */ | |
126 | 0x00C0, /* R30 - DAC Digital Volume Left */ | |
127 | 0x00C0, /* R31 - DAC Digital Volume Right */ | |
128 | 0x0000, /* R32 - DAC Digital 0 */ | |
129 | 0x0008, /* R33 - DAC Digital 1 */ | |
130 | 0x0000, /* R34 */ | |
131 | 0x0000, /* R35 */ | |
132 | 0x00C0, /* R36 - ADC Digital Volume Left */ | |
133 | 0x00C0, /* R37 - ADC Digital Volume Right */ | |
134 | 0x0010, /* R38 - ADC Digital 0 */ | |
135 | 0x0000, /* R39 - Digital Microphone 0 */ | |
136 | 0x01AF, /* R40 - DRC 0 */ | |
137 | 0x3248, /* R41 - DRC 1 */ | |
138 | 0x0000, /* R42 - DRC 2 */ | |
139 | 0x0000, /* R43 - DRC 3 */ | |
140 | 0x0085, /* R44 - Analogue Left Input 0 */ | |
141 | 0x0085, /* R45 - Analogue Right Input 0 */ | |
142 | 0x0044, /* R46 - Analogue Left Input 1 */ | |
143 | 0x0044, /* R47 - Analogue Right Input 1 */ | |
144 | 0x0000, /* R48 */ | |
145 | 0x0000, /* R49 */ | |
146 | 0x0000, /* R50 */ | |
147 | 0x0000, /* R51 */ | |
148 | 0x0000, /* R52 */ | |
149 | 0x0000, /* R53 */ | |
150 | 0x0000, /* R54 */ | |
151 | 0x0000, /* R55 */ | |
152 | 0x0000, /* R56 */ | |
153 | 0x002D, /* R57 - Analogue OUT1 Left */ | |
154 | 0x002D, /* R58 - Analogue OUT1 Right */ | |
155 | 0x0039, /* R59 - Analogue OUT2 Left */ | |
156 | 0x0039, /* R60 - Analogue OUT2 Right */ | |
157 | 0x0000, /* R61 - Analogue OUT12 ZC */ | |
158 | 0x0000, /* R62 */ | |
159 | 0x0000, /* R63 */ | |
160 | 0x0000, /* R64 */ | |
161 | 0x0000, /* R65 */ | |
162 | 0x0000, /* R66 */ | |
163 | 0x0000, /* R67 - DC Servo 0 */ | |
164 | 0x0000, /* R68 - DC Servo 1 */ | |
165 | 0xAAAA, /* R69 - DC Servo 2 */ | |
166 | 0x0000, /* R70 */ | |
167 | 0xAAAA, /* R71 - DC Servo 4 */ | |
168 | 0xAAAA, /* R72 - DC Servo 5 */ | |
169 | 0x0000, /* R73 - DC Servo 6 */ | |
170 | 0x0000, /* R74 - DC Servo 7 */ | |
171 | 0x0000, /* R75 - DC Servo 8 */ | |
172 | 0x0000, /* R76 - DC Servo 9 */ | |
173 | 0x0000, /* R77 - DC Servo Readback 0 */ | |
174 | 0x0000, /* R78 */ | |
175 | 0x0000, /* R79 */ | |
176 | 0x0000, /* R80 */ | |
177 | 0x0000, /* R81 */ | |
178 | 0x0000, /* R82 */ | |
179 | 0x0000, /* R83 */ | |
180 | 0x0000, /* R84 */ | |
181 | 0x0000, /* R85 */ | |
182 | 0x0000, /* R86 */ | |
183 | 0x0000, /* R87 */ | |
184 | 0x0000, /* R88 */ | |
185 | 0x0000, /* R89 */ | |
186 | 0x0000, /* R90 - Analogue HP 0 */ | |
187 | 0x0000, /* R91 */ | |
188 | 0x0000, /* R92 */ | |
189 | 0x0000, /* R93 */ | |
190 | 0x0000, /* R94 - Analogue Lineout 0 */ | |
191 | 0x0000, /* R95 */ | |
192 | 0x0000, /* R96 */ | |
193 | 0x0000, /* R97 */ | |
194 | 0x0000, /* R98 - Charge Pump 0 */ | |
195 | 0x0000, /* R99 */ | |
196 | 0x0000, /* R100 */ | |
197 | 0x0000, /* R101 */ | |
198 | 0x0000, /* R102 */ | |
199 | 0x0000, /* R103 */ | |
200 | 0x0004, /* R104 - Class W 0 */ | |
201 | 0x0000, /* R105 */ | |
202 | 0x0000, /* R106 */ | |
203 | 0x0000, /* R107 */ | |
204 | 0x0000, /* R108 - Write Sequencer 0 */ | |
205 | 0x0000, /* R109 - Write Sequencer 1 */ | |
206 | 0x0000, /* R110 - Write Sequencer 2 */ | |
207 | 0x0000, /* R111 - Write Sequencer 3 */ | |
208 | 0x0000, /* R112 - Write Sequencer 4 */ | |
209 | 0x0000, /* R113 */ | |
210 | 0x0000, /* R114 */ | |
211 | 0x0000, /* R115 */ | |
212 | 0x0000, /* R116 - FLL Control 1 */ | |
213 | 0x0007, /* R117 - FLL Control 2 */ | |
214 | 0x0000, /* R118 - FLL Control 3 */ | |
215 | 0x2EE0, /* R119 - FLL Control 4 */ | |
216 | 0x0004, /* R120 - FLL Control 5 */ | |
217 | 0x0014, /* R121 - GPIO Control 1 */ | |
218 | 0x0010, /* R122 - GPIO Control 2 */ | |
219 | 0x0010, /* R123 - GPIO Control 3 */ | |
220 | 0x0000, /* R124 - GPIO Control 4 */ | |
221 | 0x0000, /* R125 */ | |
222 | 0x0000, /* R126 - Digital Pulls */ | |
223 | 0x0000, /* R127 - Interrupt Status */ | |
224 | 0xFFFF, /* R128 - Interrupt Status Mask */ | |
225 | 0x0000, /* R129 - Interrupt Polarity */ | |
226 | 0x0000, /* R130 - Interrupt Debounce */ | |
227 | 0x0000, /* R131 */ | |
228 | 0x0000, /* R132 */ | |
229 | 0x0000, /* R133 */ | |
230 | 0x0000, /* R134 - EQ1 */ | |
231 | 0x000C, /* R135 - EQ2 */ | |
232 | 0x000C, /* R136 - EQ3 */ | |
233 | 0x000C, /* R137 - EQ4 */ | |
234 | 0x000C, /* R138 - EQ5 */ | |
235 | 0x000C, /* R139 - EQ6 */ | |
236 | 0x0FCA, /* R140 - EQ7 */ | |
237 | 0x0400, /* R141 - EQ8 */ | |
238 | 0x00D8, /* R142 - EQ9 */ | |
239 | 0x1EB5, /* R143 - EQ10 */ | |
240 | 0xF145, /* R144 - EQ11 */ | |
241 | 0x0B75, /* R145 - EQ12 */ | |
242 | 0x01C5, /* R146 - EQ13 */ | |
243 | 0x1C58, /* R147 - EQ14 */ | |
244 | 0xF373, /* R148 - EQ15 */ | |
245 | 0x0A54, /* R149 - EQ16 */ | |
246 | 0x0558, /* R150 - EQ17 */ | |
247 | 0x168E, /* R151 - EQ18 */ | |
248 | 0xF829, /* R152 - EQ19 */ | |
249 | 0x07AD, /* R153 - EQ20 */ | |
250 | 0x1103, /* R154 - EQ21 */ | |
251 | 0x0564, /* R155 - EQ22 */ | |
252 | 0x0559, /* R156 - EQ23 */ | |
253 | 0x4000, /* R157 - EQ24 */ | |
254 | 0x0000, /* R158 */ | |
255 | 0x0000, /* R159 */ | |
256 | 0x0000, /* R160 */ | |
257 | 0x0000, /* R161 - Control Interface Test 1 */ | |
258 | 0x0000, /* R162 */ | |
259 | 0x0000, /* R163 */ | |
260 | 0x0000, /* R164 */ | |
261 | 0x0000, /* R165 */ | |
262 | 0x0000, /* R166 */ | |
263 | 0x0000, /* R167 */ | |
264 | 0x0000, /* R168 */ | |
265 | 0x0000, /* R169 */ | |
266 | 0x0000, /* R170 */ | |
267 | 0x0000, /* R171 */ | |
268 | 0x0000, /* R172 */ | |
269 | 0x0000, /* R173 */ | |
270 | 0x0000, /* R174 */ | |
271 | 0x0000, /* R175 */ | |
272 | 0x0000, /* R176 */ | |
273 | 0x0000, /* R177 */ | |
274 | 0x0000, /* R178 */ | |
275 | 0x0000, /* R179 */ | |
276 | 0x0000, /* R180 */ | |
277 | 0x0000, /* R181 */ | |
278 | 0x0000, /* R182 */ | |
279 | 0x0000, /* R183 */ | |
280 | 0x0000, /* R184 */ | |
281 | 0x0000, /* R185 */ | |
282 | 0x0000, /* R186 */ | |
283 | 0x0000, /* R187 */ | |
284 | 0x0000, /* R188 */ | |
285 | 0x0000, /* R189 */ | |
286 | 0x0000, /* R190 */ | |
287 | 0x0000, /* R191 */ | |
288 | 0x0000, /* R192 */ | |
289 | 0x0000, /* R193 */ | |
290 | 0x0000, /* R194 */ | |
291 | 0x0000, /* R195 */ | |
292 | 0x0000, /* R196 */ | |
293 | 0x0000, /* R197 */ | |
294 | 0x0000, /* R198 */ | |
295 | 0x0000, /* R199 */ | |
296 | 0x0000, /* R200 */ | |
297 | 0x0000, /* R201 */ | |
298 | 0x0000, /* R202 */ | |
299 | 0x0000, /* R203 */ | |
300 | 0x0000, /* R204 - Analogue Output Bias 0 */ | |
301 | 0x0000, /* R205 */ | |
302 | 0x0000, /* R206 */ | |
303 | 0x0000, /* R207 */ | |
304 | 0x0000, /* R208 */ | |
305 | 0x0000, /* R209 */ | |
306 | 0x0000, /* R210 */ | |
307 | 0x0000, /* R211 */ | |
308 | 0x0000, /* R212 */ | |
309 | 0x0000, /* R213 */ | |
310 | 0x0000, /* R214 */ | |
311 | 0x0000, /* R215 */ | |
312 | 0x0000, /* R216 */ | |
313 | 0x0000, /* R217 */ | |
314 | 0x0000, /* R218 */ | |
315 | 0x0000, /* R219 */ | |
316 | 0x0000, /* R220 */ | |
317 | 0x0000, /* R221 */ | |
318 | 0x0000, /* R222 */ | |
319 | 0x0000, /* R223 */ | |
320 | 0x0000, /* R224 */ | |
321 | 0x0000, /* R225 */ | |
322 | 0x0000, /* R226 */ | |
323 | 0x0000, /* R227 */ | |
324 | 0x0000, /* R228 */ | |
325 | 0x0000, /* R229 */ | |
326 | 0x0000, /* R230 */ | |
327 | 0x0000, /* R231 */ | |
328 | 0x0000, /* R232 */ | |
329 | 0x0000, /* R233 */ | |
330 | 0x0000, /* R234 */ | |
331 | 0x0000, /* R235 */ | |
332 | 0x0000, /* R236 */ | |
333 | 0x0000, /* R237 */ | |
334 | 0x0000, /* R238 */ | |
335 | 0x0000, /* R239 */ | |
336 | 0x0000, /* R240 */ | |
337 | 0x0000, /* R241 */ | |
338 | 0x0000, /* R242 */ | |
339 | 0x0000, /* R243 */ | |
340 | 0x0000, /* R244 */ | |
341 | 0x0000, /* R245 */ | |
342 | 0x0000, /* R246 */ | |
343 | 0x0000, /* R247 - FLL NCO Test 0 */ | |
344 | 0x0019, /* R248 - FLL NCO Test 1 */ | |
345 | }; | |
346 | ||
347 | static struct { | |
348 | int readable; | |
349 | int writable; | |
350 | int vol; | |
351 | } wm8904_access[] = { | |
352 | { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */ | |
353 | { 0x0000, 0x0000, 0 }, /* R1 - Revision */ | |
354 | { 0x0000, 0x0000, 0 }, /* R2 */ | |
355 | { 0x0000, 0x0000, 0 }, /* R3 */ | |
356 | { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */ | |
357 | { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */ | |
358 | { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */ | |
359 | { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */ | |
360 | { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */ | |
361 | { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */ | |
362 | { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */ | |
363 | { 0x0000, 0x0000, 0 }, /* R11 */ | |
364 | { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */ | |
365 | { 0x0000, 0x0000, 0 }, /* R13 */ | |
366 | { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */ | |
367 | { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */ | |
368 | { 0x0000, 0x0000, 0 }, /* R16 */ | |
369 | { 0x0000, 0x0000, 0 }, /* R17 */ | |
370 | { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */ | |
371 | { 0x0000, 0x0000, 0 }, /* R19 */ | |
372 | { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */ | |
373 | { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */ | |
374 | { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */ | |
375 | { 0x0000, 0x0000, 0 }, /* R23 */ | |
376 | { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */ | |
377 | { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */ | |
378 | { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */ | |
379 | { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */ | |
380 | { 0x0000, 0x0000, 0 }, /* R28 */ | |
381 | { 0x0000, 0x0000, 0 }, /* R29 */ | |
382 | { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */ | |
383 | { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */ | |
384 | { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */ | |
385 | { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */ | |
386 | { 0x0000, 0x0000, 0 }, /* R34 */ | |
387 | { 0x0000, 0x0000, 0 }, /* R35 */ | |
388 | { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */ | |
389 | { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */ | |
390 | { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */ | |
391 | { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */ | |
392 | { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */ | |
393 | { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */ | |
394 | { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */ | |
395 | { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */ | |
396 | { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */ | |
397 | { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */ | |
398 | { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */ | |
399 | { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */ | |
400 | { 0x0000, 0x0000, 0 }, /* R48 */ | |
401 | { 0x0000, 0x0000, 0 }, /* R49 */ | |
402 | { 0x0000, 0x0000, 0 }, /* R50 */ | |
403 | { 0x0000, 0x0000, 0 }, /* R51 */ | |
404 | { 0x0000, 0x0000, 0 }, /* R52 */ | |
405 | { 0x0000, 0x0000, 0 }, /* R53 */ | |
406 | { 0x0000, 0x0000, 0 }, /* R54 */ | |
407 | { 0x0000, 0x0000, 0 }, /* R55 */ | |
408 | { 0x0000, 0x0000, 0 }, /* R56 */ | |
409 | { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */ | |
410 | { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */ | |
411 | { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */ | |
412 | { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */ | |
413 | { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */ | |
414 | { 0x0000, 0x0000, 0 }, /* R62 */ | |
415 | { 0x0000, 0x0000, 0 }, /* R63 */ | |
416 | { 0x0000, 0x0000, 0 }, /* R64 */ | |
417 | { 0x0000, 0x0000, 0 }, /* R65 */ | |
418 | { 0x0000, 0x0000, 0 }, /* R66 */ | |
419 | { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */ | |
420 | { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */ | |
421 | { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */ | |
422 | { 0x0000, 0x0000, 0 }, /* R70 */ | |
423 | { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */ | |
424 | { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */ | |
425 | { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */ | |
426 | { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */ | |
427 | { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */ | |
428 | { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */ | |
429 | { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */ | |
430 | { 0x0000, 0x0000, 0 }, /* R78 */ | |
431 | { 0x0000, 0x0000, 0 }, /* R79 */ | |
432 | { 0x0000, 0x0000, 0 }, /* R80 */ | |
433 | { 0x0000, 0x0000, 0 }, /* R81 */ | |
434 | { 0x0000, 0x0000, 0 }, /* R82 */ | |
435 | { 0x0000, 0x0000, 0 }, /* R83 */ | |
436 | { 0x0000, 0x0000, 0 }, /* R84 */ | |
437 | { 0x0000, 0x0000, 0 }, /* R85 */ | |
438 | { 0x0000, 0x0000, 0 }, /* R86 */ | |
439 | { 0x0000, 0x0000, 0 }, /* R87 */ | |
440 | { 0x0000, 0x0000, 0 }, /* R88 */ | |
441 | { 0x0000, 0x0000, 0 }, /* R89 */ | |
442 | { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */ | |
443 | { 0x0000, 0x0000, 0 }, /* R91 */ | |
444 | { 0x0000, 0x0000, 0 }, /* R92 */ | |
445 | { 0x0000, 0x0000, 0 }, /* R93 */ | |
446 | { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */ | |
447 | { 0x0000, 0x0000, 0 }, /* R95 */ | |
448 | { 0x0000, 0x0000, 0 }, /* R96 */ | |
449 | { 0x0000, 0x0000, 0 }, /* R97 */ | |
450 | { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */ | |
451 | { 0x0000, 0x0000, 0 }, /* R99 */ | |
452 | { 0x0000, 0x0000, 0 }, /* R100 */ | |
453 | { 0x0000, 0x0000, 0 }, /* R101 */ | |
454 | { 0x0000, 0x0000, 0 }, /* R102 */ | |
455 | { 0x0000, 0x0000, 0 }, /* R103 */ | |
456 | { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */ | |
457 | { 0x0000, 0x0000, 0 }, /* R105 */ | |
458 | { 0x0000, 0x0000, 0 }, /* R106 */ | |
459 | { 0x0000, 0x0000, 0 }, /* R107 */ | |
460 | { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */ | |
461 | { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */ | |
462 | { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */ | |
463 | { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */ | |
464 | { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */ | |
465 | { 0x0000, 0x0000, 0 }, /* R113 */ | |
466 | { 0x0000, 0x0000, 0 }, /* R114 */ | |
467 | { 0x0000, 0x0000, 0 }, /* R115 */ | |
468 | { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */ | |
469 | { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */ | |
470 | { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */ | |
471 | { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */ | |
472 | { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */ | |
473 | { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */ | |
474 | { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */ | |
475 | { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */ | |
476 | { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */ | |
477 | { 0x0000, 0x0000, 0 }, /* R125 */ | |
478 | { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */ | |
479 | { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */ | |
480 | { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */ | |
481 | { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */ | |
482 | { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */ | |
483 | { 0x0000, 0x0000, 0 }, /* R131 */ | |
484 | { 0x0000, 0x0000, 0 }, /* R132 */ | |
485 | { 0x0000, 0x0000, 0 }, /* R133 */ | |
486 | { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */ | |
487 | { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */ | |
488 | { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */ | |
489 | { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */ | |
490 | { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */ | |
491 | { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */ | |
492 | { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */ | |
493 | { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */ | |
494 | { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */ | |
495 | { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */ | |
496 | { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */ | |
497 | { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */ | |
498 | { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */ | |
499 | { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */ | |
500 | { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */ | |
501 | { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */ | |
502 | { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */ | |
503 | { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */ | |
504 | { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */ | |
505 | { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */ | |
506 | { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */ | |
507 | { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */ | |
508 | { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */ | |
509 | { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */ | |
510 | { 0x0000, 0x0000, 0 }, /* R158 */ | |
511 | { 0x0000, 0x0000, 0 }, /* R159 */ | |
512 | { 0x0000, 0x0000, 0 }, /* R160 */ | |
513 | { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */ | |
514 | { 0x0000, 0x0000, 0 }, /* R162 */ | |
515 | { 0x0000, 0x0000, 0 }, /* R163 */ | |
516 | { 0x0000, 0x0000, 0 }, /* R164 */ | |
517 | { 0x0000, 0x0000, 0 }, /* R165 */ | |
518 | { 0x0000, 0x0000, 0 }, /* R166 */ | |
519 | { 0x0000, 0x0000, 0 }, /* R167 */ | |
520 | { 0x0000, 0x0000, 0 }, /* R168 */ | |
521 | { 0x0000, 0x0000, 0 }, /* R169 */ | |
522 | { 0x0000, 0x0000, 0 }, /* R170 */ | |
523 | { 0x0000, 0x0000, 0 }, /* R171 */ | |
524 | { 0x0000, 0x0000, 0 }, /* R172 */ | |
525 | { 0x0000, 0x0000, 0 }, /* R173 */ | |
526 | { 0x0000, 0x0000, 0 }, /* R174 */ | |
527 | { 0x0000, 0x0000, 0 }, /* R175 */ | |
528 | { 0x0000, 0x0000, 0 }, /* R176 */ | |
529 | { 0x0000, 0x0000, 0 }, /* R177 */ | |
530 | { 0x0000, 0x0000, 0 }, /* R178 */ | |
531 | { 0x0000, 0x0000, 0 }, /* R179 */ | |
532 | { 0x0000, 0x0000, 0 }, /* R180 */ | |
533 | { 0x0000, 0x0000, 0 }, /* R181 */ | |
534 | { 0x0000, 0x0000, 0 }, /* R182 */ | |
535 | { 0x0000, 0x0000, 0 }, /* R183 */ | |
536 | { 0x0000, 0x0000, 0 }, /* R184 */ | |
537 | { 0x0000, 0x0000, 0 }, /* R185 */ | |
538 | { 0x0000, 0x0000, 0 }, /* R186 */ | |
539 | { 0x0000, 0x0000, 0 }, /* R187 */ | |
540 | { 0x0000, 0x0000, 0 }, /* R188 */ | |
541 | { 0x0000, 0x0000, 0 }, /* R189 */ | |
542 | { 0x0000, 0x0000, 0 }, /* R190 */ | |
543 | { 0x0000, 0x0000, 0 }, /* R191 */ | |
544 | { 0x0000, 0x0000, 0 }, /* R192 */ | |
545 | { 0x0000, 0x0000, 0 }, /* R193 */ | |
546 | { 0x0000, 0x0000, 0 }, /* R194 */ | |
547 | { 0x0000, 0x0000, 0 }, /* R195 */ | |
548 | { 0x0000, 0x0000, 0 }, /* R196 */ | |
549 | { 0x0000, 0x0000, 0 }, /* R197 */ | |
550 | { 0x0000, 0x0000, 0 }, /* R198 */ | |
551 | { 0x0000, 0x0000, 0 }, /* R199 */ | |
552 | { 0x0000, 0x0000, 0 }, /* R200 */ | |
553 | { 0x0000, 0x0000, 0 }, /* R201 */ | |
554 | { 0x0000, 0x0000, 0 }, /* R202 */ | |
555 | { 0x0000, 0x0000, 0 }, /* R203 */ | |
556 | { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */ | |
557 | { 0x0000, 0x0000, 0 }, /* R205 */ | |
558 | { 0x0000, 0x0000, 0 }, /* R206 */ | |
559 | { 0x0000, 0x0000, 0 }, /* R207 */ | |
560 | { 0x0000, 0x0000, 0 }, /* R208 */ | |
561 | { 0x0000, 0x0000, 0 }, /* R209 */ | |
562 | { 0x0000, 0x0000, 0 }, /* R210 */ | |
563 | { 0x0000, 0x0000, 0 }, /* R211 */ | |
564 | { 0x0000, 0x0000, 0 }, /* R212 */ | |
565 | { 0x0000, 0x0000, 0 }, /* R213 */ | |
566 | { 0x0000, 0x0000, 0 }, /* R214 */ | |
567 | { 0x0000, 0x0000, 0 }, /* R215 */ | |
568 | { 0x0000, 0x0000, 0 }, /* R216 */ | |
569 | { 0x0000, 0x0000, 0 }, /* R217 */ | |
570 | { 0x0000, 0x0000, 0 }, /* R218 */ | |
571 | { 0x0000, 0x0000, 0 }, /* R219 */ | |
572 | { 0x0000, 0x0000, 0 }, /* R220 */ | |
573 | { 0x0000, 0x0000, 0 }, /* R221 */ | |
574 | { 0x0000, 0x0000, 0 }, /* R222 */ | |
575 | { 0x0000, 0x0000, 0 }, /* R223 */ | |
576 | { 0x0000, 0x0000, 0 }, /* R224 */ | |
577 | { 0x0000, 0x0000, 0 }, /* R225 */ | |
578 | { 0x0000, 0x0000, 0 }, /* R226 */ | |
579 | { 0x0000, 0x0000, 0 }, /* R227 */ | |
580 | { 0x0000, 0x0000, 0 }, /* R228 */ | |
581 | { 0x0000, 0x0000, 0 }, /* R229 */ | |
582 | { 0x0000, 0x0000, 0 }, /* R230 */ | |
583 | { 0x0000, 0x0000, 0 }, /* R231 */ | |
584 | { 0x0000, 0x0000, 0 }, /* R232 */ | |
585 | { 0x0000, 0x0000, 0 }, /* R233 */ | |
586 | { 0x0000, 0x0000, 0 }, /* R234 */ | |
587 | { 0x0000, 0x0000, 0 }, /* R235 */ | |
588 | { 0x0000, 0x0000, 0 }, /* R236 */ | |
589 | { 0x0000, 0x0000, 0 }, /* R237 */ | |
590 | { 0x0000, 0x0000, 0 }, /* R238 */ | |
591 | { 0x0000, 0x0000, 0 }, /* R239 */ | |
592 | { 0x0000, 0x0000, 0 }, /* R240 */ | |
593 | { 0x0000, 0x0000, 0 }, /* R241 */ | |
594 | { 0x0000, 0x0000, 0 }, /* R242 */ | |
595 | { 0x0000, 0x0000, 0 }, /* R243 */ | |
596 | { 0x0000, 0x0000, 0 }, /* R244 */ | |
597 | { 0x0000, 0x0000, 0 }, /* R245 */ | |
598 | { 0x0000, 0x0000, 0 }, /* R246 */ | |
599 | { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */ | |
600 | { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */ | |
601 | }; | |
602 | ||
603 | static int wm8904_volatile_register(unsigned int reg) | |
604 | { | |
605 | return wm8904_access[reg].vol; | |
606 | } | |
607 | ||
608 | static int wm8904_reset(struct snd_soc_codec *codec) | |
609 | { | |
610 | return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0); | |
611 | } | |
612 | ||
613 | static int wm8904_configure_clocking(struct snd_soc_codec *codec) | |
614 | { | |
615 | struct wm8904_priv *wm8904 = codec->private_data; | |
616 | unsigned int clock0, clock2, rate; | |
617 | ||
618 | /* Gate the clock while we're updating to avoid misclocking */ | |
619 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); | |
620 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
621 | WM8904_SYSCLK_SRC, 0); | |
622 | ||
623 | /* This should be done on init() for bypass paths */ | |
624 | switch (wm8904->sysclk_src) { | |
625 | case WM8904_CLK_MCLK: | |
626 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); | |
627 | ||
628 | clock2 &= ~WM8904_SYSCLK_SRC; | |
629 | rate = wm8904->mclk_rate; | |
630 | ||
631 | /* Ensure the FLL is stopped */ | |
632 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
633 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
634 | break; | |
635 | ||
636 | case WM8904_CLK_FLL: | |
637 | dev_dbg(codec->dev, "Using %dHz FLL clock\n", | |
638 | wm8904->fll_fout); | |
639 | ||
640 | clock2 |= WM8904_SYSCLK_SRC; | |
641 | rate = wm8904->fll_fout; | |
642 | break; | |
643 | ||
644 | default: | |
645 | dev_err(codec->dev, "System clock not configured\n"); | |
646 | return -EINVAL; | |
647 | } | |
648 | ||
649 | /* SYSCLK shouldn't be over 13.5MHz */ | |
650 | if (rate > 13500000) { | |
651 | clock0 = WM8904_MCLK_DIV; | |
652 | wm8904->sysclk_rate = rate / 2; | |
653 | } else { | |
654 | clock0 = 0; | |
655 | wm8904->sysclk_rate = rate; | |
656 | } | |
657 | ||
658 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, | |
659 | clock0); | |
660 | ||
661 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
662 | WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); | |
663 | ||
664 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); | |
665 | ||
666 | return 0; | |
667 | } | |
668 | ||
669 | static void wm8904_set_drc(struct snd_soc_codec *codec) | |
670 | { | |
671 | struct wm8904_priv *wm8904 = codec->private_data; | |
672 | struct wm8904_pdata *pdata = wm8904->pdata; | |
673 | int save, i; | |
674 | ||
675 | /* Save any enables; the configuration should clear them. */ | |
676 | save = snd_soc_read(codec, WM8904_DRC_0); | |
677 | ||
678 | for (i = 0; i < WM8904_DRC_REGS; i++) | |
679 | snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, | |
680 | pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); | |
681 | ||
682 | /* Reenable the DRC */ | |
683 | snd_soc_update_bits(codec, WM8904_DRC_0, | |
684 | WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); | |
685 | } | |
686 | ||
687 | static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, | |
688 | struct snd_ctl_elem_value *ucontrol) | |
689 | { | |
690 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
691 | struct wm8904_priv *wm8904 = codec->private_data; | |
692 | struct wm8904_pdata *pdata = wm8904->pdata; | |
693 | int value = ucontrol->value.integer.value[0]; | |
694 | ||
695 | if (value >= pdata->num_drc_cfgs) | |
696 | return -EINVAL; | |
697 | ||
698 | wm8904->drc_cfg = value; | |
699 | ||
700 | wm8904_set_drc(codec); | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, | |
706 | struct snd_ctl_elem_value *ucontrol) | |
707 | { | |
708 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
709 | struct wm8904_priv *wm8904 = codec->private_data; | |
710 | ||
711 | ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; | |
712 | ||
713 | return 0; | |
714 | } | |
715 | ||
716 | static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) | |
717 | { | |
718 | struct wm8904_priv *wm8904 = codec->private_data; | |
719 | struct wm8904_pdata *pdata = wm8904->pdata; | |
720 | int best, best_val, save, i, cfg; | |
721 | ||
722 | if (!pdata || !wm8904->num_retune_mobile_texts) | |
723 | return; | |
724 | ||
725 | /* Find the version of the currently selected configuration | |
726 | * with the nearest sample rate. */ | |
727 | cfg = wm8904->retune_mobile_cfg; | |
728 | best = 0; | |
729 | best_val = INT_MAX; | |
730 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
731 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
732 | wm8904->retune_mobile_texts[cfg]) == 0 && | |
733 | abs(pdata->retune_mobile_cfgs[i].rate | |
734 | - wm8904->fs) < best_val) { | |
735 | best = i; | |
736 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
737 | - wm8904->fs); | |
738 | } | |
739 | } | |
740 | ||
741 | dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", | |
742 | pdata->retune_mobile_cfgs[best].name, | |
743 | pdata->retune_mobile_cfgs[best].rate, | |
744 | wm8904->fs); | |
745 | ||
746 | /* The EQ will be disabled while reconfiguring it, remember the | |
747 | * current configuration. | |
748 | */ | |
749 | save = snd_soc_read(codec, WM8904_EQ1); | |
750 | ||
751 | for (i = 0; i < WM8904_EQ_REGS; i++) | |
752 | snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, | |
753 | pdata->retune_mobile_cfgs[best].regs[i]); | |
754 | ||
755 | snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); | |
756 | } | |
757 | ||
758 | static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
759 | struct snd_ctl_elem_value *ucontrol) | |
760 | { | |
761 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
762 | struct wm8904_priv *wm8904 = codec->private_data; | |
763 | struct wm8904_pdata *pdata = wm8904->pdata; | |
764 | int value = ucontrol->value.integer.value[0]; | |
765 | ||
766 | if (value >= pdata->num_retune_mobile_cfgs) | |
767 | return -EINVAL; | |
768 | ||
769 | wm8904->retune_mobile_cfg = value; | |
770 | ||
771 | wm8904_set_retune_mobile(codec); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
776 | static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
777 | struct snd_ctl_elem_value *ucontrol) | |
778 | { | |
779 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
780 | struct wm8904_priv *wm8904 = codec->private_data; | |
781 | ||
782 | ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; | |
783 | ||
784 | return 0; | |
785 | } | |
786 | ||
787 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
788 | ||
789 | static int wm8904_set_deemph(struct snd_soc_codec *codec) | |
790 | { | |
791 | struct wm8904_priv *wm8904 = codec->private_data; | |
792 | int val, i, best; | |
793 | ||
794 | /* If we're using deemphasis select the nearest available sample | |
795 | * rate. | |
796 | */ | |
797 | if (wm8904->deemph) { | |
798 | best = 1; | |
799 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
800 | if (abs(deemph_settings[i] - wm8904->fs) < | |
801 | abs(deemph_settings[best] - wm8904->fs)) | |
802 | best = i; | |
803 | } | |
804 | ||
805 | val = best << WM8904_DEEMPH_SHIFT; | |
806 | } else { | |
807 | val = 0; | |
808 | } | |
809 | ||
810 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
811 | ||
812 | return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
813 | WM8904_DEEMPH_MASK, val); | |
814 | } | |
815 | ||
816 | static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, | |
817 | struct snd_ctl_elem_value *ucontrol) | |
818 | { | |
819 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
820 | struct wm8904_priv *wm8904 = codec->private_data; | |
821 | ||
822 | return wm8904->deemph; | |
823 | } | |
824 | ||
825 | static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, | |
826 | struct snd_ctl_elem_value *ucontrol) | |
827 | { | |
828 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
829 | struct wm8904_priv *wm8904 = codec->private_data; | |
830 | int deemph = ucontrol->value.enumerated.item[0]; | |
831 | ||
832 | if (deemph > 1) | |
833 | return -EINVAL; | |
834 | ||
835 | wm8904->deemph = deemph; | |
836 | ||
837 | return wm8904_set_deemph(codec); | |
838 | } | |
839 | ||
840 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); | |
841 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
842 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
843 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); | |
844 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
845 | ||
846 | static const char *input_mode_text[] = { | |
847 | "Single-Ended", "Differential Line", "Differential Mic" | |
848 | }; | |
849 | ||
850 | static const struct soc_enum lin_mode = | |
851 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
852 | ||
853 | static const struct soc_enum rin_mode = | |
854 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
855 | ||
856 | static const char *hpf_mode_text[] = { | |
857 | "Hi-fi", "Voice 1", "Voice 2", "Voice 3" | |
858 | }; | |
859 | ||
860 | static const struct soc_enum hpf_mode = | |
861 | SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); | |
862 | ||
863 | static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { | |
864 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
865 | WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), | |
866 | ||
867 | SOC_ENUM("Left Caputure Mode", lin_mode), | |
868 | SOC_ENUM("Right Capture Mode", rin_mode), | |
869 | ||
870 | /* No TLV since it depends on mode */ | |
871 | SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, | |
872 | WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), | |
873 | SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, | |
874 | WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0), | |
875 | ||
876 | SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), | |
877 | SOC_ENUM("High Pass Filter Mode", hpf_mode), | |
878 | ||
879 | SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0), | |
880 | }; | |
881 | ||
882 | static const char *drc_path_text[] = { | |
883 | "ADC", "DAC" | |
884 | }; | |
885 | ||
886 | static const struct soc_enum drc_path = | |
887 | SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); | |
888 | ||
889 | static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { | |
890 | SOC_SINGLE_TLV("Digital Playback Boost Volume", | |
891 | WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), | |
892 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
893 | WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
894 | ||
895 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, | |
896 | WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), | |
897 | SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
898 | WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), | |
899 | SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
900 | WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), | |
901 | ||
902 | SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, | |
903 | WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), | |
904 | SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
905 | WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), | |
906 | SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
907 | WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), | |
908 | ||
909 | SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), | |
910 | SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), | |
911 | SOC_ENUM("DRC Path", drc_path), | |
912 | SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), | |
913 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
914 | wm8904_get_deemph, wm8904_put_deemph), | |
915 | }; | |
916 | ||
917 | static const struct snd_kcontrol_new wm8904_snd_controls[] = { | |
918 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, | |
919 | sidetone_tlv), | |
920 | }; | |
921 | ||
922 | static const struct snd_kcontrol_new wm8904_eq_controls[] = { | |
923 | SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), | |
924 | SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), | |
925 | SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), | |
926 | SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), | |
927 | SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), | |
928 | }; | |
929 | ||
930 | static int cp_event(struct snd_soc_dapm_widget *w, | |
931 | struct snd_kcontrol *kcontrol, int event) | |
932 | { | |
933 | BUG_ON(event != SND_SOC_DAPM_POST_PMU); | |
934 | ||
935 | /* Maximum startup time */ | |
936 | udelay(500); | |
937 | ||
938 | return 0; | |
939 | } | |
940 | ||
941 | static int sysclk_event(struct snd_soc_dapm_widget *w, | |
942 | struct snd_kcontrol *kcontrol, int event) | |
943 | { | |
944 | struct snd_soc_codec *codec = w->codec; | |
945 | struct wm8904_priv *wm8904 = codec->private_data; | |
946 | ||
947 | switch (event) { | |
948 | case SND_SOC_DAPM_PRE_PMU: | |
949 | /* If we're using the FLL then we only start it when | |
950 | * required; we assume that the configuration has been | |
951 | * done previously and all we need to do is kick it | |
952 | * off. | |
953 | */ | |
954 | switch (wm8904->sysclk_src) { | |
955 | case WM8904_CLK_FLL: | |
956 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
957 | WM8904_FLL_OSC_ENA, | |
958 | WM8904_FLL_OSC_ENA); | |
959 | ||
960 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
961 | WM8904_FLL_ENA, | |
962 | WM8904_FLL_ENA); | |
963 | break; | |
964 | ||
965 | default: | |
966 | break; | |
967 | } | |
968 | break; | |
969 | ||
970 | case SND_SOC_DAPM_POST_PMD: | |
971 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
972 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
973 | break; | |
974 | } | |
975 | ||
976 | return 0; | |
977 | } | |
978 | ||
979 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
980 | struct snd_kcontrol *kcontrol, int event) | |
981 | { | |
982 | struct snd_soc_codec *codec = w->codec; | |
983 | struct wm8904_priv *wm8904 = codec->private_data; | |
984 | int reg, val; | |
985 | int dcs_mask; | |
986 | int dcs_l, dcs_r; | |
987 | int dcs_l_reg, dcs_r_reg; | |
988 | int timeout; | |
e4bc6696 | 989 | int pwr_reg; |
a91eb199 MB |
990 | |
991 | /* This code is shared between HP and LINEOUT; we do all our | |
992 | * power management in stereo pairs to avoid latency issues so | |
993 | * we reuse shift to identify which rather than strcmp() the | |
994 | * name. */ | |
995 | reg = w->shift; | |
996 | ||
997 | switch (reg) { | |
998 | case WM8904_ANALOGUE_HP_0: | |
e4bc6696 | 999 | pwr_reg = WM8904_POWER_MANAGEMENT_2; |
a91eb199 MB |
1000 | dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; |
1001 | dcs_r_reg = WM8904_DC_SERVO_8; | |
1002 | dcs_l_reg = WM8904_DC_SERVO_9; | |
1003 | dcs_l = 0; | |
1004 | dcs_r = 1; | |
1005 | break; | |
1006 | case WM8904_ANALOGUE_LINEOUT_0: | |
e4bc6696 | 1007 | pwr_reg = WM8904_POWER_MANAGEMENT_3; |
a91eb199 MB |
1008 | dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; |
1009 | dcs_r_reg = WM8904_DC_SERVO_6; | |
1010 | dcs_l_reg = WM8904_DC_SERVO_7; | |
1011 | dcs_l = 2; | |
1012 | dcs_r = 3; | |
1013 | break; | |
1014 | default: | |
1015 | BUG(); | |
1016 | return -EINVAL; | |
1017 | } | |
1018 | ||
1019 | switch (event) { | |
e4bc6696 MB |
1020 | case SND_SOC_DAPM_PRE_PMU: |
1021 | /* Power on the PGAs */ | |
1022 | snd_soc_update_bits(codec, pwr_reg, | |
1023 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
1024 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); | |
1025 | ||
a91eb199 MB |
1026 | /* Power on the amplifier */ |
1027 | snd_soc_update_bits(codec, reg, | |
1028 | WM8904_HPL_ENA | WM8904_HPR_ENA, | |
1029 | WM8904_HPL_ENA | WM8904_HPR_ENA); | |
1030 | ||
e4bc6696 | 1031 | |
a91eb199 MB |
1032 | /* Enable the first stage */ |
1033 | snd_soc_update_bits(codec, reg, | |
1034 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, | |
1035 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); | |
1036 | ||
1037 | /* Power up the DC servo */ | |
1038 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
1039 | dcs_mask, dcs_mask); | |
1040 | ||
1041 | /* Either calibrate the DC servo or restore cached state | |
1042 | * if we have that. | |
1043 | */ | |
1044 | if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { | |
1045 | dev_dbg(codec->dev, "Restoring DC servo state\n"); | |
1046 | ||
1047 | snd_soc_write(codec, dcs_l_reg, | |
1048 | wm8904->dcs_state[dcs_l]); | |
1049 | snd_soc_write(codec, dcs_r_reg, | |
1050 | wm8904->dcs_state[dcs_r]); | |
1051 | ||
1052 | snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); | |
1053 | ||
1054 | timeout = 20; | |
1055 | } else { | |
1056 | dev_dbg(codec->dev, "Calibrating DC servo\n"); | |
1057 | ||
1058 | snd_soc_write(codec, WM8904_DC_SERVO_1, | |
1059 | dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); | |
1060 | ||
1061 | timeout = 500; | |
1062 | } | |
1063 | ||
1064 | /* Wait for DC servo to complete */ | |
1065 | dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; | |
1066 | do { | |
1067 | val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); | |
1068 | if ((val & dcs_mask) == dcs_mask) | |
1069 | break; | |
1070 | ||
1071 | msleep(1); | |
1072 | } while (--timeout); | |
1073 | ||
1074 | if ((val & dcs_mask) != dcs_mask) | |
1075 | dev_warn(codec->dev, "DC servo timed out\n"); | |
1076 | else | |
1077 | dev_dbg(codec->dev, "DC servo ready\n"); | |
1078 | ||
1079 | /* Enable the output stage */ | |
1080 | snd_soc_update_bits(codec, reg, | |
1081 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
1082 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); | |
e4bc6696 | 1083 | break; |
a91eb199 | 1084 | |
e4bc6696 | 1085 | case SND_SOC_DAPM_POST_PMU: |
a91eb199 MB |
1086 | /* Unshort the output itself */ |
1087 | snd_soc_update_bits(codec, reg, | |
1088 | WM8904_HPL_RMV_SHORT | | |
1089 | WM8904_HPR_RMV_SHORT, | |
1090 | WM8904_HPL_RMV_SHORT | | |
1091 | WM8904_HPR_RMV_SHORT); | |
1092 | ||
1093 | break; | |
1094 | ||
1095 | case SND_SOC_DAPM_PRE_PMD: | |
1096 | /* Short the output */ | |
1097 | snd_soc_update_bits(codec, reg, | |
1098 | WM8904_HPL_RMV_SHORT | | |
1099 | WM8904_HPR_RMV_SHORT, 0); | |
e4bc6696 | 1100 | break; |
a91eb199 | 1101 | |
e4bc6696 | 1102 | case SND_SOC_DAPM_POST_PMD: |
a91eb199 MB |
1103 | /* Cache the DC servo configuration; this will be |
1104 | * invalidated if we change the configuration. */ | |
1105 | wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); | |
1106 | wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); | |
1107 | ||
1108 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
1109 | dcs_mask, 0); | |
1110 | ||
1111 | /* Disable the amplifier input and output stages */ | |
1112 | snd_soc_update_bits(codec, reg, | |
1113 | WM8904_HPL_ENA | WM8904_HPR_ENA | | |
1114 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | | |
1115 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
1116 | 0); | |
e4bc6696 MB |
1117 | |
1118 | /* PGAs too */ | |
1119 | snd_soc_update_bits(codec, pwr_reg, | |
1120 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
1121 | 0); | |
a91eb199 MB |
1122 | break; |
1123 | } | |
1124 | ||
1125 | return 0; | |
1126 | } | |
1127 | ||
1128 | static const char *lin_text[] = { | |
1129 | "IN1L", "IN2L", "IN3L" | |
1130 | }; | |
1131 | ||
1132 | static const struct soc_enum lin_enum = | |
1133 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); | |
1134 | ||
1135 | static const struct snd_kcontrol_new lin_mux = | |
1136 | SOC_DAPM_ENUM("Left Capture Mux", lin_enum); | |
1137 | ||
1138 | static const struct soc_enum lin_inv_enum = | |
1139 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); | |
1140 | ||
1141 | static const struct snd_kcontrol_new lin_inv_mux = | |
1142 | SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); | |
1143 | ||
1144 | static const char *rin_text[] = { | |
1145 | "IN1R", "IN2R", "IN3R" | |
1146 | }; | |
1147 | ||
1148 | static const struct soc_enum rin_enum = | |
1149 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); | |
1150 | ||
1151 | static const struct snd_kcontrol_new rin_mux = | |
1152 | SOC_DAPM_ENUM("Right Capture Mux", rin_enum); | |
1153 | ||
1154 | static const struct soc_enum rin_inv_enum = | |
1155 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); | |
1156 | ||
1157 | static const struct snd_kcontrol_new rin_inv_mux = | |
1158 | SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); | |
1159 | ||
1160 | static const char *aif_text[] = { | |
1161 | "Left", "Right" | |
1162 | }; | |
1163 | ||
1164 | static const struct soc_enum aifoutl_enum = | |
1165 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); | |
1166 | ||
1167 | static const struct snd_kcontrol_new aifoutl_mux = | |
1168 | SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); | |
1169 | ||
1170 | static const struct soc_enum aifoutr_enum = | |
1171 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); | |
1172 | ||
1173 | static const struct snd_kcontrol_new aifoutr_mux = | |
1174 | SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); | |
1175 | ||
1176 | static const struct soc_enum aifinl_enum = | |
1177 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); | |
1178 | ||
1179 | static const struct snd_kcontrol_new aifinl_mux = | |
1180 | SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); | |
1181 | ||
1182 | static const struct soc_enum aifinr_enum = | |
1183 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); | |
1184 | ||
1185 | static const struct snd_kcontrol_new aifinr_mux = | |
1186 | SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); | |
1187 | ||
1188 | static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { | |
1189 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, | |
1190 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
1191 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), | |
1192 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), | |
1193 | }; | |
1194 | ||
1195 | static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { | |
1196 | SND_SOC_DAPM_INPUT("IN1L"), | |
1197 | SND_SOC_DAPM_INPUT("IN1R"), | |
1198 | SND_SOC_DAPM_INPUT("IN2L"), | |
1199 | SND_SOC_DAPM_INPUT("IN2R"), | |
1200 | SND_SOC_DAPM_INPUT("IN3L"), | |
1201 | SND_SOC_DAPM_INPUT("IN3R"), | |
1202 | ||
1203 | SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0), | |
1204 | ||
1205 | SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), | |
1206 | SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
1207 | &lin_inv_mux), | |
1208 | SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), | |
1209 | SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
1210 | &rin_inv_mux), | |
1211 | ||
1212 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, | |
1213 | NULL, 0), | |
1214 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, | |
1215 | NULL, 0), | |
1216 | ||
1217 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), | |
1218 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), | |
1219 | ||
1220 | SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), | |
1221 | SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), | |
1222 | ||
1223 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), | |
1224 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), | |
1225 | }; | |
1226 | ||
1227 | static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { | |
1228 | SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), | |
1229 | SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), | |
1230 | ||
1231 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), | |
1232 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), | |
1233 | ||
1234 | SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), | |
1235 | SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), | |
1236 | ||
1237 | SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, | |
1238 | SND_SOC_DAPM_POST_PMU), | |
1239 | ||
e4bc6696 MB |
1240 | SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
1241 | SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 | 1242 | |
e4bc6696 MB |
1243 | SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
1244 | SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 MB |
1245 | |
1246 | SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, | |
1247 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
1248 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1249 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
1250 | SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, |
1251 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
1252 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1253 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
1254 | |
1255 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
1256 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
1257 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
1258 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
1259 | }; | |
1260 | ||
1261 | static const char *out_mux_text[] = { | |
1262 | "DAC", "Bypass" | |
1263 | }; | |
1264 | ||
1265 | static const struct soc_enum hpl_enum = | |
1266 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); | |
1267 | ||
1268 | static const struct snd_kcontrol_new hpl_mux = | |
1269 | SOC_DAPM_ENUM("HPL Mux", hpl_enum); | |
1270 | ||
1271 | static const struct soc_enum hpr_enum = | |
1272 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); | |
1273 | ||
1274 | static const struct snd_kcontrol_new hpr_mux = | |
1275 | SOC_DAPM_ENUM("HPR Mux", hpr_enum); | |
1276 | ||
1277 | static const struct soc_enum linel_enum = | |
1278 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); | |
1279 | ||
1280 | static const struct snd_kcontrol_new linel_mux = | |
1281 | SOC_DAPM_ENUM("LINEL Mux", linel_enum); | |
1282 | ||
1283 | static const struct soc_enum liner_enum = | |
1284 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); | |
1285 | ||
1286 | static const struct snd_kcontrol_new liner_mux = | |
1287 | SOC_DAPM_ENUM("LINEL Mux", liner_enum); | |
1288 | ||
1289 | static const char *sidetone_text[] = { | |
1290 | "None", "Left", "Right" | |
1291 | }; | |
1292 | ||
1293 | static const struct soc_enum dacl_sidetone_enum = | |
1294 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
1295 | ||
1296 | static const struct snd_kcontrol_new dacl_sidetone_mux = | |
1297 | SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); | |
1298 | ||
1299 | static const struct soc_enum dacr_sidetone_enum = | |
1300 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
1301 | ||
1302 | static const struct snd_kcontrol_new dacr_sidetone_mux = | |
1303 | SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); | |
1304 | ||
1305 | static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { | |
1306 | SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), | |
1307 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1308 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1309 | ||
1310 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), | |
1311 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), | |
1312 | ||
1313 | SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
1314 | SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
1315 | SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), | |
1316 | SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), | |
1317 | }; | |
1318 | ||
1319 | static const struct snd_soc_dapm_route core_intercon[] = { | |
1320 | { "CLK_DSP", NULL, "SYSCLK" }, | |
1321 | { "TOCLK", NULL, "SYSCLK" }, | |
1322 | }; | |
1323 | ||
1324 | static const struct snd_soc_dapm_route adc_intercon[] = { | |
1325 | { "Left Capture Mux", "IN1L", "IN1L" }, | |
1326 | { "Left Capture Mux", "IN2L", "IN2L" }, | |
1327 | { "Left Capture Mux", "IN3L", "IN3L" }, | |
1328 | ||
1329 | { "Left Capture Inverting Mux", "IN1L", "IN1L" }, | |
1330 | { "Left Capture Inverting Mux", "IN2L", "IN2L" }, | |
1331 | { "Left Capture Inverting Mux", "IN3L", "IN3L" }, | |
1332 | ||
1333 | { "Right Capture Mux", "IN1R", "IN1R" }, | |
1334 | { "Right Capture Mux", "IN2R", "IN2R" }, | |
1335 | { "Right Capture Mux", "IN3R", "IN3R" }, | |
1336 | ||
1337 | { "Right Capture Inverting Mux", "IN1R", "IN1R" }, | |
1338 | { "Right Capture Inverting Mux", "IN2R", "IN2R" }, | |
1339 | { "Right Capture Inverting Mux", "IN3R", "IN3R" }, | |
1340 | ||
1341 | { "Left Capture PGA", NULL, "Left Capture Mux" }, | |
1342 | { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, | |
1343 | ||
1344 | { "Right Capture PGA", NULL, "Right Capture Mux" }, | |
1345 | { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, | |
1346 | ||
1347 | { "AIFOUTL", "Left", "ADCL" }, | |
1348 | { "AIFOUTL", "Right", "ADCR" }, | |
1349 | { "AIFOUTR", "Left", "ADCL" }, | |
1350 | { "AIFOUTR", "Right", "ADCR" }, | |
1351 | ||
1352 | { "ADCL", NULL, "CLK_DSP" }, | |
1353 | { "ADCL", NULL, "Left Capture PGA" }, | |
1354 | ||
1355 | { "ADCR", NULL, "CLK_DSP" }, | |
1356 | { "ADCR", NULL, "Right Capture PGA" }, | |
1357 | }; | |
1358 | ||
1359 | static const struct snd_soc_dapm_route dac_intercon[] = { | |
1360 | { "DACL", "Right", "AIFINR" }, | |
1361 | { "DACL", "Left", "AIFINL" }, | |
1362 | { "DACL", NULL, "CLK_DSP" }, | |
1363 | ||
1364 | { "DACR", "Right", "AIFINR" }, | |
1365 | { "DACR", "Left", "AIFINL" }, | |
1366 | { "DACR", NULL, "CLK_DSP" }, | |
1367 | ||
1368 | { "Charge pump", NULL, "SYSCLK" }, | |
1369 | ||
1370 | { "Headphone Output", NULL, "HPL PGA" }, | |
1371 | { "Headphone Output", NULL, "HPR PGA" }, | |
1372 | { "Headphone Output", NULL, "Charge pump" }, | |
1373 | { "Headphone Output", NULL, "TOCLK" }, | |
1374 | ||
1375 | { "Line Output", NULL, "LINEL PGA" }, | |
1376 | { "Line Output", NULL, "LINER PGA" }, | |
1377 | { "Line Output", NULL, "Charge pump" }, | |
1378 | { "Line Output", NULL, "TOCLK" }, | |
1379 | ||
1380 | { "HPOUTL", NULL, "Headphone Output" }, | |
1381 | { "HPOUTR", NULL, "Headphone Output" }, | |
1382 | ||
1383 | { "LINEOUTL", NULL, "Line Output" }, | |
1384 | { "LINEOUTR", NULL, "Line Output" }, | |
1385 | }; | |
1386 | ||
1387 | static const struct snd_soc_dapm_route wm8904_intercon[] = { | |
1388 | { "Left Sidetone", "Left", "ADCL" }, | |
1389 | { "Left Sidetone", "Right", "ADCR" }, | |
1390 | { "DACL", NULL, "Left Sidetone" }, | |
1391 | ||
1392 | { "Right Sidetone", "Left", "ADCL" }, | |
1393 | { "Right Sidetone", "Right", "ADCR" }, | |
1394 | { "DACR", NULL, "Right Sidetone" }, | |
1395 | ||
1396 | { "Left Bypass", NULL, "Class G" }, | |
1397 | { "Left Bypass", NULL, "Left Capture PGA" }, | |
1398 | ||
1399 | { "Right Bypass", NULL, "Class G" }, | |
1400 | { "Right Bypass", NULL, "Right Capture PGA" }, | |
1401 | ||
1402 | { "HPL Mux", "DAC", "DACL" }, | |
1403 | { "HPL Mux", "Bypass", "Left Bypass" }, | |
1404 | ||
1405 | { "HPR Mux", "DAC", "DACR" }, | |
1406 | { "HPR Mux", "Bypass", "Right Bypass" }, | |
1407 | ||
1408 | { "LINEL Mux", "DAC", "DACL" }, | |
1409 | { "LINEL Mux", "Bypass", "Left Bypass" }, | |
1410 | ||
1411 | { "LINER Mux", "DAC", "DACR" }, | |
1412 | { "LINER Mux", "Bypass", "Right Bypass" }, | |
1413 | ||
1414 | { "HPL PGA", NULL, "HPL Mux" }, | |
1415 | { "HPR PGA", NULL, "HPR Mux" }, | |
1416 | ||
1417 | { "LINEL PGA", NULL, "LINEL Mux" }, | |
1418 | { "LINER PGA", NULL, "LINER Mux" }, | |
1419 | }; | |
1420 | ||
8c126474 MB |
1421 | static const struct snd_soc_dapm_route wm8912_intercon[] = { |
1422 | { "HPL PGA", NULL, "DACL" }, | |
1423 | { "HPR PGA", NULL, "DACR" }, | |
1424 | ||
1425 | { "LINEL PGA", NULL, "DACL" }, | |
1426 | { "LINER PGA", NULL, "DACR" }, | |
1427 | }; | |
1428 | ||
a91eb199 MB |
1429 | static int wm8904_add_widgets(struct snd_soc_codec *codec) |
1430 | { | |
8c126474 | 1431 | struct wm8904_priv *wm8904 = codec->private_data; |
a91eb199 MB |
1432 | |
1433 | snd_soc_dapm_new_controls(codec, wm8904_core_dapm_widgets, | |
1434 | ARRAY_SIZE(wm8904_core_dapm_widgets)); | |
a91eb199 MB |
1435 | snd_soc_dapm_add_routes(codec, core_intercon, |
1436 | ARRAY_SIZE(core_intercon)); | |
8c126474 MB |
1437 | |
1438 | switch (wm8904->devtype) { | |
1439 | case WM8904: | |
1440 | snd_soc_add_controls(codec, wm8904_adc_snd_controls, | |
1441 | ARRAY_SIZE(wm8904_adc_snd_controls)); | |
1442 | snd_soc_add_controls(codec, wm8904_dac_snd_controls, | |
1443 | ARRAY_SIZE(wm8904_dac_snd_controls)); | |
1444 | snd_soc_add_controls(codec, wm8904_snd_controls, | |
1445 | ARRAY_SIZE(wm8904_snd_controls)); | |
1446 | ||
1447 | snd_soc_dapm_new_controls(codec, wm8904_adc_dapm_widgets, | |
1448 | ARRAY_SIZE(wm8904_adc_dapm_widgets)); | |
1449 | snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, | |
1450 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); | |
1451 | snd_soc_dapm_new_controls(codec, wm8904_dapm_widgets, | |
1452 | ARRAY_SIZE(wm8904_dapm_widgets)); | |
1453 | ||
1454 | snd_soc_dapm_add_routes(codec, core_intercon, | |
1455 | ARRAY_SIZE(core_intercon)); | |
1456 | snd_soc_dapm_add_routes(codec, adc_intercon, | |
1457 | ARRAY_SIZE(adc_intercon)); | |
1458 | snd_soc_dapm_add_routes(codec, dac_intercon, | |
1459 | ARRAY_SIZE(dac_intercon)); | |
1460 | snd_soc_dapm_add_routes(codec, wm8904_intercon, | |
1461 | ARRAY_SIZE(wm8904_intercon)); | |
1462 | break; | |
1463 | ||
1464 | case WM8912: | |
1465 | snd_soc_add_controls(codec, wm8904_dac_snd_controls, | |
1466 | ARRAY_SIZE(wm8904_dac_snd_controls)); | |
1467 | ||
1468 | snd_soc_dapm_new_controls(codec, wm8904_dac_dapm_widgets, | |
1469 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); | |
1470 | ||
1471 | snd_soc_dapm_add_routes(codec, dac_intercon, | |
1472 | ARRAY_SIZE(dac_intercon)); | |
1473 | snd_soc_dapm_add_routes(codec, wm8912_intercon, | |
1474 | ARRAY_SIZE(wm8912_intercon)); | |
1475 | break; | |
1476 | } | |
a91eb199 MB |
1477 | |
1478 | snd_soc_dapm_new_widgets(codec); | |
1479 | return 0; | |
1480 | } | |
1481 | ||
1482 | static struct { | |
1483 | int ratio; | |
1484 | unsigned int clk_sys_rate; | |
1485 | } clk_sys_rates[] = { | |
1486 | { 64, 0 }, | |
1487 | { 128, 1 }, | |
1488 | { 192, 2 }, | |
1489 | { 256, 3 }, | |
1490 | { 384, 4 }, | |
1491 | { 512, 5 }, | |
1492 | { 786, 6 }, | |
1493 | { 1024, 7 }, | |
1494 | { 1408, 8 }, | |
1495 | { 1536, 9 }, | |
1496 | }; | |
1497 | ||
1498 | static struct { | |
1499 | int rate; | |
1500 | int sample_rate; | |
1501 | } sample_rates[] = { | |
1502 | { 8000, 0 }, | |
1503 | { 11025, 1 }, | |
1504 | { 12000, 1 }, | |
1505 | { 16000, 2 }, | |
1506 | { 22050, 3 }, | |
1507 | { 24000, 3 }, | |
1508 | { 32000, 4 }, | |
1509 | { 44100, 5 }, | |
1510 | { 48000, 5 }, | |
1511 | }; | |
1512 | ||
1513 | static struct { | |
1514 | int div; /* *10 due to .5s */ | |
1515 | int bclk_div; | |
1516 | } bclk_divs[] = { | |
1517 | { 10, 0 }, | |
1518 | { 15, 1 }, | |
1519 | { 20, 2 }, | |
1520 | { 30, 3 }, | |
1521 | { 40, 4 }, | |
1522 | { 50, 5 }, | |
1523 | { 55, 6 }, | |
1524 | { 60, 7 }, | |
1525 | { 80, 8 }, | |
1526 | { 100, 9 }, | |
1527 | { 110, 10 }, | |
1528 | { 120, 11 }, | |
1529 | { 160, 12 }, | |
1530 | { 200, 13 }, | |
1531 | { 220, 14 }, | |
1532 | { 240, 16 }, | |
1533 | { 200, 17 }, | |
1534 | { 320, 18 }, | |
1535 | { 440, 19 }, | |
1536 | { 480, 20 }, | |
1537 | }; | |
1538 | ||
1539 | ||
1540 | static int wm8904_hw_params(struct snd_pcm_substream *substream, | |
1541 | struct snd_pcm_hw_params *params, | |
1542 | struct snd_soc_dai *dai) | |
1543 | { | |
1544 | struct snd_soc_codec *codec = dai->codec; | |
1545 | struct wm8904_priv *wm8904 = codec->private_data; | |
1546 | int ret, i, best, best_val, cur_val; | |
1547 | unsigned int aif1 = 0; | |
1548 | unsigned int aif2 = 0; | |
1549 | unsigned int aif3 = 0; | |
1550 | unsigned int clock1 = 0; | |
1551 | unsigned int dac_digital1 = 0; | |
1552 | ||
1553 | /* What BCLK do we need? */ | |
1554 | wm8904->fs = params_rate(params); | |
1555 | if (wm8904->tdm_slots) { | |
1556 | dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", | |
1557 | wm8904->tdm_slots, wm8904->tdm_width); | |
1558 | wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, | |
1559 | wm8904->tdm_width, 2, | |
1560 | wm8904->tdm_slots); | |
1561 | } else { | |
1562 | wm8904->bclk = snd_soc_params_to_bclk(params); | |
1563 | } | |
1564 | ||
56927eb0 MB |
1565 | switch (params_format(params)) { |
1566 | case SNDRV_PCM_FORMAT_S16_LE: | |
1567 | break; | |
1568 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1569 | aif1 |= 0x40; | |
1570 | break; | |
1571 | case SNDRV_PCM_FORMAT_S24_LE: | |
1572 | aif1 |= 0x80; | |
1573 | break; | |
1574 | case SNDRV_PCM_FORMAT_S32_LE: | |
1575 | aif1 |= 0xc0; | |
1576 | break; | |
1577 | default: | |
1578 | return -EINVAL; | |
1579 | } | |
1580 | ||
1581 | ||
a91eb199 MB |
1582 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); |
1583 | ||
1584 | ret = wm8904_configure_clocking(codec); | |
1585 | if (ret != 0) | |
1586 | return ret; | |
1587 | ||
1588 | /* Select nearest CLK_SYS_RATE */ | |
1589 | best = 0; | |
1590 | best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) | |
1591 | - wm8904->fs); | |
1592 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1593 | cur_val = abs((wm8904->sysclk_rate / | |
1594 | clk_sys_rates[i].ratio) - wm8904->fs);; | |
1595 | if (cur_val < best_val) { | |
1596 | best = i; | |
1597 | best_val = cur_val; | |
1598 | } | |
1599 | } | |
1600 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | |
1601 | clk_sys_rates[best].ratio); | |
1602 | clock1 |= (clk_sys_rates[best].clk_sys_rate | |
1603 | << WM8904_CLK_SYS_RATE_SHIFT); | |
1604 | ||
1605 | /* SAMPLE_RATE */ | |
1606 | best = 0; | |
1607 | best_val = abs(wm8904->fs - sample_rates[0].rate); | |
1608 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1609 | /* Closest match */ | |
1610 | cur_val = abs(wm8904->fs - sample_rates[i].rate); | |
1611 | if (cur_val < best_val) { | |
1612 | best = i; | |
1613 | best_val = cur_val; | |
1614 | } | |
1615 | } | |
1616 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | |
1617 | sample_rates[best].rate); | |
1618 | clock1 |= (sample_rates[best].sample_rate | |
1619 | << WM8904_SAMPLE_RATE_SHIFT); | |
1620 | ||
1621 | /* Enable sloping stopband filter for low sample rates */ | |
1622 | if (wm8904->fs <= 24000) | |
1623 | dac_digital1 |= WM8904_DAC_SB_FILT; | |
1624 | ||
1625 | /* BCLK_DIV */ | |
1626 | best = 0; | |
1627 | best_val = INT_MAX; | |
1628 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1629 | cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) | |
1630 | - wm8904->bclk; | |
1631 | if (cur_val < 0) /* Table is sorted */ | |
1632 | break; | |
1633 | if (cur_val < best_val) { | |
1634 | best = i; | |
1635 | best_val = cur_val; | |
1636 | } | |
1637 | } | |
1638 | wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; | |
1639 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | |
1640 | bclk_divs[best].div, wm8904->bclk); | |
1641 | aif2 |= bclk_divs[best].bclk_div; | |
1642 | ||
1643 | /* LRCLK is a simple fraction of BCLK */ | |
1644 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); | |
1645 | aif3 |= wm8904->bclk / wm8904->fs; | |
1646 | ||
1647 | /* Apply the settings */ | |
1648 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
1649 | WM8904_DAC_SB_FILT, dac_digital1); | |
1650 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1651 | WM8904_AIF_WL_MASK, aif1); | |
1652 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, | |
1653 | WM8904_BCLK_DIV_MASK, aif2); | |
1654 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1655 | WM8904_LRCLK_RATE_MASK, aif3); | |
1656 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, | |
1657 | WM8904_SAMPLE_RATE_MASK | | |
1658 | WM8904_CLK_SYS_RATE_MASK, clock1); | |
1659 | ||
1660 | /* Update filters for the new settings */ | |
1661 | wm8904_set_retune_mobile(codec); | |
1662 | wm8904_set_deemph(codec); | |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | ||
1668 | static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |
1669 | unsigned int freq, int dir) | |
1670 | { | |
1671 | struct snd_soc_codec *codec = dai->codec; | |
1672 | struct wm8904_priv *priv = codec->private_data; | |
1673 | ||
1674 | switch (clk_id) { | |
1675 | case WM8904_CLK_MCLK: | |
1676 | priv->sysclk_src = clk_id; | |
1677 | priv->mclk_rate = freq; | |
1678 | break; | |
1679 | ||
1680 | case WM8904_CLK_FLL: | |
1681 | priv->sysclk_src = clk_id; | |
1682 | break; | |
1683 | ||
1684 | default: | |
1685 | return -EINVAL; | |
1686 | } | |
1687 | ||
1688 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1689 | ||
1690 | wm8904_configure_clocking(codec); | |
1691 | ||
1692 | return 0; | |
1693 | } | |
1694 | ||
1695 | static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1696 | { | |
1697 | struct snd_soc_codec *codec = dai->codec; | |
1698 | unsigned int aif1 = 0; | |
1699 | unsigned int aif3 = 0; | |
1700 | ||
1701 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1702 | case SND_SOC_DAIFMT_CBS_CFS: | |
1703 | break; | |
1704 | case SND_SOC_DAIFMT_CBS_CFM: | |
1705 | aif3 |= WM8904_LRCLK_DIR; | |
1706 | break; | |
1707 | case SND_SOC_DAIFMT_CBM_CFS: | |
1708 | aif1 |= WM8904_BCLK_DIR; | |
1709 | break; | |
1710 | case SND_SOC_DAIFMT_CBM_CFM: | |
1711 | aif1 |= WM8904_BCLK_DIR; | |
1712 | aif3 |= WM8904_LRCLK_DIR; | |
1713 | break; | |
1714 | default: | |
1715 | return -EINVAL; | |
1716 | } | |
1717 | ||
1718 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1719 | case SND_SOC_DAIFMT_DSP_B: | |
1720 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1721 | case SND_SOC_DAIFMT_DSP_A: | |
1722 | aif1 |= 0x3; | |
1723 | break; | |
1724 | case SND_SOC_DAIFMT_I2S: | |
1725 | aif1 |= 0x2; | |
1726 | break; | |
1727 | case SND_SOC_DAIFMT_RIGHT_J: | |
1728 | break; | |
1729 | case SND_SOC_DAIFMT_LEFT_J: | |
1730 | aif1 |= 0x1; | |
1731 | break; | |
1732 | default: | |
1733 | return -EINVAL; | |
1734 | } | |
1735 | ||
1736 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1737 | case SND_SOC_DAIFMT_DSP_A: | |
1738 | case SND_SOC_DAIFMT_DSP_B: | |
1739 | /* frame inversion not valid for DSP modes */ | |
1740 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1741 | case SND_SOC_DAIFMT_NB_NF: | |
1742 | break; | |
1743 | case SND_SOC_DAIFMT_IB_NF: | |
1744 | aif1 |= WM8904_AIF_BCLK_INV; | |
1745 | break; | |
1746 | default: | |
1747 | return -EINVAL; | |
1748 | } | |
1749 | break; | |
1750 | ||
1751 | case SND_SOC_DAIFMT_I2S: | |
1752 | case SND_SOC_DAIFMT_RIGHT_J: | |
1753 | case SND_SOC_DAIFMT_LEFT_J: | |
1754 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1755 | case SND_SOC_DAIFMT_NB_NF: | |
1756 | break; | |
1757 | case SND_SOC_DAIFMT_IB_IF: | |
1758 | aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; | |
1759 | break; | |
1760 | case SND_SOC_DAIFMT_IB_NF: | |
1761 | aif1 |= WM8904_AIF_BCLK_INV; | |
1762 | break; | |
1763 | case SND_SOC_DAIFMT_NB_IF: | |
1764 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1765 | break; | |
1766 | default: | |
1767 | return -EINVAL; | |
1768 | } | |
1769 | break; | |
1770 | default: | |
1771 | return -EINVAL; | |
1772 | } | |
1773 | ||
1774 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1775 | WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | | |
1776 | WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); | |
1777 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1778 | WM8904_LRCLK_DIR, aif3); | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
1783 | ||
1784 | static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
1785 | unsigned int rx_mask, int slots, int slot_width) | |
1786 | { | |
1787 | struct snd_soc_codec *codec = dai->codec; | |
1788 | struct wm8904_priv *wm8904 = codec->private_data; | |
1789 | int aif1 = 0; | |
1790 | ||
1791 | /* Don't need to validate anything if we're turning off TDM */ | |
1792 | if (slots == 0) | |
1793 | goto out; | |
1794 | ||
1795 | /* Note that we allow configurations we can't handle ourselves - | |
1796 | * for example, we can generate clocks for slots 2 and up even if | |
1797 | * we can't use those slots ourselves. | |
1798 | */ | |
1799 | aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; | |
1800 | ||
1801 | switch (rx_mask) { | |
1802 | case 3: | |
1803 | break; | |
1804 | case 0xc: | |
1805 | aif1 |= WM8904_AIFADC_TDM_CHAN; | |
1806 | break; | |
1807 | default: | |
1808 | return -EINVAL; | |
1809 | } | |
1810 | ||
1811 | ||
1812 | switch (tx_mask) { | |
1813 | case 3: | |
1814 | break; | |
1815 | case 0xc: | |
1816 | aif1 |= WM8904_AIFDAC_TDM_CHAN; | |
1817 | break; | |
1818 | default: | |
1819 | return -EINVAL; | |
1820 | } | |
1821 | ||
1822 | out: | |
1823 | wm8904->tdm_width = slot_width; | |
1824 | wm8904->tdm_slots = slots / 2; | |
1825 | ||
1826 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1827 | WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | | |
1828 | WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
1832 | ||
1833 | struct _fll_div { | |
1834 | u16 fll_fratio; | |
1835 | u16 fll_outdiv; | |
1836 | u16 fll_clk_ref_div; | |
1837 | u16 n; | |
1838 | u16 k; | |
1839 | }; | |
1840 | ||
1841 | /* The size in bits of the FLL divide multiplied by 10 | |
1842 | * to allow rounding later */ | |
1843 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1844 | ||
1845 | static struct { | |
1846 | unsigned int min; | |
1847 | unsigned int max; | |
1848 | u16 fll_fratio; | |
1849 | int ratio; | |
1850 | } fll_fratios[] = { | |
1851 | { 0, 64000, 4, 16 }, | |
1852 | { 64000, 128000, 3, 8 }, | |
1853 | { 128000, 256000, 2, 4 }, | |
1854 | { 256000, 1000000, 1, 2 }, | |
1855 | { 1000000, 13500000, 0, 1 }, | |
1856 | }; | |
1857 | ||
1858 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1859 | unsigned int Fout) | |
1860 | { | |
1861 | u64 Kpart; | |
1862 | unsigned int K, Ndiv, Nmod, target; | |
1863 | unsigned int div; | |
1864 | int i; | |
1865 | ||
1866 | /* Fref must be <=13.5MHz */ | |
1867 | div = 1; | |
1868 | fll_div->fll_clk_ref_div = 0; | |
1869 | while ((Fref / div) > 13500000) { | |
1870 | div *= 2; | |
1871 | fll_div->fll_clk_ref_div++; | |
1872 | ||
1873 | if (div > 8) { | |
1874 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1875 | Fref); | |
1876 | return -EINVAL; | |
1877 | } | |
1878 | } | |
1879 | ||
1880 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
1881 | ||
1882 | /* Apply the division for our remaining calculations */ | |
1883 | Fref /= div; | |
1884 | ||
1885 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
1886 | div = 4; | |
1887 | while (Fout * div < 90000000) { | |
1888 | div++; | |
1889 | if (div > 64) { | |
1890 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
1891 | Fout); | |
1892 | return -EINVAL; | |
1893 | } | |
1894 | } | |
1895 | target = Fout * div; | |
1896 | fll_div->fll_outdiv = div - 1; | |
1897 | ||
1898 | pr_debug("Fvco=%dHz\n", target); | |
1899 | ||
1900 | /* Find an appropraite FLL_FRATIO and factor it out of the target */ | |
1901 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { | |
1902 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
1903 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
1904 | target /= fll_fratios[i].ratio; | |
1905 | break; | |
1906 | } | |
1907 | } | |
1908 | if (i == ARRAY_SIZE(fll_fratios)) { | |
1909 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
1910 | return -EINVAL; | |
1911 | } | |
1912 | ||
1913 | /* Now, calculate N.K */ | |
1914 | Ndiv = target / Fref; | |
1915 | ||
1916 | fll_div->n = Ndiv; | |
1917 | Nmod = target % Fref; | |
1918 | pr_debug("Nmod=%d\n", Nmod); | |
1919 | ||
1920 | /* Calculate fractional part - scale up so we can round. */ | |
1921 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1922 | ||
1923 | do_div(Kpart, Fref); | |
1924 | ||
1925 | K = Kpart & 0xFFFFFFFF; | |
1926 | ||
1927 | if ((K % 10) >= 5) | |
1928 | K += 5; | |
1929 | ||
1930 | /* Move down to proper range now rounding is done */ | |
1931 | fll_div->k = K / 10; | |
1932 | ||
1933 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
1934 | fll_div->n, fll_div->k, | |
1935 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
1936 | fll_div->fll_clk_ref_div); | |
1937 | ||
1938 | return 0; | |
1939 | } | |
1940 | ||
1941 | static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, | |
1942 | unsigned int Fref, unsigned int Fout) | |
1943 | { | |
1944 | struct snd_soc_codec *codec = dai->codec; | |
1945 | struct wm8904_priv *wm8904 = codec->private_data; | |
1946 | struct _fll_div fll_div; | |
1947 | int ret, val; | |
1948 | int clock2, fll1; | |
1949 | ||
1950 | /* Any change? */ | |
1951 | if (source == wm8904->fll_src && Fref == wm8904->fll_fref && | |
1952 | Fout == wm8904->fll_fout) | |
1953 | return 0; | |
1954 | ||
18240b67 MB |
1955 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); |
1956 | ||
a91eb199 MB |
1957 | if (Fout == 0) { |
1958 | dev_dbg(codec->dev, "FLL disabled\n"); | |
1959 | ||
1960 | wm8904->fll_fref = 0; | |
1961 | wm8904->fll_fout = 0; | |
1962 | ||
1963 | /* Gate SYSCLK to avoid glitches */ | |
1964 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
1965 | WM8904_CLK_SYS_ENA, 0); | |
1966 | ||
1967 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1968 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
1969 | ||
1970 | goto out; | |
1971 | } | |
1972 | ||
1973 | /* Validate the FLL ID */ | |
1974 | switch (source) { | |
1975 | case WM8904_FLL_MCLK: | |
1976 | case WM8904_FLL_LRCLK: | |
1977 | case WM8904_FLL_BCLK: | |
1978 | ret = fll_factors(&fll_div, Fref, Fout); | |
1979 | if (ret != 0) | |
1980 | return ret; | |
1981 | break; | |
1982 | ||
1983 | case WM8904_FLL_FREE_RUNNING: | |
1984 | dev_dbg(codec->dev, "Using free running FLL\n"); | |
1985 | /* Force 12MHz and output/4 for now */ | |
1986 | Fout = 12000000; | |
1987 | Fref = 12000000; | |
1988 | ||
1989 | memset(&fll_div, 0, sizeof(fll_div)); | |
1990 | fll_div.fll_outdiv = 3; | |
1991 | break; | |
1992 | ||
1993 | default: | |
1994 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | |
1995 | return -EINVAL; | |
1996 | } | |
1997 | ||
1998 | /* Save current state then disable the FLL and SYSCLK to avoid | |
1999 | * misclocking */ | |
a91eb199 MB |
2000 | fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); |
2001 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
2002 | WM8904_CLK_SYS_ENA, 0); | |
2003 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2004 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
2005 | ||
2006 | /* Unlock forced oscilator control to switch it on/off */ | |
2007 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
2008 | WM8904_USER_KEY, WM8904_USER_KEY); | |
2009 | ||
2010 | if (fll_id == WM8904_FLL_FREE_RUNNING) { | |
2011 | val = WM8904_FLL_FRC_NCO; | |
2012 | } else { | |
2013 | val = 0; | |
2014 | } | |
2015 | ||
2016 | snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, | |
2017 | val); | |
2018 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
2019 | WM8904_USER_KEY, 0); | |
2020 | ||
2021 | switch (fll_id) { | |
2022 | case WM8904_FLL_MCLK: | |
2023 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2024 | WM8904_FLL_CLK_REF_SRC_MASK, 0); | |
2025 | break; | |
2026 | ||
2027 | case WM8904_FLL_LRCLK: | |
2028 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2029 | WM8904_FLL_CLK_REF_SRC_MASK, 1); | |
2030 | break; | |
2031 | ||
2032 | case WM8904_FLL_BCLK: | |
2033 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2034 | WM8904_FLL_CLK_REF_SRC_MASK, 2); | |
2035 | break; | |
2036 | } | |
2037 | ||
2038 | if (fll_div.k) | |
2039 | val = WM8904_FLL_FRACN_ENA; | |
2040 | else | |
2041 | val = 0; | |
2042 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2043 | WM8904_FLL_FRACN_ENA, val); | |
2044 | ||
2045 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, | |
2046 | WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, | |
2047 | (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | | |
2048 | (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); | |
2049 | ||
2050 | snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); | |
2051 | ||
2052 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, | |
2053 | fll_div.n << WM8904_FLL_N_SHIFT); | |
2054 | ||
2055 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
2056 | WM8904_FLL_CLK_REF_DIV_MASK, | |
2057 | fll_div.fll_clk_ref_div | |
2058 | << WM8904_FLL_CLK_REF_DIV_SHIFT); | |
2059 | ||
2060 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
2061 | ||
2062 | wm8904->fll_fref = Fref; | |
2063 | wm8904->fll_fout = Fout; | |
2064 | wm8904->fll_src = source; | |
2065 | ||
2066 | /* Enable the FLL if it was previously active */ | |
2067 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2068 | WM8904_FLL_OSC_ENA, fll1); | |
2069 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
2070 | WM8904_FLL_ENA, fll1); | |
2071 | ||
2072 | out: | |
2073 | /* Reenable SYSCLK if it was previously active */ | |
2074 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
2075 | WM8904_CLK_SYS_ENA, clock2); | |
2076 | ||
2077 | return 0; | |
2078 | } | |
2079 | ||
2080 | static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
2081 | { | |
2082 | struct snd_soc_codec *codec = codec_dai->codec; | |
2083 | int val; | |
2084 | ||
2085 | if (mute) | |
2086 | val = WM8904_DAC_MUTE; | |
2087 | else | |
2088 | val = 0; | |
2089 | ||
2090 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); | |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
c1334218 MB |
2095 | static void wm8904_sync_cache(struct snd_soc_codec *codec) |
2096 | { | |
2097 | struct wm8904_priv *wm8904 = codec->private_data; | |
2098 | int i; | |
2099 | ||
2100 | if (!codec->cache_sync) | |
2101 | return; | |
2102 | ||
2103 | codec->cache_only = 0; | |
2104 | ||
2105 | /* Sync back cached values if they're different from the | |
2106 | * hardware default. | |
2107 | */ | |
2108 | for (i = 1; i < ARRAY_SIZE(wm8904->reg_cache); i++) { | |
2109 | if (!wm8904_access[i].writable) | |
2110 | continue; | |
2111 | ||
2112 | if (wm8904->reg_cache[i] == wm8904_reg[i]) | |
2113 | continue; | |
2114 | ||
2115 | snd_soc_write(codec, i, wm8904->reg_cache[i]); | |
2116 | } | |
2117 | ||
2118 | codec->cache_sync = 0; | |
2119 | } | |
2120 | ||
a91eb199 MB |
2121 | static int wm8904_set_bias_level(struct snd_soc_codec *codec, |
2122 | enum snd_soc_bias_level level) | |
2123 | { | |
2124 | struct wm8904_priv *wm8904 = codec->private_data; | |
c1334218 | 2125 | int ret; |
a91eb199 MB |
2126 | |
2127 | switch (level) { | |
2128 | case SND_SOC_BIAS_ON: | |
2129 | break; | |
2130 | ||
2131 | case SND_SOC_BIAS_PREPARE: | |
2132 | /* VMID resistance 2*50k */ | |
2133 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2134 | WM8904_VMID_RES_MASK, | |
2135 | 0x1 << WM8904_VMID_RES_SHIFT); | |
2136 | ||
2137 | /* Normal bias current */ | |
2138 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2139 | WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); | |
2140 | break; | |
2141 | ||
2142 | case SND_SOC_BIAS_STANDBY: | |
2143 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | |
2144 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2145 | wm8904->supplies); | |
2146 | if (ret != 0) { | |
2147 | dev_err(codec->dev, | |
2148 | "Failed to enable supplies: %d\n", | |
2149 | ret); | |
2150 | return ret; | |
2151 | } | |
2152 | ||
c1334218 | 2153 | wm8904_sync_cache(codec); |
a91eb199 MB |
2154 | |
2155 | /* Enable bias */ | |
2156 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2157 | WM8904_BIAS_ENA, WM8904_BIAS_ENA); | |
2158 | ||
2159 | /* Enable VMID, VMID buffering, 2*5k resistance */ | |
2160 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2161 | WM8904_VMID_ENA | | |
2162 | WM8904_VMID_RES_MASK, | |
2163 | WM8904_VMID_ENA | | |
2164 | 0x3 << WM8904_VMID_RES_SHIFT); | |
2165 | ||
2166 | /* Let VMID ramp */ | |
2167 | msleep(1); | |
2168 | } | |
2169 | ||
2170 | /* Maintain VMID with 2*250k */ | |
2171 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2172 | WM8904_VMID_RES_MASK, | |
2173 | 0x2 << WM8904_VMID_RES_SHIFT); | |
2174 | ||
2175 | /* Bias current *0.5 */ | |
2176 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2177 | WM8904_ISEL_MASK, 0); | |
2178 | break; | |
2179 | ||
2180 | case SND_SOC_BIAS_OFF: | |
2181 | /* Turn off VMID */ | |
2182 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
2183 | WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); | |
2184 | ||
2185 | /* Stop bias generation */ | |
2186 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
2187 | WM8904_BIAS_ENA, 0); | |
2188 | ||
c1334218 MB |
2189 | #ifdef CONFIG_REGULATOR |
2190 | /* Post 2.6.34 we will be able to get a callback when | |
2191 | * the regulators are disabled which we can use but | |
2192 | * for now just assume that the power will be cut if | |
2193 | * the regulator API is in use. | |
2194 | */ | |
2195 | codec->cache_sync = 1; | |
2196 | #endif | |
2197 | ||
a91eb199 MB |
2198 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), |
2199 | wm8904->supplies); | |
2200 | break; | |
2201 | } | |
2202 | codec->bias_level = level; | |
2203 | return 0; | |
2204 | } | |
2205 | ||
2206 | #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 | |
2207 | ||
2208 | #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
2209 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
2210 | ||
2211 | static struct snd_soc_dai_ops wm8904_dai_ops = { | |
2212 | .set_sysclk = wm8904_set_sysclk, | |
2213 | .set_fmt = wm8904_set_fmt, | |
2214 | .set_tdm_slot = wm8904_set_tdm_slot, | |
2215 | .set_pll = wm8904_set_fll, | |
2216 | .hw_params = wm8904_hw_params, | |
2217 | .digital_mute = wm8904_digital_mute, | |
2218 | }; | |
2219 | ||
2220 | struct snd_soc_dai wm8904_dai = { | |
2221 | .name = "WM8904", | |
2222 | .playback = { | |
2223 | .stream_name = "Playback", | |
2224 | .channels_min = 2, | |
2225 | .channels_max = 2, | |
2226 | .rates = WM8904_RATES, | |
2227 | .formats = WM8904_FORMATS, | |
2228 | }, | |
2229 | .capture = { | |
2230 | .stream_name = "Capture", | |
2231 | .channels_min = 2, | |
2232 | .channels_max = 2, | |
2233 | .rates = WM8904_RATES, | |
2234 | .formats = WM8904_FORMATS, | |
2235 | }, | |
2236 | .ops = &wm8904_dai_ops, | |
2237 | .symmetric_rates = 1, | |
2238 | }; | |
2239 | EXPORT_SYMBOL_GPL(wm8904_dai); | |
2240 | ||
2241 | #ifdef CONFIG_PM | |
2242 | static int wm8904_suspend(struct platform_device *pdev, pm_message_t state) | |
2243 | { | |
2244 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
2245 | struct snd_soc_codec *codec = socdev->card->codec; | |
2246 | ||
2247 | wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
2248 | ||
2249 | return 0; | |
2250 | } | |
2251 | ||
2252 | static int wm8904_resume(struct platform_device *pdev) | |
2253 | { | |
2254 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
2255 | struct snd_soc_codec *codec = socdev->card->codec; | |
2256 | ||
2257 | wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2258 | ||
2259 | return 0; | |
2260 | } | |
2261 | #else | |
2262 | #define wm8904_suspend NULL | |
2263 | #define wm8904_resume NULL | |
2264 | #endif | |
2265 | ||
2266 | static void wm8904_handle_retune_mobile_pdata(struct wm8904_priv *wm8904) | |
2267 | { | |
2268 | struct snd_soc_codec *codec = &wm8904->codec; | |
2269 | struct wm8904_pdata *pdata = wm8904->pdata; | |
2270 | struct snd_kcontrol_new control = | |
2271 | SOC_ENUM_EXT("EQ Mode", | |
2272 | wm8904->retune_mobile_enum, | |
2273 | wm8904_get_retune_mobile_enum, | |
2274 | wm8904_put_retune_mobile_enum); | |
2275 | int ret, i, j; | |
2276 | const char **t; | |
2277 | ||
2278 | /* We need an array of texts for the enum API but the number | |
2279 | * of texts is likely to be less than the number of | |
2280 | * configurations due to the sample rate dependency of the | |
2281 | * configurations. */ | |
2282 | wm8904->num_retune_mobile_texts = 0; | |
2283 | wm8904->retune_mobile_texts = NULL; | |
2284 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
2285 | for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { | |
2286 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
2287 | wm8904->retune_mobile_texts[j]) == 0) | |
2288 | break; | |
2289 | } | |
2290 | ||
2291 | if (j != wm8904->num_retune_mobile_texts) | |
2292 | continue; | |
2293 | ||
2294 | /* Expand the array... */ | |
2295 | t = krealloc(wm8904->retune_mobile_texts, | |
2296 | sizeof(char *) * | |
2297 | (wm8904->num_retune_mobile_texts + 1), | |
2298 | GFP_KERNEL); | |
2299 | if (t == NULL) | |
2300 | continue; | |
2301 | ||
2302 | /* ...store the new entry... */ | |
2303 | t[wm8904->num_retune_mobile_texts] = | |
2304 | pdata->retune_mobile_cfgs[i].name; | |
2305 | ||
2306 | /* ...and remember the new version. */ | |
2307 | wm8904->num_retune_mobile_texts++; | |
2308 | wm8904->retune_mobile_texts = t; | |
2309 | } | |
2310 | ||
2311 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
2312 | wm8904->num_retune_mobile_texts); | |
2313 | ||
2314 | wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; | |
2315 | wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; | |
2316 | ||
2317 | ret = snd_soc_add_controls(&wm8904->codec, &control, 1); | |
2318 | if (ret != 0) | |
2319 | dev_err(wm8904->codec.dev, | |
2320 | "Failed to add ReTune Mobile control: %d\n", ret); | |
2321 | } | |
2322 | ||
2323 | static void wm8904_handle_pdata(struct wm8904_priv *wm8904) | |
2324 | { | |
2325 | struct snd_soc_codec *codec = &wm8904->codec; | |
2326 | struct wm8904_pdata *pdata = wm8904->pdata; | |
2327 | int ret, i; | |
2328 | ||
2329 | if (!pdata) { | |
2330 | snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls, | |
2331 | ARRAY_SIZE(wm8904_eq_controls)); | |
2332 | return; | |
2333 | } | |
2334 | ||
2335 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
2336 | ||
2337 | if (pdata->num_drc_cfgs) { | |
2338 | struct snd_kcontrol_new control = | |
2339 | SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, | |
2340 | wm8904_get_drc_enum, wm8904_put_drc_enum); | |
2341 | ||
2342 | /* We need an array of texts for the enum API */ | |
2343 | wm8904->drc_texts = kmalloc(sizeof(char *) | |
2344 | * pdata->num_drc_cfgs, GFP_KERNEL); | |
2345 | if (!wm8904->drc_texts) { | |
2346 | dev_err(wm8904->codec.dev, | |
2347 | "Failed to allocate %d DRC config texts\n", | |
2348 | pdata->num_drc_cfgs); | |
2349 | return; | |
2350 | } | |
2351 | ||
2352 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
2353 | wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; | |
2354 | ||
2355 | wm8904->drc_enum.max = pdata->num_drc_cfgs; | |
2356 | wm8904->drc_enum.texts = wm8904->drc_texts; | |
2357 | ||
2358 | ret = snd_soc_add_controls(&wm8904->codec, &control, 1); | |
2359 | if (ret != 0) | |
2360 | dev_err(wm8904->codec.dev, | |
2361 | "Failed to add DRC mode control: %d\n", ret); | |
2362 | ||
2363 | wm8904_set_drc(codec); | |
2364 | } | |
2365 | ||
2366 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", | |
2367 | pdata->num_retune_mobile_cfgs); | |
2368 | ||
2369 | if (pdata->num_retune_mobile_cfgs) | |
2370 | wm8904_handle_retune_mobile_pdata(wm8904); | |
2371 | else | |
2372 | snd_soc_add_controls(&wm8904->codec, wm8904_eq_controls, | |
2373 | ARRAY_SIZE(wm8904_eq_controls)); | |
2374 | } | |
2375 | ||
2376 | static int wm8904_probe(struct platform_device *pdev) | |
2377 | { | |
2378 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
2379 | struct snd_soc_codec *codec; | |
2380 | int ret = 0; | |
2381 | ||
2382 | if (wm8904_codec == NULL) { | |
2383 | dev_err(&pdev->dev, "Codec device not registered\n"); | |
2384 | return -ENODEV; | |
2385 | } | |
2386 | ||
2387 | socdev->card->codec = wm8904_codec; | |
2388 | codec = wm8904_codec; | |
2389 | ||
2390 | /* register pcms */ | |
2391 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
2392 | if (ret < 0) { | |
2393 | dev_err(codec->dev, "failed to create pcms: %d\n", ret); | |
2394 | goto pcm_err; | |
2395 | } | |
2396 | ||
2397 | wm8904_handle_pdata(codec->private_data); | |
2398 | ||
2399 | wm8904_add_widgets(codec); | |
2400 | ||
2401 | return ret; | |
2402 | ||
2403 | pcm_err: | |
2404 | return ret; | |
2405 | } | |
2406 | ||
2407 | static int wm8904_remove(struct platform_device *pdev) | |
2408 | { | |
2409 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
2410 | ||
2411 | snd_soc_free_pcms(socdev); | |
2412 | snd_soc_dapm_free(socdev); | |
2413 | ||
2414 | return 0; | |
2415 | } | |
2416 | ||
2417 | struct snd_soc_codec_device soc_codec_dev_wm8904 = { | |
2418 | .probe = wm8904_probe, | |
2419 | .remove = wm8904_remove, | |
2420 | .suspend = wm8904_suspend, | |
2421 | .resume = wm8904_resume, | |
2422 | }; | |
2423 | EXPORT_SYMBOL_GPL(soc_codec_dev_wm8904); | |
2424 | ||
2425 | static int wm8904_register(struct wm8904_priv *wm8904, | |
2426 | enum snd_soc_control_type control) | |
2427 | { | |
2428 | int ret; | |
2429 | struct snd_soc_codec *codec = &wm8904->codec; | |
2430 | int i; | |
2431 | ||
2432 | if (wm8904_codec) { | |
2433 | dev_err(codec->dev, "Another WM8904 is registered\n"); | |
2434 | return -EINVAL; | |
2435 | } | |
2436 | ||
2437 | mutex_init(&codec->mutex); | |
2438 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
2439 | INIT_LIST_HEAD(&codec->dapm_paths); | |
2440 | ||
2441 | codec->private_data = wm8904; | |
2442 | codec->name = "WM8904"; | |
2443 | codec->owner = THIS_MODULE; | |
2444 | codec->bias_level = SND_SOC_BIAS_OFF; | |
2445 | codec->set_bias_level = wm8904_set_bias_level; | |
2446 | codec->dai = &wm8904_dai; | |
2447 | codec->num_dai = 1; | |
2448 | codec->reg_cache_size = WM8904_MAX_REGISTER; | |
2449 | codec->reg_cache = &wm8904->reg_cache; | |
2450 | codec->volatile_register = wm8904_volatile_register; | |
c1334218 MB |
2451 | codec->cache_sync = 1; |
2452 | codec->idle_bias_off = 1; | |
a91eb199 | 2453 | |
8c126474 MB |
2454 | switch (wm8904->devtype) { |
2455 | case WM8904: | |
2456 | break; | |
2457 | case WM8912: | |
2458 | memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); | |
2459 | break; | |
2460 | default: | |
2461 | dev_err(codec->dev, "Unknown device type %d\n", | |
2462 | wm8904->devtype); | |
2463 | return -EINVAL; | |
2464 | } | |
2465 | ||
a91eb199 MB |
2466 | memcpy(codec->reg_cache, wm8904_reg, sizeof(wm8904_reg)); |
2467 | ||
2468 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, control); | |
2469 | if (ret != 0) { | |
2470 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
2471 | goto err; | |
2472 | } | |
2473 | ||
2474 | for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) | |
2475 | wm8904->supplies[i].supply = wm8904_supply_names[i]; | |
2476 | ||
2477 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies), | |
2478 | wm8904->supplies); | |
2479 | if (ret != 0) { | |
2480 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
2481 | goto err; | |
2482 | } | |
2483 | ||
2484 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2485 | wm8904->supplies); | |
2486 | if (ret != 0) { | |
2487 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
2488 | goto err_get; | |
2489 | } | |
2490 | ||
2491 | ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID); | |
2492 | if (ret < 0) { | |
2493 | dev_err(codec->dev, "Failed to read ID register\n"); | |
2494 | goto err_enable; | |
2495 | } | |
2496 | if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) { | |
2497 | dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret); | |
2498 | ret = -EINVAL; | |
2499 | goto err_enable; | |
2500 | } | |
2501 | ||
2502 | ret = snd_soc_read(codec, WM8904_REVISION); | |
2503 | if (ret < 0) { | |
2504 | dev_err(codec->dev, "Failed to read device revision: %d\n", | |
2505 | ret); | |
2506 | goto err_enable; | |
2507 | } | |
2508 | dev_info(codec->dev, "revision %c\n", ret + 'A'); | |
2509 | ||
2510 | ret = wm8904_reset(codec); | |
2511 | if (ret < 0) { | |
2512 | dev_err(codec->dev, "Failed to issue reset\n"); | |
2513 | goto err_enable; | |
2514 | } | |
2515 | ||
2516 | wm8904_dai.dev = codec->dev; | |
2517 | ||
2518 | /* Change some default settings - latch VU and enable ZC */ | |
2519 | wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_LEFT] |= WM8904_ADC_VU; | |
2520 | wm8904->reg_cache[WM8904_ADC_DIGITAL_VOLUME_RIGHT] |= WM8904_ADC_VU; | |
2521 | wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_LEFT] |= WM8904_DAC_VU; | |
2522 | wm8904->reg_cache[WM8904_DAC_DIGITAL_VOLUME_RIGHT] |= WM8904_DAC_VU; | |
2523 | wm8904->reg_cache[WM8904_ANALOGUE_OUT1_LEFT] |= WM8904_HPOUT_VU | | |
2524 | WM8904_HPOUTLZC; | |
2525 | wm8904->reg_cache[WM8904_ANALOGUE_OUT1_RIGHT] |= WM8904_HPOUT_VU | | |
2526 | WM8904_HPOUTRZC; | |
2527 | wm8904->reg_cache[WM8904_ANALOGUE_OUT2_LEFT] |= WM8904_LINEOUT_VU | | |
2528 | WM8904_LINEOUTLZC; | |
2529 | wm8904->reg_cache[WM8904_ANALOGUE_OUT2_RIGHT] |= WM8904_LINEOUT_VU | | |
2530 | WM8904_LINEOUTRZC; | |
2531 | wm8904->reg_cache[WM8904_CLOCK_RATES_0] &= ~WM8904_SR_MODE; | |
2532 | ||
2533 | /* Set Class W by default - this will be managed by the Class | |
2534 | * G widget at runtime where bypass paths are available. | |
2535 | */ | |
2536 | wm8904->reg_cache[WM8904_CLASS_W_0] |= WM8904_CP_DYN_PWR; | |
2537 | ||
2538 | /* Use normal bias source */ | |
2539 | wm8904->reg_cache[WM8904_BIAS_CONTROL_0] &= ~WM8904_POBCTRL; | |
2540 | ||
2541 | wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
2542 | ||
2543 | /* Bias level configuration will have done an extra enable */ | |
2544 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2545 | ||
2546 | wm8904_codec = codec; | |
2547 | ||
2548 | ret = snd_soc_register_codec(codec); | |
2549 | if (ret != 0) { | |
2550 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | |
2551 | return ret; | |
2552 | } | |
2553 | ||
2554 | ret = snd_soc_register_dai(&wm8904_dai); | |
2555 | if (ret != 0) { | |
2556 | dev_err(codec->dev, "Failed to register DAI: %d\n", ret); | |
2557 | snd_soc_unregister_codec(codec); | |
2558 | return ret; | |
2559 | } | |
2560 | ||
2561 | return 0; | |
2562 | ||
2563 | err_enable: | |
2564 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2565 | err_get: | |
2566 | regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2567 | err: | |
2568 | kfree(wm8904); | |
2569 | return ret; | |
2570 | } | |
2571 | ||
2572 | static void wm8904_unregister(struct wm8904_priv *wm8904) | |
2573 | { | |
2574 | wm8904_set_bias_level(&wm8904->codec, SND_SOC_BIAS_OFF); | |
2575 | regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2576 | snd_soc_unregister_dai(&wm8904_dai); | |
2577 | snd_soc_unregister_codec(&wm8904->codec); | |
2578 | kfree(wm8904); | |
2579 | wm8904_codec = NULL; | |
2580 | } | |
2581 | ||
2582 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
2583 | static __devinit int wm8904_i2c_probe(struct i2c_client *i2c, | |
2584 | const struct i2c_device_id *id) | |
2585 | { | |
2586 | struct wm8904_priv *wm8904; | |
2587 | struct snd_soc_codec *codec; | |
2588 | ||
2589 | wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL); | |
2590 | if (wm8904 == NULL) | |
2591 | return -ENOMEM; | |
2592 | ||
2593 | codec = &wm8904->codec; | |
2594 | codec->hw_write = (hw_write_t)i2c_master_send; | |
2595 | ||
8c126474 MB |
2596 | wm8904->devtype = id->driver_data; |
2597 | ||
a91eb199 MB |
2598 | i2c_set_clientdata(i2c, wm8904); |
2599 | codec->control_data = i2c; | |
2600 | wm8904->pdata = i2c->dev.platform_data; | |
2601 | ||
2602 | codec->dev = &i2c->dev; | |
2603 | ||
2604 | return wm8904_register(wm8904, SND_SOC_I2C); | |
2605 | } | |
2606 | ||
2607 | static __devexit int wm8904_i2c_remove(struct i2c_client *client) | |
2608 | { | |
2609 | struct wm8904_priv *wm8904 = i2c_get_clientdata(client); | |
2610 | wm8904_unregister(wm8904); | |
2611 | return 0; | |
2612 | } | |
2613 | ||
2614 | static const struct i2c_device_id wm8904_i2c_id[] = { | |
8c126474 MB |
2615 | { "wm8904", WM8904 }, |
2616 | { "wm8912", WM8912 }, | |
a91eb199 MB |
2617 | { } |
2618 | }; | |
2619 | MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); | |
2620 | ||
2621 | static struct i2c_driver wm8904_i2c_driver = { | |
2622 | .driver = { | |
2623 | .name = "WM8904", | |
2624 | .owner = THIS_MODULE, | |
2625 | }, | |
2626 | .probe = wm8904_i2c_probe, | |
2627 | .remove = __devexit_p(wm8904_i2c_remove), | |
2628 | .id_table = wm8904_i2c_id, | |
2629 | }; | |
2630 | #endif | |
2631 | ||
2632 | static int __init wm8904_modinit(void) | |
2633 | { | |
2634 | int ret; | |
2635 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
2636 | ret = i2c_add_driver(&wm8904_i2c_driver); | |
2637 | if (ret != 0) { | |
2638 | printk(KERN_ERR "Failed to register WM8904 I2C driver: %d\n", | |
2639 | ret); | |
2640 | } | |
2641 | #endif | |
2642 | return 0; | |
2643 | } | |
2644 | module_init(wm8904_modinit); | |
2645 | ||
2646 | static void __exit wm8904_exit(void) | |
2647 | { | |
2648 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
2649 | i2c_del_driver(&wm8904_i2c_driver); | |
2650 | #endif | |
2651 | } | |
2652 | module_exit(wm8904_exit); | |
2653 | ||
2654 | MODULE_DESCRIPTION("ASoC WM8904 driver"); | |
2655 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
2656 | MODULE_LICENSE("GPL"); |