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ASoC: Convert wm8960 MICBIAS to a supply widget
[deliverable/linux.git] / sound / soc / codecs / wm8904.c
CommitLineData
a91eb199
MB		 1/*
2 * wm8904.c -- WM8904 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
5a0e3ad6 22#include <linux/slab.h>
a91eb199
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
a91eb199
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/wm8904.h>
30
31#include "wm8904.h"
32
8c126474
MB		 33enum wm8904_type {
34 WM8904,
35 WM8912,
36};
37
a91eb199
MB		 38#define WM8904_NUM_DCS_CHANNELS 4
39
40#define WM8904_NUM_SUPPLIES 5
41static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47};
48
49/* codec private data */
50struct wm8904_priv {
f0fba2ad 51
8c126474
MB		 52 enum wm8904_type devtype;
53
a91eb199
MB		 54 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
55
56 struct wm8904_pdata *pdata;
57
58 int deemph;
59
60 /* Platform provided DRC configuration */
61 const char **drc_texts;
62 int drc_cfg;
63 struct soc_enum drc_enum;
64
65 /* Platform provided ReTune mobile configuration */
66 int num_retune_mobile_texts;
67 const char **retune_mobile_texts;
68 int retune_mobile_cfg;
69 struct soc_enum retune_mobile_enum;
70
71 /* FLL setup */
72 int fll_src;
73 int fll_fref;
74 int fll_fout;
75
76 /* Clocking configuration */
77 unsigned int mclk_rate;
78 int sysclk_src;
79 unsigned int sysclk_rate;
80
81 int tdm_width;
82 int tdm_slots;
83 int bclk;
84 int fs;
85
86 /* DC servo configuration - cached offset values */
87 int dcs_state[WM8904_NUM_DCS_CHANNELS];
88};
89
90static const u16 wm8904_reg[WM8904_MAX_REGISTER + 1] = {
91 0x8904, /* R0 - SW Reset and ID */
92 0x0000, /* R1 - Revision */
93 0x0000, /* R2 */
94 0x0000, /* R3 */
95 0x0018, /* R4 - Bias Control 0 */
96 0x0000, /* R5 - VMID Control 0 */
97 0x0000, /* R6 - Mic Bias Control 0 */
98 0x0000, /* R7 - Mic Bias Control 1 */
99 0x0001, /* R8 - Analogue DAC 0 */
100 0x9696, /* R9 - mic Filter Control */
101 0x0001, /* R10 - Analogue ADC 0 */
102 0x0000, /* R11 */
103 0x0000, /* R12 - Power Management 0 */
104 0x0000, /* R13 */
105 0x0000, /* R14 - Power Management 2 */
106 0x0000, /* R15 - Power Management 3 */
107 0x0000, /* R16 */
108 0x0000, /* R17 */
109 0x0000, /* R18 - Power Management 6 */
110 0x0000, /* R19 */
111 0x945E, /* R20 - Clock Rates 0 */
112 0x0C05, /* R21 - Clock Rates 1 */
113 0x0006, /* R22 - Clock Rates 2 */
114 0x0000, /* R23 */
115 0x0050, /* R24 - Audio Interface 0 */
116 0x000A, /* R25 - Audio Interface 1 */
117 0x00E4, /* R26 - Audio Interface 2 */
118 0x0040, /* R27 - Audio Interface 3 */
119 0x0000, /* R28 */
120 0x0000, /* R29 */
121 0x00C0, /* R30 - DAC Digital Volume Left */
122 0x00C0, /* R31 - DAC Digital Volume Right */
123 0x0000, /* R32 - DAC Digital 0 */
124 0x0008, /* R33 - DAC Digital 1 */
125 0x0000, /* R34 */
126 0x0000, /* R35 */
127 0x00C0, /* R36 - ADC Digital Volume Left */
128 0x00C0, /* R37 - ADC Digital Volume Right */
129 0x0010, /* R38 - ADC Digital 0 */
130 0x0000, /* R39 - Digital Microphone 0 */
131 0x01AF, /* R40 - DRC 0 */
132 0x3248, /* R41 - DRC 1 */
133 0x0000, /* R42 - DRC 2 */
134 0x0000, /* R43 - DRC 3 */
135 0x0085, /* R44 - Analogue Left Input 0 */
136 0x0085, /* R45 - Analogue Right Input 0 */
137 0x0044, /* R46 - Analogue Left Input 1 */
138 0x0044, /* R47 - Analogue Right Input 1 */
139 0x0000, /* R48 */
140 0x0000, /* R49 */
141 0x0000, /* R50 */
142 0x0000, /* R51 */
143 0x0000, /* R52 */
144 0x0000, /* R53 */
145 0x0000, /* R54 */
146 0x0000, /* R55 */
147 0x0000, /* R56 */
148 0x002D, /* R57 - Analogue OUT1 Left */
149 0x002D, /* R58 - Analogue OUT1 Right */
150 0x0039, /* R59 - Analogue OUT2 Left */
151 0x0039, /* R60 - Analogue OUT2 Right */
152 0x0000, /* R61 - Analogue OUT12 ZC */
153 0x0000, /* R62 */
154 0x0000, /* R63 */
155 0x0000, /* R64 */
156 0x0000, /* R65 */
157 0x0000, /* R66 */
158 0x0000, /* R67 - DC Servo 0 */
159 0x0000, /* R68 - DC Servo 1 */
160 0xAAAA, /* R69 - DC Servo 2 */
161 0x0000, /* R70 */
162 0xAAAA, /* R71 - DC Servo 4 */
163 0xAAAA, /* R72 - DC Servo 5 */
164 0x0000, /* R73 - DC Servo 6 */
165 0x0000, /* R74 - DC Servo 7 */
166 0x0000, /* R75 - DC Servo 8 */
167 0x0000, /* R76 - DC Servo 9 */
168 0x0000, /* R77 - DC Servo Readback 0 */
169 0x0000, /* R78 */
170 0x0000, /* R79 */
171 0x0000, /* R80 */
172 0x0000, /* R81 */
173 0x0000, /* R82 */
174 0x0000, /* R83 */
175 0x0000, /* R84 */
176 0x0000, /* R85 */
177 0x0000, /* R86 */
178 0x0000, /* R87 */
179 0x0000, /* R88 */
180 0x0000, /* R89 */
181 0x0000, /* R90 - Analogue HP 0 */
182 0x0000, /* R91 */
183 0x0000, /* R92 */
184 0x0000, /* R93 */
185 0x0000, /* R94 - Analogue Lineout 0 */
186 0x0000, /* R95 */
187 0x0000, /* R96 */
188 0x0000, /* R97 */
189 0x0000, /* R98 - Charge Pump 0 */
190 0x0000, /* R99 */
191 0x0000, /* R100 */
192 0x0000, /* R101 */
193 0x0000, /* R102 */
194 0x0000, /* R103 */
195 0x0004, /* R104 - Class W 0 */
196 0x0000, /* R105 */
197 0x0000, /* R106 */
198 0x0000, /* R107 */
199 0x0000, /* R108 - Write Sequencer 0 */
200 0x0000, /* R109 - Write Sequencer 1 */
201 0x0000, /* R110 - Write Sequencer 2 */
202 0x0000, /* R111 - Write Sequencer 3 */
203 0x0000, /* R112 - Write Sequencer 4 */
204 0x0000, /* R113 */
205 0x0000, /* R114 */
206 0x0000, /* R115 */
207 0x0000, /* R116 - FLL Control 1 */
208 0x0007, /* R117 - FLL Control 2 */
209 0x0000, /* R118 - FLL Control 3 */
210 0x2EE0, /* R119 - FLL Control 4 */
211 0x0004, /* R120 - FLL Control 5 */
212 0x0014, /* R121 - GPIO Control 1 */
213 0x0010, /* R122 - GPIO Control 2 */
214 0x0010, /* R123 - GPIO Control 3 */
215 0x0000, /* R124 - GPIO Control 4 */
216 0x0000, /* R125 */
217 0x0000, /* R126 - Digital Pulls */
218 0x0000, /* R127 - Interrupt Status */
219 0xFFFF, /* R128 - Interrupt Status Mask */
220 0x0000, /* R129 - Interrupt Polarity */
221 0x0000, /* R130 - Interrupt Debounce */
222 0x0000, /* R131 */
223 0x0000, /* R132 */
224 0x0000, /* R133 */
225 0x0000, /* R134 - EQ1 */
226 0x000C, /* R135 - EQ2 */
227 0x000C, /* R136 - EQ3 */
228 0x000C, /* R137 - EQ4 */
229 0x000C, /* R138 - EQ5 */
230 0x000C, /* R139 - EQ6 */
231 0x0FCA, /* R140 - EQ7 */
232 0x0400, /* R141 - EQ8 */
233 0x00D8, /* R142 - EQ9 */
234 0x1EB5, /* R143 - EQ10 */
235 0xF145, /* R144 - EQ11 */
236 0x0B75, /* R145 - EQ12 */
237 0x01C5, /* R146 - EQ13 */
238 0x1C58, /* R147 - EQ14 */
239 0xF373, /* R148 - EQ15 */
240 0x0A54, /* R149 - EQ16 */
241 0x0558, /* R150 - EQ17 */
242 0x168E, /* R151 - EQ18 */
243 0xF829, /* R152 - EQ19 */
244 0x07AD, /* R153 - EQ20 */
245 0x1103, /* R154 - EQ21 */
246 0x0564, /* R155 - EQ22 */
247 0x0559, /* R156 - EQ23 */
248 0x4000, /* R157 - EQ24 */
249 0x0000, /* R158 */
250 0x0000, /* R159 */
251 0x0000, /* R160 */
252 0x0000, /* R161 - Control Interface Test 1 */
253 0x0000, /* R162 */
254 0x0000, /* R163 */
255 0x0000, /* R164 */
256 0x0000, /* R165 */
257 0x0000, /* R166 */
258 0x0000, /* R167 */
259 0x0000, /* R168 */
260 0x0000, /* R169 */
261 0x0000, /* R170 */
262 0x0000, /* R171 */
263 0x0000, /* R172 */
264 0x0000, /* R173 */
265 0x0000, /* R174 */
266 0x0000, /* R175 */
267 0x0000, /* R176 */
268 0x0000, /* R177 */
269 0x0000, /* R178 */
270 0x0000, /* R179 */
271 0x0000, /* R180 */
272 0x0000, /* R181 */
273 0x0000, /* R182 */
274 0x0000, /* R183 */
275 0x0000, /* R184 */
276 0x0000, /* R185 */
277 0x0000, /* R186 */
278 0x0000, /* R187 */
279 0x0000, /* R188 */
280 0x0000, /* R189 */
281 0x0000, /* R190 */
282 0x0000, /* R191 */
283 0x0000, /* R192 */
284 0x0000, /* R193 */
285 0x0000, /* R194 */
286 0x0000, /* R195 */
287 0x0000, /* R196 */
288 0x0000, /* R197 */
289 0x0000, /* R198 */
290 0x0000, /* R199 */
291 0x0000, /* R200 */
292 0x0000, /* R201 */
293 0x0000, /* R202 */
294 0x0000, /* R203 */
295 0x0000, /* R204 - Analogue Output Bias 0 */
296 0x0000, /* R205 */
297 0x0000, /* R206 */
298 0x0000, /* R207 */
299 0x0000, /* R208 */
300 0x0000, /* R209 */
301 0x0000, /* R210 */
302 0x0000, /* R211 */
303 0x0000, /* R212 */
304 0x0000, /* R213 */
305 0x0000, /* R214 */
306 0x0000, /* R215 */
307 0x0000, /* R216 */
308 0x0000, /* R217 */
309 0x0000, /* R218 */
310 0x0000, /* R219 */
311 0x0000, /* R220 */
312 0x0000, /* R221 */
313 0x0000, /* R222 */
314 0x0000, /* R223 */
315 0x0000, /* R224 */
316 0x0000, /* R225 */
317 0x0000, /* R226 */
318 0x0000, /* R227 */
319 0x0000, /* R228 */
320 0x0000, /* R229 */
321 0x0000, /* R230 */
322 0x0000, /* R231 */
323 0x0000, /* R232 */
324 0x0000, /* R233 */
325 0x0000, /* R234 */
326 0x0000, /* R235 */
327 0x0000, /* R236 */
328 0x0000, /* R237 */
329 0x0000, /* R238 */
330 0x0000, /* R239 */
331 0x0000, /* R240 */
332 0x0000, /* R241 */
333 0x0000, /* R242 */
334 0x0000, /* R243 */
335 0x0000, /* R244 */
336 0x0000, /* R245 */
337 0x0000, /* R246 */
338 0x0000, /* R247 - FLL NCO Test 0 */
339 0x0019, /* R248 - FLL NCO Test 1 */
340};
341
342static struct {
343 int readable;
344 int writable;
345 int vol;
346} wm8904_access[] = {
347 { 0xFFFF, 0xFFFF, 1 }, /* R0 - SW Reset and ID */
348 { 0x0000, 0x0000, 0 }, /* R1 - Revision */
349 { 0x0000, 0x0000, 0 }, /* R2 */
350 { 0x0000, 0x0000, 0 }, /* R3 */
351 { 0x001F, 0x001F, 0 }, /* R4 - Bias Control 0 */
352 { 0x0047, 0x0047, 0 }, /* R5 - VMID Control 0 */
353 { 0x007F, 0x007F, 0 }, /* R6 - Mic Bias Control 0 */
354 { 0xC007, 0xC007, 0 }, /* R7 - Mic Bias Control 1 */
355 { 0x001E, 0x001E, 0 }, /* R8 - Analogue DAC 0 */
356 { 0xFFFF, 0xFFFF, 0 }, /* R9 - mic Filter Control */
357 { 0x0001, 0x0001, 0 }, /* R10 - Analogue ADC 0 */
358 { 0x0000, 0x0000, 0 }, /* R11 */
359 { 0x0003, 0x0003, 0 }, /* R12 - Power Management 0 */
360 { 0x0000, 0x0000, 0 }, /* R13 */
361 { 0x0003, 0x0003, 0 }, /* R14 - Power Management 2 */
362 { 0x0003, 0x0003, 0 }, /* R15 - Power Management 3 */
363 { 0x0000, 0x0000, 0 }, /* R16 */
364 { 0x0000, 0x0000, 0 }, /* R17 */
365 { 0x000F, 0x000F, 0 }, /* R18 - Power Management 6 */
366 { 0x0000, 0x0000, 0 }, /* R19 */
367 { 0x7001, 0x7001, 0 }, /* R20 - Clock Rates 0 */
368 { 0x3C07, 0x3C07, 0 }, /* R21 - Clock Rates 1 */
369 { 0xD00F, 0xD00F, 0 }, /* R22 - Clock Rates 2 */
370 { 0x0000, 0x0000, 0 }, /* R23 */
371 { 0x1FFF, 0x1FFF, 0 }, /* R24 - Audio Interface 0 */
372 { 0x3DDF, 0x3DDF, 0 }, /* R25 - Audio Interface 1 */
373 { 0x0F1F, 0x0F1F, 0 }, /* R26 - Audio Interface 2 */
374 { 0x0FFF, 0x0FFF, 0 }, /* R27 - Audio Interface 3 */
375 { 0x0000, 0x0000, 0 }, /* R28 */
376 { 0x0000, 0x0000, 0 }, /* R29 */
377 { 0x00FF, 0x01FF, 0 }, /* R30 - DAC Digital Volume Left */
378 { 0x00FF, 0x01FF, 0 }, /* R31 - DAC Digital Volume Right */
379 { 0x0FFF, 0x0FFF, 0 }, /* R32 - DAC Digital 0 */
380 { 0x1E4E, 0x1E4E, 0 }, /* R33 - DAC Digital 1 */
381 { 0x0000, 0x0000, 0 }, /* R34 */
382 { 0x0000, 0x0000, 0 }, /* R35 */
383 { 0x00FF, 0x01FF, 0 }, /* R36 - ADC Digital Volume Left */
384 { 0x00FF, 0x01FF, 0 }, /* R37 - ADC Digital Volume Right */
385 { 0x0073, 0x0073, 0 }, /* R38 - ADC Digital 0 */
386 { 0x1800, 0x1800, 0 }, /* R39 - Digital Microphone 0 */
387 { 0xDFEF, 0xDFEF, 0 }, /* R40 - DRC 0 */
388 { 0xFFFF, 0xFFFF, 0 }, /* R41 - DRC 1 */
389 { 0x003F, 0x003F, 0 }, /* R42 - DRC 2 */
390 { 0x07FF, 0x07FF, 0 }, /* R43 - DRC 3 */
391 { 0x009F, 0x009F, 0 }, /* R44 - Analogue Left Input 0 */
392 { 0x009F, 0x009F, 0 }, /* R45 - Analogue Right Input 0 */
393 { 0x007F, 0x007F, 0 }, /* R46 - Analogue Left Input 1 */
394 { 0x007F, 0x007F, 0 }, /* R47 - Analogue Right Input 1 */
395 { 0x0000, 0x0000, 0 }, /* R48 */
396 { 0x0000, 0x0000, 0 }, /* R49 */
397 { 0x0000, 0x0000, 0 }, /* R50 */
398 { 0x0000, 0x0000, 0 }, /* R51 */
399 { 0x0000, 0x0000, 0 }, /* R52 */
400 { 0x0000, 0x0000, 0 }, /* R53 */
401 { 0x0000, 0x0000, 0 }, /* R54 */
402 { 0x0000, 0x0000, 0 }, /* R55 */
403 { 0x0000, 0x0000, 0 }, /* R56 */
404 { 0x017F, 0x01FF, 0 }, /* R57 - Analogue OUT1 Left */
405 { 0x017F, 0x01FF, 0 }, /* R58 - Analogue OUT1 Right */
406 { 0x017F, 0x01FF, 0 }, /* R59 - Analogue OUT2 Left */
407 { 0x017F, 0x01FF, 0 }, /* R60 - Analogue OUT2 Right */
408 { 0x000F, 0x000F, 0 }, /* R61 - Analogue OUT12 ZC */
409 { 0x0000, 0x0000, 0 }, /* R62 */
410 { 0x0000, 0x0000, 0 }, /* R63 */
411 { 0x0000, 0x0000, 0 }, /* R64 */
412 { 0x0000, 0x0000, 0 }, /* R65 */
413 { 0x0000, 0x0000, 0 }, /* R66 */
414 { 0x000F, 0x000F, 0 }, /* R67 - DC Servo 0 */
415 { 0xFFFF, 0xFFFF, 1 }, /* R68 - DC Servo 1 */
416 { 0x0F0F, 0x0F0F, 0 }, /* R69 - DC Servo 2 */
417 { 0x0000, 0x0000, 0 }, /* R70 */
418 { 0x007F, 0x007F, 0 }, /* R71 - DC Servo 4 */
419 { 0x007F, 0x007F, 0 }, /* R72 - DC Servo 5 */
420 { 0x00FF, 0x00FF, 1 }, /* R73 - DC Servo 6 */
421 { 0x00FF, 0x00FF, 1 }, /* R74 - DC Servo 7 */
422 { 0x00FF, 0x00FF, 1 }, /* R75 - DC Servo 8 */
423 { 0x00FF, 0x00FF, 1 }, /* R76 - DC Servo 9 */
424 { 0x0FFF, 0x0000, 1 }, /* R77 - DC Servo Readback 0 */
425 { 0x0000, 0x0000, 0 }, /* R78 */
426 { 0x0000, 0x0000, 0 }, /* R79 */
427 { 0x0000, 0x0000, 0 }, /* R80 */
428 { 0x0000, 0x0000, 0 }, /* R81 */
429 { 0x0000, 0x0000, 0 }, /* R82 */
430 { 0x0000, 0x0000, 0 }, /* R83 */
431 { 0x0000, 0x0000, 0 }, /* R84 */
432 { 0x0000, 0x0000, 0 }, /* R85 */
433 { 0x0000, 0x0000, 0 }, /* R86 */
434 { 0x0000, 0x0000, 0 }, /* R87 */
435 { 0x0000, 0x0000, 0 }, /* R88 */
436 { 0x0000, 0x0000, 0 }, /* R89 */
437 { 0x00FF, 0x00FF, 0 }, /* R90 - Analogue HP 0 */
438 { 0x0000, 0x0000, 0 }, /* R91 */
439 { 0x0000, 0x0000, 0 }, /* R92 */
440 { 0x0000, 0x0000, 0 }, /* R93 */
441 { 0x00FF, 0x00FF, 0 }, /* R94 - Analogue Lineout 0 */
442 { 0x0000, 0x0000, 0 }, /* R95 */
443 { 0x0000, 0x0000, 0 }, /* R96 */
444 { 0x0000, 0x0000, 0 }, /* R97 */
445 { 0x0001, 0x0001, 0 }, /* R98 - Charge Pump 0 */
446 { 0x0000, 0x0000, 0 }, /* R99 */
447 { 0x0000, 0x0000, 0 }, /* R100 */
448 { 0x0000, 0x0000, 0 }, /* R101 */
449 { 0x0000, 0x0000, 0 }, /* R102 */
450 { 0x0000, 0x0000, 0 }, /* R103 */
451 { 0x0001, 0x0001, 0 }, /* R104 - Class W 0 */
452 { 0x0000, 0x0000, 0 }, /* R105 */
453 { 0x0000, 0x0000, 0 }, /* R106 */
454 { 0x0000, 0x0000, 0 }, /* R107 */
455 { 0x011F, 0x011F, 0 }, /* R108 - Write Sequencer 0 */
456 { 0x7FFF, 0x7FFF, 0 }, /* R109 - Write Sequencer 1 */
457 { 0x4FFF, 0x4FFF, 0 }, /* R110 - Write Sequencer 2 */
458 { 0x003F, 0x033F, 0 }, /* R111 - Write Sequencer 3 */
459 { 0x03F1, 0x0000, 0 }, /* R112 - Write Sequencer 4 */
460 { 0x0000, 0x0000, 0 }, /* R113 */
461 { 0x0000, 0x0000, 0 }, /* R114 */
462 { 0x0000, 0x0000, 0 }, /* R115 */
463 { 0x0007, 0x0007, 0 }, /* R116 - FLL Control 1 */
464 { 0x3F77, 0x3F77, 0 }, /* R117 - FLL Control 2 */
465 { 0xFFFF, 0xFFFF, 0 }, /* R118 - FLL Control 3 */
466 { 0x7FEF, 0x7FEF, 0 }, /* R119 - FLL Control 4 */
467 { 0x001B, 0x001B, 0 }, /* R120 - FLL Control 5 */
468 { 0x003F, 0x003F, 0 }, /* R121 - GPIO Control 1 */
469 { 0x003F, 0x003F, 0 }, /* R122 - GPIO Control 2 */
470 { 0x003F, 0x003F, 0 }, /* R123 - GPIO Control 3 */
471 { 0x038F, 0x038F, 0 }, /* R124 - GPIO Control 4 */
472 { 0x0000, 0x0000, 0 }, /* R125 */
473 { 0x00FF, 0x00FF, 0 }, /* R126 - Digital Pulls */
474 { 0x07FF, 0x03FF, 1 }, /* R127 - Interrupt Status */
475 { 0x03FF, 0x03FF, 0 }, /* R128 - Interrupt Status Mask */
476 { 0x03FF, 0x03FF, 0 }, /* R129 - Interrupt Polarity */
477 { 0x03FF, 0x03FF, 0 }, /* R130 - Interrupt Debounce */
478 { 0x0000, 0x0000, 0 }, /* R131 */
479 { 0x0000, 0x0000, 0 }, /* R132 */
480 { 0x0000, 0x0000, 0 }, /* R133 */
481 { 0x0001, 0x0001, 0 }, /* R134 - EQ1 */
482 { 0x001F, 0x001F, 0 }, /* R135 - EQ2 */
483 { 0x001F, 0x001F, 0 }, /* R136 - EQ3 */
484 { 0x001F, 0x001F, 0 }, /* R137 - EQ4 */
485 { 0x001F, 0x001F, 0 }, /* R138 - EQ5 */
486 { 0x001F, 0x001F, 0 }, /* R139 - EQ6 */
487 { 0xFFFF, 0xFFFF, 0 }, /* R140 - EQ7 */
488 { 0xFFFF, 0xFFFF, 0 }, /* R141 - EQ8 */
489 { 0xFFFF, 0xFFFF, 0 }, /* R142 - EQ9 */
490 { 0xFFFF, 0xFFFF, 0 }, /* R143 - EQ10 */
491 { 0xFFFF, 0xFFFF, 0 }, /* R144 - EQ11 */
492 { 0xFFFF, 0xFFFF, 0 }, /* R145 - EQ12 */
493 { 0xFFFF, 0xFFFF, 0 }, /* R146 - EQ13 */
494 { 0xFFFF, 0xFFFF, 0 }, /* R147 - EQ14 */
495 { 0xFFFF, 0xFFFF, 0 }, /* R148 - EQ15 */
496 { 0xFFFF, 0xFFFF, 0 }, /* R149 - EQ16 */
497 { 0xFFFF, 0xFFFF, 0 }, /* R150 - EQ17 */
498 { 0xFFFF, 0xFFFF, 0 }, /* R151wm8523_dai - EQ18 */
499 { 0xFFFF, 0xFFFF, 0 }, /* R152 - EQ19 */
500 { 0xFFFF, 0xFFFF, 0 }, /* R153 - EQ20 */
501 { 0xFFFF, 0xFFFF, 0 }, /* R154 - EQ21 */
502 { 0xFFFF, 0xFFFF, 0 }, /* R155 - EQ22 */
503 { 0xFFFF, 0xFFFF, 0 }, /* R156 - EQ23 */
504 { 0xFFFF, 0xFFFF, 0 }, /* R157 - EQ24 */
505 { 0x0000, 0x0000, 0 }, /* R158 */
506 { 0x0000, 0x0000, 0 }, /* R159 */
507 { 0x0000, 0x0000, 0 }, /* R160 */
508 { 0x0002, 0x0002, 0 }, /* R161 - Control Interface Test 1 */
509 { 0x0000, 0x0000, 0 }, /* R162 */
510 { 0x0000, 0x0000, 0 }, /* R163 */
511 { 0x0000, 0x0000, 0 }, /* R164 */
512 { 0x0000, 0x0000, 0 }, /* R165 */
513 { 0x0000, 0x0000, 0 }, /* R166 */
514 { 0x0000, 0x0000, 0 }, /* R167 */
515 { 0x0000, 0x0000, 0 }, /* R168 */
516 { 0x0000, 0x0000, 0 }, /* R169 */
517 { 0x0000, 0x0000, 0 }, /* R170 */
518 { 0x0000, 0x0000, 0 }, /* R171 */
519 { 0x0000, 0x0000, 0 }, /* R172 */
520 { 0x0000, 0x0000, 0 }, /* R173 */
521 { 0x0000, 0x0000, 0 }, /* R174 */
522 { 0x0000, 0x0000, 0 }, /* R175 */
523 { 0x0000, 0x0000, 0 }, /* R176 */
524 { 0x0000, 0x0000, 0 }, /* R177 */
525 { 0x0000, 0x0000, 0 }, /* R178 */
526 { 0x0000, 0x0000, 0 }, /* R179 */
527 { 0x0000, 0x0000, 0 }, /* R180 */
528 { 0x0000, 0x0000, 0 }, /* R181 */
529 { 0x0000, 0x0000, 0 }, /* R182 */
530 { 0x0000, 0x0000, 0 }, /* R183 */
531 { 0x0000, 0x0000, 0 }, /* R184 */
532 { 0x0000, 0x0000, 0 }, /* R185 */
533 { 0x0000, 0x0000, 0 }, /* R186 */
534 { 0x0000, 0x0000, 0 }, /* R187 */
535 { 0x0000, 0x0000, 0 }, /* R188 */
536 { 0x0000, 0x0000, 0 }, /* R189 */
537 { 0x0000, 0x0000, 0 }, /* R190 */
538 { 0x0000, 0x0000, 0 }, /* R191 */
539 { 0x0000, 0x0000, 0 }, /* R192 */
540 { 0x0000, 0x0000, 0 }, /* R193 */
541 { 0x0000, 0x0000, 0 }, /* R194 */
542 { 0x0000, 0x0000, 0 }, /* R195 */
543 { 0x0000, 0x0000, 0 }, /* R196 */
544 { 0x0000, 0x0000, 0 }, /* R197 */
545 { 0x0000, 0x0000, 0 }, /* R198 */
546 { 0x0000, 0x0000, 0 }, /* R199 */
547 { 0x0000, 0x0000, 0 }, /* R200 */
548 { 0x0000, 0x0000, 0 }, /* R201 */
549 { 0x0000, 0x0000, 0 }, /* R202 */
550 { 0x0000, 0x0000, 0 }, /* R203 */
551 { 0x0070, 0x0070, 0 }, /* R204 - Analogue Output Bias 0 */
552 { 0x0000, 0x0000, 0 }, /* R205 */
553 { 0x0000, 0x0000, 0 }, /* R206 */
554 { 0x0000, 0x0000, 0 }, /* R207 */
555 { 0x0000, 0x0000, 0 }, /* R208 */
556 { 0x0000, 0x0000, 0 }, /* R209 */
557 { 0x0000, 0x0000, 0 }, /* R210 */
558 { 0x0000, 0x0000, 0 }, /* R211 */
559 { 0x0000, 0x0000, 0 }, /* R212 */
560 { 0x0000, 0x0000, 0 }, /* R213 */
561 { 0x0000, 0x0000, 0 }, /* R214 */
562 { 0x0000, 0x0000, 0 }, /* R215 */
563 { 0x0000, 0x0000, 0 }, /* R216 */
564 { 0x0000, 0x0000, 0 }, /* R217 */
565 { 0x0000, 0x0000, 0 }, /* R218 */
566 { 0x0000, 0x0000, 0 }, /* R219 */
567 { 0x0000, 0x0000, 0 }, /* R220 */
568 { 0x0000, 0x0000, 0 }, /* R221 */
569 { 0x0000, 0x0000, 0 }, /* R222 */
570 { 0x0000, 0x0000, 0 }, /* R223 */
571 { 0x0000, 0x0000, 0 }, /* R224 */
572 { 0x0000, 0x0000, 0 }, /* R225 */
573 { 0x0000, 0x0000, 0 }, /* R226 */
574 { 0x0000, 0x0000, 0 }, /* R227 */
575 { 0x0000, 0x0000, 0 }, /* R228 */
576 { 0x0000, 0x0000, 0 }, /* R229 */
577 { 0x0000, 0x0000, 0 }, /* R230 */
578 { 0x0000, 0x0000, 0 }, /* R231 */
579 { 0x0000, 0x0000, 0 }, /* R232 */
580 { 0x0000, 0x0000, 0 }, /* R233 */
581 { 0x0000, 0x0000, 0 }, /* R234 */
582 { 0x0000, 0x0000, 0 }, /* R235 */
583 { 0x0000, 0x0000, 0 }, /* R236 */
584 { 0x0000, 0x0000, 0 }, /* R237 */
585 { 0x0000, 0x0000, 0 }, /* R238 */
586 { 0x0000, 0x0000, 0 }, /* R239 */
587 { 0x0000, 0x0000, 0 }, /* R240 */
588 { 0x0000, 0x0000, 0 }, /* R241 */
589 { 0x0000, 0x0000, 0 }, /* R242 */
590 { 0x0000, 0x0000, 0 }, /* R243 */
591 { 0x0000, 0x0000, 0 }, /* R244 */
592 { 0x0000, 0x0000, 0 }, /* R245 */
593 { 0x0000, 0x0000, 0 }, /* R246 */
594 { 0x0001, 0x0001, 0 }, /* R247 - FLL NCO Test 0 */
595 { 0x003F, 0x003F, 0 }, /* R248 - FLL NCO Test 1 */
596};
597
d4754ec9 598static int wm8904_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
a91eb199
MB		 599{
600 return wm8904_access[reg].vol;
601}
602
603static int wm8904_reset(struct snd_soc_codec *codec)
604{
605 return snd_soc_write(codec, WM8904_SW_RESET_AND_ID, 0);
606}
607
608static int wm8904_configure_clocking(struct snd_soc_codec *codec)
609{
b2c812e2 610 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 611 unsigned int clock0, clock2, rate;
612
613 /* Gate the clock while we're updating to avoid misclocking */
614 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
615 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
616 WM8904_SYSCLK_SRC, 0);
617
618 /* This should be done on init() for bypass paths */
619 switch (wm8904->sysclk_src) {
620 case WM8904_CLK_MCLK:
621 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
622
623 clock2 &= ~WM8904_SYSCLK_SRC;
624 rate = wm8904->mclk_rate;
625
626 /* Ensure the FLL is stopped */
627 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
628 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
629 break;
630
631 case WM8904_CLK_FLL:
632 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
633 wm8904->fll_fout);
634
635 clock2 |= WM8904_SYSCLK_SRC;
636 rate = wm8904->fll_fout;
637 break;
638
639 default:
640 dev_err(codec->dev, "System clock not configured\n");
641 return -EINVAL;
642 }
643
644 /* SYSCLK shouldn't be over 13.5MHz */
645 if (rate > 13500000) {
646 clock0 = WM8904_MCLK_DIV;
647 wm8904->sysclk_rate = rate / 2;
648 } else {
649 clock0 = 0;
650 wm8904->sysclk_rate = rate;
651 }
652
653 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
654 clock0);
655
656 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
657 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
658
659 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
660
661 return 0;
662}
663
664static void wm8904_set_drc(struct snd_soc_codec *codec)
665{
b2c812e2 666 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 667 struct wm8904_pdata *pdata = wm8904->pdata;
668 int save, i;
669
670 /* Save any enables; the configuration should clear them. */
671 save = snd_soc_read(codec, WM8904_DRC_0);
672
673 for (i = 0; i < WM8904_DRC_REGS; i++)
674 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
675 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
676
677 /* Reenable the DRC */
678 snd_soc_update_bits(codec, WM8904_DRC_0,
679 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
680}
681
682static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
683 struct snd_ctl_elem_value *ucontrol)
684{
685 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 686 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 687 struct wm8904_pdata *pdata = wm8904->pdata;
688 int value = ucontrol->value.integer.value[0];
689
690 if (value >= pdata->num_drc_cfgs)
691 return -EINVAL;
692
693 wm8904->drc_cfg = value;
694
695 wm8904_set_drc(codec);
696
697 return 0;
698}
699
700static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
701 struct snd_ctl_elem_value *ucontrol)
702{
703 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 704 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 705
706 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
707
708 return 0;
709}
710
711static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
712{
b2c812e2 713 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 714 struct wm8904_pdata *pdata = wm8904->pdata;
715 int best, best_val, save, i, cfg;
716
717 if (!pdata || !wm8904->num_retune_mobile_texts)
718 return;
719
720 /* Find the version of the currently selected configuration
721 * with the nearest sample rate. */
722 cfg = wm8904->retune_mobile_cfg;
723 best = 0;
724 best_val = INT_MAX;
725 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
726 if (strcmp(pdata->retune_mobile_cfgs[i].name,
727 wm8904->retune_mobile_texts[cfg]) == 0 &&
728 abs(pdata->retune_mobile_cfgs[i].rate
729 - wm8904->fs) < best_val) {
730 best = i;
731 best_val = abs(pdata->retune_mobile_cfgs[i].rate
732 - wm8904->fs);
733 }
734 }
735
736 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
737 pdata->retune_mobile_cfgs[best].name,
738 pdata->retune_mobile_cfgs[best].rate,
739 wm8904->fs);
740
741 /* The EQ will be disabled while reconfiguring it, remember the
742 * current configuration.
743 */
744 save = snd_soc_read(codec, WM8904_EQ1);
745
746 for (i = 0; i < WM8904_EQ_REGS; i++)
747 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
748 pdata->retune_mobile_cfgs[best].regs[i]);
749
750 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
751}
752
753static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
754 struct snd_ctl_elem_value *ucontrol)
755{
756 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 757 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 758 struct wm8904_pdata *pdata = wm8904->pdata;
759 int value = ucontrol->value.integer.value[0];
760
761 if (value >= pdata->num_retune_mobile_cfgs)
762 return -EINVAL;
763
764 wm8904->retune_mobile_cfg = value;
765
766 wm8904_set_retune_mobile(codec);
767
768 return 0;
769}
770
771static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
772 struct snd_ctl_elem_value *ucontrol)
773{
774 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 775 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 776
777 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
778
779 return 0;
780}
781
782static int deemph_settings[] = { 0, 32000, 44100, 48000 };
783
784static int wm8904_set_deemph(struct snd_soc_codec *codec)
785{
b2c812e2 786 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 787 int val, i, best;
788
789 /* If we're using deemphasis select the nearest available sample
790 * rate.
791 */
792 if (wm8904->deemph) {
793 best = 1;
794 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
795 if (abs(deemph_settings[i] - wm8904->fs) <
796 abs(deemph_settings[best] - wm8904->fs))
797 best = i;
798 }
799
800 val = best << WM8904_DEEMPH_SHIFT;
801 } else {
802 val = 0;
803 }
804
805 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
806
807 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
808 WM8904_DEEMPH_MASK, val);
809}
810
811static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
812 struct snd_ctl_elem_value *ucontrol)
813{
814 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 815 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199 816
3f343f85
DA		 817 ucontrol->value.enumerated.item[0] = wm8904->deemph;
818 return 0;
a91eb199
MB		 819}
820
821static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
822 struct snd_ctl_elem_value *ucontrol)
823{
824 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 825 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 826 int deemph = ucontrol->value.enumerated.item[0];
827
828 if (deemph > 1)
829 return -EINVAL;
830
831 wm8904->deemph = deemph;
832
833 return wm8904_set_deemph(codec);
834}
835
836static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
837static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
838static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
839static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
840static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
841
842static const char *input_mode_text[] = {
843 "Single-Ended", "Differential Line", "Differential Mic"
844};
845
846static const struct soc_enum lin_mode =
847 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
848
849static const struct soc_enum rin_mode =
850 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
851
852static const char *hpf_mode_text[] = {
853 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
854};
855
856static const struct soc_enum hpf_mode =
857 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
858
859static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
860SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
861 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
862
863SOC_ENUM("Left Caputure Mode", lin_mode),
864SOC_ENUM("Right Capture Mode", rin_mode),
865
866/* No TLV since it depends on mode */
867SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
868 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
869SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
870 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 0),
871
872SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
873SOC_ENUM("High Pass Filter Mode", hpf_mode),
874
875SOC_SINGLE("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0),
876};
877
878static const char *drc_path_text[] = {
879 "ADC", "DAC"
880};
881
882static const struct soc_enum drc_path =
883 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
884
885static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
886SOC_SINGLE_TLV("Digital Playback Boost Volume",
887 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
888SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
889 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
890
891SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
892 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
893SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
894 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
895SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
896 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
897
898SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
899 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
900SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
901 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
902SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
903 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
904
905SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
906SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
907SOC_ENUM("DRC Path", drc_path),
908SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
909SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
910 wm8904_get_deemph, wm8904_put_deemph),
911};
912
913static const struct snd_kcontrol_new wm8904_snd_controls[] = {
914SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
915 sidetone_tlv),
916};
917
918static const struct snd_kcontrol_new wm8904_eq_controls[] = {
919SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
920SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
921SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
922SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
923SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
924};
925
926static int cp_event(struct snd_soc_dapm_widget *w,
927 struct snd_kcontrol *kcontrol, int event)
928{
929 BUG_ON(event != SND_SOC_DAPM_POST_PMU);
930
931 /* Maximum startup time */
932 udelay(500);
933
934 return 0;
935}
936
937static int sysclk_event(struct snd_soc_dapm_widget *w,
938 struct snd_kcontrol *kcontrol, int event)
939{
940 struct snd_soc_codec *codec = w->codec;
b2c812e2 941 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 942
943 switch (event) {
944 case SND_SOC_DAPM_PRE_PMU:
945 /* If we're using the FLL then we only start it when
946 * required; we assume that the configuration has been
947 * done previously and all we need to do is kick it
948 * off.
949 */
950 switch (wm8904->sysclk_src) {
951 case WM8904_CLK_FLL:
952 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
953 WM8904_FLL_OSC_ENA,
954 WM8904_FLL_OSC_ENA);
955
956 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
957 WM8904_FLL_ENA,
958 WM8904_FLL_ENA);
959 break;
960
961 default:
962 break;
963 }
964 break;
965
966 case SND_SOC_DAPM_POST_PMD:
967 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
968 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
969 break;
970 }
971
972 return 0;
973}
974
975static int out_pga_event(struct snd_soc_dapm_widget *w,
976 struct snd_kcontrol *kcontrol, int event)
977{
978 struct snd_soc_codec *codec = w->codec;
b2c812e2 979 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 980 int reg, val;
981 int dcs_mask;
982 int dcs_l, dcs_r;
983 int dcs_l_reg, dcs_r_reg;
984 int timeout;
e4bc6696 985 int pwr_reg;
a91eb199
MB		 986
987 /* This code is shared between HP and LINEOUT; we do all our
988 * power management in stereo pairs to avoid latency issues so
989 * we reuse shift to identify which rather than strcmp() the
990 * name. */
991 reg = w->shift;
992
993 switch (reg) {
994 case WM8904_ANALOGUE_HP_0:
e4bc6696 995 pwr_reg = WM8904_POWER_MANAGEMENT_2;
a91eb199
MB		 996 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
997 dcs_r_reg = WM8904_DC_SERVO_8;
998 dcs_l_reg = WM8904_DC_SERVO_9;
999 dcs_l = 0;
1000 dcs_r = 1;
1001 break;
1002 case WM8904_ANALOGUE_LINEOUT_0:
e4bc6696 1003 pwr_reg = WM8904_POWER_MANAGEMENT_3;
a91eb199
MB		 1004 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
1005 dcs_r_reg = WM8904_DC_SERVO_6;
1006 dcs_l_reg = WM8904_DC_SERVO_7;
1007 dcs_l = 2;
1008 dcs_r = 3;
1009 break;
1010 default:
1011 BUG();
1012 return -EINVAL;
1013 }
1014
1015 switch (event) {
e4bc6696
MB		 1016 case SND_SOC_DAPM_PRE_PMU:
1017 /* Power on the PGAs */
1018 snd_soc_update_bits(codec, pwr_reg,
1019 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
1020 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
1021
a91eb199
MB		 1022 /* Power on the amplifier */
1023 snd_soc_update_bits(codec, reg,
1024 WM8904_HPL_ENA | WM8904_HPR_ENA,
1025 WM8904_HPL_ENA | WM8904_HPR_ENA);
1026
e4bc6696 1027
a91eb199
MB		 1028 /* Enable the first stage */
1029 snd_soc_update_bits(codec, reg,
1030 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
1031 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
1032
1033 /* Power up the DC servo */
1034 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
1035 dcs_mask, dcs_mask);
1036
1037 /* Either calibrate the DC servo or restore cached state
1038 * if we have that.
1039 */
1040 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
1041 dev_dbg(codec->dev, "Restoring DC servo state\n");
1042
1043 snd_soc_write(codec, dcs_l_reg,
1044 wm8904->dcs_state[dcs_l]);
1045 snd_soc_write(codec, dcs_r_reg,
1046 wm8904->dcs_state[dcs_r]);
1047
1048 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
1049
1050 timeout = 20;
1051 } else {
1052 dev_dbg(codec->dev, "Calibrating DC servo\n");
1053
1054 snd_soc_write(codec, WM8904_DC_SERVO_1,
1055 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
1056
1057 timeout = 500;
1058 }
1059
1060 /* Wait for DC servo to complete */
1061 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
1062 do {
1063 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
1064 if ((val & dcs_mask) == dcs_mask)
1065 break;
1066
1067 msleep(1);
1068 } while (--timeout);
1069
1070 if ((val & dcs_mask) != dcs_mask)
1071 dev_warn(codec->dev, "DC servo timed out\n");
1072 else
1073 dev_dbg(codec->dev, "DC servo ready\n");
1074
1075 /* Enable the output stage */
1076 snd_soc_update_bits(codec, reg,
1077 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
1078 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
e4bc6696 1079 break;
a91eb199 1080
e4bc6696 1081 case SND_SOC_DAPM_POST_PMU:
a91eb199
MB		 1082 /* Unshort the output itself */
1083 snd_soc_update_bits(codec, reg,
1084 WM8904_HPL_RMV_SHORT |
1085 WM8904_HPR_RMV_SHORT,
1086 WM8904_HPL_RMV_SHORT |
1087 WM8904_HPR_RMV_SHORT);
1088
1089 break;
1090
1091 case SND_SOC_DAPM_PRE_PMD:
1092 /* Short the output */
1093 snd_soc_update_bits(codec, reg,
1094 WM8904_HPL_RMV_SHORT |
1095 WM8904_HPR_RMV_SHORT, 0);
e4bc6696 1096 break;
a91eb199 1097
e4bc6696 1098 case SND_SOC_DAPM_POST_PMD:
a91eb199
MB		 1099 /* Cache the DC servo configuration; this will be
1100 * invalidated if we change the configuration. */
1101 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
1102 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
1103
1104 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
1105 dcs_mask, 0);
1106
1107 /* Disable the amplifier input and output stages */
1108 snd_soc_update_bits(codec, reg,
1109 WM8904_HPL_ENA | WM8904_HPR_ENA |
1110 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
1111 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
1112 0);
e4bc6696
MB		 1113
1114 /* PGAs too */
1115 snd_soc_update_bits(codec, pwr_reg,
1116 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
1117 0);
a91eb199
MB		 1118 break;
1119 }
1120
1121 return 0;
1122}
1123
1124static const char *lin_text[] = {
1125 "IN1L", "IN2L", "IN3L"
1126};
1127
1128static const struct soc_enum lin_enum =
1129 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
1130
1131static const struct snd_kcontrol_new lin_mux =
1132 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
1133
1134static const struct soc_enum lin_inv_enum =
1135 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
1136
1137static const struct snd_kcontrol_new lin_inv_mux =
1138 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
1139
1140static const char *rin_text[] = {
1141 "IN1R", "IN2R", "IN3R"
1142};
1143
1144static const struct soc_enum rin_enum =
1145 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
1146
1147static const struct snd_kcontrol_new rin_mux =
1148 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
1149
1150static const struct soc_enum rin_inv_enum =
1151 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
1152
1153static const struct snd_kcontrol_new rin_inv_mux =
1154 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
1155
1156static const char *aif_text[] = {
1157 "Left", "Right"
1158};
1159
1160static const struct soc_enum aifoutl_enum =
1161 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
1162
1163static const struct snd_kcontrol_new aifoutl_mux =
1164 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
1165
1166static const struct soc_enum aifoutr_enum =
1167 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
1168
1169static const struct snd_kcontrol_new aifoutr_mux =
1170 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
1171
1172static const struct soc_enum aifinl_enum =
1173 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
1174
1175static const struct snd_kcontrol_new aifinl_mux =
1176 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
1177
1178static const struct soc_enum aifinr_enum =
1179 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
1180
1181static const struct snd_kcontrol_new aifinr_mux =
1182 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
1183
1184static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
1185SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
1186 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1187SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
1188SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
1189};
1190
1191static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
1192SND_SOC_DAPM_INPUT("IN1L"),
1193SND_SOC_DAPM_INPUT("IN1R"),
1194SND_SOC_DAPM_INPUT("IN2L"),
1195SND_SOC_DAPM_INPUT("IN2R"),
1196SND_SOC_DAPM_INPUT("IN3L"),
1197SND_SOC_DAPM_INPUT("IN3R"),
1198
1199SND_SOC_DAPM_MICBIAS("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0),
1200
1201SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
1202SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1203 &lin_inv_mux),
1204SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
1205SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
1206 &rin_inv_mux),
1207
1208SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
1209 NULL, 0),
1210SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
1211 NULL, 0),
1212
1213SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
1214SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
1215
1216SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
1217SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
1218
1219SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
1220SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
1221};
1222
1223static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
1224SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
1225SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
1226
1227SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
1228SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
1229
1230SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
1231SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
1232
1233SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
1234 SND_SOC_DAPM_POST_PMU),
1235
e4bc6696
MB		 1236SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
1237SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
a91eb199 1238
e4bc6696
MB		 1239SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
1240SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
a91eb199
MB		 1241
1242SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
1243 0, NULL, 0, out_pga_event,
e4bc6696
MB		 1244 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1245 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
a91eb199
MB		 1246SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
1247 0, NULL, 0, out_pga_event,
e4bc6696
MB		 1248 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1249 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
a91eb199
MB		 1250
1251SND_SOC_DAPM_OUTPUT("HPOUTL"),
1252SND_SOC_DAPM_OUTPUT("HPOUTR"),
1253SND_SOC_DAPM_OUTPUT("LINEOUTL"),
1254SND_SOC_DAPM_OUTPUT("LINEOUTR"),
1255};
1256
1257static const char *out_mux_text[] = {
1258 "DAC", "Bypass"
1259};
1260
1261static const struct soc_enum hpl_enum =
1262 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
1263
1264static const struct snd_kcontrol_new hpl_mux =
1265 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1266
1267static const struct soc_enum hpr_enum =
1268 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
1269
1270static const struct snd_kcontrol_new hpr_mux =
1271 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1272
1273static const struct soc_enum linel_enum =
1274 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
1275
1276static const struct snd_kcontrol_new linel_mux =
1277 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1278
1279static const struct soc_enum liner_enum =
1280 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
1281
1282static const struct snd_kcontrol_new liner_mux =
1283 SOC_DAPM_ENUM("LINEL Mux", liner_enum);
1284
1285static const char *sidetone_text[] = {
1286 "None", "Left", "Right"
1287};
1288
1289static const struct soc_enum dacl_sidetone_enum =
1290 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
1291
1292static const struct snd_kcontrol_new dacl_sidetone_mux =
1293 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1294
1295static const struct soc_enum dacr_sidetone_enum =
1296 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
1297
1298static const struct snd_kcontrol_new dacr_sidetone_mux =
1299 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1300
1301static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1302SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1303SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1304SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1305
1306SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1307SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1308
1309SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1310SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1311SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1312SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1313};
1314
1315static const struct snd_soc_dapm_route core_intercon[] = {
1316 { "CLK_DSP", NULL, "SYSCLK" },
1317 { "TOCLK", NULL, "SYSCLK" },
1318};
1319
1320static const struct snd_soc_dapm_route adc_intercon[] = {
1321 { "Left Capture Mux", "IN1L", "IN1L" },
1322 { "Left Capture Mux", "IN2L", "IN2L" },
1323 { "Left Capture Mux", "IN3L", "IN3L" },
1324
1325 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1326 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1327 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1328
1329 { "Right Capture Mux", "IN1R", "IN1R" },
1330 { "Right Capture Mux", "IN2R", "IN2R" },
1331 { "Right Capture Mux", "IN3R", "IN3R" },
1332
1333 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1334 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1335 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1336
1337 { "Left Capture PGA", NULL, "Left Capture Mux" },
1338 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1339
1340 { "Right Capture PGA", NULL, "Right Capture Mux" },
1341 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1342
1343 { "AIFOUTL", "Left", "ADCL" },
1344 { "AIFOUTL", "Right", "ADCR" },
1345 { "AIFOUTR", "Left", "ADCL" },
1346 { "AIFOUTR", "Right", "ADCR" },
1347
1348 { "ADCL", NULL, "CLK_DSP" },
1349 { "ADCL", NULL, "Left Capture PGA" },
1350
1351 { "ADCR", NULL, "CLK_DSP" },
1352 { "ADCR", NULL, "Right Capture PGA" },
1353};
1354
1355static const struct snd_soc_dapm_route dac_intercon[] = {
1356 { "DACL", "Right", "AIFINR" },
1357 { "DACL", "Left", "AIFINL" },
1358 { "DACL", NULL, "CLK_DSP" },
1359
1360 { "DACR", "Right", "AIFINR" },
1361 { "DACR", "Left", "AIFINL" },
1362 { "DACR", NULL, "CLK_DSP" },
1363
1364 { "Charge pump", NULL, "SYSCLK" },
1365
1366 { "Headphone Output", NULL, "HPL PGA" },
1367 { "Headphone Output", NULL, "HPR PGA" },
1368 { "Headphone Output", NULL, "Charge pump" },
1369 { "Headphone Output", NULL, "TOCLK" },
1370
1371 { "Line Output", NULL, "LINEL PGA" },
1372 { "Line Output", NULL, "LINER PGA" },
1373 { "Line Output", NULL, "Charge pump" },
1374 { "Line Output", NULL, "TOCLK" },
1375
1376 { "HPOUTL", NULL, "Headphone Output" },
1377 { "HPOUTR", NULL, "Headphone Output" },
1378
1379 { "LINEOUTL", NULL, "Line Output" },
1380 { "LINEOUTR", NULL, "Line Output" },
1381};
1382
1383static const struct snd_soc_dapm_route wm8904_intercon[] = {
1384 { "Left Sidetone", "Left", "ADCL" },
1385 { "Left Sidetone", "Right", "ADCR" },
1386 { "DACL", NULL, "Left Sidetone" },
1387
1388 { "Right Sidetone", "Left", "ADCL" },
1389 { "Right Sidetone", "Right", "ADCR" },
1390 { "DACR", NULL, "Right Sidetone" },
1391
1392 { "Left Bypass", NULL, "Class G" },
1393 { "Left Bypass", NULL, "Left Capture PGA" },
1394
1395 { "Right Bypass", NULL, "Class G" },
1396 { "Right Bypass", NULL, "Right Capture PGA" },
1397
1398 { "HPL Mux", "DAC", "DACL" },
1399 { "HPL Mux", "Bypass", "Left Bypass" },
1400
1401 { "HPR Mux", "DAC", "DACR" },
1402 { "HPR Mux", "Bypass", "Right Bypass" },
1403
1404 { "LINEL Mux", "DAC", "DACL" },
1405 { "LINEL Mux", "Bypass", "Left Bypass" },
1406
1407 { "LINER Mux", "DAC", "DACR" },
1408 { "LINER Mux", "Bypass", "Right Bypass" },
1409
1410 { "HPL PGA", NULL, "HPL Mux" },
1411 { "HPR PGA", NULL, "HPR Mux" },
1412
1413 { "LINEL PGA", NULL, "LINEL Mux" },
1414 { "LINER PGA", NULL, "LINER Mux" },
1415};
1416
8c126474
MB		 1417static const struct snd_soc_dapm_route wm8912_intercon[] = {
1418 { "HPL PGA", NULL, "DACL" },
1419 { "HPR PGA", NULL, "DACR" },
1420
1421 { "LINEL PGA", NULL, "DACL" },
1422 { "LINER PGA", NULL, "DACR" },
1423};
1424
a91eb199
MB		 1425static int wm8904_add_widgets(struct snd_soc_codec *codec)
1426{
b2c812e2 1427 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
ce6120cc 1428 struct snd_soc_dapm_context *dapm = &codec->dapm;
a91eb199 1429
ce6120cc 1430 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
a91eb199 1431 ARRAY_SIZE(wm8904_core_dapm_widgets));
ce6120cc 1432 snd_soc_dapm_add_routes(dapm, core_intercon,
a91eb199 1433 ARRAY_SIZE(core_intercon));
8c126474
MB		 1434
1435 switch (wm8904->devtype) {
1436 case WM8904:
1437 snd_soc_add_controls(codec, wm8904_adc_snd_controls,
1438 ARRAY_SIZE(wm8904_adc_snd_controls));
1439 snd_soc_add_controls(codec, wm8904_dac_snd_controls,
1440 ARRAY_SIZE(wm8904_dac_snd_controls));
1441 snd_soc_add_controls(codec, wm8904_snd_controls,
1442 ARRAY_SIZE(wm8904_snd_controls));
1443
ce6120cc 1444 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
8c126474 1445 ARRAY_SIZE(wm8904_adc_dapm_widgets));
ce6120cc 1446 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
8c126474 1447 ARRAY_SIZE(wm8904_dac_dapm_widgets));
ce6120cc 1448 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
8c126474
MB		 1449 ARRAY_SIZE(wm8904_dapm_widgets));
1450
ce6120cc 1451 snd_soc_dapm_add_routes(dapm, core_intercon,
8c126474 1452 ARRAY_SIZE(core_intercon));
ce6120cc 1453 snd_soc_dapm_add_routes(dapm, adc_intercon,
8c126474 1454 ARRAY_SIZE(adc_intercon));
ce6120cc 1455 snd_soc_dapm_add_routes(dapm, dac_intercon,
8c126474 1456 ARRAY_SIZE(dac_intercon));
ce6120cc 1457 snd_soc_dapm_add_routes(dapm, wm8904_intercon,
8c126474
MB		 1458 ARRAY_SIZE(wm8904_intercon));
1459 break;
1460
1461 case WM8912:
1462 snd_soc_add_controls(codec, wm8904_dac_snd_controls,
1463 ARRAY_SIZE(wm8904_dac_snd_controls));
1464
ce6120cc 1465 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
8c126474
MB		 1466 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1467
ce6120cc 1468 snd_soc_dapm_add_routes(dapm, dac_intercon,
8c126474 1469 ARRAY_SIZE(dac_intercon));
ce6120cc 1470 snd_soc_dapm_add_routes(dapm, wm8912_intercon,
8c126474
MB		 1471 ARRAY_SIZE(wm8912_intercon));
1472 break;
1473 }
a91eb199 1474
ce6120cc 1475 snd_soc_dapm_new_widgets(dapm);
a91eb199
MB		 1476 return 0;
1477}
1478
1479static struct {
1480 int ratio;
1481 unsigned int clk_sys_rate;
1482} clk_sys_rates[] = {
1483 { 64, 0 },
1484 { 128, 1 },
1485 { 192, 2 },
1486 { 256, 3 },
1487 { 384, 4 },
1488 { 512, 5 },
1489 { 786, 6 },
1490 { 1024, 7 },
1491 { 1408, 8 },
1492 { 1536, 9 },
1493};
1494
1495static struct {
1496 int rate;
1497 int sample_rate;
1498} sample_rates[] = {
1499 { 8000, 0 },
1500 { 11025, 1 },
1501 { 12000, 1 },
1502 { 16000, 2 },
1503 { 22050, 3 },
1504 { 24000, 3 },
1505 { 32000, 4 },
1506 { 44100, 5 },
1507 { 48000, 5 },
1508};
1509
1510static struct {
1511 int div; /* *10 due to .5s */
1512 int bclk_div;
1513} bclk_divs[] = {
1514 { 10, 0 },
1515 { 15, 1 },
1516 { 20, 2 },
1517 { 30, 3 },
1518 { 40, 4 },
1519 { 50, 5 },
1520 { 55, 6 },
1521 { 60, 7 },
1522 { 80, 8 },
1523 { 100, 9 },
1524 { 110, 10 },
1525 { 120, 11 },
1526 { 160, 12 },
1527 { 200, 13 },
1528 { 220, 14 },
1529 { 240, 16 },
1530 { 200, 17 },
1531 { 320, 18 },
1532 { 440, 19 },
1533 { 480, 20 },
1534};
1535
1536
1537static int wm8904_hw_params(struct snd_pcm_substream *substream,
1538 struct snd_pcm_hw_params *params,
1539 struct snd_soc_dai *dai)
1540{
1541 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1542 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1543 int ret, i, best, best_val, cur_val;
1544 unsigned int aif1 = 0;
1545 unsigned int aif2 = 0;
1546 unsigned int aif3 = 0;
1547 unsigned int clock1 = 0;
1548 unsigned int dac_digital1 = 0;
1549
1550 /* What BCLK do we need? */
1551 wm8904->fs = params_rate(params);
1552 if (wm8904->tdm_slots) {
1553 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1554 wm8904->tdm_slots, wm8904->tdm_width);
1555 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1556 wm8904->tdm_width, 2,
1557 wm8904->tdm_slots);
1558 } else {
1559 wm8904->bclk = snd_soc_params_to_bclk(params);
1560 }
1561
56927eb0
MB		 1562 switch (params_format(params)) {
1563 case SNDRV_PCM_FORMAT_S16_LE:
1564 break;
1565 case SNDRV_PCM_FORMAT_S20_3LE:
1566 aif1 |= 0x40;
1567 break;
1568 case SNDRV_PCM_FORMAT_S24_LE:
1569 aif1 |= 0x80;
1570 break;
1571 case SNDRV_PCM_FORMAT_S32_LE:
1572 aif1 |= 0xc0;
1573 break;
1574 default:
1575 return -EINVAL;
1576 }
1577
1578
a91eb199
MB		 1579 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1580
1581 ret = wm8904_configure_clocking(codec);
1582 if (ret != 0)
1583 return ret;
1584
1585 /* Select nearest CLK_SYS_RATE */
1586 best = 0;
1587 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1588 - wm8904->fs);
1589 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1590 cur_val = abs((wm8904->sysclk_rate /
ef995e3a 1591 clk_sys_rates[i].ratio) - wm8904->fs);
a91eb199
MB		 1592 if (cur_val < best_val) {
1593 best = i;
1594 best_val = cur_val;
1595 }
1596 }
1597 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1598 clk_sys_rates[best].ratio);
1599 clock1 |= (clk_sys_rates[best].clk_sys_rate
1600 << WM8904_CLK_SYS_RATE_SHIFT);
1601
1602 /* SAMPLE_RATE */
1603 best = 0;
1604 best_val = abs(wm8904->fs - sample_rates[0].rate);
1605 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1606 /* Closest match */
1607 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1608 if (cur_val < best_val) {
1609 best = i;
1610 best_val = cur_val;
1611 }
1612 }
1613 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1614 sample_rates[best].rate);
1615 clock1 |= (sample_rates[best].sample_rate
1616 << WM8904_SAMPLE_RATE_SHIFT);
1617
1618 /* Enable sloping stopband filter for low sample rates */
1619 if (wm8904->fs <= 24000)
1620 dac_digital1 |= WM8904_DAC_SB_FILT;
1621
1622 /* BCLK_DIV */
1623 best = 0;
1624 best_val = INT_MAX;
1625 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1626 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1627 - wm8904->bclk;
1628 if (cur_val < 0) /* Table is sorted */
1629 break;
1630 if (cur_val < best_val) {
1631 best = i;
1632 best_val = cur_val;
1633 }
1634 }
1635 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1636 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1637 bclk_divs[best].div, wm8904->bclk);
1638 aif2 |= bclk_divs[best].bclk_div;
1639
1640 /* LRCLK is a simple fraction of BCLK */
1641 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1642 aif3 |= wm8904->bclk / wm8904->fs;
1643
1644 /* Apply the settings */
1645 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1646 WM8904_DAC_SB_FILT, dac_digital1);
1647 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1648 WM8904_AIF_WL_MASK, aif1);
1649 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1650 WM8904_BCLK_DIV_MASK, aif2);
1651 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1652 WM8904_LRCLK_RATE_MASK, aif3);
1653 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1654 WM8904_SAMPLE_RATE_MASK |
1655 WM8904_CLK_SYS_RATE_MASK, clock1);
1656
1657 /* Update filters for the new settings */
1658 wm8904_set_retune_mobile(codec);
1659 wm8904_set_deemph(codec);
1660
1661 return 0;
1662}
1663
1664
1665static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1666 unsigned int freq, int dir)
1667{
1668 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1669 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1670
1671 switch (clk_id) {
1672 case WM8904_CLK_MCLK:
1673 priv->sysclk_src = clk_id;
1674 priv->mclk_rate = freq;
1675 break;
1676
1677 case WM8904_CLK_FLL:
1678 priv->sysclk_src = clk_id;
1679 break;
1680
1681 default:
1682 return -EINVAL;
1683 }
1684
1685 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1686
1687 wm8904_configure_clocking(codec);
1688
1689 return 0;
1690}
1691
1692static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1693{
1694 struct snd_soc_codec *codec = dai->codec;
1695 unsigned int aif1 = 0;
1696 unsigned int aif3 = 0;
1697
1698 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1699 case SND_SOC_DAIFMT_CBS_CFS:
1700 break;
1701 case SND_SOC_DAIFMT_CBS_CFM:
1702 aif3 |= WM8904_LRCLK_DIR;
1703 break;
1704 case SND_SOC_DAIFMT_CBM_CFS:
1705 aif1 |= WM8904_BCLK_DIR;
1706 break;
1707 case SND_SOC_DAIFMT_CBM_CFM:
1708 aif1 |= WM8904_BCLK_DIR;
1709 aif3 |= WM8904_LRCLK_DIR;
1710 break;
1711 default:
1712 return -EINVAL;
1713 }
1714
1715 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1716 case SND_SOC_DAIFMT_DSP_B:
1717 aif1 |= WM8904_AIF_LRCLK_INV;
1718 case SND_SOC_DAIFMT_DSP_A:
1719 aif1 |= 0x3;
1720 break;
1721 case SND_SOC_DAIFMT_I2S:
1722 aif1 |= 0x2;
1723 break;
1724 case SND_SOC_DAIFMT_RIGHT_J:
1725 break;
1726 case SND_SOC_DAIFMT_LEFT_J:
1727 aif1 |= 0x1;
1728 break;
1729 default:
1730 return -EINVAL;
1731 }
1732
1733 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1734 case SND_SOC_DAIFMT_DSP_A:
1735 case SND_SOC_DAIFMT_DSP_B:
1736 /* frame inversion not valid for DSP modes */
1737 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1738 case SND_SOC_DAIFMT_NB_NF:
1739 break;
1740 case SND_SOC_DAIFMT_IB_NF:
1741 aif1 |= WM8904_AIF_BCLK_INV;
1742 break;
1743 default:
1744 return -EINVAL;
1745 }
1746 break;
1747
1748 case SND_SOC_DAIFMT_I2S:
1749 case SND_SOC_DAIFMT_RIGHT_J:
1750 case SND_SOC_DAIFMT_LEFT_J:
1751 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1752 case SND_SOC_DAIFMT_NB_NF:
1753 break;
1754 case SND_SOC_DAIFMT_IB_IF:
1755 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1756 break;
1757 case SND_SOC_DAIFMT_IB_NF:
1758 aif1 |= WM8904_AIF_BCLK_INV;
1759 break;
1760 case SND_SOC_DAIFMT_NB_IF:
1761 aif1 |= WM8904_AIF_LRCLK_INV;
1762 break;
1763 default:
1764 return -EINVAL;
1765 }
1766 break;
1767 default:
1768 return -EINVAL;
1769 }
1770
1771 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1772 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1773 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1774 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1775 WM8904_LRCLK_DIR, aif3);
1776
1777 return 0;
1778}
1779
1780
1781static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1782 unsigned int rx_mask, int slots, int slot_width)
1783{
1784 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1785 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1786 int aif1 = 0;
1787
1788 /* Don't need to validate anything if we're turning off TDM */
1789 if (slots == 0)
1790 goto out;
1791
1792 /* Note that we allow configurations we can't handle ourselves -
1793 * for example, we can generate clocks for slots 2 and up even if
1794 * we can't use those slots ourselves.
1795 */
1796 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1797
1798 switch (rx_mask) {
1799 case 3:
1800 break;
1801 case 0xc:
1802 aif1 |= WM8904_AIFADC_TDM_CHAN;
1803 break;
1804 default:
1805 return -EINVAL;
1806 }
1807
1808
1809 switch (tx_mask) {
1810 case 3:
1811 break;
1812 case 0xc:
1813 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1814 break;
1815 default:
1816 return -EINVAL;
1817 }
1818
1819out:
1820 wm8904->tdm_width = slot_width;
1821 wm8904->tdm_slots = slots / 2;
1822
1823 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1824 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1825 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1826
1827 return 0;
1828}
1829
1830struct _fll_div {
1831 u16 fll_fratio;
1832 u16 fll_outdiv;
1833 u16 fll_clk_ref_div;
1834 u16 n;
1835 u16 k;
1836};
1837
1838/* The size in bits of the FLL divide multiplied by 10
1839 * to allow rounding later */
1840#define FIXED_FLL_SIZE ((1 << 16) * 10)
1841
1842static struct {
1843 unsigned int min;
1844 unsigned int max;
1845 u16 fll_fratio;
1846 int ratio;
1847} fll_fratios[] = {
1848 { 0, 64000, 4, 16 },
1849 { 64000, 128000, 3, 8 },
1850 { 128000, 256000, 2, 4 },
1851 { 256000, 1000000, 1, 2 },
1852 { 1000000, 13500000, 0, 1 },
1853};
1854
1855static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1856 unsigned int Fout)
1857{
1858 u64 Kpart;
1859 unsigned int K, Ndiv, Nmod, target;
1860 unsigned int div;
1861 int i;
1862
1863 /* Fref must be <=13.5MHz */
1864 div = 1;
1865 fll_div->fll_clk_ref_div = 0;
1866 while ((Fref / div) > 13500000) {
1867 div *= 2;
1868 fll_div->fll_clk_ref_div++;
1869
1870 if (div > 8) {
1871 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1872 Fref);
1873 return -EINVAL;
1874 }
1875 }
1876
1877 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1878
1879 /* Apply the division for our remaining calculations */
1880 Fref /= div;
1881
1882 /* Fvco should be 90-100MHz; don't check the upper bound */
1883 div = 4;
1884 while (Fout * div < 90000000) {
1885 div++;
1886 if (div > 64) {
1887 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1888 Fout);
1889 return -EINVAL;
1890 }
1891 }
1892 target = Fout * div;
1893 fll_div->fll_outdiv = div - 1;
1894
1895 pr_debug("Fvco=%dHz\n", target);
1896
25985edc 1897 /* Find an appropriate FLL_FRATIO and factor it out of the target */
a91eb199
MB		 1898 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1899 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1900 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1901 target /= fll_fratios[i].ratio;
1902 break;
1903 }
1904 }
1905 if (i == ARRAY_SIZE(fll_fratios)) {
1906 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1907 return -EINVAL;
1908 }
1909
1910 /* Now, calculate N.K */
1911 Ndiv = target / Fref;
1912
1913 fll_div->n = Ndiv;
1914 Nmod = target % Fref;
1915 pr_debug("Nmod=%d\n", Nmod);
1916
1917 /* Calculate fractional part - scale up so we can round. */
1918 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1919
1920 do_div(Kpart, Fref);
1921
1922 K = Kpart & 0xFFFFFFFF;
1923
1924 if ((K % 10) >= 5)
1925 K += 5;
1926
1927 /* Move down to proper range now rounding is done */
1928 fll_div->k = K / 10;
1929
1930 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1931 fll_div->n, fll_div->k,
1932 fll_div->fll_fratio, fll_div->fll_outdiv,
1933 fll_div->fll_clk_ref_div);
1934
1935 return 0;
1936}
1937
1938static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1939 unsigned int Fref, unsigned int Fout)
1940{
1941 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1942 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1943 struct _fll_div fll_div;
1944 int ret, val;
1945 int clock2, fll1;
1946
1947 /* Any change? */
1948 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1949 Fout == wm8904->fll_fout)
1950 return 0;
1951
18240b67
MB		 1952 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1953
a91eb199
MB		 1954 if (Fout == 0) {
1955 dev_dbg(codec->dev, "FLL disabled\n");
1956
1957 wm8904->fll_fref = 0;
1958 wm8904->fll_fout = 0;
1959
1960 /* Gate SYSCLK to avoid glitches */
1961 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1962 WM8904_CLK_SYS_ENA, 0);
1963
1964 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1965 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1966
1967 goto out;
1968 }
1969
1970 /* Validate the FLL ID */
1971 switch (source) {
1972 case WM8904_FLL_MCLK:
1973 case WM8904_FLL_LRCLK:
1974 case WM8904_FLL_BCLK:
1975 ret = fll_factors(&fll_div, Fref, Fout);
1976 if (ret != 0)
1977 return ret;
1978 break;
1979
1980 case WM8904_FLL_FREE_RUNNING:
1981 dev_dbg(codec->dev, "Using free running FLL\n");
1982 /* Force 12MHz and output/4 for now */
1983 Fout = 12000000;
1984 Fref = 12000000;
1985
1986 memset(&fll_div, 0, sizeof(fll_div));
1987 fll_div.fll_outdiv = 3;
1988 break;
1989
1990 default:
1991 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1992 return -EINVAL;
1993 }
1994
1995 /* Save current state then disable the FLL and SYSCLK to avoid
1996 * misclocking */
a91eb199
MB		 1997 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1998 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1999 WM8904_CLK_SYS_ENA, 0);
2000 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2001 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
2002
2003 /* Unlock forced oscilator control to switch it on/off */
2004 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
2005 WM8904_USER_KEY, WM8904_USER_KEY);
2006
2007 if (fll_id == WM8904_FLL_FREE_RUNNING) {
2008 val = WM8904_FLL_FRC_NCO;
2009 } else {
2010 val = 0;
2011 }
2012
2013 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
2014 val);
2015 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
2016 WM8904_USER_KEY, 0);
2017
2018 switch (fll_id) {
2019 case WM8904_FLL_MCLK:
2020 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
2021 WM8904_FLL_CLK_REF_SRC_MASK, 0);
2022 break;
2023
2024 case WM8904_FLL_LRCLK:
2025 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
2026 WM8904_FLL_CLK_REF_SRC_MASK, 1);
2027 break;
2028
2029 case WM8904_FLL_BCLK:
2030 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
2031 WM8904_FLL_CLK_REF_SRC_MASK, 2);
2032 break;
2033 }
2034
2035 if (fll_div.k)
2036 val = WM8904_FLL_FRACN_ENA;
2037 else
2038 val = 0;
2039 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2040 WM8904_FLL_FRACN_ENA, val);
2041
2042 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
2043 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
2044 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
2045 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
2046
2047 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
2048
2049 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
2050 fll_div.n << WM8904_FLL_N_SHIFT);
2051
2052 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
2053 WM8904_FLL_CLK_REF_DIV_MASK,
2054 fll_div.fll_clk_ref_div
2055 << WM8904_FLL_CLK_REF_DIV_SHIFT);
2056
2057 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2058
2059 wm8904->fll_fref = Fref;
2060 wm8904->fll_fout = Fout;
2061 wm8904->fll_src = source;
2062
2063 /* Enable the FLL if it was previously active */
2064 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2065 WM8904_FLL_OSC_ENA, fll1);
2066 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
2067 WM8904_FLL_ENA, fll1);
2068
2069out:
2070 /* Reenable SYSCLK if it was previously active */
2071 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
2072 WM8904_CLK_SYS_ENA, clock2);
2073
2074 return 0;
2075}
2076
2077static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2078{
2079 struct snd_soc_codec *codec = codec_dai->codec;
2080 int val;
2081
2082 if (mute)
2083 val = WM8904_DAC_MUTE;
2084 else
2085 val = 0;
2086
2087 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
2088
2089 return 0;
2090}
2091
c1334218
MB		 2092static void wm8904_sync_cache(struct snd_soc_codec *codec)
2093{
f578a188 2094 u16 *reg_cache = codec->reg_cache;
c1334218
MB		 2095 int i;
2096
2097 if (!codec->cache_sync)
2098 return;
2099
2100 codec->cache_only = 0;
2101
2102 /* Sync back cached values if they're different from the
2103 * hardware default.
2104 */
f578a188 2105 for (i = 1; i < codec->driver->reg_cache_size; i++) {
c1334218
MB		 2106 if (!wm8904_access[i].writable)
2107 continue;
2108
f578a188 2109 if (reg_cache[i] == wm8904_reg[i])
c1334218
MB		 2110 continue;
2111
f578a188 2112 snd_soc_write(codec, i, reg_cache[i]);
c1334218
MB		 2113 }
2114
2115 codec->cache_sync = 0;
2116}
2117
a91eb199
MB		 2118static int wm8904_set_bias_level(struct snd_soc_codec *codec,
2119 enum snd_soc_bias_level level)
2120{
b2c812e2 2121 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
c1334218 2122 int ret;
a91eb199
MB		 2123
2124 switch (level) {
2125 case SND_SOC_BIAS_ON:
2126 break;
2127
2128 case SND_SOC_BIAS_PREPARE:
2129 /* VMID resistance 2*50k */
2130 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2131 WM8904_VMID_RES_MASK,
2132 0x1 << WM8904_VMID_RES_SHIFT);
2133
2134 /* Normal bias current */
2135 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2136 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
2137 break;
2138
2139 case SND_SOC_BIAS_STANDBY:
ce6120cc 2140 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
a91eb199
MB		 2141 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2142 wm8904->supplies);
2143 if (ret != 0) {
2144 dev_err(codec->dev,
2145 "Failed to enable supplies: %d\n",
2146 ret);
2147 return ret;
2148 }
2149
c1334218 2150 wm8904_sync_cache(codec);
a91eb199
MB		 2151
2152 /* Enable bias */
2153 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2154 WM8904_BIAS_ENA, WM8904_BIAS_ENA);
2155
2156 /* Enable VMID, VMID buffering, 2*5k resistance */
2157 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2158 WM8904_VMID_ENA |
2159 WM8904_VMID_RES_MASK,
2160 WM8904_VMID_ENA |
2161 0x3 << WM8904_VMID_RES_SHIFT);
2162
2163 /* Let VMID ramp */
2164 msleep(1);
2165 }
2166
2167 /* Maintain VMID with 2*250k */
2168 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2169 WM8904_VMID_RES_MASK,
2170 0x2 << WM8904_VMID_RES_SHIFT);
2171
2172 /* Bias current *0.5 */
2173 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2174 WM8904_ISEL_MASK, 0);
2175 break;
2176
2177 case SND_SOC_BIAS_OFF:
2178 /* Turn off VMID */
2179 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
2180 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
2181
2182 /* Stop bias generation */
2183 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2184 WM8904_BIAS_ENA, 0);
2185
c1334218
MB		 2186#ifdef CONFIG_REGULATOR
2187 /* Post 2.6.34 we will be able to get a callback when
2188 * the regulators are disabled which we can use but
2189 * for now just assume that the power will be cut if
2190 * the regulator API is in use.
2191 */
2192 codec->cache_sync = 1;
2193#endif
2194
a91eb199
MB		 2195 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
2196 wm8904->supplies);
2197 break;
2198 }
ce6120cc 2199 codec->dapm.bias_level = level;
a91eb199
MB		 2200 return 0;
2201}
2202
2203#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
2204
2205#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2206 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2207
2208static struct snd_soc_dai_ops wm8904_dai_ops = {
2209 .set_sysclk = wm8904_set_sysclk,
2210 .set_fmt = wm8904_set_fmt,
2211 .set_tdm_slot = wm8904_set_tdm_slot,
2212 .set_pll = wm8904_set_fll,
2213 .hw_params = wm8904_hw_params,
2214 .digital_mute = wm8904_digital_mute,
2215};
2216
f0fba2ad
LG		 2217static struct snd_soc_dai_driver wm8904_dai = {
2218 .name = "wm8904-hifi",
a91eb199
MB		 2219 .playback = {
2220 .stream_name = "Playback",
2221 .channels_min = 2,
2222 .channels_max = 2,
2223 .rates = WM8904_RATES,
2224 .formats = WM8904_FORMATS,
2225 },
2226 .capture = {
2227 .stream_name = "Capture",
2228 .channels_min = 2,
2229 .channels_max = 2,
2230 .rates = WM8904_RATES,
2231 .formats = WM8904_FORMATS,
2232 },
2233 .ops = &wm8904_dai_ops,
2234 .symmetric_rates = 1,
2235};
a91eb199
MB		 2236
2237#ifdef CONFIG_PM
f0fba2ad 2238static int wm8904_suspend(struct snd_soc_codec *codec, pm_message_t state)
a91eb199 2239{
a91eb199
MB		 2240 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
2241
2242 return 0;
2243}
2244
f0fba2ad 2245static int wm8904_resume(struct snd_soc_codec *codec)
a91eb199 2246{
a91eb199
MB		 2247 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2248
2249 return 0;
2250}
2251#else
2252#define wm8904_suspend NULL
2253#define wm8904_resume NULL
2254#endif
2255
f0fba2ad 2256static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
a91eb199 2257{
f0fba2ad 2258 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 2259 struct wm8904_pdata *pdata = wm8904->pdata;
2260 struct snd_kcontrol_new control =
2261 SOC_ENUM_EXT("EQ Mode",
2262 wm8904->retune_mobile_enum,
2263 wm8904_get_retune_mobile_enum,
2264 wm8904_put_retune_mobile_enum);
2265 int ret, i, j;
2266 const char **t;
2267
2268 /* We need an array of texts for the enum API but the number
2269 * of texts is likely to be less than the number of
2270 * configurations due to the sample rate dependency of the
2271 * configurations. */
2272 wm8904->num_retune_mobile_texts = 0;
2273 wm8904->retune_mobile_texts = NULL;
2274 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2275 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
2276 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2277 wm8904->retune_mobile_texts[j]) == 0)
2278 break;
2279 }
2280
2281 if (j != wm8904->num_retune_mobile_texts)
2282 continue;
2283
2284 /* Expand the array... */
2285 t = krealloc(wm8904->retune_mobile_texts,
2286 sizeof(char *) *
2287 (wm8904->num_retune_mobile_texts + 1),
2288 GFP_KERNEL);
2289 if (t == NULL)
2290 continue;
2291
2292 /* ...store the new entry... */
2293 t[wm8904->num_retune_mobile_texts] =
2294 pdata->retune_mobile_cfgs[i].name;
2295
2296 /* ...and remember the new version. */
2297 wm8904->num_retune_mobile_texts++;
2298 wm8904->retune_mobile_texts = t;
2299 }
2300
2301 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2302 wm8904->num_retune_mobile_texts);
2303
2304 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
2305 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
2306
f0fba2ad 2307 ret = snd_soc_add_controls(codec, &control, 1);
a91eb199 2308 if (ret != 0)
f0fba2ad 2309 dev_err(codec->dev,
a91eb199
MB		 2310 "Failed to add ReTune Mobile control: %d\n", ret);
2311}
2312
f0fba2ad 2313static void wm8904_handle_pdata(struct snd_soc_codec *codec)
a91eb199 2314{
f0fba2ad 2315 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 2316 struct wm8904_pdata *pdata = wm8904->pdata;
2317 int ret, i;
2318
2319 if (!pdata) {
f0fba2ad 2320 snd_soc_add_controls(codec, wm8904_eq_controls,
a91eb199
MB		 2321 ARRAY_SIZE(wm8904_eq_controls));
2322 return;
2323 }
2324
2325 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2326
2327 if (pdata->num_drc_cfgs) {
2328 struct snd_kcontrol_new control =
2329 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2330 wm8904_get_drc_enum, wm8904_put_drc_enum);
2331
2332 /* We need an array of texts for the enum API */
2333 wm8904->drc_texts = kmalloc(sizeof(char *)
2334 * pdata->num_drc_cfgs, GFP_KERNEL);
2335 if (!wm8904->drc_texts) {
f0fba2ad 2336 dev_err(codec->dev,
a91eb199
MB		 2337 "Failed to allocate %d DRC config texts\n",
2338 pdata->num_drc_cfgs);
2339 return;
2340 }
2341
2342 for (i = 0; i < pdata->num_drc_cfgs; i++)
2343 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2344
2345 wm8904->drc_enum.max = pdata->num_drc_cfgs;
2346 wm8904->drc_enum.texts = wm8904->drc_texts;
2347
f0fba2ad 2348 ret = snd_soc_add_controls(codec, &control, 1);
a91eb199 2349 if (ret != 0)
f0fba2ad 2350 dev_err(codec->dev,
a91eb199
MB		 2351 "Failed to add DRC mode control: %d\n", ret);
2352
2353 wm8904_set_drc(codec);
2354 }
2355
2356 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2357 pdata->num_retune_mobile_cfgs);
2358
2359 if (pdata->num_retune_mobile_cfgs)
f0fba2ad 2360 wm8904_handle_retune_mobile_pdata(codec);
a91eb199 2361 else
f0fba2ad 2362 snd_soc_add_controls(codec, wm8904_eq_controls,
a91eb199
MB		 2363 ARRAY_SIZE(wm8904_eq_controls));
2364}
2365
a91eb199 2366
f0fba2ad 2367static int wm8904_probe(struct snd_soc_codec *codec)
a91eb199 2368{
f0fba2ad 2369 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
cdce4e9b 2370 struct wm8904_pdata *pdata = wm8904->pdata;
f578a188 2371 u16 *reg_cache = codec->reg_cache;
f0fba2ad 2372 int ret, i;
a91eb199 2373
c1334218 2374 codec->cache_sync = 1;
ce6120cc 2375 codec->dapm.idle_bias_off = 1;
a91eb199 2376
8c126474
MB		 2377 switch (wm8904->devtype) {
2378 case WM8904:
2379 break;
2380 case WM8912:
2381 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2382 break;
2383 default:
2384 dev_err(codec->dev, "Unknown device type %d\n",
2385 wm8904->devtype);
f0fba2ad 2386 return -EINVAL;
8c126474
MB		 2387 }
2388
f0fba2ad 2389 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
a91eb199
MB		 2390 if (ret != 0) {
2391 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 2392 return ret;
a91eb199
MB		 2393 }
2394
2395 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2396 wm8904->supplies[i].supply = wm8904_supply_names[i];
2397
2398 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8904->supplies),
2399 wm8904->supplies);
2400 if (ret != 0) {
2401 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 2402 return ret;
a91eb199
MB		 2403 }
2404
2405 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2406 wm8904->supplies);
2407 if (ret != 0) {
2408 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2409 goto err_get;
2410 }
2411
2412 ret = snd_soc_read(codec, WM8904_SW_RESET_AND_ID);
2413 if (ret < 0) {
2414 dev_err(codec->dev, "Failed to read ID register\n");
2415 goto err_enable;
2416 }
2417 if (ret != wm8904_reg[WM8904_SW_RESET_AND_ID]) {
2418 dev_err(codec->dev, "Device is not a WM8904, ID is %x\n", ret);
2419 ret = -EINVAL;
2420 goto err_enable;
2421 }
2422
2423 ret = snd_soc_read(codec, WM8904_REVISION);
2424 if (ret < 0) {
2425 dev_err(codec->dev, "Failed to read device revision: %d\n",
2426 ret);
2427 goto err_enable;
2428 }
2429 dev_info(codec->dev, "revision %c\n", ret + 'A');
2430
2431 ret = wm8904_reset(codec);
2432 if (ret < 0) {
2433 dev_err(codec->dev, "Failed to issue reset\n");
2434 goto err_enable;
2435 }
2436
a91eb199 2437 /* Change some default settings - latch VU and enable ZC */
a1b3b5ee
MB		 2438 snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2439 WM8904_ADC_VU, WM8904_ADC_VU);
2440 snd_soc_update_bits(codec, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2441 WM8904_ADC_VU, WM8904_ADC_VU);
2442 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2443 WM8904_DAC_VU, WM8904_DAC_VU);
2444 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2445 WM8904_DAC_VU, WM8904_DAC_VU);
2446 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_LEFT,
2447 WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2448 WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2449 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT1_RIGHT,
2450 WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2451 WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2452 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_LEFT,
2453 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2454 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2455 snd_soc_update_bits(codec, WM8904_ANALOGUE_OUT2_RIGHT,
2456 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2457 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2458 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0,
2459 WM8904_SR_MODE, 0);
a91eb199 2460
cdce4e9b
MB		 2461 /* Apply configuration from the platform data. */
2462 if (wm8904->pdata) {
2463 for (i = 0; i < WM8904_GPIO_REGS; i++) {
2464 if (!pdata->gpio_cfg[i])
2465 continue;
2466
f578a188 2467 reg_cache[WM8904_GPIO_CONTROL_1 + i]
cdce4e9b
MB		 2468 = pdata->gpio_cfg[i] & 0xffff;
2469 }
fbc2dae8
MB		 2470
2471 /* Zero is the default value for these anyway */
2472 for (i = 0; i < WM8904_MIC_REGS; i++)
f578a188 2473 reg_cache[WM8904_MIC_BIAS_CONTROL_0 + i]
fbc2dae8 2474 = pdata->mic_cfg[i];
cdce4e9b
MB		 2475 }
2476
a91eb199
MB		 2477 /* Set Class W by default - this will be managed by the Class
2478 * G widget at runtime where bypass paths are available.
2479 */
a1b3b5ee
MB		 2480 snd_soc_update_bits(codec, WM8904_CLASS_W_0,
2481 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
a91eb199
MB		 2482
2483 /* Use normal bias source */
a1b3b5ee
MB		 2484 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
2485 WM8904_POBCTRL, 0);
a91eb199
MB		 2486
2487 wm8904_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2488
2489 /* Bias level configuration will have done an extra enable */
2490 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2491
f0fba2ad 2492 wm8904_handle_pdata(codec);
a91eb199 2493
f0fba2ad 2494 wm8904_add_widgets(codec);
a91eb199
MB		 2495
2496 return 0;
2497
2498err_enable:
2499 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2500err_get:
2501 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
a91eb199
MB		 2502 return ret;
2503}
2504
f0fba2ad 2505static int wm8904_remove(struct snd_soc_codec *codec)
a91eb199 2506{
f0fba2ad
LG		 2507 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2508
2509 wm8904_set_bias_level(codec, SND_SOC_BIAS_OFF);
a91eb199 2510 regulator_bulk_free(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
cd70978c
AL		 2511 kfree(wm8904->retune_mobile_texts);
2512 kfree(wm8904->drc_texts);
f0fba2ad
LG		 2513
2514 return 0;
a91eb199
MB		 2515}
2516
f0fba2ad
LG		 2517static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
2518 .probe = wm8904_probe,
2519 .remove = wm8904_remove,
2520 .suspend = wm8904_suspend,
2521 .resume = wm8904_resume,
2522 .set_bias_level = wm8904_set_bias_level,
2523 .reg_cache_size = ARRAY_SIZE(wm8904_reg),
2524 .reg_word_size = sizeof(u16),
2525 .reg_cache_default = wm8904_reg,
2526 .volatile_register = wm8904_volatile_register,
2527};
2528
a91eb199
MB		 2529#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2530static __devinit int wm8904_i2c_probe(struct i2c_client *i2c,
2531 const struct i2c_device_id *id)
2532{
2533 struct wm8904_priv *wm8904;
f0fba2ad 2534 int ret;
a91eb199
MB		 2535
2536 wm8904 = kzalloc(sizeof(struct wm8904_priv), GFP_KERNEL);
2537 if (wm8904 == NULL)
2538 return -ENOMEM;
2539
8c126474 2540 wm8904->devtype = id->driver_data;
a91eb199 2541 i2c_set_clientdata(i2c, wm8904);
a91eb199
MB		 2542 wm8904->pdata = i2c->dev.platform_data;
2543
f0fba2ad
LG		 2544 ret = snd_soc_register_codec(&i2c->dev,
2545 &soc_codec_dev_wm8904, &wm8904_dai, 1);
2546 if (ret < 0)
2547 kfree(wm8904);
2548 return ret;
a91eb199
MB		 2549}
2550
2551static __devexit int wm8904_i2c_remove(struct i2c_client *client)
2552{
f0fba2ad
LG		 2553 snd_soc_unregister_codec(&client->dev);
2554 kfree(i2c_get_clientdata(client));
a91eb199
MB		 2555 return 0;
2556}
2557
2558static const struct i2c_device_id wm8904_i2c_id[] = {
8c126474
MB		 2559 { "wm8904", WM8904 },
2560 { "wm8912", WM8912 },
df1553c8 2561 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
a91eb199
MB		 2562 { }
2563};
2564MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2565
2566static struct i2c_driver wm8904_i2c_driver = {
2567 .driver = {
f0fba2ad 2568 .name = "wm8904-codec",
a91eb199
MB		 2569 .owner = THIS_MODULE,
2570 },
2571 .probe = wm8904_i2c_probe,
2572 .remove = __devexit_p(wm8904_i2c_remove),
2573 .id_table = wm8904_i2c_id,
2574};
2575#endif
2576
2577static int __init wm8904_modinit(void)
2578{
f0fba2ad 2579 int ret = 0;
a91eb199
MB		 2580#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2581 ret = i2c_add_driver(&wm8904_i2c_driver);
2582 if (ret != 0) {
f0fba2ad 2583 printk(KERN_ERR "Failed to register wm8904 I2C driver: %d\n",
a91eb199
MB		 2584 ret);
2585 }
2586#endif
f0fba2ad 2587 return ret;
a91eb199
MB		 2588}
2589module_init(wm8904_modinit);
2590
2591static void __exit wm8904_exit(void)
2592{
2593#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2594 i2c_del_driver(&wm8904_i2c_driver);
2595#endif
2596}
2597module_exit(wm8904_exit);
2598
2599MODULE_DESCRIPTION("ASoC WM8904 driver");
2600MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2601MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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