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Linus 3.14-rc1
[deliverable/linux.git] / sound / soc / codecs / wm8904.c
CommitLineData
a91eb199
MB		 1/*
2 * wm8904.c -- WM8904 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
a91eb199
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
84d0d831 20#include <linux/regmap.h>
a91eb199 21#include <linux/regulator/consumer.h>
5a0e3ad6 22#include <linux/slab.h>
a91eb199
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
a91eb199
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/wm8904.h>
30
31#include "wm8904.h"
32
8c126474
MB		 33enum wm8904_type {
34 WM8904,
35 WM8912,
36};
37
a91eb199
MB		 38#define WM8904_NUM_DCS_CHANNELS 4
39
40#define WM8904_NUM_SUPPLIES 5
41static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47};
48
49/* codec private data */
50struct wm8904_priv {
84d0d831 51 struct regmap *regmap;
f0fba2ad 52
8c126474
MB		 53 enum wm8904_type devtype;
54
a91eb199
MB		 55 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
56
57 struct wm8904_pdata *pdata;
58
59 int deemph;
60
61 /* Platform provided DRC configuration */
62 const char **drc_texts;
63 int drc_cfg;
64 struct soc_enum drc_enum;
65
66 /* Platform provided ReTune mobile configuration */
67 int num_retune_mobile_texts;
68 const char **retune_mobile_texts;
69 int retune_mobile_cfg;
70 struct soc_enum retune_mobile_enum;
71
72 /* FLL setup */
73 int fll_src;
74 int fll_fref;
75 int fll_fout;
76
77 /* Clocking configuration */
78 unsigned int mclk_rate;
79 int sysclk_src;
80 unsigned int sysclk_rate;
81
82 int tdm_width;
83 int tdm_slots;
84 int bclk;
85 int fs;
86
87 /* DC servo configuration - cached offset values */
88 int dcs_state[WM8904_NUM_DCS_CHANNELS];
89};
90
84d0d831
MB		 91static const struct reg_default wm8904_reg_defaults[] = {
92 { 4, 0x0018 }, /* R4 - Bias Control 0 */
93 { 5, 0x0000 }, /* R5 - VMID Control 0 */
94 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
95 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
96 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
97 { 9, 0x9696 }, /* R9 - mic Filter Control */
98 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
99 { 12, 0x0000 }, /* R12 - Power Management 0 */
100 { 14, 0x0000 }, /* R14 - Power Management 2 */
101 { 15, 0x0000 }, /* R15 - Power Management 3 */
102 { 18, 0x0000 }, /* R18 - Power Management 6 */
985b11fa 103 { 20, 0x945E }, /* R20 - Clock Rates 0 */
84d0d831
MB		 104 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
105 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
106 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
107 { 25, 0x000A }, /* R25 - Audio Interface 1 */
108 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
109 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
110 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
111 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
112 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
113 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
114 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
115 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
116 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
117 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
118 { 40, 0x01AF }, /* R40 - DRC 0 */
119 { 41, 0x3248 }, /* R41 - DRC 1 */
120 { 42, 0x0000 }, /* R42 - DRC 2 */
121 { 43, 0x0000 }, /* R43 - DRC 3 */
122 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
123 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
124 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
125 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
126 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
127 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
128 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
129 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
130 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
131 { 67, 0x0000 }, /* R67 - DC Servo 0 */
132 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
133 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
134 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
135 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
136 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
137 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
138 { 104, 0x0004 }, /* R104 - Class W 0 */
139 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
140 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
141 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
142 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
143 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
144 { 116, 0x0000 }, /* R116 - FLL Control 1 */
145 { 117, 0x0007 }, /* R117 - FLL Control 2 */
146 { 118, 0x0000 }, /* R118 - FLL Control 3 */
147 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
148 { 120, 0x0004 }, /* R120 - FLL Control 5 */
149 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
150 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
151 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
152 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
153 { 126, 0x0000 }, /* R126 - Digital Pulls */
154 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
155 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
156 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
157 { 134, 0x0000 }, /* R134 - EQ1 */
158 { 135, 0x000C }, /* R135 - EQ2 */
159 { 136, 0x000C }, /* R136 - EQ3 */
160 { 137, 0x000C }, /* R137 - EQ4 */
161 { 138, 0x000C }, /* R138 - EQ5 */
162 { 139, 0x000C }, /* R139 - EQ6 */
163 { 140, 0x0FCA }, /* R140 - EQ7 */
164 { 141, 0x0400 }, /* R141 - EQ8 */
165 { 142, 0x00D8 }, /* R142 - EQ9 */
166 { 143, 0x1EB5 }, /* R143 - EQ10 */
167 { 144, 0xF145 }, /* R144 - EQ11 */
168 { 145, 0x0B75 }, /* R145 - EQ12 */
169 { 146, 0x01C5 }, /* R146 - EQ13 */
170 { 147, 0x1C58 }, /* R147 - EQ14 */
171 { 148, 0xF373 }, /* R148 - EQ15 */
172 { 149, 0x0A54 }, /* R149 - EQ16 */
173 { 150, 0x0558 }, /* R150 - EQ17 */
174 { 151, 0x168E }, /* R151 - EQ18 */
175 { 152, 0xF829 }, /* R152 - EQ19 */
176 { 153, 0x07AD }, /* R153 - EQ20 */
177 { 154, 0x1103 }, /* R154 - EQ21 */
178 { 155, 0x0564 }, /* R155 - EQ22 */
179 { 156, 0x0559 }, /* R156 - EQ23 */
180 { 157, 0x4000 }, /* R157 - EQ24 */
181 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
182 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
183 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
184 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
a91eb199
MB		 185};
186
84d0d831
MB		 187static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
188{
189 switch (reg) {
190 case WM8904_SW_RESET_AND_ID:
191 case WM8904_REVISION:
192 case WM8904_DC_SERVO_1:
193 case WM8904_DC_SERVO_6:
194 case WM8904_DC_SERVO_7:
195 case WM8904_DC_SERVO_8:
196 case WM8904_DC_SERVO_9:
197 case WM8904_DC_SERVO_READBACK_0:
198 case WM8904_INTERRUPT_STATUS:
199 return true;
200 default:
201 return false;
202 }
203}
a91eb199 204
84d0d831 205static bool wm8904_readable_register(struct device *dev, unsigned int reg)
a91eb199 206{
84d0d831
MB		 207 switch (reg) {
208 case WM8904_SW_RESET_AND_ID:
209 case WM8904_REVISION:
210 case WM8904_BIAS_CONTROL_0:
211 case WM8904_VMID_CONTROL_0:
212 case WM8904_MIC_BIAS_CONTROL_0:
213 case WM8904_MIC_BIAS_CONTROL_1:
214 case WM8904_ANALOGUE_DAC_0:
215 case WM8904_MIC_FILTER_CONTROL:
216 case WM8904_ANALOGUE_ADC_0:
217 case WM8904_POWER_MANAGEMENT_0:
218 case WM8904_POWER_MANAGEMENT_2:
219 case WM8904_POWER_MANAGEMENT_3:
220 case WM8904_POWER_MANAGEMENT_6:
221 case WM8904_CLOCK_RATES_0:
222 case WM8904_CLOCK_RATES_1:
223 case WM8904_CLOCK_RATES_2:
224 case WM8904_AUDIO_INTERFACE_0:
225 case WM8904_AUDIO_INTERFACE_1:
226 case WM8904_AUDIO_INTERFACE_2:
227 case WM8904_AUDIO_INTERFACE_3:
228 case WM8904_DAC_DIGITAL_VOLUME_LEFT:
229 case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
230 case WM8904_DAC_DIGITAL_0:
231 case WM8904_DAC_DIGITAL_1:
232 case WM8904_ADC_DIGITAL_VOLUME_LEFT:
233 case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
234 case WM8904_ADC_DIGITAL_0:
235 case WM8904_DIGITAL_MICROPHONE_0:
236 case WM8904_DRC_0:
237 case WM8904_DRC_1:
238 case WM8904_DRC_2:
239 case WM8904_DRC_3:
240 case WM8904_ANALOGUE_LEFT_INPUT_0:
241 case WM8904_ANALOGUE_RIGHT_INPUT_0:
242 case WM8904_ANALOGUE_LEFT_INPUT_1:
243 case WM8904_ANALOGUE_RIGHT_INPUT_1:
244 case WM8904_ANALOGUE_OUT1_LEFT:
245 case WM8904_ANALOGUE_OUT1_RIGHT:
246 case WM8904_ANALOGUE_OUT2_LEFT:
247 case WM8904_ANALOGUE_OUT2_RIGHT:
248 case WM8904_ANALOGUE_OUT12_ZC:
249 case WM8904_DC_SERVO_0:
250 case WM8904_DC_SERVO_1:
251 case WM8904_DC_SERVO_2:
252 case WM8904_DC_SERVO_4:
253 case WM8904_DC_SERVO_5:
254 case WM8904_DC_SERVO_6:
255 case WM8904_DC_SERVO_7:
256 case WM8904_DC_SERVO_8:
257 case WM8904_DC_SERVO_9:
258 case WM8904_DC_SERVO_READBACK_0:
259 case WM8904_ANALOGUE_HP_0:
260 case WM8904_ANALOGUE_LINEOUT_0:
261 case WM8904_CHARGE_PUMP_0:
262 case WM8904_CLASS_W_0:
263 case WM8904_WRITE_SEQUENCER_0:
264 case WM8904_WRITE_SEQUENCER_1:
265 case WM8904_WRITE_SEQUENCER_2:
266 case WM8904_WRITE_SEQUENCER_3:
267 case WM8904_WRITE_SEQUENCER_4:
268 case WM8904_FLL_CONTROL_1:
269 case WM8904_FLL_CONTROL_2:
270 case WM8904_FLL_CONTROL_3:
271 case WM8904_FLL_CONTROL_4:
272 case WM8904_FLL_CONTROL_5:
273 case WM8904_GPIO_CONTROL_1:
274 case WM8904_GPIO_CONTROL_2:
275 case WM8904_GPIO_CONTROL_3:
276 case WM8904_GPIO_CONTROL_4:
277 case WM8904_DIGITAL_PULLS:
278 case WM8904_INTERRUPT_STATUS:
279 case WM8904_INTERRUPT_STATUS_MASK:
280 case WM8904_INTERRUPT_POLARITY:
281 case WM8904_INTERRUPT_DEBOUNCE:
282 case WM8904_EQ1:
283 case WM8904_EQ2:
284 case WM8904_EQ3:
285 case WM8904_EQ4:
286 case WM8904_EQ5:
287 case WM8904_EQ6:
288 case WM8904_EQ7:
289 case WM8904_EQ8:
290 case WM8904_EQ9:
291 case WM8904_EQ10:
292 case WM8904_EQ11:
293 case WM8904_EQ12:
294 case WM8904_EQ13:
295 case WM8904_EQ14:
296 case WM8904_EQ15:
297 case WM8904_EQ16:
298 case WM8904_EQ17:
299 case WM8904_EQ18:
300 case WM8904_EQ19:
301 case WM8904_EQ20:
302 case WM8904_EQ21:
303 case WM8904_EQ22:
304 case WM8904_EQ23:
305 case WM8904_EQ24:
306 case WM8904_CONTROL_INTERFACE_TEST_1:
9b85fc90 307 case WM8904_ADC_TEST_0:
84d0d831
MB		 308 case WM8904_ANALOGUE_OUTPUT_BIAS_0:
309 case WM8904_FLL_NCO_TEST_0:
310 case WM8904_FLL_NCO_TEST_1:
311 return true;
312 default:
313 return true;
314 }
a91eb199
MB		 315}
316
a91eb199
MB		 317static int wm8904_configure_clocking(struct snd_soc_codec *codec)
318{
b2c812e2 319 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 320 unsigned int clock0, clock2, rate;
321
322 /* Gate the clock while we're updating to avoid misclocking */
323 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
324 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
325 WM8904_SYSCLK_SRC, 0);
326
327 /* This should be done on init() for bypass paths */
328 switch (wm8904->sysclk_src) {
329 case WM8904_CLK_MCLK:
330 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
331
332 clock2 &= ~WM8904_SYSCLK_SRC;
333 rate = wm8904->mclk_rate;
334
335 /* Ensure the FLL is stopped */
336 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
337 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
338 break;
339
340 case WM8904_CLK_FLL:
341 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
342 wm8904->fll_fout);
343
344 clock2 |= WM8904_SYSCLK_SRC;
345 rate = wm8904->fll_fout;
346 break;
347
348 default:
349 dev_err(codec->dev, "System clock not configured\n");
350 return -EINVAL;
351 }
352
353 /* SYSCLK shouldn't be over 13.5MHz */
354 if (rate > 13500000) {
355 clock0 = WM8904_MCLK_DIV;
356 wm8904->sysclk_rate = rate / 2;
357 } else {
358 clock0 = 0;
359 wm8904->sysclk_rate = rate;
360 }
361
362 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
363 clock0);
364
365 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
366 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
367
368 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
369
370 return 0;
371}
372
373static void wm8904_set_drc(struct snd_soc_codec *codec)
374{
b2c812e2 375 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 376 struct wm8904_pdata *pdata = wm8904->pdata;
377 int save, i;
378
379 /* Save any enables; the configuration should clear them. */
380 save = snd_soc_read(codec, WM8904_DRC_0);
381
382 for (i = 0; i < WM8904_DRC_REGS; i++)
383 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
384 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
385
386 /* Reenable the DRC */
387 snd_soc_update_bits(codec, WM8904_DRC_0,
388 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
389}
390
391static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_value *ucontrol)
393{
394 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 395 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 396 struct wm8904_pdata *pdata = wm8904->pdata;
397 int value = ucontrol->value.integer.value[0];
398
399 if (value >= pdata->num_drc_cfgs)
400 return -EINVAL;
401
402 wm8904->drc_cfg = value;
403
404 wm8904_set_drc(codec);
405
406 return 0;
407}
408
409static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 413 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 414
415 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
416
417 return 0;
418}
419
420static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
421{
b2c812e2 422 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 423 struct wm8904_pdata *pdata = wm8904->pdata;
424 int best, best_val, save, i, cfg;
425
426 if (!pdata || !wm8904->num_retune_mobile_texts)
427 return;
428
429 /* Find the version of the currently selected configuration
430 * with the nearest sample rate. */
431 cfg = wm8904->retune_mobile_cfg;
432 best = 0;
433 best_val = INT_MAX;
434 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
435 if (strcmp(pdata->retune_mobile_cfgs[i].name,
436 wm8904->retune_mobile_texts[cfg]) == 0 &&
437 abs(pdata->retune_mobile_cfgs[i].rate
438 - wm8904->fs) < best_val) {
439 best = i;
440 best_val = abs(pdata->retune_mobile_cfgs[i].rate
441 - wm8904->fs);
442 }
443 }
444
445 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
446 pdata->retune_mobile_cfgs[best].name,
447 pdata->retune_mobile_cfgs[best].rate,
448 wm8904->fs);
449
450 /* The EQ will be disabled while reconfiguring it, remember the
451 * current configuration.
452 */
453 save = snd_soc_read(codec, WM8904_EQ1);
454
455 for (i = 0; i < WM8904_EQ_REGS; i++)
456 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
457 pdata->retune_mobile_cfgs[best].regs[i]);
458
459 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
460}
461
462static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 467 struct wm8904_pdata *pdata = wm8904->pdata;
468 int value = ucontrol->value.integer.value[0];
469
470 if (value >= pdata->num_retune_mobile_cfgs)
471 return -EINVAL;
472
473 wm8904->retune_mobile_cfg = value;
474
475 wm8904_set_retune_mobile(codec);
476
477 return 0;
478}
479
480static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
481 struct snd_ctl_elem_value *ucontrol)
482{
483 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 484 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 485
486 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
487
488 return 0;
489}
490
491static int deemph_settings[] = { 0, 32000, 44100, 48000 };
492
493static int wm8904_set_deemph(struct snd_soc_codec *codec)
494{
b2c812e2 495 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 496 int val, i, best;
497
498 /* If we're using deemphasis select the nearest available sample
499 * rate.
500 */
501 if (wm8904->deemph) {
502 best = 1;
503 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
504 if (abs(deemph_settings[i] - wm8904->fs) <
505 abs(deemph_settings[best] - wm8904->fs))
506 best = i;
507 }
508
509 val = best << WM8904_DEEMPH_SHIFT;
510 } else {
511 val = 0;
512 }
513
514 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
515
516 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
517 WM8904_DEEMPH_MASK, val);
518}
519
520static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 524 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199 525
3f343f85
DA		 526 ucontrol->value.enumerated.item[0] = wm8904->deemph;
527 return 0;
a91eb199
MB		 528}
529
530static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_value *ucontrol)
532{
533 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 534 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 535 int deemph = ucontrol->value.enumerated.item[0];
536
537 if (deemph > 1)
538 return -EINVAL;
539
540 wm8904->deemph = deemph;
541
542 return wm8904_set_deemph(codec);
543}
544
545static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
546static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
547static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
548static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
549static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
550
551static const char *input_mode_text[] = {
552 "Single-Ended", "Differential Line", "Differential Mic"
553};
554
555static const struct soc_enum lin_mode =
556 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
557
558static const struct soc_enum rin_mode =
559 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
560
561static const char *hpf_mode_text[] = {
562 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
563};
564
565static const struct soc_enum hpf_mode =
566 SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
567
9b85fc90
MB		 568static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
569 struct snd_ctl_elem_value *ucontrol)
570{
571 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
572 unsigned int val;
573 int ret;
574
575 ret = snd_soc_put_volsw(kcontrol, ucontrol);
576 if (ret < 0)
577 return ret;
578
579 if (ucontrol->value.integer.value[0])
580 val = 0;
581 else
582 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
583
584 snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
585 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
586 val);
587
588 return ret;
589}
590
a91eb199
MB		 591static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
592SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
593 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
594
595SOC_ENUM("Left Caputure Mode", lin_mode),
596SOC_ENUM("Right Capture Mode", rin_mode),
597
598/* No TLV since it depends on mode */
599SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
600 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
601SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
5a7c5f26 602 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
a91eb199
MB		 603
604SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
605SOC_ENUM("High Pass Filter Mode", hpf_mode),
5a68bae2
LPC		 606SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
607 snd_soc_get_volsw, wm8904_adc_osr_put),
a91eb199
MB		 608};
609
610static const char *drc_path_text[] = {
611 "ADC", "DAC"
612};
613
614static const struct soc_enum drc_path =
615 SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text);
616
617static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
618SOC_SINGLE_TLV("Digital Playback Boost Volume",
619 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
620SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
621 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
622
623SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
624 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
625SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
626 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
627SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
628 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
629
630SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
631 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
632SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
633 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
634SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
635 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
636
637SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
638SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
639SOC_ENUM("DRC Path", drc_path),
640SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
641SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
642 wm8904_get_deemph, wm8904_put_deemph),
643};
644
645static const struct snd_kcontrol_new wm8904_snd_controls[] = {
646SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
647 sidetone_tlv),
648};
649
650static const struct snd_kcontrol_new wm8904_eq_controls[] = {
651SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
652SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
653SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
654SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
656};
657
658static int cp_event(struct snd_soc_dapm_widget *w,
659 struct snd_kcontrol *kcontrol, int event)
660{
4c8d620a
TI		 661 if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
662 return -EINVAL;
a91eb199
MB		 663
664 /* Maximum startup time */
665 udelay(500);
666
667 return 0;
668}
669
670static int sysclk_event(struct snd_soc_dapm_widget *w,
671 struct snd_kcontrol *kcontrol, int event)
672{
673 struct snd_soc_codec *codec = w->codec;
b2c812e2 674 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 675
676 switch (event) {
677 case SND_SOC_DAPM_PRE_PMU:
678 /* If we're using the FLL then we only start it when
679 * required; we assume that the configuration has been
680 * done previously and all we need to do is kick it
681 * off.
682 */
683 switch (wm8904->sysclk_src) {
684 case WM8904_CLK_FLL:
685 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
686 WM8904_FLL_OSC_ENA,
687 WM8904_FLL_OSC_ENA);
688
689 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
690 WM8904_FLL_ENA,
691 WM8904_FLL_ENA);
692 break;
693
694 default:
695 break;
696 }
697 break;
698
699 case SND_SOC_DAPM_POST_PMD:
700 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
701 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
702 break;
703 }
704
705 return 0;
706}
707
708static int out_pga_event(struct snd_soc_dapm_widget *w,
709 struct snd_kcontrol *kcontrol, int event)
710{
711 struct snd_soc_codec *codec = w->codec;
b2c812e2 712 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 713 int reg, val;
714 int dcs_mask;
715 int dcs_l, dcs_r;
716 int dcs_l_reg, dcs_r_reg;
717 int timeout;
e4bc6696 718 int pwr_reg;
a91eb199
MB		 719
720 /* This code is shared between HP and LINEOUT; we do all our
721 * power management in stereo pairs to avoid latency issues so
722 * we reuse shift to identify which rather than strcmp() the
723 * name. */
724 reg = w->shift;
725
726 switch (reg) {
727 case WM8904_ANALOGUE_HP_0:
e4bc6696 728 pwr_reg = WM8904_POWER_MANAGEMENT_2;
a91eb199
MB		 729 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
730 dcs_r_reg = WM8904_DC_SERVO_8;
731 dcs_l_reg = WM8904_DC_SERVO_9;
732 dcs_l = 0;
733 dcs_r = 1;
734 break;
735 case WM8904_ANALOGUE_LINEOUT_0:
e4bc6696 736 pwr_reg = WM8904_POWER_MANAGEMENT_3;
a91eb199
MB		 737 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
738 dcs_r_reg = WM8904_DC_SERVO_6;
739 dcs_l_reg = WM8904_DC_SERVO_7;
740 dcs_l = 2;
741 dcs_r = 3;
742 break;
743 default:
8d8bb1ad 744 WARN(1, "Invalid reg %d\n", reg);
a91eb199
MB		 745 return -EINVAL;
746 }
747
748 switch (event) {
e4bc6696
MB		 749 case SND_SOC_DAPM_PRE_PMU:
750 /* Power on the PGAs */
751 snd_soc_update_bits(codec, pwr_reg,
752 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
753 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
754
a91eb199
MB		 755 /* Power on the amplifier */
756 snd_soc_update_bits(codec, reg,
757 WM8904_HPL_ENA | WM8904_HPR_ENA,
758 WM8904_HPL_ENA | WM8904_HPR_ENA);
759
e4bc6696 760
a91eb199
MB		 761 /* Enable the first stage */
762 snd_soc_update_bits(codec, reg,
763 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
764 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
765
766 /* Power up the DC servo */
767 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
768 dcs_mask, dcs_mask);
769
770 /* Either calibrate the DC servo or restore cached state
771 * if we have that.
772 */
773 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
774 dev_dbg(codec->dev, "Restoring DC servo state\n");
775
776 snd_soc_write(codec, dcs_l_reg,
777 wm8904->dcs_state[dcs_l]);
778 snd_soc_write(codec, dcs_r_reg,
779 wm8904->dcs_state[dcs_r]);
780
781 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
782
783 timeout = 20;
784 } else {
785 dev_dbg(codec->dev, "Calibrating DC servo\n");
786
787 snd_soc_write(codec, WM8904_DC_SERVO_1,
788 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
789
790 timeout = 500;
791 }
792
793 /* Wait for DC servo to complete */
794 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
795 do {
796 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
797 if ((val & dcs_mask) == dcs_mask)
798 break;
799
800 msleep(1);
801 } while (--timeout);
802
803 if ((val & dcs_mask) != dcs_mask)
804 dev_warn(codec->dev, "DC servo timed out\n");
805 else
806 dev_dbg(codec->dev, "DC servo ready\n");
807
808 /* Enable the output stage */
809 snd_soc_update_bits(codec, reg,
810 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
811 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
e4bc6696 812 break;
a91eb199 813
e4bc6696 814 case SND_SOC_DAPM_POST_PMU:
a91eb199
MB		 815 /* Unshort the output itself */
816 snd_soc_update_bits(codec, reg,
817 WM8904_HPL_RMV_SHORT |
818 WM8904_HPR_RMV_SHORT,
819 WM8904_HPL_RMV_SHORT |
820 WM8904_HPR_RMV_SHORT);
821
822 break;
823
824 case SND_SOC_DAPM_PRE_PMD:
825 /* Short the output */
826 snd_soc_update_bits(codec, reg,
827 WM8904_HPL_RMV_SHORT |
828 WM8904_HPR_RMV_SHORT, 0);
e4bc6696 829 break;
a91eb199 830
e4bc6696 831 case SND_SOC_DAPM_POST_PMD:
a91eb199
MB		 832 /* Cache the DC servo configuration; this will be
833 * invalidated if we change the configuration. */
834 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
835 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
836
837 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
838 dcs_mask, 0);
839
840 /* Disable the amplifier input and output stages */
841 snd_soc_update_bits(codec, reg,
842 WM8904_HPL_ENA | WM8904_HPR_ENA |
843 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
844 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
845 0);
e4bc6696
MB		 846
847 /* PGAs too */
848 snd_soc_update_bits(codec, pwr_reg,
849 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
850 0);
a91eb199
MB		 851 break;
852 }
853
854 return 0;
855}
856
857static const char *lin_text[] = {
858 "IN1L", "IN2L", "IN3L"
859};
860
861static const struct soc_enum lin_enum =
862 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text);
863
864static const struct snd_kcontrol_new lin_mux =
865 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
866
867static const struct soc_enum lin_inv_enum =
868 SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text);
869
870static const struct snd_kcontrol_new lin_inv_mux =
871 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
872
873static const char *rin_text[] = {
874 "IN1R", "IN2R", "IN3R"
875};
876
877static const struct soc_enum rin_enum =
878 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text);
879
880static const struct snd_kcontrol_new rin_mux =
881 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
882
883static const struct soc_enum rin_inv_enum =
884 SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text);
885
886static const struct snd_kcontrol_new rin_inv_mux =
887 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
888
889static const char *aif_text[] = {
890 "Left", "Right"
891};
892
893static const struct soc_enum aifoutl_enum =
894 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text);
895
896static const struct snd_kcontrol_new aifoutl_mux =
897 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
898
899static const struct soc_enum aifoutr_enum =
900 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text);
901
902static const struct snd_kcontrol_new aifoutr_mux =
903 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
904
905static const struct soc_enum aifinl_enum =
906 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text);
907
908static const struct snd_kcontrol_new aifinl_mux =
909 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
910
911static const struct soc_enum aifinr_enum =
912 SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text);
913
914static const struct snd_kcontrol_new aifinr_mux =
915 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
916
917static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
918SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
919 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
920SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
921SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
922};
923
924static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
925SND_SOC_DAPM_INPUT("IN1L"),
926SND_SOC_DAPM_INPUT("IN1R"),
927SND_SOC_DAPM_INPUT("IN2L"),
928SND_SOC_DAPM_INPUT("IN2R"),
929SND_SOC_DAPM_INPUT("IN3L"),
930SND_SOC_DAPM_INPUT("IN3R"),
931
dcd658c5 932SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
a91eb199
MB		 933
934SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
935SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
936 &lin_inv_mux),
937SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
938SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
939 &rin_inv_mux),
940
941SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
942 NULL, 0),
943SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
944 NULL, 0),
945
946SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
947SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
948
949SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
950SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
951
952SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
953SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
954};
955
956static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
957SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
958SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
959
960SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
961SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
962
963SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
964SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
965
966SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
967 SND_SOC_DAPM_POST_PMU),
968
e4bc6696
MB		 969SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
970SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
a91eb199 971
e4bc6696
MB		 972SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
973SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
a91eb199
MB		 974
975SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
976 0, NULL, 0, out_pga_event,
e4bc6696
MB		 977 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
978 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
a91eb199
MB		 979SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
980 0, NULL, 0, out_pga_event,
e4bc6696
MB		 981 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
982 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
a91eb199
MB		 983
984SND_SOC_DAPM_OUTPUT("HPOUTL"),
985SND_SOC_DAPM_OUTPUT("HPOUTR"),
986SND_SOC_DAPM_OUTPUT("LINEOUTL"),
987SND_SOC_DAPM_OUTPUT("LINEOUTR"),
988};
989
990static const char *out_mux_text[] = {
991 "DAC", "Bypass"
992};
993
994static const struct soc_enum hpl_enum =
995 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text);
996
997static const struct snd_kcontrol_new hpl_mux =
998 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
999
1000static const struct soc_enum hpr_enum =
1001 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text);
1002
1003static const struct snd_kcontrol_new hpr_mux =
1004 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1005
1006static const struct soc_enum linel_enum =
1007 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text);
1008
1009static const struct snd_kcontrol_new linel_mux =
1010 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1011
1012static const struct soc_enum liner_enum =
1013 SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text);
1014
1015static const struct snd_kcontrol_new liner_mux =
e94a093c 1016 SOC_DAPM_ENUM("LINER Mux", liner_enum);
a91eb199
MB		 1017
1018static const char *sidetone_text[] = {
1019 "None", "Left", "Right"
1020};
1021
1022static const struct soc_enum dacl_sidetone_enum =
1023 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text);
1024
1025static const struct snd_kcontrol_new dacl_sidetone_mux =
1026 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1027
1028static const struct soc_enum dacr_sidetone_enum =
1029 SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text);
1030
1031static const struct snd_kcontrol_new dacr_sidetone_mux =
1032 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1033
1034static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1035SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1036SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1037SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1038
1039SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1040SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1041
1042SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1043SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1044SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1045SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1046};
1047
1048static const struct snd_soc_dapm_route core_intercon[] = {
1049 { "CLK_DSP", NULL, "SYSCLK" },
1050 { "TOCLK", NULL, "SYSCLK" },
1051};
1052
1053static const struct snd_soc_dapm_route adc_intercon[] = {
1054 { "Left Capture Mux", "IN1L", "IN1L" },
1055 { "Left Capture Mux", "IN2L", "IN2L" },
1056 { "Left Capture Mux", "IN3L", "IN3L" },
1057
1058 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1059 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1060 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1061
1062 { "Right Capture Mux", "IN1R", "IN1R" },
1063 { "Right Capture Mux", "IN2R", "IN2R" },
1064 { "Right Capture Mux", "IN3R", "IN3R" },
1065
1066 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1067 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1068 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1069
1070 { "Left Capture PGA", NULL, "Left Capture Mux" },
1071 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1072
1073 { "Right Capture PGA", NULL, "Right Capture Mux" },
1074 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1075
1076 { "AIFOUTL", "Left", "ADCL" },
1077 { "AIFOUTL", "Right", "ADCR" },
1078 { "AIFOUTR", "Left", "ADCL" },
1079 { "AIFOUTR", "Right", "ADCR" },
1080
1081 { "ADCL", NULL, "CLK_DSP" },
1082 { "ADCL", NULL, "Left Capture PGA" },
1083
1084 { "ADCR", NULL, "CLK_DSP" },
1085 { "ADCR", NULL, "Right Capture PGA" },
1086};
1087
1088static const struct snd_soc_dapm_route dac_intercon[] = {
1089 { "DACL", "Right", "AIFINR" },
1090 { "DACL", "Left", "AIFINL" },
1091 { "DACL", NULL, "CLK_DSP" },
1092
1093 { "DACR", "Right", "AIFINR" },
1094 { "DACR", "Left", "AIFINL" },
1095 { "DACR", NULL, "CLK_DSP" },
1096
1097 { "Charge pump", NULL, "SYSCLK" },
1098
1099 { "Headphone Output", NULL, "HPL PGA" },
1100 { "Headphone Output", NULL, "HPR PGA" },
1101 { "Headphone Output", NULL, "Charge pump" },
1102 { "Headphone Output", NULL, "TOCLK" },
1103
1104 { "Line Output", NULL, "LINEL PGA" },
1105 { "Line Output", NULL, "LINER PGA" },
1106 { "Line Output", NULL, "Charge pump" },
1107 { "Line Output", NULL, "TOCLK" },
1108
1109 { "HPOUTL", NULL, "Headphone Output" },
1110 { "HPOUTR", NULL, "Headphone Output" },
1111
1112 { "LINEOUTL", NULL, "Line Output" },
1113 { "LINEOUTR", NULL, "Line Output" },
1114};
1115
1116static const struct snd_soc_dapm_route wm8904_intercon[] = {
1117 { "Left Sidetone", "Left", "ADCL" },
1118 { "Left Sidetone", "Right", "ADCR" },
1119 { "DACL", NULL, "Left Sidetone" },
1120
1121 { "Right Sidetone", "Left", "ADCL" },
1122 { "Right Sidetone", "Right", "ADCR" },
1123 { "DACR", NULL, "Right Sidetone" },
1124
1125 { "Left Bypass", NULL, "Class G" },
1126 { "Left Bypass", NULL, "Left Capture PGA" },
1127
1128 { "Right Bypass", NULL, "Class G" },
1129 { "Right Bypass", NULL, "Right Capture PGA" },
1130
1131 { "HPL Mux", "DAC", "DACL" },
1132 { "HPL Mux", "Bypass", "Left Bypass" },
1133
1134 { "HPR Mux", "DAC", "DACR" },
1135 { "HPR Mux", "Bypass", "Right Bypass" },
1136
1137 { "LINEL Mux", "DAC", "DACL" },
1138 { "LINEL Mux", "Bypass", "Left Bypass" },
1139
1140 { "LINER Mux", "DAC", "DACR" },
1141 { "LINER Mux", "Bypass", "Right Bypass" },
1142
1143 { "HPL PGA", NULL, "HPL Mux" },
1144 { "HPR PGA", NULL, "HPR Mux" },
1145
1146 { "LINEL PGA", NULL, "LINEL Mux" },
1147 { "LINER PGA", NULL, "LINER Mux" },
1148};
1149
8c126474
MB		 1150static const struct snd_soc_dapm_route wm8912_intercon[] = {
1151 { "HPL PGA", NULL, "DACL" },
1152 { "HPR PGA", NULL, "DACR" },
1153
1154 { "LINEL PGA", NULL, "DACL" },
1155 { "LINER PGA", NULL, "DACR" },
1156};
1157
a91eb199
MB		 1158static int wm8904_add_widgets(struct snd_soc_codec *codec)
1159{
b2c812e2 1160 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
ce6120cc 1161 struct snd_soc_dapm_context *dapm = &codec->dapm;
a91eb199 1162
ce6120cc 1163 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
a91eb199 1164 ARRAY_SIZE(wm8904_core_dapm_widgets));
ce6120cc 1165 snd_soc_dapm_add_routes(dapm, core_intercon,
a91eb199 1166 ARRAY_SIZE(core_intercon));
8c126474
MB		 1167
1168 switch (wm8904->devtype) {
1169 case WM8904:
022658be 1170 snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
8c126474 1171 ARRAY_SIZE(wm8904_adc_snd_controls));
022658be 1172 snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
8c126474 1173 ARRAY_SIZE(wm8904_dac_snd_controls));
022658be 1174 snd_soc_add_codec_controls(codec, wm8904_snd_controls,
8c126474
MB		 1175 ARRAY_SIZE(wm8904_snd_controls));
1176
ce6120cc 1177 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
8c126474 1178 ARRAY_SIZE(wm8904_adc_dapm_widgets));
ce6120cc 1179 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
8c126474 1180 ARRAY_SIZE(wm8904_dac_dapm_widgets));
ce6120cc 1181 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
8c126474
MB		 1182 ARRAY_SIZE(wm8904_dapm_widgets));
1183
ce6120cc 1184 snd_soc_dapm_add_routes(dapm, adc_intercon,
8c126474 1185 ARRAY_SIZE(adc_intercon));
ce6120cc 1186 snd_soc_dapm_add_routes(dapm, dac_intercon,
8c126474 1187 ARRAY_SIZE(dac_intercon));
ce6120cc 1188 snd_soc_dapm_add_routes(dapm, wm8904_intercon,
8c126474
MB		 1189 ARRAY_SIZE(wm8904_intercon));
1190 break;
1191
1192 case WM8912:
022658be 1193 snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
8c126474
MB		 1194 ARRAY_SIZE(wm8904_dac_snd_controls));
1195
ce6120cc 1196 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
8c126474
MB		 1197 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1198
ce6120cc 1199 snd_soc_dapm_add_routes(dapm, dac_intercon,
8c126474 1200 ARRAY_SIZE(dac_intercon));
ce6120cc 1201 snd_soc_dapm_add_routes(dapm, wm8912_intercon,
8c126474
MB		 1202 ARRAY_SIZE(wm8912_intercon));
1203 break;
1204 }
a91eb199 1205
a91eb199
MB		 1206 return 0;
1207}
1208
1209static struct {
1210 int ratio;
1211 unsigned int clk_sys_rate;
1212} clk_sys_rates[] = {
1213 { 64, 0 },
1214 { 128, 1 },
1215 { 192, 2 },
1216 { 256, 3 },
1217 { 384, 4 },
1218 { 512, 5 },
1219 { 786, 6 },
1220 { 1024, 7 },
1221 { 1408, 8 },
1222 { 1536, 9 },
1223};
1224
1225static struct {
1226 int rate;
1227 int sample_rate;
1228} sample_rates[] = {
1229 { 8000, 0 },
1230 { 11025, 1 },
1231 { 12000, 1 },
1232 { 16000, 2 },
1233 { 22050, 3 },
1234 { 24000, 3 },
1235 { 32000, 4 },
1236 { 44100, 5 },
1237 { 48000, 5 },
1238};
1239
1240static struct {
1241 int div; /* *10 due to .5s */
1242 int bclk_div;
1243} bclk_divs[] = {
1244 { 10, 0 },
1245 { 15, 1 },
1246 { 20, 2 },
1247 { 30, 3 },
1248 { 40, 4 },
1249 { 50, 5 },
1250 { 55, 6 },
1251 { 60, 7 },
1252 { 80, 8 },
1253 { 100, 9 },
1254 { 110, 10 },
1255 { 120, 11 },
1256 { 160, 12 },
1257 { 200, 13 },
1258 { 220, 14 },
1259 { 240, 16 },
1260 { 200, 17 },
1261 { 320, 18 },
1262 { 440, 19 },
1263 { 480, 20 },
1264};
1265
1266
1267static int wm8904_hw_params(struct snd_pcm_substream *substream,
1268 struct snd_pcm_hw_params *params,
1269 struct snd_soc_dai *dai)
1270{
1271 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1272 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1273 int ret, i, best, best_val, cur_val;
1274 unsigned int aif1 = 0;
1275 unsigned int aif2 = 0;
1276 unsigned int aif3 = 0;
1277 unsigned int clock1 = 0;
1278 unsigned int dac_digital1 = 0;
1279
1280 /* What BCLK do we need? */
1281 wm8904->fs = params_rate(params);
1282 if (wm8904->tdm_slots) {
1283 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1284 wm8904->tdm_slots, wm8904->tdm_width);
1285 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1286 wm8904->tdm_width, 2,
1287 wm8904->tdm_slots);
1288 } else {
1289 wm8904->bclk = snd_soc_params_to_bclk(params);
1290 }
1291
56927eb0
MB		 1292 switch (params_format(params)) {
1293 case SNDRV_PCM_FORMAT_S16_LE:
1294 break;
1295 case SNDRV_PCM_FORMAT_S20_3LE:
1296 aif1 |= 0x40;
1297 break;
1298 case SNDRV_PCM_FORMAT_S24_LE:
1299 aif1 |= 0x80;
1300 break;
1301 case SNDRV_PCM_FORMAT_S32_LE:
1302 aif1 |= 0xc0;
1303 break;
1304 default:
1305 return -EINVAL;
1306 }
1307
1308
a91eb199
MB		 1309 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1310
1311 ret = wm8904_configure_clocking(codec);
1312 if (ret != 0)
1313 return ret;
1314
1315 /* Select nearest CLK_SYS_RATE */
1316 best = 0;
1317 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1318 - wm8904->fs);
1319 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1320 cur_val = abs((wm8904->sysclk_rate /
ef995e3a 1321 clk_sys_rates[i].ratio) - wm8904->fs);
a91eb199
MB		 1322 if (cur_val < best_val) {
1323 best = i;
1324 best_val = cur_val;
1325 }
1326 }
1327 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1328 clk_sys_rates[best].ratio);
1329 clock1 |= (clk_sys_rates[best].clk_sys_rate
1330 << WM8904_CLK_SYS_RATE_SHIFT);
1331
1332 /* SAMPLE_RATE */
1333 best = 0;
1334 best_val = abs(wm8904->fs - sample_rates[0].rate);
1335 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1336 /* Closest match */
1337 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1338 if (cur_val < best_val) {
1339 best = i;
1340 best_val = cur_val;
1341 }
1342 }
1343 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1344 sample_rates[best].rate);
1345 clock1 |= (sample_rates[best].sample_rate
1346 << WM8904_SAMPLE_RATE_SHIFT);
1347
1348 /* Enable sloping stopband filter for low sample rates */
1349 if (wm8904->fs <= 24000)
1350 dac_digital1 |= WM8904_DAC_SB_FILT;
1351
1352 /* BCLK_DIV */
1353 best = 0;
1354 best_val = INT_MAX;
1355 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1356 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1357 - wm8904->bclk;
1358 if (cur_val < 0) /* Table is sorted */
1359 break;
1360 if (cur_val < best_val) {
1361 best = i;
1362 best_val = cur_val;
1363 }
1364 }
1365 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1366 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1367 bclk_divs[best].div, wm8904->bclk);
1368 aif2 |= bclk_divs[best].bclk_div;
1369
1370 /* LRCLK is a simple fraction of BCLK */
1371 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1372 aif3 |= wm8904->bclk / wm8904->fs;
1373
1374 /* Apply the settings */
1375 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1376 WM8904_DAC_SB_FILT, dac_digital1);
1377 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1378 WM8904_AIF_WL_MASK, aif1);
1379 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1380 WM8904_BCLK_DIV_MASK, aif2);
1381 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1382 WM8904_LRCLK_RATE_MASK, aif3);
1383 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1384 WM8904_SAMPLE_RATE_MASK |
1385 WM8904_CLK_SYS_RATE_MASK, clock1);
1386
1387 /* Update filters for the new settings */
1388 wm8904_set_retune_mobile(codec);
1389 wm8904_set_deemph(codec);
1390
1391 return 0;
1392}
1393
1394
1395static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1396 unsigned int freq, int dir)
1397{
1398 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1399 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1400
1401 switch (clk_id) {
1402 case WM8904_CLK_MCLK:
1403 priv->sysclk_src = clk_id;
1404 priv->mclk_rate = freq;
1405 break;
1406
1407 case WM8904_CLK_FLL:
1408 priv->sysclk_src = clk_id;
1409 break;
1410
1411 default:
1412 return -EINVAL;
1413 }
1414
1415 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1416
1417 wm8904_configure_clocking(codec);
1418
1419 return 0;
1420}
1421
1422static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1423{
1424 struct snd_soc_codec *codec = dai->codec;
1425 unsigned int aif1 = 0;
1426 unsigned int aif3 = 0;
1427
1428 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1429 case SND_SOC_DAIFMT_CBS_CFS:
1430 break;
1431 case SND_SOC_DAIFMT_CBS_CFM:
1432 aif3 |= WM8904_LRCLK_DIR;
1433 break;
1434 case SND_SOC_DAIFMT_CBM_CFS:
1435 aif1 |= WM8904_BCLK_DIR;
1436 break;
1437 case SND_SOC_DAIFMT_CBM_CFM:
1438 aif1 |= WM8904_BCLK_DIR;
1439 aif3 |= WM8904_LRCLK_DIR;
1440 break;
1441 default:
1442 return -EINVAL;
1443 }
1444
1445 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1446 case SND_SOC_DAIFMT_DSP_B:
f0199bc5 1447 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
a91eb199
MB		 1448 case SND_SOC_DAIFMT_DSP_A:
1449 aif1 |= 0x3;
1450 break;
1451 case SND_SOC_DAIFMT_I2S:
1452 aif1 |= 0x2;
1453 break;
1454 case SND_SOC_DAIFMT_RIGHT_J:
1455 break;
1456 case SND_SOC_DAIFMT_LEFT_J:
1457 aif1 |= 0x1;
1458 break;
1459 default:
1460 return -EINVAL;
1461 }
1462
1463 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1464 case SND_SOC_DAIFMT_DSP_A:
1465 case SND_SOC_DAIFMT_DSP_B:
1466 /* frame inversion not valid for DSP modes */
1467 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1468 case SND_SOC_DAIFMT_NB_NF:
1469 break;
1470 case SND_SOC_DAIFMT_IB_NF:
1471 aif1 |= WM8904_AIF_BCLK_INV;
1472 break;
1473 default:
1474 return -EINVAL;
1475 }
1476 break;
1477
1478 case SND_SOC_DAIFMT_I2S:
1479 case SND_SOC_DAIFMT_RIGHT_J:
1480 case SND_SOC_DAIFMT_LEFT_J:
1481 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1482 case SND_SOC_DAIFMT_NB_NF:
1483 break;
1484 case SND_SOC_DAIFMT_IB_IF:
1485 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1486 break;
1487 case SND_SOC_DAIFMT_IB_NF:
1488 aif1 |= WM8904_AIF_BCLK_INV;
1489 break;
1490 case SND_SOC_DAIFMT_NB_IF:
1491 aif1 |= WM8904_AIF_LRCLK_INV;
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1502 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1503 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1504 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1505 WM8904_LRCLK_DIR, aif3);
1506
1507 return 0;
1508}
1509
1510
1511static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1512 unsigned int rx_mask, int slots, int slot_width)
1513{
1514 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1515 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1516 int aif1 = 0;
1517
1518 /* Don't need to validate anything if we're turning off TDM */
1519 if (slots == 0)
1520 goto out;
1521
1522 /* Note that we allow configurations we can't handle ourselves -
1523 * for example, we can generate clocks for slots 2 and up even if
1524 * we can't use those slots ourselves.
1525 */
1526 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1527
1528 switch (rx_mask) {
1529 case 3:
1530 break;
1531 case 0xc:
1532 aif1 |= WM8904_AIFADC_TDM_CHAN;
1533 break;
1534 default:
1535 return -EINVAL;
1536 }
1537
1538
1539 switch (tx_mask) {
1540 case 3:
1541 break;
1542 case 0xc:
1543 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1544 break;
1545 default:
1546 return -EINVAL;
1547 }
1548
1549out:
1550 wm8904->tdm_width = slot_width;
1551 wm8904->tdm_slots = slots / 2;
1552
1553 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1554 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1555 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1556
1557 return 0;
1558}
1559
1560struct _fll_div {
1561 u16 fll_fratio;
1562 u16 fll_outdiv;
1563 u16 fll_clk_ref_div;
1564 u16 n;
1565 u16 k;
1566};
1567
1568/* The size in bits of the FLL divide multiplied by 10
1569 * to allow rounding later */
1570#define FIXED_FLL_SIZE ((1 << 16) * 10)
1571
1572static struct {
1573 unsigned int min;
1574 unsigned int max;
1575 u16 fll_fratio;
1576 int ratio;
1577} fll_fratios[] = {
1578 { 0, 64000, 4, 16 },
1579 { 64000, 128000, 3, 8 },
1580 { 128000, 256000, 2, 4 },
1581 { 256000, 1000000, 1, 2 },
1582 { 1000000, 13500000, 0, 1 },
1583};
1584
1585static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1586 unsigned int Fout)
1587{
1588 u64 Kpart;
1589 unsigned int K, Ndiv, Nmod, target;
1590 unsigned int div;
1591 int i;
1592
1593 /* Fref must be <=13.5MHz */
1594 div = 1;
1595 fll_div->fll_clk_ref_div = 0;
1596 while ((Fref / div) > 13500000) {
1597 div *= 2;
1598 fll_div->fll_clk_ref_div++;
1599
1600 if (div > 8) {
1601 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1602 Fref);
1603 return -EINVAL;
1604 }
1605 }
1606
1607 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1608
1609 /* Apply the division for our remaining calculations */
1610 Fref /= div;
1611
1612 /* Fvco should be 90-100MHz; don't check the upper bound */
1613 div = 4;
1614 while (Fout * div < 90000000) {
1615 div++;
1616 if (div > 64) {
1617 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1618 Fout);
1619 return -EINVAL;
1620 }
1621 }
1622 target = Fout * div;
1623 fll_div->fll_outdiv = div - 1;
1624
1625 pr_debug("Fvco=%dHz\n", target);
1626
25985edc 1627 /* Find an appropriate FLL_FRATIO and factor it out of the target */
a91eb199
MB		 1628 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1629 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1630 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1631 target /= fll_fratios[i].ratio;
1632 break;
1633 }
1634 }
1635 if (i == ARRAY_SIZE(fll_fratios)) {
1636 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1637 return -EINVAL;
1638 }
1639
1640 /* Now, calculate N.K */
1641 Ndiv = target / Fref;
1642
1643 fll_div->n = Ndiv;
1644 Nmod = target % Fref;
1645 pr_debug("Nmod=%d\n", Nmod);
1646
1647 /* Calculate fractional part - scale up so we can round. */
1648 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1649
1650 do_div(Kpart, Fref);
1651
1652 K = Kpart & 0xFFFFFFFF;
1653
1654 if ((K % 10) >= 5)
1655 K += 5;
1656
1657 /* Move down to proper range now rounding is done */
1658 fll_div->k = K / 10;
1659
1660 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1661 fll_div->n, fll_div->k,
1662 fll_div->fll_fratio, fll_div->fll_outdiv,
1663 fll_div->fll_clk_ref_div);
1664
1665 return 0;
1666}
1667
1668static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1669 unsigned int Fref, unsigned int Fout)
1670{
1671 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1672 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1673 struct _fll_div fll_div;
1674 int ret, val;
1675 int clock2, fll1;
1676
1677 /* Any change? */
1678 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1679 Fout == wm8904->fll_fout)
1680 return 0;
1681
18240b67
MB		 1682 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1683
a91eb199
MB		 1684 if (Fout == 0) {
1685 dev_dbg(codec->dev, "FLL disabled\n");
1686
1687 wm8904->fll_fref = 0;
1688 wm8904->fll_fout = 0;
1689
1690 /* Gate SYSCLK to avoid glitches */
1691 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1692 WM8904_CLK_SYS_ENA, 0);
1693
1694 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1695 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1696
1697 goto out;
1698 }
1699
1700 /* Validate the FLL ID */
1701 switch (source) {
1702 case WM8904_FLL_MCLK:
1703 case WM8904_FLL_LRCLK:
1704 case WM8904_FLL_BCLK:
1705 ret = fll_factors(&fll_div, Fref, Fout);
1706 if (ret != 0)
1707 return ret;
1708 break;
1709
1710 case WM8904_FLL_FREE_RUNNING:
1711 dev_dbg(codec->dev, "Using free running FLL\n");
1712 /* Force 12MHz and output/4 for now */
1713 Fout = 12000000;
1714 Fref = 12000000;
1715
1716 memset(&fll_div, 0, sizeof(fll_div));
1717 fll_div.fll_outdiv = 3;
1718 break;
1719
1720 default:
1721 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1722 return -EINVAL;
1723 }
1724
1725 /* Save current state then disable the FLL and SYSCLK to avoid
1726 * misclocking */
a91eb199
MB		 1727 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1728 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1729 WM8904_CLK_SYS_ENA, 0);
1730 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1731 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1732
1733 /* Unlock forced oscilator control to switch it on/off */
1734 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1735 WM8904_USER_KEY, WM8904_USER_KEY);
1736
1737 if (fll_id == WM8904_FLL_FREE_RUNNING) {
1738 val = WM8904_FLL_FRC_NCO;
1739 } else {
1740 val = 0;
1741 }
1742
1743 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1744 val);
1745 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1746 WM8904_USER_KEY, 0);
1747
1748 switch (fll_id) {
1749 case WM8904_FLL_MCLK:
1750 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1751 WM8904_FLL_CLK_REF_SRC_MASK, 0);
1752 break;
1753
1754 case WM8904_FLL_LRCLK:
1755 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1756 WM8904_FLL_CLK_REF_SRC_MASK, 1);
1757 break;
1758
1759 case WM8904_FLL_BCLK:
1760 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1761 WM8904_FLL_CLK_REF_SRC_MASK, 2);
1762 break;
1763 }
1764
1765 if (fll_div.k)
1766 val = WM8904_FLL_FRACN_ENA;
1767 else
1768 val = 0;
1769 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1770 WM8904_FLL_FRACN_ENA, val);
1771
1772 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
1773 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1774 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1775 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1776
1777 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
1778
1779 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1780 fll_div.n << WM8904_FLL_N_SHIFT);
1781
1782 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1783 WM8904_FLL_CLK_REF_DIV_MASK,
1784 fll_div.fll_clk_ref_div
1785 << WM8904_FLL_CLK_REF_DIV_SHIFT);
1786
1787 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1788
1789 wm8904->fll_fref = Fref;
1790 wm8904->fll_fout = Fout;
1791 wm8904->fll_src = source;
1792
1793 /* Enable the FLL if it was previously active */
1794 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1795 WM8904_FLL_OSC_ENA, fll1);
1796 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1797 WM8904_FLL_ENA, fll1);
1798
1799out:
1800 /* Reenable SYSCLK if it was previously active */
1801 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1802 WM8904_CLK_SYS_ENA, clock2);
1803
1804 return 0;
1805}
1806
1807static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1808{
1809 struct snd_soc_codec *codec = codec_dai->codec;
1810 int val;
1811
1812 if (mute)
1813 val = WM8904_DAC_MUTE;
1814 else
1815 val = 0;
1816
1817 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1818
1819 return 0;
1820}
1821
1822static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1823 enum snd_soc_bias_level level)
1824{
b2c812e2 1825 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
c1334218 1826 int ret;
a91eb199
MB		 1827
1828 switch (level) {
1829 case SND_SOC_BIAS_ON:
1830 break;
1831
1832 case SND_SOC_BIAS_PREPARE:
1833 /* VMID resistance 2*50k */
1834 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1835 WM8904_VMID_RES_MASK,
1836 0x1 << WM8904_VMID_RES_SHIFT);
1837
1838 /* Normal bias current */
1839 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1840 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1841 break;
1842
1843 case SND_SOC_BIAS_STANDBY:
ce6120cc 1844 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
a91eb199
MB		 1845 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1846 wm8904->supplies);
1847 if (ret != 0) {
1848 dev_err(codec->dev,
1849 "Failed to enable supplies: %d\n",
1850 ret);
1851 return ret;
1852 }
1853
c1b88ee2 1854 regcache_cache_only(wm8904->regmap, false);
84d0d831 1855 regcache_sync(wm8904->regmap);
a91eb199
MB		 1856
1857 /* Enable bias */
1858 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1859 WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1860
1861 /* Enable VMID, VMID buffering, 2*5k resistance */
1862 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1863 WM8904_VMID_ENA |
1864 WM8904_VMID_RES_MASK,
1865 WM8904_VMID_ENA |
1866 0x3 << WM8904_VMID_RES_SHIFT);
1867
1868 /* Let VMID ramp */
1869 msleep(1);
1870 }
1871
1872 /* Maintain VMID with 2*250k */
1873 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1874 WM8904_VMID_RES_MASK,
1875 0x2 << WM8904_VMID_RES_SHIFT);
1876
1877 /* Bias current *0.5 */
1878 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1879 WM8904_ISEL_MASK, 0);
1880 break;
1881
1882 case SND_SOC_BIAS_OFF:
1883 /* Turn off VMID */
1884 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1885 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1886
1887 /* Stop bias generation */
1888 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1889 WM8904_BIAS_ENA, 0);
1890
c1b88ee2
MB		 1891 regcache_cache_only(wm8904->regmap, true);
1892 regcache_mark_dirty(wm8904->regmap);
c1334218 1893
a91eb199
MB		 1894 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1895 wm8904->supplies);
1896 break;
1897 }
ce6120cc 1898 codec->dapm.bias_level = level;
a91eb199
MB		 1899 return 0;
1900}
1901
1902#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1903
1904#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1905 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1906
85e7652d 1907static const struct snd_soc_dai_ops wm8904_dai_ops = {
a91eb199
MB		 1908 .set_sysclk = wm8904_set_sysclk,
1909 .set_fmt = wm8904_set_fmt,
1910 .set_tdm_slot = wm8904_set_tdm_slot,
1911 .set_pll = wm8904_set_fll,
1912 .hw_params = wm8904_hw_params,
1913 .digital_mute = wm8904_digital_mute,
1914};
1915
f0fba2ad
LG		 1916static struct snd_soc_dai_driver wm8904_dai = {
1917 .name = "wm8904-hifi",
a91eb199
MB		 1918 .playback = {
1919 .stream_name = "Playback",
1920 .channels_min = 2,
1921 .channels_max = 2,
1922 .rates = WM8904_RATES,
1923 .formats = WM8904_FORMATS,
1924 },
1925 .capture = {
1926 .stream_name = "Capture",
1927 .channels_min = 2,
1928 .channels_max = 2,
1929 .rates = WM8904_RATES,
1930 .formats = WM8904_FORMATS,
1931 },
1932 .ops = &wm8904_dai_ops,
1933 .symmetric_rates = 1,
1934};
a91eb199 1935
f0fba2ad 1936static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
a91eb199 1937{
f0fba2ad 1938 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1939 struct wm8904_pdata *pdata = wm8904->pdata;
1940 struct snd_kcontrol_new control =
1941 SOC_ENUM_EXT("EQ Mode",
1942 wm8904->retune_mobile_enum,
1943 wm8904_get_retune_mobile_enum,
1944 wm8904_put_retune_mobile_enum);
1945 int ret, i, j;
1946 const char **t;
1947
1948 /* We need an array of texts for the enum API but the number
1949 * of texts is likely to be less than the number of
1950 * configurations due to the sample rate dependency of the
1951 * configurations. */
1952 wm8904->num_retune_mobile_texts = 0;
1953 wm8904->retune_mobile_texts = NULL;
1954 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
1955 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
1956 if (strcmp(pdata->retune_mobile_cfgs[i].name,
1957 wm8904->retune_mobile_texts[j]) == 0)
1958 break;
1959 }
1960
1961 if (j != wm8904->num_retune_mobile_texts)
1962 continue;
1963
1964 /* Expand the array... */
1965 t = krealloc(wm8904->retune_mobile_texts,
1966 sizeof(char *) *
1967 (wm8904->num_retune_mobile_texts + 1),
1968 GFP_KERNEL);
1969 if (t == NULL)
1970 continue;
1971
1972 /* ...store the new entry... */
1973 t[wm8904->num_retune_mobile_texts] =
1974 pdata->retune_mobile_cfgs[i].name;
1975
1976 /* ...and remember the new version. */
1977 wm8904->num_retune_mobile_texts++;
1978 wm8904->retune_mobile_texts = t;
1979 }
1980
1981 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
1982 wm8904->num_retune_mobile_texts);
1983
1984 wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts;
1985 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
1986
022658be 1987 ret = snd_soc_add_codec_controls(codec, &control, 1);
a91eb199 1988 if (ret != 0)
f0fba2ad 1989 dev_err(codec->dev,
a91eb199
MB		 1990 "Failed to add ReTune Mobile control: %d\n", ret);
1991}
1992
f0fba2ad 1993static void wm8904_handle_pdata(struct snd_soc_codec *codec)
a91eb199 1994{
f0fba2ad 1995 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1996 struct wm8904_pdata *pdata = wm8904->pdata;
1997 int ret, i;
1998
1999 if (!pdata) {
022658be 2000 snd_soc_add_codec_controls(codec, wm8904_eq_controls,
a91eb199
MB		 2001 ARRAY_SIZE(wm8904_eq_controls));
2002 return;
2003 }
2004
2005 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2006
2007 if (pdata->num_drc_cfgs) {
2008 struct snd_kcontrol_new control =
2009 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2010 wm8904_get_drc_enum, wm8904_put_drc_enum);
2011
2012 /* We need an array of texts for the enum API */
2013 wm8904->drc_texts = kmalloc(sizeof(char *)
2014 * pdata->num_drc_cfgs, GFP_KERNEL);
2015 if (!wm8904->drc_texts) {
f0fba2ad 2016 dev_err(codec->dev,
a91eb199
MB		 2017 "Failed to allocate %d DRC config texts\n",
2018 pdata->num_drc_cfgs);
2019 return;
2020 }
2021
2022 for (i = 0; i < pdata->num_drc_cfgs; i++)
2023 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2024
2025 wm8904->drc_enum.max = pdata->num_drc_cfgs;
2026 wm8904->drc_enum.texts = wm8904->drc_texts;
2027
022658be 2028 ret = snd_soc_add_codec_controls(codec, &control, 1);
a91eb199 2029 if (ret != 0)
f0fba2ad 2030 dev_err(codec->dev,
a91eb199
MB		 2031 "Failed to add DRC mode control: %d\n", ret);
2032
2033 wm8904_set_drc(codec);
2034 }
2035
2036 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2037 pdata->num_retune_mobile_cfgs);
2038
2039 if (pdata->num_retune_mobile_cfgs)
f0fba2ad 2040 wm8904_handle_retune_mobile_pdata(codec);
a91eb199 2041 else
022658be 2042 snd_soc_add_codec_controls(codec, wm8904_eq_controls,
a91eb199
MB		 2043 ARRAY_SIZE(wm8904_eq_controls));
2044}
2045
a91eb199 2046
f0fba2ad 2047static int wm8904_probe(struct snd_soc_codec *codec)
a91eb199 2048{
f0fba2ad 2049 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
725e7a7b 2050 int ret;
a91eb199 2051
84d0d831 2052 codec->control_data = wm8904->regmap;
a91eb199 2053
8c126474
MB		 2054 switch (wm8904->devtype) {
2055 case WM8904:
2056 break;
2057 case WM8912:
2058 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2059 break;
2060 default:
2061 dev_err(codec->dev, "Unknown device type %d\n",
2062 wm8904->devtype);
f0fba2ad 2063 return -EINVAL;
8c126474
MB		 2064 }
2065
84d0d831 2066 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
a91eb199
MB		 2067 if (ret != 0) {
2068 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 2069 return ret;
a91eb199
MB		 2070 }
2071
f0fba2ad 2072 wm8904_handle_pdata(codec);
a91eb199 2073
f0fba2ad 2074 wm8904_add_widgets(codec);
a91eb199
MB		 2075
2076 return 0;
a91eb199
MB		 2077}
2078
f0fba2ad 2079static int wm8904_remove(struct snd_soc_codec *codec)
a91eb199 2080{
f0fba2ad
LG		 2081 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2082
cd70978c
AL		 2083 kfree(wm8904->retune_mobile_texts);
2084 kfree(wm8904->drc_texts);
f0fba2ad
LG		 2085
2086 return 0;
a91eb199
MB		 2087}
2088
f0fba2ad
LG		 2089static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
2090 .probe = wm8904_probe,
2091 .remove = wm8904_remove,
f0fba2ad 2092 .set_bias_level = wm8904_set_bias_level,
eb3032f8 2093 .idle_bias_off = true,
84d0d831
MB		 2094};
2095
2096static const struct regmap_config wm8904_regmap = {
2097 .reg_bits = 8,
2098 .val_bits = 16,
2099
2100 .max_register = WM8904_MAX_REGISTER,
2101 .volatile_reg = wm8904_volatile_register,
2102 .readable_reg = wm8904_readable_register,
2103
2104 .cache_type = REGCACHE_RBTREE,
2105 .reg_defaults = wm8904_reg_defaults,
2106 .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
f0fba2ad
LG		 2107};
2108
7a79e94e
BP		 2109static int wm8904_i2c_probe(struct i2c_client *i2c,
2110 const struct i2c_device_id *id)
a91eb199
MB		 2111{
2112 struct wm8904_priv *wm8904;
03862cf6
MB		 2113 unsigned int val;
2114 int ret, i;
a91eb199 2115
93e26d4e
MB		 2116 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2117 GFP_KERNEL);
a91eb199
MB		 2118 if (wm8904 == NULL)
2119 return -ENOMEM;
2120
d633edd9 2121 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
84d0d831
MB		 2122 if (IS_ERR(wm8904->regmap)) {
2123 ret = PTR_ERR(wm8904->regmap);
2124 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2125 ret);
2126 return ret;
2127 }
2128
8c126474 2129 wm8904->devtype = id->driver_data;
a91eb199 2130 i2c_set_clientdata(i2c, wm8904);
a91eb199
MB		 2131 wm8904->pdata = i2c->dev.platform_data;
2132
03862cf6
MB		 2133 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2134 wm8904->supplies[i].supply = wm8904_supply_names[i];
2135
2136 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2137 wm8904->supplies);
2138 if (ret != 0) {
2139 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2140 return ret;
2141 }
2142
2143 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2144 wm8904->supplies);
2145 if (ret != 0) {
2146 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2147 return ret;
2148 }
2149
2150 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2151 if (ret < 0) {
2152 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2153 goto err_enable;
2154 }
2155 if (val != 0x8904) {
2156 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2157 ret = -EINVAL;
2158 goto err_enable;
2159 }
2160
2161 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2162 if (ret < 0) {
2163 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2164 ret);
2165 goto err_enable;
2166 }
2167 dev_info(&i2c->dev, "revision %c\n", val + 'A');
2168
2169 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2170 if (ret < 0) {
2171 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2172 goto err_enable;
2173 }
2174
725e7a7b
MB		 2175 /* Change some default settings - latch VU and enable ZC */
2176 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2177 WM8904_ADC_VU, WM8904_ADC_VU);
2178 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2179 WM8904_ADC_VU, WM8904_ADC_VU);
2180 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2181 WM8904_DAC_VU, WM8904_DAC_VU);
2182 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2183 WM8904_DAC_VU, WM8904_DAC_VU);
2184 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2185 WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2186 WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2187 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2188 WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2189 WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2190 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2191 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2192 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2193 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2194 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2195 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2196 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2197 WM8904_SR_MODE, 0);
2198
2199 /* Apply configuration from the platform data. */
2200 if (wm8904->pdata) {
2201 for (i = 0; i < WM8904_GPIO_REGS; i++) {
2202 if (!wm8904->pdata->gpio_cfg[i])
2203 continue;
2204
2205 regmap_update_bits(wm8904->regmap,
2206 WM8904_GPIO_CONTROL_1 + i,
2207 0xffff,
2208 wm8904->pdata->gpio_cfg[i]);
2209 }
2210
2211 /* Zero is the default value for these anyway */
2212 for (i = 0; i < WM8904_MIC_REGS; i++)
2213 regmap_update_bits(wm8904->regmap,
2214 WM8904_MIC_BIAS_CONTROL_0 + i,
2215 0xffff,
2216 wm8904->pdata->mic_cfg[i]);
2217 }
2218
2219 /* Set Class W by default - this will be managed by the Class
2220 * G widget at runtime where bypass paths are available.
2221 */
2222 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2223 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2224
2225 /* Use normal bias source */
2226 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2227 WM8904_POBCTRL, 0);
2228
03862cf6
MB		 2229 /* Can leave the device powered off until we need it */
2230 regcache_cache_only(wm8904->regmap, true);
2231 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2232
f0fba2ad
LG		 2233 ret = snd_soc_register_codec(&i2c->dev,
2234 &soc_codec_dev_wm8904, &wm8904_dai, 1);
84d0d831 2235 if (ret != 0)
03862cf6 2236 return ret;
84d0d831
MB		 2237
2238 return 0;
93e26d4e 2239
03862cf6
MB		 2240err_enable:
2241 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
f0fba2ad 2242 return ret;
a91eb199
MB		 2243}
2244
7a79e94e 2245static int wm8904_i2c_remove(struct i2c_client *client)
a91eb199 2246{
f0fba2ad 2247 snd_soc_unregister_codec(&client->dev);
a91eb199
MB		 2248 return 0;
2249}
2250
2251static const struct i2c_device_id wm8904_i2c_id[] = {
8c126474
MB		 2252 { "wm8904", WM8904 },
2253 { "wm8912", WM8912 },
df1553c8 2254 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
a91eb199
MB		 2255 { }
2256};
2257MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2258
2259static struct i2c_driver wm8904_i2c_driver = {
2260 .driver = {
091edccf 2261 .name = "wm8904",
a91eb199
MB		 2262 .owner = THIS_MODULE,
2263 },
2264 .probe = wm8904_i2c_probe,
7a79e94e 2265 .remove = wm8904_i2c_remove,
a91eb199
MB		 2266 .id_table = wm8904_i2c_id,
2267};
a91eb199 2268
8cb28fd6 2269module_i2c_driver(wm8904_i2c_driver);
a91eb199
MB		 2270
2271MODULE_DESCRIPTION("ASoC WM8904 driver");
2272MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2273MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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