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Linux 3.15-rc1
[deliverable/linux.git] / sound / soc / codecs / wm8904.c
CommitLineData
a91eb199
MB		 1/*
2 * wm8904.c -- WM8904 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
a91eb199
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
84d0d831 20#include <linux/regmap.h>
a91eb199 21#include <linux/regulator/consumer.h>
5a0e3ad6 22#include <linux/slab.h>
a91eb199
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
a91eb199
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/wm8904.h>
30
31#include "wm8904.h"
32
8c126474
MB		 33enum wm8904_type {
34 WM8904,
35 WM8912,
36};
37
a91eb199
MB		 38#define WM8904_NUM_DCS_CHANNELS 4
39
40#define WM8904_NUM_SUPPLIES 5
41static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47};
48
49/* codec private data */
50struct wm8904_priv {
84d0d831 51 struct regmap *regmap;
f0fba2ad 52
8c126474
MB		 53 enum wm8904_type devtype;
54
a91eb199
MB		 55 struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES];
56
57 struct wm8904_pdata *pdata;
58
59 int deemph;
60
61 /* Platform provided DRC configuration */
62 const char **drc_texts;
63 int drc_cfg;
64 struct soc_enum drc_enum;
65
66 /* Platform provided ReTune mobile configuration */
67 int num_retune_mobile_texts;
68 const char **retune_mobile_texts;
69 int retune_mobile_cfg;
70 struct soc_enum retune_mobile_enum;
71
72 /* FLL setup */
73 int fll_src;
74 int fll_fref;
75 int fll_fout;
76
77 /* Clocking configuration */
78 unsigned int mclk_rate;
79 int sysclk_src;
80 unsigned int sysclk_rate;
81
82 int tdm_width;
83 int tdm_slots;
84 int bclk;
85 int fs;
86
87 /* DC servo configuration - cached offset values */
88 int dcs_state[WM8904_NUM_DCS_CHANNELS];
89};
90
84d0d831
MB		 91static const struct reg_default wm8904_reg_defaults[] = {
92 { 4, 0x0018 }, /* R4 - Bias Control 0 */
93 { 5, 0x0000 }, /* R5 - VMID Control 0 */
94 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
95 { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */
96 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
97 { 9, 0x9696 }, /* R9 - mic Filter Control */
98 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
99 { 12, 0x0000 }, /* R12 - Power Management 0 */
100 { 14, 0x0000 }, /* R14 - Power Management 2 */
101 { 15, 0x0000 }, /* R15 - Power Management 3 */
102 { 18, 0x0000 }, /* R18 - Power Management 6 */
985b11fa 103 { 20, 0x945E }, /* R20 - Clock Rates 0 */
84d0d831
MB		 104 { 21, 0x0C05 }, /* R21 - Clock Rates 1 */
105 { 22, 0x0006 }, /* R22 - Clock Rates 2 */
106 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
107 { 25, 0x000A }, /* R25 - Audio Interface 1 */
108 { 26, 0x00E4 }, /* R26 - Audio Interface 2 */
109 { 27, 0x0040 }, /* R27 - Audio Interface 3 */
110 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
111 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
112 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
113 { 33, 0x0008 }, /* R33 - DAC Digital 1 */
114 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
115 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
116 { 38, 0x0010 }, /* R38 - ADC Digital 0 */
117 { 39, 0x0000 }, /* R39 - Digital Microphone 0 */
118 { 40, 0x01AF }, /* R40 - DRC 0 */
119 { 41, 0x3248 }, /* R41 - DRC 1 */
120 { 42, 0x0000 }, /* R42 - DRC 2 */
121 { 43, 0x0000 }, /* R43 - DRC 3 */
122 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
123 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
124 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
125 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
126 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
127 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
128 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
129 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
130 { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */
131 { 67, 0x0000 }, /* R67 - DC Servo 0 */
132 { 69, 0xAAAA }, /* R69 - DC Servo 2 */
133 { 71, 0xAAAA }, /* R71 - DC Servo 4 */
134 { 72, 0xAAAA }, /* R72 - DC Servo 5 */
135 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
136 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
137 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
138 { 104, 0x0004 }, /* R104 - Class W 0 */
139 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
140 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
141 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
142 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
143 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
144 { 116, 0x0000 }, /* R116 - FLL Control 1 */
145 { 117, 0x0007 }, /* R117 - FLL Control 2 */
146 { 118, 0x0000 }, /* R118 - FLL Control 3 */
147 { 119, 0x2EE0 }, /* R119 - FLL Control 4 */
148 { 120, 0x0004 }, /* R120 - FLL Control 5 */
149 { 121, 0x0014 }, /* R121 - GPIO Control 1 */
150 { 122, 0x0010 }, /* R122 - GPIO Control 2 */
151 { 123, 0x0010 }, /* R123 - GPIO Control 3 */
152 { 124, 0x0000 }, /* R124 - GPIO Control 4 */
153 { 126, 0x0000 }, /* R126 - Digital Pulls */
154 { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */
155 { 129, 0x0000 }, /* R129 - Interrupt Polarity */
156 { 130, 0x0000 }, /* R130 - Interrupt Debounce */
157 { 134, 0x0000 }, /* R134 - EQ1 */
158 { 135, 0x000C }, /* R135 - EQ2 */
159 { 136, 0x000C }, /* R136 - EQ3 */
160 { 137, 0x000C }, /* R137 - EQ4 */
161 { 138, 0x000C }, /* R138 - EQ5 */
162 { 139, 0x000C }, /* R139 - EQ6 */
163 { 140, 0x0FCA }, /* R140 - EQ7 */
164 { 141, 0x0400 }, /* R141 - EQ8 */
165 { 142, 0x00D8 }, /* R142 - EQ9 */
166 { 143, 0x1EB5 }, /* R143 - EQ10 */
167 { 144, 0xF145 }, /* R144 - EQ11 */
168 { 145, 0x0B75 }, /* R145 - EQ12 */
169 { 146, 0x01C5 }, /* R146 - EQ13 */
170 { 147, 0x1C58 }, /* R147 - EQ14 */
171 { 148, 0xF373 }, /* R148 - EQ15 */
172 { 149, 0x0A54 }, /* R149 - EQ16 */
173 { 150, 0x0558 }, /* R150 - EQ17 */
174 { 151, 0x168E }, /* R151 - EQ18 */
175 { 152, 0xF829 }, /* R152 - EQ19 */
176 { 153, 0x07AD }, /* R153 - EQ20 */
177 { 154, 0x1103 }, /* R154 - EQ21 */
178 { 155, 0x0564 }, /* R155 - EQ22 */
179 { 156, 0x0559 }, /* R156 - EQ23 */
180 { 157, 0x4000 }, /* R157 - EQ24 */
181 { 161, 0x0000 }, /* R161 - Control Interface Test 1 */
182 { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */
183 { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */
184 { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */
a91eb199
MB		 185};
186
84d0d831
MB		 187static bool wm8904_volatile_register(struct device *dev, unsigned int reg)
188{
189 switch (reg) {
190 case WM8904_SW_RESET_AND_ID:
191 case WM8904_REVISION:
192 case WM8904_DC_SERVO_1:
193 case WM8904_DC_SERVO_6:
194 case WM8904_DC_SERVO_7:
195 case WM8904_DC_SERVO_8:
196 case WM8904_DC_SERVO_9:
197 case WM8904_DC_SERVO_READBACK_0:
198 case WM8904_INTERRUPT_STATUS:
199 return true;
200 default:
201 return false;
202 }
203}
a91eb199 204
84d0d831 205static bool wm8904_readable_register(struct device *dev, unsigned int reg)
a91eb199 206{
84d0d831
MB		 207 switch (reg) {
208 case WM8904_SW_RESET_AND_ID:
209 case WM8904_REVISION:
210 case WM8904_BIAS_CONTROL_0:
211 case WM8904_VMID_CONTROL_0:
212 case WM8904_MIC_BIAS_CONTROL_0:
213 case WM8904_MIC_BIAS_CONTROL_1:
214 case WM8904_ANALOGUE_DAC_0:
215 case WM8904_MIC_FILTER_CONTROL:
216 case WM8904_ANALOGUE_ADC_0:
217 case WM8904_POWER_MANAGEMENT_0:
218 case WM8904_POWER_MANAGEMENT_2:
219 case WM8904_POWER_MANAGEMENT_3:
220 case WM8904_POWER_MANAGEMENT_6:
221 case WM8904_CLOCK_RATES_0:
222 case WM8904_CLOCK_RATES_1:
223 case WM8904_CLOCK_RATES_2:
224 case WM8904_AUDIO_INTERFACE_0:
225 case WM8904_AUDIO_INTERFACE_1:
226 case WM8904_AUDIO_INTERFACE_2:
227 case WM8904_AUDIO_INTERFACE_3:
228 case WM8904_DAC_DIGITAL_VOLUME_LEFT:
229 case WM8904_DAC_DIGITAL_VOLUME_RIGHT:
230 case WM8904_DAC_DIGITAL_0:
231 case WM8904_DAC_DIGITAL_1:
232 case WM8904_ADC_DIGITAL_VOLUME_LEFT:
233 case WM8904_ADC_DIGITAL_VOLUME_RIGHT:
234 case WM8904_ADC_DIGITAL_0:
235 case WM8904_DIGITAL_MICROPHONE_0:
236 case WM8904_DRC_0:
237 case WM8904_DRC_1:
238 case WM8904_DRC_2:
239 case WM8904_DRC_3:
240 case WM8904_ANALOGUE_LEFT_INPUT_0:
241 case WM8904_ANALOGUE_RIGHT_INPUT_0:
242 case WM8904_ANALOGUE_LEFT_INPUT_1:
243 case WM8904_ANALOGUE_RIGHT_INPUT_1:
244 case WM8904_ANALOGUE_OUT1_LEFT:
245 case WM8904_ANALOGUE_OUT1_RIGHT:
246 case WM8904_ANALOGUE_OUT2_LEFT:
247 case WM8904_ANALOGUE_OUT2_RIGHT:
248 case WM8904_ANALOGUE_OUT12_ZC:
249 case WM8904_DC_SERVO_0:
250 case WM8904_DC_SERVO_1:
251 case WM8904_DC_SERVO_2:
252 case WM8904_DC_SERVO_4:
253 case WM8904_DC_SERVO_5:
254 case WM8904_DC_SERVO_6:
255 case WM8904_DC_SERVO_7:
256 case WM8904_DC_SERVO_8:
257 case WM8904_DC_SERVO_9:
258 case WM8904_DC_SERVO_READBACK_0:
259 case WM8904_ANALOGUE_HP_0:
260 case WM8904_ANALOGUE_LINEOUT_0:
261 case WM8904_CHARGE_PUMP_0:
262 case WM8904_CLASS_W_0:
263 case WM8904_WRITE_SEQUENCER_0:
264 case WM8904_WRITE_SEQUENCER_1:
265 case WM8904_WRITE_SEQUENCER_2:
266 case WM8904_WRITE_SEQUENCER_3:
267 case WM8904_WRITE_SEQUENCER_4:
268 case WM8904_FLL_CONTROL_1:
269 case WM8904_FLL_CONTROL_2:
270 case WM8904_FLL_CONTROL_3:
271 case WM8904_FLL_CONTROL_4:
272 case WM8904_FLL_CONTROL_5:
273 case WM8904_GPIO_CONTROL_1:
274 case WM8904_GPIO_CONTROL_2:
275 case WM8904_GPIO_CONTROL_3:
276 case WM8904_GPIO_CONTROL_4:
277 case WM8904_DIGITAL_PULLS:
278 case WM8904_INTERRUPT_STATUS:
279 case WM8904_INTERRUPT_STATUS_MASK:
280 case WM8904_INTERRUPT_POLARITY:
281 case WM8904_INTERRUPT_DEBOUNCE:
282 case WM8904_EQ1:
283 case WM8904_EQ2:
284 case WM8904_EQ3:
285 case WM8904_EQ4:
286 case WM8904_EQ5:
287 case WM8904_EQ6:
288 case WM8904_EQ7:
289 case WM8904_EQ8:
290 case WM8904_EQ9:
291 case WM8904_EQ10:
292 case WM8904_EQ11:
293 case WM8904_EQ12:
294 case WM8904_EQ13:
295 case WM8904_EQ14:
296 case WM8904_EQ15:
297 case WM8904_EQ16:
298 case WM8904_EQ17:
299 case WM8904_EQ18:
300 case WM8904_EQ19:
301 case WM8904_EQ20:
302 case WM8904_EQ21:
303 case WM8904_EQ22:
304 case WM8904_EQ23:
305 case WM8904_EQ24:
306 case WM8904_CONTROL_INTERFACE_TEST_1:
9b85fc90 307 case WM8904_ADC_TEST_0:
84d0d831
MB		 308 case WM8904_ANALOGUE_OUTPUT_BIAS_0:
309 case WM8904_FLL_NCO_TEST_0:
310 case WM8904_FLL_NCO_TEST_1:
311 return true;
312 default:
313 return true;
314 }
a91eb199
MB		 315}
316
a91eb199
MB		 317static int wm8904_configure_clocking(struct snd_soc_codec *codec)
318{
b2c812e2 319 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 320 unsigned int clock0, clock2, rate;
321
322 /* Gate the clock while we're updating to avoid misclocking */
323 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
324 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
325 WM8904_SYSCLK_SRC, 0);
326
327 /* This should be done on init() for bypass paths */
328 switch (wm8904->sysclk_src) {
329 case WM8904_CLK_MCLK:
330 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate);
331
332 clock2 &= ~WM8904_SYSCLK_SRC;
333 rate = wm8904->mclk_rate;
334
335 /* Ensure the FLL is stopped */
336 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
337 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
338 break;
339
340 case WM8904_CLK_FLL:
341 dev_dbg(codec->dev, "Using %dHz FLL clock\n",
342 wm8904->fll_fout);
343
344 clock2 |= WM8904_SYSCLK_SRC;
345 rate = wm8904->fll_fout;
346 break;
347
348 default:
349 dev_err(codec->dev, "System clock not configured\n");
350 return -EINVAL;
351 }
352
353 /* SYSCLK shouldn't be over 13.5MHz */
354 if (rate > 13500000) {
355 clock0 = WM8904_MCLK_DIV;
356 wm8904->sysclk_rate = rate / 2;
357 } else {
358 clock0 = 0;
359 wm8904->sysclk_rate = rate;
360 }
361
362 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV,
363 clock0);
364
365 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
366 WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2);
367
368 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate);
369
370 return 0;
371}
372
373static void wm8904_set_drc(struct snd_soc_codec *codec)
374{
b2c812e2 375 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 376 struct wm8904_pdata *pdata = wm8904->pdata;
377 int save, i;
378
379 /* Save any enables; the configuration should clear them. */
380 save = snd_soc_read(codec, WM8904_DRC_0);
381
382 for (i = 0; i < WM8904_DRC_REGS; i++)
383 snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff,
384 pdata->drc_cfgs[wm8904->drc_cfg].regs[i]);
385
386 /* Reenable the DRC */
387 snd_soc_update_bits(codec, WM8904_DRC_0,
388 WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save);
389}
390
391static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol,
392 struct snd_ctl_elem_value *ucontrol)
393{
394 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 395 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 396 struct wm8904_pdata *pdata = wm8904->pdata;
397 int value = ucontrol->value.integer.value[0];
398
399 if (value >= pdata->num_drc_cfgs)
400 return -EINVAL;
401
402 wm8904->drc_cfg = value;
403
404 wm8904_set_drc(codec);
405
406 return 0;
407}
408
409static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411{
412 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 413 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 414
415 ucontrol->value.enumerated.item[0] = wm8904->drc_cfg;
416
417 return 0;
418}
419
420static void wm8904_set_retune_mobile(struct snd_soc_codec *codec)
421{
b2c812e2 422 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 423 struct wm8904_pdata *pdata = wm8904->pdata;
424 int best, best_val, save, i, cfg;
425
426 if (!pdata || !wm8904->num_retune_mobile_texts)
427 return;
428
429 /* Find the version of the currently selected configuration
430 * with the nearest sample rate. */
431 cfg = wm8904->retune_mobile_cfg;
432 best = 0;
433 best_val = INT_MAX;
434 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
435 if (strcmp(pdata->retune_mobile_cfgs[i].name,
436 wm8904->retune_mobile_texts[cfg]) == 0 &&
437 abs(pdata->retune_mobile_cfgs[i].rate
438 - wm8904->fs) < best_val) {
439 best = i;
440 best_val = abs(pdata->retune_mobile_cfgs[i].rate
441 - wm8904->fs);
442 }
443 }
444
445 dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n",
446 pdata->retune_mobile_cfgs[best].name,
447 pdata->retune_mobile_cfgs[best].rate,
448 wm8904->fs);
449
450 /* The EQ will be disabled while reconfiguring it, remember the
451 * current configuration.
452 */
453 save = snd_soc_read(codec, WM8904_EQ1);
454
455 for (i = 0; i < WM8904_EQ_REGS; i++)
456 snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff,
457 pdata->retune_mobile_cfgs[best].regs[i]);
458
459 snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save);
460}
461
462static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 467 struct wm8904_pdata *pdata = wm8904->pdata;
468 int value = ucontrol->value.integer.value[0];
469
470 if (value >= pdata->num_retune_mobile_cfgs)
471 return -EINVAL;
472
473 wm8904->retune_mobile_cfg = value;
474
475 wm8904_set_retune_mobile(codec);
476
477 return 0;
478}
479
480static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
481 struct snd_ctl_elem_value *ucontrol)
482{
483 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 484 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 485
486 ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg;
487
488 return 0;
489}
490
491static int deemph_settings[] = { 0, 32000, 44100, 48000 };
492
493static int wm8904_set_deemph(struct snd_soc_codec *codec)
494{
b2c812e2 495 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 496 int val, i, best;
497
498 /* If we're using deemphasis select the nearest available sample
499 * rate.
500 */
501 if (wm8904->deemph) {
502 best = 1;
503 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
504 if (abs(deemph_settings[i] - wm8904->fs) <
505 abs(deemph_settings[best] - wm8904->fs))
506 best = i;
507 }
508
509 val = best << WM8904_DEEMPH_SHIFT;
510 } else {
511 val = 0;
512 }
513
514 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
515
516 return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
517 WM8904_DEEMPH_MASK, val);
518}
519
520static int wm8904_get_deemph(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 524 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199 525
3f343f85
DA		 526 ucontrol->value.enumerated.item[0] = wm8904->deemph;
527 return 0;
a91eb199
MB		 528}
529
530static int wm8904_put_deemph(struct snd_kcontrol *kcontrol,
531 struct snd_ctl_elem_value *ucontrol)
532{
533 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 534 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 535 int deemph = ucontrol->value.enumerated.item[0];
536
537 if (deemph > 1)
538 return -EINVAL;
539
540 wm8904->deemph = deemph;
541
542 return wm8904_set_deemph(codec);
543}
544
545static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
546static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
547static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
548static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
549static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
550
551static const char *input_mode_text[] = {
552 "Single-Ended", "Differential Line", "Differential Mic"
553};
554
d12bfd62
TI		 555static SOC_ENUM_SINGLE_DECL(lin_mode,
556 WM8904_ANALOGUE_LEFT_INPUT_1, 0,
557 input_mode_text);
a91eb199 558
d12bfd62
TI		 559static SOC_ENUM_SINGLE_DECL(rin_mode,
560 WM8904_ANALOGUE_RIGHT_INPUT_1, 0,
561 input_mode_text);
a91eb199
MB		 562
563static const char *hpf_mode_text[] = {
564 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
565};
566
d12bfd62
TI		 567static SOC_ENUM_SINGLE_DECL(hpf_mode, WM8904_ADC_DIGITAL_0, 5,
568 hpf_mode_text);
a91eb199 569
9b85fc90
MB		 570static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol,
571 struct snd_ctl_elem_value *ucontrol)
572{
573 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
574 unsigned int val;
575 int ret;
576
577 ret = snd_soc_put_volsw(kcontrol, ucontrol);
578 if (ret < 0)
579 return ret;
580
581 if (ucontrol->value.integer.value[0])
582 val = 0;
583 else
584 val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5;
585
586 snd_soc_update_bits(codec, WM8904_ADC_TEST_0,
587 WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5,
588 val);
589
590 return ret;
591}
592
a91eb199
MB		 593static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = {
594SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT,
595 WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv),
596
597SOC_ENUM("Left Caputure Mode", lin_mode),
598SOC_ENUM("Right Capture Mode", rin_mode),
599
600/* No TLV since it depends on mode */
601SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0,
602 WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0),
603SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0,
5a7c5f26 604 WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1),
a91eb199
MB		 605
606SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0),
607SOC_ENUM("High Pass Filter Mode", hpf_mode),
5a68bae2
LPC		 608SOC_SINGLE_EXT("ADC 128x OSR Switch", WM8904_ANALOGUE_ADC_0, 0, 1, 0,
609 snd_soc_get_volsw, wm8904_adc_osr_put),
a91eb199
MB		 610};
611
612static const char *drc_path_text[] = {
613 "ADC", "DAC"
614};
615
d12bfd62 616static SOC_ENUM_SINGLE_DECL(drc_path, WM8904_DRC_0, 14, drc_path_text);
a91eb199
MB		 617
618static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = {
619SOC_SINGLE_TLV("Digital Playback Boost Volume",
620 WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv),
621SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT,
622 WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
623
624SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT,
625 WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv),
626SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT,
627 WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1),
628SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT,
629 WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0),
630
631SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT,
632 WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv),
633SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT,
634 WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1),
635SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT,
636 WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0),
637
638SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0),
639SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0),
640SOC_ENUM("DRC Path", drc_path),
641SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0),
642SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
643 wm8904_get_deemph, wm8904_put_deemph),
644};
645
646static const struct snd_kcontrol_new wm8904_snd_controls[] = {
647SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0,
648 sidetone_tlv),
649};
650
651static const struct snd_kcontrol_new wm8904_eq_controls[] = {
652SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv),
653SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv),
654SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv),
656SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv),
657};
658
659static int cp_event(struct snd_soc_dapm_widget *w,
660 struct snd_kcontrol *kcontrol, int event)
661{
4c8d620a
TI		 662 if (WARN_ON(event != SND_SOC_DAPM_POST_PMU))
663 return -EINVAL;
a91eb199
MB		 664
665 /* Maximum startup time */
666 udelay(500);
667
668 return 0;
669}
670
671static int sysclk_event(struct snd_soc_dapm_widget *w,
672 struct snd_kcontrol *kcontrol, int event)
673{
674 struct snd_soc_codec *codec = w->codec;
b2c812e2 675 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 676
677 switch (event) {
678 case SND_SOC_DAPM_PRE_PMU:
679 /* If we're using the FLL then we only start it when
680 * required; we assume that the configuration has been
681 * done previously and all we need to do is kick it
682 * off.
683 */
684 switch (wm8904->sysclk_src) {
685 case WM8904_CLK_FLL:
686 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
687 WM8904_FLL_OSC_ENA,
688 WM8904_FLL_OSC_ENA);
689
690 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
691 WM8904_FLL_ENA,
692 WM8904_FLL_ENA);
693 break;
694
695 default:
696 break;
697 }
698 break;
699
700 case SND_SOC_DAPM_POST_PMD:
701 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
702 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
703 break;
704 }
705
706 return 0;
707}
708
709static int out_pga_event(struct snd_soc_dapm_widget *w,
710 struct snd_kcontrol *kcontrol, int event)
711{
712 struct snd_soc_codec *codec = w->codec;
b2c812e2 713 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 714 int reg, val;
715 int dcs_mask;
716 int dcs_l, dcs_r;
717 int dcs_l_reg, dcs_r_reg;
718 int timeout;
e4bc6696 719 int pwr_reg;
a91eb199
MB		 720
721 /* This code is shared between HP and LINEOUT; we do all our
722 * power management in stereo pairs to avoid latency issues so
723 * we reuse shift to identify which rather than strcmp() the
724 * name. */
725 reg = w->shift;
726
727 switch (reg) {
728 case WM8904_ANALOGUE_HP_0:
e4bc6696 729 pwr_reg = WM8904_POWER_MANAGEMENT_2;
a91eb199
MB		 730 dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1;
731 dcs_r_reg = WM8904_DC_SERVO_8;
732 dcs_l_reg = WM8904_DC_SERVO_9;
733 dcs_l = 0;
734 dcs_r = 1;
735 break;
736 case WM8904_ANALOGUE_LINEOUT_0:
e4bc6696 737 pwr_reg = WM8904_POWER_MANAGEMENT_3;
a91eb199
MB		 738 dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3;
739 dcs_r_reg = WM8904_DC_SERVO_6;
740 dcs_l_reg = WM8904_DC_SERVO_7;
741 dcs_l = 2;
742 dcs_r = 3;
743 break;
744 default:
8d8bb1ad 745 WARN(1, "Invalid reg %d\n", reg);
a91eb199
MB		 746 return -EINVAL;
747 }
748
749 switch (event) {
e4bc6696
MB		 750 case SND_SOC_DAPM_PRE_PMU:
751 /* Power on the PGAs */
752 snd_soc_update_bits(codec, pwr_reg,
753 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
754 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA);
755
a91eb199
MB		 756 /* Power on the amplifier */
757 snd_soc_update_bits(codec, reg,
758 WM8904_HPL_ENA | WM8904_HPR_ENA,
759 WM8904_HPL_ENA | WM8904_HPR_ENA);
760
e4bc6696 761
a91eb199
MB		 762 /* Enable the first stage */
763 snd_soc_update_bits(codec, reg,
764 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY,
765 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY);
766
767 /* Power up the DC servo */
768 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
769 dcs_mask, dcs_mask);
770
771 /* Either calibrate the DC servo or restore cached state
772 * if we have that.
773 */
774 if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) {
775 dev_dbg(codec->dev, "Restoring DC servo state\n");
776
777 snd_soc_write(codec, dcs_l_reg,
778 wm8904->dcs_state[dcs_l]);
779 snd_soc_write(codec, dcs_r_reg,
780 wm8904->dcs_state[dcs_r]);
781
782 snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask);
783
784 timeout = 20;
785 } else {
786 dev_dbg(codec->dev, "Calibrating DC servo\n");
787
788 snd_soc_write(codec, WM8904_DC_SERVO_1,
789 dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT);
790
791 timeout = 500;
792 }
793
794 /* Wait for DC servo to complete */
795 dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT;
796 do {
797 val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0);
798 if ((val & dcs_mask) == dcs_mask)
799 break;
800
801 msleep(1);
802 } while (--timeout);
803
804 if ((val & dcs_mask) != dcs_mask)
805 dev_warn(codec->dev, "DC servo timed out\n");
806 else
807 dev_dbg(codec->dev, "DC servo ready\n");
808
809 /* Enable the output stage */
810 snd_soc_update_bits(codec, reg,
811 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
812 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP);
e4bc6696 813 break;
a91eb199 814
e4bc6696 815 case SND_SOC_DAPM_POST_PMU:
a91eb199
MB		 816 /* Unshort the output itself */
817 snd_soc_update_bits(codec, reg,
818 WM8904_HPL_RMV_SHORT |
819 WM8904_HPR_RMV_SHORT,
820 WM8904_HPL_RMV_SHORT |
821 WM8904_HPR_RMV_SHORT);
822
823 break;
824
825 case SND_SOC_DAPM_PRE_PMD:
826 /* Short the output */
827 snd_soc_update_bits(codec, reg,
828 WM8904_HPL_RMV_SHORT |
829 WM8904_HPR_RMV_SHORT, 0);
e4bc6696 830 break;
a91eb199 831
e4bc6696 832 case SND_SOC_DAPM_POST_PMD:
a91eb199
MB		 833 /* Cache the DC servo configuration; this will be
834 * invalidated if we change the configuration. */
835 wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg);
836 wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg);
837
838 snd_soc_update_bits(codec, WM8904_DC_SERVO_0,
839 dcs_mask, 0);
840
841 /* Disable the amplifier input and output stages */
842 snd_soc_update_bits(codec, reg,
843 WM8904_HPL_ENA | WM8904_HPR_ENA |
844 WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY |
845 WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP,
846 0);
e4bc6696
MB		 847
848 /* PGAs too */
849 snd_soc_update_bits(codec, pwr_reg,
850 WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA,
851 0);
a91eb199
MB		 852 break;
853 }
854
855 return 0;
856}
857
858static const char *lin_text[] = {
859 "IN1L", "IN2L", "IN3L"
860};
861
d12bfd62
TI		 862static SOC_ENUM_SINGLE_DECL(lin_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 2,
863 lin_text);
a91eb199
MB		 864
865static const struct snd_kcontrol_new lin_mux =
866 SOC_DAPM_ENUM("Left Capture Mux", lin_enum);
867
d12bfd62
TI		 868static SOC_ENUM_SINGLE_DECL(lin_inv_enum, WM8904_ANALOGUE_LEFT_INPUT_1, 4,
869 lin_text);
a91eb199
MB		 870
871static const struct snd_kcontrol_new lin_inv_mux =
872 SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum);
873
874static const char *rin_text[] = {
875 "IN1R", "IN2R", "IN3R"
876};
877
d12bfd62
TI		 878static SOC_ENUM_SINGLE_DECL(rin_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 2,
879 rin_text);
a91eb199
MB		 880
881static const struct snd_kcontrol_new rin_mux =
882 SOC_DAPM_ENUM("Right Capture Mux", rin_enum);
883
d12bfd62
TI		 884static SOC_ENUM_SINGLE_DECL(rin_inv_enum, WM8904_ANALOGUE_RIGHT_INPUT_1, 4,
885 rin_text);
a91eb199
MB		 886
887static const struct snd_kcontrol_new rin_inv_mux =
888 SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum);
889
890static const char *aif_text[] = {
891 "Left", "Right"
892};
893
d12bfd62
TI		 894static SOC_ENUM_SINGLE_DECL(aifoutl_enum, WM8904_AUDIO_INTERFACE_0, 7,
895 aif_text);
a91eb199
MB		 896
897static const struct snd_kcontrol_new aifoutl_mux =
898 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
899
d12bfd62
TI		 900static SOC_ENUM_SINGLE_DECL(aifoutr_enum, WM8904_AUDIO_INTERFACE_0, 6,
901 aif_text);
a91eb199
MB		 902
903static const struct snd_kcontrol_new aifoutr_mux =
904 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
905
d12bfd62
TI		 906static SOC_ENUM_SINGLE_DECL(aifinl_enum, WM8904_AUDIO_INTERFACE_0, 5,
907 aif_text);
a91eb199
MB		 908
909static const struct snd_kcontrol_new aifinl_mux =
910 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
911
d12bfd62
TI		 912static SOC_ENUM_SINGLE_DECL(aifinr_enum, WM8904_AUDIO_INTERFACE_0, 4,
913 aif_text);
a91eb199
MB		 914
915static const struct snd_kcontrol_new aifinr_mux =
916 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
917
918static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = {
919SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event,
920 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
921SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0),
922SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0),
923};
924
925static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = {
926SND_SOC_DAPM_INPUT("IN1L"),
927SND_SOC_DAPM_INPUT("IN1R"),
928SND_SOC_DAPM_INPUT("IN2L"),
929SND_SOC_DAPM_INPUT("IN2R"),
930SND_SOC_DAPM_INPUT("IN3L"),
931SND_SOC_DAPM_INPUT("IN3R"),
932
dcd658c5 933SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
a91eb199
MB		 934
935SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux),
936SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
937 &lin_inv_mux),
938SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux),
939SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0,
940 &rin_inv_mux),
941
942SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0,
943 NULL, 0),
944SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0,
945 NULL, 0),
946
947SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0),
948SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
949
950SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
951SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
952
953SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
954SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
955};
956
957static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = {
958SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
959SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
960
961SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
962SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
963
964SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0),
965SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0),
966
967SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event,
968 SND_SOC_DAPM_POST_PMU),
969
e4bc6696
MB		 970SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
971SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
a91eb199 972
e4bc6696
MB		 973SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0),
974SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
a91eb199
MB		 975
976SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0,
977 0, NULL, 0, out_pga_event,
e4bc6696
MB		 978 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
979 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
a91eb199
MB		 980SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0,
981 0, NULL, 0, out_pga_event,
e4bc6696
MB		 982 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
983 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
a91eb199
MB		 984
985SND_SOC_DAPM_OUTPUT("HPOUTL"),
986SND_SOC_DAPM_OUTPUT("HPOUTR"),
987SND_SOC_DAPM_OUTPUT("LINEOUTL"),
988SND_SOC_DAPM_OUTPUT("LINEOUTR"),
989};
990
991static const char *out_mux_text[] = {
992 "DAC", "Bypass"
993};
994
d12bfd62
TI		 995static SOC_ENUM_SINGLE_DECL(hpl_enum, WM8904_ANALOGUE_OUT12_ZC, 3,
996 out_mux_text);
a91eb199
MB		 997
998static const struct snd_kcontrol_new hpl_mux =
999 SOC_DAPM_ENUM("HPL Mux", hpl_enum);
1000
d12bfd62
TI		 1001static SOC_ENUM_SINGLE_DECL(hpr_enum, WM8904_ANALOGUE_OUT12_ZC, 2,
1002 out_mux_text);
a91eb199
MB		 1003
1004static const struct snd_kcontrol_new hpr_mux =
1005 SOC_DAPM_ENUM("HPR Mux", hpr_enum);
1006
d12bfd62
TI		 1007static SOC_ENUM_SINGLE_DECL(linel_enum, WM8904_ANALOGUE_OUT12_ZC, 1,
1008 out_mux_text);
a91eb199
MB		 1009
1010static const struct snd_kcontrol_new linel_mux =
1011 SOC_DAPM_ENUM("LINEL Mux", linel_enum);
1012
d12bfd62
TI		 1013static SOC_ENUM_SINGLE_DECL(liner_enum, WM8904_ANALOGUE_OUT12_ZC, 0,
1014 out_mux_text);
a91eb199
MB		 1015
1016static const struct snd_kcontrol_new liner_mux =
e94a093c 1017 SOC_DAPM_ENUM("LINER Mux", liner_enum);
a91eb199
MB		 1018
1019static const char *sidetone_text[] = {
1020 "None", "Left", "Right"
1021};
1022
d12bfd62
TI		 1023static SOC_ENUM_SINGLE_DECL(dacl_sidetone_enum, WM8904_DAC_DIGITAL_0, 2,
1024 sidetone_text);
a91eb199
MB		 1025
1026static const struct snd_kcontrol_new dacl_sidetone_mux =
1027 SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum);
1028
d12bfd62
TI		 1029static SOC_ENUM_SINGLE_DECL(dacr_sidetone_enum, WM8904_DAC_DIGITAL_0, 0,
1030 sidetone_text);
a91eb199
MB		 1031
1032static const struct snd_kcontrol_new dacr_sidetone_mux =
1033 SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum);
1034
1035static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = {
1036SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0),
1037SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1038SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
1039
1040SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux),
1041SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux),
1042
1043SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1044SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1045SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux),
1046SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux),
1047};
1048
1049static const struct snd_soc_dapm_route core_intercon[] = {
1050 { "CLK_DSP", NULL, "SYSCLK" },
1051 { "TOCLK", NULL, "SYSCLK" },
1052};
1053
1054static const struct snd_soc_dapm_route adc_intercon[] = {
1055 { "Left Capture Mux", "IN1L", "IN1L" },
1056 { "Left Capture Mux", "IN2L", "IN2L" },
1057 { "Left Capture Mux", "IN3L", "IN3L" },
1058
1059 { "Left Capture Inverting Mux", "IN1L", "IN1L" },
1060 { "Left Capture Inverting Mux", "IN2L", "IN2L" },
1061 { "Left Capture Inverting Mux", "IN3L", "IN3L" },
1062
1063 { "Right Capture Mux", "IN1R", "IN1R" },
1064 { "Right Capture Mux", "IN2R", "IN2R" },
1065 { "Right Capture Mux", "IN3R", "IN3R" },
1066
1067 { "Right Capture Inverting Mux", "IN1R", "IN1R" },
1068 { "Right Capture Inverting Mux", "IN2R", "IN2R" },
1069 { "Right Capture Inverting Mux", "IN3R", "IN3R" },
1070
1071 { "Left Capture PGA", NULL, "Left Capture Mux" },
1072 { "Left Capture PGA", NULL, "Left Capture Inverting Mux" },
1073
1074 { "Right Capture PGA", NULL, "Right Capture Mux" },
1075 { "Right Capture PGA", NULL, "Right Capture Inverting Mux" },
1076
1077 { "AIFOUTL", "Left", "ADCL" },
1078 { "AIFOUTL", "Right", "ADCR" },
1079 { "AIFOUTR", "Left", "ADCL" },
1080 { "AIFOUTR", "Right", "ADCR" },
1081
1082 { "ADCL", NULL, "CLK_DSP" },
1083 { "ADCL", NULL, "Left Capture PGA" },
1084
1085 { "ADCR", NULL, "CLK_DSP" },
1086 { "ADCR", NULL, "Right Capture PGA" },
1087};
1088
1089static const struct snd_soc_dapm_route dac_intercon[] = {
1090 { "DACL", "Right", "AIFINR" },
1091 { "DACL", "Left", "AIFINL" },
1092 { "DACL", NULL, "CLK_DSP" },
1093
1094 { "DACR", "Right", "AIFINR" },
1095 { "DACR", "Left", "AIFINL" },
1096 { "DACR", NULL, "CLK_DSP" },
1097
1098 { "Charge pump", NULL, "SYSCLK" },
1099
1100 { "Headphone Output", NULL, "HPL PGA" },
1101 { "Headphone Output", NULL, "HPR PGA" },
1102 { "Headphone Output", NULL, "Charge pump" },
1103 { "Headphone Output", NULL, "TOCLK" },
1104
1105 { "Line Output", NULL, "LINEL PGA" },
1106 { "Line Output", NULL, "LINER PGA" },
1107 { "Line Output", NULL, "Charge pump" },
1108 { "Line Output", NULL, "TOCLK" },
1109
1110 { "HPOUTL", NULL, "Headphone Output" },
1111 { "HPOUTR", NULL, "Headphone Output" },
1112
1113 { "LINEOUTL", NULL, "Line Output" },
1114 { "LINEOUTR", NULL, "Line Output" },
1115};
1116
1117static const struct snd_soc_dapm_route wm8904_intercon[] = {
1118 { "Left Sidetone", "Left", "ADCL" },
1119 { "Left Sidetone", "Right", "ADCR" },
1120 { "DACL", NULL, "Left Sidetone" },
1121
1122 { "Right Sidetone", "Left", "ADCL" },
1123 { "Right Sidetone", "Right", "ADCR" },
1124 { "DACR", NULL, "Right Sidetone" },
1125
1126 { "Left Bypass", NULL, "Class G" },
1127 { "Left Bypass", NULL, "Left Capture PGA" },
1128
1129 { "Right Bypass", NULL, "Class G" },
1130 { "Right Bypass", NULL, "Right Capture PGA" },
1131
1132 { "HPL Mux", "DAC", "DACL" },
1133 { "HPL Mux", "Bypass", "Left Bypass" },
1134
1135 { "HPR Mux", "DAC", "DACR" },
1136 { "HPR Mux", "Bypass", "Right Bypass" },
1137
1138 { "LINEL Mux", "DAC", "DACL" },
1139 { "LINEL Mux", "Bypass", "Left Bypass" },
1140
1141 { "LINER Mux", "DAC", "DACR" },
1142 { "LINER Mux", "Bypass", "Right Bypass" },
1143
1144 { "HPL PGA", NULL, "HPL Mux" },
1145 { "HPR PGA", NULL, "HPR Mux" },
1146
1147 { "LINEL PGA", NULL, "LINEL Mux" },
1148 { "LINER PGA", NULL, "LINER Mux" },
1149};
1150
8c126474
MB		 1151static const struct snd_soc_dapm_route wm8912_intercon[] = {
1152 { "HPL PGA", NULL, "DACL" },
1153 { "HPR PGA", NULL, "DACR" },
1154
1155 { "LINEL PGA", NULL, "DACL" },
1156 { "LINER PGA", NULL, "DACR" },
1157};
1158
a91eb199
MB		 1159static int wm8904_add_widgets(struct snd_soc_codec *codec)
1160{
b2c812e2 1161 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
ce6120cc 1162 struct snd_soc_dapm_context *dapm = &codec->dapm;
a91eb199 1163
ce6120cc 1164 snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets,
a91eb199 1165 ARRAY_SIZE(wm8904_core_dapm_widgets));
ce6120cc 1166 snd_soc_dapm_add_routes(dapm, core_intercon,
a91eb199 1167 ARRAY_SIZE(core_intercon));
8c126474
MB		 1168
1169 switch (wm8904->devtype) {
1170 case WM8904:
022658be 1171 snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls,
8c126474 1172 ARRAY_SIZE(wm8904_adc_snd_controls));
022658be 1173 snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
8c126474 1174 ARRAY_SIZE(wm8904_dac_snd_controls));
022658be 1175 snd_soc_add_codec_controls(codec, wm8904_snd_controls,
8c126474
MB		 1176 ARRAY_SIZE(wm8904_snd_controls));
1177
ce6120cc 1178 snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets,
8c126474 1179 ARRAY_SIZE(wm8904_adc_dapm_widgets));
ce6120cc 1180 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
8c126474 1181 ARRAY_SIZE(wm8904_dac_dapm_widgets));
ce6120cc 1182 snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets,
8c126474
MB		 1183 ARRAY_SIZE(wm8904_dapm_widgets));
1184
ce6120cc 1185 snd_soc_dapm_add_routes(dapm, adc_intercon,
8c126474 1186 ARRAY_SIZE(adc_intercon));
ce6120cc 1187 snd_soc_dapm_add_routes(dapm, dac_intercon,
8c126474 1188 ARRAY_SIZE(dac_intercon));
ce6120cc 1189 snd_soc_dapm_add_routes(dapm, wm8904_intercon,
8c126474
MB		 1190 ARRAY_SIZE(wm8904_intercon));
1191 break;
1192
1193 case WM8912:
022658be 1194 snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls,
8c126474
MB		 1195 ARRAY_SIZE(wm8904_dac_snd_controls));
1196
ce6120cc 1197 snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets,
8c126474
MB		 1198 ARRAY_SIZE(wm8904_dac_dapm_widgets));
1199
ce6120cc 1200 snd_soc_dapm_add_routes(dapm, dac_intercon,
8c126474 1201 ARRAY_SIZE(dac_intercon));
ce6120cc 1202 snd_soc_dapm_add_routes(dapm, wm8912_intercon,
8c126474
MB		 1203 ARRAY_SIZE(wm8912_intercon));
1204 break;
1205 }
a91eb199 1206
a91eb199
MB		 1207 return 0;
1208}
1209
1210static struct {
1211 int ratio;
1212 unsigned int clk_sys_rate;
1213} clk_sys_rates[] = {
1214 { 64, 0 },
1215 { 128, 1 },
1216 { 192, 2 },
1217 { 256, 3 },
1218 { 384, 4 },
1219 { 512, 5 },
1220 { 786, 6 },
1221 { 1024, 7 },
1222 { 1408, 8 },
1223 { 1536, 9 },
1224};
1225
1226static struct {
1227 int rate;
1228 int sample_rate;
1229} sample_rates[] = {
1230 { 8000, 0 },
1231 { 11025, 1 },
1232 { 12000, 1 },
1233 { 16000, 2 },
1234 { 22050, 3 },
1235 { 24000, 3 },
1236 { 32000, 4 },
1237 { 44100, 5 },
1238 { 48000, 5 },
1239};
1240
1241static struct {
1242 int div; /* *10 due to .5s */
1243 int bclk_div;
1244} bclk_divs[] = {
1245 { 10, 0 },
1246 { 15, 1 },
1247 { 20, 2 },
1248 { 30, 3 },
1249 { 40, 4 },
1250 { 50, 5 },
1251 { 55, 6 },
1252 { 60, 7 },
1253 { 80, 8 },
1254 { 100, 9 },
1255 { 110, 10 },
1256 { 120, 11 },
1257 { 160, 12 },
1258 { 200, 13 },
1259 { 220, 14 },
1260 { 240, 16 },
1261 { 200, 17 },
1262 { 320, 18 },
1263 { 440, 19 },
1264 { 480, 20 },
1265};
1266
1267
1268static int wm8904_hw_params(struct snd_pcm_substream *substream,
1269 struct snd_pcm_hw_params *params,
1270 struct snd_soc_dai *dai)
1271{
1272 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1273 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1274 int ret, i, best, best_val, cur_val;
1275 unsigned int aif1 = 0;
1276 unsigned int aif2 = 0;
1277 unsigned int aif3 = 0;
1278 unsigned int clock1 = 0;
1279 unsigned int dac_digital1 = 0;
1280
1281 /* What BCLK do we need? */
1282 wm8904->fs = params_rate(params);
1283 if (wm8904->tdm_slots) {
1284 dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n",
1285 wm8904->tdm_slots, wm8904->tdm_width);
1286 wm8904->bclk = snd_soc_calc_bclk(wm8904->fs,
1287 wm8904->tdm_width, 2,
1288 wm8904->tdm_slots);
1289 } else {
1290 wm8904->bclk = snd_soc_params_to_bclk(params);
1291 }
1292
56927eb0
MB		 1293 switch (params_format(params)) {
1294 case SNDRV_PCM_FORMAT_S16_LE:
1295 break;
1296 case SNDRV_PCM_FORMAT_S20_3LE:
1297 aif1 |= 0x40;
1298 break;
1299 case SNDRV_PCM_FORMAT_S24_LE:
1300 aif1 |= 0x80;
1301 break;
1302 case SNDRV_PCM_FORMAT_S32_LE:
1303 aif1 |= 0xc0;
1304 break;
1305 default:
1306 return -EINVAL;
1307 }
1308
1309
a91eb199
MB		 1310 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk);
1311
1312 ret = wm8904_configure_clocking(codec);
1313 if (ret != 0)
1314 return ret;
1315
1316 /* Select nearest CLK_SYS_RATE */
1317 best = 0;
1318 best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio)
1319 - wm8904->fs);
1320 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1321 cur_val = abs((wm8904->sysclk_rate /
ef995e3a 1322 clk_sys_rates[i].ratio) - wm8904->fs);
a91eb199
MB		 1323 if (cur_val < best_val) {
1324 best = i;
1325 best_val = cur_val;
1326 }
1327 }
1328 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1329 clk_sys_rates[best].ratio);
1330 clock1 |= (clk_sys_rates[best].clk_sys_rate
1331 << WM8904_CLK_SYS_RATE_SHIFT);
1332
1333 /* SAMPLE_RATE */
1334 best = 0;
1335 best_val = abs(wm8904->fs - sample_rates[0].rate);
1336 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1337 /* Closest match */
1338 cur_val = abs(wm8904->fs - sample_rates[i].rate);
1339 if (cur_val < best_val) {
1340 best = i;
1341 best_val = cur_val;
1342 }
1343 }
1344 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1345 sample_rates[best].rate);
1346 clock1 |= (sample_rates[best].sample_rate
1347 << WM8904_SAMPLE_RATE_SHIFT);
1348
1349 /* Enable sloping stopband filter for low sample rates */
1350 if (wm8904->fs <= 24000)
1351 dac_digital1 |= WM8904_DAC_SB_FILT;
1352
1353 /* BCLK_DIV */
1354 best = 0;
1355 best_val = INT_MAX;
1356 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1357 cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div)
1358 - wm8904->bclk;
1359 if (cur_val < 0) /* Table is sorted */
1360 break;
1361 if (cur_val < best_val) {
1362 best = i;
1363 best_val = cur_val;
1364 }
1365 }
1366 wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div;
1367 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1368 bclk_divs[best].div, wm8904->bclk);
1369 aif2 |= bclk_divs[best].bclk_div;
1370
1371 /* LRCLK is a simple fraction of BCLK */
1372 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs);
1373 aif3 |= wm8904->bclk / wm8904->fs;
1374
1375 /* Apply the settings */
1376 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1,
1377 WM8904_DAC_SB_FILT, dac_digital1);
1378 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1379 WM8904_AIF_WL_MASK, aif1);
1380 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2,
1381 WM8904_BCLK_DIV_MASK, aif2);
1382 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1383 WM8904_LRCLK_RATE_MASK, aif3);
1384 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1,
1385 WM8904_SAMPLE_RATE_MASK |
1386 WM8904_CLK_SYS_RATE_MASK, clock1);
1387
1388 /* Update filters for the new settings */
1389 wm8904_set_retune_mobile(codec);
1390 wm8904_set_deemph(codec);
1391
1392 return 0;
1393}
1394
1395
1396static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id,
1397 unsigned int freq, int dir)
1398{
1399 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1400 struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1401
1402 switch (clk_id) {
1403 case WM8904_CLK_MCLK:
1404 priv->sysclk_src = clk_id;
1405 priv->mclk_rate = freq;
1406 break;
1407
1408 case WM8904_CLK_FLL:
1409 priv->sysclk_src = clk_id;
1410 break;
1411
1412 default:
1413 return -EINVAL;
1414 }
1415
1416 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1417
1418 wm8904_configure_clocking(codec);
1419
1420 return 0;
1421}
1422
1423static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1424{
1425 struct snd_soc_codec *codec = dai->codec;
1426 unsigned int aif1 = 0;
1427 unsigned int aif3 = 0;
1428
1429 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1430 case SND_SOC_DAIFMT_CBS_CFS:
1431 break;
1432 case SND_SOC_DAIFMT_CBS_CFM:
1433 aif3 |= WM8904_LRCLK_DIR;
1434 break;
1435 case SND_SOC_DAIFMT_CBM_CFS:
1436 aif1 |= WM8904_BCLK_DIR;
1437 break;
1438 case SND_SOC_DAIFMT_CBM_CFM:
1439 aif1 |= WM8904_BCLK_DIR;
1440 aif3 |= WM8904_LRCLK_DIR;
1441 break;
1442 default:
1443 return -EINVAL;
1444 }
1445
1446 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1447 case SND_SOC_DAIFMT_DSP_B:
f0199bc5 1448 aif1 |= 0x3 | WM8904_AIF_LRCLK_INV;
a91eb199
MB		 1449 case SND_SOC_DAIFMT_DSP_A:
1450 aif1 |= 0x3;
1451 break;
1452 case SND_SOC_DAIFMT_I2S:
1453 aif1 |= 0x2;
1454 break;
1455 case SND_SOC_DAIFMT_RIGHT_J:
1456 break;
1457 case SND_SOC_DAIFMT_LEFT_J:
1458 aif1 |= 0x1;
1459 break;
1460 default:
1461 return -EINVAL;
1462 }
1463
1464 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1465 case SND_SOC_DAIFMT_DSP_A:
1466 case SND_SOC_DAIFMT_DSP_B:
1467 /* frame inversion not valid for DSP modes */
1468 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1469 case SND_SOC_DAIFMT_NB_NF:
1470 break;
1471 case SND_SOC_DAIFMT_IB_NF:
1472 aif1 |= WM8904_AIF_BCLK_INV;
1473 break;
1474 default:
1475 return -EINVAL;
1476 }
1477 break;
1478
1479 case SND_SOC_DAIFMT_I2S:
1480 case SND_SOC_DAIFMT_RIGHT_J:
1481 case SND_SOC_DAIFMT_LEFT_J:
1482 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1483 case SND_SOC_DAIFMT_NB_NF:
1484 break;
1485 case SND_SOC_DAIFMT_IB_IF:
1486 aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV;
1487 break;
1488 case SND_SOC_DAIFMT_IB_NF:
1489 aif1 |= WM8904_AIF_BCLK_INV;
1490 break;
1491 case SND_SOC_DAIFMT_NB_IF:
1492 aif1 |= WM8904_AIF_LRCLK_INV;
1493 break;
1494 default:
1495 return -EINVAL;
1496 }
1497 break;
1498 default:
1499 return -EINVAL;
1500 }
1501
1502 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1503 WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV |
1504 WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1);
1505 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3,
1506 WM8904_LRCLK_DIR, aif3);
1507
1508 return 0;
1509}
1510
1511
1512static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1513 unsigned int rx_mask, int slots, int slot_width)
1514{
1515 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1516 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1517 int aif1 = 0;
1518
1519 /* Don't need to validate anything if we're turning off TDM */
1520 if (slots == 0)
1521 goto out;
1522
1523 /* Note that we allow configurations we can't handle ourselves -
1524 * for example, we can generate clocks for slots 2 and up even if
1525 * we can't use those slots ourselves.
1526 */
1527 aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM;
1528
1529 switch (rx_mask) {
1530 case 3:
1531 break;
1532 case 0xc:
1533 aif1 |= WM8904_AIFADC_TDM_CHAN;
1534 break;
1535 default:
1536 return -EINVAL;
1537 }
1538
1539
1540 switch (tx_mask) {
1541 case 3:
1542 break;
1543 case 0xc:
1544 aif1 |= WM8904_AIFDAC_TDM_CHAN;
1545 break;
1546 default:
1547 return -EINVAL;
1548 }
1549
1550out:
1551 wm8904->tdm_width = slot_width;
1552 wm8904->tdm_slots = slots / 2;
1553
1554 snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1,
1555 WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN |
1556 WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1);
1557
1558 return 0;
1559}
1560
1561struct _fll_div {
1562 u16 fll_fratio;
1563 u16 fll_outdiv;
1564 u16 fll_clk_ref_div;
1565 u16 n;
1566 u16 k;
1567};
1568
1569/* The size in bits of the FLL divide multiplied by 10
1570 * to allow rounding later */
1571#define FIXED_FLL_SIZE ((1 << 16) * 10)
1572
1573static struct {
1574 unsigned int min;
1575 unsigned int max;
1576 u16 fll_fratio;
1577 int ratio;
1578} fll_fratios[] = {
1579 { 0, 64000, 4, 16 },
1580 { 64000, 128000, 3, 8 },
1581 { 128000, 256000, 2, 4 },
1582 { 256000, 1000000, 1, 2 },
1583 { 1000000, 13500000, 0, 1 },
1584};
1585
1586static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1587 unsigned int Fout)
1588{
1589 u64 Kpart;
1590 unsigned int K, Ndiv, Nmod, target;
1591 unsigned int div;
1592 int i;
1593
1594 /* Fref must be <=13.5MHz */
1595 div = 1;
1596 fll_div->fll_clk_ref_div = 0;
1597 while ((Fref / div) > 13500000) {
1598 div *= 2;
1599 fll_div->fll_clk_ref_div++;
1600
1601 if (div > 8) {
1602 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1603 Fref);
1604 return -EINVAL;
1605 }
1606 }
1607
1608 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
1609
1610 /* Apply the division for our remaining calculations */
1611 Fref /= div;
1612
1613 /* Fvco should be 90-100MHz; don't check the upper bound */
1614 div = 4;
1615 while (Fout * div < 90000000) {
1616 div++;
1617 if (div > 64) {
1618 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1619 Fout);
1620 return -EINVAL;
1621 }
1622 }
1623 target = Fout * div;
1624 fll_div->fll_outdiv = div - 1;
1625
1626 pr_debug("Fvco=%dHz\n", target);
1627
25985edc 1628 /* Find an appropriate FLL_FRATIO and factor it out of the target */
a91eb199
MB		 1629 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1630 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1631 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1632 target /= fll_fratios[i].ratio;
1633 break;
1634 }
1635 }
1636 if (i == ARRAY_SIZE(fll_fratios)) {
1637 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1638 return -EINVAL;
1639 }
1640
1641 /* Now, calculate N.K */
1642 Ndiv = target / Fref;
1643
1644 fll_div->n = Ndiv;
1645 Nmod = target % Fref;
1646 pr_debug("Nmod=%d\n", Nmod);
1647
1648 /* Calculate fractional part - scale up so we can round. */
1649 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1650
1651 do_div(Kpart, Fref);
1652
1653 K = Kpart & 0xFFFFFFFF;
1654
1655 if ((K % 10) >= 5)
1656 K += 5;
1657
1658 /* Move down to proper range now rounding is done */
1659 fll_div->k = K / 10;
1660
1661 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
1662 fll_div->n, fll_div->k,
1663 fll_div->fll_fratio, fll_div->fll_outdiv,
1664 fll_div->fll_clk_ref_div);
1665
1666 return 0;
1667}
1668
1669static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1670 unsigned int Fref, unsigned int Fout)
1671{
1672 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1673 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1674 struct _fll_div fll_div;
1675 int ret, val;
1676 int clock2, fll1;
1677
1678 /* Any change? */
1679 if (source == wm8904->fll_src && Fref == wm8904->fll_fref &&
1680 Fout == wm8904->fll_fout)
1681 return 0;
1682
18240b67
MB		 1683 clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2);
1684
a91eb199
MB		 1685 if (Fout == 0) {
1686 dev_dbg(codec->dev, "FLL disabled\n");
1687
1688 wm8904->fll_fref = 0;
1689 wm8904->fll_fout = 0;
1690
1691 /* Gate SYSCLK to avoid glitches */
1692 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1693 WM8904_CLK_SYS_ENA, 0);
1694
1695 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1696 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1697
1698 goto out;
1699 }
1700
1701 /* Validate the FLL ID */
1702 switch (source) {
1703 case WM8904_FLL_MCLK:
1704 case WM8904_FLL_LRCLK:
1705 case WM8904_FLL_BCLK:
1706 ret = fll_factors(&fll_div, Fref, Fout);
1707 if (ret != 0)
1708 return ret;
1709 break;
1710
1711 case WM8904_FLL_FREE_RUNNING:
1712 dev_dbg(codec->dev, "Using free running FLL\n");
1713 /* Force 12MHz and output/4 for now */
1714 Fout = 12000000;
1715 Fref = 12000000;
1716
1717 memset(&fll_div, 0, sizeof(fll_div));
1718 fll_div.fll_outdiv = 3;
1719 break;
1720
1721 default:
1722 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
1723 return -EINVAL;
1724 }
1725
1726 /* Save current state then disable the FLL and SYSCLK to avoid
1727 * misclocking */
a91eb199
MB		 1728 fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1);
1729 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1730 WM8904_CLK_SYS_ENA, 0);
1731 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1732 WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0);
1733
1734 /* Unlock forced oscilator control to switch it on/off */
1735 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1736 WM8904_USER_KEY, WM8904_USER_KEY);
1737
1738 if (fll_id == WM8904_FLL_FREE_RUNNING) {
1739 val = WM8904_FLL_FRC_NCO;
1740 } else {
1741 val = 0;
1742 }
1743
1744 snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO,
1745 val);
1746 snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1,
1747 WM8904_USER_KEY, 0);
1748
1749 switch (fll_id) {
1750 case WM8904_FLL_MCLK:
1751 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1752 WM8904_FLL_CLK_REF_SRC_MASK, 0);
1753 break;
1754
1755 case WM8904_FLL_LRCLK:
1756 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1757 WM8904_FLL_CLK_REF_SRC_MASK, 1);
1758 break;
1759
1760 case WM8904_FLL_BCLK:
1761 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1762 WM8904_FLL_CLK_REF_SRC_MASK, 2);
1763 break;
1764 }
1765
1766 if (fll_div.k)
1767 val = WM8904_FLL_FRACN_ENA;
1768 else
1769 val = 0;
1770 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1771 WM8904_FLL_FRACN_ENA, val);
1772
1773 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2,
1774 WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK,
1775 (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) |
1776 (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT));
1777
1778 snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k);
1779
1780 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK,
1781 fll_div.n << WM8904_FLL_N_SHIFT);
1782
1783 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5,
1784 WM8904_FLL_CLK_REF_DIV_MASK,
1785 fll_div.fll_clk_ref_div
1786 << WM8904_FLL_CLK_REF_DIV_SHIFT);
1787
1788 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1789
1790 wm8904->fll_fref = Fref;
1791 wm8904->fll_fout = Fout;
1792 wm8904->fll_src = source;
1793
1794 /* Enable the FLL if it was previously active */
1795 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1796 WM8904_FLL_OSC_ENA, fll1);
1797 snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1,
1798 WM8904_FLL_ENA, fll1);
1799
1800out:
1801 /* Reenable SYSCLK if it was previously active */
1802 snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2,
1803 WM8904_CLK_SYS_ENA, clock2);
1804
1805 return 0;
1806}
1807
1808static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1809{
1810 struct snd_soc_codec *codec = codec_dai->codec;
1811 int val;
1812
1813 if (mute)
1814 val = WM8904_DAC_MUTE;
1815 else
1816 val = 0;
1817
1818 snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val);
1819
1820 return 0;
1821}
1822
1823static int wm8904_set_bias_level(struct snd_soc_codec *codec,
1824 enum snd_soc_bias_level level)
1825{
b2c812e2 1826 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
c1334218 1827 int ret;
a91eb199
MB		 1828
1829 switch (level) {
1830 case SND_SOC_BIAS_ON:
1831 break;
1832
1833 case SND_SOC_BIAS_PREPARE:
1834 /* VMID resistance 2*50k */
1835 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1836 WM8904_VMID_RES_MASK,
1837 0x1 << WM8904_VMID_RES_SHIFT);
1838
1839 /* Normal bias current */
1840 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1841 WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT);
1842 break;
1843
1844 case SND_SOC_BIAS_STANDBY:
ce6120cc 1845 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
a91eb199
MB		 1846 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
1847 wm8904->supplies);
1848 if (ret != 0) {
1849 dev_err(codec->dev,
1850 "Failed to enable supplies: %d\n",
1851 ret);
1852 return ret;
1853 }
1854
c1b88ee2 1855 regcache_cache_only(wm8904->regmap, false);
84d0d831 1856 regcache_sync(wm8904->regmap);
a91eb199
MB		 1857
1858 /* Enable bias */
1859 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1860 WM8904_BIAS_ENA, WM8904_BIAS_ENA);
1861
1862 /* Enable VMID, VMID buffering, 2*5k resistance */
1863 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1864 WM8904_VMID_ENA |
1865 WM8904_VMID_RES_MASK,
1866 WM8904_VMID_ENA |
1867 0x3 << WM8904_VMID_RES_SHIFT);
1868
1869 /* Let VMID ramp */
1870 msleep(1);
1871 }
1872
1873 /* Maintain VMID with 2*250k */
1874 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1875 WM8904_VMID_RES_MASK,
1876 0x2 << WM8904_VMID_RES_SHIFT);
1877
1878 /* Bias current *0.5 */
1879 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1880 WM8904_ISEL_MASK, 0);
1881 break;
1882
1883 case SND_SOC_BIAS_OFF:
1884 /* Turn off VMID */
1885 snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0,
1886 WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0);
1887
1888 /* Stop bias generation */
1889 snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0,
1890 WM8904_BIAS_ENA, 0);
1891
c1b88ee2
MB		 1892 regcache_cache_only(wm8904->regmap, true);
1893 regcache_mark_dirty(wm8904->regmap);
c1334218 1894
a91eb199
MB		 1895 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies),
1896 wm8904->supplies);
1897 break;
1898 }
ce6120cc 1899 codec->dapm.bias_level = level;
a91eb199
MB		 1900 return 0;
1901}
1902
1903#define WM8904_RATES SNDRV_PCM_RATE_8000_96000
1904
1905#define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1906 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1907
85e7652d 1908static const struct snd_soc_dai_ops wm8904_dai_ops = {
a91eb199
MB		 1909 .set_sysclk = wm8904_set_sysclk,
1910 .set_fmt = wm8904_set_fmt,
1911 .set_tdm_slot = wm8904_set_tdm_slot,
1912 .set_pll = wm8904_set_fll,
1913 .hw_params = wm8904_hw_params,
1914 .digital_mute = wm8904_digital_mute,
1915};
1916
f0fba2ad
LG		 1917static struct snd_soc_dai_driver wm8904_dai = {
1918 .name = "wm8904-hifi",
a91eb199
MB		 1919 .playback = {
1920 .stream_name = "Playback",
1921 .channels_min = 2,
1922 .channels_max = 2,
1923 .rates = WM8904_RATES,
1924 .formats = WM8904_FORMATS,
1925 },
1926 .capture = {
1927 .stream_name = "Capture",
1928 .channels_min = 2,
1929 .channels_max = 2,
1930 .rates = WM8904_RATES,
1931 .formats = WM8904_FORMATS,
1932 },
1933 .ops = &wm8904_dai_ops,
1934 .symmetric_rates = 1,
1935};
a91eb199 1936
f0fba2ad 1937static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec)
a91eb199 1938{
f0fba2ad 1939 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1940 struct wm8904_pdata *pdata = wm8904->pdata;
1941 struct snd_kcontrol_new control =
1942 SOC_ENUM_EXT("EQ Mode",
1943 wm8904->retune_mobile_enum,
1944 wm8904_get_retune_mobile_enum,
1945 wm8904_put_retune_mobile_enum);
1946 int ret, i, j;
1947 const char **t;
1948
1949 /* We need an array of texts for the enum API but the number
1950 * of texts is likely to be less than the number of
1951 * configurations due to the sample rate dependency of the
1952 * configurations. */
1953 wm8904->num_retune_mobile_texts = 0;
1954 wm8904->retune_mobile_texts = NULL;
1955 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
1956 for (j = 0; j < wm8904->num_retune_mobile_texts; j++) {
1957 if (strcmp(pdata->retune_mobile_cfgs[i].name,
1958 wm8904->retune_mobile_texts[j]) == 0)
1959 break;
1960 }
1961
1962 if (j != wm8904->num_retune_mobile_texts)
1963 continue;
1964
1965 /* Expand the array... */
1966 t = krealloc(wm8904->retune_mobile_texts,
1967 sizeof(char *) *
1968 (wm8904->num_retune_mobile_texts + 1),
1969 GFP_KERNEL);
1970 if (t == NULL)
1971 continue;
1972
1973 /* ...store the new entry... */
1974 t[wm8904->num_retune_mobile_texts] =
1975 pdata->retune_mobile_cfgs[i].name;
1976
1977 /* ...and remember the new version. */
1978 wm8904->num_retune_mobile_texts++;
1979 wm8904->retune_mobile_texts = t;
1980 }
1981
1982 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
1983 wm8904->num_retune_mobile_texts);
1984
9a8d38db 1985 wm8904->retune_mobile_enum.items = wm8904->num_retune_mobile_texts;
a91eb199
MB		 1986 wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts;
1987
022658be 1988 ret = snd_soc_add_codec_controls(codec, &control, 1);
a91eb199 1989 if (ret != 0)
f0fba2ad 1990 dev_err(codec->dev,
a91eb199
MB		 1991 "Failed to add ReTune Mobile control: %d\n", ret);
1992}
1993
f0fba2ad 1994static void wm8904_handle_pdata(struct snd_soc_codec *codec)
a91eb199 1995{
f0fba2ad 1996 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199
MB		 1997 struct wm8904_pdata *pdata = wm8904->pdata;
1998 int ret, i;
1999
2000 if (!pdata) {
022658be 2001 snd_soc_add_codec_controls(codec, wm8904_eq_controls,
a91eb199
MB		 2002 ARRAY_SIZE(wm8904_eq_controls));
2003 return;
2004 }
2005
2006 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2007
2008 if (pdata->num_drc_cfgs) {
2009 struct snd_kcontrol_new control =
2010 SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum,
2011 wm8904_get_drc_enum, wm8904_put_drc_enum);
2012
2013 /* We need an array of texts for the enum API */
2014 wm8904->drc_texts = kmalloc(sizeof(char *)
2015 * pdata->num_drc_cfgs, GFP_KERNEL);
2016 if (!wm8904->drc_texts) {
f0fba2ad 2017 dev_err(codec->dev,
a91eb199
MB		 2018 "Failed to allocate %d DRC config texts\n",
2019 pdata->num_drc_cfgs);
2020 return;
2021 }
2022
2023 for (i = 0; i < pdata->num_drc_cfgs; i++)
2024 wm8904->drc_texts[i] = pdata->drc_cfgs[i].name;
2025
9a8d38db 2026 wm8904->drc_enum.items = pdata->num_drc_cfgs;
a91eb199
MB		 2027 wm8904->drc_enum.texts = wm8904->drc_texts;
2028
022658be 2029 ret = snd_soc_add_codec_controls(codec, &control, 1);
a91eb199 2030 if (ret != 0)
f0fba2ad 2031 dev_err(codec->dev,
a91eb199
MB		 2032 "Failed to add DRC mode control: %d\n", ret);
2033
2034 wm8904_set_drc(codec);
2035 }
2036
2037 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2038 pdata->num_retune_mobile_cfgs);
2039
2040 if (pdata->num_retune_mobile_cfgs)
f0fba2ad 2041 wm8904_handle_retune_mobile_pdata(codec);
a91eb199 2042 else
022658be 2043 snd_soc_add_codec_controls(codec, wm8904_eq_controls,
a91eb199
MB		 2044 ARRAY_SIZE(wm8904_eq_controls));
2045}
2046
a91eb199 2047
f0fba2ad 2048static int wm8904_probe(struct snd_soc_codec *codec)
a91eb199 2049{
f0fba2ad 2050 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
a91eb199 2051
8c126474
MB		 2052 switch (wm8904->devtype) {
2053 case WM8904:
2054 break;
2055 case WM8912:
2056 memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture));
2057 break;
2058 default:
2059 dev_err(codec->dev, "Unknown device type %d\n",
2060 wm8904->devtype);
f0fba2ad 2061 return -EINVAL;
8c126474
MB		 2062 }
2063
f0fba2ad 2064 wm8904_handle_pdata(codec);
a91eb199 2065
f0fba2ad 2066 wm8904_add_widgets(codec);
a91eb199
MB		 2067
2068 return 0;
a91eb199
MB		 2069}
2070
f0fba2ad 2071static int wm8904_remove(struct snd_soc_codec *codec)
a91eb199 2072{
f0fba2ad
LG		 2073 struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec);
2074
cd70978c
AL		 2075 kfree(wm8904->retune_mobile_texts);
2076 kfree(wm8904->drc_texts);
f0fba2ad
LG		 2077
2078 return 0;
a91eb199
MB		 2079}
2080
f0fba2ad
LG		 2081static struct snd_soc_codec_driver soc_codec_dev_wm8904 = {
2082 .probe = wm8904_probe,
2083 .remove = wm8904_remove,
f0fba2ad 2084 .set_bias_level = wm8904_set_bias_level,
eb3032f8 2085 .idle_bias_off = true,
84d0d831
MB		 2086};
2087
2088static const struct regmap_config wm8904_regmap = {
2089 .reg_bits = 8,
2090 .val_bits = 16,
2091
2092 .max_register = WM8904_MAX_REGISTER,
2093 .volatile_reg = wm8904_volatile_register,
2094 .readable_reg = wm8904_readable_register,
2095
2096 .cache_type = REGCACHE_RBTREE,
2097 .reg_defaults = wm8904_reg_defaults,
2098 .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults),
f0fba2ad
LG		 2099};
2100
7a79e94e
BP		 2101static int wm8904_i2c_probe(struct i2c_client *i2c,
2102 const struct i2c_device_id *id)
a91eb199
MB		 2103{
2104 struct wm8904_priv *wm8904;
03862cf6
MB		 2105 unsigned int val;
2106 int ret, i;
a91eb199 2107
93e26d4e
MB		 2108 wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv),
2109 GFP_KERNEL);
a91eb199
MB		 2110 if (wm8904 == NULL)
2111 return -ENOMEM;
2112
d633edd9 2113 wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap);
84d0d831
MB		 2114 if (IS_ERR(wm8904->regmap)) {
2115 ret = PTR_ERR(wm8904->regmap);
2116 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2117 ret);
2118 return ret;
2119 }
2120
8c126474 2121 wm8904->devtype = id->driver_data;
a91eb199 2122 i2c_set_clientdata(i2c, wm8904);
a91eb199
MB		 2123 wm8904->pdata = i2c->dev.platform_data;
2124
03862cf6
MB		 2125 for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++)
2126 wm8904->supplies[i].supply = wm8904_supply_names[i];
2127
2128 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies),
2129 wm8904->supplies);
2130 if (ret != 0) {
2131 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2132 return ret;
2133 }
2134
2135 ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies),
2136 wm8904->supplies);
2137 if (ret != 0) {
2138 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2139 return ret;
2140 }
2141
2142 ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val);
2143 if (ret < 0) {
2144 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2145 goto err_enable;
2146 }
2147 if (val != 0x8904) {
2148 dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val);
2149 ret = -EINVAL;
2150 goto err_enable;
2151 }
2152
2153 ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val);
2154 if (ret < 0) {
2155 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2156 ret);
2157 goto err_enable;
2158 }
2159 dev_info(&i2c->dev, "revision %c\n", val + 'A');
2160
2161 ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0);
2162 if (ret < 0) {
2163 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2164 goto err_enable;
2165 }
2166
725e7a7b
MB		 2167 /* Change some default settings - latch VU and enable ZC */
2168 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT,
2169 WM8904_ADC_VU, WM8904_ADC_VU);
2170 regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT,
2171 WM8904_ADC_VU, WM8904_ADC_VU);
2172 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT,
2173 WM8904_DAC_VU, WM8904_DAC_VU);
2174 regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT,
2175 WM8904_DAC_VU, WM8904_DAC_VU);
2176 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT,
2177 WM8904_HPOUT_VU | WM8904_HPOUTLZC,
2178 WM8904_HPOUT_VU | WM8904_HPOUTLZC);
2179 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT,
2180 WM8904_HPOUT_VU | WM8904_HPOUTRZC,
2181 WM8904_HPOUT_VU | WM8904_HPOUTRZC);
2182 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT,
2183 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC,
2184 WM8904_LINEOUT_VU | WM8904_LINEOUTLZC);
2185 regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT,
2186 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC,
2187 WM8904_LINEOUT_VU | WM8904_LINEOUTRZC);
2188 regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0,
2189 WM8904_SR_MODE, 0);
2190
2191 /* Apply configuration from the platform data. */
2192 if (wm8904->pdata) {
2193 for (i = 0; i < WM8904_GPIO_REGS; i++) {
2194 if (!wm8904->pdata->gpio_cfg[i])
2195 continue;
2196
2197 regmap_update_bits(wm8904->regmap,
2198 WM8904_GPIO_CONTROL_1 + i,
2199 0xffff,
2200 wm8904->pdata->gpio_cfg[i]);
2201 }
2202
2203 /* Zero is the default value for these anyway */
2204 for (i = 0; i < WM8904_MIC_REGS; i++)
2205 regmap_update_bits(wm8904->regmap,
2206 WM8904_MIC_BIAS_CONTROL_0 + i,
2207 0xffff,
2208 wm8904->pdata->mic_cfg[i]);
2209 }
2210
2211 /* Set Class W by default - this will be managed by the Class
2212 * G widget at runtime where bypass paths are available.
2213 */
2214 regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0,
2215 WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR);
2216
2217 /* Use normal bias source */
2218 regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0,
2219 WM8904_POBCTRL, 0);
2220
03862cf6
MB		 2221 /* Can leave the device powered off until we need it */
2222 regcache_cache_only(wm8904->regmap, true);
2223 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
2224
f0fba2ad
LG		 2225 ret = snd_soc_register_codec(&i2c->dev,
2226 &soc_codec_dev_wm8904, &wm8904_dai, 1);
84d0d831 2227 if (ret != 0)
03862cf6 2228 return ret;
84d0d831
MB		 2229
2230 return 0;
93e26d4e 2231
03862cf6
MB		 2232err_enable:
2233 regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies);
f0fba2ad 2234 return ret;
a91eb199
MB		 2235}
2236
7a79e94e 2237static int wm8904_i2c_remove(struct i2c_client *client)
a91eb199 2238{
f0fba2ad 2239 snd_soc_unregister_codec(&client->dev);
a91eb199
MB		 2240 return 0;
2241}
2242
2243static const struct i2c_device_id wm8904_i2c_id[] = {
8c126474
MB		 2244 { "wm8904", WM8904 },
2245 { "wm8912", WM8912 },
df1553c8 2246 { "wm8918", WM8904 }, /* Actually a subset, updates to follow */
a91eb199
MB		 2247 { }
2248};
2249MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id);
2250
2251static struct i2c_driver wm8904_i2c_driver = {
2252 .driver = {
091edccf 2253 .name = "wm8904",
a91eb199
MB		 2254 .owner = THIS_MODULE,
2255 },
2256 .probe = wm8904_i2c_probe,
7a79e94e 2257 .remove = wm8904_i2c_remove,
a91eb199
MB		 2258 .id_table = wm8904_i2c_id,
2259};
a91eb199 2260
8cb28fd6 2261module_i2c_driver(wm8904_i2c_driver);
a91eb199
MB		 2262
2263MODULE_DESCRIPTION("ASoC WM8904 driver");
2264MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2265MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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