Commit | Line | Data |
---|---|---|
a91eb199 MB |
1 | /* |
2 | * wm8904.c -- WM8904 ALSA SoC Audio driver | |
3 | * | |
656baaeb | 4 | * Copyright 2009-12 Wolfson Microelectronics plc |
a91eb199 MB |
5 | * |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
84d0d831 | 20 | #include <linux/regmap.h> |
a91eb199 | 21 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 22 | #include <linux/slab.h> |
a91eb199 MB |
23 | #include <sound/core.h> |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
a91eb199 MB |
27 | #include <sound/initval.h> |
28 | #include <sound/tlv.h> | |
29 | #include <sound/wm8904.h> | |
30 | ||
31 | #include "wm8904.h" | |
32 | ||
8c126474 MB |
33 | enum wm8904_type { |
34 | WM8904, | |
35 | WM8912, | |
36 | }; | |
37 | ||
a91eb199 MB |
38 | #define WM8904_NUM_DCS_CHANNELS 4 |
39 | ||
40 | #define WM8904_NUM_SUPPLIES 5 | |
41 | static const char *wm8904_supply_names[WM8904_NUM_SUPPLIES] = { | |
42 | "DCVDD", | |
43 | "DBVDD", | |
44 | "AVDD", | |
45 | "CPVDD", | |
46 | "MICVDD", | |
47 | }; | |
48 | ||
49 | /* codec private data */ | |
50 | struct wm8904_priv { | |
84d0d831 | 51 | struct regmap *regmap; |
f0fba2ad | 52 | |
8c126474 MB |
53 | enum wm8904_type devtype; |
54 | ||
a91eb199 MB |
55 | struct regulator_bulk_data supplies[WM8904_NUM_SUPPLIES]; |
56 | ||
57 | struct wm8904_pdata *pdata; | |
58 | ||
59 | int deemph; | |
60 | ||
61 | /* Platform provided DRC configuration */ | |
62 | const char **drc_texts; | |
63 | int drc_cfg; | |
64 | struct soc_enum drc_enum; | |
65 | ||
66 | /* Platform provided ReTune mobile configuration */ | |
67 | int num_retune_mobile_texts; | |
68 | const char **retune_mobile_texts; | |
69 | int retune_mobile_cfg; | |
70 | struct soc_enum retune_mobile_enum; | |
71 | ||
72 | /* FLL setup */ | |
73 | int fll_src; | |
74 | int fll_fref; | |
75 | int fll_fout; | |
76 | ||
77 | /* Clocking configuration */ | |
78 | unsigned int mclk_rate; | |
79 | int sysclk_src; | |
80 | unsigned int sysclk_rate; | |
81 | ||
82 | int tdm_width; | |
83 | int tdm_slots; | |
84 | int bclk; | |
85 | int fs; | |
86 | ||
87 | /* DC servo configuration - cached offset values */ | |
88 | int dcs_state[WM8904_NUM_DCS_CHANNELS]; | |
89 | }; | |
90 | ||
84d0d831 MB |
91 | static const struct reg_default wm8904_reg_defaults[] = { |
92 | { 4, 0x0018 }, /* R4 - Bias Control 0 */ | |
93 | { 5, 0x0000 }, /* R5 - VMID Control 0 */ | |
94 | { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */ | |
95 | { 7, 0x0000 }, /* R7 - Mic Bias Control 1 */ | |
96 | { 8, 0x0001 }, /* R8 - Analogue DAC 0 */ | |
97 | { 9, 0x9696 }, /* R9 - mic Filter Control */ | |
98 | { 10, 0x0001 }, /* R10 - Analogue ADC 0 */ | |
99 | { 12, 0x0000 }, /* R12 - Power Management 0 */ | |
100 | { 14, 0x0000 }, /* R14 - Power Management 2 */ | |
101 | { 15, 0x0000 }, /* R15 - Power Management 3 */ | |
102 | { 18, 0x0000 }, /* R18 - Power Management 6 */ | |
985b11fa | 103 | { 20, 0x945E }, /* R20 - Clock Rates 0 */ |
84d0d831 MB |
104 | { 21, 0x0C05 }, /* R21 - Clock Rates 1 */ |
105 | { 22, 0x0006 }, /* R22 - Clock Rates 2 */ | |
106 | { 24, 0x0050 }, /* R24 - Audio Interface 0 */ | |
107 | { 25, 0x000A }, /* R25 - Audio Interface 1 */ | |
108 | { 26, 0x00E4 }, /* R26 - Audio Interface 2 */ | |
109 | { 27, 0x0040 }, /* R27 - Audio Interface 3 */ | |
110 | { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */ | |
111 | { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */ | |
112 | { 32, 0x0000 }, /* R32 - DAC Digital 0 */ | |
113 | { 33, 0x0008 }, /* R33 - DAC Digital 1 */ | |
114 | { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */ | |
115 | { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */ | |
116 | { 38, 0x0010 }, /* R38 - ADC Digital 0 */ | |
117 | { 39, 0x0000 }, /* R39 - Digital Microphone 0 */ | |
118 | { 40, 0x01AF }, /* R40 - DRC 0 */ | |
119 | { 41, 0x3248 }, /* R41 - DRC 1 */ | |
120 | { 42, 0x0000 }, /* R42 - DRC 2 */ | |
121 | { 43, 0x0000 }, /* R43 - DRC 3 */ | |
122 | { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */ | |
123 | { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */ | |
124 | { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */ | |
125 | { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */ | |
126 | { 57, 0x002D }, /* R57 - Analogue OUT1 Left */ | |
127 | { 58, 0x002D }, /* R58 - Analogue OUT1 Right */ | |
128 | { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */ | |
129 | { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */ | |
130 | { 61, 0x0000 }, /* R61 - Analogue OUT12 ZC */ | |
131 | { 67, 0x0000 }, /* R67 - DC Servo 0 */ | |
132 | { 69, 0xAAAA }, /* R69 - DC Servo 2 */ | |
133 | { 71, 0xAAAA }, /* R71 - DC Servo 4 */ | |
134 | { 72, 0xAAAA }, /* R72 - DC Servo 5 */ | |
135 | { 90, 0x0000 }, /* R90 - Analogue HP 0 */ | |
136 | { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */ | |
137 | { 98, 0x0000 }, /* R98 - Charge Pump 0 */ | |
138 | { 104, 0x0004 }, /* R104 - Class W 0 */ | |
139 | { 108, 0x0000 }, /* R108 - Write Sequencer 0 */ | |
140 | { 109, 0x0000 }, /* R109 - Write Sequencer 1 */ | |
141 | { 110, 0x0000 }, /* R110 - Write Sequencer 2 */ | |
142 | { 111, 0x0000 }, /* R111 - Write Sequencer 3 */ | |
143 | { 112, 0x0000 }, /* R112 - Write Sequencer 4 */ | |
144 | { 116, 0x0000 }, /* R116 - FLL Control 1 */ | |
145 | { 117, 0x0007 }, /* R117 - FLL Control 2 */ | |
146 | { 118, 0x0000 }, /* R118 - FLL Control 3 */ | |
147 | { 119, 0x2EE0 }, /* R119 - FLL Control 4 */ | |
148 | { 120, 0x0004 }, /* R120 - FLL Control 5 */ | |
149 | { 121, 0x0014 }, /* R121 - GPIO Control 1 */ | |
150 | { 122, 0x0010 }, /* R122 - GPIO Control 2 */ | |
151 | { 123, 0x0010 }, /* R123 - GPIO Control 3 */ | |
152 | { 124, 0x0000 }, /* R124 - GPIO Control 4 */ | |
153 | { 126, 0x0000 }, /* R126 - Digital Pulls */ | |
154 | { 128, 0xFFFF }, /* R128 - Interrupt Status Mask */ | |
155 | { 129, 0x0000 }, /* R129 - Interrupt Polarity */ | |
156 | { 130, 0x0000 }, /* R130 - Interrupt Debounce */ | |
157 | { 134, 0x0000 }, /* R134 - EQ1 */ | |
158 | { 135, 0x000C }, /* R135 - EQ2 */ | |
159 | { 136, 0x000C }, /* R136 - EQ3 */ | |
160 | { 137, 0x000C }, /* R137 - EQ4 */ | |
161 | { 138, 0x000C }, /* R138 - EQ5 */ | |
162 | { 139, 0x000C }, /* R139 - EQ6 */ | |
163 | { 140, 0x0FCA }, /* R140 - EQ7 */ | |
164 | { 141, 0x0400 }, /* R141 - EQ8 */ | |
165 | { 142, 0x00D8 }, /* R142 - EQ9 */ | |
166 | { 143, 0x1EB5 }, /* R143 - EQ10 */ | |
167 | { 144, 0xF145 }, /* R144 - EQ11 */ | |
168 | { 145, 0x0B75 }, /* R145 - EQ12 */ | |
169 | { 146, 0x01C5 }, /* R146 - EQ13 */ | |
170 | { 147, 0x1C58 }, /* R147 - EQ14 */ | |
171 | { 148, 0xF373 }, /* R148 - EQ15 */ | |
172 | { 149, 0x0A54 }, /* R149 - EQ16 */ | |
173 | { 150, 0x0558 }, /* R150 - EQ17 */ | |
174 | { 151, 0x168E }, /* R151 - EQ18 */ | |
175 | { 152, 0xF829 }, /* R152 - EQ19 */ | |
176 | { 153, 0x07AD }, /* R153 - EQ20 */ | |
177 | { 154, 0x1103 }, /* R154 - EQ21 */ | |
178 | { 155, 0x0564 }, /* R155 - EQ22 */ | |
179 | { 156, 0x0559 }, /* R156 - EQ23 */ | |
180 | { 157, 0x4000 }, /* R157 - EQ24 */ | |
181 | { 161, 0x0000 }, /* R161 - Control Interface Test 1 */ | |
182 | { 204, 0x0000 }, /* R204 - Analogue Output Bias 0 */ | |
183 | { 247, 0x0000 }, /* R247 - FLL NCO Test 0 */ | |
184 | { 248, 0x0019 }, /* R248 - FLL NCO Test 1 */ | |
a91eb199 MB |
185 | }; |
186 | ||
84d0d831 MB |
187 | static bool wm8904_volatile_register(struct device *dev, unsigned int reg) |
188 | { | |
189 | switch (reg) { | |
190 | case WM8904_SW_RESET_AND_ID: | |
191 | case WM8904_REVISION: | |
192 | case WM8904_DC_SERVO_1: | |
193 | case WM8904_DC_SERVO_6: | |
194 | case WM8904_DC_SERVO_7: | |
195 | case WM8904_DC_SERVO_8: | |
196 | case WM8904_DC_SERVO_9: | |
197 | case WM8904_DC_SERVO_READBACK_0: | |
198 | case WM8904_INTERRUPT_STATUS: | |
199 | return true; | |
200 | default: | |
201 | return false; | |
202 | } | |
203 | } | |
a91eb199 | 204 | |
84d0d831 | 205 | static bool wm8904_readable_register(struct device *dev, unsigned int reg) |
a91eb199 | 206 | { |
84d0d831 MB |
207 | switch (reg) { |
208 | case WM8904_SW_RESET_AND_ID: | |
209 | case WM8904_REVISION: | |
210 | case WM8904_BIAS_CONTROL_0: | |
211 | case WM8904_VMID_CONTROL_0: | |
212 | case WM8904_MIC_BIAS_CONTROL_0: | |
213 | case WM8904_MIC_BIAS_CONTROL_1: | |
214 | case WM8904_ANALOGUE_DAC_0: | |
215 | case WM8904_MIC_FILTER_CONTROL: | |
216 | case WM8904_ANALOGUE_ADC_0: | |
217 | case WM8904_POWER_MANAGEMENT_0: | |
218 | case WM8904_POWER_MANAGEMENT_2: | |
219 | case WM8904_POWER_MANAGEMENT_3: | |
220 | case WM8904_POWER_MANAGEMENT_6: | |
221 | case WM8904_CLOCK_RATES_0: | |
222 | case WM8904_CLOCK_RATES_1: | |
223 | case WM8904_CLOCK_RATES_2: | |
224 | case WM8904_AUDIO_INTERFACE_0: | |
225 | case WM8904_AUDIO_INTERFACE_1: | |
226 | case WM8904_AUDIO_INTERFACE_2: | |
227 | case WM8904_AUDIO_INTERFACE_3: | |
228 | case WM8904_DAC_DIGITAL_VOLUME_LEFT: | |
229 | case WM8904_DAC_DIGITAL_VOLUME_RIGHT: | |
230 | case WM8904_DAC_DIGITAL_0: | |
231 | case WM8904_DAC_DIGITAL_1: | |
232 | case WM8904_ADC_DIGITAL_VOLUME_LEFT: | |
233 | case WM8904_ADC_DIGITAL_VOLUME_RIGHT: | |
234 | case WM8904_ADC_DIGITAL_0: | |
235 | case WM8904_DIGITAL_MICROPHONE_0: | |
236 | case WM8904_DRC_0: | |
237 | case WM8904_DRC_1: | |
238 | case WM8904_DRC_2: | |
239 | case WM8904_DRC_3: | |
240 | case WM8904_ANALOGUE_LEFT_INPUT_0: | |
241 | case WM8904_ANALOGUE_RIGHT_INPUT_0: | |
242 | case WM8904_ANALOGUE_LEFT_INPUT_1: | |
243 | case WM8904_ANALOGUE_RIGHT_INPUT_1: | |
244 | case WM8904_ANALOGUE_OUT1_LEFT: | |
245 | case WM8904_ANALOGUE_OUT1_RIGHT: | |
246 | case WM8904_ANALOGUE_OUT2_LEFT: | |
247 | case WM8904_ANALOGUE_OUT2_RIGHT: | |
248 | case WM8904_ANALOGUE_OUT12_ZC: | |
249 | case WM8904_DC_SERVO_0: | |
250 | case WM8904_DC_SERVO_1: | |
251 | case WM8904_DC_SERVO_2: | |
252 | case WM8904_DC_SERVO_4: | |
253 | case WM8904_DC_SERVO_5: | |
254 | case WM8904_DC_SERVO_6: | |
255 | case WM8904_DC_SERVO_7: | |
256 | case WM8904_DC_SERVO_8: | |
257 | case WM8904_DC_SERVO_9: | |
258 | case WM8904_DC_SERVO_READBACK_0: | |
259 | case WM8904_ANALOGUE_HP_0: | |
260 | case WM8904_ANALOGUE_LINEOUT_0: | |
261 | case WM8904_CHARGE_PUMP_0: | |
262 | case WM8904_CLASS_W_0: | |
263 | case WM8904_WRITE_SEQUENCER_0: | |
264 | case WM8904_WRITE_SEQUENCER_1: | |
265 | case WM8904_WRITE_SEQUENCER_2: | |
266 | case WM8904_WRITE_SEQUENCER_3: | |
267 | case WM8904_WRITE_SEQUENCER_4: | |
268 | case WM8904_FLL_CONTROL_1: | |
269 | case WM8904_FLL_CONTROL_2: | |
270 | case WM8904_FLL_CONTROL_3: | |
271 | case WM8904_FLL_CONTROL_4: | |
272 | case WM8904_FLL_CONTROL_5: | |
273 | case WM8904_GPIO_CONTROL_1: | |
274 | case WM8904_GPIO_CONTROL_2: | |
275 | case WM8904_GPIO_CONTROL_3: | |
276 | case WM8904_GPIO_CONTROL_4: | |
277 | case WM8904_DIGITAL_PULLS: | |
278 | case WM8904_INTERRUPT_STATUS: | |
279 | case WM8904_INTERRUPT_STATUS_MASK: | |
280 | case WM8904_INTERRUPT_POLARITY: | |
281 | case WM8904_INTERRUPT_DEBOUNCE: | |
282 | case WM8904_EQ1: | |
283 | case WM8904_EQ2: | |
284 | case WM8904_EQ3: | |
285 | case WM8904_EQ4: | |
286 | case WM8904_EQ5: | |
287 | case WM8904_EQ6: | |
288 | case WM8904_EQ7: | |
289 | case WM8904_EQ8: | |
290 | case WM8904_EQ9: | |
291 | case WM8904_EQ10: | |
292 | case WM8904_EQ11: | |
293 | case WM8904_EQ12: | |
294 | case WM8904_EQ13: | |
295 | case WM8904_EQ14: | |
296 | case WM8904_EQ15: | |
297 | case WM8904_EQ16: | |
298 | case WM8904_EQ17: | |
299 | case WM8904_EQ18: | |
300 | case WM8904_EQ19: | |
301 | case WM8904_EQ20: | |
302 | case WM8904_EQ21: | |
303 | case WM8904_EQ22: | |
304 | case WM8904_EQ23: | |
305 | case WM8904_EQ24: | |
306 | case WM8904_CONTROL_INTERFACE_TEST_1: | |
9b85fc90 | 307 | case WM8904_ADC_TEST_0: |
84d0d831 MB |
308 | case WM8904_ANALOGUE_OUTPUT_BIAS_0: |
309 | case WM8904_FLL_NCO_TEST_0: | |
310 | case WM8904_FLL_NCO_TEST_1: | |
311 | return true; | |
312 | default: | |
313 | return true; | |
314 | } | |
a91eb199 MB |
315 | } |
316 | ||
a91eb199 MB |
317 | static int wm8904_configure_clocking(struct snd_soc_codec *codec) |
318 | { | |
b2c812e2 | 319 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
320 | unsigned int clock0, clock2, rate; |
321 | ||
322 | /* Gate the clock while we're updating to avoid misclocking */ | |
323 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); | |
324 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
325 | WM8904_SYSCLK_SRC, 0); | |
326 | ||
327 | /* This should be done on init() for bypass paths */ | |
328 | switch (wm8904->sysclk_src) { | |
329 | case WM8904_CLK_MCLK: | |
330 | dev_dbg(codec->dev, "Using %dHz MCLK\n", wm8904->mclk_rate); | |
331 | ||
332 | clock2 &= ~WM8904_SYSCLK_SRC; | |
333 | rate = wm8904->mclk_rate; | |
334 | ||
335 | /* Ensure the FLL is stopped */ | |
336 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
337 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
338 | break; | |
339 | ||
340 | case WM8904_CLK_FLL: | |
341 | dev_dbg(codec->dev, "Using %dHz FLL clock\n", | |
342 | wm8904->fll_fout); | |
343 | ||
344 | clock2 |= WM8904_SYSCLK_SRC; | |
345 | rate = wm8904->fll_fout; | |
346 | break; | |
347 | ||
348 | default: | |
349 | dev_err(codec->dev, "System clock not configured\n"); | |
350 | return -EINVAL; | |
351 | } | |
352 | ||
353 | /* SYSCLK shouldn't be over 13.5MHz */ | |
354 | if (rate > 13500000) { | |
355 | clock0 = WM8904_MCLK_DIV; | |
356 | wm8904->sysclk_rate = rate / 2; | |
357 | } else { | |
358 | clock0 = 0; | |
359 | wm8904->sysclk_rate = rate; | |
360 | } | |
361 | ||
362 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_0, WM8904_MCLK_DIV, | |
363 | clock0); | |
364 | ||
365 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
366 | WM8904_CLK_SYS_ENA | WM8904_SYSCLK_SRC, clock2); | |
367 | ||
368 | dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm8904->sysclk_rate); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static void wm8904_set_drc(struct snd_soc_codec *codec) | |
374 | { | |
b2c812e2 | 375 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
376 | struct wm8904_pdata *pdata = wm8904->pdata; |
377 | int save, i; | |
378 | ||
379 | /* Save any enables; the configuration should clear them. */ | |
380 | save = snd_soc_read(codec, WM8904_DRC_0); | |
381 | ||
382 | for (i = 0; i < WM8904_DRC_REGS; i++) | |
383 | snd_soc_update_bits(codec, WM8904_DRC_0 + i, 0xffff, | |
384 | pdata->drc_cfgs[wm8904->drc_cfg].regs[i]); | |
385 | ||
386 | /* Reenable the DRC */ | |
387 | snd_soc_update_bits(codec, WM8904_DRC_0, | |
388 | WM8904_DRC_ENA | WM8904_DRC_DAC_PATH, save); | |
389 | } | |
390 | ||
391 | static int wm8904_put_drc_enum(struct snd_kcontrol *kcontrol, | |
392 | struct snd_ctl_elem_value *ucontrol) | |
393 | { | |
394 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 395 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
396 | struct wm8904_pdata *pdata = wm8904->pdata; |
397 | int value = ucontrol->value.integer.value[0]; | |
398 | ||
399 | if (value >= pdata->num_drc_cfgs) | |
400 | return -EINVAL; | |
401 | ||
402 | wm8904->drc_cfg = value; | |
403 | ||
404 | wm8904_set_drc(codec); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | static int wm8904_get_drc_enum(struct snd_kcontrol *kcontrol, | |
410 | struct snd_ctl_elem_value *ucontrol) | |
411 | { | |
412 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 413 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
414 | |
415 | ucontrol->value.enumerated.item[0] = wm8904->drc_cfg; | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static void wm8904_set_retune_mobile(struct snd_soc_codec *codec) | |
421 | { | |
b2c812e2 | 422 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
423 | struct wm8904_pdata *pdata = wm8904->pdata; |
424 | int best, best_val, save, i, cfg; | |
425 | ||
426 | if (!pdata || !wm8904->num_retune_mobile_texts) | |
427 | return; | |
428 | ||
429 | /* Find the version of the currently selected configuration | |
430 | * with the nearest sample rate. */ | |
431 | cfg = wm8904->retune_mobile_cfg; | |
432 | best = 0; | |
433 | best_val = INT_MAX; | |
434 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
435 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
436 | wm8904->retune_mobile_texts[cfg]) == 0 && | |
437 | abs(pdata->retune_mobile_cfgs[i].rate | |
438 | - wm8904->fs) < best_val) { | |
439 | best = i; | |
440 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
441 | - wm8904->fs); | |
442 | } | |
443 | } | |
444 | ||
445 | dev_dbg(codec->dev, "ReTune Mobile %s/%dHz for %dHz sample rate\n", | |
446 | pdata->retune_mobile_cfgs[best].name, | |
447 | pdata->retune_mobile_cfgs[best].rate, | |
448 | wm8904->fs); | |
449 | ||
450 | /* The EQ will be disabled while reconfiguring it, remember the | |
451 | * current configuration. | |
452 | */ | |
453 | save = snd_soc_read(codec, WM8904_EQ1); | |
454 | ||
455 | for (i = 0; i < WM8904_EQ_REGS; i++) | |
456 | snd_soc_update_bits(codec, WM8904_EQ1 + i, 0xffff, | |
457 | pdata->retune_mobile_cfgs[best].regs[i]); | |
458 | ||
459 | snd_soc_update_bits(codec, WM8904_EQ1, WM8904_EQ_ENA, save); | |
460 | } | |
461 | ||
462 | static int wm8904_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
463 | struct snd_ctl_elem_value *ucontrol) | |
464 | { | |
465 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 466 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
467 | struct wm8904_pdata *pdata = wm8904->pdata; |
468 | int value = ucontrol->value.integer.value[0]; | |
469 | ||
470 | if (value >= pdata->num_retune_mobile_cfgs) | |
471 | return -EINVAL; | |
472 | ||
473 | wm8904->retune_mobile_cfg = value; | |
474 | ||
475 | wm8904_set_retune_mobile(codec); | |
476 | ||
477 | return 0; | |
478 | } | |
479 | ||
480 | static int wm8904_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
481 | struct snd_ctl_elem_value *ucontrol) | |
482 | { | |
483 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 484 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
485 | |
486 | ucontrol->value.enumerated.item[0] = wm8904->retune_mobile_cfg; | |
487 | ||
488 | return 0; | |
489 | } | |
490 | ||
491 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
492 | ||
493 | static int wm8904_set_deemph(struct snd_soc_codec *codec) | |
494 | { | |
b2c812e2 | 495 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
496 | int val, i, best; |
497 | ||
498 | /* If we're using deemphasis select the nearest available sample | |
499 | * rate. | |
500 | */ | |
501 | if (wm8904->deemph) { | |
502 | best = 1; | |
503 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
504 | if (abs(deemph_settings[i] - wm8904->fs) < | |
505 | abs(deemph_settings[best] - wm8904->fs)) | |
506 | best = i; | |
507 | } | |
508 | ||
509 | val = best << WM8904_DEEMPH_SHIFT; | |
510 | } else { | |
511 | val = 0; | |
512 | } | |
513 | ||
514 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
515 | ||
516 | return snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
517 | WM8904_DEEMPH_MASK, val); | |
518 | } | |
519 | ||
520 | static int wm8904_get_deemph(struct snd_kcontrol *kcontrol, | |
521 | struct snd_ctl_elem_value *ucontrol) | |
522 | { | |
523 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 524 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 | 525 | |
3f343f85 DA |
526 | ucontrol->value.enumerated.item[0] = wm8904->deemph; |
527 | return 0; | |
a91eb199 MB |
528 | } |
529 | ||
530 | static int wm8904_put_deemph(struct snd_kcontrol *kcontrol, | |
531 | struct snd_ctl_elem_value *ucontrol) | |
532 | { | |
533 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 534 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
535 | int deemph = ucontrol->value.enumerated.item[0]; |
536 | ||
537 | if (deemph > 1) | |
538 | return -EINVAL; | |
539 | ||
540 | wm8904->deemph = deemph; | |
541 | ||
542 | return wm8904_set_deemph(codec); | |
543 | } | |
544 | ||
545 | static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0); | |
546 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
547 | static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0); | |
548 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0); | |
549 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
550 | ||
551 | static const char *input_mode_text[] = { | |
552 | "Single-Ended", "Differential Line", "Differential Mic" | |
553 | }; | |
554 | ||
555 | static const struct soc_enum lin_mode = | |
556 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text); | |
557 | ||
558 | static const struct soc_enum rin_mode = | |
559 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text); | |
560 | ||
561 | static const char *hpf_mode_text[] = { | |
562 | "Hi-fi", "Voice 1", "Voice 2", "Voice 3" | |
563 | }; | |
564 | ||
565 | static const struct soc_enum hpf_mode = | |
566 | SOC_ENUM_SINGLE(WM8904_ADC_DIGITAL_0, 5, 4, hpf_mode_text); | |
567 | ||
9b85fc90 MB |
568 | static int wm8904_adc_osr_put(struct snd_kcontrol *kcontrol, |
569 | struct snd_ctl_elem_value *ucontrol) | |
570 | { | |
571 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
572 | unsigned int val; | |
573 | int ret; | |
574 | ||
575 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
576 | if (ret < 0) | |
577 | return ret; | |
578 | ||
579 | if (ucontrol->value.integer.value[0]) | |
580 | val = 0; | |
581 | else | |
582 | val = WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5; | |
583 | ||
584 | snd_soc_update_bits(codec, WM8904_ADC_TEST_0, | |
585 | WM8904_ADC_128_OSR_TST_MODE | WM8904_ADC_BIASX1P5, | |
586 | val); | |
587 | ||
588 | return ret; | |
589 | } | |
590 | ||
a91eb199 MB |
591 | static const struct snd_kcontrol_new wm8904_adc_snd_controls[] = { |
592 | SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
593 | WM8904_ADC_DIGITAL_VOLUME_RIGHT, 1, 119, 0, digital_tlv), | |
594 | ||
595 | SOC_ENUM("Left Caputure Mode", lin_mode), | |
596 | SOC_ENUM("Right Capture Mode", rin_mode), | |
597 | ||
598 | /* No TLV since it depends on mode */ | |
599 | SOC_DOUBLE_R("Capture Volume", WM8904_ANALOGUE_LEFT_INPUT_0, | |
600 | WM8904_ANALOGUE_RIGHT_INPUT_0, 0, 31, 0), | |
601 | SOC_DOUBLE_R("Capture Switch", WM8904_ANALOGUE_LEFT_INPUT_0, | |
5a7c5f26 | 602 | WM8904_ANALOGUE_RIGHT_INPUT_0, 7, 1, 1), |
a91eb199 MB |
603 | |
604 | SOC_SINGLE("High Pass Filter Switch", WM8904_ADC_DIGITAL_0, 4, 1, 0), | |
605 | SOC_ENUM("High Pass Filter Mode", hpf_mode), | |
606 | ||
9b85fc90 MB |
607 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
608 | .name = "ADC 128x OSR Switch", | |
609 | .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, | |
610 | .put = wm8904_adc_osr_put, | |
611 | .private_value = SOC_SINGLE_VALUE(WM8904_ANALOGUE_ADC_0, 0, 1, 0), | |
612 | }, | |
a91eb199 MB |
613 | }; |
614 | ||
615 | static const char *drc_path_text[] = { | |
616 | "ADC", "DAC" | |
617 | }; | |
618 | ||
619 | static const struct soc_enum drc_path = | |
620 | SOC_ENUM_SINGLE(WM8904_DRC_0, 14, 2, drc_path_text); | |
621 | ||
622 | static const struct snd_kcontrol_new wm8904_dac_snd_controls[] = { | |
623 | SOC_SINGLE_TLV("Digital Playback Boost Volume", | |
624 | WM8904_AUDIO_INTERFACE_0, 9, 3, 0, dac_boost_tlv), | |
625 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
626 | WM8904_DAC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv), | |
627 | ||
628 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8904_ANALOGUE_OUT1_LEFT, | |
629 | WM8904_ANALOGUE_OUT1_RIGHT, 0, 63, 0, out_tlv), | |
630 | SOC_DOUBLE_R("Headphone Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
631 | WM8904_ANALOGUE_OUT1_RIGHT, 8, 1, 1), | |
632 | SOC_DOUBLE_R("Headphone ZC Switch", WM8904_ANALOGUE_OUT1_LEFT, | |
633 | WM8904_ANALOGUE_OUT1_RIGHT, 6, 1, 0), | |
634 | ||
635 | SOC_DOUBLE_R_TLV("Line Output Volume", WM8904_ANALOGUE_OUT2_LEFT, | |
636 | WM8904_ANALOGUE_OUT2_RIGHT, 0, 63, 0, out_tlv), | |
637 | SOC_DOUBLE_R("Line Output Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
638 | WM8904_ANALOGUE_OUT2_RIGHT, 8, 1, 1), | |
639 | SOC_DOUBLE_R("Line Output ZC Switch", WM8904_ANALOGUE_OUT2_LEFT, | |
640 | WM8904_ANALOGUE_OUT2_RIGHT, 6, 1, 0), | |
641 | ||
642 | SOC_SINGLE("EQ Switch", WM8904_EQ1, 0, 1, 0), | |
643 | SOC_SINGLE("DRC Switch", WM8904_DRC_0, 15, 1, 0), | |
644 | SOC_ENUM("DRC Path", drc_path), | |
645 | SOC_SINGLE("DAC OSRx2 Switch", WM8904_DAC_DIGITAL_1, 6, 1, 0), | |
646 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
647 | wm8904_get_deemph, wm8904_put_deemph), | |
648 | }; | |
649 | ||
650 | static const struct snd_kcontrol_new wm8904_snd_controls[] = { | |
651 | SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8904_DAC_DIGITAL_0, 4, 8, 15, 0, | |
652 | sidetone_tlv), | |
653 | }; | |
654 | ||
655 | static const struct snd_kcontrol_new wm8904_eq_controls[] = { | |
656 | SOC_SINGLE_TLV("EQ1 Volume", WM8904_EQ2, 0, 24, 0, eq_tlv), | |
657 | SOC_SINGLE_TLV("EQ2 Volume", WM8904_EQ3, 0, 24, 0, eq_tlv), | |
658 | SOC_SINGLE_TLV("EQ3 Volume", WM8904_EQ4, 0, 24, 0, eq_tlv), | |
659 | SOC_SINGLE_TLV("EQ4 Volume", WM8904_EQ5, 0, 24, 0, eq_tlv), | |
660 | SOC_SINGLE_TLV("EQ5 Volume", WM8904_EQ6, 0, 24, 0, eq_tlv), | |
661 | }; | |
662 | ||
663 | static int cp_event(struct snd_soc_dapm_widget *w, | |
664 | struct snd_kcontrol *kcontrol, int event) | |
665 | { | |
666 | BUG_ON(event != SND_SOC_DAPM_POST_PMU); | |
667 | ||
668 | /* Maximum startup time */ | |
669 | udelay(500); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | static int sysclk_event(struct snd_soc_dapm_widget *w, | |
675 | struct snd_kcontrol *kcontrol, int event) | |
676 | { | |
677 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 678 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
679 | |
680 | switch (event) { | |
681 | case SND_SOC_DAPM_PRE_PMU: | |
682 | /* If we're using the FLL then we only start it when | |
683 | * required; we assume that the configuration has been | |
684 | * done previously and all we need to do is kick it | |
685 | * off. | |
686 | */ | |
687 | switch (wm8904->sysclk_src) { | |
688 | case WM8904_CLK_FLL: | |
689 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
690 | WM8904_FLL_OSC_ENA, | |
691 | WM8904_FLL_OSC_ENA); | |
692 | ||
693 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
694 | WM8904_FLL_ENA, | |
695 | WM8904_FLL_ENA); | |
696 | break; | |
697 | ||
698 | default: | |
699 | break; | |
700 | } | |
701 | break; | |
702 | ||
703 | case SND_SOC_DAPM_POST_PMD: | |
704 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
705 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
706 | break; | |
707 | } | |
708 | ||
709 | return 0; | |
710 | } | |
711 | ||
712 | static int out_pga_event(struct snd_soc_dapm_widget *w, | |
713 | struct snd_kcontrol *kcontrol, int event) | |
714 | { | |
715 | struct snd_soc_codec *codec = w->codec; | |
b2c812e2 | 716 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
717 | int reg, val; |
718 | int dcs_mask; | |
719 | int dcs_l, dcs_r; | |
720 | int dcs_l_reg, dcs_r_reg; | |
721 | int timeout; | |
e4bc6696 | 722 | int pwr_reg; |
a91eb199 MB |
723 | |
724 | /* This code is shared between HP and LINEOUT; we do all our | |
725 | * power management in stereo pairs to avoid latency issues so | |
726 | * we reuse shift to identify which rather than strcmp() the | |
727 | * name. */ | |
728 | reg = w->shift; | |
729 | ||
730 | switch (reg) { | |
731 | case WM8904_ANALOGUE_HP_0: | |
e4bc6696 | 732 | pwr_reg = WM8904_POWER_MANAGEMENT_2; |
a91eb199 MB |
733 | dcs_mask = WM8904_DCS_ENA_CHAN_0 | WM8904_DCS_ENA_CHAN_1; |
734 | dcs_r_reg = WM8904_DC_SERVO_8; | |
735 | dcs_l_reg = WM8904_DC_SERVO_9; | |
736 | dcs_l = 0; | |
737 | dcs_r = 1; | |
738 | break; | |
739 | case WM8904_ANALOGUE_LINEOUT_0: | |
e4bc6696 | 740 | pwr_reg = WM8904_POWER_MANAGEMENT_3; |
a91eb199 MB |
741 | dcs_mask = WM8904_DCS_ENA_CHAN_2 | WM8904_DCS_ENA_CHAN_3; |
742 | dcs_r_reg = WM8904_DC_SERVO_6; | |
743 | dcs_l_reg = WM8904_DC_SERVO_7; | |
744 | dcs_l = 2; | |
745 | dcs_r = 3; | |
746 | break; | |
747 | default: | |
748 | BUG(); | |
749 | return -EINVAL; | |
750 | } | |
751 | ||
752 | switch (event) { | |
e4bc6696 MB |
753 | case SND_SOC_DAPM_PRE_PMU: |
754 | /* Power on the PGAs */ | |
755 | snd_soc_update_bits(codec, pwr_reg, | |
756 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
757 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA); | |
758 | ||
a91eb199 MB |
759 | /* Power on the amplifier */ |
760 | snd_soc_update_bits(codec, reg, | |
761 | WM8904_HPL_ENA | WM8904_HPR_ENA, | |
762 | WM8904_HPL_ENA | WM8904_HPR_ENA); | |
763 | ||
e4bc6696 | 764 | |
a91eb199 MB |
765 | /* Enable the first stage */ |
766 | snd_soc_update_bits(codec, reg, | |
767 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY, | |
768 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY); | |
769 | ||
770 | /* Power up the DC servo */ | |
771 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
772 | dcs_mask, dcs_mask); | |
773 | ||
774 | /* Either calibrate the DC servo or restore cached state | |
775 | * if we have that. | |
776 | */ | |
777 | if (wm8904->dcs_state[dcs_l] || wm8904->dcs_state[dcs_r]) { | |
778 | dev_dbg(codec->dev, "Restoring DC servo state\n"); | |
779 | ||
780 | snd_soc_write(codec, dcs_l_reg, | |
781 | wm8904->dcs_state[dcs_l]); | |
782 | snd_soc_write(codec, dcs_r_reg, | |
783 | wm8904->dcs_state[dcs_r]); | |
784 | ||
785 | snd_soc_write(codec, WM8904_DC_SERVO_1, dcs_mask); | |
786 | ||
787 | timeout = 20; | |
788 | } else { | |
789 | dev_dbg(codec->dev, "Calibrating DC servo\n"); | |
790 | ||
791 | snd_soc_write(codec, WM8904_DC_SERVO_1, | |
792 | dcs_mask << WM8904_DCS_TRIG_STARTUP_0_SHIFT); | |
793 | ||
794 | timeout = 500; | |
795 | } | |
796 | ||
797 | /* Wait for DC servo to complete */ | |
798 | dcs_mask <<= WM8904_DCS_CAL_COMPLETE_SHIFT; | |
799 | do { | |
800 | val = snd_soc_read(codec, WM8904_DC_SERVO_READBACK_0); | |
801 | if ((val & dcs_mask) == dcs_mask) | |
802 | break; | |
803 | ||
804 | msleep(1); | |
805 | } while (--timeout); | |
806 | ||
807 | if ((val & dcs_mask) != dcs_mask) | |
808 | dev_warn(codec->dev, "DC servo timed out\n"); | |
809 | else | |
810 | dev_dbg(codec->dev, "DC servo ready\n"); | |
811 | ||
812 | /* Enable the output stage */ | |
813 | snd_soc_update_bits(codec, reg, | |
814 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
815 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP); | |
e4bc6696 | 816 | break; |
a91eb199 | 817 | |
e4bc6696 | 818 | case SND_SOC_DAPM_POST_PMU: |
a91eb199 MB |
819 | /* Unshort the output itself */ |
820 | snd_soc_update_bits(codec, reg, | |
821 | WM8904_HPL_RMV_SHORT | | |
822 | WM8904_HPR_RMV_SHORT, | |
823 | WM8904_HPL_RMV_SHORT | | |
824 | WM8904_HPR_RMV_SHORT); | |
825 | ||
826 | break; | |
827 | ||
828 | case SND_SOC_DAPM_PRE_PMD: | |
829 | /* Short the output */ | |
830 | snd_soc_update_bits(codec, reg, | |
831 | WM8904_HPL_RMV_SHORT | | |
832 | WM8904_HPR_RMV_SHORT, 0); | |
e4bc6696 | 833 | break; |
a91eb199 | 834 | |
e4bc6696 | 835 | case SND_SOC_DAPM_POST_PMD: |
a91eb199 MB |
836 | /* Cache the DC servo configuration; this will be |
837 | * invalidated if we change the configuration. */ | |
838 | wm8904->dcs_state[dcs_l] = snd_soc_read(codec, dcs_l_reg); | |
839 | wm8904->dcs_state[dcs_r] = snd_soc_read(codec, dcs_r_reg); | |
840 | ||
841 | snd_soc_update_bits(codec, WM8904_DC_SERVO_0, | |
842 | dcs_mask, 0); | |
843 | ||
844 | /* Disable the amplifier input and output stages */ | |
845 | snd_soc_update_bits(codec, reg, | |
846 | WM8904_HPL_ENA | WM8904_HPR_ENA | | |
847 | WM8904_HPL_ENA_DLY | WM8904_HPR_ENA_DLY | | |
848 | WM8904_HPL_ENA_OUTP | WM8904_HPR_ENA_OUTP, | |
849 | 0); | |
e4bc6696 MB |
850 | |
851 | /* PGAs too */ | |
852 | snd_soc_update_bits(codec, pwr_reg, | |
853 | WM8904_HPL_PGA_ENA | WM8904_HPR_PGA_ENA, | |
854 | 0); | |
a91eb199 MB |
855 | break; |
856 | } | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | static const char *lin_text[] = { | |
862 | "IN1L", "IN2L", "IN3L" | |
863 | }; | |
864 | ||
865 | static const struct soc_enum lin_enum = | |
866 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 2, 3, lin_text); | |
867 | ||
868 | static const struct snd_kcontrol_new lin_mux = | |
869 | SOC_DAPM_ENUM("Left Capture Mux", lin_enum); | |
870 | ||
871 | static const struct soc_enum lin_inv_enum = | |
872 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_LEFT_INPUT_1, 4, 3, lin_text); | |
873 | ||
874 | static const struct snd_kcontrol_new lin_inv_mux = | |
875 | SOC_DAPM_ENUM("Left Capture Inveting Mux", lin_inv_enum); | |
876 | ||
877 | static const char *rin_text[] = { | |
878 | "IN1R", "IN2R", "IN3R" | |
879 | }; | |
880 | ||
881 | static const struct soc_enum rin_enum = | |
882 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 2, 3, rin_text); | |
883 | ||
884 | static const struct snd_kcontrol_new rin_mux = | |
885 | SOC_DAPM_ENUM("Right Capture Mux", rin_enum); | |
886 | ||
887 | static const struct soc_enum rin_inv_enum = | |
888 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_RIGHT_INPUT_1, 4, 3, rin_text); | |
889 | ||
890 | static const struct snd_kcontrol_new rin_inv_mux = | |
891 | SOC_DAPM_ENUM("Right Capture Inveting Mux", rin_inv_enum); | |
892 | ||
893 | static const char *aif_text[] = { | |
894 | "Left", "Right" | |
895 | }; | |
896 | ||
897 | static const struct soc_enum aifoutl_enum = | |
898 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 7, 2, aif_text); | |
899 | ||
900 | static const struct snd_kcontrol_new aifoutl_mux = | |
901 | SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum); | |
902 | ||
903 | static const struct soc_enum aifoutr_enum = | |
904 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 6, 2, aif_text); | |
905 | ||
906 | static const struct snd_kcontrol_new aifoutr_mux = | |
907 | SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum); | |
908 | ||
909 | static const struct soc_enum aifinl_enum = | |
910 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 5, 2, aif_text); | |
911 | ||
912 | static const struct snd_kcontrol_new aifinl_mux = | |
913 | SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum); | |
914 | ||
915 | static const struct soc_enum aifinr_enum = | |
916 | SOC_ENUM_SINGLE(WM8904_AUDIO_INTERFACE_0, 4, 2, aif_text); | |
917 | ||
918 | static const struct snd_kcontrol_new aifinr_mux = | |
919 | SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum); | |
920 | ||
921 | static const struct snd_soc_dapm_widget wm8904_core_dapm_widgets[] = { | |
922 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8904_CLOCK_RATES_2, 2, 0, sysclk_event, | |
923 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
924 | SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8904_CLOCK_RATES_2, 1, 0, NULL, 0), | |
925 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8904_CLOCK_RATES_2, 0, 0, NULL, 0), | |
926 | }; | |
927 | ||
928 | static const struct snd_soc_dapm_widget wm8904_adc_dapm_widgets[] = { | |
929 | SND_SOC_DAPM_INPUT("IN1L"), | |
930 | SND_SOC_DAPM_INPUT("IN1R"), | |
931 | SND_SOC_DAPM_INPUT("IN2L"), | |
932 | SND_SOC_DAPM_INPUT("IN2R"), | |
933 | SND_SOC_DAPM_INPUT("IN3L"), | |
934 | SND_SOC_DAPM_INPUT("IN3R"), | |
935 | ||
dcd658c5 | 936 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8904_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0), |
a91eb199 MB |
937 | |
938 | SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lin_mux), | |
939 | SND_SOC_DAPM_MUX("Left Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
940 | &lin_inv_mux), | |
941 | SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rin_mux), | |
942 | SND_SOC_DAPM_MUX("Right Capture Inverting Mux", SND_SOC_NOPM, 0, 0, | |
943 | &rin_inv_mux), | |
944 | ||
945 | SND_SOC_DAPM_PGA("Left Capture PGA", WM8904_POWER_MANAGEMENT_0, 1, 0, | |
946 | NULL, 0), | |
947 | SND_SOC_DAPM_PGA("Right Capture PGA", WM8904_POWER_MANAGEMENT_0, 0, 0, | |
948 | NULL, 0), | |
949 | ||
950 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8904_POWER_MANAGEMENT_6, 1, 0), | |
951 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0), | |
952 | ||
953 | SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux), | |
954 | SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux), | |
955 | ||
956 | SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0), | |
957 | SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0), | |
958 | }; | |
959 | ||
960 | static const struct snd_soc_dapm_widget wm8904_dac_dapm_widgets[] = { | |
961 | SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0), | |
962 | SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0), | |
963 | ||
964 | SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux), | |
965 | SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux), | |
966 | ||
967 | SND_SOC_DAPM_DAC("DACL", NULL, WM8904_POWER_MANAGEMENT_6, 3, 0), | |
968 | SND_SOC_DAPM_DAC("DACR", NULL, WM8904_POWER_MANAGEMENT_6, 2, 0), | |
969 | ||
970 | SND_SOC_DAPM_SUPPLY("Charge pump", WM8904_CHARGE_PUMP_0, 0, 0, cp_event, | |
971 | SND_SOC_DAPM_POST_PMU), | |
972 | ||
e4bc6696 MB |
973 | SND_SOC_DAPM_PGA("HPL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
974 | SND_SOC_DAPM_PGA("HPR PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 | 975 | |
e4bc6696 MB |
976 | SND_SOC_DAPM_PGA("LINEL PGA", SND_SOC_NOPM, 1, 0, NULL, 0), |
977 | SND_SOC_DAPM_PGA("LINER PGA", SND_SOC_NOPM, 0, 0, NULL, 0), | |
a91eb199 MB |
978 | |
979 | SND_SOC_DAPM_PGA_E("Headphone Output", SND_SOC_NOPM, WM8904_ANALOGUE_HP_0, | |
980 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
981 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
982 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
983 | SND_SOC_DAPM_PGA_E("Line Output", SND_SOC_NOPM, WM8904_ANALOGUE_LINEOUT_0, |
984 | 0, NULL, 0, out_pga_event, | |
e4bc6696 MB |
985 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
986 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), | |
a91eb199 MB |
987 | |
988 | SND_SOC_DAPM_OUTPUT("HPOUTL"), | |
989 | SND_SOC_DAPM_OUTPUT("HPOUTR"), | |
990 | SND_SOC_DAPM_OUTPUT("LINEOUTL"), | |
991 | SND_SOC_DAPM_OUTPUT("LINEOUTR"), | |
992 | }; | |
993 | ||
994 | static const char *out_mux_text[] = { | |
995 | "DAC", "Bypass" | |
996 | }; | |
997 | ||
998 | static const struct soc_enum hpl_enum = | |
999 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 3, 2, out_mux_text); | |
1000 | ||
1001 | static const struct snd_kcontrol_new hpl_mux = | |
1002 | SOC_DAPM_ENUM("HPL Mux", hpl_enum); | |
1003 | ||
1004 | static const struct soc_enum hpr_enum = | |
1005 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 2, 2, out_mux_text); | |
1006 | ||
1007 | static const struct snd_kcontrol_new hpr_mux = | |
1008 | SOC_DAPM_ENUM("HPR Mux", hpr_enum); | |
1009 | ||
1010 | static const struct soc_enum linel_enum = | |
1011 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 1, 2, out_mux_text); | |
1012 | ||
1013 | static const struct snd_kcontrol_new linel_mux = | |
1014 | SOC_DAPM_ENUM("LINEL Mux", linel_enum); | |
1015 | ||
1016 | static const struct soc_enum liner_enum = | |
1017 | SOC_ENUM_SINGLE(WM8904_ANALOGUE_OUT12_ZC, 0, 2, out_mux_text); | |
1018 | ||
1019 | static const struct snd_kcontrol_new liner_mux = | |
1020 | SOC_DAPM_ENUM("LINEL Mux", liner_enum); | |
1021 | ||
1022 | static const char *sidetone_text[] = { | |
1023 | "None", "Left", "Right" | |
1024 | }; | |
1025 | ||
1026 | static const struct soc_enum dacl_sidetone_enum = | |
1027 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 2, 3, sidetone_text); | |
1028 | ||
1029 | static const struct snd_kcontrol_new dacl_sidetone_mux = | |
1030 | SOC_DAPM_ENUM("Left Sidetone Mux", dacl_sidetone_enum); | |
1031 | ||
1032 | static const struct soc_enum dacr_sidetone_enum = | |
1033 | SOC_ENUM_SINGLE(WM8904_DAC_DIGITAL_0, 0, 3, sidetone_text); | |
1034 | ||
1035 | static const struct snd_kcontrol_new dacr_sidetone_mux = | |
1036 | SOC_DAPM_ENUM("Right Sidetone Mux", dacr_sidetone_enum); | |
1037 | ||
1038 | static const struct snd_soc_dapm_widget wm8904_dapm_widgets[] = { | |
1039 | SND_SOC_DAPM_SUPPLY("Class G", WM8904_CLASS_W_0, 0, 1, NULL, 0), | |
1040 | SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1041 | SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), | |
1042 | ||
1043 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &dacl_sidetone_mux), | |
1044 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &dacr_sidetone_mux), | |
1045 | ||
1046 | SND_SOC_DAPM_MUX("HPL Mux", SND_SOC_NOPM, 0, 0, &hpl_mux), | |
1047 | SND_SOC_DAPM_MUX("HPR Mux", SND_SOC_NOPM, 0, 0, &hpr_mux), | |
1048 | SND_SOC_DAPM_MUX("LINEL Mux", SND_SOC_NOPM, 0, 0, &linel_mux), | |
1049 | SND_SOC_DAPM_MUX("LINER Mux", SND_SOC_NOPM, 0, 0, &liner_mux), | |
1050 | }; | |
1051 | ||
1052 | static const struct snd_soc_dapm_route core_intercon[] = { | |
1053 | { "CLK_DSP", NULL, "SYSCLK" }, | |
1054 | { "TOCLK", NULL, "SYSCLK" }, | |
1055 | }; | |
1056 | ||
1057 | static const struct snd_soc_dapm_route adc_intercon[] = { | |
1058 | { "Left Capture Mux", "IN1L", "IN1L" }, | |
1059 | { "Left Capture Mux", "IN2L", "IN2L" }, | |
1060 | { "Left Capture Mux", "IN3L", "IN3L" }, | |
1061 | ||
1062 | { "Left Capture Inverting Mux", "IN1L", "IN1L" }, | |
1063 | { "Left Capture Inverting Mux", "IN2L", "IN2L" }, | |
1064 | { "Left Capture Inverting Mux", "IN3L", "IN3L" }, | |
1065 | ||
1066 | { "Right Capture Mux", "IN1R", "IN1R" }, | |
1067 | { "Right Capture Mux", "IN2R", "IN2R" }, | |
1068 | { "Right Capture Mux", "IN3R", "IN3R" }, | |
1069 | ||
1070 | { "Right Capture Inverting Mux", "IN1R", "IN1R" }, | |
1071 | { "Right Capture Inverting Mux", "IN2R", "IN2R" }, | |
1072 | { "Right Capture Inverting Mux", "IN3R", "IN3R" }, | |
1073 | ||
1074 | { "Left Capture PGA", NULL, "Left Capture Mux" }, | |
1075 | { "Left Capture PGA", NULL, "Left Capture Inverting Mux" }, | |
1076 | ||
1077 | { "Right Capture PGA", NULL, "Right Capture Mux" }, | |
1078 | { "Right Capture PGA", NULL, "Right Capture Inverting Mux" }, | |
1079 | ||
1080 | { "AIFOUTL", "Left", "ADCL" }, | |
1081 | { "AIFOUTL", "Right", "ADCR" }, | |
1082 | { "AIFOUTR", "Left", "ADCL" }, | |
1083 | { "AIFOUTR", "Right", "ADCR" }, | |
1084 | ||
1085 | { "ADCL", NULL, "CLK_DSP" }, | |
1086 | { "ADCL", NULL, "Left Capture PGA" }, | |
1087 | ||
1088 | { "ADCR", NULL, "CLK_DSP" }, | |
1089 | { "ADCR", NULL, "Right Capture PGA" }, | |
1090 | }; | |
1091 | ||
1092 | static const struct snd_soc_dapm_route dac_intercon[] = { | |
1093 | { "DACL", "Right", "AIFINR" }, | |
1094 | { "DACL", "Left", "AIFINL" }, | |
1095 | { "DACL", NULL, "CLK_DSP" }, | |
1096 | ||
1097 | { "DACR", "Right", "AIFINR" }, | |
1098 | { "DACR", "Left", "AIFINL" }, | |
1099 | { "DACR", NULL, "CLK_DSP" }, | |
1100 | ||
1101 | { "Charge pump", NULL, "SYSCLK" }, | |
1102 | ||
1103 | { "Headphone Output", NULL, "HPL PGA" }, | |
1104 | { "Headphone Output", NULL, "HPR PGA" }, | |
1105 | { "Headphone Output", NULL, "Charge pump" }, | |
1106 | { "Headphone Output", NULL, "TOCLK" }, | |
1107 | ||
1108 | { "Line Output", NULL, "LINEL PGA" }, | |
1109 | { "Line Output", NULL, "LINER PGA" }, | |
1110 | { "Line Output", NULL, "Charge pump" }, | |
1111 | { "Line Output", NULL, "TOCLK" }, | |
1112 | ||
1113 | { "HPOUTL", NULL, "Headphone Output" }, | |
1114 | { "HPOUTR", NULL, "Headphone Output" }, | |
1115 | ||
1116 | { "LINEOUTL", NULL, "Line Output" }, | |
1117 | { "LINEOUTR", NULL, "Line Output" }, | |
1118 | }; | |
1119 | ||
1120 | static const struct snd_soc_dapm_route wm8904_intercon[] = { | |
1121 | { "Left Sidetone", "Left", "ADCL" }, | |
1122 | { "Left Sidetone", "Right", "ADCR" }, | |
1123 | { "DACL", NULL, "Left Sidetone" }, | |
1124 | ||
1125 | { "Right Sidetone", "Left", "ADCL" }, | |
1126 | { "Right Sidetone", "Right", "ADCR" }, | |
1127 | { "DACR", NULL, "Right Sidetone" }, | |
1128 | ||
1129 | { "Left Bypass", NULL, "Class G" }, | |
1130 | { "Left Bypass", NULL, "Left Capture PGA" }, | |
1131 | ||
1132 | { "Right Bypass", NULL, "Class G" }, | |
1133 | { "Right Bypass", NULL, "Right Capture PGA" }, | |
1134 | ||
1135 | { "HPL Mux", "DAC", "DACL" }, | |
1136 | { "HPL Mux", "Bypass", "Left Bypass" }, | |
1137 | ||
1138 | { "HPR Mux", "DAC", "DACR" }, | |
1139 | { "HPR Mux", "Bypass", "Right Bypass" }, | |
1140 | ||
1141 | { "LINEL Mux", "DAC", "DACL" }, | |
1142 | { "LINEL Mux", "Bypass", "Left Bypass" }, | |
1143 | ||
1144 | { "LINER Mux", "DAC", "DACR" }, | |
1145 | { "LINER Mux", "Bypass", "Right Bypass" }, | |
1146 | ||
1147 | { "HPL PGA", NULL, "HPL Mux" }, | |
1148 | { "HPR PGA", NULL, "HPR Mux" }, | |
1149 | ||
1150 | { "LINEL PGA", NULL, "LINEL Mux" }, | |
1151 | { "LINER PGA", NULL, "LINER Mux" }, | |
1152 | }; | |
1153 | ||
8c126474 MB |
1154 | static const struct snd_soc_dapm_route wm8912_intercon[] = { |
1155 | { "HPL PGA", NULL, "DACL" }, | |
1156 | { "HPR PGA", NULL, "DACR" }, | |
1157 | ||
1158 | { "LINEL PGA", NULL, "DACL" }, | |
1159 | { "LINER PGA", NULL, "DACR" }, | |
1160 | }; | |
1161 | ||
a91eb199 MB |
1162 | static int wm8904_add_widgets(struct snd_soc_codec *codec) |
1163 | { | |
b2c812e2 | 1164 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
ce6120cc | 1165 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
a91eb199 | 1166 | |
ce6120cc | 1167 | snd_soc_dapm_new_controls(dapm, wm8904_core_dapm_widgets, |
a91eb199 | 1168 | ARRAY_SIZE(wm8904_core_dapm_widgets)); |
ce6120cc | 1169 | snd_soc_dapm_add_routes(dapm, core_intercon, |
a91eb199 | 1170 | ARRAY_SIZE(core_intercon)); |
8c126474 MB |
1171 | |
1172 | switch (wm8904->devtype) { | |
1173 | case WM8904: | |
022658be | 1174 | snd_soc_add_codec_controls(codec, wm8904_adc_snd_controls, |
8c126474 | 1175 | ARRAY_SIZE(wm8904_adc_snd_controls)); |
022658be | 1176 | snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls, |
8c126474 | 1177 | ARRAY_SIZE(wm8904_dac_snd_controls)); |
022658be | 1178 | snd_soc_add_codec_controls(codec, wm8904_snd_controls, |
8c126474 MB |
1179 | ARRAY_SIZE(wm8904_snd_controls)); |
1180 | ||
ce6120cc | 1181 | snd_soc_dapm_new_controls(dapm, wm8904_adc_dapm_widgets, |
8c126474 | 1182 | ARRAY_SIZE(wm8904_adc_dapm_widgets)); |
ce6120cc | 1183 | snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, |
8c126474 | 1184 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); |
ce6120cc | 1185 | snd_soc_dapm_new_controls(dapm, wm8904_dapm_widgets, |
8c126474 MB |
1186 | ARRAY_SIZE(wm8904_dapm_widgets)); |
1187 | ||
ce6120cc | 1188 | snd_soc_dapm_add_routes(dapm, adc_intercon, |
8c126474 | 1189 | ARRAY_SIZE(adc_intercon)); |
ce6120cc | 1190 | snd_soc_dapm_add_routes(dapm, dac_intercon, |
8c126474 | 1191 | ARRAY_SIZE(dac_intercon)); |
ce6120cc | 1192 | snd_soc_dapm_add_routes(dapm, wm8904_intercon, |
8c126474 MB |
1193 | ARRAY_SIZE(wm8904_intercon)); |
1194 | break; | |
1195 | ||
1196 | case WM8912: | |
022658be | 1197 | snd_soc_add_codec_controls(codec, wm8904_dac_snd_controls, |
8c126474 MB |
1198 | ARRAY_SIZE(wm8904_dac_snd_controls)); |
1199 | ||
ce6120cc | 1200 | snd_soc_dapm_new_controls(dapm, wm8904_dac_dapm_widgets, |
8c126474 MB |
1201 | ARRAY_SIZE(wm8904_dac_dapm_widgets)); |
1202 | ||
ce6120cc | 1203 | snd_soc_dapm_add_routes(dapm, dac_intercon, |
8c126474 | 1204 | ARRAY_SIZE(dac_intercon)); |
ce6120cc | 1205 | snd_soc_dapm_add_routes(dapm, wm8912_intercon, |
8c126474 MB |
1206 | ARRAY_SIZE(wm8912_intercon)); |
1207 | break; | |
1208 | } | |
a91eb199 | 1209 | |
ce6120cc | 1210 | snd_soc_dapm_new_widgets(dapm); |
a91eb199 MB |
1211 | return 0; |
1212 | } | |
1213 | ||
1214 | static struct { | |
1215 | int ratio; | |
1216 | unsigned int clk_sys_rate; | |
1217 | } clk_sys_rates[] = { | |
1218 | { 64, 0 }, | |
1219 | { 128, 1 }, | |
1220 | { 192, 2 }, | |
1221 | { 256, 3 }, | |
1222 | { 384, 4 }, | |
1223 | { 512, 5 }, | |
1224 | { 786, 6 }, | |
1225 | { 1024, 7 }, | |
1226 | { 1408, 8 }, | |
1227 | { 1536, 9 }, | |
1228 | }; | |
1229 | ||
1230 | static struct { | |
1231 | int rate; | |
1232 | int sample_rate; | |
1233 | } sample_rates[] = { | |
1234 | { 8000, 0 }, | |
1235 | { 11025, 1 }, | |
1236 | { 12000, 1 }, | |
1237 | { 16000, 2 }, | |
1238 | { 22050, 3 }, | |
1239 | { 24000, 3 }, | |
1240 | { 32000, 4 }, | |
1241 | { 44100, 5 }, | |
1242 | { 48000, 5 }, | |
1243 | }; | |
1244 | ||
1245 | static struct { | |
1246 | int div; /* *10 due to .5s */ | |
1247 | int bclk_div; | |
1248 | } bclk_divs[] = { | |
1249 | { 10, 0 }, | |
1250 | { 15, 1 }, | |
1251 | { 20, 2 }, | |
1252 | { 30, 3 }, | |
1253 | { 40, 4 }, | |
1254 | { 50, 5 }, | |
1255 | { 55, 6 }, | |
1256 | { 60, 7 }, | |
1257 | { 80, 8 }, | |
1258 | { 100, 9 }, | |
1259 | { 110, 10 }, | |
1260 | { 120, 11 }, | |
1261 | { 160, 12 }, | |
1262 | { 200, 13 }, | |
1263 | { 220, 14 }, | |
1264 | { 240, 16 }, | |
1265 | { 200, 17 }, | |
1266 | { 320, 18 }, | |
1267 | { 440, 19 }, | |
1268 | { 480, 20 }, | |
1269 | }; | |
1270 | ||
1271 | ||
1272 | static int wm8904_hw_params(struct snd_pcm_substream *substream, | |
1273 | struct snd_pcm_hw_params *params, | |
1274 | struct snd_soc_dai *dai) | |
1275 | { | |
1276 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1277 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1278 | int ret, i, best, best_val, cur_val; |
1279 | unsigned int aif1 = 0; | |
1280 | unsigned int aif2 = 0; | |
1281 | unsigned int aif3 = 0; | |
1282 | unsigned int clock1 = 0; | |
1283 | unsigned int dac_digital1 = 0; | |
1284 | ||
1285 | /* What BCLK do we need? */ | |
1286 | wm8904->fs = params_rate(params); | |
1287 | if (wm8904->tdm_slots) { | |
1288 | dev_dbg(codec->dev, "Configuring for %d %d bit TDM slots\n", | |
1289 | wm8904->tdm_slots, wm8904->tdm_width); | |
1290 | wm8904->bclk = snd_soc_calc_bclk(wm8904->fs, | |
1291 | wm8904->tdm_width, 2, | |
1292 | wm8904->tdm_slots); | |
1293 | } else { | |
1294 | wm8904->bclk = snd_soc_params_to_bclk(params); | |
1295 | } | |
1296 | ||
56927eb0 MB |
1297 | switch (params_format(params)) { |
1298 | case SNDRV_PCM_FORMAT_S16_LE: | |
1299 | break; | |
1300 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1301 | aif1 |= 0x40; | |
1302 | break; | |
1303 | case SNDRV_PCM_FORMAT_S24_LE: | |
1304 | aif1 |= 0x80; | |
1305 | break; | |
1306 | case SNDRV_PCM_FORMAT_S32_LE: | |
1307 | aif1 |= 0xc0; | |
1308 | break; | |
1309 | default: | |
1310 | return -EINVAL; | |
1311 | } | |
1312 | ||
1313 | ||
a91eb199 MB |
1314 | dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); |
1315 | ||
1316 | ret = wm8904_configure_clocking(codec); | |
1317 | if (ret != 0) | |
1318 | return ret; | |
1319 | ||
1320 | /* Select nearest CLK_SYS_RATE */ | |
1321 | best = 0; | |
1322 | best_val = abs((wm8904->sysclk_rate / clk_sys_rates[0].ratio) | |
1323 | - wm8904->fs); | |
1324 | for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) { | |
1325 | cur_val = abs((wm8904->sysclk_rate / | |
ef995e3a | 1326 | clk_sys_rates[i].ratio) - wm8904->fs); |
a91eb199 MB |
1327 | if (cur_val < best_val) { |
1328 | best = i; | |
1329 | best_val = cur_val; | |
1330 | } | |
1331 | } | |
1332 | dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n", | |
1333 | clk_sys_rates[best].ratio); | |
1334 | clock1 |= (clk_sys_rates[best].clk_sys_rate | |
1335 | << WM8904_CLK_SYS_RATE_SHIFT); | |
1336 | ||
1337 | /* SAMPLE_RATE */ | |
1338 | best = 0; | |
1339 | best_val = abs(wm8904->fs - sample_rates[0].rate); | |
1340 | for (i = 1; i < ARRAY_SIZE(sample_rates); i++) { | |
1341 | /* Closest match */ | |
1342 | cur_val = abs(wm8904->fs - sample_rates[i].rate); | |
1343 | if (cur_val < best_val) { | |
1344 | best = i; | |
1345 | best_val = cur_val; | |
1346 | } | |
1347 | } | |
1348 | dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n", | |
1349 | sample_rates[best].rate); | |
1350 | clock1 |= (sample_rates[best].sample_rate | |
1351 | << WM8904_SAMPLE_RATE_SHIFT); | |
1352 | ||
1353 | /* Enable sloping stopband filter for low sample rates */ | |
1354 | if (wm8904->fs <= 24000) | |
1355 | dac_digital1 |= WM8904_DAC_SB_FILT; | |
1356 | ||
1357 | /* BCLK_DIV */ | |
1358 | best = 0; | |
1359 | best_val = INT_MAX; | |
1360 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1361 | cur_val = ((wm8904->sysclk_rate * 10) / bclk_divs[i].div) | |
1362 | - wm8904->bclk; | |
1363 | if (cur_val < 0) /* Table is sorted */ | |
1364 | break; | |
1365 | if (cur_val < best_val) { | |
1366 | best = i; | |
1367 | best_val = cur_val; | |
1368 | } | |
1369 | } | |
1370 | wm8904->bclk = (wm8904->sysclk_rate * 10) / bclk_divs[best].div; | |
1371 | dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", | |
1372 | bclk_divs[best].div, wm8904->bclk); | |
1373 | aif2 |= bclk_divs[best].bclk_div; | |
1374 | ||
1375 | /* LRCLK is a simple fraction of BCLK */ | |
1376 | dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm8904->bclk / wm8904->fs); | |
1377 | aif3 |= wm8904->bclk / wm8904->fs; | |
1378 | ||
1379 | /* Apply the settings */ | |
1380 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, | |
1381 | WM8904_DAC_SB_FILT, dac_digital1); | |
1382 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1383 | WM8904_AIF_WL_MASK, aif1); | |
1384 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_2, | |
1385 | WM8904_BCLK_DIV_MASK, aif2); | |
1386 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1387 | WM8904_LRCLK_RATE_MASK, aif3); | |
1388 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_1, | |
1389 | WM8904_SAMPLE_RATE_MASK | | |
1390 | WM8904_CLK_SYS_RATE_MASK, clock1); | |
1391 | ||
1392 | /* Update filters for the new settings */ | |
1393 | wm8904_set_retune_mobile(codec); | |
1394 | wm8904_set_deemph(codec); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
1399 | ||
1400 | static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |
1401 | unsigned int freq, int dir) | |
1402 | { | |
1403 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1404 | struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1405 | |
1406 | switch (clk_id) { | |
1407 | case WM8904_CLK_MCLK: | |
1408 | priv->sysclk_src = clk_id; | |
1409 | priv->mclk_rate = freq; | |
1410 | break; | |
1411 | ||
1412 | case WM8904_CLK_FLL: | |
1413 | priv->sysclk_src = clk_id; | |
1414 | break; | |
1415 | ||
1416 | default: | |
1417 | return -EINVAL; | |
1418 | } | |
1419 | ||
1420 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
1421 | ||
1422 | wm8904_configure_clocking(codec); | |
1423 | ||
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | static int wm8904_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
1428 | { | |
1429 | struct snd_soc_codec *codec = dai->codec; | |
1430 | unsigned int aif1 = 0; | |
1431 | unsigned int aif3 = 0; | |
1432 | ||
1433 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1434 | case SND_SOC_DAIFMT_CBS_CFS: | |
1435 | break; | |
1436 | case SND_SOC_DAIFMT_CBS_CFM: | |
1437 | aif3 |= WM8904_LRCLK_DIR; | |
1438 | break; | |
1439 | case SND_SOC_DAIFMT_CBM_CFS: | |
1440 | aif1 |= WM8904_BCLK_DIR; | |
1441 | break; | |
1442 | case SND_SOC_DAIFMT_CBM_CFM: | |
1443 | aif1 |= WM8904_BCLK_DIR; | |
1444 | aif3 |= WM8904_LRCLK_DIR; | |
1445 | break; | |
1446 | default: | |
1447 | return -EINVAL; | |
1448 | } | |
1449 | ||
1450 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1451 | case SND_SOC_DAIFMT_DSP_B: | |
1452 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1453 | case SND_SOC_DAIFMT_DSP_A: | |
1454 | aif1 |= 0x3; | |
1455 | break; | |
1456 | case SND_SOC_DAIFMT_I2S: | |
1457 | aif1 |= 0x2; | |
1458 | break; | |
1459 | case SND_SOC_DAIFMT_RIGHT_J: | |
1460 | break; | |
1461 | case SND_SOC_DAIFMT_LEFT_J: | |
1462 | aif1 |= 0x1; | |
1463 | break; | |
1464 | default: | |
1465 | return -EINVAL; | |
1466 | } | |
1467 | ||
1468 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1469 | case SND_SOC_DAIFMT_DSP_A: | |
1470 | case SND_SOC_DAIFMT_DSP_B: | |
1471 | /* frame inversion not valid for DSP modes */ | |
1472 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1473 | case SND_SOC_DAIFMT_NB_NF: | |
1474 | break; | |
1475 | case SND_SOC_DAIFMT_IB_NF: | |
1476 | aif1 |= WM8904_AIF_BCLK_INV; | |
1477 | break; | |
1478 | default: | |
1479 | return -EINVAL; | |
1480 | } | |
1481 | break; | |
1482 | ||
1483 | case SND_SOC_DAIFMT_I2S: | |
1484 | case SND_SOC_DAIFMT_RIGHT_J: | |
1485 | case SND_SOC_DAIFMT_LEFT_J: | |
1486 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1487 | case SND_SOC_DAIFMT_NB_NF: | |
1488 | break; | |
1489 | case SND_SOC_DAIFMT_IB_IF: | |
1490 | aif1 |= WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV; | |
1491 | break; | |
1492 | case SND_SOC_DAIFMT_IB_NF: | |
1493 | aif1 |= WM8904_AIF_BCLK_INV; | |
1494 | break; | |
1495 | case SND_SOC_DAIFMT_NB_IF: | |
1496 | aif1 |= WM8904_AIF_LRCLK_INV; | |
1497 | break; | |
1498 | default: | |
1499 | return -EINVAL; | |
1500 | } | |
1501 | break; | |
1502 | default: | |
1503 | return -EINVAL; | |
1504 | } | |
1505 | ||
1506 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1507 | WM8904_AIF_BCLK_INV | WM8904_AIF_LRCLK_INV | | |
1508 | WM8904_AIF_FMT_MASK | WM8904_BCLK_DIR, aif1); | |
1509 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_3, | |
1510 | WM8904_LRCLK_DIR, aif3); | |
1511 | ||
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | ||
1516 | static int wm8904_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask, | |
1517 | unsigned int rx_mask, int slots, int slot_width) | |
1518 | { | |
1519 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1520 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1521 | int aif1 = 0; |
1522 | ||
1523 | /* Don't need to validate anything if we're turning off TDM */ | |
1524 | if (slots == 0) | |
1525 | goto out; | |
1526 | ||
1527 | /* Note that we allow configurations we can't handle ourselves - | |
1528 | * for example, we can generate clocks for slots 2 and up even if | |
1529 | * we can't use those slots ourselves. | |
1530 | */ | |
1531 | aif1 |= WM8904_AIFADC_TDM | WM8904_AIFDAC_TDM; | |
1532 | ||
1533 | switch (rx_mask) { | |
1534 | case 3: | |
1535 | break; | |
1536 | case 0xc: | |
1537 | aif1 |= WM8904_AIFADC_TDM_CHAN; | |
1538 | break; | |
1539 | default: | |
1540 | return -EINVAL; | |
1541 | } | |
1542 | ||
1543 | ||
1544 | switch (tx_mask) { | |
1545 | case 3: | |
1546 | break; | |
1547 | case 0xc: | |
1548 | aif1 |= WM8904_AIFDAC_TDM_CHAN; | |
1549 | break; | |
1550 | default: | |
1551 | return -EINVAL; | |
1552 | } | |
1553 | ||
1554 | out: | |
1555 | wm8904->tdm_width = slot_width; | |
1556 | wm8904->tdm_slots = slots / 2; | |
1557 | ||
1558 | snd_soc_update_bits(codec, WM8904_AUDIO_INTERFACE_1, | |
1559 | WM8904_AIFADC_TDM | WM8904_AIFADC_TDM_CHAN | | |
1560 | WM8904_AIFDAC_TDM | WM8904_AIFDAC_TDM_CHAN, aif1); | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | struct _fll_div { | |
1566 | u16 fll_fratio; | |
1567 | u16 fll_outdiv; | |
1568 | u16 fll_clk_ref_div; | |
1569 | u16 n; | |
1570 | u16 k; | |
1571 | }; | |
1572 | ||
1573 | /* The size in bits of the FLL divide multiplied by 10 | |
1574 | * to allow rounding later */ | |
1575 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1576 | ||
1577 | static struct { | |
1578 | unsigned int min; | |
1579 | unsigned int max; | |
1580 | u16 fll_fratio; | |
1581 | int ratio; | |
1582 | } fll_fratios[] = { | |
1583 | { 0, 64000, 4, 16 }, | |
1584 | { 64000, 128000, 3, 8 }, | |
1585 | { 128000, 256000, 2, 4 }, | |
1586 | { 256000, 1000000, 1, 2 }, | |
1587 | { 1000000, 13500000, 0, 1 }, | |
1588 | }; | |
1589 | ||
1590 | static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |
1591 | unsigned int Fout) | |
1592 | { | |
1593 | u64 Kpart; | |
1594 | unsigned int K, Ndiv, Nmod, target; | |
1595 | unsigned int div; | |
1596 | int i; | |
1597 | ||
1598 | /* Fref must be <=13.5MHz */ | |
1599 | div = 1; | |
1600 | fll_div->fll_clk_ref_div = 0; | |
1601 | while ((Fref / div) > 13500000) { | |
1602 | div *= 2; | |
1603 | fll_div->fll_clk_ref_div++; | |
1604 | ||
1605 | if (div > 8) { | |
1606 | pr_err("Can't scale %dMHz input down to <=13.5MHz\n", | |
1607 | Fref); | |
1608 | return -EINVAL; | |
1609 | } | |
1610 | } | |
1611 | ||
1612 | pr_debug("Fref=%u Fout=%u\n", Fref, Fout); | |
1613 | ||
1614 | /* Apply the division for our remaining calculations */ | |
1615 | Fref /= div; | |
1616 | ||
1617 | /* Fvco should be 90-100MHz; don't check the upper bound */ | |
1618 | div = 4; | |
1619 | while (Fout * div < 90000000) { | |
1620 | div++; | |
1621 | if (div > 64) { | |
1622 | pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", | |
1623 | Fout); | |
1624 | return -EINVAL; | |
1625 | } | |
1626 | } | |
1627 | target = Fout * div; | |
1628 | fll_div->fll_outdiv = div - 1; | |
1629 | ||
1630 | pr_debug("Fvco=%dHz\n", target); | |
1631 | ||
25985edc | 1632 | /* Find an appropriate FLL_FRATIO and factor it out of the target */ |
a91eb199 MB |
1633 | for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { |
1634 | if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { | |
1635 | fll_div->fll_fratio = fll_fratios[i].fll_fratio; | |
1636 | target /= fll_fratios[i].ratio; | |
1637 | break; | |
1638 | } | |
1639 | } | |
1640 | if (i == ARRAY_SIZE(fll_fratios)) { | |
1641 | pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); | |
1642 | return -EINVAL; | |
1643 | } | |
1644 | ||
1645 | /* Now, calculate N.K */ | |
1646 | Ndiv = target / Fref; | |
1647 | ||
1648 | fll_div->n = Ndiv; | |
1649 | Nmod = target % Fref; | |
1650 | pr_debug("Nmod=%d\n", Nmod); | |
1651 | ||
1652 | /* Calculate fractional part - scale up so we can round. */ | |
1653 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1654 | ||
1655 | do_div(Kpart, Fref); | |
1656 | ||
1657 | K = Kpart & 0xFFFFFFFF; | |
1658 | ||
1659 | if ((K % 10) >= 5) | |
1660 | K += 5; | |
1661 | ||
1662 | /* Move down to proper range now rounding is done */ | |
1663 | fll_div->k = K / 10; | |
1664 | ||
1665 | pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n", | |
1666 | fll_div->n, fll_div->k, | |
1667 | fll_div->fll_fratio, fll_div->fll_outdiv, | |
1668 | fll_div->fll_clk_ref_div); | |
1669 | ||
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | static int wm8904_set_fll(struct snd_soc_dai *dai, int fll_id, int source, | |
1674 | unsigned int Fref, unsigned int Fout) | |
1675 | { | |
1676 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 1677 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1678 | struct _fll_div fll_div; |
1679 | int ret, val; | |
1680 | int clock2, fll1; | |
1681 | ||
1682 | /* Any change? */ | |
1683 | if (source == wm8904->fll_src && Fref == wm8904->fll_fref && | |
1684 | Fout == wm8904->fll_fout) | |
1685 | return 0; | |
1686 | ||
18240b67 MB |
1687 | clock2 = snd_soc_read(codec, WM8904_CLOCK_RATES_2); |
1688 | ||
a91eb199 MB |
1689 | if (Fout == 0) { |
1690 | dev_dbg(codec->dev, "FLL disabled\n"); | |
1691 | ||
1692 | wm8904->fll_fref = 0; | |
1693 | wm8904->fll_fout = 0; | |
1694 | ||
1695 | /* Gate SYSCLK to avoid glitches */ | |
1696 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
1697 | WM8904_CLK_SYS_ENA, 0); | |
1698 | ||
1699 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1700 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
1701 | ||
1702 | goto out; | |
1703 | } | |
1704 | ||
1705 | /* Validate the FLL ID */ | |
1706 | switch (source) { | |
1707 | case WM8904_FLL_MCLK: | |
1708 | case WM8904_FLL_LRCLK: | |
1709 | case WM8904_FLL_BCLK: | |
1710 | ret = fll_factors(&fll_div, Fref, Fout); | |
1711 | if (ret != 0) | |
1712 | return ret; | |
1713 | break; | |
1714 | ||
1715 | case WM8904_FLL_FREE_RUNNING: | |
1716 | dev_dbg(codec->dev, "Using free running FLL\n"); | |
1717 | /* Force 12MHz and output/4 for now */ | |
1718 | Fout = 12000000; | |
1719 | Fref = 12000000; | |
1720 | ||
1721 | memset(&fll_div, 0, sizeof(fll_div)); | |
1722 | fll_div.fll_outdiv = 3; | |
1723 | break; | |
1724 | ||
1725 | default: | |
1726 | dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id); | |
1727 | return -EINVAL; | |
1728 | } | |
1729 | ||
1730 | /* Save current state then disable the FLL and SYSCLK to avoid | |
1731 | * misclocking */ | |
a91eb199 MB |
1732 | fll1 = snd_soc_read(codec, WM8904_FLL_CONTROL_1); |
1733 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
1734 | WM8904_CLK_SYS_ENA, 0); | |
1735 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1736 | WM8904_FLL_OSC_ENA | WM8904_FLL_ENA, 0); | |
1737 | ||
1738 | /* Unlock forced oscilator control to switch it on/off */ | |
1739 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
1740 | WM8904_USER_KEY, WM8904_USER_KEY); | |
1741 | ||
1742 | if (fll_id == WM8904_FLL_FREE_RUNNING) { | |
1743 | val = WM8904_FLL_FRC_NCO; | |
1744 | } else { | |
1745 | val = 0; | |
1746 | } | |
1747 | ||
1748 | snd_soc_update_bits(codec, WM8904_FLL_NCO_TEST_1, WM8904_FLL_FRC_NCO, | |
1749 | val); | |
1750 | snd_soc_update_bits(codec, WM8904_CONTROL_INTERFACE_TEST_1, | |
1751 | WM8904_USER_KEY, 0); | |
1752 | ||
1753 | switch (fll_id) { | |
1754 | case WM8904_FLL_MCLK: | |
1755 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
1756 | WM8904_FLL_CLK_REF_SRC_MASK, 0); | |
1757 | break; | |
1758 | ||
1759 | case WM8904_FLL_LRCLK: | |
1760 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
1761 | WM8904_FLL_CLK_REF_SRC_MASK, 1); | |
1762 | break; | |
1763 | ||
1764 | case WM8904_FLL_BCLK: | |
1765 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
1766 | WM8904_FLL_CLK_REF_SRC_MASK, 2); | |
1767 | break; | |
1768 | } | |
1769 | ||
1770 | if (fll_div.k) | |
1771 | val = WM8904_FLL_FRACN_ENA; | |
1772 | else | |
1773 | val = 0; | |
1774 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1775 | WM8904_FLL_FRACN_ENA, val); | |
1776 | ||
1777 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_2, | |
1778 | WM8904_FLL_OUTDIV_MASK | WM8904_FLL_FRATIO_MASK, | |
1779 | (fll_div.fll_outdiv << WM8904_FLL_OUTDIV_SHIFT) | | |
1780 | (fll_div.fll_fratio << WM8904_FLL_FRATIO_SHIFT)); | |
1781 | ||
1782 | snd_soc_write(codec, WM8904_FLL_CONTROL_3, fll_div.k); | |
1783 | ||
1784 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_4, WM8904_FLL_N_MASK, | |
1785 | fll_div.n << WM8904_FLL_N_SHIFT); | |
1786 | ||
1787 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_5, | |
1788 | WM8904_FLL_CLK_REF_DIV_MASK, | |
1789 | fll_div.fll_clk_ref_div | |
1790 | << WM8904_FLL_CLK_REF_DIV_SHIFT); | |
1791 | ||
1792 | dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); | |
1793 | ||
1794 | wm8904->fll_fref = Fref; | |
1795 | wm8904->fll_fout = Fout; | |
1796 | wm8904->fll_src = source; | |
1797 | ||
1798 | /* Enable the FLL if it was previously active */ | |
1799 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1800 | WM8904_FLL_OSC_ENA, fll1); | |
1801 | snd_soc_update_bits(codec, WM8904_FLL_CONTROL_1, | |
1802 | WM8904_FLL_ENA, fll1); | |
1803 | ||
1804 | out: | |
1805 | /* Reenable SYSCLK if it was previously active */ | |
1806 | snd_soc_update_bits(codec, WM8904_CLOCK_RATES_2, | |
1807 | WM8904_CLK_SYS_ENA, clock2); | |
1808 | ||
1809 | return 0; | |
1810 | } | |
1811 | ||
1812 | static int wm8904_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
1813 | { | |
1814 | struct snd_soc_codec *codec = codec_dai->codec; | |
1815 | int val; | |
1816 | ||
1817 | if (mute) | |
1818 | val = WM8904_DAC_MUTE; | |
1819 | else | |
1820 | val = 0; | |
1821 | ||
1822 | snd_soc_update_bits(codec, WM8904_DAC_DIGITAL_1, WM8904_DAC_MUTE, val); | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
1827 | static int wm8904_set_bias_level(struct snd_soc_codec *codec, | |
1828 | enum snd_soc_bias_level level) | |
1829 | { | |
b2c812e2 | 1830 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
c1334218 | 1831 | int ret; |
a91eb199 MB |
1832 | |
1833 | switch (level) { | |
1834 | case SND_SOC_BIAS_ON: | |
1835 | break; | |
1836 | ||
1837 | case SND_SOC_BIAS_PREPARE: | |
1838 | /* VMID resistance 2*50k */ | |
1839 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
1840 | WM8904_VMID_RES_MASK, | |
1841 | 0x1 << WM8904_VMID_RES_SHIFT); | |
1842 | ||
1843 | /* Normal bias current */ | |
1844 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
1845 | WM8904_ISEL_MASK, 2 << WM8904_ISEL_SHIFT); | |
1846 | break; | |
1847 | ||
1848 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 1849 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
a91eb199 MB |
1850 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), |
1851 | wm8904->supplies); | |
1852 | if (ret != 0) { | |
1853 | dev_err(codec->dev, | |
1854 | "Failed to enable supplies: %d\n", | |
1855 | ret); | |
1856 | return ret; | |
1857 | } | |
1858 | ||
c1b88ee2 | 1859 | regcache_cache_only(wm8904->regmap, false); |
84d0d831 | 1860 | regcache_sync(wm8904->regmap); |
a91eb199 MB |
1861 | |
1862 | /* Enable bias */ | |
1863 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
1864 | WM8904_BIAS_ENA, WM8904_BIAS_ENA); | |
1865 | ||
1866 | /* Enable VMID, VMID buffering, 2*5k resistance */ | |
1867 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
1868 | WM8904_VMID_ENA | | |
1869 | WM8904_VMID_RES_MASK, | |
1870 | WM8904_VMID_ENA | | |
1871 | 0x3 << WM8904_VMID_RES_SHIFT); | |
1872 | ||
1873 | /* Let VMID ramp */ | |
1874 | msleep(1); | |
1875 | } | |
1876 | ||
1877 | /* Maintain VMID with 2*250k */ | |
1878 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
1879 | WM8904_VMID_RES_MASK, | |
1880 | 0x2 << WM8904_VMID_RES_SHIFT); | |
1881 | ||
1882 | /* Bias current *0.5 */ | |
1883 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
1884 | WM8904_ISEL_MASK, 0); | |
1885 | break; | |
1886 | ||
1887 | case SND_SOC_BIAS_OFF: | |
1888 | /* Turn off VMID */ | |
1889 | snd_soc_update_bits(codec, WM8904_VMID_CONTROL_0, | |
1890 | WM8904_VMID_RES_MASK | WM8904_VMID_ENA, 0); | |
1891 | ||
1892 | /* Stop bias generation */ | |
1893 | snd_soc_update_bits(codec, WM8904_BIAS_CONTROL_0, | |
1894 | WM8904_BIAS_ENA, 0); | |
1895 | ||
c1b88ee2 MB |
1896 | regcache_cache_only(wm8904->regmap, true); |
1897 | regcache_mark_dirty(wm8904->regmap); | |
c1334218 | 1898 | |
a91eb199 MB |
1899 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), |
1900 | wm8904->supplies); | |
1901 | break; | |
1902 | } | |
ce6120cc | 1903 | codec->dapm.bias_level = level; |
a91eb199 MB |
1904 | return 0; |
1905 | } | |
1906 | ||
1907 | #define WM8904_RATES SNDRV_PCM_RATE_8000_96000 | |
1908 | ||
1909 | #define WM8904_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1910 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1911 | ||
85e7652d | 1912 | static const struct snd_soc_dai_ops wm8904_dai_ops = { |
a91eb199 MB |
1913 | .set_sysclk = wm8904_set_sysclk, |
1914 | .set_fmt = wm8904_set_fmt, | |
1915 | .set_tdm_slot = wm8904_set_tdm_slot, | |
1916 | .set_pll = wm8904_set_fll, | |
1917 | .hw_params = wm8904_hw_params, | |
1918 | .digital_mute = wm8904_digital_mute, | |
1919 | }; | |
1920 | ||
f0fba2ad LG |
1921 | static struct snd_soc_dai_driver wm8904_dai = { |
1922 | .name = "wm8904-hifi", | |
a91eb199 MB |
1923 | .playback = { |
1924 | .stream_name = "Playback", | |
1925 | .channels_min = 2, | |
1926 | .channels_max = 2, | |
1927 | .rates = WM8904_RATES, | |
1928 | .formats = WM8904_FORMATS, | |
1929 | }, | |
1930 | .capture = { | |
1931 | .stream_name = "Capture", | |
1932 | .channels_min = 2, | |
1933 | .channels_max = 2, | |
1934 | .rates = WM8904_RATES, | |
1935 | .formats = WM8904_FORMATS, | |
1936 | }, | |
1937 | .ops = &wm8904_dai_ops, | |
1938 | .symmetric_rates = 1, | |
1939 | }; | |
a91eb199 | 1940 | |
f0fba2ad | 1941 | static void wm8904_handle_retune_mobile_pdata(struct snd_soc_codec *codec) |
a91eb199 | 1942 | { |
f0fba2ad | 1943 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
1944 | struct wm8904_pdata *pdata = wm8904->pdata; |
1945 | struct snd_kcontrol_new control = | |
1946 | SOC_ENUM_EXT("EQ Mode", | |
1947 | wm8904->retune_mobile_enum, | |
1948 | wm8904_get_retune_mobile_enum, | |
1949 | wm8904_put_retune_mobile_enum); | |
1950 | int ret, i, j; | |
1951 | const char **t; | |
1952 | ||
1953 | /* We need an array of texts for the enum API but the number | |
1954 | * of texts is likely to be less than the number of | |
1955 | * configurations due to the sample rate dependency of the | |
1956 | * configurations. */ | |
1957 | wm8904->num_retune_mobile_texts = 0; | |
1958 | wm8904->retune_mobile_texts = NULL; | |
1959 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
1960 | for (j = 0; j < wm8904->num_retune_mobile_texts; j++) { | |
1961 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
1962 | wm8904->retune_mobile_texts[j]) == 0) | |
1963 | break; | |
1964 | } | |
1965 | ||
1966 | if (j != wm8904->num_retune_mobile_texts) | |
1967 | continue; | |
1968 | ||
1969 | /* Expand the array... */ | |
1970 | t = krealloc(wm8904->retune_mobile_texts, | |
1971 | sizeof(char *) * | |
1972 | (wm8904->num_retune_mobile_texts + 1), | |
1973 | GFP_KERNEL); | |
1974 | if (t == NULL) | |
1975 | continue; | |
1976 | ||
1977 | /* ...store the new entry... */ | |
1978 | t[wm8904->num_retune_mobile_texts] = | |
1979 | pdata->retune_mobile_cfgs[i].name; | |
1980 | ||
1981 | /* ...and remember the new version. */ | |
1982 | wm8904->num_retune_mobile_texts++; | |
1983 | wm8904->retune_mobile_texts = t; | |
1984 | } | |
1985 | ||
1986 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
1987 | wm8904->num_retune_mobile_texts); | |
1988 | ||
1989 | wm8904->retune_mobile_enum.max = wm8904->num_retune_mobile_texts; | |
1990 | wm8904->retune_mobile_enum.texts = wm8904->retune_mobile_texts; | |
1991 | ||
022658be | 1992 | ret = snd_soc_add_codec_controls(codec, &control, 1); |
a91eb199 | 1993 | if (ret != 0) |
f0fba2ad | 1994 | dev_err(codec->dev, |
a91eb199 MB |
1995 | "Failed to add ReTune Mobile control: %d\n", ret); |
1996 | } | |
1997 | ||
f0fba2ad | 1998 | static void wm8904_handle_pdata(struct snd_soc_codec *codec) |
a91eb199 | 1999 | { |
f0fba2ad | 2000 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
a91eb199 MB |
2001 | struct wm8904_pdata *pdata = wm8904->pdata; |
2002 | int ret, i; | |
2003 | ||
2004 | if (!pdata) { | |
022658be | 2005 | snd_soc_add_codec_controls(codec, wm8904_eq_controls, |
a91eb199 MB |
2006 | ARRAY_SIZE(wm8904_eq_controls)); |
2007 | return; | |
2008 | } | |
2009 | ||
2010 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
2011 | ||
2012 | if (pdata->num_drc_cfgs) { | |
2013 | struct snd_kcontrol_new control = | |
2014 | SOC_ENUM_EXT("DRC Mode", wm8904->drc_enum, | |
2015 | wm8904_get_drc_enum, wm8904_put_drc_enum); | |
2016 | ||
2017 | /* We need an array of texts for the enum API */ | |
2018 | wm8904->drc_texts = kmalloc(sizeof(char *) | |
2019 | * pdata->num_drc_cfgs, GFP_KERNEL); | |
2020 | if (!wm8904->drc_texts) { | |
f0fba2ad | 2021 | dev_err(codec->dev, |
a91eb199 MB |
2022 | "Failed to allocate %d DRC config texts\n", |
2023 | pdata->num_drc_cfgs); | |
2024 | return; | |
2025 | } | |
2026 | ||
2027 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
2028 | wm8904->drc_texts[i] = pdata->drc_cfgs[i].name; | |
2029 | ||
2030 | wm8904->drc_enum.max = pdata->num_drc_cfgs; | |
2031 | wm8904->drc_enum.texts = wm8904->drc_texts; | |
2032 | ||
022658be | 2033 | ret = snd_soc_add_codec_controls(codec, &control, 1); |
a91eb199 | 2034 | if (ret != 0) |
f0fba2ad | 2035 | dev_err(codec->dev, |
a91eb199 MB |
2036 | "Failed to add DRC mode control: %d\n", ret); |
2037 | ||
2038 | wm8904_set_drc(codec); | |
2039 | } | |
2040 | ||
2041 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", | |
2042 | pdata->num_retune_mobile_cfgs); | |
2043 | ||
2044 | if (pdata->num_retune_mobile_cfgs) | |
f0fba2ad | 2045 | wm8904_handle_retune_mobile_pdata(codec); |
a91eb199 | 2046 | else |
022658be | 2047 | snd_soc_add_codec_controls(codec, wm8904_eq_controls, |
a91eb199 MB |
2048 | ARRAY_SIZE(wm8904_eq_controls)); |
2049 | } | |
2050 | ||
a91eb199 | 2051 | |
f0fba2ad | 2052 | static int wm8904_probe(struct snd_soc_codec *codec) |
a91eb199 | 2053 | { |
f0fba2ad | 2054 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
725e7a7b | 2055 | int ret; |
a91eb199 | 2056 | |
84d0d831 | 2057 | codec->control_data = wm8904->regmap; |
a91eb199 | 2058 | |
8c126474 MB |
2059 | switch (wm8904->devtype) { |
2060 | case WM8904: | |
2061 | break; | |
2062 | case WM8912: | |
2063 | memset(&wm8904_dai.capture, 0, sizeof(wm8904_dai.capture)); | |
2064 | break; | |
2065 | default: | |
2066 | dev_err(codec->dev, "Unknown device type %d\n", | |
2067 | wm8904->devtype); | |
f0fba2ad | 2068 | return -EINVAL; |
8c126474 MB |
2069 | } |
2070 | ||
84d0d831 | 2071 | ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP); |
a91eb199 MB |
2072 | if (ret != 0) { |
2073 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 2074 | return ret; |
a91eb199 MB |
2075 | } |
2076 | ||
f0fba2ad | 2077 | wm8904_handle_pdata(codec); |
a91eb199 | 2078 | |
f0fba2ad | 2079 | wm8904_add_widgets(codec); |
a91eb199 MB |
2080 | |
2081 | return 0; | |
a91eb199 MB |
2082 | } |
2083 | ||
f0fba2ad | 2084 | static int wm8904_remove(struct snd_soc_codec *codec) |
a91eb199 | 2085 | { |
f0fba2ad LG |
2086 | struct wm8904_priv *wm8904 = snd_soc_codec_get_drvdata(codec); |
2087 | ||
cd70978c AL |
2088 | kfree(wm8904->retune_mobile_texts); |
2089 | kfree(wm8904->drc_texts); | |
f0fba2ad LG |
2090 | |
2091 | return 0; | |
a91eb199 MB |
2092 | } |
2093 | ||
f0fba2ad LG |
2094 | static struct snd_soc_codec_driver soc_codec_dev_wm8904 = { |
2095 | .probe = wm8904_probe, | |
2096 | .remove = wm8904_remove, | |
f0fba2ad | 2097 | .set_bias_level = wm8904_set_bias_level, |
eb3032f8 | 2098 | .idle_bias_off = true, |
84d0d831 MB |
2099 | }; |
2100 | ||
2101 | static const struct regmap_config wm8904_regmap = { | |
2102 | .reg_bits = 8, | |
2103 | .val_bits = 16, | |
2104 | ||
2105 | .max_register = WM8904_MAX_REGISTER, | |
2106 | .volatile_reg = wm8904_volatile_register, | |
2107 | .readable_reg = wm8904_readable_register, | |
2108 | ||
2109 | .cache_type = REGCACHE_RBTREE, | |
2110 | .reg_defaults = wm8904_reg_defaults, | |
2111 | .num_reg_defaults = ARRAY_SIZE(wm8904_reg_defaults), | |
f0fba2ad LG |
2112 | }; |
2113 | ||
7a79e94e BP |
2114 | static int wm8904_i2c_probe(struct i2c_client *i2c, |
2115 | const struct i2c_device_id *id) | |
a91eb199 MB |
2116 | { |
2117 | struct wm8904_priv *wm8904; | |
03862cf6 MB |
2118 | unsigned int val; |
2119 | int ret, i; | |
a91eb199 | 2120 | |
93e26d4e MB |
2121 | wm8904 = devm_kzalloc(&i2c->dev, sizeof(struct wm8904_priv), |
2122 | GFP_KERNEL); | |
a91eb199 MB |
2123 | if (wm8904 == NULL) |
2124 | return -ENOMEM; | |
2125 | ||
d633edd9 | 2126 | wm8904->regmap = devm_regmap_init_i2c(i2c, &wm8904_regmap); |
84d0d831 MB |
2127 | if (IS_ERR(wm8904->regmap)) { |
2128 | ret = PTR_ERR(wm8904->regmap); | |
2129 | dev_err(&i2c->dev, "Failed to allocate register map: %d\n", | |
2130 | ret); | |
2131 | return ret; | |
2132 | } | |
2133 | ||
8c126474 | 2134 | wm8904->devtype = id->driver_data; |
a91eb199 | 2135 | i2c_set_clientdata(i2c, wm8904); |
a91eb199 MB |
2136 | wm8904->pdata = i2c->dev.platform_data; |
2137 | ||
03862cf6 MB |
2138 | for (i = 0; i < ARRAY_SIZE(wm8904->supplies); i++) |
2139 | wm8904->supplies[i].supply = wm8904_supply_names[i]; | |
2140 | ||
2141 | ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8904->supplies), | |
2142 | wm8904->supplies); | |
2143 | if (ret != 0) { | |
2144 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
2145 | return ret; | |
2146 | } | |
2147 | ||
2148 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8904->supplies), | |
2149 | wm8904->supplies); | |
2150 | if (ret != 0) { | |
2151 | dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); | |
2152 | return ret; | |
2153 | } | |
2154 | ||
2155 | ret = regmap_read(wm8904->regmap, WM8904_SW_RESET_AND_ID, &val); | |
2156 | if (ret < 0) { | |
2157 | dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret); | |
2158 | goto err_enable; | |
2159 | } | |
2160 | if (val != 0x8904) { | |
2161 | dev_err(&i2c->dev, "Device is not a WM8904, ID is %x\n", val); | |
2162 | ret = -EINVAL; | |
2163 | goto err_enable; | |
2164 | } | |
2165 | ||
2166 | ret = regmap_read(wm8904->regmap, WM8904_REVISION, &val); | |
2167 | if (ret < 0) { | |
2168 | dev_err(&i2c->dev, "Failed to read device revision: %d\n", | |
2169 | ret); | |
2170 | goto err_enable; | |
2171 | } | |
2172 | dev_info(&i2c->dev, "revision %c\n", val + 'A'); | |
2173 | ||
2174 | ret = regmap_write(wm8904->regmap, WM8904_SW_RESET_AND_ID, 0); | |
2175 | if (ret < 0) { | |
2176 | dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); | |
2177 | goto err_enable; | |
2178 | } | |
2179 | ||
725e7a7b MB |
2180 | /* Change some default settings - latch VU and enable ZC */ |
2181 | regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_LEFT, | |
2182 | WM8904_ADC_VU, WM8904_ADC_VU); | |
2183 | regmap_update_bits(wm8904->regmap, WM8904_ADC_DIGITAL_VOLUME_RIGHT, | |
2184 | WM8904_ADC_VU, WM8904_ADC_VU); | |
2185 | regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_LEFT, | |
2186 | WM8904_DAC_VU, WM8904_DAC_VU); | |
2187 | regmap_update_bits(wm8904->regmap, WM8904_DAC_DIGITAL_VOLUME_RIGHT, | |
2188 | WM8904_DAC_VU, WM8904_DAC_VU); | |
2189 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_LEFT, | |
2190 | WM8904_HPOUT_VU | WM8904_HPOUTLZC, | |
2191 | WM8904_HPOUT_VU | WM8904_HPOUTLZC); | |
2192 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT1_RIGHT, | |
2193 | WM8904_HPOUT_VU | WM8904_HPOUTRZC, | |
2194 | WM8904_HPOUT_VU | WM8904_HPOUTRZC); | |
2195 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_LEFT, | |
2196 | WM8904_LINEOUT_VU | WM8904_LINEOUTLZC, | |
2197 | WM8904_LINEOUT_VU | WM8904_LINEOUTLZC); | |
2198 | regmap_update_bits(wm8904->regmap, WM8904_ANALOGUE_OUT2_RIGHT, | |
2199 | WM8904_LINEOUT_VU | WM8904_LINEOUTRZC, | |
2200 | WM8904_LINEOUT_VU | WM8904_LINEOUTRZC); | |
2201 | regmap_update_bits(wm8904->regmap, WM8904_CLOCK_RATES_0, | |
2202 | WM8904_SR_MODE, 0); | |
2203 | ||
2204 | /* Apply configuration from the platform data. */ | |
2205 | if (wm8904->pdata) { | |
2206 | for (i = 0; i < WM8904_GPIO_REGS; i++) { | |
2207 | if (!wm8904->pdata->gpio_cfg[i]) | |
2208 | continue; | |
2209 | ||
2210 | regmap_update_bits(wm8904->regmap, | |
2211 | WM8904_GPIO_CONTROL_1 + i, | |
2212 | 0xffff, | |
2213 | wm8904->pdata->gpio_cfg[i]); | |
2214 | } | |
2215 | ||
2216 | /* Zero is the default value for these anyway */ | |
2217 | for (i = 0; i < WM8904_MIC_REGS; i++) | |
2218 | regmap_update_bits(wm8904->regmap, | |
2219 | WM8904_MIC_BIAS_CONTROL_0 + i, | |
2220 | 0xffff, | |
2221 | wm8904->pdata->mic_cfg[i]); | |
2222 | } | |
2223 | ||
2224 | /* Set Class W by default - this will be managed by the Class | |
2225 | * G widget at runtime where bypass paths are available. | |
2226 | */ | |
2227 | regmap_update_bits(wm8904->regmap, WM8904_CLASS_W_0, | |
2228 | WM8904_CP_DYN_PWR, WM8904_CP_DYN_PWR); | |
2229 | ||
2230 | /* Use normal bias source */ | |
2231 | regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, | |
2232 | WM8904_POBCTRL, 0); | |
2233 | ||
03862cf6 MB |
2234 | /* Can leave the device powered off until we need it */ |
2235 | regcache_cache_only(wm8904->regmap, true); | |
2236 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
2237 | ||
f0fba2ad LG |
2238 | ret = snd_soc_register_codec(&i2c->dev, |
2239 | &soc_codec_dev_wm8904, &wm8904_dai, 1); | |
84d0d831 | 2240 | if (ret != 0) |
03862cf6 | 2241 | return ret; |
84d0d831 MB |
2242 | |
2243 | return 0; | |
93e26d4e | 2244 | |
03862cf6 MB |
2245 | err_enable: |
2246 | regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); | |
f0fba2ad | 2247 | return ret; |
a91eb199 MB |
2248 | } |
2249 | ||
7a79e94e | 2250 | static int wm8904_i2c_remove(struct i2c_client *client) |
a91eb199 | 2251 | { |
f0fba2ad | 2252 | snd_soc_unregister_codec(&client->dev); |
a91eb199 MB |
2253 | return 0; |
2254 | } | |
2255 | ||
2256 | static const struct i2c_device_id wm8904_i2c_id[] = { | |
8c126474 MB |
2257 | { "wm8904", WM8904 }, |
2258 | { "wm8912", WM8912 }, | |
df1553c8 | 2259 | { "wm8918", WM8904 }, /* Actually a subset, updates to follow */ |
a91eb199 MB |
2260 | { } |
2261 | }; | |
2262 | MODULE_DEVICE_TABLE(i2c, wm8904_i2c_id); | |
2263 | ||
2264 | static struct i2c_driver wm8904_i2c_driver = { | |
2265 | .driver = { | |
091edccf | 2266 | .name = "wm8904", |
a91eb199 MB |
2267 | .owner = THIS_MODULE, |
2268 | }, | |
2269 | .probe = wm8904_i2c_probe, | |
7a79e94e | 2270 | .remove = wm8904_i2c_remove, |
a91eb199 MB |
2271 | .id_table = wm8904_i2c_id, |
2272 | }; | |
a91eb199 | 2273 | |
8cb28fd6 | 2274 | module_i2c_driver(wm8904_i2c_driver); |
a91eb199 MB |
2275 | |
2276 | MODULE_DESCRIPTION("ASoC WM8904 driver"); | |
2277 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
2278 | MODULE_LICENSE("GPL"); |