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a91eb199 MB |
1 | /* |
2 | * wm8904.h -- WM8904 ASoC driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics, plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef _WM8904_H | |
14 | #define _WM8904_H | |
15 | ||
16 | #define WM8904_CLK_MCLK 1 | |
17 | #define WM8904_CLK_FLL 2 | |
18 | ||
19 | #define WM8904_FLL_MCLK 1 | |
20 | #define WM8904_FLL_BCLK 2 | |
21 | #define WM8904_FLL_LRCLK 3 | |
22 | #define WM8904_FLL_FREE_RUNNING 4 | |
23 | ||
a91eb199 MB |
24 | /* |
25 | * Register values. | |
26 | */ | |
27 | #define WM8904_SW_RESET_AND_ID 0x00 | |
28 | #define WM8904_REVISION 0x01 | |
29 | #define WM8904_BIAS_CONTROL_0 0x04 | |
30 | #define WM8904_VMID_CONTROL_0 0x05 | |
31 | #define WM8904_MIC_BIAS_CONTROL_0 0x06 | |
32 | #define WM8904_MIC_BIAS_CONTROL_1 0x07 | |
33 | #define WM8904_ANALOGUE_DAC_0 0x08 | |
34 | #define WM8904_MIC_FILTER_CONTROL 0x09 | |
35 | #define WM8904_ANALOGUE_ADC_0 0x0A | |
36 | #define WM8904_POWER_MANAGEMENT_0 0x0C | |
37 | #define WM8904_POWER_MANAGEMENT_2 0x0E | |
38 | #define WM8904_POWER_MANAGEMENT_3 0x0F | |
39 | #define WM8904_POWER_MANAGEMENT_6 0x12 | |
40 | #define WM8904_CLOCK_RATES_0 0x14 | |
41 | #define WM8904_CLOCK_RATES_1 0x15 | |
42 | #define WM8904_CLOCK_RATES_2 0x16 | |
43 | #define WM8904_AUDIO_INTERFACE_0 0x18 | |
44 | #define WM8904_AUDIO_INTERFACE_1 0x19 | |
45 | #define WM8904_AUDIO_INTERFACE_2 0x1A | |
46 | #define WM8904_AUDIO_INTERFACE_3 0x1B | |
47 | #define WM8904_DAC_DIGITAL_VOLUME_LEFT 0x1E | |
48 | #define WM8904_DAC_DIGITAL_VOLUME_RIGHT 0x1F | |
49 | #define WM8904_DAC_DIGITAL_0 0x20 | |
50 | #define WM8904_DAC_DIGITAL_1 0x21 | |
51 | #define WM8904_ADC_DIGITAL_VOLUME_LEFT 0x24 | |
52 | #define WM8904_ADC_DIGITAL_VOLUME_RIGHT 0x25 | |
53 | #define WM8904_ADC_DIGITAL_0 0x26 | |
54 | #define WM8904_DIGITAL_MICROPHONE_0 0x27 | |
55 | #define WM8904_DRC_0 0x28 | |
56 | #define WM8904_DRC_1 0x29 | |
57 | #define WM8904_DRC_2 0x2A | |
58 | #define WM8904_DRC_3 0x2B | |
59 | #define WM8904_ANALOGUE_LEFT_INPUT_0 0x2C | |
60 | #define WM8904_ANALOGUE_RIGHT_INPUT_0 0x2D | |
61 | #define WM8904_ANALOGUE_LEFT_INPUT_1 0x2E | |
62 | #define WM8904_ANALOGUE_RIGHT_INPUT_1 0x2F | |
63 | #define WM8904_ANALOGUE_OUT1_LEFT 0x39 | |
64 | #define WM8904_ANALOGUE_OUT1_RIGHT 0x3A | |
65 | #define WM8904_ANALOGUE_OUT2_LEFT 0x3B | |
66 | #define WM8904_ANALOGUE_OUT2_RIGHT 0x3C | |
67 | #define WM8904_ANALOGUE_OUT12_ZC 0x3D | |
68 | #define WM8904_DC_SERVO_0 0x43 | |
69 | #define WM8904_DC_SERVO_1 0x44 | |
70 | #define WM8904_DC_SERVO_2 0x45 | |
71 | #define WM8904_DC_SERVO_4 0x47 | |
72 | #define WM8904_DC_SERVO_5 0x48 | |
73 | #define WM8904_DC_SERVO_6 0x49 | |
74 | #define WM8904_DC_SERVO_7 0x4A | |
75 | #define WM8904_DC_SERVO_8 0x4B | |
76 | #define WM8904_DC_SERVO_9 0x4C | |
77 | #define WM8904_DC_SERVO_READBACK_0 0x4D | |
78 | #define WM8904_ANALOGUE_HP_0 0x5A | |
79 | #define WM8904_ANALOGUE_LINEOUT_0 0x5E | |
80 | #define WM8904_CHARGE_PUMP_0 0x62 | |
81 | #define WM8904_CLASS_W_0 0x68 | |
82 | #define WM8904_WRITE_SEQUENCER_0 0x6C | |
83 | #define WM8904_WRITE_SEQUENCER_1 0x6D | |
84 | #define WM8904_WRITE_SEQUENCER_2 0x6E | |
85 | #define WM8904_WRITE_SEQUENCER_3 0x6F | |
86 | #define WM8904_WRITE_SEQUENCER_4 0x70 | |
87 | #define WM8904_FLL_CONTROL_1 0x74 | |
88 | #define WM8904_FLL_CONTROL_2 0x75 | |
89 | #define WM8904_FLL_CONTROL_3 0x76 | |
90 | #define WM8904_FLL_CONTROL_4 0x77 | |
91 | #define WM8904_FLL_CONTROL_5 0x78 | |
92 | #define WM8904_GPIO_CONTROL_1 0x79 | |
93 | #define WM8904_GPIO_CONTROL_2 0x7A | |
94 | #define WM8904_GPIO_CONTROL_3 0x7B | |
95 | #define WM8904_GPIO_CONTROL_4 0x7C | |
96 | #define WM8904_DIGITAL_PULLS 0x7E | |
97 | #define WM8904_INTERRUPT_STATUS 0x7F | |
98 | #define WM8904_INTERRUPT_STATUS_MASK 0x80 | |
99 | #define WM8904_INTERRUPT_POLARITY 0x81 | |
100 | #define WM8904_INTERRUPT_DEBOUNCE 0x82 | |
101 | #define WM8904_EQ1 0x86 | |
102 | #define WM8904_EQ2 0x87 | |
103 | #define WM8904_EQ3 0x88 | |
104 | #define WM8904_EQ4 0x89 | |
105 | #define WM8904_EQ5 0x8A | |
106 | #define WM8904_EQ6 0x8B | |
107 | #define WM8904_EQ7 0x8C | |
108 | #define WM8904_EQ8 0x8D | |
109 | #define WM8904_EQ9 0x8E | |
110 | #define WM8904_EQ10 0x8F | |
111 | #define WM8904_EQ11 0x90 | |
112 | #define WM8904_EQ12 0x91 | |
113 | #define WM8904_EQ13 0x92 | |
114 | #define WM8904_EQ14 0x93 | |
115 | #define WM8904_EQ15 0x94 | |
116 | #define WM8904_EQ16 0x95 | |
117 | #define WM8904_EQ17 0x96 | |
118 | #define WM8904_EQ18 0x97 | |
119 | #define WM8904_EQ19 0x98 | |
120 | #define WM8904_EQ20 0x99 | |
121 | #define WM8904_EQ21 0x9A | |
122 | #define WM8904_EQ22 0x9B | |
123 | #define WM8904_EQ23 0x9C | |
124 | #define WM8904_EQ24 0x9D | |
125 | #define WM8904_CONTROL_INTERFACE_TEST_1 0xA1 | |
9b85fc90 | 126 | #define WM8904_ADC_TEST_0 0xC6 |
a91eb199 MB |
127 | #define WM8904_ANALOGUE_OUTPUT_BIAS_0 0xCC |
128 | #define WM8904_FLL_NCO_TEST_0 0xF7 | |
129 | #define WM8904_FLL_NCO_TEST_1 0xF8 | |
130 | ||
131 | #define WM8904_REGISTER_COUNT 101 | |
132 | #define WM8904_MAX_REGISTER 0xF8 | |
133 | ||
134 | /* | |
135 | * Field Definitions. | |
136 | */ | |
137 | ||
138 | /* | |
139 | * R0 (0x00) - SW Reset and ID | |
140 | */ | |
141 | #define WM8904_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ | |
142 | #define WM8904_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ | |
143 | #define WM8904_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ | |
144 | ||
145 | /* | |
146 | * R1 (0x01) - Revision | |
147 | */ | |
148 | #define WM8904_REVISION_MASK 0x000F /* REVISION - [3:0] */ | |
149 | #define WM8904_REVISION_SHIFT 0 /* REVISION - [3:0] */ | |
150 | #define WM8904_REVISION_WIDTH 16 /* REVISION - [3:0] */ | |
151 | ||
152 | /* | |
153 | * R4 (0x04) - Bias Control 0 | |
154 | */ | |
155 | #define WM8904_POBCTRL 0x0010 /* POBCTRL */ | |
156 | #define WM8904_POBCTRL_MASK 0x0010 /* POBCTRL */ | |
157 | #define WM8904_POBCTRL_SHIFT 4 /* POBCTRL */ | |
158 | #define WM8904_POBCTRL_WIDTH 1 /* POBCTRL */ | |
159 | #define WM8904_ISEL_MASK 0x000C /* ISEL - [3:2] */ | |
160 | #define WM8904_ISEL_SHIFT 2 /* ISEL - [3:2] */ | |
161 | #define WM8904_ISEL_WIDTH 2 /* ISEL - [3:2] */ | |
162 | #define WM8904_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */ | |
163 | #define WM8904_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */ | |
164 | #define WM8904_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */ | |
165 | #define WM8904_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ | |
166 | #define WM8904_BIAS_ENA 0x0001 /* BIAS_ENA */ | |
167 | #define WM8904_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ | |
168 | #define WM8904_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ | |
169 | #define WM8904_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ | |
170 | ||
171 | /* | |
172 | * R5 (0x05) - VMID Control 0 | |
173 | */ | |
174 | #define WM8904_VMID_BUF_ENA 0x0040 /* VMID_BUF_ENA */ | |
175 | #define WM8904_VMID_BUF_ENA_MASK 0x0040 /* VMID_BUF_ENA */ | |
176 | #define WM8904_VMID_BUF_ENA_SHIFT 6 /* VMID_BUF_ENA */ | |
177 | #define WM8904_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ | |
178 | #define WM8904_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ | |
179 | #define WM8904_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ | |
180 | #define WM8904_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ | |
181 | #define WM8904_VMID_ENA 0x0001 /* VMID_ENA */ | |
182 | #define WM8904_VMID_ENA_MASK 0x0001 /* VMID_ENA */ | |
183 | #define WM8904_VMID_ENA_SHIFT 0 /* VMID_ENA */ | |
184 | #define WM8904_VMID_ENA_WIDTH 1 /* VMID_ENA */ | |
185 | ||
a91eb199 MB |
186 | /* |
187 | * R8 (0x08) - Analogue DAC 0 | |
188 | */ | |
189 | #define WM8904_DAC_BIAS_SEL_MASK 0x0018 /* DAC_BIAS_SEL - [4:3] */ | |
190 | #define WM8904_DAC_BIAS_SEL_SHIFT 3 /* DAC_BIAS_SEL - [4:3] */ | |
191 | #define WM8904_DAC_BIAS_SEL_WIDTH 2 /* DAC_BIAS_SEL - [4:3] */ | |
192 | #define WM8904_DAC_VMID_BIAS_SEL_MASK 0x0006 /* DAC_VMID_BIAS_SEL - [2:1] */ | |
193 | #define WM8904_DAC_VMID_BIAS_SEL_SHIFT 1 /* DAC_VMID_BIAS_SEL - [2:1] */ | |
194 | #define WM8904_DAC_VMID_BIAS_SEL_WIDTH 2 /* DAC_VMID_BIAS_SEL - [2:1] */ | |
195 | ||
196 | /* | |
197 | * R9 (0x09) - mic Filter Control | |
198 | */ | |
199 | #define WM8904_MIC_DET_SET_THRESHOLD_MASK 0xF000 /* MIC_DET_SET_THRESHOLD - [15:12] */ | |
200 | #define WM8904_MIC_DET_SET_THRESHOLD_SHIFT 12 /* MIC_DET_SET_THRESHOLD - [15:12] */ | |
201 | #define WM8904_MIC_DET_SET_THRESHOLD_WIDTH 4 /* MIC_DET_SET_THRESHOLD - [15:12] */ | |
202 | #define WM8904_MIC_DET_RESET_THRESHOLD_MASK 0x0F00 /* MIC_DET_RESET_THRESHOLD - [11:8] */ | |
203 | #define WM8904_MIC_DET_RESET_THRESHOLD_SHIFT 8 /* MIC_DET_RESET_THRESHOLD - [11:8] */ | |
204 | #define WM8904_MIC_DET_RESET_THRESHOLD_WIDTH 4 /* MIC_DET_RESET_THRESHOLD - [11:8] */ | |
205 | #define WM8904_MIC_SHORT_SET_THRESHOLD_MASK 0x00F0 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ | |
206 | #define WM8904_MIC_SHORT_SET_THRESHOLD_SHIFT 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ | |
207 | #define WM8904_MIC_SHORT_SET_THRESHOLD_WIDTH 4 /* MIC_SHORT_SET_THRESHOLD - [7:4] */ | |
208 | #define WM8904_MIC_SHORT_RESET_THRESHOLD_MASK 0x000F /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ | |
209 | #define WM8904_MIC_SHORT_RESET_THRESHOLD_SHIFT 0 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ | |
210 | #define WM8904_MIC_SHORT_RESET_THRESHOLD_WIDTH 4 /* MIC_SHORT_RESET_THRESHOLD - [3:0] */ | |
211 | ||
212 | /* | |
213 | * R10 (0x0A) - Analogue ADC 0 | |
214 | */ | |
215 | #define WM8904_ADC_OSR128 0x0001 /* ADC_OSR128 */ | |
216 | #define WM8904_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */ | |
217 | #define WM8904_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */ | |
218 | #define WM8904_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ | |
219 | ||
220 | /* | |
221 | * R12 (0x0C) - Power Management 0 | |
222 | */ | |
223 | #define WM8904_INL_ENA 0x0002 /* INL_ENA */ | |
224 | #define WM8904_INL_ENA_MASK 0x0002 /* INL_ENA */ | |
225 | #define WM8904_INL_ENA_SHIFT 1 /* INL_ENA */ | |
226 | #define WM8904_INL_ENA_WIDTH 1 /* INL_ENA */ | |
227 | #define WM8904_INR_ENA 0x0001 /* INR_ENA */ | |
228 | #define WM8904_INR_ENA_MASK 0x0001 /* INR_ENA */ | |
229 | #define WM8904_INR_ENA_SHIFT 0 /* INR_ENA */ | |
230 | #define WM8904_INR_ENA_WIDTH 1 /* INR_ENA */ | |
231 | ||
232 | /* | |
233 | * R14 (0x0E) - Power Management 2 | |
234 | */ | |
235 | #define WM8904_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */ | |
236 | #define WM8904_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */ | |
237 | #define WM8904_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */ | |
238 | #define WM8904_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */ | |
239 | #define WM8904_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */ | |
240 | #define WM8904_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */ | |
241 | #define WM8904_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */ | |
242 | #define WM8904_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */ | |
243 | ||
244 | /* | |
245 | * R15 (0x0F) - Power Management 3 | |
246 | */ | |
247 | #define WM8904_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */ | |
248 | #define WM8904_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */ | |
249 | #define WM8904_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */ | |
250 | #define WM8904_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */ | |
251 | #define WM8904_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */ | |
252 | #define WM8904_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */ | |
253 | #define WM8904_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */ | |
254 | #define WM8904_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */ | |
255 | ||
256 | /* | |
257 | * R18 (0x12) - Power Management 6 | |
258 | */ | |
259 | #define WM8904_DACL_ENA 0x0008 /* DACL_ENA */ | |
260 | #define WM8904_DACL_ENA_MASK 0x0008 /* DACL_ENA */ | |
261 | #define WM8904_DACL_ENA_SHIFT 3 /* DACL_ENA */ | |
262 | #define WM8904_DACL_ENA_WIDTH 1 /* DACL_ENA */ | |
263 | #define WM8904_DACR_ENA 0x0004 /* DACR_ENA */ | |
264 | #define WM8904_DACR_ENA_MASK 0x0004 /* DACR_ENA */ | |
265 | #define WM8904_DACR_ENA_SHIFT 2 /* DACR_ENA */ | |
266 | #define WM8904_DACR_ENA_WIDTH 1 /* DACR_ENA */ | |
267 | #define WM8904_ADCL_ENA 0x0002 /* ADCL_ENA */ | |
268 | #define WM8904_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ | |
269 | #define WM8904_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ | |
270 | #define WM8904_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ | |
271 | #define WM8904_ADCR_ENA 0x0001 /* ADCR_ENA */ | |
272 | #define WM8904_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ | |
273 | #define WM8904_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ | |
274 | #define WM8904_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ | |
275 | ||
276 | /* | |
277 | * R20 (0x14) - Clock Rates 0 | |
278 | */ | |
279 | #define WM8904_TOCLK_RATE_DIV16 0x4000 /* TOCLK_RATE_DIV16 */ | |
280 | #define WM8904_TOCLK_RATE_DIV16_MASK 0x4000 /* TOCLK_RATE_DIV16 */ | |
281 | #define WM8904_TOCLK_RATE_DIV16_SHIFT 14 /* TOCLK_RATE_DIV16 */ | |
282 | #define WM8904_TOCLK_RATE_DIV16_WIDTH 1 /* TOCLK_RATE_DIV16 */ | |
283 | #define WM8904_TOCLK_RATE_X4 0x2000 /* TOCLK_RATE_X4 */ | |
284 | #define WM8904_TOCLK_RATE_X4_MASK 0x2000 /* TOCLK_RATE_X4 */ | |
285 | #define WM8904_TOCLK_RATE_X4_SHIFT 13 /* TOCLK_RATE_X4 */ | |
286 | #define WM8904_TOCLK_RATE_X4_WIDTH 1 /* TOCLK_RATE_X4 */ | |
287 | #define WM8904_SR_MODE 0x1000 /* SR_MODE */ | |
288 | #define WM8904_SR_MODE_MASK 0x1000 /* SR_MODE */ | |
289 | #define WM8904_SR_MODE_SHIFT 12 /* SR_MODE */ | |
290 | #define WM8904_SR_MODE_WIDTH 1 /* SR_MODE */ | |
291 | #define WM8904_MCLK_DIV 0x0001 /* MCLK_DIV */ | |
292 | #define WM8904_MCLK_DIV_MASK 0x0001 /* MCLK_DIV */ | |
293 | #define WM8904_MCLK_DIV_SHIFT 0 /* MCLK_DIV */ | |
294 | #define WM8904_MCLK_DIV_WIDTH 1 /* MCLK_DIV */ | |
295 | ||
296 | /* | |
297 | * R21 (0x15) - Clock Rates 1 | |
298 | */ | |
299 | #define WM8904_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */ | |
300 | #define WM8904_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */ | |
301 | #define WM8904_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */ | |
302 | #define WM8904_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ | |
303 | #define WM8904_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ | |
304 | #define WM8904_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ | |
305 | ||
306 | /* | |
307 | * R22 (0x16) - Clock Rates 2 | |
308 | */ | |
309 | #define WM8904_MCLK_INV 0x8000 /* MCLK_INV */ | |
310 | #define WM8904_MCLK_INV_MASK 0x8000 /* MCLK_INV */ | |
311 | #define WM8904_MCLK_INV_SHIFT 15 /* MCLK_INV */ | |
312 | #define WM8904_MCLK_INV_WIDTH 1 /* MCLK_INV */ | |
313 | #define WM8904_SYSCLK_SRC 0x4000 /* SYSCLK_SRC */ | |
314 | #define WM8904_SYSCLK_SRC_MASK 0x4000 /* SYSCLK_SRC */ | |
315 | #define WM8904_SYSCLK_SRC_SHIFT 14 /* SYSCLK_SRC */ | |
316 | #define WM8904_SYSCLK_SRC_WIDTH 1 /* SYSCLK_SRC */ | |
317 | #define WM8904_TOCLK_RATE 0x1000 /* TOCLK_RATE */ | |
318 | #define WM8904_TOCLK_RATE_MASK 0x1000 /* TOCLK_RATE */ | |
319 | #define WM8904_TOCLK_RATE_SHIFT 12 /* TOCLK_RATE */ | |
320 | #define WM8904_TOCLK_RATE_WIDTH 1 /* TOCLK_RATE */ | |
321 | #define WM8904_OPCLK_ENA 0x0008 /* OPCLK_ENA */ | |
322 | #define WM8904_OPCLK_ENA_MASK 0x0008 /* OPCLK_ENA */ | |
323 | #define WM8904_OPCLK_ENA_SHIFT 3 /* OPCLK_ENA */ | |
324 | #define WM8904_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */ | |
325 | #define WM8904_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */ | |
326 | #define WM8904_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */ | |
327 | #define WM8904_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */ | |
328 | #define WM8904_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ | |
329 | #define WM8904_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ | |
330 | #define WM8904_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ | |
331 | #define WM8904_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ | |
332 | #define WM8904_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ | |
333 | #define WM8904_TOCLK_ENA 0x0001 /* TOCLK_ENA */ | |
334 | #define WM8904_TOCLK_ENA_MASK 0x0001 /* TOCLK_ENA */ | |
335 | #define WM8904_TOCLK_ENA_SHIFT 0 /* TOCLK_ENA */ | |
336 | #define WM8904_TOCLK_ENA_WIDTH 1 /* TOCLK_ENA */ | |
337 | ||
338 | /* | |
339 | * R24 (0x18) - Audio Interface 0 | |
340 | */ | |
341 | #define WM8904_DACL_DATINV 0x1000 /* DACL_DATINV */ | |
342 | #define WM8904_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */ | |
343 | #define WM8904_DACL_DATINV_SHIFT 12 /* DACL_DATINV */ | |
344 | #define WM8904_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ | |
345 | #define WM8904_DACR_DATINV 0x0800 /* DACR_DATINV */ | |
346 | #define WM8904_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */ | |
347 | #define WM8904_DACR_DATINV_SHIFT 11 /* DACR_DATINV */ | |
348 | #define WM8904_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ | |
349 | #define WM8904_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */ | |
350 | #define WM8904_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */ | |
351 | #define WM8904_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */ | |
352 | #define WM8904_LOOPBACK 0x0100 /* LOOPBACK */ | |
353 | #define WM8904_LOOPBACK_MASK 0x0100 /* LOOPBACK */ | |
354 | #define WM8904_LOOPBACK_SHIFT 8 /* LOOPBACK */ | |
355 | #define WM8904_LOOPBACK_WIDTH 1 /* LOOPBACK */ | |
356 | #define WM8904_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */ | |
357 | #define WM8904_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */ | |
358 | #define WM8904_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */ | |
359 | #define WM8904_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ | |
360 | #define WM8904_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */ | |
361 | #define WM8904_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */ | |
362 | #define WM8904_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */ | |
363 | #define WM8904_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ | |
364 | #define WM8904_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */ | |
365 | #define WM8904_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */ | |
366 | #define WM8904_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */ | |
367 | #define WM8904_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */ | |
368 | #define WM8904_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */ | |
369 | #define WM8904_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */ | |
370 | #define WM8904_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */ | |
371 | #define WM8904_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */ | |
372 | #define WM8904_ADC_COMP 0x0008 /* ADC_COMP */ | |
373 | #define WM8904_ADC_COMP_MASK 0x0008 /* ADC_COMP */ | |
374 | #define WM8904_ADC_COMP_SHIFT 3 /* ADC_COMP */ | |
375 | #define WM8904_ADC_COMP_WIDTH 1 /* ADC_COMP */ | |
376 | #define WM8904_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */ | |
377 | #define WM8904_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */ | |
378 | #define WM8904_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */ | |
379 | #define WM8904_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ | |
380 | #define WM8904_DAC_COMP 0x0002 /* DAC_COMP */ | |
381 | #define WM8904_DAC_COMP_MASK 0x0002 /* DAC_COMP */ | |
382 | #define WM8904_DAC_COMP_SHIFT 1 /* DAC_COMP */ | |
383 | #define WM8904_DAC_COMP_WIDTH 1 /* DAC_COMP */ | |
384 | #define WM8904_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ | |
385 | #define WM8904_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ | |
386 | #define WM8904_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ | |
387 | #define WM8904_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ | |
388 | ||
389 | /* | |
390 | * R25 (0x19) - Audio Interface 1 | |
391 | */ | |
392 | #define WM8904_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ | |
393 | #define WM8904_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ | |
394 | #define WM8904_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ | |
395 | #define WM8904_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ | |
396 | #define WM8904_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ | |
397 | #define WM8904_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ | |
398 | #define WM8904_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ | |
399 | #define WM8904_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ | |
400 | #define WM8904_AIFADC_TDM 0x0800 /* AIFADC_TDM */ | |
401 | #define WM8904_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */ | |
402 | #define WM8904_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */ | |
403 | #define WM8904_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ | |
404 | #define WM8904_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */ | |
405 | #define WM8904_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */ | |
406 | #define WM8904_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */ | |
407 | #define WM8904_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ | |
408 | #define WM8904_AIF_TRIS 0x0100 /* AIF_TRIS */ | |
409 | #define WM8904_AIF_TRIS_MASK 0x0100 /* AIF_TRIS */ | |
410 | #define WM8904_AIF_TRIS_SHIFT 8 /* AIF_TRIS */ | |
411 | #define WM8904_AIF_TRIS_WIDTH 1 /* AIF_TRIS */ | |
412 | #define WM8904_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ | |
413 | #define WM8904_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ | |
414 | #define WM8904_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ | |
415 | #define WM8904_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ | |
416 | #define WM8904_BCLK_DIR 0x0040 /* BCLK_DIR */ | |
417 | #define WM8904_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ | |
418 | #define WM8904_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ | |
419 | #define WM8904_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ | |
420 | #define WM8904_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ | |
421 | #define WM8904_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ | |
422 | #define WM8904_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ | |
423 | #define WM8904_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ | |
424 | #define WM8904_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ | |
425 | #define WM8904_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ | |
426 | #define WM8904_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ | |
427 | #define WM8904_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ | |
428 | #define WM8904_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ | |
429 | #define WM8904_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ | |
430 | ||
431 | /* | |
432 | * R26 (0x1A) - Audio Interface 2 | |
433 | */ | |
434 | #define WM8904_OPCLK_DIV_MASK 0x0F00 /* OPCLK_DIV - [11:8] */ | |
435 | #define WM8904_OPCLK_DIV_SHIFT 8 /* OPCLK_DIV - [11:8] */ | |
436 | #define WM8904_OPCLK_DIV_WIDTH 4 /* OPCLK_DIV - [11:8] */ | |
437 | #define WM8904_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ | |
438 | #define WM8904_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ | |
439 | #define WM8904_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ | |
440 | ||
441 | /* | |
442 | * R27 (0x1B) - Audio Interface 3 | |
443 | */ | |
444 | #define WM8904_LRCLK_DIR 0x0800 /* LRCLK_DIR */ | |
445 | #define WM8904_LRCLK_DIR_MASK 0x0800 /* LRCLK_DIR */ | |
446 | #define WM8904_LRCLK_DIR_SHIFT 11 /* LRCLK_DIR */ | |
447 | #define WM8904_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ | |
448 | #define WM8904_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ | |
449 | #define WM8904_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ | |
450 | #define WM8904_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ | |
451 | ||
452 | /* | |
453 | * R30 (0x1E) - DAC Digital Volume Left | |
454 | */ | |
455 | #define WM8904_DAC_VU 0x0100 /* DAC_VU */ | |
456 | #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */ | |
457 | #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */ | |
458 | #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */ | |
459 | #define WM8904_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ | |
460 | #define WM8904_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ | |
461 | #define WM8904_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ | |
462 | ||
463 | /* | |
464 | * R31 (0x1F) - DAC Digital Volume Right | |
465 | */ | |
466 | #define WM8904_DAC_VU 0x0100 /* DAC_VU */ | |
467 | #define WM8904_DAC_VU_MASK 0x0100 /* DAC_VU */ | |
468 | #define WM8904_DAC_VU_SHIFT 8 /* DAC_VU */ | |
469 | #define WM8904_DAC_VU_WIDTH 1 /* DAC_VU */ | |
470 | #define WM8904_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ | |
471 | #define WM8904_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ | |
472 | #define WM8904_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ | |
473 | ||
474 | /* | |
475 | * R32 (0x20) - DAC Digital 0 | |
476 | */ | |
477 | #define WM8904_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */ | |
478 | #define WM8904_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */ | |
479 | #define WM8904_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */ | |
480 | #define WM8904_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ | |
481 | #define WM8904_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ | |
482 | #define WM8904_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ | |
483 | #define WM8904_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ | |
484 | #define WM8904_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ | |
485 | #define WM8904_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ | |
486 | #define WM8904_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ | |
487 | #define WM8904_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ | |
488 | #define WM8904_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ | |
489 | ||
490 | /* | |
491 | * R33 (0x21) - DAC Digital 1 | |
492 | */ | |
493 | #define WM8904_DAC_MONO 0x1000 /* DAC_MONO */ | |
494 | #define WM8904_DAC_MONO_MASK 0x1000 /* DAC_MONO */ | |
495 | #define WM8904_DAC_MONO_SHIFT 12 /* DAC_MONO */ | |
496 | #define WM8904_DAC_MONO_WIDTH 1 /* DAC_MONO */ | |
497 | #define WM8904_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */ | |
498 | #define WM8904_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */ | |
499 | #define WM8904_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */ | |
500 | #define WM8904_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ | |
501 | #define WM8904_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ | |
502 | #define WM8904_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ | |
503 | #define WM8904_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ | |
504 | #define WM8904_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ | |
505 | #define WM8904_DAC_UNMUTE_RAMP 0x0200 /* DAC_UNMUTE_RAMP */ | |
506 | #define WM8904_DAC_UNMUTE_RAMP_MASK 0x0200 /* DAC_UNMUTE_RAMP */ | |
507 | #define WM8904_DAC_UNMUTE_RAMP_SHIFT 9 /* DAC_UNMUTE_RAMP */ | |
508 | #define WM8904_DAC_UNMUTE_RAMP_WIDTH 1 /* DAC_UNMUTE_RAMP */ | |
509 | #define WM8904_DAC_OSR128 0x0040 /* DAC_OSR128 */ | |
510 | #define WM8904_DAC_OSR128_MASK 0x0040 /* DAC_OSR128 */ | |
511 | #define WM8904_DAC_OSR128_SHIFT 6 /* DAC_OSR128 */ | |
512 | #define WM8904_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ | |
513 | #define WM8904_DAC_MUTE 0x0008 /* DAC_MUTE */ | |
514 | #define WM8904_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ | |
515 | #define WM8904_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ | |
516 | #define WM8904_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ | |
517 | #define WM8904_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ | |
518 | #define WM8904_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ | |
519 | #define WM8904_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ | |
520 | ||
521 | /* | |
522 | * R36 (0x24) - ADC Digital Volume Left | |
523 | */ | |
524 | #define WM8904_ADC_VU 0x0100 /* ADC_VU */ | |
525 | #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */ | |
526 | #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */ | |
527 | #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */ | |
528 | #define WM8904_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ | |
529 | #define WM8904_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ | |
530 | #define WM8904_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ | |
531 | ||
532 | /* | |
533 | * R37 (0x25) - ADC Digital Volume Right | |
534 | */ | |
535 | #define WM8904_ADC_VU 0x0100 /* ADC_VU */ | |
536 | #define WM8904_ADC_VU_MASK 0x0100 /* ADC_VU */ | |
537 | #define WM8904_ADC_VU_SHIFT 8 /* ADC_VU */ | |
538 | #define WM8904_ADC_VU_WIDTH 1 /* ADC_VU */ | |
539 | #define WM8904_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ | |
540 | #define WM8904_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ | |
541 | #define WM8904_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ | |
542 | ||
543 | /* | |
544 | * R38 (0x26) - ADC Digital 0 | |
545 | */ | |
546 | #define WM8904_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ | |
547 | #define WM8904_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ | |
548 | #define WM8904_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ | |
549 | #define WM8904_ADC_HPF 0x0010 /* ADC_HPF */ | |
550 | #define WM8904_ADC_HPF_MASK 0x0010 /* ADC_HPF */ | |
551 | #define WM8904_ADC_HPF_SHIFT 4 /* ADC_HPF */ | |
552 | #define WM8904_ADC_HPF_WIDTH 1 /* ADC_HPF */ | |
553 | #define WM8904_ADCL_DATINV 0x0002 /* ADCL_DATINV */ | |
554 | #define WM8904_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ | |
555 | #define WM8904_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ | |
556 | #define WM8904_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ | |
557 | #define WM8904_ADCR_DATINV 0x0001 /* ADCR_DATINV */ | |
558 | #define WM8904_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ | |
559 | #define WM8904_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ | |
560 | #define WM8904_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ | |
561 | ||
562 | /* | |
563 | * R39 (0x27) - Digital Microphone 0 | |
564 | */ | |
565 | #define WM8904_DMIC_ENA 0x1000 /* DMIC_ENA */ | |
566 | #define WM8904_DMIC_ENA_MASK 0x1000 /* DMIC_ENA */ | |
567 | #define WM8904_DMIC_ENA_SHIFT 12 /* DMIC_ENA */ | |
568 | #define WM8904_DMIC_ENA_WIDTH 1 /* DMIC_ENA */ | |
569 | #define WM8904_DMIC_SRC 0x0800 /* DMIC_SRC */ | |
570 | #define WM8904_DMIC_SRC_MASK 0x0800 /* DMIC_SRC */ | |
571 | #define WM8904_DMIC_SRC_SHIFT 11 /* DMIC_SRC */ | |
572 | #define WM8904_DMIC_SRC_WIDTH 1 /* DMIC_SRC */ | |
573 | ||
574 | /* | |
575 | * R40 (0x28) - DRC 0 | |
576 | */ | |
577 | #define WM8904_DRC_ENA 0x8000 /* DRC_ENA */ | |
578 | #define WM8904_DRC_ENA_MASK 0x8000 /* DRC_ENA */ | |
579 | #define WM8904_DRC_ENA_SHIFT 15 /* DRC_ENA */ | |
580 | #define WM8904_DRC_ENA_WIDTH 1 /* DRC_ENA */ | |
581 | #define WM8904_DRC_DAC_PATH 0x4000 /* DRC_DAC_PATH */ | |
582 | #define WM8904_DRC_DAC_PATH_MASK 0x4000 /* DRC_DAC_PATH */ | |
583 | #define WM8904_DRC_DAC_PATH_SHIFT 14 /* DRC_DAC_PATH */ | |
584 | #define WM8904_DRC_DAC_PATH_WIDTH 1 /* DRC_DAC_PATH */ | |
585 | #define WM8904_DRC_GS_HYST_LVL_MASK 0x1800 /* DRC_GS_HYST_LVL - [12:11] */ | |
586 | #define WM8904_DRC_GS_HYST_LVL_SHIFT 11 /* DRC_GS_HYST_LVL - [12:11] */ | |
587 | #define WM8904_DRC_GS_HYST_LVL_WIDTH 2 /* DRC_GS_HYST_LVL - [12:11] */ | |
588 | #define WM8904_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ | |
589 | #define WM8904_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ | |
590 | #define WM8904_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ | |
591 | #define WM8904_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */ | |
592 | #define WM8904_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */ | |
593 | #define WM8904_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */ | |
594 | #define WM8904_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */ | |
595 | #define WM8904_DRC_GS_ENA 0x0008 /* DRC_GS_ENA */ | |
596 | #define WM8904_DRC_GS_ENA_MASK 0x0008 /* DRC_GS_ENA */ | |
597 | #define WM8904_DRC_GS_ENA_SHIFT 3 /* DRC_GS_ENA */ | |
598 | #define WM8904_DRC_GS_ENA_WIDTH 1 /* DRC_GS_ENA */ | |
599 | #define WM8904_DRC_QR 0x0004 /* DRC_QR */ | |
600 | #define WM8904_DRC_QR_MASK 0x0004 /* DRC_QR */ | |
601 | #define WM8904_DRC_QR_SHIFT 2 /* DRC_QR */ | |
602 | #define WM8904_DRC_QR_WIDTH 1 /* DRC_QR */ | |
603 | #define WM8904_DRC_ANTICLIP 0x0002 /* DRC_ANTICLIP */ | |
604 | #define WM8904_DRC_ANTICLIP_MASK 0x0002 /* DRC_ANTICLIP */ | |
605 | #define WM8904_DRC_ANTICLIP_SHIFT 1 /* DRC_ANTICLIP */ | |
606 | #define WM8904_DRC_ANTICLIP_WIDTH 1 /* DRC_ANTICLIP */ | |
607 | #define WM8904_DRC_GS_HYST 0x0001 /* DRC_GS_HYST */ | |
608 | #define WM8904_DRC_GS_HYST_MASK 0x0001 /* DRC_GS_HYST */ | |
609 | #define WM8904_DRC_GS_HYST_SHIFT 0 /* DRC_GS_HYST */ | |
610 | #define WM8904_DRC_GS_HYST_WIDTH 1 /* DRC_GS_HYST */ | |
611 | ||
612 | /* | |
613 | * R41 (0x29) - DRC 1 | |
614 | */ | |
615 | #define WM8904_DRC_ATK_MASK 0xF000 /* DRC_ATK - [15:12] */ | |
616 | #define WM8904_DRC_ATK_SHIFT 12 /* DRC_ATK - [15:12] */ | |
617 | #define WM8904_DRC_ATK_WIDTH 4 /* DRC_ATK - [15:12] */ | |
618 | #define WM8904_DRC_DCY_MASK 0x0F00 /* DRC_DCY - [11:8] */ | |
619 | #define WM8904_DRC_DCY_SHIFT 8 /* DRC_DCY - [11:8] */ | |
620 | #define WM8904_DRC_DCY_WIDTH 4 /* DRC_DCY - [11:8] */ | |
621 | #define WM8904_DRC_QR_THR_MASK 0x00C0 /* DRC_QR_THR - [7:6] */ | |
622 | #define WM8904_DRC_QR_THR_SHIFT 6 /* DRC_QR_THR - [7:6] */ | |
623 | #define WM8904_DRC_QR_THR_WIDTH 2 /* DRC_QR_THR - [7:6] */ | |
624 | #define WM8904_DRC_QR_DCY_MASK 0x0030 /* DRC_QR_DCY - [5:4] */ | |
625 | #define WM8904_DRC_QR_DCY_SHIFT 4 /* DRC_QR_DCY - [5:4] */ | |
626 | #define WM8904_DRC_QR_DCY_WIDTH 2 /* DRC_QR_DCY - [5:4] */ | |
627 | #define WM8904_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ | |
628 | #define WM8904_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ | |
629 | #define WM8904_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ | |
630 | #define WM8904_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ | |
631 | #define WM8904_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ | |
632 | #define WM8904_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ | |
633 | ||
634 | /* | |
635 | * R42 (0x2A) - DRC 2 | |
636 | */ | |
637 | #define WM8904_DRC_HI_COMP_MASK 0x0038 /* DRC_HI_COMP - [5:3] */ | |
638 | #define WM8904_DRC_HI_COMP_SHIFT 3 /* DRC_HI_COMP - [5:3] */ | |
639 | #define WM8904_DRC_HI_COMP_WIDTH 3 /* DRC_HI_COMP - [5:3] */ | |
640 | #define WM8904_DRC_LO_COMP_MASK 0x0007 /* DRC_LO_COMP - [2:0] */ | |
641 | #define WM8904_DRC_LO_COMP_SHIFT 0 /* DRC_LO_COMP - [2:0] */ | |
642 | #define WM8904_DRC_LO_COMP_WIDTH 3 /* DRC_LO_COMP - [2:0] */ | |
643 | ||
644 | /* | |
645 | * R43 (0x2B) - DRC 3 | |
646 | */ | |
647 | #define WM8904_DRC_KNEE_IP_MASK 0x07E0 /* DRC_KNEE_IP - [10:5] */ | |
648 | #define WM8904_DRC_KNEE_IP_SHIFT 5 /* DRC_KNEE_IP - [10:5] */ | |
649 | #define WM8904_DRC_KNEE_IP_WIDTH 6 /* DRC_KNEE_IP - [10:5] */ | |
650 | #define WM8904_DRC_KNEE_OP_MASK 0x001F /* DRC_KNEE_OP - [4:0] */ | |
651 | #define WM8904_DRC_KNEE_OP_SHIFT 0 /* DRC_KNEE_OP - [4:0] */ | |
652 | #define WM8904_DRC_KNEE_OP_WIDTH 5 /* DRC_KNEE_OP - [4:0] */ | |
653 | ||
654 | /* | |
655 | * R44 (0x2C) - Analogue Left Input 0 | |
656 | */ | |
657 | #define WM8904_LINMUTE 0x0080 /* LINMUTE */ | |
658 | #define WM8904_LINMUTE_MASK 0x0080 /* LINMUTE */ | |
659 | #define WM8904_LINMUTE_SHIFT 7 /* LINMUTE */ | |
660 | #define WM8904_LINMUTE_WIDTH 1 /* LINMUTE */ | |
661 | #define WM8904_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */ | |
662 | #define WM8904_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */ | |
663 | #define WM8904_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */ | |
664 | ||
665 | /* | |
666 | * R45 (0x2D) - Analogue Right Input 0 | |
667 | */ | |
668 | #define WM8904_RINMUTE 0x0080 /* RINMUTE */ | |
669 | #define WM8904_RINMUTE_MASK 0x0080 /* RINMUTE */ | |
670 | #define WM8904_RINMUTE_SHIFT 7 /* RINMUTE */ | |
671 | #define WM8904_RINMUTE_WIDTH 1 /* RINMUTE */ | |
672 | #define WM8904_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */ | |
673 | #define WM8904_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */ | |
674 | #define WM8904_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */ | |
675 | ||
676 | /* | |
677 | * R46 (0x2E) - Analogue Left Input 1 | |
678 | */ | |
679 | #define WM8904_INL_CM_ENA 0x0040 /* INL_CM_ENA */ | |
680 | #define WM8904_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */ | |
681 | #define WM8904_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */ | |
682 | #define WM8904_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */ | |
683 | #define WM8904_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */ | |
684 | #define WM8904_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */ | |
685 | #define WM8904_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */ | |
686 | #define WM8904_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */ | |
687 | #define WM8904_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */ | |
688 | #define WM8904_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */ | |
689 | #define WM8904_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */ | |
690 | #define WM8904_L_MODE_SHIFT 0 /* L_MODE - [1:0] */ | |
691 | #define WM8904_L_MODE_WIDTH 2 /* L_MODE - [1:0] */ | |
692 | ||
693 | /* | |
694 | * R47 (0x2F) - Analogue Right Input 1 | |
695 | */ | |
696 | #define WM8904_INR_CM_ENA 0x0040 /* INR_CM_ENA */ | |
697 | #define WM8904_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */ | |
698 | #define WM8904_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */ | |
699 | #define WM8904_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */ | |
700 | #define WM8904_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */ | |
701 | #define WM8904_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */ | |
702 | #define WM8904_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */ | |
703 | #define WM8904_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */ | |
704 | #define WM8904_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */ | |
705 | #define WM8904_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */ | |
706 | #define WM8904_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */ | |
707 | #define WM8904_R_MODE_SHIFT 0 /* R_MODE - [1:0] */ | |
708 | #define WM8904_R_MODE_WIDTH 2 /* R_MODE - [1:0] */ | |
709 | ||
710 | /* | |
711 | * R57 (0x39) - Analogue OUT1 Left | |
712 | */ | |
713 | #define WM8904_HPOUTL_MUTE 0x0100 /* HPOUTL_MUTE */ | |
714 | #define WM8904_HPOUTL_MUTE_MASK 0x0100 /* HPOUTL_MUTE */ | |
715 | #define WM8904_HPOUTL_MUTE_SHIFT 8 /* HPOUTL_MUTE */ | |
716 | #define WM8904_HPOUTL_MUTE_WIDTH 1 /* HPOUTL_MUTE */ | |
717 | #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */ | |
718 | #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */ | |
719 | #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */ | |
720 | #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ | |
721 | #define WM8904_HPOUTLZC 0x0040 /* HPOUTLZC */ | |
722 | #define WM8904_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */ | |
723 | #define WM8904_HPOUTLZC_SHIFT 6 /* HPOUTLZC */ | |
724 | #define WM8904_HPOUTLZC_WIDTH 1 /* HPOUTLZC */ | |
725 | #define WM8904_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */ | |
726 | #define WM8904_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */ | |
727 | #define WM8904_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */ | |
728 | ||
729 | /* | |
730 | * R58 (0x3A) - Analogue OUT1 Right | |
731 | */ | |
732 | #define WM8904_HPOUTR_MUTE 0x0100 /* HPOUTR_MUTE */ | |
733 | #define WM8904_HPOUTR_MUTE_MASK 0x0100 /* HPOUTR_MUTE */ | |
734 | #define WM8904_HPOUTR_MUTE_SHIFT 8 /* HPOUTR_MUTE */ | |
735 | #define WM8904_HPOUTR_MUTE_WIDTH 1 /* HPOUTR_MUTE */ | |
736 | #define WM8904_HPOUT_VU 0x0080 /* HPOUT_VU */ | |
737 | #define WM8904_HPOUT_VU_MASK 0x0080 /* HPOUT_VU */ | |
738 | #define WM8904_HPOUT_VU_SHIFT 7 /* HPOUT_VU */ | |
739 | #define WM8904_HPOUT_VU_WIDTH 1 /* HPOUT_VU */ | |
740 | #define WM8904_HPOUTRZC 0x0040 /* HPOUTRZC */ | |
741 | #define WM8904_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */ | |
742 | #define WM8904_HPOUTRZC_SHIFT 6 /* HPOUTRZC */ | |
743 | #define WM8904_HPOUTRZC_WIDTH 1 /* HPOUTRZC */ | |
744 | #define WM8904_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */ | |
745 | #define WM8904_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */ | |
746 | #define WM8904_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */ | |
747 | ||
748 | /* | |
749 | * R59 (0x3B) - Analogue OUT2 Left | |
750 | */ | |
751 | #define WM8904_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */ | |
752 | #define WM8904_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */ | |
753 | #define WM8904_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */ | |
754 | #define WM8904_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */ | |
755 | #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */ | |
756 | #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */ | |
757 | #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */ | |
758 | #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */ | |
759 | #define WM8904_LINEOUTLZC 0x0040 /* LINEOUTLZC */ | |
760 | #define WM8904_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */ | |
761 | #define WM8904_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */ | |
762 | #define WM8904_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */ | |
763 | #define WM8904_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */ | |
764 | #define WM8904_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */ | |
765 | #define WM8904_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */ | |
766 | ||
767 | /* | |
768 | * R60 (0x3C) - Analogue OUT2 Right | |
769 | */ | |
770 | #define WM8904_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */ | |
771 | #define WM8904_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */ | |
772 | #define WM8904_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */ | |
773 | #define WM8904_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */ | |
774 | #define WM8904_LINEOUT_VU 0x0080 /* LINEOUT_VU */ | |
775 | #define WM8904_LINEOUT_VU_MASK 0x0080 /* LINEOUT_VU */ | |
776 | #define WM8904_LINEOUT_VU_SHIFT 7 /* LINEOUT_VU */ | |
777 | #define WM8904_LINEOUT_VU_WIDTH 1 /* LINEOUT_VU */ | |
778 | #define WM8904_LINEOUTRZC 0x0040 /* LINEOUTRZC */ | |
779 | #define WM8904_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */ | |
780 | #define WM8904_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */ | |
781 | #define WM8904_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */ | |
782 | #define WM8904_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */ | |
783 | #define WM8904_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */ | |
784 | #define WM8904_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */ | |
785 | ||
786 | /* | |
787 | * R61 (0x3D) - Analogue OUT12 ZC | |
788 | */ | |
789 | #define WM8904_HPL_BYP_ENA 0x0008 /* HPL_BYP_ENA */ | |
790 | #define WM8904_HPL_BYP_ENA_MASK 0x0008 /* HPL_BYP_ENA */ | |
791 | #define WM8904_HPL_BYP_ENA_SHIFT 3 /* HPL_BYP_ENA */ | |
792 | #define WM8904_HPL_BYP_ENA_WIDTH 1 /* HPL_BYP_ENA */ | |
793 | #define WM8904_HPR_BYP_ENA 0x0004 /* HPR_BYP_ENA */ | |
794 | #define WM8904_HPR_BYP_ENA_MASK 0x0004 /* HPR_BYP_ENA */ | |
795 | #define WM8904_HPR_BYP_ENA_SHIFT 2 /* HPR_BYP_ENA */ | |
796 | #define WM8904_HPR_BYP_ENA_WIDTH 1 /* HPR_BYP_ENA */ | |
797 | #define WM8904_LINEOUTL_BYP_ENA 0x0002 /* LINEOUTL_BYP_ENA */ | |
798 | #define WM8904_LINEOUTL_BYP_ENA_MASK 0x0002 /* LINEOUTL_BYP_ENA */ | |
799 | #define WM8904_LINEOUTL_BYP_ENA_SHIFT 1 /* LINEOUTL_BYP_ENA */ | |
800 | #define WM8904_LINEOUTL_BYP_ENA_WIDTH 1 /* LINEOUTL_BYP_ENA */ | |
801 | #define WM8904_LINEOUTR_BYP_ENA 0x0001 /* LINEOUTR_BYP_ENA */ | |
802 | #define WM8904_LINEOUTR_BYP_ENA_MASK 0x0001 /* LINEOUTR_BYP_ENA */ | |
803 | #define WM8904_LINEOUTR_BYP_ENA_SHIFT 0 /* LINEOUTR_BYP_ENA */ | |
804 | #define WM8904_LINEOUTR_BYP_ENA_WIDTH 1 /* LINEOUTR_BYP_ENA */ | |
805 | ||
806 | /* | |
807 | * R67 (0x43) - DC Servo 0 | |
808 | */ | |
809 | #define WM8904_DCS_ENA_CHAN_3 0x0008 /* DCS_ENA_CHAN_3 */ | |
810 | #define WM8904_DCS_ENA_CHAN_3_MASK 0x0008 /* DCS_ENA_CHAN_3 */ | |
811 | #define WM8904_DCS_ENA_CHAN_3_SHIFT 3 /* DCS_ENA_CHAN_3 */ | |
812 | #define WM8904_DCS_ENA_CHAN_3_WIDTH 1 /* DCS_ENA_CHAN_3 */ | |
813 | #define WM8904_DCS_ENA_CHAN_2 0x0004 /* DCS_ENA_CHAN_2 */ | |
814 | #define WM8904_DCS_ENA_CHAN_2_MASK 0x0004 /* DCS_ENA_CHAN_2 */ | |
815 | #define WM8904_DCS_ENA_CHAN_2_SHIFT 2 /* DCS_ENA_CHAN_2 */ | |
816 | #define WM8904_DCS_ENA_CHAN_2_WIDTH 1 /* DCS_ENA_CHAN_2 */ | |
817 | #define WM8904_DCS_ENA_CHAN_1 0x0002 /* DCS_ENA_CHAN_1 */ | |
818 | #define WM8904_DCS_ENA_CHAN_1_MASK 0x0002 /* DCS_ENA_CHAN_1 */ | |
819 | #define WM8904_DCS_ENA_CHAN_1_SHIFT 1 /* DCS_ENA_CHAN_1 */ | |
820 | #define WM8904_DCS_ENA_CHAN_1_WIDTH 1 /* DCS_ENA_CHAN_1 */ | |
821 | #define WM8904_DCS_ENA_CHAN_0 0x0001 /* DCS_ENA_CHAN_0 */ | |
822 | #define WM8904_DCS_ENA_CHAN_0_MASK 0x0001 /* DCS_ENA_CHAN_0 */ | |
823 | #define WM8904_DCS_ENA_CHAN_0_SHIFT 0 /* DCS_ENA_CHAN_0 */ | |
824 | #define WM8904_DCS_ENA_CHAN_0_WIDTH 1 /* DCS_ENA_CHAN_0 */ | |
825 | ||
826 | /* | |
827 | * R68 (0x44) - DC Servo 1 | |
828 | */ | |
829 | #define WM8904_DCS_TRIG_SINGLE_3 0x8000 /* DCS_TRIG_SINGLE_3 */ | |
830 | #define WM8904_DCS_TRIG_SINGLE_3_MASK 0x8000 /* DCS_TRIG_SINGLE_3 */ | |
831 | #define WM8904_DCS_TRIG_SINGLE_3_SHIFT 15 /* DCS_TRIG_SINGLE_3 */ | |
832 | #define WM8904_DCS_TRIG_SINGLE_3_WIDTH 1 /* DCS_TRIG_SINGLE_3 */ | |
833 | #define WM8904_DCS_TRIG_SINGLE_2 0x4000 /* DCS_TRIG_SINGLE_2 */ | |
834 | #define WM8904_DCS_TRIG_SINGLE_2_MASK 0x4000 /* DCS_TRIG_SINGLE_2 */ | |
835 | #define WM8904_DCS_TRIG_SINGLE_2_SHIFT 14 /* DCS_TRIG_SINGLE_2 */ | |
836 | #define WM8904_DCS_TRIG_SINGLE_2_WIDTH 1 /* DCS_TRIG_SINGLE_2 */ | |
837 | #define WM8904_DCS_TRIG_SINGLE_1 0x2000 /* DCS_TRIG_SINGLE_1 */ | |
838 | #define WM8904_DCS_TRIG_SINGLE_1_MASK 0x2000 /* DCS_TRIG_SINGLE_1 */ | |
839 | #define WM8904_DCS_TRIG_SINGLE_1_SHIFT 13 /* DCS_TRIG_SINGLE_1 */ | |
840 | #define WM8904_DCS_TRIG_SINGLE_1_WIDTH 1 /* DCS_TRIG_SINGLE_1 */ | |
841 | #define WM8904_DCS_TRIG_SINGLE_0 0x1000 /* DCS_TRIG_SINGLE_0 */ | |
842 | #define WM8904_DCS_TRIG_SINGLE_0_MASK 0x1000 /* DCS_TRIG_SINGLE_0 */ | |
843 | #define WM8904_DCS_TRIG_SINGLE_0_SHIFT 12 /* DCS_TRIG_SINGLE_0 */ | |
844 | #define WM8904_DCS_TRIG_SINGLE_0_WIDTH 1 /* DCS_TRIG_SINGLE_0 */ | |
845 | #define WM8904_DCS_TRIG_SERIES_3 0x0800 /* DCS_TRIG_SERIES_3 */ | |
846 | #define WM8904_DCS_TRIG_SERIES_3_MASK 0x0800 /* DCS_TRIG_SERIES_3 */ | |
847 | #define WM8904_DCS_TRIG_SERIES_3_SHIFT 11 /* DCS_TRIG_SERIES_3 */ | |
848 | #define WM8904_DCS_TRIG_SERIES_3_WIDTH 1 /* DCS_TRIG_SERIES_3 */ | |
849 | #define WM8904_DCS_TRIG_SERIES_2 0x0400 /* DCS_TRIG_SERIES_2 */ | |
850 | #define WM8904_DCS_TRIG_SERIES_2_MASK 0x0400 /* DCS_TRIG_SERIES_2 */ | |
851 | #define WM8904_DCS_TRIG_SERIES_2_SHIFT 10 /* DCS_TRIG_SERIES_2 */ | |
852 | #define WM8904_DCS_TRIG_SERIES_2_WIDTH 1 /* DCS_TRIG_SERIES_2 */ | |
853 | #define WM8904_DCS_TRIG_SERIES_1 0x0200 /* DCS_TRIG_SERIES_1 */ | |
854 | #define WM8904_DCS_TRIG_SERIES_1_MASK 0x0200 /* DCS_TRIG_SERIES_1 */ | |
855 | #define WM8904_DCS_TRIG_SERIES_1_SHIFT 9 /* DCS_TRIG_SERIES_1 */ | |
856 | #define WM8904_DCS_TRIG_SERIES_1_WIDTH 1 /* DCS_TRIG_SERIES_1 */ | |
857 | #define WM8904_DCS_TRIG_SERIES_0 0x0100 /* DCS_TRIG_SERIES_0 */ | |
858 | #define WM8904_DCS_TRIG_SERIES_0_MASK 0x0100 /* DCS_TRIG_SERIES_0 */ | |
859 | #define WM8904_DCS_TRIG_SERIES_0_SHIFT 8 /* DCS_TRIG_SERIES_0 */ | |
860 | #define WM8904_DCS_TRIG_SERIES_0_WIDTH 1 /* DCS_TRIG_SERIES_0 */ | |
861 | #define WM8904_DCS_TRIG_STARTUP_3 0x0080 /* DCS_TRIG_STARTUP_3 */ | |
862 | #define WM8904_DCS_TRIG_STARTUP_3_MASK 0x0080 /* DCS_TRIG_STARTUP_3 */ | |
863 | #define WM8904_DCS_TRIG_STARTUP_3_SHIFT 7 /* DCS_TRIG_STARTUP_3 */ | |
864 | #define WM8904_DCS_TRIG_STARTUP_3_WIDTH 1 /* DCS_TRIG_STARTUP_3 */ | |
865 | #define WM8904_DCS_TRIG_STARTUP_2 0x0040 /* DCS_TRIG_STARTUP_2 */ | |
866 | #define WM8904_DCS_TRIG_STARTUP_2_MASK 0x0040 /* DCS_TRIG_STARTUP_2 */ | |
867 | #define WM8904_DCS_TRIG_STARTUP_2_SHIFT 6 /* DCS_TRIG_STARTUP_2 */ | |
868 | #define WM8904_DCS_TRIG_STARTUP_2_WIDTH 1 /* DCS_TRIG_STARTUP_2 */ | |
869 | #define WM8904_DCS_TRIG_STARTUP_1 0x0020 /* DCS_TRIG_STARTUP_1 */ | |
870 | #define WM8904_DCS_TRIG_STARTUP_1_MASK 0x0020 /* DCS_TRIG_STARTUP_1 */ | |
871 | #define WM8904_DCS_TRIG_STARTUP_1_SHIFT 5 /* DCS_TRIG_STARTUP_1 */ | |
872 | #define WM8904_DCS_TRIG_STARTUP_1_WIDTH 1 /* DCS_TRIG_STARTUP_1 */ | |
873 | #define WM8904_DCS_TRIG_STARTUP_0 0x0010 /* DCS_TRIG_STARTUP_0 */ | |
874 | #define WM8904_DCS_TRIG_STARTUP_0_MASK 0x0010 /* DCS_TRIG_STARTUP_0 */ | |
875 | #define WM8904_DCS_TRIG_STARTUP_0_SHIFT 4 /* DCS_TRIG_STARTUP_0 */ | |
876 | #define WM8904_DCS_TRIG_STARTUP_0_WIDTH 1 /* DCS_TRIG_STARTUP_0 */ | |
877 | #define WM8904_DCS_TRIG_DAC_WR_3 0x0008 /* DCS_TRIG_DAC_WR_3 */ | |
878 | #define WM8904_DCS_TRIG_DAC_WR_3_MASK 0x0008 /* DCS_TRIG_DAC_WR_3 */ | |
879 | #define WM8904_DCS_TRIG_DAC_WR_3_SHIFT 3 /* DCS_TRIG_DAC_WR_3 */ | |
880 | #define WM8904_DCS_TRIG_DAC_WR_3_WIDTH 1 /* DCS_TRIG_DAC_WR_3 */ | |
881 | #define WM8904_DCS_TRIG_DAC_WR_2 0x0004 /* DCS_TRIG_DAC_WR_2 */ | |
882 | #define WM8904_DCS_TRIG_DAC_WR_2_MASK 0x0004 /* DCS_TRIG_DAC_WR_2 */ | |
883 | #define WM8904_DCS_TRIG_DAC_WR_2_SHIFT 2 /* DCS_TRIG_DAC_WR_2 */ | |
884 | #define WM8904_DCS_TRIG_DAC_WR_2_WIDTH 1 /* DCS_TRIG_DAC_WR_2 */ | |
885 | #define WM8904_DCS_TRIG_DAC_WR_1 0x0002 /* DCS_TRIG_DAC_WR_1 */ | |
886 | #define WM8904_DCS_TRIG_DAC_WR_1_MASK 0x0002 /* DCS_TRIG_DAC_WR_1 */ | |
887 | #define WM8904_DCS_TRIG_DAC_WR_1_SHIFT 1 /* DCS_TRIG_DAC_WR_1 */ | |
888 | #define WM8904_DCS_TRIG_DAC_WR_1_WIDTH 1 /* DCS_TRIG_DAC_WR_1 */ | |
889 | #define WM8904_DCS_TRIG_DAC_WR_0 0x0001 /* DCS_TRIG_DAC_WR_0 */ | |
890 | #define WM8904_DCS_TRIG_DAC_WR_0_MASK 0x0001 /* DCS_TRIG_DAC_WR_0 */ | |
891 | #define WM8904_DCS_TRIG_DAC_WR_0_SHIFT 0 /* DCS_TRIG_DAC_WR_0 */ | |
892 | #define WM8904_DCS_TRIG_DAC_WR_0_WIDTH 1 /* DCS_TRIG_DAC_WR_0 */ | |
893 | ||
894 | /* | |
895 | * R69 (0x45) - DC Servo 2 | |
896 | */ | |
897 | #define WM8904_DCS_TIMER_PERIOD_23_MASK 0x0F00 /* DCS_TIMER_PERIOD_23 - [11:8] */ | |
898 | #define WM8904_DCS_TIMER_PERIOD_23_SHIFT 8 /* DCS_TIMER_PERIOD_23 - [11:8] */ | |
899 | #define WM8904_DCS_TIMER_PERIOD_23_WIDTH 4 /* DCS_TIMER_PERIOD_23 - [11:8] */ | |
900 | #define WM8904_DCS_TIMER_PERIOD_01_MASK 0x000F /* DCS_TIMER_PERIOD_01 - [3:0] */ | |
901 | #define WM8904_DCS_TIMER_PERIOD_01_SHIFT 0 /* DCS_TIMER_PERIOD_01 - [3:0] */ | |
902 | #define WM8904_DCS_TIMER_PERIOD_01_WIDTH 4 /* DCS_TIMER_PERIOD_01 - [3:0] */ | |
903 | ||
904 | /* | |
905 | * R71 (0x47) - DC Servo 4 | |
906 | */ | |
907 | #define WM8904_DCS_SERIES_NO_23_MASK 0x007F /* DCS_SERIES_NO_23 - [6:0] */ | |
908 | #define WM8904_DCS_SERIES_NO_23_SHIFT 0 /* DCS_SERIES_NO_23 - [6:0] */ | |
909 | #define WM8904_DCS_SERIES_NO_23_WIDTH 7 /* DCS_SERIES_NO_23 - [6:0] */ | |
910 | ||
911 | /* | |
912 | * R72 (0x48) - DC Servo 5 | |
913 | */ | |
914 | #define WM8904_DCS_SERIES_NO_01_MASK 0x007F /* DCS_SERIES_NO_01 - [6:0] */ | |
915 | #define WM8904_DCS_SERIES_NO_01_SHIFT 0 /* DCS_SERIES_NO_01 - [6:0] */ | |
916 | #define WM8904_DCS_SERIES_NO_01_WIDTH 7 /* DCS_SERIES_NO_01 - [6:0] */ | |
917 | ||
918 | /* | |
919 | * R73 (0x49) - DC Servo 6 | |
920 | */ | |
921 | #define WM8904_DCS_DAC_WR_VAL_3_MASK 0x00FF /* DCS_DAC_WR_VAL_3 - [7:0] */ | |
922 | #define WM8904_DCS_DAC_WR_VAL_3_SHIFT 0 /* DCS_DAC_WR_VAL_3 - [7:0] */ | |
923 | #define WM8904_DCS_DAC_WR_VAL_3_WIDTH 8 /* DCS_DAC_WR_VAL_3 - [7:0] */ | |
924 | ||
925 | /* | |
926 | * R74 (0x4A) - DC Servo 7 | |
927 | */ | |
928 | #define WM8904_DCS_DAC_WR_VAL_2_MASK 0x00FF /* DCS_DAC_WR_VAL_2 - [7:0] */ | |
929 | #define WM8904_DCS_DAC_WR_VAL_2_SHIFT 0 /* DCS_DAC_WR_VAL_2 - [7:0] */ | |
930 | #define WM8904_DCS_DAC_WR_VAL_2_WIDTH 8 /* DCS_DAC_WR_VAL_2 - [7:0] */ | |
931 | ||
932 | /* | |
933 | * R75 (0x4B) - DC Servo 8 | |
934 | */ | |
935 | #define WM8904_DCS_DAC_WR_VAL_1_MASK 0x00FF /* DCS_DAC_WR_VAL_1 - [7:0] */ | |
936 | #define WM8904_DCS_DAC_WR_VAL_1_SHIFT 0 /* DCS_DAC_WR_VAL_1 - [7:0] */ | |
937 | #define WM8904_DCS_DAC_WR_VAL_1_WIDTH 8 /* DCS_DAC_WR_VAL_1 - [7:0] */ | |
938 | ||
939 | /* | |
940 | * R76 (0x4C) - DC Servo 9 | |
941 | */ | |
942 | #define WM8904_DCS_DAC_WR_VAL_0_MASK 0x00FF /* DCS_DAC_WR_VAL_0 - [7:0] */ | |
943 | #define WM8904_DCS_DAC_WR_VAL_0_SHIFT 0 /* DCS_DAC_WR_VAL_0 - [7:0] */ | |
944 | #define WM8904_DCS_DAC_WR_VAL_0_WIDTH 8 /* DCS_DAC_WR_VAL_0 - [7:0] */ | |
945 | ||
946 | /* | |
947 | * R77 (0x4D) - DC Servo Readback 0 | |
948 | */ | |
949 | #define WM8904_DCS_CAL_COMPLETE_MASK 0x0F00 /* DCS_CAL_COMPLETE - [11:8] */ | |
950 | #define WM8904_DCS_CAL_COMPLETE_SHIFT 8 /* DCS_CAL_COMPLETE - [11:8] */ | |
951 | #define WM8904_DCS_CAL_COMPLETE_WIDTH 4 /* DCS_CAL_COMPLETE - [11:8] */ | |
952 | #define WM8904_DCS_DAC_WR_COMPLETE_MASK 0x00F0 /* DCS_DAC_WR_COMPLETE - [7:4] */ | |
953 | #define WM8904_DCS_DAC_WR_COMPLETE_SHIFT 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ | |
954 | #define WM8904_DCS_DAC_WR_COMPLETE_WIDTH 4 /* DCS_DAC_WR_COMPLETE - [7:4] */ | |
955 | #define WM8904_DCS_STARTUP_COMPLETE_MASK 0x000F /* DCS_STARTUP_COMPLETE - [3:0] */ | |
956 | #define WM8904_DCS_STARTUP_COMPLETE_SHIFT 0 /* DCS_STARTUP_COMPLETE - [3:0] */ | |
957 | #define WM8904_DCS_STARTUP_COMPLETE_WIDTH 4 /* DCS_STARTUP_COMPLETE - [3:0] */ | |
958 | ||
959 | /* | |
960 | * R90 (0x5A) - Analogue HP 0 | |
961 | */ | |
962 | #define WM8904_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ | |
963 | #define WM8904_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ | |
964 | #define WM8904_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ | |
965 | #define WM8904_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ | |
966 | #define WM8904_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ | |
967 | #define WM8904_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ | |
968 | #define WM8904_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ | |
969 | #define WM8904_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ | |
970 | #define WM8904_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ | |
971 | #define WM8904_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ | |
972 | #define WM8904_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ | |
973 | #define WM8904_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ | |
974 | #define WM8904_HPL_ENA 0x0010 /* HPL_ENA */ | |
975 | #define WM8904_HPL_ENA_MASK 0x0010 /* HPL_ENA */ | |
976 | #define WM8904_HPL_ENA_SHIFT 4 /* HPL_ENA */ | |
977 | #define WM8904_HPL_ENA_WIDTH 1 /* HPL_ENA */ | |
978 | #define WM8904_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ | |
979 | #define WM8904_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ | |
980 | #define WM8904_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ | |
981 | #define WM8904_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ | |
982 | #define WM8904_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ | |
983 | #define WM8904_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ | |
984 | #define WM8904_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ | |
985 | #define WM8904_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ | |
986 | #define WM8904_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ | |
987 | #define WM8904_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ | |
988 | #define WM8904_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ | |
989 | #define WM8904_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ | |
990 | #define WM8904_HPR_ENA 0x0001 /* HPR_ENA */ | |
991 | #define WM8904_HPR_ENA_MASK 0x0001 /* HPR_ENA */ | |
992 | #define WM8904_HPR_ENA_SHIFT 0 /* HPR_ENA */ | |
993 | #define WM8904_HPR_ENA_WIDTH 1 /* HPR_ENA */ | |
994 | ||
995 | /* | |
996 | * R94 (0x5E) - Analogue Lineout 0 | |
997 | */ | |
998 | #define WM8904_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */ | |
999 | #define WM8904_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */ | |
1000 | #define WM8904_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */ | |
1001 | #define WM8904_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */ | |
1002 | #define WM8904_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */ | |
1003 | #define WM8904_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */ | |
1004 | #define WM8904_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */ | |
1005 | #define WM8904_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */ | |
1006 | #define WM8904_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */ | |
1007 | #define WM8904_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */ | |
1008 | #define WM8904_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */ | |
1009 | #define WM8904_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */ | |
1010 | #define WM8904_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */ | |
1011 | #define WM8904_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */ | |
1012 | #define WM8904_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */ | |
1013 | #define WM8904_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */ | |
1014 | #define WM8904_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */ | |
1015 | #define WM8904_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */ | |
1016 | #define WM8904_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */ | |
1017 | #define WM8904_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */ | |
1018 | #define WM8904_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */ | |
1019 | #define WM8904_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */ | |
1020 | #define WM8904_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */ | |
1021 | #define WM8904_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */ | |
1022 | #define WM8904_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */ | |
1023 | #define WM8904_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */ | |
1024 | #define WM8904_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */ | |
1025 | #define WM8904_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */ | |
1026 | #define WM8904_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */ | |
1027 | #define WM8904_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */ | |
1028 | #define WM8904_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */ | |
1029 | #define WM8904_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */ | |
1030 | ||
1031 | /* | |
1032 | * R98 (0x62) - Charge Pump 0 | |
1033 | */ | |
1034 | #define WM8904_CP_ENA 0x0001 /* CP_ENA */ | |
1035 | #define WM8904_CP_ENA_MASK 0x0001 /* CP_ENA */ | |
1036 | #define WM8904_CP_ENA_SHIFT 0 /* CP_ENA */ | |
1037 | #define WM8904_CP_ENA_WIDTH 1 /* CP_ENA */ | |
1038 | ||
1039 | /* | |
1040 | * R104 (0x68) - Class W 0 | |
1041 | */ | |
1042 | #define WM8904_CP_DYN_PWR 0x0001 /* CP_DYN_PWR */ | |
1043 | #define WM8904_CP_DYN_PWR_MASK 0x0001 /* CP_DYN_PWR */ | |
1044 | #define WM8904_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR */ | |
1045 | #define WM8904_CP_DYN_PWR_WIDTH 1 /* CP_DYN_PWR */ | |
1046 | ||
1047 | /* | |
1048 | * R108 (0x6C) - Write Sequencer 0 | |
1049 | */ | |
1050 | #define WM8904_WSEQ_ENA 0x0100 /* WSEQ_ENA */ | |
1051 | #define WM8904_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ | |
1052 | #define WM8904_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ | |
1053 | #define WM8904_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ | |
1054 | #define WM8904_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ | |
1055 | #define WM8904_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ | |
1056 | #define WM8904_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ | |
1057 | ||
1058 | /* | |
1059 | * R109 (0x6D) - Write Sequencer 1 | |
1060 | */ | |
1061 | #define WM8904_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ | |
1062 | #define WM8904_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ | |
1063 | #define WM8904_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ | |
1064 | #define WM8904_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ | |
1065 | #define WM8904_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ | |
1066 | #define WM8904_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ | |
1067 | #define WM8904_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ | |
1068 | #define WM8904_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ | |
1069 | #define WM8904_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ | |
1070 | ||
1071 | /* | |
1072 | * R110 (0x6E) - Write Sequencer 2 | |
1073 | */ | |
1074 | #define WM8904_WSEQ_EOS 0x4000 /* WSEQ_EOS */ | |
1075 | #define WM8904_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ | |
1076 | #define WM8904_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ | |
1077 | #define WM8904_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ | |
1078 | #define WM8904_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ | |
1079 | #define WM8904_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ | |
1080 | #define WM8904_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ | |
1081 | #define WM8904_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ | |
1082 | #define WM8904_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ | |
1083 | #define WM8904_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ | |
1084 | ||
1085 | /* | |
1086 | * R111 (0x6F) - Write Sequencer 3 | |
1087 | */ | |
1088 | #define WM8904_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ | |
1089 | #define WM8904_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ | |
1090 | #define WM8904_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ | |
1091 | #define WM8904_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ | |
1092 | #define WM8904_WSEQ_START 0x0100 /* WSEQ_START */ | |
1093 | #define WM8904_WSEQ_START_MASK 0x0100 /* WSEQ_START */ | |
1094 | #define WM8904_WSEQ_START_SHIFT 8 /* WSEQ_START */ | |
1095 | #define WM8904_WSEQ_START_WIDTH 1 /* WSEQ_START */ | |
1096 | #define WM8904_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ | |
1097 | #define WM8904_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ | |
1098 | #define WM8904_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ | |
1099 | ||
1100 | /* | |
1101 | * R112 (0x70) - Write Sequencer 4 | |
1102 | */ | |
1103 | #define WM8904_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */ | |
1104 | #define WM8904_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */ | |
1105 | #define WM8904_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */ | |
1106 | #define WM8904_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ | |
1107 | #define WM8904_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ | |
1108 | #define WM8904_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ | |
1109 | #define WM8904_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ | |
1110 | ||
1111 | /* | |
1112 | * R116 (0x74) - FLL Control 1 | |
1113 | */ | |
1114 | #define WM8904_FLL_FRACN_ENA 0x0004 /* FLL_FRACN_ENA */ | |
1115 | #define WM8904_FLL_FRACN_ENA_MASK 0x0004 /* FLL_FRACN_ENA */ | |
1116 | #define WM8904_FLL_FRACN_ENA_SHIFT 2 /* FLL_FRACN_ENA */ | |
1117 | #define WM8904_FLL_FRACN_ENA_WIDTH 1 /* FLL_FRACN_ENA */ | |
1118 | #define WM8904_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */ | |
1119 | #define WM8904_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */ | |
1120 | #define WM8904_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */ | |
1121 | #define WM8904_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */ | |
1122 | #define WM8904_FLL_ENA 0x0001 /* FLL_ENA */ | |
1123 | #define WM8904_FLL_ENA_MASK 0x0001 /* FLL_ENA */ | |
1124 | #define WM8904_FLL_ENA_SHIFT 0 /* FLL_ENA */ | |
1125 | #define WM8904_FLL_ENA_WIDTH 1 /* FLL_ENA */ | |
1126 | ||
1127 | /* | |
1128 | * R117 (0x75) - FLL Control 2 | |
1129 | */ | |
1130 | #define WM8904_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */ | |
1131 | #define WM8904_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */ | |
1132 | #define WM8904_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */ | |
1133 | #define WM8904_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */ | |
1134 | #define WM8904_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */ | |
1135 | #define WM8904_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */ | |
1136 | #define WM8904_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */ | |
1137 | #define WM8904_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */ | |
1138 | #define WM8904_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */ | |
1139 | ||
1140 | /* | |
1141 | * R118 (0x76) - FLL Control 3 | |
1142 | */ | |
1143 | #define WM8904_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */ | |
1144 | #define WM8904_FLL_K_SHIFT 0 /* FLL_K - [15:0] */ | |
1145 | #define WM8904_FLL_K_WIDTH 16 /* FLL_K - [15:0] */ | |
1146 | ||
1147 | /* | |
1148 | * R119 (0x77) - FLL Control 4 | |
1149 | */ | |
1150 | #define WM8904_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */ | |
1151 | #define WM8904_FLL_N_SHIFT 5 /* FLL_N - [14:5] */ | |
1152 | #define WM8904_FLL_N_WIDTH 10 /* FLL_N - [14:5] */ | |
1153 | #define WM8904_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */ | |
1154 | #define WM8904_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */ | |
1155 | #define WM8904_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */ | |
1156 | ||
1157 | /* | |
1158 | * R120 (0x78) - FLL Control 5 | |
1159 | */ | |
1160 | #define WM8904_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */ | |
1161 | #define WM8904_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */ | |
1162 | #define WM8904_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */ | |
1163 | #define WM8904_FLL_CLK_REF_SRC_MASK 0x0003 /* FLL_CLK_REF_SRC - [1:0] */ | |
1164 | #define WM8904_FLL_CLK_REF_SRC_SHIFT 0 /* FLL_CLK_REF_SRC - [1:0] */ | |
1165 | #define WM8904_FLL_CLK_REF_SRC_WIDTH 2 /* FLL_CLK_REF_SRC - [1:0] */ | |
1166 | ||
a91eb199 MB |
1167 | /* |
1168 | * R126 (0x7E) - Digital Pulls | |
1169 | */ | |
1170 | #define WM8904_MCLK_PU 0x0080 /* MCLK_PU */ | |
1171 | #define WM8904_MCLK_PU_MASK 0x0080 /* MCLK_PU */ | |
1172 | #define WM8904_MCLK_PU_SHIFT 7 /* MCLK_PU */ | |
1173 | #define WM8904_MCLK_PU_WIDTH 1 /* MCLK_PU */ | |
1174 | #define WM8904_MCLK_PD 0x0040 /* MCLK_PD */ | |
1175 | #define WM8904_MCLK_PD_MASK 0x0040 /* MCLK_PD */ | |
1176 | #define WM8904_MCLK_PD_SHIFT 6 /* MCLK_PD */ | |
1177 | #define WM8904_MCLK_PD_WIDTH 1 /* MCLK_PD */ | |
1178 | #define WM8904_DACDAT_PU 0x0020 /* DACDAT_PU */ | |
1179 | #define WM8904_DACDAT_PU_MASK 0x0020 /* DACDAT_PU */ | |
1180 | #define WM8904_DACDAT_PU_SHIFT 5 /* DACDAT_PU */ | |
1181 | #define WM8904_DACDAT_PU_WIDTH 1 /* DACDAT_PU */ | |
1182 | #define WM8904_DACDAT_PD 0x0010 /* DACDAT_PD */ | |
1183 | #define WM8904_DACDAT_PD_MASK 0x0010 /* DACDAT_PD */ | |
1184 | #define WM8904_DACDAT_PD_SHIFT 4 /* DACDAT_PD */ | |
1185 | #define WM8904_DACDAT_PD_WIDTH 1 /* DACDAT_PD */ | |
1186 | #define WM8904_LRCLK_PU 0x0008 /* LRCLK_PU */ | |
1187 | #define WM8904_LRCLK_PU_MASK 0x0008 /* LRCLK_PU */ | |
1188 | #define WM8904_LRCLK_PU_SHIFT 3 /* LRCLK_PU */ | |
1189 | #define WM8904_LRCLK_PU_WIDTH 1 /* LRCLK_PU */ | |
1190 | #define WM8904_LRCLK_PD 0x0004 /* LRCLK_PD */ | |
1191 | #define WM8904_LRCLK_PD_MASK 0x0004 /* LRCLK_PD */ | |
1192 | #define WM8904_LRCLK_PD_SHIFT 2 /* LRCLK_PD */ | |
1193 | #define WM8904_LRCLK_PD_WIDTH 1 /* LRCLK_PD */ | |
1194 | #define WM8904_BCLK_PU 0x0002 /* BCLK_PU */ | |
1195 | #define WM8904_BCLK_PU_MASK 0x0002 /* BCLK_PU */ | |
1196 | #define WM8904_BCLK_PU_SHIFT 1 /* BCLK_PU */ | |
1197 | #define WM8904_BCLK_PU_WIDTH 1 /* BCLK_PU */ | |
1198 | #define WM8904_BCLK_PD 0x0001 /* BCLK_PD */ | |
1199 | #define WM8904_BCLK_PD_MASK 0x0001 /* BCLK_PD */ | |
1200 | #define WM8904_BCLK_PD_SHIFT 0 /* BCLK_PD */ | |
1201 | #define WM8904_BCLK_PD_WIDTH 1 /* BCLK_PD */ | |
1202 | ||
1203 | /* | |
1204 | * R127 (0x7F) - Interrupt Status | |
1205 | */ | |
1206 | #define WM8904_IRQ 0x0400 /* IRQ */ | |
1207 | #define WM8904_IRQ_MASK 0x0400 /* IRQ */ | |
1208 | #define WM8904_IRQ_SHIFT 10 /* IRQ */ | |
1209 | #define WM8904_IRQ_WIDTH 1 /* IRQ */ | |
1210 | #define WM8904_GPIO_BCLK_EINT 0x0200 /* GPIO_BCLK_EINT */ | |
1211 | #define WM8904_GPIO_BCLK_EINT_MASK 0x0200 /* GPIO_BCLK_EINT */ | |
1212 | #define WM8904_GPIO_BCLK_EINT_SHIFT 9 /* GPIO_BCLK_EINT */ | |
1213 | #define WM8904_GPIO_BCLK_EINT_WIDTH 1 /* GPIO_BCLK_EINT */ | |
1214 | #define WM8904_WSEQ_EINT 0x0100 /* WSEQ_EINT */ | |
1215 | #define WM8904_WSEQ_EINT_MASK 0x0100 /* WSEQ_EINT */ | |
1216 | #define WM8904_WSEQ_EINT_SHIFT 8 /* WSEQ_EINT */ | |
1217 | #define WM8904_WSEQ_EINT_WIDTH 1 /* WSEQ_EINT */ | |
1218 | #define WM8904_GPIO3_EINT 0x0080 /* GPIO3_EINT */ | |
1219 | #define WM8904_GPIO3_EINT_MASK 0x0080 /* GPIO3_EINT */ | |
1220 | #define WM8904_GPIO3_EINT_SHIFT 7 /* GPIO3_EINT */ | |
1221 | #define WM8904_GPIO3_EINT_WIDTH 1 /* GPIO3_EINT */ | |
1222 | #define WM8904_GPIO2_EINT 0x0040 /* GPIO2_EINT */ | |
1223 | #define WM8904_GPIO2_EINT_MASK 0x0040 /* GPIO2_EINT */ | |
1224 | #define WM8904_GPIO2_EINT_SHIFT 6 /* GPIO2_EINT */ | |
1225 | #define WM8904_GPIO2_EINT_WIDTH 1 /* GPIO2_EINT */ | |
1226 | #define WM8904_GPIO1_EINT 0x0020 /* GPIO1_EINT */ | |
1227 | #define WM8904_GPIO1_EINT_MASK 0x0020 /* GPIO1_EINT */ | |
1228 | #define WM8904_GPIO1_EINT_SHIFT 5 /* GPIO1_EINT */ | |
1229 | #define WM8904_GPIO1_EINT_WIDTH 1 /* GPIO1_EINT */ | |
1230 | #define WM8904_GPI8_EINT 0x0010 /* GPI8_EINT */ | |
1231 | #define WM8904_GPI8_EINT_MASK 0x0010 /* GPI8_EINT */ | |
1232 | #define WM8904_GPI8_EINT_SHIFT 4 /* GPI8_EINT */ | |
1233 | #define WM8904_GPI8_EINT_WIDTH 1 /* GPI8_EINT */ | |
1234 | #define WM8904_GPI7_EINT 0x0008 /* GPI7_EINT */ | |
1235 | #define WM8904_GPI7_EINT_MASK 0x0008 /* GPI7_EINT */ | |
1236 | #define WM8904_GPI7_EINT_SHIFT 3 /* GPI7_EINT */ | |
1237 | #define WM8904_GPI7_EINT_WIDTH 1 /* GPI7_EINT */ | |
1238 | #define WM8904_FLL_LOCK_EINT 0x0004 /* FLL_LOCK_EINT */ | |
1239 | #define WM8904_FLL_LOCK_EINT_MASK 0x0004 /* FLL_LOCK_EINT */ | |
1240 | #define WM8904_FLL_LOCK_EINT_SHIFT 2 /* FLL_LOCK_EINT */ | |
1241 | #define WM8904_FLL_LOCK_EINT_WIDTH 1 /* FLL_LOCK_EINT */ | |
1242 | #define WM8904_MIC_SHRT_EINT 0x0002 /* MIC_SHRT_EINT */ | |
1243 | #define WM8904_MIC_SHRT_EINT_MASK 0x0002 /* MIC_SHRT_EINT */ | |
1244 | #define WM8904_MIC_SHRT_EINT_SHIFT 1 /* MIC_SHRT_EINT */ | |
1245 | #define WM8904_MIC_SHRT_EINT_WIDTH 1 /* MIC_SHRT_EINT */ | |
1246 | #define WM8904_MIC_DET_EINT 0x0001 /* MIC_DET_EINT */ | |
1247 | #define WM8904_MIC_DET_EINT_MASK 0x0001 /* MIC_DET_EINT */ | |
1248 | #define WM8904_MIC_DET_EINT_SHIFT 0 /* MIC_DET_EINT */ | |
1249 | #define WM8904_MIC_DET_EINT_WIDTH 1 /* MIC_DET_EINT */ | |
1250 | ||
1251 | /* | |
1252 | * R128 (0x80) - Interrupt Status Mask | |
1253 | */ | |
1254 | #define WM8904_IM_GPIO_BCLK_EINT 0x0200 /* IM_GPIO_BCLK_EINT */ | |
1255 | #define WM8904_IM_GPIO_BCLK_EINT_MASK 0x0200 /* IM_GPIO_BCLK_EINT */ | |
1256 | #define WM8904_IM_GPIO_BCLK_EINT_SHIFT 9 /* IM_GPIO_BCLK_EINT */ | |
1257 | #define WM8904_IM_GPIO_BCLK_EINT_WIDTH 1 /* IM_GPIO_BCLK_EINT */ | |
1258 | #define WM8904_IM_WSEQ_EINT 0x0100 /* IM_WSEQ_EINT */ | |
1259 | #define WM8904_IM_WSEQ_EINT_MASK 0x0100 /* IM_WSEQ_EINT */ | |
1260 | #define WM8904_IM_WSEQ_EINT_SHIFT 8 /* IM_WSEQ_EINT */ | |
1261 | #define WM8904_IM_WSEQ_EINT_WIDTH 1 /* IM_WSEQ_EINT */ | |
1262 | #define WM8904_IM_GPIO3_EINT 0x0080 /* IM_GPIO3_EINT */ | |
1263 | #define WM8904_IM_GPIO3_EINT_MASK 0x0080 /* IM_GPIO3_EINT */ | |
1264 | #define WM8904_IM_GPIO3_EINT_SHIFT 7 /* IM_GPIO3_EINT */ | |
1265 | #define WM8904_IM_GPIO3_EINT_WIDTH 1 /* IM_GPIO3_EINT */ | |
1266 | #define WM8904_IM_GPIO2_EINT 0x0040 /* IM_GPIO2_EINT */ | |
1267 | #define WM8904_IM_GPIO2_EINT_MASK 0x0040 /* IM_GPIO2_EINT */ | |
1268 | #define WM8904_IM_GPIO2_EINT_SHIFT 6 /* IM_GPIO2_EINT */ | |
1269 | #define WM8904_IM_GPIO2_EINT_WIDTH 1 /* IM_GPIO2_EINT */ | |
1270 | #define WM8904_IM_GPIO1_EINT 0x0020 /* IM_GPIO1_EINT */ | |
1271 | #define WM8904_IM_GPIO1_EINT_MASK 0x0020 /* IM_GPIO1_EINT */ | |
1272 | #define WM8904_IM_GPIO1_EINT_SHIFT 5 /* IM_GPIO1_EINT */ | |
1273 | #define WM8904_IM_GPIO1_EINT_WIDTH 1 /* IM_GPIO1_EINT */ | |
1274 | #define WM8904_IM_GPI8_EINT 0x0010 /* IM_GPI8_EINT */ | |
1275 | #define WM8904_IM_GPI8_EINT_MASK 0x0010 /* IM_GPI8_EINT */ | |
1276 | #define WM8904_IM_GPI8_EINT_SHIFT 4 /* IM_GPI8_EINT */ | |
1277 | #define WM8904_IM_GPI8_EINT_WIDTH 1 /* IM_GPI8_EINT */ | |
1278 | #define WM8904_IM_GPI7_EINT 0x0008 /* IM_GPI7_EINT */ | |
1279 | #define WM8904_IM_GPI7_EINT_MASK 0x0008 /* IM_GPI7_EINT */ | |
1280 | #define WM8904_IM_GPI7_EINT_SHIFT 3 /* IM_GPI7_EINT */ | |
1281 | #define WM8904_IM_GPI7_EINT_WIDTH 1 /* IM_GPI7_EINT */ | |
1282 | #define WM8904_IM_FLL_LOCK_EINT 0x0004 /* IM_FLL_LOCK_EINT */ | |
1283 | #define WM8904_IM_FLL_LOCK_EINT_MASK 0x0004 /* IM_FLL_LOCK_EINT */ | |
1284 | #define WM8904_IM_FLL_LOCK_EINT_SHIFT 2 /* IM_FLL_LOCK_EINT */ | |
1285 | #define WM8904_IM_FLL_LOCK_EINT_WIDTH 1 /* IM_FLL_LOCK_EINT */ | |
1286 | #define WM8904_IM_MIC_SHRT_EINT 0x0002 /* IM_MIC_SHRT_EINT */ | |
1287 | #define WM8904_IM_MIC_SHRT_EINT_MASK 0x0002 /* IM_MIC_SHRT_EINT */ | |
1288 | #define WM8904_IM_MIC_SHRT_EINT_SHIFT 1 /* IM_MIC_SHRT_EINT */ | |
1289 | #define WM8904_IM_MIC_SHRT_EINT_WIDTH 1 /* IM_MIC_SHRT_EINT */ | |
1290 | #define WM8904_IM_MIC_DET_EINT 0x0001 /* IM_MIC_DET_EINT */ | |
1291 | #define WM8904_IM_MIC_DET_EINT_MASK 0x0001 /* IM_MIC_DET_EINT */ | |
1292 | #define WM8904_IM_MIC_DET_EINT_SHIFT 0 /* IM_MIC_DET_EINT */ | |
1293 | #define WM8904_IM_MIC_DET_EINT_WIDTH 1 /* IM_MIC_DET_EINT */ | |
1294 | ||
1295 | /* | |
1296 | * R129 (0x81) - Interrupt Polarity | |
1297 | */ | |
1298 | #define WM8904_GPIO_BCLK_EINT_POL 0x0200 /* GPIO_BCLK_EINT_POL */ | |
1299 | #define WM8904_GPIO_BCLK_EINT_POL_MASK 0x0200 /* GPIO_BCLK_EINT_POL */ | |
1300 | #define WM8904_GPIO_BCLK_EINT_POL_SHIFT 9 /* GPIO_BCLK_EINT_POL */ | |
1301 | #define WM8904_GPIO_BCLK_EINT_POL_WIDTH 1 /* GPIO_BCLK_EINT_POL */ | |
1302 | #define WM8904_WSEQ_EINT_POL 0x0100 /* WSEQ_EINT_POL */ | |
1303 | #define WM8904_WSEQ_EINT_POL_MASK 0x0100 /* WSEQ_EINT_POL */ | |
1304 | #define WM8904_WSEQ_EINT_POL_SHIFT 8 /* WSEQ_EINT_POL */ | |
1305 | #define WM8904_WSEQ_EINT_POL_WIDTH 1 /* WSEQ_EINT_POL */ | |
1306 | #define WM8904_GPIO3_EINT_POL 0x0080 /* GPIO3_EINT_POL */ | |
1307 | #define WM8904_GPIO3_EINT_POL_MASK 0x0080 /* GPIO3_EINT_POL */ | |
1308 | #define WM8904_GPIO3_EINT_POL_SHIFT 7 /* GPIO3_EINT_POL */ | |
1309 | #define WM8904_GPIO3_EINT_POL_WIDTH 1 /* GPIO3_EINT_POL */ | |
1310 | #define WM8904_GPIO2_EINT_POL 0x0040 /* GPIO2_EINT_POL */ | |
1311 | #define WM8904_GPIO2_EINT_POL_MASK 0x0040 /* GPIO2_EINT_POL */ | |
1312 | #define WM8904_GPIO2_EINT_POL_SHIFT 6 /* GPIO2_EINT_POL */ | |
1313 | #define WM8904_GPIO2_EINT_POL_WIDTH 1 /* GPIO2_EINT_POL */ | |
1314 | #define WM8904_GPIO1_EINT_POL 0x0020 /* GPIO1_EINT_POL */ | |
1315 | #define WM8904_GPIO1_EINT_POL_MASK 0x0020 /* GPIO1_EINT_POL */ | |
1316 | #define WM8904_GPIO1_EINT_POL_SHIFT 5 /* GPIO1_EINT_POL */ | |
1317 | #define WM8904_GPIO1_EINT_POL_WIDTH 1 /* GPIO1_EINT_POL */ | |
1318 | #define WM8904_GPI8_EINT_POL 0x0010 /* GPI8_EINT_POL */ | |
1319 | #define WM8904_GPI8_EINT_POL_MASK 0x0010 /* GPI8_EINT_POL */ | |
1320 | #define WM8904_GPI8_EINT_POL_SHIFT 4 /* GPI8_EINT_POL */ | |
1321 | #define WM8904_GPI8_EINT_POL_WIDTH 1 /* GPI8_EINT_POL */ | |
1322 | #define WM8904_GPI7_EINT_POL 0x0008 /* GPI7_EINT_POL */ | |
1323 | #define WM8904_GPI7_EINT_POL_MASK 0x0008 /* GPI7_EINT_POL */ | |
1324 | #define WM8904_GPI7_EINT_POL_SHIFT 3 /* GPI7_EINT_POL */ | |
1325 | #define WM8904_GPI7_EINT_POL_WIDTH 1 /* GPI7_EINT_POL */ | |
1326 | #define WM8904_FLL_LOCK_EINT_POL 0x0004 /* FLL_LOCK_EINT_POL */ | |
1327 | #define WM8904_FLL_LOCK_EINT_POL_MASK 0x0004 /* FLL_LOCK_EINT_POL */ | |
1328 | #define WM8904_FLL_LOCK_EINT_POL_SHIFT 2 /* FLL_LOCK_EINT_POL */ | |
1329 | #define WM8904_FLL_LOCK_EINT_POL_WIDTH 1 /* FLL_LOCK_EINT_POL */ | |
1330 | #define WM8904_MIC_SHRT_EINT_POL 0x0002 /* MIC_SHRT_EINT_POL */ | |
1331 | #define WM8904_MIC_SHRT_EINT_POL_MASK 0x0002 /* MIC_SHRT_EINT_POL */ | |
1332 | #define WM8904_MIC_SHRT_EINT_POL_SHIFT 1 /* MIC_SHRT_EINT_POL */ | |
1333 | #define WM8904_MIC_SHRT_EINT_POL_WIDTH 1 /* MIC_SHRT_EINT_POL */ | |
1334 | #define WM8904_MIC_DET_EINT_POL 0x0001 /* MIC_DET_EINT_POL */ | |
1335 | #define WM8904_MIC_DET_EINT_POL_MASK 0x0001 /* MIC_DET_EINT_POL */ | |
1336 | #define WM8904_MIC_DET_EINT_POL_SHIFT 0 /* MIC_DET_EINT_POL */ | |
1337 | #define WM8904_MIC_DET_EINT_POL_WIDTH 1 /* MIC_DET_EINT_POL */ | |
1338 | ||
1339 | /* | |
1340 | * R130 (0x82) - Interrupt Debounce | |
1341 | */ | |
1342 | #define WM8904_GPIO_BCLK_EINT_DB 0x0200 /* GPIO_BCLK_EINT_DB */ | |
1343 | #define WM8904_GPIO_BCLK_EINT_DB_MASK 0x0200 /* GPIO_BCLK_EINT_DB */ | |
1344 | #define WM8904_GPIO_BCLK_EINT_DB_SHIFT 9 /* GPIO_BCLK_EINT_DB */ | |
1345 | #define WM8904_GPIO_BCLK_EINT_DB_WIDTH 1 /* GPIO_BCLK_EINT_DB */ | |
1346 | #define WM8904_WSEQ_EINT_DB 0x0100 /* WSEQ_EINT_DB */ | |
1347 | #define WM8904_WSEQ_EINT_DB_MASK 0x0100 /* WSEQ_EINT_DB */ | |
1348 | #define WM8904_WSEQ_EINT_DB_SHIFT 8 /* WSEQ_EINT_DB */ | |
1349 | #define WM8904_WSEQ_EINT_DB_WIDTH 1 /* WSEQ_EINT_DB */ | |
1350 | #define WM8904_GPIO3_EINT_DB 0x0080 /* GPIO3_EINT_DB */ | |
1351 | #define WM8904_GPIO3_EINT_DB_MASK 0x0080 /* GPIO3_EINT_DB */ | |
1352 | #define WM8904_GPIO3_EINT_DB_SHIFT 7 /* GPIO3_EINT_DB */ | |
1353 | #define WM8904_GPIO3_EINT_DB_WIDTH 1 /* GPIO3_EINT_DB */ | |
1354 | #define WM8904_GPIO2_EINT_DB 0x0040 /* GPIO2_EINT_DB */ | |
1355 | #define WM8904_GPIO2_EINT_DB_MASK 0x0040 /* GPIO2_EINT_DB */ | |
1356 | #define WM8904_GPIO2_EINT_DB_SHIFT 6 /* GPIO2_EINT_DB */ | |
1357 | #define WM8904_GPIO2_EINT_DB_WIDTH 1 /* GPIO2_EINT_DB */ | |
1358 | #define WM8904_GPIO1_EINT_DB 0x0020 /* GPIO1_EINT_DB */ | |
1359 | #define WM8904_GPIO1_EINT_DB_MASK 0x0020 /* GPIO1_EINT_DB */ | |
1360 | #define WM8904_GPIO1_EINT_DB_SHIFT 5 /* GPIO1_EINT_DB */ | |
1361 | #define WM8904_GPIO1_EINT_DB_WIDTH 1 /* GPIO1_EINT_DB */ | |
1362 | #define WM8904_GPI8_EINT_DB 0x0010 /* GPI8_EINT_DB */ | |
1363 | #define WM8904_GPI8_EINT_DB_MASK 0x0010 /* GPI8_EINT_DB */ | |
1364 | #define WM8904_GPI8_EINT_DB_SHIFT 4 /* GPI8_EINT_DB */ | |
1365 | #define WM8904_GPI8_EINT_DB_WIDTH 1 /* GPI8_EINT_DB */ | |
1366 | #define WM8904_GPI7_EINT_DB 0x0008 /* GPI7_EINT_DB */ | |
1367 | #define WM8904_GPI7_EINT_DB_MASK 0x0008 /* GPI7_EINT_DB */ | |
1368 | #define WM8904_GPI7_EINT_DB_SHIFT 3 /* GPI7_EINT_DB */ | |
1369 | #define WM8904_GPI7_EINT_DB_WIDTH 1 /* GPI7_EINT_DB */ | |
1370 | #define WM8904_FLL_LOCK_EINT_DB 0x0004 /* FLL_LOCK_EINT_DB */ | |
1371 | #define WM8904_FLL_LOCK_EINT_DB_MASK 0x0004 /* FLL_LOCK_EINT_DB */ | |
1372 | #define WM8904_FLL_LOCK_EINT_DB_SHIFT 2 /* FLL_LOCK_EINT_DB */ | |
1373 | #define WM8904_FLL_LOCK_EINT_DB_WIDTH 1 /* FLL_LOCK_EINT_DB */ | |
1374 | #define WM8904_MIC_SHRT_EINT_DB 0x0002 /* MIC_SHRT_EINT_DB */ | |
1375 | #define WM8904_MIC_SHRT_EINT_DB_MASK 0x0002 /* MIC_SHRT_EINT_DB */ | |
1376 | #define WM8904_MIC_SHRT_EINT_DB_SHIFT 1 /* MIC_SHRT_EINT_DB */ | |
1377 | #define WM8904_MIC_SHRT_EINT_DB_WIDTH 1 /* MIC_SHRT_EINT_DB */ | |
1378 | #define WM8904_MIC_DET_EINT_DB 0x0001 /* MIC_DET_EINT_DB */ | |
1379 | #define WM8904_MIC_DET_EINT_DB_MASK 0x0001 /* MIC_DET_EINT_DB */ | |
1380 | #define WM8904_MIC_DET_EINT_DB_SHIFT 0 /* MIC_DET_EINT_DB */ | |
1381 | #define WM8904_MIC_DET_EINT_DB_WIDTH 1 /* MIC_DET_EINT_DB */ | |
1382 | ||
1383 | /* | |
1384 | * R134 (0x86) - EQ1 | |
1385 | */ | |
1386 | #define WM8904_EQ_ENA 0x0001 /* EQ_ENA */ | |
1387 | #define WM8904_EQ_ENA_MASK 0x0001 /* EQ_ENA */ | |
1388 | #define WM8904_EQ_ENA_SHIFT 0 /* EQ_ENA */ | |
1389 | #define WM8904_EQ_ENA_WIDTH 1 /* EQ_ENA */ | |
1390 | ||
1391 | /* | |
1392 | * R135 (0x87) - EQ2 | |
1393 | */ | |
1394 | #define WM8904_EQ_B1_GAIN_MASK 0x001F /* EQ_B1_GAIN - [4:0] */ | |
1395 | #define WM8904_EQ_B1_GAIN_SHIFT 0 /* EQ_B1_GAIN - [4:0] */ | |
1396 | #define WM8904_EQ_B1_GAIN_WIDTH 5 /* EQ_B1_GAIN - [4:0] */ | |
1397 | ||
1398 | /* | |
1399 | * R136 (0x88) - EQ3 | |
1400 | */ | |
1401 | #define WM8904_EQ_B2_GAIN_MASK 0x001F /* EQ_B2_GAIN - [4:0] */ | |
1402 | #define WM8904_EQ_B2_GAIN_SHIFT 0 /* EQ_B2_GAIN - [4:0] */ | |
1403 | #define WM8904_EQ_B2_GAIN_WIDTH 5 /* EQ_B2_GAIN - [4:0] */ | |
1404 | ||
1405 | /* | |
1406 | * R137 (0x89) - EQ4 | |
1407 | */ | |
1408 | #define WM8904_EQ_B3_GAIN_MASK 0x001F /* EQ_B3_GAIN - [4:0] */ | |
1409 | #define WM8904_EQ_B3_GAIN_SHIFT 0 /* EQ_B3_GAIN - [4:0] */ | |
1410 | #define WM8904_EQ_B3_GAIN_WIDTH 5 /* EQ_B3_GAIN - [4:0] */ | |
1411 | ||
1412 | /* | |
1413 | * R138 (0x8A) - EQ5 | |
1414 | */ | |
1415 | #define WM8904_EQ_B4_GAIN_MASK 0x001F /* EQ_B4_GAIN - [4:0] */ | |
1416 | #define WM8904_EQ_B4_GAIN_SHIFT 0 /* EQ_B4_GAIN - [4:0] */ | |
1417 | #define WM8904_EQ_B4_GAIN_WIDTH 5 /* EQ_B4_GAIN - [4:0] */ | |
1418 | ||
1419 | /* | |
1420 | * R139 (0x8B) - EQ6 | |
1421 | */ | |
1422 | #define WM8904_EQ_B5_GAIN_MASK 0x001F /* EQ_B5_GAIN - [4:0] */ | |
1423 | #define WM8904_EQ_B5_GAIN_SHIFT 0 /* EQ_B5_GAIN - [4:0] */ | |
1424 | #define WM8904_EQ_B5_GAIN_WIDTH 5 /* EQ_B5_GAIN - [4:0] */ | |
1425 | ||
1426 | /* | |
1427 | * R140 (0x8C) - EQ7 | |
1428 | */ | |
1429 | #define WM8904_EQ_B1_A_MASK 0xFFFF /* EQ_B1_A - [15:0] */ | |
1430 | #define WM8904_EQ_B1_A_SHIFT 0 /* EQ_B1_A - [15:0] */ | |
1431 | #define WM8904_EQ_B1_A_WIDTH 16 /* EQ_B1_A - [15:0] */ | |
1432 | ||
1433 | /* | |
1434 | * R141 (0x8D) - EQ8 | |
1435 | */ | |
1436 | #define WM8904_EQ_B1_B_MASK 0xFFFF /* EQ_B1_B - [15:0] */ | |
1437 | #define WM8904_EQ_B1_B_SHIFT 0 /* EQ_B1_B - [15:0] */ | |
1438 | #define WM8904_EQ_B1_B_WIDTH 16 /* EQ_B1_B - [15:0] */ | |
1439 | ||
1440 | /* | |
1441 | * R142 (0x8E) - EQ9 | |
1442 | */ | |
1443 | #define WM8904_EQ_B1_PG_MASK 0xFFFF /* EQ_B1_PG - [15:0] */ | |
1444 | #define WM8904_EQ_B1_PG_SHIFT 0 /* EQ_B1_PG - [15:0] */ | |
1445 | #define WM8904_EQ_B1_PG_WIDTH 16 /* EQ_B1_PG - [15:0] */ | |
1446 | ||
1447 | /* | |
1448 | * R143 (0x8F) - EQ10 | |
1449 | */ | |
1450 | #define WM8904_EQ_B2_A_MASK 0xFFFF /* EQ_B2_A - [15:0] */ | |
1451 | #define WM8904_EQ_B2_A_SHIFT 0 /* EQ_B2_A - [15:0] */ | |
1452 | #define WM8904_EQ_B2_A_WIDTH 16 /* EQ_B2_A - [15:0] */ | |
1453 | ||
1454 | /* | |
1455 | * R144 (0x90) - EQ11 | |
1456 | */ | |
1457 | #define WM8904_EQ_B2_B_MASK 0xFFFF /* EQ_B2_B - [15:0] */ | |
1458 | #define WM8904_EQ_B2_B_SHIFT 0 /* EQ_B2_B - [15:0] */ | |
1459 | #define WM8904_EQ_B2_B_WIDTH 16 /* EQ_B2_B - [15:0] */ | |
1460 | ||
1461 | /* | |
1462 | * R145 (0x91) - EQ12 | |
1463 | */ | |
1464 | #define WM8904_EQ_B2_C_MASK 0xFFFF /* EQ_B2_C - [15:0] */ | |
1465 | #define WM8904_EQ_B2_C_SHIFT 0 /* EQ_B2_C - [15:0] */ | |
1466 | #define WM8904_EQ_B2_C_WIDTH 16 /* EQ_B2_C - [15:0] */ | |
1467 | ||
1468 | /* | |
1469 | * R146 (0x92) - EQ13 | |
1470 | */ | |
1471 | #define WM8904_EQ_B2_PG_MASK 0xFFFF /* EQ_B2_PG - [15:0] */ | |
1472 | #define WM8904_EQ_B2_PG_SHIFT 0 /* EQ_B2_PG - [15:0] */ | |
1473 | #define WM8904_EQ_B2_PG_WIDTH 16 /* EQ_B2_PG - [15:0] */ | |
1474 | ||
1475 | /* | |
1476 | * R147 (0x93) - EQ14 | |
1477 | */ | |
1478 | #define WM8904_EQ_B3_A_MASK 0xFFFF /* EQ_B3_A - [15:0] */ | |
1479 | #define WM8904_EQ_B3_A_SHIFT 0 /* EQ_B3_A - [15:0] */ | |
1480 | #define WM8904_EQ_B3_A_WIDTH 16 /* EQ_B3_A - [15:0] */ | |
1481 | ||
1482 | /* | |
1483 | * R148 (0x94) - EQ15 | |
1484 | */ | |
1485 | #define WM8904_EQ_B3_B_MASK 0xFFFF /* EQ_B3_B - [15:0] */ | |
1486 | #define WM8904_EQ_B3_B_SHIFT 0 /* EQ_B3_B - [15:0] */ | |
1487 | #define WM8904_EQ_B3_B_WIDTH 16 /* EQ_B3_B - [15:0] */ | |
1488 | ||
1489 | /* | |
1490 | * R149 (0x95) - EQ16 | |
1491 | */ | |
1492 | #define WM8904_EQ_B3_C_MASK 0xFFFF /* EQ_B3_C - [15:0] */ | |
1493 | #define WM8904_EQ_B3_C_SHIFT 0 /* EQ_B3_C - [15:0] */ | |
1494 | #define WM8904_EQ_B3_C_WIDTH 16 /* EQ_B3_C - [15:0] */ | |
1495 | ||
1496 | /* | |
1497 | * R150 (0x96) - EQ17 | |
1498 | */ | |
1499 | #define WM8904_EQ_B3_PG_MASK 0xFFFF /* EQ_B3_PG - [15:0] */ | |
1500 | #define WM8904_EQ_B3_PG_SHIFT 0 /* EQ_B3_PG - [15:0] */ | |
1501 | #define WM8904_EQ_B3_PG_WIDTH 16 /* EQ_B3_PG - [15:0] */ | |
1502 | ||
1503 | /* | |
1504 | * R151 (0x97) - EQ18 | |
1505 | */ | |
1506 | #define WM8904_EQ_B4_A_MASK 0xFFFF /* EQ_B4_A - [15:0] */ | |
1507 | #define WM8904_EQ_B4_A_SHIFT 0 /* EQ_B4_A - [15:0] */ | |
1508 | #define WM8904_EQ_B4_A_WIDTH 16 /* EQ_B4_A - [15:0] */ | |
1509 | ||
1510 | /* | |
1511 | * R152 (0x98) - EQ19 | |
1512 | */ | |
1513 | #define WM8904_EQ_B4_B_MASK 0xFFFF /* EQ_B4_B - [15:0] */ | |
1514 | #define WM8904_EQ_B4_B_SHIFT 0 /* EQ_B4_B - [15:0] */ | |
1515 | #define WM8904_EQ_B4_B_WIDTH 16 /* EQ_B4_B - [15:0] */ | |
1516 | ||
1517 | /* | |
1518 | * R153 (0x99) - EQ20 | |
1519 | */ | |
1520 | #define WM8904_EQ_B4_C_MASK 0xFFFF /* EQ_B4_C - [15:0] */ | |
1521 | #define WM8904_EQ_B4_C_SHIFT 0 /* EQ_B4_C - [15:0] */ | |
1522 | #define WM8904_EQ_B4_C_WIDTH 16 /* EQ_B4_C - [15:0] */ | |
1523 | ||
1524 | /* | |
1525 | * R154 (0x9A) - EQ21 | |
1526 | */ | |
1527 | #define WM8904_EQ_B4_PG_MASK 0xFFFF /* EQ_B4_PG - [15:0] */ | |
1528 | #define WM8904_EQ_B4_PG_SHIFT 0 /* EQ_B4_PG - [15:0] */ | |
1529 | #define WM8904_EQ_B4_PG_WIDTH 16 /* EQ_B4_PG - [15:0] */ | |
1530 | ||
1531 | /* | |
1532 | * R155 (0x9B) - EQ22 | |
1533 | */ | |
1534 | #define WM8904_EQ_B5_A_MASK 0xFFFF /* EQ_B5_A - [15:0] */ | |
1535 | #define WM8904_EQ_B5_A_SHIFT 0 /* EQ_B5_A - [15:0] */ | |
1536 | #define WM8904_EQ_B5_A_WIDTH 16 /* EQ_B5_A - [15:0] */ | |
1537 | ||
1538 | /* | |
1539 | * R156 (0x9C) - EQ23 | |
1540 | */ | |
1541 | #define WM8904_EQ_B5_B_MASK 0xFFFF /* EQ_B5_B - [15:0] */ | |
1542 | #define WM8904_EQ_B5_B_SHIFT 0 /* EQ_B5_B - [15:0] */ | |
1543 | #define WM8904_EQ_B5_B_WIDTH 16 /* EQ_B5_B - [15:0] */ | |
1544 | ||
1545 | /* | |
1546 | * R157 (0x9D) - EQ24 | |
1547 | */ | |
1548 | #define WM8904_EQ_B5_PG_MASK 0xFFFF /* EQ_B5_PG - [15:0] */ | |
1549 | #define WM8904_EQ_B5_PG_SHIFT 0 /* EQ_B5_PG - [15:0] */ | |
1550 | #define WM8904_EQ_B5_PG_WIDTH 16 /* EQ_B5_PG - [15:0] */ | |
1551 | ||
1552 | /* | |
1553 | * R161 (0xA1) - Control Interface Test 1 | |
1554 | */ | |
1555 | #define WM8904_USER_KEY 0x0002 /* USER_KEY */ | |
1556 | #define WM8904_USER_KEY_MASK 0x0002 /* USER_KEY */ | |
1557 | #define WM8904_USER_KEY_SHIFT 1 /* USER_KEY */ | |
1558 | #define WM8904_USER_KEY_WIDTH 1 /* USER_KEY */ | |
1559 | ||
9b85fc90 MB |
1560 | /* |
1561 | * R198 (0xC6) - ADC Test 0 | |
1562 | */ | |
1563 | #define WM8904_ADC_128_OSR_TST_MODE 0x0004 /* ADC_128_OSR_TST_MODE */ | |
1564 | #define WM8904_ADC_128_OSR_TST_MODE_SHIFT 2 /* ADC_128_OSR_TST_MODE */ | |
1565 | #define WM8904_ADC_128_OSR_TST_MODE_WIDTH 1 /* ADC_128_OSR_TST_MODE */ | |
1566 | #define WM8904_ADC_BIASX1P5 0x0001 /* ADC_BIASX1P5 */ | |
1567 | #define WM8904_ADC_BIASX1P5_SHIFT 0 /* ADC_BIASX1P5 */ | |
1568 | #define WM8904_ADC_BIASX1P5_WIDTH 1 /* ADC_BIASX1P5 */ | |
1569 | ||
a91eb199 MB |
1570 | /* |
1571 | * R204 (0xCC) - Analogue Output Bias 0 | |
1572 | */ | |
1573 | #define WM8904_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */ | |
1574 | #define WM8904_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */ | |
1575 | #define WM8904_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */ | |
1576 | ||
1577 | /* | |
1578 | * R247 (0xF7) - FLL NCO Test 0 | |
1579 | */ | |
1580 | #define WM8904_FLL_FRC_NCO 0x0001 /* FLL_FRC_NCO */ | |
1581 | #define WM8904_FLL_FRC_NCO_MASK 0x0001 /* FLL_FRC_NCO */ | |
1582 | #define WM8904_FLL_FRC_NCO_SHIFT 0 /* FLL_FRC_NCO */ | |
1583 | #define WM8904_FLL_FRC_NCO_WIDTH 1 /* FLL_FRC_NCO */ | |
1584 | ||
1585 | /* | |
1586 | * R248 (0xF8) - FLL NCO Test 1 | |
1587 | */ | |
1588 | #define WM8904_FLL_FRC_NCO_VAL_MASK 0x003F /* FLL_FRC_NCO_VAL - [5:0] */ | |
1589 | #define WM8904_FLL_FRC_NCO_VAL_SHIFT 0 /* FLL_FRC_NCO_VAL - [5:0] */ | |
1590 | #define WM8904_FLL_FRC_NCO_VAL_WIDTH 6 /* FLL_FRC_NCO_VAL - [5:0] */ | |
1591 | ||
1592 | #endif |