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ASoC: Support edge triggered IRQs for WM8915
[deliverable/linux.git] / sound / soc / codecs / wm8915.c
CommitLineData
c93993ac
MB		 1/*
2 * wm8915.c - WM8915 audio codec interface
3 *
4 * Copyright 2011 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/completion.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
c93993ac
MB		 22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <linux/workqueue.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <sound/wm8915.h>
35#include "wm8915.h"
36
37#define WM8915_AIFS 2
38
39#define HPOUT1L 1
40#define HPOUT1R 2
41#define HPOUT2L 4
42#define HPOUT2R 8
43
44#define WM8915_NUM_SUPPLIES 6
45static const char *wm8915_supply_names[WM8915_NUM_SUPPLIES] = {
46 "DCVDD",
47 "DBVDD",
48 "AVDD1",
49 "AVDD2",
50 "CPVDD",
51 "MICVDD",
52};
53
54struct wm8915_priv {
55 struct snd_soc_codec *codec;
56
57 int ldo1ena;
58
59 int sysclk;
60
61 int fll_src;
62 int fll_fref;
63 int fll_fout;
64
65 struct completion fll_lock;
66
67 u16 dcs_pending;
68 struct completion dcs_done;
69
70 u16 hpout_ena;
71 u16 hpout_pending;
72
73 struct regulator_bulk_data supplies[WM8915_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8915_NUM_SUPPLIES];
75
76 struct wm8915_pdata pdata;
77
78 int rx_rate[WM8915_AIFS];
79
80 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 wm8915_polarity_fn polarity_cb;
90
91#ifdef CONFIG_GPIOLIB
92 struct gpio_chip gpio_chip;
93#endif
94};
95
96/* We can't use the same notifier block for more than one supply and
97 * there's no way I can see to get from a callback to the caller
98 * except container_of().
99 */
100#define WM8915_REGULATOR_EVENT(n) \
101static int wm8915_regulator_event_##n(struct notifier_block *nb, \
102 unsigned long event, void *data) \
103{ \
104 struct wm8915_priv *wm8915 = container_of(nb, struct wm8915_priv, \
105 disable_nb[n]); \
106 if (event & REGULATOR_EVENT_DISABLE) { \
107 wm8915->codec->cache_sync = 1; \
108 } \
109 return 0; \
110}
111
112WM8915_REGULATOR_EVENT(0)
113WM8915_REGULATOR_EVENT(1)
114WM8915_REGULATOR_EVENT(2)
115WM8915_REGULATOR_EVENT(3)
116WM8915_REGULATOR_EVENT(4)
117WM8915_REGULATOR_EVENT(5)
118
119static const u16 wm8915_reg[WM8915_MAX_REGISTER] = {
120 [WM8915_SOFTWARE_RESET] = 0x8915,
121 [WM8915_POWER_MANAGEMENT_7] = 0x10,
122 [WM8915_DAC1_HPOUT1_VOLUME] = 0x88,
123 [WM8915_DAC2_HPOUT2_VOLUME] = 0x88,
124 [WM8915_DAC1_LEFT_VOLUME] = 0x2c0,
125 [WM8915_DAC1_RIGHT_VOLUME] = 0x2c0,
126 [WM8915_DAC2_LEFT_VOLUME] = 0x2c0,
127 [WM8915_DAC2_RIGHT_VOLUME] = 0x2c0,
128 [WM8915_OUTPUT1_LEFT_VOLUME] = 0x80,
129 [WM8915_OUTPUT1_RIGHT_VOLUME] = 0x80,
130 [WM8915_OUTPUT2_LEFT_VOLUME] = 0x80,
131 [WM8915_OUTPUT2_RIGHT_VOLUME] = 0x80,
132 [WM8915_MICBIAS_1] = 0x39,
133 [WM8915_MICBIAS_2] = 0x39,
134 [WM8915_LDO_1] = 0x3,
135 [WM8915_LDO_2] = 0x13,
136 [WM8915_ACCESSORY_DETECT_MODE_1] = 0x4,
137 [WM8915_HEADPHONE_DETECT_1] = 0x20,
138 [WM8915_MIC_DETECT_1] = 0x7600,
139 [WM8915_MIC_DETECT_2] = 0xbf,
140 [WM8915_CHARGE_PUMP_1] = 0x1f25,
141 [WM8915_CHARGE_PUMP_2] = 0xab19,
142 [WM8915_DC_SERVO_5] = 0x2a2a,
143 [WM8915_CONTROL_INTERFACE_1] = 0x8004,
144 [WM8915_CLOCKING_1] = 0x10,
145 [WM8915_AIF_RATE] = 0x83,
146 [WM8915_FLL_CONTROL_4] = 0x5dc0,
147 [WM8915_FLL_CONTROL_5] = 0xc84,
148 [WM8915_FLL_EFS_2] = 0x2,
149 [WM8915_AIF1_TX_LRCLK_1] = 0x80,
150 [WM8915_AIF1_TX_LRCLK_2] = 0x8,
151 [WM8915_AIF1_RX_LRCLK_1] = 0x80,
152 [WM8915_AIF1TX_DATA_CONFIGURATION_1] = 0x1818,
153 [WM8915_AIF1RX_DATA_CONFIGURATION] = 0x1818,
154 [WM8915_AIF1TX_TEST] = 0x7,
155 [WM8915_AIF2_TX_LRCLK_1] = 0x80,
156 [WM8915_AIF2_TX_LRCLK_2] = 0x8,
157 [WM8915_AIF2_RX_LRCLK_1] = 0x80,
158 [WM8915_AIF2TX_DATA_CONFIGURATION_1] = 0x1818,
159 [WM8915_AIF2RX_DATA_CONFIGURATION] = 0x1818,
160 [WM8915_AIF2TX_TEST] = 0x1,
161 [WM8915_DSP1_TX_LEFT_VOLUME] = 0xc0,
162 [WM8915_DSP1_TX_RIGHT_VOLUME] = 0xc0,
163 [WM8915_DSP1_RX_LEFT_VOLUME] = 0xc0,
164 [WM8915_DSP1_RX_RIGHT_VOLUME] = 0xc0,
165 [WM8915_DSP1_TX_FILTERS] = 0x2000,
166 [WM8915_DSP1_RX_FILTERS_1] = 0x200,
167 [WM8915_DSP1_RX_FILTERS_2] = 0x10,
168 [WM8915_DSP1_DRC_1] = 0x98,
169 [WM8915_DSP1_DRC_2] = 0x845,
170 [WM8915_DSP1_RX_EQ_GAINS_1] = 0x6318,
171 [WM8915_DSP1_RX_EQ_GAINS_2] = 0x6300,
172 [WM8915_DSP1_RX_EQ_BAND_1_A] = 0xfca,
173 [WM8915_DSP1_RX_EQ_BAND_1_B] = 0x400,
174 [WM8915_DSP1_RX_EQ_BAND_1_PG] = 0xd8,
175 [WM8915_DSP1_RX_EQ_BAND_2_A] = 0x1eb5,
176 [WM8915_DSP1_RX_EQ_BAND_2_B] = 0xf145,
177 [WM8915_DSP1_RX_EQ_BAND_2_C] = 0xb75,
178 [WM8915_DSP1_RX_EQ_BAND_2_PG] = 0x1c5,
179 [WM8915_DSP1_RX_EQ_BAND_3_A] = 0x1c58,
180 [WM8915_DSP1_RX_EQ_BAND_3_B] = 0xf373,
181 [WM8915_DSP1_RX_EQ_BAND_3_C] = 0xa54,
182 [WM8915_DSP1_RX_EQ_BAND_3_PG] = 0x558,
183 [WM8915_DSP1_RX_EQ_BAND_4_A] = 0x168e,
184 [WM8915_DSP1_RX_EQ_BAND_4_B] = 0xf829,
185 [WM8915_DSP1_RX_EQ_BAND_4_C] = 0x7ad,
186 [WM8915_DSP1_RX_EQ_BAND_4_PG] = 0x1103,
187 [WM8915_DSP1_RX_EQ_BAND_5_A] = 0x564,
188 [WM8915_DSP1_RX_EQ_BAND_5_B] = 0x559,
189 [WM8915_DSP1_RX_EQ_BAND_5_PG] = 0x4000,
190 [WM8915_DSP2_TX_LEFT_VOLUME] = 0xc0,
191 [WM8915_DSP2_TX_RIGHT_VOLUME] = 0xc0,
192 [WM8915_DSP2_RX_LEFT_VOLUME] = 0xc0,
193 [WM8915_DSP2_RX_RIGHT_VOLUME] = 0xc0,
194 [WM8915_DSP2_TX_FILTERS] = 0x2000,
195 [WM8915_DSP2_RX_FILTERS_1] = 0x200,
196 [WM8915_DSP2_RX_FILTERS_2] = 0x10,
197 [WM8915_DSP2_DRC_1] = 0x98,
198 [WM8915_DSP2_DRC_2] = 0x845,
199 [WM8915_DSP2_RX_EQ_GAINS_1] = 0x6318,
200 [WM8915_DSP2_RX_EQ_GAINS_2] = 0x6300,
201 [WM8915_DSP2_RX_EQ_BAND_1_A] = 0xfca,
202 [WM8915_DSP2_RX_EQ_BAND_1_B] = 0x400,
203 [WM8915_DSP2_RX_EQ_BAND_1_PG] = 0xd8,
204 [WM8915_DSP2_RX_EQ_BAND_2_A] = 0x1eb5,
205 [WM8915_DSP2_RX_EQ_BAND_2_B] = 0xf145,
206 [WM8915_DSP2_RX_EQ_BAND_2_C] = 0xb75,
207 [WM8915_DSP2_RX_EQ_BAND_2_PG] = 0x1c5,
208 [WM8915_DSP2_RX_EQ_BAND_3_A] = 0x1c58,
209 [WM8915_DSP2_RX_EQ_BAND_3_B] = 0xf373,
210 [WM8915_DSP2_RX_EQ_BAND_3_C] = 0xa54,
211 [WM8915_DSP2_RX_EQ_BAND_3_PG] = 0x558,
212 [WM8915_DSP2_RX_EQ_BAND_4_A] = 0x168e,
213 [WM8915_DSP2_RX_EQ_BAND_4_B] = 0xf829,
214 [WM8915_DSP2_RX_EQ_BAND_4_C] = 0x7ad,
215 [WM8915_DSP2_RX_EQ_BAND_4_PG] = 0x1103,
216 [WM8915_DSP2_RX_EQ_BAND_5_A] = 0x564,
217 [WM8915_DSP2_RX_EQ_BAND_5_B] = 0x559,
218 [WM8915_DSP2_RX_EQ_BAND_5_PG] = 0x4000,
219 [WM8915_OVERSAMPLING] = 0xd,
220 [WM8915_SIDETONE] = 0x1040,
221 [WM8915_GPIO_1] = 0xa101,
222 [WM8915_GPIO_2] = 0xa101,
223 [WM8915_GPIO_3] = 0xa101,
224 [WM8915_GPIO_4] = 0xa101,
225 [WM8915_GPIO_5] = 0xa101,
226 [WM8915_PULL_CONTROL_2] = 0x140,
227 [WM8915_INTERRUPT_STATUS_1_MASK] = 0x1f,
228 [WM8915_INTERRUPT_STATUS_2_MASK] = 0x1ecf,
229 [WM8915_RIGHT_PDM_SPEAKER] = 0x1,
230 [WM8915_PDM_SPEAKER_MUTE_SEQUENCE] = 0x69,
231 [WM8915_PDM_SPEAKER_VOLUME] = 0x66,
232 [WM8915_WRITE_SEQUENCER_0] = 0x1,
233 [WM8915_WRITE_SEQUENCER_1] = 0x1,
234 [WM8915_WRITE_SEQUENCER_3] = 0x6,
235 [WM8915_WRITE_SEQUENCER_4] = 0x40,
236 [WM8915_WRITE_SEQUENCER_5] = 0x1,
237 [WM8915_WRITE_SEQUENCER_6] = 0xf,
238 [WM8915_WRITE_SEQUENCER_7] = 0x6,
239 [WM8915_WRITE_SEQUENCER_8] = 0x1,
240 [WM8915_WRITE_SEQUENCER_9] = 0x3,
241 [WM8915_WRITE_SEQUENCER_10] = 0x104,
242 [WM8915_WRITE_SEQUENCER_12] = 0x60,
243 [WM8915_WRITE_SEQUENCER_13] = 0x11,
244 [WM8915_WRITE_SEQUENCER_14] = 0x401,
245 [WM8915_WRITE_SEQUENCER_16] = 0x50,
246 [WM8915_WRITE_SEQUENCER_17] = 0x3,
247 [WM8915_WRITE_SEQUENCER_18] = 0x100,
248 [WM8915_WRITE_SEQUENCER_20] = 0x51,
249 [WM8915_WRITE_SEQUENCER_21] = 0x3,
250 [WM8915_WRITE_SEQUENCER_22] = 0x104,
251 [WM8915_WRITE_SEQUENCER_23] = 0xa,
252 [WM8915_WRITE_SEQUENCER_24] = 0x60,
253 [WM8915_WRITE_SEQUENCER_25] = 0x3b,
254 [WM8915_WRITE_SEQUENCER_26] = 0x502,
255 [WM8915_WRITE_SEQUENCER_27] = 0x100,
256 [WM8915_WRITE_SEQUENCER_28] = 0x2fff,
257 [WM8915_WRITE_SEQUENCER_32] = 0x2fff,
258 [WM8915_WRITE_SEQUENCER_36] = 0x2fff,
259 [WM8915_WRITE_SEQUENCER_40] = 0x2fff,
260 [WM8915_WRITE_SEQUENCER_44] = 0x2fff,
261 [WM8915_WRITE_SEQUENCER_48] = 0x2fff,
262 [WM8915_WRITE_SEQUENCER_52] = 0x2fff,
263 [WM8915_WRITE_SEQUENCER_56] = 0x2fff,
264 [WM8915_WRITE_SEQUENCER_60] = 0x2fff,
265 [WM8915_WRITE_SEQUENCER_64] = 0x1,
266 [WM8915_WRITE_SEQUENCER_65] = 0x1,
267 [WM8915_WRITE_SEQUENCER_67] = 0x6,
268 [WM8915_WRITE_SEQUENCER_68] = 0x40,
269 [WM8915_WRITE_SEQUENCER_69] = 0x1,
270 [WM8915_WRITE_SEQUENCER_70] = 0xf,
271 [WM8915_WRITE_SEQUENCER_71] = 0x6,
272 [WM8915_WRITE_SEQUENCER_72] = 0x1,
273 [WM8915_WRITE_SEQUENCER_73] = 0x3,
274 [WM8915_WRITE_SEQUENCER_74] = 0x104,
275 [WM8915_WRITE_SEQUENCER_76] = 0x60,
276 [WM8915_WRITE_SEQUENCER_77] = 0x11,
277 [WM8915_WRITE_SEQUENCER_78] = 0x401,
278 [WM8915_WRITE_SEQUENCER_80] = 0x50,
279 [WM8915_WRITE_SEQUENCER_81] = 0x3,
280 [WM8915_WRITE_SEQUENCER_82] = 0x100,
281 [WM8915_WRITE_SEQUENCER_84] = 0x60,
282 [WM8915_WRITE_SEQUENCER_85] = 0x3b,
283 [WM8915_WRITE_SEQUENCER_86] = 0x502,
284 [WM8915_WRITE_SEQUENCER_87] = 0x100,
285 [WM8915_WRITE_SEQUENCER_88] = 0x2fff,
286 [WM8915_WRITE_SEQUENCER_92] = 0x2fff,
287 [WM8915_WRITE_SEQUENCER_96] = 0x2fff,
288 [WM8915_WRITE_SEQUENCER_100] = 0x2fff,
289 [WM8915_WRITE_SEQUENCER_104] = 0x2fff,
290 [WM8915_WRITE_SEQUENCER_108] = 0x2fff,
291 [WM8915_WRITE_SEQUENCER_112] = 0x2fff,
292 [WM8915_WRITE_SEQUENCER_116] = 0x2fff,
293 [WM8915_WRITE_SEQUENCER_120] = 0x2fff,
294 [WM8915_WRITE_SEQUENCER_124] = 0x2fff,
295 [WM8915_WRITE_SEQUENCER_128] = 0x1,
296 [WM8915_WRITE_SEQUENCER_129] = 0x1,
297 [WM8915_WRITE_SEQUENCER_131] = 0x6,
298 [WM8915_WRITE_SEQUENCER_132] = 0x40,
299 [WM8915_WRITE_SEQUENCER_133] = 0x1,
300 [WM8915_WRITE_SEQUENCER_134] = 0xf,
301 [WM8915_WRITE_SEQUENCER_135] = 0x6,
302 [WM8915_WRITE_SEQUENCER_136] = 0x1,
303 [WM8915_WRITE_SEQUENCER_137] = 0x3,
304 [WM8915_WRITE_SEQUENCER_138] = 0x106,
305 [WM8915_WRITE_SEQUENCER_140] = 0x61,
306 [WM8915_WRITE_SEQUENCER_141] = 0x11,
307 [WM8915_WRITE_SEQUENCER_142] = 0x401,
308 [WM8915_WRITE_SEQUENCER_144] = 0x50,
309 [WM8915_WRITE_SEQUENCER_145] = 0x3,
310 [WM8915_WRITE_SEQUENCER_146] = 0x102,
311 [WM8915_WRITE_SEQUENCER_148] = 0x51,
312 [WM8915_WRITE_SEQUENCER_149] = 0x3,
313 [WM8915_WRITE_SEQUENCER_150] = 0x106,
314 [WM8915_WRITE_SEQUENCER_151] = 0xa,
315 [WM8915_WRITE_SEQUENCER_152] = 0x61,
316 [WM8915_WRITE_SEQUENCER_153] = 0x3b,
317 [WM8915_WRITE_SEQUENCER_154] = 0x502,
318 [WM8915_WRITE_SEQUENCER_155] = 0x100,
319 [WM8915_WRITE_SEQUENCER_156] = 0x2fff,
320 [WM8915_WRITE_SEQUENCER_160] = 0x2fff,
321 [WM8915_WRITE_SEQUENCER_164] = 0x2fff,
322 [WM8915_WRITE_SEQUENCER_168] = 0x2fff,
323 [WM8915_WRITE_SEQUENCER_172] = 0x2fff,
324 [WM8915_WRITE_SEQUENCER_176] = 0x2fff,
325 [WM8915_WRITE_SEQUENCER_180] = 0x2fff,
326 [WM8915_WRITE_SEQUENCER_184] = 0x2fff,
327 [WM8915_WRITE_SEQUENCER_188] = 0x2fff,
328 [WM8915_WRITE_SEQUENCER_192] = 0x1,
329 [WM8915_WRITE_SEQUENCER_193] = 0x1,
330 [WM8915_WRITE_SEQUENCER_195] = 0x6,
331 [WM8915_WRITE_SEQUENCER_196] = 0x40,
332 [WM8915_WRITE_SEQUENCER_197] = 0x1,
333 [WM8915_WRITE_SEQUENCER_198] = 0xf,
334 [WM8915_WRITE_SEQUENCER_199] = 0x6,
335 [WM8915_WRITE_SEQUENCER_200] = 0x1,
336 [WM8915_WRITE_SEQUENCER_201] = 0x3,
337 [WM8915_WRITE_SEQUENCER_202] = 0x106,
338 [WM8915_WRITE_SEQUENCER_204] = 0x61,
339 [WM8915_WRITE_SEQUENCER_205] = 0x11,
340 [WM8915_WRITE_SEQUENCER_206] = 0x401,
341 [WM8915_WRITE_SEQUENCER_208] = 0x50,
342 [WM8915_WRITE_SEQUENCER_209] = 0x3,
343 [WM8915_WRITE_SEQUENCER_210] = 0x102,
344 [WM8915_WRITE_SEQUENCER_212] = 0x61,
345 [WM8915_WRITE_SEQUENCER_213] = 0x3b,
346 [WM8915_WRITE_SEQUENCER_214] = 0x502,
347 [WM8915_WRITE_SEQUENCER_215] = 0x100,
348 [WM8915_WRITE_SEQUENCER_216] = 0x2fff,
349 [WM8915_WRITE_SEQUENCER_220] = 0x2fff,
350 [WM8915_WRITE_SEQUENCER_224] = 0x2fff,
351 [WM8915_WRITE_SEQUENCER_228] = 0x2fff,
352 [WM8915_WRITE_SEQUENCER_232] = 0x2fff,
353 [WM8915_WRITE_SEQUENCER_236] = 0x2fff,
354 [WM8915_WRITE_SEQUENCER_240] = 0x2fff,
355 [WM8915_WRITE_SEQUENCER_244] = 0x2fff,
356 [WM8915_WRITE_SEQUENCER_248] = 0x2fff,
357 [WM8915_WRITE_SEQUENCER_252] = 0x2fff,
358 [WM8915_WRITE_SEQUENCER_256] = 0x60,
359 [WM8915_WRITE_SEQUENCER_258] = 0x601,
360 [WM8915_WRITE_SEQUENCER_260] = 0x50,
361 [WM8915_WRITE_SEQUENCER_262] = 0x100,
362 [WM8915_WRITE_SEQUENCER_264] = 0x1,
363 [WM8915_WRITE_SEQUENCER_266] = 0x104,
364 [WM8915_WRITE_SEQUENCER_267] = 0x100,
365 [WM8915_WRITE_SEQUENCER_268] = 0x2fff,
366 [WM8915_WRITE_SEQUENCER_272] = 0x2fff,
367 [WM8915_WRITE_SEQUENCER_276] = 0x2fff,
368 [WM8915_WRITE_SEQUENCER_280] = 0x2fff,
369 [WM8915_WRITE_SEQUENCER_284] = 0x2fff,
370 [WM8915_WRITE_SEQUENCER_288] = 0x2fff,
371 [WM8915_WRITE_SEQUENCER_292] = 0x2fff,
372 [WM8915_WRITE_SEQUENCER_296] = 0x2fff,
373 [WM8915_WRITE_SEQUENCER_300] = 0x2fff,
374 [WM8915_WRITE_SEQUENCER_304] = 0x2fff,
375 [WM8915_WRITE_SEQUENCER_308] = 0x2fff,
376 [WM8915_WRITE_SEQUENCER_312] = 0x2fff,
377 [WM8915_WRITE_SEQUENCER_316] = 0x2fff,
378 [WM8915_WRITE_SEQUENCER_320] = 0x61,
379 [WM8915_WRITE_SEQUENCER_322] = 0x601,
380 [WM8915_WRITE_SEQUENCER_324] = 0x50,
381 [WM8915_WRITE_SEQUENCER_326] = 0x102,
382 [WM8915_WRITE_SEQUENCER_328] = 0x1,
383 [WM8915_WRITE_SEQUENCER_330] = 0x106,
384 [WM8915_WRITE_SEQUENCER_331] = 0x100,
385 [WM8915_WRITE_SEQUENCER_332] = 0x2fff,
386 [WM8915_WRITE_SEQUENCER_336] = 0x2fff,
387 [WM8915_WRITE_SEQUENCER_340] = 0x2fff,
388 [WM8915_WRITE_SEQUENCER_344] = 0x2fff,
389 [WM8915_WRITE_SEQUENCER_348] = 0x2fff,
390 [WM8915_WRITE_SEQUENCER_352] = 0x2fff,
391 [WM8915_WRITE_SEQUENCER_356] = 0x2fff,
392 [WM8915_WRITE_SEQUENCER_360] = 0x2fff,
393 [WM8915_WRITE_SEQUENCER_364] = 0x2fff,
394 [WM8915_WRITE_SEQUENCER_368] = 0x2fff,
395 [WM8915_WRITE_SEQUENCER_372] = 0x2fff,
396 [WM8915_WRITE_SEQUENCER_376] = 0x2fff,
397 [WM8915_WRITE_SEQUENCER_380] = 0x2fff,
398 [WM8915_WRITE_SEQUENCER_384] = 0x60,
399 [WM8915_WRITE_SEQUENCER_386] = 0x601,
400 [WM8915_WRITE_SEQUENCER_388] = 0x61,
401 [WM8915_WRITE_SEQUENCER_390] = 0x601,
402 [WM8915_WRITE_SEQUENCER_392] = 0x50,
403 [WM8915_WRITE_SEQUENCER_394] = 0x300,
404 [WM8915_WRITE_SEQUENCER_396] = 0x1,
405 [WM8915_WRITE_SEQUENCER_398] = 0x304,
406 [WM8915_WRITE_SEQUENCER_400] = 0x40,
407 [WM8915_WRITE_SEQUENCER_402] = 0xf,
408 [WM8915_WRITE_SEQUENCER_404] = 0x1,
409 [WM8915_WRITE_SEQUENCER_407] = 0x100,
410};
411
412static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
413static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
414static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
415static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
416static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
417static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
418static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
419
420static const char *sidetone_hpf_text[] = {
421 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
422};
423
424static const struct soc_enum sidetone_hpf =
425 SOC_ENUM_SINGLE(WM8915_SIDETONE, 7, 6, sidetone_hpf_text);
426
427static const char *hpf_mode_text[] = {
428 "HiFi", "Custom", "Voice"
429};
430
431static const struct soc_enum dsp1tx_hpf_mode =
432 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 3, 3, hpf_mode_text);
433
434static const struct soc_enum dsp2tx_hpf_mode =
435 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 3, 3, hpf_mode_text);
436
437static const char *hpf_cutoff_text[] = {
438 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
439};
440
441static const struct soc_enum dsp1tx_hpf_cutoff =
442 SOC_ENUM_SINGLE(WM8915_DSP1_TX_FILTERS, 0, 7, hpf_cutoff_text);
443
444static const struct soc_enum dsp2tx_hpf_cutoff =
445 SOC_ENUM_SINGLE(WM8915_DSP2_TX_FILTERS, 0, 7, hpf_cutoff_text);
446
447static void wm8915_set_retune_mobile(struct snd_soc_codec *codec, int block)
448{
449 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
450 struct wm8915_pdata *pdata = &wm8915->pdata;
451 int base, best, best_val, save, i, cfg, iface;
452
453 if (!wm8915->num_retune_mobile_texts)
454 return;
455
456 switch (block) {
457 case 0:
458 base = WM8915_DSP1_RX_EQ_GAINS_1;
459 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
460 WM8915_DSP1RX_SRC)
461 iface = 1;
462 else
463 iface = 0;
464 break;
465 case 1:
466 base = WM8915_DSP1_RX_EQ_GAINS_2;
467 if (snd_soc_read(codec, WM8915_POWER_MANAGEMENT_8) &
468 WM8915_DSP2RX_SRC)
469 iface = 1;
470 else
471 iface = 0;
472 break;
473 default:
474 return;
475 }
476
477 /* Find the version of the currently selected configuration
478 * with the nearest sample rate. */
479 cfg = wm8915->retune_mobile_cfg[block];
480 best = 0;
481 best_val = INT_MAX;
482 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
483 if (strcmp(pdata->retune_mobile_cfgs[i].name,
484 wm8915->retune_mobile_texts[cfg]) == 0 &&
485 abs(pdata->retune_mobile_cfgs[i].rate
486 - wm8915->rx_rate[iface]) < best_val) {
487 best = i;
488 best_val = abs(pdata->retune_mobile_cfgs[i].rate
489 - wm8915->rx_rate[iface]);
490 }
491 }
492
493 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
494 block,
495 pdata->retune_mobile_cfgs[best].name,
496 pdata->retune_mobile_cfgs[best].rate,
497 wm8915->rx_rate[iface]);
498
499 /* The EQ will be disabled while reconfiguring it, remember the
500 * current configuration.
501 */
502 save = snd_soc_read(codec, base);
503 save &= WM8915_DSP1RX_EQ_ENA;
504
505 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
506 snd_soc_update_bits(codec, base + i, 0xffff,
507 pdata->retune_mobile_cfgs[best].regs[i]);
508
509 snd_soc_update_bits(codec, base, WM8915_DSP1RX_EQ_ENA, save);
510}
511
512/* Icky as hell but saves code duplication */
513static int wm8915_get_retune_mobile_block(const char *name)
514{
515 if (strcmp(name, "DSP1 EQ Mode") == 0)
516 return 0;
517 if (strcmp(name, "DSP2 EQ Mode") == 0)
518 return 1;
519 return -EINVAL;
520}
521
522static int wm8915_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
523 struct snd_ctl_elem_value *ucontrol)
524{
525 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
526 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
527 struct wm8915_pdata *pdata = &wm8915->pdata;
528 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
529 int value = ucontrol->value.integer.value[0];
530
531 if (block < 0)
532 return block;
533
534 if (value >= pdata->num_retune_mobile_cfgs)
535 return -EINVAL;
536
537 wm8915->retune_mobile_cfg[block] = value;
538
539 wm8915_set_retune_mobile(codec, block);
540
541 return 0;
542}
543
544static int wm8915_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
545 struct snd_ctl_elem_value *ucontrol)
546{
547 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
548 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
549 int block = wm8915_get_retune_mobile_block(kcontrol->id.name);
550
551 ucontrol->value.enumerated.item[0] = wm8915->retune_mobile_cfg[block];
552
553 return 0;
554}
555
556static const struct snd_kcontrol_new wm8915_snd_controls[] = {
557SOC_DOUBLE_R_TLV("Capture Volume", WM8915_LEFT_LINE_INPUT_VOLUME,
558 WM8915_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
559SOC_DOUBLE_R("Capture ZC Switch", WM8915_LEFT_LINE_INPUT_VOLUME,
560 WM8915_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
561
562SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8915_DAC1_MIXER_VOLUMES,
563 0, 5, 24, 0, sidetone_tlv),
564SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8915_DAC2_MIXER_VOLUMES,
565 0, 5, 24, 0, sidetone_tlv),
566SOC_SINGLE("Sidetone LPF Switch", WM8915_SIDETONE, 12, 1, 0),
567SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
568SOC_SINGLE("Sidetone HPF Switch", WM8915_SIDETONE, 6, 1, 0),
569
570SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8915_DSP1_TX_LEFT_VOLUME,
571 WM8915_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
572SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8915_DSP2_TX_LEFT_VOLUME,
573 WM8915_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574
575SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8915_DSP1_TX_FILTERS,
576 13, 1, 0),
577SOC_DOUBLE("DSP1 Capture HPF Switch", WM8915_DSP1_TX_FILTERS, 12, 11, 1, 0),
578SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
579SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
580
581SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8915_DSP2_TX_FILTERS,
582 13, 1, 0),
583SOC_DOUBLE("DSP2 Capture HPF Switch", WM8915_DSP2_TX_FILTERS, 12, 11, 1, 0),
584SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
585SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
586
587SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8915_DSP1_RX_LEFT_VOLUME,
588 WM8915_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
589SOC_SINGLE("DSP1 Playback Switch", WM8915_DSP1_RX_FILTERS_1, 9, 1, 1),
590
591SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8915_DSP2_RX_LEFT_VOLUME,
592 WM8915_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
593SOC_SINGLE("DSP2 Playback Switch", WM8915_DSP2_RX_FILTERS_1, 9, 1, 1),
594
595SOC_DOUBLE_R_TLV("DAC1 Volume", WM8915_DAC1_LEFT_VOLUME,
596 WM8915_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
597SOC_DOUBLE_R("DAC1 Switch", WM8915_DAC1_LEFT_VOLUME,
598 WM8915_DAC1_RIGHT_VOLUME, 9, 1, 1),
599
600SOC_DOUBLE_R_TLV("DAC2 Volume", WM8915_DAC2_LEFT_VOLUME,
601 WM8915_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
602SOC_DOUBLE_R("DAC2 Switch", WM8915_DAC2_LEFT_VOLUME,
603 WM8915_DAC2_RIGHT_VOLUME, 9, 1, 1),
604
605SOC_SINGLE("Speaker High Performance Switch", WM8915_OVERSAMPLING, 3, 1, 0),
606SOC_SINGLE("DMIC High Performance Switch", WM8915_OVERSAMPLING, 2, 1, 0),
607SOC_SINGLE("ADC High Performance Switch", WM8915_OVERSAMPLING, 1, 1, 0),
608SOC_SINGLE("DAC High Performance Switch", WM8915_OVERSAMPLING, 0, 1, 0),
609
610SOC_SINGLE("DAC Soft Mute Switch", WM8915_DAC_SOFTMUTE, 1, 1, 0),
611SOC_SINGLE("DAC Slow Soft Mute Switch", WM8915_DAC_SOFTMUTE, 0, 1, 0),
612
613SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8915_DAC1_HPOUT1_VOLUME, 0, 4,
614 8, 0, out_digital_tlv),
615SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8915_DAC2_HPOUT2_VOLUME, 0, 4,
616 8, 0, out_digital_tlv),
617
618SOC_DOUBLE_R_TLV("Output 1 Volume", WM8915_OUTPUT1_LEFT_VOLUME,
619 WM8915_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
620SOC_DOUBLE_R("Output 1 ZC Switch", WM8915_OUTPUT1_LEFT_VOLUME,
621 WM8915_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
622
623SOC_DOUBLE_R_TLV("Output 2 Volume", WM8915_OUTPUT2_LEFT_VOLUME,
624 WM8915_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
625SOC_DOUBLE_R("Output 2 ZC Switch", WM8915_OUTPUT2_LEFT_VOLUME,
626 WM8915_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
627
628SOC_DOUBLE_TLV("Speaker Volume", WM8915_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
629 spk_tlv),
630SOC_DOUBLE_R("Speaker Switch", WM8915_LEFT_PDM_SPEAKER,
631 WM8915_RIGHT_PDM_SPEAKER, 3, 1, 1),
632SOC_DOUBLE_R("Speaker ZC Switch", WM8915_LEFT_PDM_SPEAKER,
633 WM8915_RIGHT_PDM_SPEAKER, 2, 1, 0),
634
635SOC_SINGLE("DSP1 EQ Switch", WM8915_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
636SOC_SINGLE("DSP2 EQ Switch", WM8915_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
637};
638
639static const struct snd_kcontrol_new wm8915_eq_controls[] = {
640SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8915_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8915_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8915_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8915_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661};
662
663static int cp_event(struct snd_soc_dapm_widget *w,
664 struct snd_kcontrol *kcontrol, int event)
665{
666 switch (event) {
667 case SND_SOC_DAPM_POST_PMU:
668 msleep(5);
669 break;
670 default:
671 BUG();
672 return -EINVAL;
673 }
674
675 return 0;
676}
677
678static int rmv_short_event(struct snd_soc_dapm_widget *w,
679 struct snd_kcontrol *kcontrol, int event)
680{
681 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
682
683 /* Record which outputs we enabled */
684 switch (event) {
685 case SND_SOC_DAPM_PRE_PMD:
686 wm8915->hpout_pending &= ~w->shift;
687 break;
688 case SND_SOC_DAPM_PRE_PMU:
689 wm8915->hpout_pending |= w->shift;
690 break;
691 default:
692 BUG();
693 return -EINVAL;
694 }
695
696 return 0;
697}
698
699static void wait_for_dc_servo(struct snd_soc_codec *codec, u16 mask)
700{
701 struct i2c_client *i2c = to_i2c_client(codec->dev);
702 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
703 int i, ret;
704 unsigned long timeout = 200;
705
706 snd_soc_write(codec, WM8915_DC_SERVO_2, mask);
707
708 /* Use the interrupt if possible */
709 do {
710 if (i2c->irq) {
711 timeout = wait_for_completion_timeout(&wm8915->dcs_done,
712 msecs_to_jiffies(200));
713 if (timeout == 0)
714 dev_err(codec->dev, "DC servo timed out\n");
715
716 } else {
717 msleep(1);
718 if (--i) {
719 timeout = 0;
720 break;
721 }
722 }
723
724 ret = snd_soc_read(codec, WM8915_DC_SERVO_2);
725 dev_dbg(codec->dev, "DC servo state: %x\n", ret);
726 } while (ret & mask);
727
728 if (timeout == 0)
729 dev_err(codec->dev, "DC servo timed out for %x\n", mask);
730 else
731 dev_dbg(codec->dev, "DC servo complete for %x\n", mask);
732}
733
734static void wm8915_seq_notifier(struct snd_soc_dapm_context *dapm,
735 enum snd_soc_dapm_type event, int subseq)
736{
737 struct snd_soc_codec *codec = container_of(dapm,
738 struct snd_soc_codec, dapm);
739 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
740 u16 val, mask;
741
742 /* Complete any pending DC servo starts */
743 if (wm8915->dcs_pending) {
744 dev_dbg(codec->dev, "Starting DC servo for %x\n",
745 wm8915->dcs_pending);
746
747 /* Trigger a startup sequence */
748 wait_for_dc_servo(codec, wm8915->dcs_pending
749 << WM8915_DCS_TRIG_STARTUP_0_SHIFT);
750
751 wm8915->dcs_pending = 0;
752 }
753
754 if (wm8915->hpout_pending != wm8915->hpout_ena) {
755 dev_dbg(codec->dev, "Applying RMV_SHORTs %x->%x\n",
756 wm8915->hpout_ena, wm8915->hpout_pending);
757
758 val = 0;
759 mask = 0;
760 if (wm8915->hpout_pending & HPOUT1L) {
761 val |= WM8915_HPOUT1L_RMV_SHORT;
762 mask |= WM8915_HPOUT1L_RMV_SHORT;
763 } else {
764 mask |= WM8915_HPOUT1L_RMV_SHORT |
765 WM8915_HPOUT1L_OUTP |
766 WM8915_HPOUT1L_DLY;
767 }
768
769 if (wm8915->hpout_pending & HPOUT1R) {
770 val |= WM8915_HPOUT1R_RMV_SHORT;
771 mask |= WM8915_HPOUT1R_RMV_SHORT;
772 } else {
773 mask |= WM8915_HPOUT1R_RMV_SHORT |
774 WM8915_HPOUT1R_OUTP |
775 WM8915_HPOUT1R_DLY;
776 }
777
778 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_1, mask, val);
779
780 val = 0;
781 mask = 0;
782 if (wm8915->hpout_pending & HPOUT2L) {
783 val |= WM8915_HPOUT2L_RMV_SHORT;
784 mask |= WM8915_HPOUT2L_RMV_SHORT;
785 } else {
786 mask |= WM8915_HPOUT2L_RMV_SHORT |
787 WM8915_HPOUT2L_OUTP |
788 WM8915_HPOUT2L_DLY;
789 }
790
791 if (wm8915->hpout_pending & HPOUT2R) {
792 val |= WM8915_HPOUT2R_RMV_SHORT;
793 mask |= WM8915_HPOUT2R_RMV_SHORT;
794 } else {
795 mask |= WM8915_HPOUT2R_RMV_SHORT |
796 WM8915_HPOUT2R_OUTP |
797 WM8915_HPOUT2R_DLY;
798 }
799
800 snd_soc_update_bits(codec, WM8915_ANALOGUE_HP_2, mask, val);
801
802 wm8915->hpout_ena = wm8915->hpout_pending;
803 }
804}
805
806static int dcs_start(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808{
809 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(w->codec);
810
811 switch (event) {
812 case SND_SOC_DAPM_POST_PMU:
813 wm8915->dcs_pending |= 1 << w->shift;
814 break;
815 default:
816 BUG();
817 return -EINVAL;
818 }
819
820 return 0;
821}
822
823static const char *sidetone_text[] = {
824 "IN1", "IN2",
825};
826
827static const struct soc_enum left_sidetone_enum =
828 SOC_ENUM_SINGLE(WM8915_SIDETONE, 0, 2, sidetone_text);
829
830static const struct snd_kcontrol_new left_sidetone =
831 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
832
833static const struct soc_enum right_sidetone_enum =
834 SOC_ENUM_SINGLE(WM8915_SIDETONE, 1, 2, sidetone_text);
835
836static const struct snd_kcontrol_new right_sidetone =
837 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
838
839static const char *spk_text[] = {
840 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
841};
842
843static const struct soc_enum spkl_enum =
844 SOC_ENUM_SINGLE(WM8915_LEFT_PDM_SPEAKER, 0, 4, spk_text);
845
846static const struct snd_kcontrol_new spkl_mux =
847 SOC_DAPM_ENUM("SPKL", spkl_enum);
848
849static const struct soc_enum spkr_enum =
850 SOC_ENUM_SINGLE(WM8915_RIGHT_PDM_SPEAKER, 0, 4, spk_text);
851
852static const struct snd_kcontrol_new spkr_mux =
853 SOC_DAPM_ENUM("SPKR", spkr_enum);
854
855static const char *dsp1rx_text[] = {
856 "AIF1", "AIF2"
857};
858
859static const struct soc_enum dsp1rx_enum =
860 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 0, 2, dsp1rx_text);
861
862static const struct snd_kcontrol_new dsp1rx =
863 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
864
865static const char *dsp2rx_text[] = {
866 "AIF2", "AIF1"
867};
868
869static const struct soc_enum dsp2rx_enum =
870 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 4, 2, dsp2rx_text);
871
872static const struct snd_kcontrol_new dsp2rx =
873 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
874
875static const char *aif2tx_text[] = {
876 "DSP2", "DSP1", "AIF1"
877};
878
879static const struct soc_enum aif2tx_enum =
880 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_8, 6, 3, aif2tx_text);
881
882static const struct snd_kcontrol_new aif2tx =
883 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
884
885static const char *inmux_text[] = {
886 "ADC", "DMIC1", "DMIC2"
887};
888
889static const struct soc_enum in1_enum =
890 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 0, 3, inmux_text);
891
892static const struct snd_kcontrol_new in1_mux =
893 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
894
895static const struct soc_enum in2_enum =
896 SOC_ENUM_SINGLE(WM8915_POWER_MANAGEMENT_7, 4, 3, inmux_text);
897
898static const struct snd_kcontrol_new in2_mux =
899 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
900
901static const struct snd_kcontrol_new dac2r_mix[] = {
902SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
903 5, 1, 0),
904SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING,
905 4, 1, 0),
906SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
907SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
908};
909
910static const struct snd_kcontrol_new dac2l_mix[] = {
911SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
912 5, 1, 0),
913SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC2_LEFT_MIXER_ROUTING,
914 4, 1, 0),
915SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
916SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
917};
918
919static const struct snd_kcontrol_new dac1r_mix[] = {
920SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
921 5, 1, 0),
922SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING,
923 4, 1, 0),
924SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
925SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
926};
927
928static const struct snd_kcontrol_new dac1l_mix[] = {
929SOC_DAPM_SINGLE("Right Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
930 5, 1, 0),
931SOC_DAPM_SINGLE("Left Sidetone Switch", WM8915_DAC1_LEFT_MIXER_ROUTING,
932 4, 1, 0),
933SOC_DAPM_SINGLE("DSP2 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
934SOC_DAPM_SINGLE("DSP1 Switch", WM8915_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
935};
936
937static const struct snd_kcontrol_new dsp1txl[] = {
938SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
939 1, 1, 0),
940SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_LEFT_MIXER_ROUTING,
941 0, 1, 0),
942};
943
944static const struct snd_kcontrol_new dsp1txr[] = {
945SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
946 1, 1, 0),
947SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP1_TX_RIGHT_MIXER_ROUTING,
948 0, 1, 0),
949};
950
951static const struct snd_kcontrol_new dsp2txl[] = {
952SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
953 1, 1, 0),
954SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_LEFT_MIXER_ROUTING,
955 0, 1, 0),
956};
957
958static const struct snd_kcontrol_new dsp2txr[] = {
959SOC_DAPM_SINGLE("IN1 Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
960 1, 1, 0),
961SOC_DAPM_SINGLE("DAC Switch", WM8915_DSP2_TX_RIGHT_MIXER_ROUTING,
962 0, 1, 0),
963};
964
965
966static const struct snd_soc_dapm_widget wm8915_dapm_widgets[] = {
967SND_SOC_DAPM_INPUT("IN1LN"),
968SND_SOC_DAPM_INPUT("IN1LP"),
969SND_SOC_DAPM_INPUT("IN1RN"),
970SND_SOC_DAPM_INPUT("IN1RP"),
971
972SND_SOC_DAPM_INPUT("IN2LN"),
973SND_SOC_DAPM_INPUT("IN2LP"),
974SND_SOC_DAPM_INPUT("IN2RN"),
975SND_SOC_DAPM_INPUT("IN2RP"),
976
977SND_SOC_DAPM_INPUT("DMIC1DAT"),
978SND_SOC_DAPM_INPUT("DMIC2DAT"),
979
980SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8915_AIF_CLOCKING_1, 0, 0, NULL, 0),
981SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8915_CLOCKING_1, 1, 0, NULL, 0),
982SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8915_CLOCKING_1, 2, 0, NULL, 0),
983SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8915_CHARGE_PUMP_1, 15, 0, cp_event,
984 SND_SOC_DAPM_POST_PMU),
985
986SND_SOC_DAPM_SUPPLY("LDO2", WM8915_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
987SND_SOC_DAPM_MICBIAS("MICB2", WM8915_POWER_MANAGEMENT_1, 9, 0),
988SND_SOC_DAPM_MICBIAS("MICB1", WM8915_POWER_MANAGEMENT_1, 8, 0),
989
990SND_SOC_DAPM_PGA("IN1L PGA", WM8915_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
991SND_SOC_DAPM_PGA("IN1R PGA", WM8915_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
992
abc9d5aa
MB		 993SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
994SND_SOC_DAPM_MUX("IN1R Mux", SND_SOC_NOPM, 0, 0, &in1_mux),
995SND_SOC_DAPM_MUX("IN2L Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
996SND_SOC_DAPM_MUX("IN2R Mux", SND_SOC_NOPM, 0, 0, &in2_mux),
c93993ac
MB		 997
998SND_SOC_DAPM_PGA("IN1L", WM8915_POWER_MANAGEMENT_7, 2, 0, NULL, 0),
999SND_SOC_DAPM_PGA("IN1R", WM8915_POWER_MANAGEMENT_7, 3, 0, NULL, 0),
1000SND_SOC_DAPM_PGA("IN2L", WM8915_POWER_MANAGEMENT_7, 6, 0, NULL, 0),
1001SND_SOC_DAPM_PGA("IN2R", WM8915_POWER_MANAGEMENT_7, 7, 0, NULL, 0),
1002
c93993ac
MB		 1003SND_SOC_DAPM_SUPPLY("DMIC2", WM8915_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
1004SND_SOC_DAPM_SUPPLY("DMIC1", WM8915_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
1005
1006SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8915_POWER_MANAGEMENT_3, 5, 0),
1007SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8915_POWER_MANAGEMENT_3, 4, 0),
1008SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8915_POWER_MANAGEMENT_3, 3, 0),
1009SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8915_POWER_MANAGEMENT_3, 2, 0),
1010
1011SND_SOC_DAPM_ADC("ADCL", NULL, WM8915_POWER_MANAGEMENT_3, 1, 0),
1012SND_SOC_DAPM_ADC("ADCR", NULL, WM8915_POWER_MANAGEMENT_3, 0, 0),
1013
1014SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
1015SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
1016
1017SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 11, 0),
1018SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 10, 0),
1019SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8915_POWER_MANAGEMENT_3, 9, 0),
1020SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8915_POWER_MANAGEMENT_3, 8, 0),
1021
1022SND_SOC_DAPM_MIXER("DSP2TXL", WM8915_POWER_MANAGEMENT_5, 11, 0,
1023 dsp2txl, ARRAY_SIZE(dsp2txl)),
1024SND_SOC_DAPM_MIXER("DSP2TXR", WM8915_POWER_MANAGEMENT_5, 10, 0,
1025 dsp2txr, ARRAY_SIZE(dsp2txr)),
1026SND_SOC_DAPM_MIXER("DSP1TXL", WM8915_POWER_MANAGEMENT_5, 9, 0,
1027 dsp1txl, ARRAY_SIZE(dsp1txl)),
1028SND_SOC_DAPM_MIXER("DSP1TXR", WM8915_POWER_MANAGEMENT_5, 8, 0,
1029 dsp1txr, ARRAY_SIZE(dsp1txr)),
1030
1031SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1032 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
1033SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1034 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
1035SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1036 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1037SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1038 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1039
1040SND_SOC_DAPM_DAC("DAC2L", NULL, WM8915_POWER_MANAGEMENT_5, 3, 0),
1041SND_SOC_DAPM_DAC("DAC2R", NULL, WM8915_POWER_MANAGEMENT_5, 2, 0),
1042SND_SOC_DAPM_DAC("DAC1L", NULL, WM8915_POWER_MANAGEMENT_5, 1, 0),
1043SND_SOC_DAPM_DAC("DAC1R", NULL, WM8915_POWER_MANAGEMENT_5, 0, 0),
1044
1045SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 1,
1046 WM8915_POWER_MANAGEMENT_4, 9, 0),
1047SND_SOC_DAPM_AIF_IN("AIF2RX0", "AIF2 Playback", 2,
1048 WM8915_POWER_MANAGEMENT_4, 8, 0),
1049
1050SND_SOC_DAPM_AIF_IN("AIF2TX1", "AIF2 Capture", 1,
1051 WM8915_POWER_MANAGEMENT_6, 9, 0),
1052SND_SOC_DAPM_AIF_IN("AIF2TX0", "AIF2 Capture", 2,
1053 WM8915_POWER_MANAGEMENT_6, 8, 0),
1054
1055SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 5,
1056 WM8915_POWER_MANAGEMENT_4, 5, 0),
1057SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 4,
1058 WM8915_POWER_MANAGEMENT_4, 4, 0),
1059SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 3,
1060 WM8915_POWER_MANAGEMENT_4, 3, 0),
1061SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 2,
1062 WM8915_POWER_MANAGEMENT_4, 2, 0),
1063SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 1,
1064 WM8915_POWER_MANAGEMENT_4, 1, 0),
1065SND_SOC_DAPM_AIF_IN("AIF1RX0", "AIF1 Playback", 0,
1066 WM8915_POWER_MANAGEMENT_4, 0, 0),
1067
1068SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 5,
1069 WM8915_POWER_MANAGEMENT_6, 5, 0),
1070SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 4,
1071 WM8915_POWER_MANAGEMENT_6, 4, 0),
1072SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 3,
1073 WM8915_POWER_MANAGEMENT_6, 3, 0),
1074SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 2,
1075 WM8915_POWER_MANAGEMENT_6, 2, 0),
1076SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 1,
1077 WM8915_POWER_MANAGEMENT_6, 1, 0),
1078SND_SOC_DAPM_AIF_OUT("AIF1TX0", "AIF1 Capture", 0,
1079 WM8915_POWER_MANAGEMENT_6, 0, 0),
1080
1081/* We route as stereo pairs so define some dummy widgets to squash
1082 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1083SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1084SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1085SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1086SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1087SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1088
1089SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1090SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1091SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1092
1093SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1094SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1095SND_SOC_DAPM_PGA("SPKL PGA", WM8915_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1096SND_SOC_DAPM_PGA("SPKR PGA", WM8915_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1097
1098SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8915_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1099SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8915_ANALOGUE_HP_2, 5, 0, NULL, 0),
1100SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8915_DC_SERVO_1, 2, 0, dcs_start,
1101 SND_SOC_DAPM_POST_PMU),
1102SND_SOC_DAPM_PGA_S("HPOUT2L_OUTP", 3, WM8915_ANALOGUE_HP_2, 6, 0, NULL, 0),
1103SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1104 rmv_short_event,
1105 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1106
1107SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8915_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1108SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8915_ANALOGUE_HP_2, 1, 0, NULL, 0),
1109SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8915_DC_SERVO_1, 3, 0, dcs_start,
1110 SND_SOC_DAPM_POST_PMU),
1111SND_SOC_DAPM_PGA_S("HPOUT2R_OUTP", 3, WM8915_ANALOGUE_HP_2, 2, 0, NULL, 0),
1112SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1113 rmv_short_event,
1114 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1115
1116SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8915_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1117SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8915_ANALOGUE_HP_1, 5, 0, NULL, 0),
1118SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8915_DC_SERVO_1, 0, 0, dcs_start,
1119 SND_SOC_DAPM_POST_PMU),
1120SND_SOC_DAPM_PGA_S("HPOUT1L_OUTP", 3, WM8915_ANALOGUE_HP_1, 6, 0, NULL, 0),
1121SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1122 rmv_short_event,
1123 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1124
1125SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8915_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1126SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8915_ANALOGUE_HP_1, 1, 0, NULL, 0),
1127SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8915_DC_SERVO_1, 1, 0, dcs_start,
1128 SND_SOC_DAPM_POST_PMU),
1129SND_SOC_DAPM_PGA_S("HPOUT1R_OUTP", 3, WM8915_ANALOGUE_HP_1, 2, 0, NULL, 0),
1130SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1131 rmv_short_event,
1132 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1133
1134SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1135SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1136SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1137SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1138SND_SOC_DAPM_OUTPUT("SPKDAT"),
1139};
1140
1141static const struct snd_soc_dapm_route wm8915_dapm_routes[] = {
1142 { "AIFCLK", NULL, "SYSCLK" },
1143 { "SYSDSPCLK", NULL, "SYSCLK" },
1144 { "Charge Pump", NULL, "SYSCLK" },
1145
1146 { "MICB1", NULL, "LDO2" },
1147 { "MICB2", NULL, "LDO2" },
1148
1149 { "IN1L PGA", NULL, "IN2LN" },
1150 { "IN1L PGA", NULL, "IN2LP" },
1151 { "IN1L PGA", NULL, "IN1LN" },
1152 { "IN1L PGA", NULL, "IN1LP" },
1153
1154 { "IN1R PGA", NULL, "IN2RN" },
1155 { "IN1R PGA", NULL, "IN2RP" },
1156 { "IN1R PGA", NULL, "IN1RN" },
1157 { "IN1R PGA", NULL, "IN1RP" },
1158
1159 { "ADCL", NULL, "IN1L PGA" },
1160
1161 { "ADCR", NULL, "IN1R PGA" },
1162
1163 { "DMIC1L", NULL, "DMIC1DAT" },
1164 { "DMIC1R", NULL, "DMIC1DAT" },
1165 { "DMIC2L", NULL, "DMIC2DAT" },
1166 { "DMIC2R", NULL, "DMIC2DAT" },
1167
1168 { "DMIC2L", NULL, "DMIC2" },
1169 { "DMIC2R", NULL, "DMIC2" },
1170 { "DMIC1L", NULL, "DMIC1" },
1171 { "DMIC1R", NULL, "DMIC1" },
1172
abc9d5aa
MB		 1173 { "IN1L Mux", "ADC", "ADCL" },
1174 { "IN1L Mux", "DMIC1", "DMIC1L" },
1175 { "IN1L Mux", "DMIC2", "DMIC2L" },
1176
1177 { "IN1R Mux", "ADC", "ADCR" },
1178 { "IN1R Mux", "DMIC1", "DMIC1R" },
1179 { "IN1R Mux", "DMIC2", "DMIC2R" },
c93993ac 1180
abc9d5aa
MB		 1181 { "IN2L Mux", "ADC", "ADCL" },
1182 { "IN2L Mux", "DMIC1", "DMIC1L" },
1183 { "IN2L Mux", "DMIC2", "DMIC2L" },
c93993ac 1184
abc9d5aa
MB		 1185 { "IN2R Mux", "ADC", "ADCR" },
1186 { "IN2R Mux", "DMIC1", "DMIC1R" },
1187 { "IN2R Mux", "DMIC2", "DMIC2R" },
c93993ac 1188
abc9d5aa
MB		 1189 { "Left Sidetone", "IN1", "IN1L Mux" },
1190 { "Left Sidetone", "IN2", "IN2L Mux" },
c93993ac 1191
abc9d5aa
MB		 1192 { "Right Sidetone", "IN1", "IN1R Mux" },
1193 { "Right Sidetone", "IN2", "IN2R Mux" },
c93993ac 1194
abc9d5aa
MB		 1195 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1196 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
c93993ac 1197
abc9d5aa
MB		 1198 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1199 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
c93993ac
MB		 1200
1201 { "AIF1TX0", NULL, "DSP1TXL" },
1202 { "AIF1TX1", NULL, "DSP1TXR" },
1203 { "AIF1TX2", NULL, "DSP2TXL" },
1204 { "AIF1TX3", NULL, "DSP2TXR" },
1205 { "AIF1TX4", NULL, "AIF2RX0" },
1206 { "AIF1TX5", NULL, "AIF2RX1" },
1207
1208 { "AIF1RX0", NULL, "AIFCLK" },
1209 { "AIF1RX1", NULL, "AIFCLK" },
1210 { "AIF1RX2", NULL, "AIFCLK" },
1211 { "AIF1RX3", NULL, "AIFCLK" },
1212 { "AIF1RX4", NULL, "AIFCLK" },
1213 { "AIF1RX5", NULL, "AIFCLK" },
1214
1215 { "AIF2RX0", NULL, "AIFCLK" },
1216 { "AIF2RX1", NULL, "AIFCLK" },
1217
1218 { "DSP1RXL", NULL, "SYSDSPCLK" },
1219 { "DSP1RXR", NULL, "SYSDSPCLK" },
1220 { "DSP2RXL", NULL, "SYSDSPCLK" },
1221 { "DSP2RXR", NULL, "SYSDSPCLK" },
1222 { "DSP1TXL", NULL, "SYSDSPCLK" },
1223 { "DSP1TXR", NULL, "SYSDSPCLK" },
1224 { "DSP2TXL", NULL, "SYSDSPCLK" },
1225 { "DSP2TXR", NULL, "SYSDSPCLK" },
1226
1227 { "AIF1RXA", NULL, "AIF1RX0" },
1228 { "AIF1RXA", NULL, "AIF1RX1" },
1229 { "AIF1RXB", NULL, "AIF1RX2" },
1230 { "AIF1RXB", NULL, "AIF1RX3" },
1231 { "AIF1RXC", NULL, "AIF1RX4" },
1232 { "AIF1RXC", NULL, "AIF1RX5" },
1233
1234 { "AIF2RX", NULL, "AIF2RX0" },
1235 { "AIF2RX", NULL, "AIF2RX1" },
1236
1237 { "AIF2TX", "DSP2", "DSP2TX" },
1238 { "AIF2TX", "DSP1", "DSP1RX" },
1239 { "AIF2TX", "AIF1", "AIF1RXC" },
1240
1241 { "DSP1RXL", NULL, "DSP1RX" },
1242 { "DSP1RXR", NULL, "DSP1RX" },
1243 { "DSP2RXL", NULL, "DSP2RX" },
1244 { "DSP2RXR", NULL, "DSP2RX" },
1245
1246 { "DSP2TX", NULL, "DSP2TXL" },
1247 { "DSP2TX", NULL, "DSP2TXR" },
1248
1249 { "DSP1RX", "AIF1", "AIF1RXA" },
1250 { "DSP1RX", "AIF2", "AIF2RX" },
1251
1252 { "DSP2RX", "AIF1", "AIF1RXB" },
1253 { "DSP2RX", "AIF2", "AIF2RX" },
1254
1255 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1256 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1257 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1258 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1259
1260 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1261 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1262 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1263 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1264
1265 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1266 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1267 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1268 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1269
1270 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1271 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1272 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1273 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1274
1275 { "DAC1L", NULL, "DAC1L Mixer" },
1276 { "DAC1R", NULL, "DAC1R Mixer" },
1277 { "DAC2L", NULL, "DAC2L Mixer" },
1278 { "DAC2R", NULL, "DAC2R Mixer" },
1279
1280 { "HPOUT2L PGA", NULL, "Charge Pump" },
1281 { "HPOUT2L PGA", NULL, "DAC2L" },
1282 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1283 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1284 { "HPOUT2L_OUTP", NULL, "HPOUT2L_DCS" },
1285 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_OUTP" },
1286
1287 { "HPOUT2R PGA", NULL, "Charge Pump" },
1288 { "HPOUT2R PGA", NULL, "DAC2R" },
1289 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1290 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1291 { "HPOUT2R_OUTP", NULL, "HPOUT2R_DCS" },
1292 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_OUTP" },
1293
1294 { "HPOUT1L PGA", NULL, "Charge Pump" },
1295 { "HPOUT1L PGA", NULL, "DAC1L" },
1296 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1297 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1298 { "HPOUT1L_OUTP", NULL, "HPOUT1L_DCS" },
1299 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_OUTP" },
1300
1301 { "HPOUT1R PGA", NULL, "Charge Pump" },
1302 { "HPOUT1R PGA", NULL, "DAC1R" },
1303 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1304 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1305 { "HPOUT1R_OUTP", NULL, "HPOUT1R_DCS" },
1306 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_OUTP" },
1307
1308 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1309 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1310 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1311 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1312
1313 { "SPKL", "DAC1L", "DAC1L" },
1314 { "SPKL", "DAC1R", "DAC1R" },
1315 { "SPKL", "DAC2L", "DAC2L" },
1316 { "SPKL", "DAC2R", "DAC2R" },
1317
1318 { "SPKR", "DAC1L", "DAC1L" },
1319 { "SPKR", "DAC1R", "DAC1R" },
1320 { "SPKR", "DAC2L", "DAC2L" },
1321 { "SPKR", "DAC2R", "DAC2R" },
1322
1323 { "SPKL PGA", NULL, "SPKL" },
1324 { "SPKR PGA", NULL, "SPKR" },
1325
1326 { "SPKDAT", NULL, "SPKL PGA" },
1327 { "SPKDAT", NULL, "SPKR PGA" },
1328};
1329
1330static int wm8915_readable_register(struct snd_soc_codec *codec,
1331 unsigned int reg)
1332{
1333 /* Due to the sparseness of the register map the compiler
1334 * output from an explicit switch statement ends up being much
1335 * more efficient than a table.
1336 */
1337 switch (reg) {
1338 case WM8915_SOFTWARE_RESET:
1339 case WM8915_POWER_MANAGEMENT_1:
1340 case WM8915_POWER_MANAGEMENT_2:
1341 case WM8915_POWER_MANAGEMENT_3:
1342 case WM8915_POWER_MANAGEMENT_4:
1343 case WM8915_POWER_MANAGEMENT_5:
1344 case WM8915_POWER_MANAGEMENT_6:
1345 case WM8915_POWER_MANAGEMENT_7:
1346 case WM8915_POWER_MANAGEMENT_8:
1347 case WM8915_LEFT_LINE_INPUT_VOLUME:
1348 case WM8915_RIGHT_LINE_INPUT_VOLUME:
1349 case WM8915_LINE_INPUT_CONTROL:
1350 case WM8915_DAC1_HPOUT1_VOLUME:
1351 case WM8915_DAC2_HPOUT2_VOLUME:
1352 case WM8915_DAC1_LEFT_VOLUME:
1353 case WM8915_DAC1_RIGHT_VOLUME:
1354 case WM8915_DAC2_LEFT_VOLUME:
1355 case WM8915_DAC2_RIGHT_VOLUME:
1356 case WM8915_OUTPUT1_LEFT_VOLUME:
1357 case WM8915_OUTPUT1_RIGHT_VOLUME:
1358 case WM8915_OUTPUT2_LEFT_VOLUME:
1359 case WM8915_OUTPUT2_RIGHT_VOLUME:
1360 case WM8915_MICBIAS_1:
1361 case WM8915_MICBIAS_2:
1362 case WM8915_LDO_1:
1363 case WM8915_LDO_2:
1364 case WM8915_ACCESSORY_DETECT_MODE_1:
1365 case WM8915_ACCESSORY_DETECT_MODE_2:
1366 case WM8915_HEADPHONE_DETECT_1:
1367 case WM8915_HEADPHONE_DETECT_2:
1368 case WM8915_MIC_DETECT_1:
1369 case WM8915_MIC_DETECT_2:
1370 case WM8915_MIC_DETECT_3:
1371 case WM8915_CHARGE_PUMP_1:
1372 case WM8915_CHARGE_PUMP_2:
1373 case WM8915_DC_SERVO_1:
1374 case WM8915_DC_SERVO_2:
1375 case WM8915_DC_SERVO_3:
1376 case WM8915_DC_SERVO_5:
1377 case WM8915_DC_SERVO_6:
1378 case WM8915_DC_SERVO_7:
1379 case WM8915_DC_SERVO_READBACK_0:
1380 case WM8915_ANALOGUE_HP_1:
1381 case WM8915_ANALOGUE_HP_2:
1382 case WM8915_CHIP_REVISION:
1383 case WM8915_CONTROL_INTERFACE_1:
1384 case WM8915_WRITE_SEQUENCER_CTRL_1:
1385 case WM8915_WRITE_SEQUENCER_CTRL_2:
1386 case WM8915_AIF_CLOCKING_1:
1387 case WM8915_AIF_CLOCKING_2:
1388 case WM8915_CLOCKING_1:
1389 case WM8915_CLOCKING_2:
1390 case WM8915_AIF_RATE:
1391 case WM8915_FLL_CONTROL_1:
1392 case WM8915_FLL_CONTROL_2:
1393 case WM8915_FLL_CONTROL_3:
1394 case WM8915_FLL_CONTROL_4:
1395 case WM8915_FLL_CONTROL_5:
1396 case WM8915_FLL_CONTROL_6:
1397 case WM8915_FLL_EFS_1:
1398 case WM8915_FLL_EFS_2:
1399 case WM8915_AIF1_CONTROL:
1400 case WM8915_AIF1_BCLK:
1401 case WM8915_AIF1_TX_LRCLK_1:
1402 case WM8915_AIF1_TX_LRCLK_2:
1403 case WM8915_AIF1_RX_LRCLK_1:
1404 case WM8915_AIF1_RX_LRCLK_2:
1405 case WM8915_AIF1TX_DATA_CONFIGURATION_1:
1406 case WM8915_AIF1TX_DATA_CONFIGURATION_2:
1407 case WM8915_AIF1RX_DATA_CONFIGURATION:
1408 case WM8915_AIF1TX_CHANNEL_0_CONFIGURATION:
1409 case WM8915_AIF1TX_CHANNEL_1_CONFIGURATION:
1410 case WM8915_AIF1TX_CHANNEL_2_CONFIGURATION:
1411 case WM8915_AIF1TX_CHANNEL_3_CONFIGURATION:
1412 case WM8915_AIF1TX_CHANNEL_4_CONFIGURATION:
1413 case WM8915_AIF1TX_CHANNEL_5_CONFIGURATION:
1414 case WM8915_AIF1RX_CHANNEL_0_CONFIGURATION:
1415 case WM8915_AIF1RX_CHANNEL_1_CONFIGURATION:
1416 case WM8915_AIF1RX_CHANNEL_2_CONFIGURATION:
1417 case WM8915_AIF1RX_CHANNEL_3_CONFIGURATION:
1418 case WM8915_AIF1RX_CHANNEL_4_CONFIGURATION:
1419 case WM8915_AIF1RX_CHANNEL_5_CONFIGURATION:
1420 case WM8915_AIF1RX_MONO_CONFIGURATION:
1421 case WM8915_AIF1TX_TEST:
1422 case WM8915_AIF2_CONTROL:
1423 case WM8915_AIF2_BCLK:
1424 case WM8915_AIF2_TX_LRCLK_1:
1425 case WM8915_AIF2_TX_LRCLK_2:
1426 case WM8915_AIF2_RX_LRCLK_1:
1427 case WM8915_AIF2_RX_LRCLK_2:
1428 case WM8915_AIF2TX_DATA_CONFIGURATION_1:
1429 case WM8915_AIF2TX_DATA_CONFIGURATION_2:
1430 case WM8915_AIF2RX_DATA_CONFIGURATION:
1431 case WM8915_AIF2TX_CHANNEL_0_CONFIGURATION:
1432 case WM8915_AIF2TX_CHANNEL_1_CONFIGURATION:
1433 case WM8915_AIF2RX_CHANNEL_0_CONFIGURATION:
1434 case WM8915_AIF2RX_CHANNEL_1_CONFIGURATION:
1435 case WM8915_AIF2RX_MONO_CONFIGURATION:
1436 case WM8915_AIF2TX_TEST:
1437 case WM8915_DSP1_TX_LEFT_VOLUME:
1438 case WM8915_DSP1_TX_RIGHT_VOLUME:
1439 case WM8915_DSP1_RX_LEFT_VOLUME:
1440 case WM8915_DSP1_RX_RIGHT_VOLUME:
1441 case WM8915_DSP1_TX_FILTERS:
1442 case WM8915_DSP1_RX_FILTERS_1:
1443 case WM8915_DSP1_RX_FILTERS_2:
1444 case WM8915_DSP1_DRC_1:
1445 case WM8915_DSP1_DRC_2:
1446 case WM8915_DSP1_DRC_3:
1447 case WM8915_DSP1_DRC_4:
1448 case WM8915_DSP1_DRC_5:
1449 case WM8915_DSP1_RX_EQ_GAINS_1:
1450 case WM8915_DSP1_RX_EQ_GAINS_2:
1451 case WM8915_DSP1_RX_EQ_BAND_1_A:
1452 case WM8915_DSP1_RX_EQ_BAND_1_B:
1453 case WM8915_DSP1_RX_EQ_BAND_1_PG:
1454 case WM8915_DSP1_RX_EQ_BAND_2_A:
1455 case WM8915_DSP1_RX_EQ_BAND_2_B:
1456 case WM8915_DSP1_RX_EQ_BAND_2_C:
1457 case WM8915_DSP1_RX_EQ_BAND_2_PG:
1458 case WM8915_DSP1_RX_EQ_BAND_3_A:
1459 case WM8915_DSP1_RX_EQ_BAND_3_B:
1460 case WM8915_DSP1_RX_EQ_BAND_3_C:
1461 case WM8915_DSP1_RX_EQ_BAND_3_PG:
1462 case WM8915_DSP1_RX_EQ_BAND_4_A:
1463 case WM8915_DSP1_RX_EQ_BAND_4_B:
1464 case WM8915_DSP1_RX_EQ_BAND_4_C:
1465 case WM8915_DSP1_RX_EQ_BAND_4_PG:
1466 case WM8915_DSP1_RX_EQ_BAND_5_A:
1467 case WM8915_DSP1_RX_EQ_BAND_5_B:
1468 case WM8915_DSP1_RX_EQ_BAND_5_PG:
1469 case WM8915_DSP2_TX_LEFT_VOLUME:
1470 case WM8915_DSP2_TX_RIGHT_VOLUME:
1471 case WM8915_DSP2_RX_LEFT_VOLUME:
1472 case WM8915_DSP2_RX_RIGHT_VOLUME:
1473 case WM8915_DSP2_TX_FILTERS:
1474 case WM8915_DSP2_RX_FILTERS_1:
1475 case WM8915_DSP2_RX_FILTERS_2:
1476 case WM8915_DSP2_DRC_1:
1477 case WM8915_DSP2_DRC_2:
1478 case WM8915_DSP2_DRC_3:
1479 case WM8915_DSP2_DRC_4:
1480 case WM8915_DSP2_DRC_5:
1481 case WM8915_DSP2_RX_EQ_GAINS_1:
1482 case WM8915_DSP2_RX_EQ_GAINS_2:
1483 case WM8915_DSP2_RX_EQ_BAND_1_A:
1484 case WM8915_DSP2_RX_EQ_BAND_1_B:
1485 case WM8915_DSP2_RX_EQ_BAND_1_PG:
1486 case WM8915_DSP2_RX_EQ_BAND_2_A:
1487 case WM8915_DSP2_RX_EQ_BAND_2_B:
1488 case WM8915_DSP2_RX_EQ_BAND_2_C:
1489 case WM8915_DSP2_RX_EQ_BAND_2_PG:
1490 case WM8915_DSP2_RX_EQ_BAND_3_A:
1491 case WM8915_DSP2_RX_EQ_BAND_3_B:
1492 case WM8915_DSP2_RX_EQ_BAND_3_C:
1493 case WM8915_DSP2_RX_EQ_BAND_3_PG:
1494 case WM8915_DSP2_RX_EQ_BAND_4_A:
1495 case WM8915_DSP2_RX_EQ_BAND_4_B:
1496 case WM8915_DSP2_RX_EQ_BAND_4_C:
1497 case WM8915_DSP2_RX_EQ_BAND_4_PG:
1498 case WM8915_DSP2_RX_EQ_BAND_5_A:
1499 case WM8915_DSP2_RX_EQ_BAND_5_B:
1500 case WM8915_DSP2_RX_EQ_BAND_5_PG:
1501 case WM8915_DAC1_MIXER_VOLUMES:
1502 case WM8915_DAC1_LEFT_MIXER_ROUTING:
1503 case WM8915_DAC1_RIGHT_MIXER_ROUTING:
1504 case WM8915_DAC2_MIXER_VOLUMES:
1505 case WM8915_DAC2_LEFT_MIXER_ROUTING:
1506 case WM8915_DAC2_RIGHT_MIXER_ROUTING:
1507 case WM8915_DSP1_TX_LEFT_MIXER_ROUTING:
1508 case WM8915_DSP1_TX_RIGHT_MIXER_ROUTING:
1509 case WM8915_DSP2_TX_LEFT_MIXER_ROUTING:
1510 case WM8915_DSP2_TX_RIGHT_MIXER_ROUTING:
1511 case WM8915_DSP_TX_MIXER_SELECT:
1512 case WM8915_DAC_SOFTMUTE:
1513 case WM8915_OVERSAMPLING:
1514 case WM8915_SIDETONE:
1515 case WM8915_GPIO_1:
1516 case WM8915_GPIO_2:
1517 case WM8915_GPIO_3:
1518 case WM8915_GPIO_4:
1519 case WM8915_GPIO_5:
1520 case WM8915_PULL_CONTROL_1:
1521 case WM8915_PULL_CONTROL_2:
1522 case WM8915_INTERRUPT_STATUS_1:
1523 case WM8915_INTERRUPT_STATUS_2:
1524 case WM8915_INTERRUPT_RAW_STATUS_2:
1525 case WM8915_INTERRUPT_STATUS_1_MASK:
1526 case WM8915_INTERRUPT_STATUS_2_MASK:
1527 case WM8915_INTERRUPT_CONTROL:
1528 case WM8915_LEFT_PDM_SPEAKER:
1529 case WM8915_RIGHT_PDM_SPEAKER:
1530 case WM8915_PDM_SPEAKER_MUTE_SEQUENCE:
1531 case WM8915_PDM_SPEAKER_VOLUME:
1532 return 1;
1533 default:
1534 return 0;
1535 }
1536}
1537
1538static int wm8915_volatile_register(struct snd_soc_codec *codec,
1539 unsigned int reg)
1540{
1541 switch (reg) {
1542 case WM8915_SOFTWARE_RESET:
1543 case WM8915_CHIP_REVISION:
1544 case WM8915_LDO_1:
1545 case WM8915_LDO_2:
1546 case WM8915_INTERRUPT_STATUS_1:
1547 case WM8915_INTERRUPT_STATUS_2:
1548 case WM8915_INTERRUPT_RAW_STATUS_2:
1549 case WM8915_DC_SERVO_READBACK_0:
1550 case WM8915_DC_SERVO_2:
1551 case WM8915_DC_SERVO_6:
1552 case WM8915_DC_SERVO_7:
1553 case WM8915_FLL_CONTROL_6:
1554 case WM8915_MIC_DETECT_3:
1555 case WM8915_HEADPHONE_DETECT_1:
1556 case WM8915_HEADPHONE_DETECT_2:
1557 return 1;
1558 default:
1559 return 0;
1560 }
1561}
1562
1563static int wm8915_reset(struct snd_soc_codec *codec)
1564{
1565 return snd_soc_write(codec, WM8915_SOFTWARE_RESET, 0x8915);
1566}
1567
1568static int wm8915_set_bias_level(struct snd_soc_codec *codec,
1569 enum snd_soc_bias_level level)
1570{
1571 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1572 int ret;
1573
1574 switch (level) {
1575 case SND_SOC_BIAS_ON:
1576 break;
1577
1578 case SND_SOC_BIAS_PREPARE:
1579 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1580 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1581 WM8915_BG_ENA, WM8915_BG_ENA);
1582 msleep(2);
1583 }
1584 break;
1585
1586 case SND_SOC_BIAS_STANDBY:
1587 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1588 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
1589 wm8915->supplies);
1590 if (ret != 0) {
1591 dev_err(codec->dev,
1592 "Failed to enable supplies: %d\n",
1593 ret);
1594 return ret;
1595 }
1596
1597 if (wm8915->pdata.ldo_ena >= 0) {
1598 gpio_set_value_cansleep(wm8915->pdata.ldo_ena,
1599 1);
1600 msleep(5);
1601 }
1602
1603 codec->cache_only = false;
1604 snd_soc_cache_sync(codec);
1605 }
1606
1607 snd_soc_update_bits(codec, WM8915_POWER_MANAGEMENT_1,
1608 WM8915_BG_ENA, 0);
1609 break;
1610
1611 case SND_SOC_BIAS_OFF:
1612 codec->cache_only = true;
1613 if (wm8915->pdata.ldo_ena >= 0)
1614 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
1615 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies),
1616 wm8915->supplies);
1617 break;
1618 }
1619
1620 codec->dapm.bias_level = level;
1621
1622 return 0;
1623}
1624
1625static int wm8915_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1626{
1627 struct snd_soc_codec *codec = dai->codec;
1628 int aifctrl = 0;
1629 int bclk = 0;
1630 int lrclk_tx = 0;
1631 int lrclk_rx = 0;
1632 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1633
1634 switch (dai->id) {
1635 case 0:
1636 aifctrl_reg = WM8915_AIF1_CONTROL;
1637 bclk_reg = WM8915_AIF1_BCLK;
1638 lrclk_tx_reg = WM8915_AIF1_TX_LRCLK_2;
1639 lrclk_rx_reg = WM8915_AIF1_RX_LRCLK_2;
1640 break;
1641 case 1:
1642 aifctrl_reg = WM8915_AIF2_CONTROL;
1643 bclk_reg = WM8915_AIF2_BCLK;
1644 lrclk_tx_reg = WM8915_AIF2_TX_LRCLK_2;
1645 lrclk_rx_reg = WM8915_AIF2_RX_LRCLK_2;
1646 break;
1647 default:
1648 BUG();
1649 return -EINVAL;
1650 }
1651
1652 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1653 case SND_SOC_DAIFMT_NB_NF:
1654 break;
1655 case SND_SOC_DAIFMT_IB_NF:
1656 bclk |= WM8915_AIF1_BCLK_INV;
1657 break;
1658 case SND_SOC_DAIFMT_NB_IF:
1659 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1660 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1661 break;
1662 case SND_SOC_DAIFMT_IB_IF:
1663 bclk |= WM8915_AIF1_BCLK_INV;
1664 lrclk_tx |= WM8915_AIF1TX_LRCLK_INV;
1665 lrclk_rx |= WM8915_AIF1RX_LRCLK_INV;
1666 break;
1667 }
1668
1669 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1670 case SND_SOC_DAIFMT_CBS_CFS:
1671 break;
1672 case SND_SOC_DAIFMT_CBS_CFM:
1673 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1674 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1675 break;
1676 case SND_SOC_DAIFMT_CBM_CFS:
1677 bclk |= WM8915_AIF1_BCLK_MSTR;
1678 break;
1679 case SND_SOC_DAIFMT_CBM_CFM:
1680 bclk |= WM8915_AIF1_BCLK_MSTR;
1681 lrclk_tx |= WM8915_AIF1TX_LRCLK_MSTR;
1682 lrclk_rx |= WM8915_AIF1RX_LRCLK_MSTR;
1683 break;
1684 default:
1685 return -EINVAL;
1686 }
1687
1688 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1689 case SND_SOC_DAIFMT_DSP_A:
1690 break;
1691 case SND_SOC_DAIFMT_DSP_B:
1692 aifctrl |= 1;
1693 break;
1694 case SND_SOC_DAIFMT_I2S:
1695 aifctrl |= 2;
1696 break;
1697 case SND_SOC_DAIFMT_LEFT_J:
1698 aifctrl |= 3;
1699 break;
1700 default:
1701 return -EINVAL;
1702 }
1703
1704 snd_soc_update_bits(codec, aifctrl_reg, WM8915_AIF1_FMT_MASK, aifctrl);
1705 snd_soc_update_bits(codec, bclk_reg,
1706 WM8915_AIF1_BCLK_INV | WM8915_AIF1_BCLK_MSTR,
1707 bclk);
1708 snd_soc_update_bits(codec, lrclk_tx_reg,
1709 WM8915_AIF1TX_LRCLK_INV |
1710 WM8915_AIF1TX_LRCLK_MSTR,
1711 lrclk_tx);
1712 snd_soc_update_bits(codec, lrclk_rx_reg,
1713 WM8915_AIF1RX_LRCLK_INV |
1714 WM8915_AIF1RX_LRCLK_MSTR,
1715 lrclk_rx);
1716
1717 return 0;
1718}
1719
1720static const int bclk_divs[] = {
1721 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1722};
1723
1724static const int dsp_divs[] = {
1725 48000, 32000, 16000, 8000
1726};
1727
1728static int wm8915_hw_params(struct snd_pcm_substream *substream,
1729 struct snd_pcm_hw_params *params,
1730 struct snd_soc_dai *dai)
1731{
1732 struct snd_soc_codec *codec = dai->codec;
1733 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1734 int bits, i, bclk_rate, best, cur_val;
1735 int aifdata = 0;
1736 int bclk = 0;
1737 int lrclk = 0;
1738 int dsp = 0;
1739 int aifdata_reg, bclk_reg, lrclk_reg, dsp_shift;
1740
1741 if (!wm8915->sysclk) {
1742 dev_err(codec->dev, "SYSCLK not configured\n");
1743 return -EINVAL;
1744 }
1745
1746 switch (dai->id) {
1747 case 0:
1748 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1749 (snd_soc_read(codec, WM8915_GPIO_1)) & WM8915_GP1_FN_MASK) {
1750 aifdata_reg = WM8915_AIF1RX_DATA_CONFIGURATION;
1751 lrclk_reg = WM8915_AIF1_RX_LRCLK_1;
1752 } else {
1753 aifdata_reg = WM8915_AIF1TX_DATA_CONFIGURATION_1;
1754 lrclk_reg = WM8915_AIF1_TX_LRCLK_1;
1755 }
1756 bclk_reg = WM8915_AIF1_BCLK;
1757 dsp_shift = 0;
1758 break;
1759 case 1:
1760 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1761 (snd_soc_read(codec, WM8915_GPIO_2)) & WM8915_GP2_FN_MASK) {
1762 aifdata_reg = WM8915_AIF2RX_DATA_CONFIGURATION;
1763 lrclk_reg = WM8915_AIF2_RX_LRCLK_1;
1764 } else {
1765 aifdata_reg = WM8915_AIF2TX_DATA_CONFIGURATION_1;
1766 lrclk_reg = WM8915_AIF2_TX_LRCLK_1;
1767 }
1768 bclk_reg = WM8915_AIF2_BCLK;
1769 dsp_shift = WM8915_DSP2_DIV_SHIFT;
1770 break;
1771 default:
1772 BUG();
1773 return -EINVAL;
1774 }
1775
1776 bclk_rate = snd_soc_params_to_bclk(params);
1777 if (bclk_rate < 0) {
1778 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1779 return bclk_rate;
1780 }
1781
1782 /* Needs looking at for TDM */
1783 bits = snd_pcm_format_width(params_format(params));
1784 if (bits < 0)
1785 return bits;
1786 aifdata |= (bits << WM8915_AIF1TX_WL_SHIFT) | bits;
1787
1788 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1789 if (dsp_divs[i] == params_rate(params))
1790 break;
1791 }
1792 if (i == ARRAY_SIZE(dsp_divs)) {
1793 dev_err(codec->dev, "Unsupported sample rate %dHz\n",
1794 params_rate(params));
1795 return -EINVAL;
1796 }
1797 dsp |= i << dsp_shift;
1798
1799 /* Pick a divisor for BCLK as close as we can get to ideal */
1800 best = 0;
1801 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1802 cur_val = (wm8915->sysclk / bclk_divs[i]) - bclk_rate;
1803 if (cur_val < 0) /* BCLK table is sorted */
1804 break;
1805 best = i;
1806 }
1807 bclk_rate = wm8915->sysclk / bclk_divs[best];
1808 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1809 bclk_divs[best], bclk_rate);
1810 bclk |= best;
1811
1812 lrclk = bclk_rate / params_rate(params);
1813 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1814 lrclk, bclk_rate / lrclk);
1815
1816 snd_soc_update_bits(codec, aifdata_reg,
1817 WM8915_AIF1TX_WL_MASK |
1818 WM8915_AIF1TX_SLOT_LEN_MASK,
1819 aifdata);
1820 snd_soc_update_bits(codec, bclk_reg, WM8915_AIF1_BCLK_DIV_MASK, bclk);
1821 snd_soc_update_bits(codec, lrclk_reg, WM8915_AIF1RX_RATE_MASK,
1822 lrclk);
1823 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_2,
1824 WM8915_DSP1_DIV_SHIFT << dsp_shift, dsp);
1825
1826 wm8915->rx_rate[dai->id] = params_rate(params);
1827
1828 return 0;
1829}
1830
1831static int wm8915_set_sysclk(struct snd_soc_dai *dai,
1832 int clk_id, unsigned int freq, int dir)
1833{
1834 struct snd_soc_codec *codec = dai->codec;
1835 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
1836 int lfclk = 0;
c5f336cc 1837 int ratediv = 0;
c93993ac
MB		 1838 int src;
1839 int old;
1840
1841 /* Disable SYSCLK while we reconfigure */
1842 old = snd_soc_read(codec, WM8915_AIF_CLOCKING_1);
1843 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1844 WM8915_SYSCLK_ENA, 0);
1845
1846 switch (clk_id) {
1847 case WM8915_SYSCLK_MCLK1:
1848 wm8915->sysclk = freq;
1849 src = 0;
1850 break;
1851 case WM8915_SYSCLK_MCLK2:
1852 wm8915->sysclk = freq;
1853 src = 1;
1854 break;
1855 case WM8915_SYSCLK_FLL:
1856 wm8915->sysclk = freq;
1857 src = 2;
1858 break;
1859 default:
1860 dev_err(codec->dev, "Unsupported clock source %d\n", clk_id);
1861 return -EINVAL;
1862 }
1863
1864 switch (wm8915->sysclk) {
1865 case 6144000:
1866 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1867 WM8915_SYSCLK_RATE, 0);
1868 break;
c5f336cc
MB		 1869 case 24576000:
1870 ratediv = WM8915_SYSCLK_DIV;
c93993ac
MB		 1871 case 12288000:
1872 snd_soc_update_bits(codec, WM8915_AIF_RATE,
1873 WM8915_SYSCLK_RATE, WM8915_SYSCLK_RATE);
1874 break;
1875 case 32000:
1876 case 32768:
1877 lfclk = WM8915_LFCLK_ENA;
1878 break;
1879 default:
1880 dev_warn(codec->dev, "Unsupported clock rate %dHz\n",
1881 wm8915->sysclk);
1882 return -EINVAL;
1883 }
1884
1885 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
c5f336cc
MB		 1886 WM8915_SYSCLK_SRC_MASK | WM8915_SYSCLK_DIV_MASK,
1887 src << WM8915_SYSCLK_SRC_SHIFT | ratediv);
c93993ac
MB		 1888 snd_soc_update_bits(codec, WM8915_CLOCKING_1, WM8915_LFCLK_ENA, lfclk);
1889 snd_soc_update_bits(codec, WM8915_AIF_CLOCKING_1,
1890 WM8915_SYSCLK_ENA, old);
1891
1892 return 0;
1893}
1894
1895struct _fll_div {
1896 u16 fll_fratio;
1897 u16 fll_outdiv;
1898 u16 fll_refclk_div;
1899 u16 fll_loop_gain;
1900 u16 fll_ref_freq;
1901 u16 n;
1902 u16 theta;
1903 u16 lambda;
1904};
1905
1906static struct {
1907 unsigned int min;
1908 unsigned int max;
1909 u16 fll_fratio;
1910 int ratio;
1911} fll_fratios[] = {
1912 { 0, 64000, 4, 16 },
1913 { 64000, 128000, 3, 8 },
1914 { 128000, 256000, 2, 4 },
1915 { 256000, 1000000, 1, 2 },
1916 { 1000000, 13500000, 0, 1 },
1917};
1918
1919static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1920 unsigned int Fout)
1921{
1922 unsigned int target;
1923 unsigned int div;
1924 unsigned int fratio, gcd_fll;
1925 int i;
1926
1927 /* Fref must be <=13.5MHz */
1928 div = 1;
1929 fll_div->fll_refclk_div = 0;
1930 while ((Fref / div) > 13500000) {
1931 div *= 2;
1932 fll_div->fll_refclk_div++;
1933
1934 if (div > 8) {
1935 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1936 Fref);
1937 return -EINVAL;
1938 }
1939 }
1940
1941 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1942
1943 /* Apply the division for our remaining calculations */
1944 Fref /= div;
1945
1946 if (Fref >= 3000000)
1947 fll_div->fll_loop_gain = 5;
1948 else
1949 fll_div->fll_loop_gain = 0;
1950
1951 if (Fref >= 48000)
1952 fll_div->fll_ref_freq = 0;
1953 else
1954 fll_div->fll_ref_freq = 1;
1955
1956 /* Fvco should be 90-100MHz; don't check the upper bound */
1957 div = 2;
1958 while (Fout * div < 90000000) {
1959 div++;
1960 if (div > 64) {
1961 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1962 Fout);
1963 return -EINVAL;
1964 }
1965 }
1966 target = Fout * div;
1967 fll_div->fll_outdiv = div - 1;
1968
1969 pr_debug("FLL Fvco=%dHz\n", target);
1970
1971 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1972 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1973 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1974 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1975 fratio = fll_fratios[i].ratio;
1976 break;
1977 }
1978 }
1979 if (i == ARRAY_SIZE(fll_fratios)) {
1980 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1981 return -EINVAL;
1982 }
1983
1984 fll_div->n = target / (fratio * Fref);
1985
1986 if (target % Fref == 0) {
1987 fll_div->theta = 0;
1988 fll_div->lambda = 0;
1989 } else {
1990 gcd_fll = gcd(target, fratio * Fref);
1991
1992 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1993 / gcd_fll;
1994 fll_div->lambda = (fratio * Fref) / gcd_fll;
1995 }
1996
1997 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1998 fll_div->n, fll_div->theta, fll_div->lambda);
1999 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2000 fll_div->fll_fratio, fll_div->fll_outdiv,
2001 fll_div->fll_refclk_div);
2002
2003 return 0;
2004}
2005
01b07e2d 2006static int wm8915_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
c93993ac
MB		 2007 unsigned int Fref, unsigned int Fout)
2008{
c93993ac
MB		 2009 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2010 struct _fll_div fll_div;
2011 unsigned long timeout;
2012 int ret, reg;
2013
2014 /* Any change? */
2015 if (source == wm8915->fll_src && Fref == wm8915->fll_fref &&
2016 Fout == wm8915->fll_fout)
2017 return 0;
2018
2019 if (Fout == 0) {
2020 dev_dbg(codec->dev, "FLL disabled\n");
2021
2022 wm8915->fll_fref = 0;
2023 wm8915->fll_fout = 0;
2024
2025 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2026 WM8915_FLL_ENA, 0);
2027
2028 return 0;
2029 }
2030
2031 ret = fll_factors(&fll_div, Fref, Fout);
2032 if (ret != 0)
2033 return ret;
2034
2035 switch (source) {
2036 case WM8915_FLL_MCLK1:
2037 reg = 0;
2038 break;
2039 case WM8915_FLL_MCLK2:
2040 reg = 1;
2041 case WM8915_FLL_DACLRCLK1:
2042 reg = 2;
2043 break;
2044 case WM8915_FLL_BCLK1:
2045 reg = 3;
2046 break;
2047 default:
2048 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2049 return -EINVAL;
2050 }
2051
2052 reg |= fll_div.fll_refclk_div << WM8915_FLL_REFCLK_DIV_SHIFT;
2053 reg |= fll_div.fll_ref_freq << WM8915_FLL_REF_FREQ_SHIFT;
2054
2055 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_5,
2056 WM8915_FLL_REFCLK_DIV_MASK | WM8915_FLL_REF_FREQ |
2057 WM8915_FLL_REFCLK_SRC_MASK, reg);
2058
2059 reg = 0;
2060 if (fll_div.theta || fll_div.lambda)
2061 reg |= WM8915_FLL_EFS_ENA | (3 << WM8915_FLL_LFSR_SEL_SHIFT);
2062 else
2063 reg |= 1 << WM8915_FLL_LFSR_SEL_SHIFT;
2064 snd_soc_write(codec, WM8915_FLL_EFS_2, reg);
2065
2066 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_2,
2067 WM8915_FLL_OUTDIV_MASK |
2068 WM8915_FLL_FRATIO_MASK,
2069 (fll_div.fll_outdiv << WM8915_FLL_OUTDIV_SHIFT) |
2070 (fll_div.fll_fratio));
2071
2072 snd_soc_write(codec, WM8915_FLL_CONTROL_3, fll_div.theta);
2073
2074 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_4,
2075 WM8915_FLL_N_MASK | WM8915_FLL_LOOP_GAIN_MASK,
2076 (fll_div.n << WM8915_FLL_N_SHIFT) |
2077 fll_div.fll_loop_gain);
2078
2079 snd_soc_write(codec, WM8915_FLL_EFS_1, fll_div.lambda);
2080
2081 snd_soc_update_bits(codec, WM8915_FLL_CONTROL_1,
2082 WM8915_FLL_ENA, WM8915_FLL_ENA);
2083
2084 /* The FLL supports live reconfiguration - kick that in case we were
2085 * already enabled.
2086 */
2087 snd_soc_write(codec, WM8915_FLL_CONTROL_6, WM8915_FLL_SWITCH_CLK);
2088
2089 /* Wait for the FLL to lock, using the interrupt if possible */
2090 if (Fref > 1000000)
2091 timeout = usecs_to_jiffies(300);
2092 else
2093 timeout = msecs_to_jiffies(2);
2094
2095 wait_for_completion_timeout(&wm8915->fll_lock, timeout);
2096
2097 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2098
2099 wm8915->fll_fref = Fref;
2100 wm8915->fll_fout = Fout;
2101 wm8915->fll_src = source;
2102
2103 return 0;
2104}
2105
2106#ifdef CONFIG_GPIOLIB
2107static inline struct wm8915_priv *gpio_to_wm8915(struct gpio_chip *chip)
2108{
2109 return container_of(chip, struct wm8915_priv, gpio_chip);
2110}
2111
2112static void wm8915_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2113{
2114 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2115 struct snd_soc_codec *codec = wm8915->codec;
2116
2117 snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2118 WM8915_GP1_LVL, !!value << WM8915_GP1_LVL_SHIFT);
2119}
2120
2121static int wm8915_gpio_direction_out(struct gpio_chip *chip,
2122 unsigned offset, int value)
2123{
2124 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2125 struct snd_soc_codec *codec = wm8915->codec;
2126 int val;
2127
2128 val = (1 << WM8915_GP1_FN_SHIFT) | (!!value << WM8915_GP1_LVL_SHIFT);
2129
2130 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2131 WM8915_GP1_FN_MASK | WM8915_GP1_DIR |
2132 WM8915_GP1_LVL, val);
2133}
2134
2135static int wm8915_gpio_get(struct gpio_chip *chip, unsigned offset)
2136{
2137 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2138 struct snd_soc_codec *codec = wm8915->codec;
2139 int ret;
2140
2141 ret = snd_soc_read(codec, WM8915_GPIO_1 + offset);
2142 if (ret < 0)
2143 return ret;
2144
2145 return (ret & WM8915_GP1_LVL) != 0;
2146}
2147
2148static int wm8915_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2149{
2150 struct wm8915_priv *wm8915 = gpio_to_wm8915(chip);
2151 struct snd_soc_codec *codec = wm8915->codec;
2152
2153 return snd_soc_update_bits(codec, WM8915_GPIO_1 + offset,
2154 WM8915_GP1_FN_MASK | WM8915_GP1_DIR,
2155 (1 << WM8915_GP1_FN_SHIFT) |
2156 (1 << WM8915_GP1_DIR_SHIFT));
2157}
2158
2159static struct gpio_chip wm8915_template_chip = {
2160 .label = "wm8915",
2161 .owner = THIS_MODULE,
2162 .direction_output = wm8915_gpio_direction_out,
2163 .set = wm8915_gpio_set,
2164 .direction_input = wm8915_gpio_direction_in,
2165 .get = wm8915_gpio_get,
2166 .can_sleep = 1,
2167};
2168
2169static void wm8915_init_gpio(struct snd_soc_codec *codec)
2170{
2171 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2172 int ret;
2173
2174 wm8915->gpio_chip = wm8915_template_chip;
2175 wm8915->gpio_chip.ngpio = 5;
2176 wm8915->gpio_chip.dev = codec->dev;
2177
2178 if (wm8915->pdata.gpio_base)
2179 wm8915->gpio_chip.base = wm8915->pdata.gpio_base;
2180 else
2181 wm8915->gpio_chip.base = -1;
2182
2183 ret = gpiochip_add(&wm8915->gpio_chip);
2184 if (ret != 0)
2185 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2186}
2187
2188static void wm8915_free_gpio(struct snd_soc_codec *codec)
2189{
2190 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2191 int ret;
2192
2193 ret = gpiochip_remove(&wm8915->gpio_chip);
2194 if (ret != 0)
2195 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2196}
2197#else
2198static void wm8915_init_gpio(struct snd_soc_codec *codec)
2199{
2200}
2201
2202static void wm8915_free_gpio(struct snd_soc_codec *codec)
2203{
2204}
2205#endif
2206
2207/**
2208 * wm8915_detect - Enable default WM8915 jack detection
2209 *
2210 * The WM8915 has advanced accessory detection support for headsets.
2211 * This function provides a default implementation which integrates
2212 * the majority of this functionality with minimal user configuration.
2213 *
2214 * This will detect headset, headphone and short circuit button and
2215 * will also detect inverted microphone ground connections and update
2216 * the polarity of the connections.
2217 */
2218int wm8915_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2219 wm8915_polarity_fn polarity_cb)
2220{
2221 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2222
2223 wm8915->jack = jack;
2224 wm8915->detecting = true;
2225 wm8915->polarity_cb = polarity_cb;
2226
2227 if (wm8915->polarity_cb)
2228 wm8915->polarity_cb(codec, 0);
2229
2230 /* Clear discarge to avoid noise during detection */
2231 snd_soc_update_bits(codec, WM8915_MICBIAS_1,
2232 WM8915_MICB1_DISCH, 0);
2233 snd_soc_update_bits(codec, WM8915_MICBIAS_2,
2234 WM8915_MICB2_DISCH, 0);
2235
2236 /* LDO2 powers the microphones, SYSCLK clocks detection */
2237 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2238 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2239
2240 /* We start off just enabling microphone detection - even a
2241 * plain headphone will trigger detection.
2242 */
2243 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2244 WM8915_MICD_ENA, WM8915_MICD_ENA);
2245
2246 /* Slowest detection rate, gives debounce for initial detection */
2247 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2248 WM8915_MICD_RATE_MASK,
2249 WM8915_MICD_RATE_MASK);
2250
2251 /* Enable interrupts and we're off */
2252 snd_soc_update_bits(codec, WM8915_INTERRUPT_STATUS_2_MASK,
2253 WM8915_IM_MICD_EINT, 0);
2254
2255 return 0;
2256}
2257EXPORT_SYMBOL_GPL(wm8915_detect);
2258
2259static void wm8915_micd(struct snd_soc_codec *codec)
2260{
2261 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2262 int val, reg;
2263
2264 val = snd_soc_read(codec, WM8915_MIC_DETECT_3);
2265
2266 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2267
2268 if (!(val & WM8915_MICD_VALID)) {
2269 dev_warn(codec->dev, "Microphone detection state invalid\n");
2270 return;
2271 }
2272
2273 /* No accessory, reset everything and report removal */
2274 if (!(val & WM8915_MICD_STS)) {
2275 dev_dbg(codec->dev, "Jack removal detected\n");
2276 wm8915->jack_mic = false;
2277 wm8915->detecting = true;
2278 snd_soc_jack_report(wm8915->jack, 0,
2279 SND_JACK_HEADSET | SND_JACK_BTN_0);
2280 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2281 WM8915_MICD_RATE_MASK,
2282 WM8915_MICD_RATE_MASK);
2283 return;
2284 }
2285
2286 /* If the measurement is very high we've got a microphone but
2287 * do a little debounce to account for mechanical issues.
2288 */
2289 if (val & 0x400) {
2290 dev_dbg(codec->dev, "Microphone detected\n");
2291 snd_soc_jack_report(wm8915->jack, SND_JACK_HEADSET,
2292 SND_JACK_HEADSET | SND_JACK_BTN_0);
2293 wm8915->jack_mic = true;
2294 wm8915->detecting = false;
2295 }
2296
2297 /* If we detected a lower impedence during initial startup
2298 * then we probably have the wrong polarity, flip it. Don't
2299 * do this for the lowest impedences to speed up detection of
2300 * plain headphones.
2301 */
2302 if (wm8915->detecting && (val & 0x3f0)) {
2303 reg = snd_soc_read(codec, WM8915_ACCESSORY_DETECT_MODE_2);
2304 reg ^= WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2305 WM8915_MICD_BIAS_SRC;
2306 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2307 WM8915_HPOUT1FB_SRC | WM8915_MICD_SRC |
2308 WM8915_MICD_BIAS_SRC, reg);
2309
2310 if (wm8915->polarity_cb)
2311 wm8915->polarity_cb(codec,
2312 (reg & WM8915_MICD_SRC) != 0);
2313
2314 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2315 (reg & WM8915_MICD_SRC) != 0);
2316
2317 return;
2318 }
2319
2320 /* Don't distinguish between buttons, just report any low
2321 * impedence as BTN_0.
2322 */
2323 if (val & 0x3fc) {
2324 if (wm8915->jack_mic) {
2325 dev_dbg(codec->dev, "Mic button detected\n");
2326 snd_soc_jack_report(wm8915->jack,
2327 SND_JACK_HEADSET | SND_JACK_BTN_0,
2328 SND_JACK_HEADSET | SND_JACK_BTN_0);
2329 } else {
2330 dev_dbg(codec->dev, "Headphone detected\n");
2331 snd_soc_jack_report(wm8915->jack,
2332 SND_JACK_HEADPHONE,
2333 SND_JACK_HEADSET |
2334 SND_JACK_BTN_0);
2335 wm8915->detecting = false;
2336 }
2337 }
2338
2339 /* Increase poll rate to give better responsiveness for buttons */
2340 if (!wm8915->detecting)
2341 snd_soc_update_bits(codec, WM8915_MIC_DETECT_1,
2342 WM8915_MICD_RATE_MASK,
2343 5 << WM8915_MICD_RATE_SHIFT);
2344}
2345
2346static irqreturn_t wm8915_irq(int irq, void *data)
2347{
2348 struct snd_soc_codec *codec = data;
2349 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2350 int irq_val;
2351
2352 irq_val = snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2);
2353 if (irq_val < 0) {
2354 dev_err(codec->dev, "Failed to read IRQ status: %d\n",
2355 irq_val);
2356 return IRQ_NONE;
2357 }
2358 irq_val &= ~snd_soc_read(codec, WM8915_INTERRUPT_STATUS_2_MASK);
2359
2360 if (irq_val & (WM8915_DCS_DONE_01_EINT | WM8915_DCS_DONE_23_EINT)) {
2361 dev_dbg(codec->dev, "DC servo IRQ\n");
2362 complete(&wm8915->dcs_done);
2363 }
2364
2365 if (irq_val & WM8915_FIFOS_ERR_EINT)
2366 dev_err(codec->dev, "Digital core FIFO error\n");
2367
2368 if (irq_val & WM8915_FLL_LOCK_EINT) {
2369 dev_dbg(codec->dev, "FLL locked\n");
2370 complete(&wm8915->fll_lock);
2371 }
2372
2373 if (irq_val & WM8915_MICD_EINT)
2374 wm8915_micd(codec);
2375
2376 if (irq_val) {
2377 snd_soc_write(codec, WM8915_INTERRUPT_STATUS_2, irq_val);
2378
2379 return IRQ_HANDLED;
2380 } else {
2381 return IRQ_NONE;
2382 }
2383}
2384
a1e9adc0
MB		 2385static irqreturn_t wm8915_edge_irq(int irq, void *data)
2386{
2387 irqreturn_t ret = IRQ_NONE;
2388 irqreturn_t val;
2389
2390 do {
2391 val = wm8915_irq(irq, data);
2392 if (val != IRQ_NONE)
2393 ret = val;
2394 } while (val != IRQ_NONE);
2395
2396 return ret;
2397}
2398
c93993ac
MB		 2399static void wm8915_retune_mobile_pdata(struct snd_soc_codec *codec)
2400{
2401 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2402 struct wm8915_pdata *pdata = &wm8915->pdata;
2403
2404 struct snd_kcontrol_new controls[] = {
2405 SOC_ENUM_EXT("DSP1 EQ Mode",
2406 wm8915->retune_mobile_enum,
2407 wm8915_get_retune_mobile_enum,
2408 wm8915_put_retune_mobile_enum),
2409 SOC_ENUM_EXT("DSP2 EQ Mode",
2410 wm8915->retune_mobile_enum,
2411 wm8915_get_retune_mobile_enum,
2412 wm8915_put_retune_mobile_enum),
2413 };
2414 int ret, i, j;
2415 const char **t;
2416
2417 /* We need an array of texts for the enum API but the number
2418 * of texts is likely to be less than the number of
2419 * configurations due to the sample rate dependency of the
2420 * configurations. */
2421 wm8915->num_retune_mobile_texts = 0;
2422 wm8915->retune_mobile_texts = NULL;
2423 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2424 for (j = 0; j < wm8915->num_retune_mobile_texts; j++) {
2425 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2426 wm8915->retune_mobile_texts[j]) == 0)
2427 break;
2428 }
2429
2430 if (j != wm8915->num_retune_mobile_texts)
2431 continue;
2432
2433 /* Expand the array... */
2434 t = krealloc(wm8915->retune_mobile_texts,
2435 sizeof(char *) *
2436 (wm8915->num_retune_mobile_texts + 1),
2437 GFP_KERNEL);
2438 if (t == NULL)
2439 continue;
2440
2441 /* ...store the new entry... */
2442 t[wm8915->num_retune_mobile_texts] =
2443 pdata->retune_mobile_cfgs[i].name;
2444
2445 /* ...and remember the new version. */
2446 wm8915->num_retune_mobile_texts++;
2447 wm8915->retune_mobile_texts = t;
2448 }
2449
2450 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2451 wm8915->num_retune_mobile_texts);
2452
2453 wm8915->retune_mobile_enum.max = wm8915->num_retune_mobile_texts;
2454 wm8915->retune_mobile_enum.texts = wm8915->retune_mobile_texts;
2455
2456 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls));
2457 if (ret != 0)
2458 dev_err(codec->dev,
2459 "Failed to add ReTune Mobile controls: %d\n", ret);
2460}
2461
2462static int wm8915_probe(struct snd_soc_codec *codec)
2463{
2464 int ret;
2465 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2466 struct i2c_client *i2c = to_i2c_client(codec->dev);
2467 struct snd_soc_dapm_context *dapm = &codec->dapm;
2468 int i, irq_flags;
2469
2470 wm8915->codec = codec;
2471
2472 init_completion(&wm8915->dcs_done);
2473 init_completion(&wm8915->fll_lock);
2474
2475 dapm->idle_bias_off = true;
2476 dapm->bias_level = SND_SOC_BIAS_OFF;
2477
2478 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2479 if (ret != 0) {
2480 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2481 goto err;
2482 }
2483
2484 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2485 wm8915->supplies[i].supply = wm8915_supply_names[i];
2486
2487 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8915->supplies),
2488 wm8915->supplies);
2489 if (ret != 0) {
2490 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
2491 goto err;
2492 }
2493
2494 wm8915->disable_nb[0].notifier_call = wm8915_regulator_event_0;
2495 wm8915->disable_nb[1].notifier_call = wm8915_regulator_event_1;
2496 wm8915->disable_nb[2].notifier_call = wm8915_regulator_event_2;
2497 wm8915->disable_nb[3].notifier_call = wm8915_regulator_event_3;
2498 wm8915->disable_nb[4].notifier_call = wm8915_regulator_event_4;
2499 wm8915->disable_nb[5].notifier_call = wm8915_regulator_event_5;
2500
2501 /* This should really be moved into the regulator core */
2502 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++) {
2503 ret = regulator_register_notifier(wm8915->supplies[i].consumer,
2504 &wm8915->disable_nb[i]);
2505 if (ret != 0) {
2506 dev_err(codec->dev,
2507 "Failed to register regulator notifier: %d\n",
2508 ret);
2509 }
2510 }
2511
2512 ret = regulator_bulk_enable(ARRAY_SIZE(wm8915->supplies),
2513 wm8915->supplies);
2514 if (ret != 0) {
2515 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
2516 goto err_get;
2517 }
2518
2519 if (wm8915->pdata.ldo_ena >= 0) {
2520 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 1);
2521 msleep(5);
2522 }
2523
2524 ret = snd_soc_read(codec, WM8915_SOFTWARE_RESET);
2525 if (ret < 0) {
2526 dev_err(codec->dev, "Failed to read ID register: %d\n", ret);
2527 goto err_enable;
2528 }
2529 if (ret != 0x8915) {
2530 dev_err(codec->dev, "Device is not a WM8915, ID %x\n", ret);
2531 ret = -EINVAL;
2532 goto err_enable;
2533 }
2534
2535 ret = snd_soc_read(codec, WM8915_CHIP_REVISION);
2536 if (ret < 0) {
2537 dev_err(codec->dev, "Failed to read device revision: %d\n",
2538 ret);
2539 goto err_enable;
2540 }
2541
2542 dev_info(codec->dev, "revision %c\n",
2543 (ret & WM8915_CHIP_REV_MASK) + 'A');
2544
2545 if (wm8915->pdata.ldo_ena >= 0) {
2546 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2547 } else {
2548 ret = wm8915_reset(codec);
2549 if (ret < 0) {
2550 dev_err(codec->dev, "Failed to issue reset\n");
2551 goto err_enable;
2552 }
2553 }
2554
2555 codec->cache_only = true;
2556
2557 /* Apply platform data settings */
2558 snd_soc_update_bits(codec, WM8915_LINE_INPUT_CONTROL,
2559 WM8915_INL_MODE_MASK | WM8915_INR_MODE_MASK,
2560 wm8915->pdata.inl_mode << WM8915_INL_MODE_SHIFT |
2561 wm8915->pdata.inr_mode);
2562
2563 for (i = 0; i < ARRAY_SIZE(wm8915->pdata.gpio_default); i++) {
2564 if (!wm8915->pdata.gpio_default[i])
2565 continue;
2566
2567 snd_soc_write(codec, WM8915_GPIO_1 + i,
2568 wm8915->pdata.gpio_default[i] & 0xffff);
2569 }
2570
2571 if (wm8915->pdata.spkmute_seq)
2572 snd_soc_update_bits(codec, WM8915_PDM_SPEAKER_MUTE_SEQUENCE,
2573 WM8915_SPK_MUTE_ENDIAN |
2574 WM8915_SPK_MUTE_SEQ1_MASK,
2575 wm8915->pdata.spkmute_seq);
2576
2577 snd_soc_update_bits(codec, WM8915_ACCESSORY_DETECT_MODE_2,
2578 WM8915_MICD_BIAS_SRC | WM8915_HPOUT1FB_SRC |
2579 WM8915_MICD_SRC, wm8915->pdata.micdet_def);
2580
2581 /* Latch volume update bits */
2582 snd_soc_update_bits(codec, WM8915_LEFT_LINE_INPUT_VOLUME,
2583 WM8915_IN1_VU, WM8915_IN1_VU);
2584 snd_soc_update_bits(codec, WM8915_RIGHT_LINE_INPUT_VOLUME,
2585 WM8915_IN1_VU, WM8915_IN1_VU);
2586
2587 snd_soc_update_bits(codec, WM8915_DAC1_LEFT_VOLUME,
2588 WM8915_DAC1_VU, WM8915_DAC1_VU);
2589 snd_soc_update_bits(codec, WM8915_DAC1_RIGHT_VOLUME,
2590 WM8915_DAC1_VU, WM8915_DAC1_VU);
2591 snd_soc_update_bits(codec, WM8915_DAC2_LEFT_VOLUME,
2592 WM8915_DAC2_VU, WM8915_DAC2_VU);
2593 snd_soc_update_bits(codec, WM8915_DAC2_RIGHT_VOLUME,
2594 WM8915_DAC2_VU, WM8915_DAC2_VU);
2595
2596 snd_soc_update_bits(codec, WM8915_OUTPUT1_LEFT_VOLUME,
2597 WM8915_DAC1_VU, WM8915_DAC1_VU);
2598 snd_soc_update_bits(codec, WM8915_OUTPUT1_RIGHT_VOLUME,
2599 WM8915_DAC1_VU, WM8915_DAC1_VU);
2600 snd_soc_update_bits(codec, WM8915_OUTPUT2_LEFT_VOLUME,
2601 WM8915_DAC2_VU, WM8915_DAC2_VU);
2602 snd_soc_update_bits(codec, WM8915_OUTPUT2_RIGHT_VOLUME,
2603 WM8915_DAC2_VU, WM8915_DAC2_VU);
2604
2605 snd_soc_update_bits(codec, WM8915_DSP1_TX_LEFT_VOLUME,
2606 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2607 snd_soc_update_bits(codec, WM8915_DSP1_TX_RIGHT_VOLUME,
2608 WM8915_DSP1TX_VU, WM8915_DSP1TX_VU);
2609 snd_soc_update_bits(codec, WM8915_DSP2_TX_LEFT_VOLUME,
2610 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2611 snd_soc_update_bits(codec, WM8915_DSP2_TX_RIGHT_VOLUME,
2612 WM8915_DSP2TX_VU, WM8915_DSP2TX_VU);
2613
2614 snd_soc_update_bits(codec, WM8915_DSP1_RX_LEFT_VOLUME,
2615 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2616 snd_soc_update_bits(codec, WM8915_DSP1_RX_RIGHT_VOLUME,
2617 WM8915_DSP1RX_VU, WM8915_DSP1RX_VU);
2618 snd_soc_update_bits(codec, WM8915_DSP2_RX_LEFT_VOLUME,
2619 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2620 snd_soc_update_bits(codec, WM8915_DSP2_RX_RIGHT_VOLUME,
2621 WM8915_DSP2RX_VU, WM8915_DSP2RX_VU);
2622
2623 /* No support currently for the underclocked TDM modes and
2624 * pick a default TDM layout with each channel pair working with
2625 * slots 0 and 1. */
2626 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_0_CONFIGURATION,
2627 WM8915_AIF1RX_CHAN0_SLOTS_MASK |
2628 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2629 1 << WM8915_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2630 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_1_CONFIGURATION,
2631 WM8915_AIF1RX_CHAN1_SLOTS_MASK |
2632 WM8915_AIF1RX_CHAN1_START_SLOT_MASK,
2633 1 << WM8915_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2634 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_2_CONFIGURATION,
2635 WM8915_AIF1RX_CHAN2_SLOTS_MASK |
2636 WM8915_AIF1RX_CHAN2_START_SLOT_MASK,
2637 1 << WM8915_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2638 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_3_CONFIGURATION,
2639 WM8915_AIF1RX_CHAN3_SLOTS_MASK |
2640 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2641 1 << WM8915_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2642 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_4_CONFIGURATION,
2643 WM8915_AIF1RX_CHAN4_SLOTS_MASK |
2644 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2645 1 << WM8915_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2646 snd_soc_update_bits(codec, WM8915_AIF1RX_CHANNEL_5_CONFIGURATION,
2647 WM8915_AIF1RX_CHAN5_SLOTS_MASK |
2648 WM8915_AIF1RX_CHAN0_START_SLOT_MASK,
2649 1 << WM8915_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2650
2651 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_0_CONFIGURATION,
2652 WM8915_AIF2RX_CHAN0_SLOTS_MASK |
2653 WM8915_AIF2RX_CHAN0_START_SLOT_MASK,
2654 1 << WM8915_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2655 snd_soc_update_bits(codec, WM8915_AIF2RX_CHANNEL_1_CONFIGURATION,
2656 WM8915_AIF2RX_CHAN1_SLOTS_MASK |
2657 WM8915_AIF2RX_CHAN1_START_SLOT_MASK,
2658 1 << WM8915_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2659
2660 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_0_CONFIGURATION,
2661 WM8915_AIF1TX_CHAN0_SLOTS_MASK |
2662 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2663 1 << WM8915_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2664 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2665 WM8915_AIF1TX_CHAN1_SLOTS_MASK |
2666 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2667 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2668 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_2_CONFIGURATION,
2669 WM8915_AIF1TX_CHAN2_SLOTS_MASK |
2670 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2671 1 << WM8915_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2672 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_3_CONFIGURATION,
2673 WM8915_AIF1TX_CHAN3_SLOTS_MASK |
2674 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2675 1 << WM8915_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2676 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_4_CONFIGURATION,
2677 WM8915_AIF1TX_CHAN4_SLOTS_MASK |
2678 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2679 1 << WM8915_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
2680 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_5_CONFIGURATION,
2681 WM8915_AIF1TX_CHAN5_SLOTS_MASK |
2682 WM8915_AIF1TX_CHAN0_START_SLOT_MASK,
2683 1 << WM8915_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
2684
2685 snd_soc_update_bits(codec, WM8915_AIF2TX_CHANNEL_0_CONFIGURATION,
2686 WM8915_AIF2TX_CHAN0_SLOTS_MASK |
2687 WM8915_AIF2TX_CHAN0_START_SLOT_MASK,
2688 1 << WM8915_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
2689 snd_soc_update_bits(codec, WM8915_AIF1TX_CHANNEL_1_CONFIGURATION,
2690 WM8915_AIF2TX_CHAN1_SLOTS_MASK |
2691 WM8915_AIF2TX_CHAN1_START_SLOT_MASK,
2692 1 << WM8915_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2693
2694 if (wm8915->pdata.num_retune_mobile_cfgs)
2695 wm8915_retune_mobile_pdata(codec);
2696 else
2697 snd_soc_add_controls(codec, wm8915_eq_controls,
2698 ARRAY_SIZE(wm8915_eq_controls));
2699
2700 /* If the TX LRCLK pins are not in LRCLK mode configure the
2701 * AIFs to source their clocks from the RX LRCLKs.
2702 */
2703 if ((snd_soc_read(codec, WM8915_GPIO_1)))
2704 snd_soc_update_bits(codec, WM8915_AIF1_TX_LRCLK_2,
2705 WM8915_AIF1TX_LRCLK_MODE,
2706 WM8915_AIF1TX_LRCLK_MODE);
2707
2708 if ((snd_soc_read(codec, WM8915_GPIO_2)))
2709 snd_soc_update_bits(codec, WM8915_AIF2_TX_LRCLK_2,
2710 WM8915_AIF2TX_LRCLK_MODE,
2711 WM8915_AIF2TX_LRCLK_MODE);
2712
2713 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2714
2715 wm8915_init_gpio(codec);
2716
2717 if (i2c->irq) {
2718 if (wm8915->pdata.irq_flags)
2719 irq_flags = wm8915->pdata.irq_flags;
2720 else
2721 irq_flags = IRQF_TRIGGER_LOW;
2722
2723 irq_flags |= IRQF_ONESHOT;
2724
a1e9adc0
MB		 2725 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2726 ret = request_threaded_irq(i2c->irq, NULL,
2727 wm8915_edge_irq,
2728 irq_flags, "wm8915", codec);
2729 else
2730 ret = request_threaded_irq(i2c->irq, NULL, wm8915_irq,
2731 irq_flags, "wm8915", codec);
2732
c93993ac
MB		 2733 if (ret == 0) {
2734 /* Unmask the interrupt */
2735 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2736 WM8915_IM_IRQ, 0);
2737
2738 /* Enable error reporting and DC servo status */
2739 snd_soc_update_bits(codec,
2740 WM8915_INTERRUPT_STATUS_2_MASK,
2741 WM8915_IM_DCS_DONE_23_EINT |
2742 WM8915_IM_DCS_DONE_01_EINT |
2743 WM8915_IM_FLL_LOCK_EINT |
2744 WM8915_IM_FIFOS_ERR_EINT,
2745 0);
2746 } else {
2747 dev_err(codec->dev, "Failed to request IRQ: %d\n",
2748 ret);
2749 }
2750 }
2751
2752 return 0;
2753
2754err_enable:
2755 if (wm8915->pdata.ldo_ena >= 0)
2756 gpio_set_value_cansleep(wm8915->pdata.ldo_ena, 0);
2757
2758 regulator_bulk_disable(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2759err_get:
2760 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2761err:
2762 return ret;
2763}
2764
2765static int wm8915_remove(struct snd_soc_codec *codec)
2766{
2767 struct wm8915_priv *wm8915 = snd_soc_codec_get_drvdata(codec);
2768 struct i2c_client *i2c = to_i2c_client(codec->dev);
2769 int i;
2770
2771 snd_soc_update_bits(codec, WM8915_INTERRUPT_CONTROL,
2772 WM8915_IM_IRQ, WM8915_IM_IRQ);
2773
2774 if (i2c->irq)
2775 free_irq(i2c->irq, codec);
2776
2777 wm8915_free_gpio(codec);
2778
2779 for (i = 0; i < ARRAY_SIZE(wm8915->supplies); i++)
2780 regulator_unregister_notifier(wm8915->supplies[i].consumer,
2781 &wm8915->disable_nb[i]);
2782 regulator_bulk_free(ARRAY_SIZE(wm8915->supplies), wm8915->supplies);
2783
2784 return 0;
2785}
2786
2787static struct snd_soc_codec_driver soc_codec_dev_wm8915 = {
2788 .probe = wm8915_probe,
2789 .remove = wm8915_remove,
2790 .set_bias_level = wm8915_set_bias_level,
2791 .seq_notifier = wm8915_seq_notifier,
2792 .reg_cache_size = WM8915_MAX_REGISTER + 1,
2793 .reg_word_size = sizeof(u16),
2794 .reg_cache_default = wm8915_reg,
2795 .volatile_register = wm8915_volatile_register,
2796 .readable_register = wm8915_readable_register,
2797 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2798 .controls = wm8915_snd_controls,
2799 .num_controls = ARRAY_SIZE(wm8915_snd_controls),
2800 .dapm_widgets = wm8915_dapm_widgets,
2801 .num_dapm_widgets = ARRAY_SIZE(wm8915_dapm_widgets),
2802 .dapm_routes = wm8915_dapm_routes,
2803 .num_dapm_routes = ARRAY_SIZE(wm8915_dapm_routes),
01b07e2d 2804 .set_pll = wm8915_set_fll,
c93993ac
MB		 2805};
2806
2807#define WM8915_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2808 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000)
2809#define WM8915_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2810 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2811 SNDRV_PCM_FMTBIT_S32_LE)
2812
2813static struct snd_soc_dai_ops wm8915_dai_ops = {
2814 .set_fmt = wm8915_set_fmt,
2815 .hw_params = wm8915_hw_params,
2816 .set_sysclk = wm8915_set_sysclk,
c93993ac
MB		 2817};
2818
2819static struct snd_soc_dai_driver wm8915_dai[] = {
2820 {
2821 .name = "wm8915-aif1",
2822 .playback = {
2823 .stream_name = "AIF1 Playback",
2824 .channels_min = 1,
2825 .channels_max = 6,
2826 .rates = WM8915_RATES,
2827 .formats = WM8915_FORMATS,
2828 },
2829 .capture = {
2830 .stream_name = "AIF1 Capture",
2831 .channels_min = 1,
2832 .channels_max = 6,
2833 .rates = WM8915_RATES,
2834 .formats = WM8915_FORMATS,
2835 },
2836 .ops = &wm8915_dai_ops,
2837 },
2838 {
2839 .name = "wm8915-aif2",
2840 .playback = {
2841 .stream_name = "AIF2 Playback",
2842 .channels_min = 1,
2843 .channels_max = 2,
2844 .rates = WM8915_RATES,
2845 .formats = WM8915_FORMATS,
2846 },
2847 .capture = {
2848 .stream_name = "AIF2 Capture",
2849 .channels_min = 1,
2850 .channels_max = 2,
2851 .rates = WM8915_RATES,
2852 .formats = WM8915_FORMATS,
2853 },
2854 .ops = &wm8915_dai_ops,
2855 },
2856};
2857
2858static __devinit int wm8915_i2c_probe(struct i2c_client *i2c,
2859 const struct i2c_device_id *id)
2860{
2861 struct wm8915_priv *wm8915;
2862 int ret;
2863
2864 wm8915 = kzalloc(sizeof(struct wm8915_priv), GFP_KERNEL);
2865 if (wm8915 == NULL)
2866 return -ENOMEM;
2867
2868 i2c_set_clientdata(i2c, wm8915);
2869
2870 if (dev_get_platdata(&i2c->dev))
2871 memcpy(&wm8915->pdata, dev_get_platdata(&i2c->dev),
2872 sizeof(wm8915->pdata));
2873
2874 if (wm8915->pdata.ldo_ena > 0) {
2875 ret = gpio_request_one(wm8915->pdata.ldo_ena,
2876 GPIOF_OUT_INIT_LOW, "WM8915 ENA");
2877 if (ret < 0) {
2878 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2879 wm8915->pdata.ldo_ena, ret);
2880 goto err;
2881 }
2882 }
2883
2884 ret = snd_soc_register_codec(&i2c->dev,
2885 &soc_codec_dev_wm8915, wm8915_dai,
2886 ARRAY_SIZE(wm8915_dai));
2887 if (ret < 0)
2888 goto err_gpio;
2889
2890 return ret;
2891
2892err_gpio:
2893 if (wm8915->pdata.ldo_ena > 0)
2894 gpio_free(wm8915->pdata.ldo_ena);
2895err:
2896 kfree(wm8915);
2897
2898 return ret;
2899}
2900
2901static __devexit int wm8915_i2c_remove(struct i2c_client *client)
2902{
2903 struct wm8915_priv *wm8915 = i2c_get_clientdata(client);
2904
2905 snd_soc_unregister_codec(&client->dev);
2906 if (wm8915->pdata.ldo_ena > 0)
2907 gpio_free(wm8915->pdata.ldo_ena);
2908 kfree(i2c_get_clientdata(client));
2909 return 0;
2910}
2911
2912static const struct i2c_device_id wm8915_i2c_id[] = {
2913 { "wm8915", 0 },
2914 { }
2915};
2916MODULE_DEVICE_TABLE(i2c, wm8915_i2c_id);
2917
2918static struct i2c_driver wm8915_i2c_driver = {
2919 .driver = {
2920 .name = "wm8915",
2921 .owner = THIS_MODULE,
2922 },
2923 .probe = wm8915_i2c_probe,
2924 .remove = __devexit_p(wm8915_i2c_remove),
2925 .id_table = wm8915_i2c_id,
2926};
2927
2928static int __init wm8915_modinit(void)
2929{
2930 int ret;
2931
2932 ret = i2c_add_driver(&wm8915_i2c_driver);
2933 if (ret != 0) {
2934 printk(KERN_ERR "Failed to register WM8915 I2C driver: %d\n",
2935 ret);
2936 }
2937
2938 return ret;
2939}
2940module_init(wm8915_modinit);
2941
2942static void __exit wm8915_exit(void)
2943{
2944 i2c_del_driver(&wm8915_i2c_driver);
2945}
2946module_exit(wm8915_exit);
2947
2948MODULE_DESCRIPTION("ASoC WM8915 driver");
2949MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2950MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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