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Merge branch 'x86/numa' into x86/urgent
[deliverable/linux.git] / sound / soc / codecs / wm8955.c
CommitLineData
b35a28af
MB		 1/*
2 * wm8955.c -- WM8955 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
19#include <linux/platform_device.h>
20#include <linux/regulator/consumer.h>
5a0e3ad6 21#include <linux/slab.h>
b35a28af
MB		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29#include <sound/wm8955.h>
30
31#include "wm8955.h"
32
b35a28af
MB		 33#define WM8955_NUM_SUPPLIES 4
34static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = {
35 "DCVDD",
36 "DBVDD",
37 "HPVDD",
38 "AVDD",
39};
40
41/* codec private data */
42struct wm8955_priv {
f0fba2ad 43 enum snd_soc_control_type control_type;
f0fba2ad 44
b35a28af
MB		 45 unsigned int mclk_rate;
46
47 int deemph;
48 int fs;
49
50 struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES];
b35a28af
MB		 51};
52
53static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = {
54 0x0000, /* R0 */
55 0x0000, /* R1 */
56 0x0079, /* R2 - LOUT1 volume */
57 0x0079, /* R3 - ROUT1 volume */
58 0x0000, /* R4 */
59 0x0008, /* R5 - DAC Control */
60 0x0000, /* R6 */
61 0x000A, /* R7 - Audio Interface */
62 0x0000, /* R8 - Sample Rate */
63 0x0000, /* R9 */
64 0x00FF, /* R10 - Left DAC volume */
65 0x00FF, /* R11 - Right DAC volume */
66 0x000F, /* R12 - Bass control */
67 0x000F, /* R13 - Treble control */
68 0x0000, /* R14 */
69 0x0000, /* R15 - Reset */
70 0x0000, /* R16 */
71 0x0000, /* R17 */
72 0x0000, /* R18 */
73 0x0000, /* R19 */
74 0x0000, /* R20 */
75 0x0000, /* R21 */
76 0x0000, /* R22 */
77 0x00C1, /* R23 - Additional control (1) */
78 0x0000, /* R24 - Additional control (2) */
79 0x0000, /* R25 - Power Management (1) */
80 0x0000, /* R26 - Power Management (2) */
81 0x0000, /* R27 - Additional Control (3) */
82 0x0000, /* R28 */
83 0x0000, /* R29 */
84 0x0000, /* R30 */
85 0x0000, /* R31 */
86 0x0000, /* R32 */
87 0x0000, /* R33 */
88 0x0050, /* R34 - Left out Mix (1) */
89 0x0050, /* R35 - Left out Mix (2) */
90 0x0050, /* R36 - Right out Mix (1) */
91 0x0050, /* R37 - Right Out Mix (2) */
92 0x0050, /* R38 - Mono out Mix (1) */
93 0x0050, /* R39 - Mono out Mix (2) */
94 0x0079, /* R40 - LOUT2 volume */
95 0x0079, /* R41 - ROUT2 volume */
96 0x0079, /* R42 - MONOOUT volume */
97 0x0000, /* R43 - Clocking / PLL */
98 0x0103, /* R44 - PLL Control 1 */
99 0x0024, /* R45 - PLL Control 2 */
100 0x01BA, /* R46 - PLL Control 3 */
101 0x0000, /* R47 */
102 0x0000, /* R48 */
103 0x0000, /* R49 */
104 0x0000, /* R50 */
105 0x0000, /* R51 */
106 0x0000, /* R52 */
107 0x0000, /* R53 */
108 0x0000, /* R54 */
109 0x0000, /* R55 */
110 0x0000, /* R56 */
111 0x0000, /* R57 */
112 0x0000, /* R58 */
113 0x0000, /* R59 - PLL Control 4 */
114};
115
116static int wm8955_reset(struct snd_soc_codec *codec)
117{
118 return snd_soc_write(codec, WM8955_RESET, 0);
119}
120
121struct pll_factors {
122 int n;
123 int k;
124 int outdiv;
125};
126
127/* The size in bits of the FLL divide multiplied by 10
128 * to allow rounding later */
129#define FIXED_FLL_SIZE ((1 << 22) * 10)
130
131static int wm8995_pll_factors(struct device *dev,
132 int Fref, int Fout, struct pll_factors *pll)
133{
134 u64 Kpart;
135 unsigned int K, Ndiv, Nmod, target;
136
137 dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout);
138
139 /* The oscilator should run at should be 90-100MHz, and
140 * there's a divide by 4 plus an optional divide by 2 in the
141 * output path to generate the system clock. The clock table
142 * is sortd so we should always generate a suitable target. */
143 target = Fout * 4;
144 if (target < 90000000) {
145 pll->outdiv = 1;
146 target *= 2;
147 } else {
148 pll->outdiv = 0;
149 }
150
151 WARN_ON(target < 90000000 || target > 100000000);
152
153 dev_dbg(dev, "Fvco=%dHz\n", target);
154
155 /* Now, calculate N.K */
156 Ndiv = target / Fref;
157
158 pll->n = Ndiv;
159 Nmod = target % Fref;
160 dev_dbg(dev, "Nmod=%d\n", Nmod);
161
162 /* Calculate fractional part - scale up so we can round. */
163 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
164
165 do_div(Kpart, Fref);
166
167 K = Kpart & 0xFFFFFFFF;
168
169 if ((K % 10) >= 5)
170 K += 5;
171
172 /* Move down to proper range now rounding is done */
173 pll->k = K / 10;
174
175 dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv);
176
177 return 0;
178}
179
180/* Lookup table specifiying SRATE (table 25 in datasheet); some of the
181 * output frequencies have been rounded to the standard frequencies
182 * they are intended to match where the error is slight. */
183static struct {
184 int mclk;
185 int fs;
186 int usb;
187 int sr;
188} clock_cfgs[] = {
189 { 18432000, 8000, 0, 3, },
190 { 18432000, 12000, 0, 9, },
191 { 18432000, 16000, 0, 11, },
192 { 18432000, 24000, 0, 29, },
193 { 18432000, 32000, 0, 13, },
194 { 18432000, 48000, 0, 1, },
195 { 18432000, 96000, 0, 15, },
196
197 { 16934400, 8018, 0, 19, },
198 { 16934400, 11025, 0, 25, },
199 { 16934400, 22050, 0, 27, },
200 { 16934400, 44100, 0, 17, },
201 { 16934400, 88200, 0, 31, },
202
203 { 12000000, 8000, 1, 2, },
204 { 12000000, 11025, 1, 25, },
205 { 12000000, 12000, 1, 8, },
206 { 12000000, 16000, 1, 10, },
207 { 12000000, 22050, 1, 27, },
208 { 12000000, 24000, 1, 28, },
209 { 12000000, 32000, 1, 12, },
210 { 12000000, 44100, 1, 17, },
211 { 12000000, 48000, 1, 0, },
212 { 12000000, 88200, 1, 31, },
213 { 12000000, 96000, 1, 14, },
214
215 { 12288000, 8000, 0, 2, },
216 { 12288000, 12000, 0, 8, },
217 { 12288000, 16000, 0, 10, },
218 { 12288000, 24000, 0, 28, },
219 { 12288000, 32000, 0, 12, },
220 { 12288000, 48000, 0, 0, },
221 { 12288000, 96000, 0, 14, },
222
223 { 12289600, 8018, 0, 18, },
224 { 12289600, 11025, 0, 24, },
225 { 12289600, 22050, 0, 26, },
226 { 11289600, 44100, 0, 16, },
227 { 11289600, 88200, 0, 31, },
228};
229
230static int wm8955_configure_clocking(struct snd_soc_codec *codec)
231{
b2c812e2 232 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 233 int i, ret, val;
234 int clocking = 0;
235 int srate = 0;
236 int sr = -1;
237 struct pll_factors pll;
238
239 /* If we're not running a sample rate currently just pick one */
240 if (wm8955->fs == 0)
241 wm8955->fs = 8000;
242
243 /* Can we generate an exact output? */
244 for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) {
245 if (wm8955->fs != clock_cfgs[i].fs)
246 continue;
247 sr = i;
248
249 if (wm8955->mclk_rate == clock_cfgs[i].mclk)
250 break;
251 }
252
253 /* We should never get here with an unsupported sample rate */
254 if (sr == -1) {
255 dev_err(codec->dev, "Sample rate %dHz unsupported\n",
256 wm8955->fs);
257 WARN_ON(sr == -1);
258 return -EINVAL;
259 }
260
261 if (i == ARRAY_SIZE(clock_cfgs)) {
262 /* If we can't generate the right clock from MCLK then
263 * we should configure the PLL to supply us with an
264 * appropriate clock.
265 */
266 clocking |= WM8955_MCLKSEL;
267
268 /* Use the last divider configuration we saw for the
269 * sample rate. */
270 ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate,
271 clock_cfgs[sr].mclk, &pll);
272 if (ret != 0) {
273 dev_err(codec->dev,
274 "Unable to generate %dHz from %dHz MCLK\n",
275 wm8955->fs, wm8955->mclk_rate);
276 return -EINVAL;
277 }
278
279 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1,
280 WM8955_N_MASK | WM8955_K_21_18_MASK,
281 (pll.n << WM8955_N_SHIFT) |
282 pll.k >> 18);
283 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
284 WM8955_K_17_9_MASK,
285 (pll.k >> 9) & WM8955_K_17_9_MASK);
286 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2,
287 WM8955_K_8_0_MASK,
288 pll.k & WM8955_K_8_0_MASK);
289 if (pll.k)
290 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
291 WM8955_KEN, WM8955_KEN);
292 else
293 snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4,
294 WM8955_KEN, 0);
295
296 if (pll.outdiv)
297 val = WM8955_PLL_RB | WM8955_PLLOUTDIV2;
298 else
299 val = WM8955_PLL_RB;
300
301 /* Now start the PLL running */
302 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
303 WM8955_PLL_RB | WM8955_PLLOUTDIV2, val);
304 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
305 WM8955_PLLEN, WM8955_PLLEN);
306 }
307
308 srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT);
309
310 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
311 WM8955_USB | WM8955_SR_MASK, srate);
312 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
313 WM8955_MCLKSEL, clocking);
314
315 return 0;
316}
317
318static int wm8955_sysclk(struct snd_soc_dapm_widget *w,
319 struct snd_kcontrol *kcontrol, int event)
320{
321 struct snd_soc_codec *codec = w->codec;
322 int ret = 0;
323
324 /* Always disable the clocks - if we're doing reconfiguration this
325 * avoids misclocking.
326 */
327 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
328 WM8955_DIGENB, 0);
329 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
330 WM8955_PLL_RB | WM8955_PLLEN, 0);
331
332 switch (event) {
333 case SND_SOC_DAPM_POST_PMD:
334 break;
335 case SND_SOC_DAPM_PRE_PMU:
336 ret = wm8955_configure_clocking(codec);
337 break;
338 default:
339 ret = -EINVAL;
340 break;
341 }
342
343 return ret;
344}
345
346static int deemph_settings[] = { 0, 32000, 44100, 48000 };
347
348static int wm8955_set_deemph(struct snd_soc_codec *codec)
349{
b2c812e2 350 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 351 int val, i, best;
352
353 /* If we're using deemphasis select the nearest available sample
354 * rate.
355 */
356 if (wm8955->deemph) {
357 best = 1;
358 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
359 if (abs(deemph_settings[i] - wm8955->fs) <
360 abs(deemph_settings[best] - wm8955->fs))
361 best = i;
362 }
363
364 val = best << WM8955_DEEMPH_SHIFT;
365 } else {
366 val = 0;
367 }
368
369 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
370
371 return snd_soc_update_bits(codec, WM8955_DAC_CONTROL,
372 WM8955_DEEMPH_MASK, val);
373}
374
375static int wm8955_get_deemph(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
377{
378 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 379 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af 380
3f343f85
DA		 381 ucontrol->value.enumerated.item[0] = wm8955->deemph;
382 return 0;
b35a28af
MB		 383}
384
385static int wm8955_put_deemph(struct snd_kcontrol *kcontrol,
386 struct snd_ctl_elem_value *ucontrol)
387{
388 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 389 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 390 int deemph = ucontrol->value.enumerated.item[0];
391
392 if (deemph > 1)
393 return -EINVAL;
394
395 wm8955->deemph = deemph;
396
397 return wm8955_set_deemph(codec);
398}
399
400static const char *bass_mode_text[] = {
401 "Linear", "Adaptive",
402};
403
404static const struct soc_enum bass_mode =
405 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text);
406
407static const char *bass_cutoff_text[] = {
408 "Low", "High"
409};
410
411static const struct soc_enum bass_cutoff =
412 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text);
413
414static const char *treble_cutoff_text[] = {
415 "High", "Low"
416};
417
418static const struct soc_enum treble_cutoff =
419 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text);
420
421static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
422static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0);
423static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
424static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0);
425static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
426static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1);
427
428static const struct snd_kcontrol_new wm8955_snd_controls[] = {
429SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME,
430 WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv),
431SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1,
432 atten_tlv),
433SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
434 wm8955_get_deemph, wm8955_put_deemph),
435
436SOC_ENUM("Bass Mode", bass_mode),
437SOC_ENUM("Bass Cutoff", bass_cutoff),
438SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1),
439
440SOC_ENUM("Treble Cutoff", treble_cutoff),
441SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv),
442
443SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1,
444 bypass_tlv),
445SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1,
446 bypass_tlv),
447
448SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1,
449 bypass_tlv),
450SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1,
451 bypass_tlv),
452
453/* Not a stereo pair so they line up with the DAPM switches */
454SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1,
455 mono_tlv),
456SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1,
457 mono_tlv),
458
459SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME,
460 WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv),
461SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME,
462 WM8955_ROUT1_VOLUME, 7, 1, 0),
463
464SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME,
465 WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv),
466SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME,
467 WM8955_ROUT2_VOLUME, 7, 1, 0),
468
469SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv),
470SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0),
471};
472
473static const struct snd_kcontrol_new lmixer[] = {
474SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0),
475SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0),
476SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0),
477SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0),
478};
479
480static const struct snd_kcontrol_new rmixer[] = {
481SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0),
482SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0),
483SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0),
484SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0),
485};
486
487static const struct snd_kcontrol_new mmixer[] = {
488SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0),
489SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0),
490SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0),
491SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0),
492};
493
494static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = {
495SND_SOC_DAPM_INPUT("MONOIN-"),
496SND_SOC_DAPM_INPUT("MONOIN+"),
497SND_SOC_DAPM_INPUT("LINEINR"),
498SND_SOC_DAPM_INPUT("LINEINL"),
499
500SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0),
501
502SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk,
503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
504SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0),
505
506SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0),
507SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0),
508
509SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0),
510SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
511SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
512SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0),
513SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0),
514SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
515
516/* The names are chosen to make the control names nice */
517SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0,
518 lmixer, ARRAY_SIZE(lmixer)),
519SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0,
520 rmixer, ARRAY_SIZE(rmixer)),
521SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0,
522 mmixer, ARRAY_SIZE(mmixer)),
523
524SND_SOC_DAPM_OUTPUT("LOUT1"),
525SND_SOC_DAPM_OUTPUT("ROUT1"),
526SND_SOC_DAPM_OUTPUT("LOUT2"),
527SND_SOC_DAPM_OUTPUT("ROUT2"),
528SND_SOC_DAPM_OUTPUT("MONOOUT"),
529SND_SOC_DAPM_OUTPUT("OUT3"),
530};
531
532static const struct snd_soc_dapm_route wm8955_intercon[] = {
533 { "DACL", NULL, "SYSCLK" },
534 { "DACR", NULL, "SYSCLK" },
535
536 { "Mono Input", NULL, "MONOIN-" },
537 { "Mono Input", NULL, "MONOIN+" },
538
539 { "Left", "Playback Switch", "DACL" },
540 { "Left", "Right Playback Switch", "DACR" },
541 { "Left", "Bypass Switch", "LINEINL" },
542 { "Left", "Mono Switch", "Mono Input" },
543
544 { "Right", "Playback Switch", "DACR" },
545 { "Right", "Left Playback Switch", "DACL" },
546 { "Right", "Bypass Switch", "LINEINR" },
547 { "Right", "Mono Switch", "Mono Input" },
548
549 { "Mono", "Left Playback Switch", "DACL" },
550 { "Mono", "Right Playback Switch", "DACR" },
551 { "Mono", "Left Bypass Switch", "LINEINL" },
552 { "Mono", "Right Bypass Switch", "LINEINR" },
553
554 { "LOUT1 PGA", NULL, "Left" },
555 { "LOUT1", NULL, "TSDEN" },
556 { "LOUT1", NULL, "LOUT1 PGA" },
557
558 { "ROUT1 PGA", NULL, "Right" },
559 { "ROUT1", NULL, "TSDEN" },
560 { "ROUT1", NULL, "ROUT1 PGA" },
561
562 { "LOUT2 PGA", NULL, "Left" },
563 { "LOUT2", NULL, "TSDEN" },
564 { "LOUT2", NULL, "LOUT2 PGA" },
565
566 { "ROUT2 PGA", NULL, "Right" },
567 { "ROUT2", NULL, "TSDEN" },
568 { "ROUT2", NULL, "ROUT2 PGA" },
569
570 { "MOUT PGA", NULL, "Mono" },
571 { "MONOOUT", NULL, "MOUT PGA" },
572
573 /* OUT3 not currently implemented */
574 { "OUT3", NULL, "OUT3 PGA" },
575};
576
577static int wm8955_add_widgets(struct snd_soc_codec *codec)
578{
579 snd_soc_add_controls(codec, wm8955_snd_controls,
580 ARRAY_SIZE(wm8955_snd_controls));
581
582 snd_soc_dapm_new_controls(codec, wm8955_dapm_widgets,
583 ARRAY_SIZE(wm8955_dapm_widgets));
584
585 snd_soc_dapm_add_routes(codec, wm8955_intercon,
586 ARRAY_SIZE(wm8955_intercon));
587
588 return 0;
589}
590
591static int wm8955_hw_params(struct snd_pcm_substream *substream,
592 struct snd_pcm_hw_params *params,
593 struct snd_soc_dai *dai)
594{
595 struct snd_soc_codec *codec = dai->codec;
b2c812e2 596 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 597 int ret;
598 int wl;
599
600 switch (params_format(params)) {
601 case SNDRV_PCM_FORMAT_S16_LE:
602 wl = 0;
603 break;
604 case SNDRV_PCM_FORMAT_S20_3LE:
605 wl = 0x4;
606 break;
607 case SNDRV_PCM_FORMAT_S24_LE:
608 wl = 0x8;
609 break;
610 case SNDRV_PCM_FORMAT_S32_LE:
611 wl = 0xc;
612 break;
613 default:
614 return -EINVAL;
615 }
616 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
617 WM8955_WL_MASK, wl);
618
619 wm8955->fs = params_rate(params);
620 wm8955_set_deemph(codec);
621
622 /* If the chip is clocked then disable the clocks and force a
623 * reconfiguration, otherwise DAPM will power up the
624 * clocks for us later. */
625 ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1);
626 if (ret < 0)
627 return ret;
628 if (ret & WM8955_DIGENB) {
629 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
630 WM8955_DIGENB, 0);
631 snd_soc_update_bits(codec, WM8955_CLOCKING_PLL,
632 WM8955_PLL_RB | WM8955_PLLEN, 0);
633
634 wm8955_configure_clocking(codec);
635 }
636
637 return 0;
638}
639
640
641static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id,
642 unsigned int freq, int dir)
643{
644 struct snd_soc_codec *codec = dai->codec;
b2c812e2 645 struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec);
b35a28af
MB		 646 int div;
647
648 switch (clk_id) {
649 case WM8955_CLK_MCLK:
650 if (freq > 15000000) {
651 priv->mclk_rate = freq /= 2;
652 div = WM8955_MCLKDIV2;
653 } else {
654 priv->mclk_rate = freq;
655 div = 0;
656 }
657
658 snd_soc_update_bits(codec, WM8955_SAMPLE_RATE,
659 WM8955_MCLKDIV2, div);
660 break;
661
662 default:
663 return -EINVAL;
664 }
665
666 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
667
668 return 0;
669}
670
671static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
672{
673 struct snd_soc_codec *codec = dai->codec;
674 u16 aif = 0;
675
676 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
677 case SND_SOC_DAIFMT_CBS_CFS:
678 break;
679 case SND_SOC_DAIFMT_CBM_CFM:
680 aif |= WM8955_MS;
681 break;
682 default:
683 return -EINVAL;
684 }
685
686 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
687 case SND_SOC_DAIFMT_DSP_B:
688 aif |= WM8955_LRP;
689 case SND_SOC_DAIFMT_DSP_A:
690 aif |= 0x3;
691 break;
692 case SND_SOC_DAIFMT_I2S:
693 aif |= 0x2;
694 break;
695 case SND_SOC_DAIFMT_RIGHT_J:
696 break;
697 case SND_SOC_DAIFMT_LEFT_J:
698 aif |= 0x1;
699 break;
700 default:
701 return -EINVAL;
702 }
703
704 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
705 case SND_SOC_DAIFMT_DSP_A:
706 case SND_SOC_DAIFMT_DSP_B:
707 /* frame inversion not valid for DSP modes */
708 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
709 case SND_SOC_DAIFMT_NB_NF:
710 break;
711 case SND_SOC_DAIFMT_IB_NF:
712 aif |= WM8955_BCLKINV;
713 break;
714 default:
715 return -EINVAL;
716 }
717 break;
718
719 case SND_SOC_DAIFMT_I2S:
720 case SND_SOC_DAIFMT_RIGHT_J:
721 case SND_SOC_DAIFMT_LEFT_J:
722 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
723 case SND_SOC_DAIFMT_NB_NF:
724 break;
725 case SND_SOC_DAIFMT_IB_IF:
726 aif |= WM8955_BCLKINV | WM8955_LRP;
727 break;
728 case SND_SOC_DAIFMT_IB_NF:
729 aif |= WM8955_BCLKINV;
730 break;
731 case SND_SOC_DAIFMT_NB_IF:
732 aif |= WM8955_LRP;
733 break;
734 default:
735 return -EINVAL;
736 }
737 break;
738 default:
739 return -EINVAL;
740 }
741
742 snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE,
743 WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV |
744 WM8955_LRP, aif);
745
746 return 0;
747}
748
749
750static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute)
751{
752 struct snd_soc_codec *codec = codec_dai->codec;
753 int val;
754
755 if (mute)
756 val = WM8955_DACMU;
757 else
758 val = 0;
759
760 snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val);
761
762 return 0;
763}
764
765static int wm8955_set_bias_level(struct snd_soc_codec *codec,
766 enum snd_soc_bias_level level)
767{
b2c812e2 768 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
715920d0 769 u16 *reg_cache = codec->reg_cache;
b35a28af
MB		 770 int ret, i;
771
772 switch (level) {
773 case SND_SOC_BIAS_ON:
774 break;
775
776 case SND_SOC_BIAS_PREPARE:
777 /* VMID resistance 2*50k */
778 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
779 WM8955_VMIDSEL_MASK,
780 0x1 << WM8955_VMIDSEL_SHIFT);
781
782 /* Default bias current */
783 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
784 WM8955_VSEL_MASK,
785 0x2 << WM8955_VSEL_SHIFT);
786 break;
787
788 case SND_SOC_BIAS_STANDBY:
789 if (codec->bias_level == SND_SOC_BIAS_OFF) {
790 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
791 wm8955->supplies);
792 if (ret != 0) {
793 dev_err(codec->dev,
794 "Failed to enable supplies: %d\n",
795 ret);
796 return ret;
797 }
798
799 /* Sync back cached values if they're
800 * different from the hardware default.
801 */
715920d0 802 for (i = 0; i < codec->driver->reg_cache_size; i++) {
b35a28af
MB		 803 if (i == WM8955_RESET)
804 continue;
805
715920d0 806 if (reg_cache[i] == wm8955_reg[i])
b35a28af
MB		 807 continue;
808
715920d0 809 snd_soc_write(codec, i, reg_cache[i]);
b35a28af
MB		 810 }
811
812 /* Enable VREF and VMID */
813 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
814 WM8955_VREF |
815 WM8955_VMIDSEL_MASK,
816 WM8955_VREF |
817 0x3 << WM8955_VREF_SHIFT);
818
819 /* Let VMID ramp */
820 msleep(500);
821
822 /* High resistance VROI to maintain outputs */
823 snd_soc_update_bits(codec,
824 WM8955_ADDITIONAL_CONTROL_3,
825 WM8955_VROI, WM8955_VROI);
826 }
827
828 /* Maintain VMID with 2*250k */
829 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
830 WM8955_VMIDSEL_MASK,
831 0x2 << WM8955_VMIDSEL_SHIFT);
832
833 /* Minimum bias current */
834 snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1,
835 WM8955_VSEL_MASK, 0);
836 break;
837
838 case SND_SOC_BIAS_OFF:
839 /* Low resistance VROI to help discharge */
840 snd_soc_update_bits(codec,
841 WM8955_ADDITIONAL_CONTROL_3,
842 WM8955_VROI, 0);
843
844 /* Turn off VMID and VREF */
845 snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1,
846 WM8955_VREF |
847 WM8955_VMIDSEL_MASK, 0);
848
849 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies),
850 wm8955->supplies);
851 break;
852 }
853 codec->bias_level = level;
854 return 0;
855}
856
857#define WM8955_RATES SNDRV_PCM_RATE_8000_96000
858
859#define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
860 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
861
862static struct snd_soc_dai_ops wm8955_dai_ops = {
863 .set_sysclk = wm8955_set_sysclk,
864 .set_fmt = wm8955_set_fmt,
865 .hw_params = wm8955_hw_params,
866 .digital_mute = wm8955_digital_mute,
867};
868
f0fba2ad
LG		 869static struct snd_soc_dai_driver wm8955_dai = {
870 .name = "wm8955-hifi",
b35a28af
MB		 871 .playback = {
872 .stream_name = "Playback",
873 .channels_min = 2,
874 .channels_max = 2,
875 .rates = WM8955_RATES,
876 .formats = WM8955_FORMATS,
877 },
878 .ops = &wm8955_dai_ops,
879};
b35a28af
MB		 880
881#ifdef CONFIG_PM
f0fba2ad 882static int wm8955_suspend(struct snd_soc_codec *codec, pm_message_t state)
b35a28af 883{
b35a28af
MB		 884 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
885
886 return 0;
887}
888
f0fba2ad 889static int wm8955_resume(struct snd_soc_codec *codec)
b35a28af 890{
b35a28af
MB		 891 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
892
893 return 0;
894}
895#else
896#define wm8955_suspend NULL
897#define wm8955_resume NULL
898#endif
899
f0fba2ad 900static int wm8955_probe(struct snd_soc_codec *codec)
b35a28af 901{
f0fba2ad
LG		 902 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
903 struct wm8955_pdata *pdata = dev_get_platdata(codec->dev);
715920d0 904 u16 *reg_cache = codec->reg_cache;
f0fba2ad 905 int ret, i;
b35a28af 906
f0fba2ad 907 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type);
b35a28af
MB		 908 if (ret != 0) {
909 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 910 return ret;
b35a28af
MB		 911 }
912
913 for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++)
914 wm8955->supplies[i].supply = wm8955_supply_names[i];
915
916 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies),
917 wm8955->supplies);
918 if (ret != 0) {
919 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 920 return ret;
b35a28af
MB		 921 }
922
923 ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies),
924 wm8955->supplies);
925 if (ret != 0) {
926 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
927 goto err_get;
928 }
929
930 ret = wm8955_reset(codec);
931 if (ret < 0) {
932 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
933 goto err_enable;
934 }
935
b35a28af 936 /* Change some default settings - latch VU and enable ZC */
715920d0
LPC		 937 reg_cache[WM8955_LEFT_DAC_VOLUME] |= WM8955_LDVU;
938 reg_cache[WM8955_RIGHT_DAC_VOLUME] |= WM8955_RDVU;
939 reg_cache[WM8955_LOUT1_VOLUME] |= WM8955_LO1VU | WM8955_LO1ZC;
940 reg_cache[WM8955_ROUT1_VOLUME] |= WM8955_RO1VU | WM8955_RO1ZC;
941 reg_cache[WM8955_LOUT2_VOLUME] |= WM8955_LO2VU | WM8955_LO2ZC;
942 reg_cache[WM8955_ROUT2_VOLUME] |= WM8955_RO2VU | WM8955_RO2ZC;
943 reg_cache[WM8955_MONOOUT_VOLUME] |= WM8955_MOZC;
b35a28af
MB		 944
945 /* Also enable adaptive bass boost by default */
715920d0 946 reg_cache[WM8955_BASS_CONTROL] |= WM8955_BB;
b35a28af
MB		 947
948 /* Set platform data values */
f0fba2ad
LG		 949 if (pdata) {
950 if (pdata->out2_speaker)
715920d0 951 reg_cache[WM8955_ADDITIONAL_CONTROL_2]
b35a28af
MB		 952 |= WM8955_ROUT2INV;
953
f0fba2ad 954 if (pdata->monoin_diff)
715920d0 955 reg_cache[WM8955_MONO_OUT_MIX_1]
b35a28af
MB		 956 |= WM8955_DMEN;
957 }
958
959 wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
960
961 /* Bias level configuration will have done an extra enable */
962 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
963
f0fba2ad 964 wm8955_add_widgets(codec);
b35a28af
MB		 965 return 0;
966
967err_enable:
968 regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
969err_get:
970 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
b35a28af
MB		 971 return ret;
972}
973
f0fba2ad 974static int wm8955_remove(struct snd_soc_codec *codec)
b35a28af 975{
f0fba2ad
LG		 976 struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec);
977
978 wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF);
b35a28af 979 regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies);
f0fba2ad 980 return 0;
b35a28af
MB		 981}
982
f0fba2ad
LG		 983static struct snd_soc_codec_driver soc_codec_dev_wm8955 = {
984 .probe = wm8955_probe,
985 .remove = wm8955_remove,
986 .suspend = wm8955_suspend,
987 .resume = wm8955_resume,
988 .set_bias_level = wm8955_set_bias_level,
989 .reg_cache_size = ARRAY_SIZE(wm8955_reg),
990 .reg_word_size = sizeof(u16),
991 .reg_cache_default = wm8955_reg,
992};
993
b35a28af
MB		 994#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
995static __devinit int wm8955_i2c_probe(struct i2c_client *i2c,
996 const struct i2c_device_id *id)
997{
998 struct wm8955_priv *wm8955;
f0fba2ad 999 int ret;
b35a28af
MB		 1000
1001 wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL);
1002 if (wm8955 == NULL)
1003 return -ENOMEM;
1004
b35a28af 1005 i2c_set_clientdata(i2c, wm8955);
7f984b55 1006 wm8955->control_type = SND_SOC_I2C;
b35a28af 1007
f0fba2ad
LG		 1008 ret = snd_soc_register_codec(&i2c->dev,
1009 &soc_codec_dev_wm8955, &wm8955_dai, 1);
1010 if (ret < 0)
1011 kfree(wm8955);
1012 return ret;
b35a28af
MB		 1013}
1014
1015static __devexit int wm8955_i2c_remove(struct i2c_client *client)
1016{
f0fba2ad
LG		 1017 snd_soc_unregister_codec(&client->dev);
1018 kfree(i2c_get_clientdata(client));
b35a28af
MB		 1019 return 0;
1020}
1021
1022static const struct i2c_device_id wm8955_i2c_id[] = {
1023 { "wm8955", 0 },
1024 { }
1025};
1026MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id);
1027
1028static struct i2c_driver wm8955_i2c_driver = {
1029 .driver = {
f0fba2ad 1030 .name = "wm8955-codec",
b35a28af
MB		 1031 .owner = THIS_MODULE,
1032 },
1033 .probe = wm8955_i2c_probe,
1034 .remove = __devexit_p(wm8955_i2c_remove),
1035 .id_table = wm8955_i2c_id,
1036};
1037#endif
1038
1039static int __init wm8955_modinit(void)
1040{
f0fba2ad 1041 int ret = 0;
b35a28af
MB		 1042#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1043 ret = i2c_add_driver(&wm8955_i2c_driver);
1044 if (ret != 0) {
1045 printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n",
1046 ret);
1047 }
1048#endif
f0fba2ad 1049 return ret;
b35a28af
MB		 1050}
1051module_init(wm8955_modinit);
1052
1053static void __exit wm8955_exit(void)
1054{
1055#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1056 i2c_del_driver(&wm8955_i2c_driver);
1057#endif
1058}
1059module_exit(wm8955_exit);
1060
1061MODULE_DESCRIPTION("ASoC WM8955 driver");
1062MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1063MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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