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b35a28af MB |
1 | /* |
2 | * wm8955.c -- WM8955 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2009 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/i2c.h> | |
19 | #include <linux/platform_device.h> | |
20 | #include <linux/regulator/consumer.h> | |
5a0e3ad6 | 21 | #include <linux/slab.h> |
b35a28af MB |
22 | #include <sound/core.h> |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
b35a28af MB |
26 | #include <sound/initval.h> |
27 | #include <sound/tlv.h> | |
28 | #include <sound/wm8955.h> | |
29 | ||
30 | #include "wm8955.h" | |
31 | ||
b35a28af MB |
32 | #define WM8955_NUM_SUPPLIES 4 |
33 | static const char *wm8955_supply_names[WM8955_NUM_SUPPLIES] = { | |
34 | "DCVDD", | |
35 | "DBVDD", | |
36 | "HPVDD", | |
37 | "AVDD", | |
38 | }; | |
39 | ||
40 | /* codec private data */ | |
41 | struct wm8955_priv { | |
f0fba2ad | 42 | enum snd_soc_control_type control_type; |
f0fba2ad | 43 | |
b35a28af MB |
44 | unsigned int mclk_rate; |
45 | ||
46 | int deemph; | |
47 | int fs; | |
48 | ||
49 | struct regulator_bulk_data supplies[WM8955_NUM_SUPPLIES]; | |
b35a28af MB |
50 | }; |
51 | ||
52 | static const u16 wm8955_reg[WM8955_MAX_REGISTER + 1] = { | |
53 | 0x0000, /* R0 */ | |
54 | 0x0000, /* R1 */ | |
55 | 0x0079, /* R2 - LOUT1 volume */ | |
56 | 0x0079, /* R3 - ROUT1 volume */ | |
57 | 0x0000, /* R4 */ | |
58 | 0x0008, /* R5 - DAC Control */ | |
59 | 0x0000, /* R6 */ | |
60 | 0x000A, /* R7 - Audio Interface */ | |
61 | 0x0000, /* R8 - Sample Rate */ | |
62 | 0x0000, /* R9 */ | |
63 | 0x00FF, /* R10 - Left DAC volume */ | |
64 | 0x00FF, /* R11 - Right DAC volume */ | |
65 | 0x000F, /* R12 - Bass control */ | |
66 | 0x000F, /* R13 - Treble control */ | |
67 | 0x0000, /* R14 */ | |
68 | 0x0000, /* R15 - Reset */ | |
69 | 0x0000, /* R16 */ | |
70 | 0x0000, /* R17 */ | |
71 | 0x0000, /* R18 */ | |
72 | 0x0000, /* R19 */ | |
73 | 0x0000, /* R20 */ | |
74 | 0x0000, /* R21 */ | |
75 | 0x0000, /* R22 */ | |
76 | 0x00C1, /* R23 - Additional control (1) */ | |
77 | 0x0000, /* R24 - Additional control (2) */ | |
78 | 0x0000, /* R25 - Power Management (1) */ | |
79 | 0x0000, /* R26 - Power Management (2) */ | |
80 | 0x0000, /* R27 - Additional Control (3) */ | |
81 | 0x0000, /* R28 */ | |
82 | 0x0000, /* R29 */ | |
83 | 0x0000, /* R30 */ | |
84 | 0x0000, /* R31 */ | |
85 | 0x0000, /* R32 */ | |
86 | 0x0000, /* R33 */ | |
87 | 0x0050, /* R34 - Left out Mix (1) */ | |
88 | 0x0050, /* R35 - Left out Mix (2) */ | |
89 | 0x0050, /* R36 - Right out Mix (1) */ | |
90 | 0x0050, /* R37 - Right Out Mix (2) */ | |
91 | 0x0050, /* R38 - Mono out Mix (1) */ | |
92 | 0x0050, /* R39 - Mono out Mix (2) */ | |
93 | 0x0079, /* R40 - LOUT2 volume */ | |
94 | 0x0079, /* R41 - ROUT2 volume */ | |
95 | 0x0079, /* R42 - MONOOUT volume */ | |
96 | 0x0000, /* R43 - Clocking / PLL */ | |
97 | 0x0103, /* R44 - PLL Control 1 */ | |
98 | 0x0024, /* R45 - PLL Control 2 */ | |
99 | 0x01BA, /* R46 - PLL Control 3 */ | |
100 | 0x0000, /* R47 */ | |
101 | 0x0000, /* R48 */ | |
102 | 0x0000, /* R49 */ | |
103 | 0x0000, /* R50 */ | |
104 | 0x0000, /* R51 */ | |
105 | 0x0000, /* R52 */ | |
106 | 0x0000, /* R53 */ | |
107 | 0x0000, /* R54 */ | |
108 | 0x0000, /* R55 */ | |
109 | 0x0000, /* R56 */ | |
110 | 0x0000, /* R57 */ | |
111 | 0x0000, /* R58 */ | |
112 | 0x0000, /* R59 - PLL Control 4 */ | |
113 | }; | |
114 | ||
115 | static int wm8955_reset(struct snd_soc_codec *codec) | |
116 | { | |
117 | return snd_soc_write(codec, WM8955_RESET, 0); | |
118 | } | |
119 | ||
120 | struct pll_factors { | |
121 | int n; | |
122 | int k; | |
123 | int outdiv; | |
124 | }; | |
125 | ||
126 | /* The size in bits of the FLL divide multiplied by 10 | |
127 | * to allow rounding later */ | |
128 | #define FIXED_FLL_SIZE ((1 << 22) * 10) | |
129 | ||
130 | static int wm8995_pll_factors(struct device *dev, | |
131 | int Fref, int Fout, struct pll_factors *pll) | |
132 | { | |
133 | u64 Kpart; | |
134 | unsigned int K, Ndiv, Nmod, target; | |
135 | ||
136 | dev_dbg(dev, "Fref=%u Fout=%u\n", Fref, Fout); | |
137 | ||
138 | /* The oscilator should run at should be 90-100MHz, and | |
139 | * there's a divide by 4 plus an optional divide by 2 in the | |
140 | * output path to generate the system clock. The clock table | |
141 | * is sortd so we should always generate a suitable target. */ | |
142 | target = Fout * 4; | |
143 | if (target < 90000000) { | |
144 | pll->outdiv = 1; | |
145 | target *= 2; | |
146 | } else { | |
147 | pll->outdiv = 0; | |
148 | } | |
149 | ||
150 | WARN_ON(target < 90000000 || target > 100000000); | |
151 | ||
152 | dev_dbg(dev, "Fvco=%dHz\n", target); | |
153 | ||
154 | /* Now, calculate N.K */ | |
155 | Ndiv = target / Fref; | |
156 | ||
157 | pll->n = Ndiv; | |
158 | Nmod = target % Fref; | |
159 | dev_dbg(dev, "Nmod=%d\n", Nmod); | |
160 | ||
161 | /* Calculate fractional part - scale up so we can round. */ | |
162 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
163 | ||
164 | do_div(Kpart, Fref); | |
165 | ||
166 | K = Kpart & 0xFFFFFFFF; | |
167 | ||
168 | if ((K % 10) >= 5) | |
169 | K += 5; | |
170 | ||
171 | /* Move down to proper range now rounding is done */ | |
172 | pll->k = K / 10; | |
173 | ||
174 | dev_dbg(dev, "N=%x K=%x OUTDIV=%x\n", pll->n, pll->k, pll->outdiv); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
25985edc | 179 | /* Lookup table specifying SRATE (table 25 in datasheet); some of the |
b35a28af MB |
180 | * output frequencies have been rounded to the standard frequencies |
181 | * they are intended to match where the error is slight. */ | |
182 | static struct { | |
183 | int mclk; | |
184 | int fs; | |
185 | int usb; | |
186 | int sr; | |
187 | } clock_cfgs[] = { | |
188 | { 18432000, 8000, 0, 3, }, | |
189 | { 18432000, 12000, 0, 9, }, | |
190 | { 18432000, 16000, 0, 11, }, | |
191 | { 18432000, 24000, 0, 29, }, | |
192 | { 18432000, 32000, 0, 13, }, | |
193 | { 18432000, 48000, 0, 1, }, | |
194 | { 18432000, 96000, 0, 15, }, | |
195 | ||
196 | { 16934400, 8018, 0, 19, }, | |
197 | { 16934400, 11025, 0, 25, }, | |
198 | { 16934400, 22050, 0, 27, }, | |
199 | { 16934400, 44100, 0, 17, }, | |
200 | { 16934400, 88200, 0, 31, }, | |
201 | ||
202 | { 12000000, 8000, 1, 2, }, | |
203 | { 12000000, 11025, 1, 25, }, | |
204 | { 12000000, 12000, 1, 8, }, | |
205 | { 12000000, 16000, 1, 10, }, | |
206 | { 12000000, 22050, 1, 27, }, | |
207 | { 12000000, 24000, 1, 28, }, | |
208 | { 12000000, 32000, 1, 12, }, | |
209 | { 12000000, 44100, 1, 17, }, | |
210 | { 12000000, 48000, 1, 0, }, | |
211 | { 12000000, 88200, 1, 31, }, | |
212 | { 12000000, 96000, 1, 14, }, | |
213 | ||
214 | { 12288000, 8000, 0, 2, }, | |
215 | { 12288000, 12000, 0, 8, }, | |
216 | { 12288000, 16000, 0, 10, }, | |
217 | { 12288000, 24000, 0, 28, }, | |
218 | { 12288000, 32000, 0, 12, }, | |
219 | { 12288000, 48000, 0, 0, }, | |
220 | { 12288000, 96000, 0, 14, }, | |
221 | ||
222 | { 12289600, 8018, 0, 18, }, | |
223 | { 12289600, 11025, 0, 24, }, | |
224 | { 12289600, 22050, 0, 26, }, | |
225 | { 11289600, 44100, 0, 16, }, | |
226 | { 11289600, 88200, 0, 31, }, | |
227 | }; | |
228 | ||
229 | static int wm8955_configure_clocking(struct snd_soc_codec *codec) | |
230 | { | |
b2c812e2 | 231 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
b35a28af MB |
232 | int i, ret, val; |
233 | int clocking = 0; | |
234 | int srate = 0; | |
235 | int sr = -1; | |
236 | struct pll_factors pll; | |
237 | ||
238 | /* If we're not running a sample rate currently just pick one */ | |
239 | if (wm8955->fs == 0) | |
240 | wm8955->fs = 8000; | |
241 | ||
242 | /* Can we generate an exact output? */ | |
243 | for (i = 0; i < ARRAY_SIZE(clock_cfgs); i++) { | |
244 | if (wm8955->fs != clock_cfgs[i].fs) | |
245 | continue; | |
246 | sr = i; | |
247 | ||
248 | if (wm8955->mclk_rate == clock_cfgs[i].mclk) | |
249 | break; | |
250 | } | |
251 | ||
252 | /* We should never get here with an unsupported sample rate */ | |
253 | if (sr == -1) { | |
254 | dev_err(codec->dev, "Sample rate %dHz unsupported\n", | |
255 | wm8955->fs); | |
256 | WARN_ON(sr == -1); | |
257 | return -EINVAL; | |
258 | } | |
259 | ||
260 | if (i == ARRAY_SIZE(clock_cfgs)) { | |
261 | /* If we can't generate the right clock from MCLK then | |
262 | * we should configure the PLL to supply us with an | |
263 | * appropriate clock. | |
264 | */ | |
265 | clocking |= WM8955_MCLKSEL; | |
266 | ||
267 | /* Use the last divider configuration we saw for the | |
268 | * sample rate. */ | |
269 | ret = wm8995_pll_factors(codec->dev, wm8955->mclk_rate, | |
270 | clock_cfgs[sr].mclk, &pll); | |
271 | if (ret != 0) { | |
272 | dev_err(codec->dev, | |
273 | "Unable to generate %dHz from %dHz MCLK\n", | |
274 | wm8955->fs, wm8955->mclk_rate); | |
275 | return -EINVAL; | |
276 | } | |
277 | ||
278 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_1, | |
279 | WM8955_N_MASK | WM8955_K_21_18_MASK, | |
280 | (pll.n << WM8955_N_SHIFT) | | |
281 | pll.k >> 18); | |
282 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2, | |
283 | WM8955_K_17_9_MASK, | |
284 | (pll.k >> 9) & WM8955_K_17_9_MASK); | |
285 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_2, | |
286 | WM8955_K_8_0_MASK, | |
287 | pll.k & WM8955_K_8_0_MASK); | |
288 | if (pll.k) | |
289 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4, | |
290 | WM8955_KEN, WM8955_KEN); | |
291 | else | |
292 | snd_soc_update_bits(codec, WM8955_PLL_CONTROL_4, | |
293 | WM8955_KEN, 0); | |
294 | ||
295 | if (pll.outdiv) | |
296 | val = WM8955_PLL_RB | WM8955_PLLOUTDIV2; | |
297 | else | |
298 | val = WM8955_PLL_RB; | |
299 | ||
300 | /* Now start the PLL running */ | |
301 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, | |
302 | WM8955_PLL_RB | WM8955_PLLOUTDIV2, val); | |
303 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, | |
304 | WM8955_PLLEN, WM8955_PLLEN); | |
305 | } | |
306 | ||
307 | srate = clock_cfgs[sr].usb | (clock_cfgs[sr].sr << WM8955_SR_SHIFT); | |
308 | ||
309 | snd_soc_update_bits(codec, WM8955_SAMPLE_RATE, | |
310 | WM8955_USB | WM8955_SR_MASK, srate); | |
311 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, | |
312 | WM8955_MCLKSEL, clocking); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static int wm8955_sysclk(struct snd_soc_dapm_widget *w, | |
318 | struct snd_kcontrol *kcontrol, int event) | |
319 | { | |
320 | struct snd_soc_codec *codec = w->codec; | |
321 | int ret = 0; | |
322 | ||
323 | /* Always disable the clocks - if we're doing reconfiguration this | |
324 | * avoids misclocking. | |
325 | */ | |
326 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, | |
327 | WM8955_DIGENB, 0); | |
328 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, | |
329 | WM8955_PLL_RB | WM8955_PLLEN, 0); | |
330 | ||
331 | switch (event) { | |
332 | case SND_SOC_DAPM_POST_PMD: | |
333 | break; | |
334 | case SND_SOC_DAPM_PRE_PMU: | |
335 | ret = wm8955_configure_clocking(codec); | |
336 | break; | |
337 | default: | |
338 | ret = -EINVAL; | |
339 | break; | |
340 | } | |
341 | ||
342 | return ret; | |
343 | } | |
344 | ||
345 | static int deemph_settings[] = { 0, 32000, 44100, 48000 }; | |
346 | ||
347 | static int wm8955_set_deemph(struct snd_soc_codec *codec) | |
348 | { | |
b2c812e2 | 349 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
b35a28af MB |
350 | int val, i, best; |
351 | ||
352 | /* If we're using deemphasis select the nearest available sample | |
353 | * rate. | |
354 | */ | |
355 | if (wm8955->deemph) { | |
356 | best = 1; | |
357 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
358 | if (abs(deemph_settings[i] - wm8955->fs) < | |
359 | abs(deemph_settings[best] - wm8955->fs)) | |
360 | best = i; | |
361 | } | |
362 | ||
363 | val = best << WM8955_DEEMPH_SHIFT; | |
364 | } else { | |
365 | val = 0; | |
366 | } | |
367 | ||
368 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
369 | ||
370 | return snd_soc_update_bits(codec, WM8955_DAC_CONTROL, | |
371 | WM8955_DEEMPH_MASK, val); | |
372 | } | |
373 | ||
374 | static int wm8955_get_deemph(struct snd_kcontrol *kcontrol, | |
375 | struct snd_ctl_elem_value *ucontrol) | |
376 | { | |
377 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 378 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
b35a28af | 379 | |
3f343f85 DA |
380 | ucontrol->value.enumerated.item[0] = wm8955->deemph; |
381 | return 0; | |
b35a28af MB |
382 | } |
383 | ||
384 | static int wm8955_put_deemph(struct snd_kcontrol *kcontrol, | |
385 | struct snd_ctl_elem_value *ucontrol) | |
386 | { | |
387 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 388 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
b35a28af MB |
389 | int deemph = ucontrol->value.enumerated.item[0]; |
390 | ||
391 | if (deemph > 1) | |
392 | return -EINVAL; | |
393 | ||
394 | wm8955->deemph = deemph; | |
395 | ||
396 | return wm8955_set_deemph(codec); | |
397 | } | |
398 | ||
399 | static const char *bass_mode_text[] = { | |
400 | "Linear", "Adaptive", | |
401 | }; | |
402 | ||
403 | static const struct soc_enum bass_mode = | |
404 | SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 7, 2, bass_mode_text); | |
405 | ||
406 | static const char *bass_cutoff_text[] = { | |
407 | "Low", "High" | |
408 | }; | |
409 | ||
410 | static const struct soc_enum bass_cutoff = | |
411 | SOC_ENUM_SINGLE(WM8955_BASS_CONTROL, 6, 2, bass_cutoff_text); | |
412 | ||
413 | static const char *treble_cutoff_text[] = { | |
414 | "High", "Low" | |
415 | }; | |
416 | ||
417 | static const struct soc_enum treble_cutoff = | |
418 | SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL, 6, 2, treble_cutoff_text); | |
419 | ||
420 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); | |
421 | static const DECLARE_TLV_DB_SCALE(atten_tlv, -600, 600, 0); | |
422 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); | |
423 | static const DECLARE_TLV_DB_SCALE(mono_tlv, -2100, 300, 0); | |
424 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
425 | static const DECLARE_TLV_DB_SCALE(treble_tlv, -1200, 150, 1); | |
426 | ||
427 | static const struct snd_kcontrol_new wm8955_snd_controls[] = { | |
428 | SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME, | |
429 | WM8955_RIGHT_DAC_VOLUME, 0, 255, 0, digital_tlv), | |
430 | SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL, 7, 1, 1, | |
431 | atten_tlv), | |
432 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, | |
433 | wm8955_get_deemph, wm8955_put_deemph), | |
434 | ||
435 | SOC_ENUM("Bass Mode", bass_mode), | |
436 | SOC_ENUM("Bass Cutoff", bass_cutoff), | |
437 | SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL, 0, 15, 1), | |
438 | ||
439 | SOC_ENUM("Treble Cutoff", treble_cutoff), | |
440 | SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL, 0, 14, 1, treble_tlv), | |
441 | ||
442 | SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1, 4, 7, 1, | |
443 | bypass_tlv), | |
444 | SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2, 4, 7, 1, | |
445 | bypass_tlv), | |
446 | ||
447 | SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1, 4, 7, 1, | |
448 | bypass_tlv), | |
449 | SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2, 4, 7, 1, | |
450 | bypass_tlv), | |
451 | ||
452 | /* Not a stereo pair so they line up with the DAPM switches */ | |
453 | SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1, 4, 7, 1, | |
454 | mono_tlv), | |
455 | SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2, 4, 7, 1, | |
456 | mono_tlv), | |
457 | ||
458 | SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME, | |
459 | WM8955_ROUT1_VOLUME, 0, 127, 0, out_tlv), | |
460 | SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME, | |
461 | WM8955_ROUT1_VOLUME, 7, 1, 0), | |
462 | ||
463 | SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME, | |
464 | WM8955_ROUT2_VOLUME, 0, 127, 0, out_tlv), | |
465 | SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME, | |
466 | WM8955_ROUT2_VOLUME, 7, 1, 0), | |
467 | ||
468 | SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME, 0, 127, 0, out_tlv), | |
469 | SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME, 7, 1, 0), | |
470 | }; | |
471 | ||
472 | static const struct snd_kcontrol_new lmixer[] = { | |
473 | SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1, 8, 1, 0), | |
474 | SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1, 7, 1, 0), | |
475 | SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2, 8, 1, 0), | |
476 | SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2, 7, 1, 0), | |
477 | }; | |
478 | ||
479 | static const struct snd_kcontrol_new rmixer[] = { | |
480 | SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1, 8, 1, 0), | |
481 | SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1, 7, 1, 0), | |
482 | SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2, 8, 1, 0), | |
483 | SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2, 7, 1, 0), | |
484 | }; | |
485 | ||
486 | static const struct snd_kcontrol_new mmixer[] = { | |
487 | SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1, 8, 1, 0), | |
488 | SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1, 7, 1, 0), | |
489 | SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2, 8, 1, 0), | |
490 | SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2, 7, 1, 0), | |
491 | }; | |
492 | ||
493 | static const struct snd_soc_dapm_widget wm8955_dapm_widgets[] = { | |
494 | SND_SOC_DAPM_INPUT("MONOIN-"), | |
495 | SND_SOC_DAPM_INPUT("MONOIN+"), | |
496 | SND_SOC_DAPM_INPUT("LINEINR"), | |
497 | SND_SOC_DAPM_INPUT("LINEINL"), | |
498 | ||
499 | SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM, 0, 0, NULL, 0), | |
500 | ||
501 | SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1, 0, 1, wm8955_sysclk, | |
502 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
503 | SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1, 8, 0, NULL, 0), | |
504 | ||
505 | SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2, 8, 0), | |
506 | SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2, 7, 0), | |
507 | ||
508 | SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2, 6, 0, NULL, 0), | |
509 | SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2, 5, 0, NULL, 0), | |
510 | SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2, 4, 0, NULL, 0), | |
511 | SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2, 3, 0, NULL, 0), | |
512 | SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2, 2, 0, NULL, 0), | |
513 | SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
514 | ||
515 | /* The names are chosen to make the control names nice */ | |
516 | SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM, 0, 0, | |
517 | lmixer, ARRAY_SIZE(lmixer)), | |
518 | SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM, 0, 0, | |
519 | rmixer, ARRAY_SIZE(rmixer)), | |
520 | SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM, 0, 0, | |
521 | mmixer, ARRAY_SIZE(mmixer)), | |
522 | ||
523 | SND_SOC_DAPM_OUTPUT("LOUT1"), | |
524 | SND_SOC_DAPM_OUTPUT("ROUT1"), | |
525 | SND_SOC_DAPM_OUTPUT("LOUT2"), | |
526 | SND_SOC_DAPM_OUTPUT("ROUT2"), | |
527 | SND_SOC_DAPM_OUTPUT("MONOOUT"), | |
528 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
529 | }; | |
530 | ||
531 | static const struct snd_soc_dapm_route wm8955_intercon[] = { | |
532 | { "DACL", NULL, "SYSCLK" }, | |
533 | { "DACR", NULL, "SYSCLK" }, | |
534 | ||
535 | { "Mono Input", NULL, "MONOIN-" }, | |
536 | { "Mono Input", NULL, "MONOIN+" }, | |
537 | ||
538 | { "Left", "Playback Switch", "DACL" }, | |
539 | { "Left", "Right Playback Switch", "DACR" }, | |
540 | { "Left", "Bypass Switch", "LINEINL" }, | |
541 | { "Left", "Mono Switch", "Mono Input" }, | |
542 | ||
543 | { "Right", "Playback Switch", "DACR" }, | |
544 | { "Right", "Left Playback Switch", "DACL" }, | |
545 | { "Right", "Bypass Switch", "LINEINR" }, | |
546 | { "Right", "Mono Switch", "Mono Input" }, | |
547 | ||
548 | { "Mono", "Left Playback Switch", "DACL" }, | |
549 | { "Mono", "Right Playback Switch", "DACR" }, | |
550 | { "Mono", "Left Bypass Switch", "LINEINL" }, | |
551 | { "Mono", "Right Bypass Switch", "LINEINR" }, | |
552 | ||
553 | { "LOUT1 PGA", NULL, "Left" }, | |
554 | { "LOUT1", NULL, "TSDEN" }, | |
555 | { "LOUT1", NULL, "LOUT1 PGA" }, | |
556 | ||
557 | { "ROUT1 PGA", NULL, "Right" }, | |
558 | { "ROUT1", NULL, "TSDEN" }, | |
559 | { "ROUT1", NULL, "ROUT1 PGA" }, | |
560 | ||
561 | { "LOUT2 PGA", NULL, "Left" }, | |
562 | { "LOUT2", NULL, "TSDEN" }, | |
563 | { "LOUT2", NULL, "LOUT2 PGA" }, | |
564 | ||
565 | { "ROUT2 PGA", NULL, "Right" }, | |
566 | { "ROUT2", NULL, "TSDEN" }, | |
567 | { "ROUT2", NULL, "ROUT2 PGA" }, | |
568 | ||
569 | { "MOUT PGA", NULL, "Mono" }, | |
570 | { "MONOOUT", NULL, "MOUT PGA" }, | |
571 | ||
572 | /* OUT3 not currently implemented */ | |
573 | { "OUT3", NULL, "OUT3 PGA" }, | |
574 | }; | |
575 | ||
576 | static int wm8955_add_widgets(struct snd_soc_codec *codec) | |
577 | { | |
ce6120cc LG |
578 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
579 | ||
b35a28af MB |
580 | snd_soc_add_controls(codec, wm8955_snd_controls, |
581 | ARRAY_SIZE(wm8955_snd_controls)); | |
582 | ||
ce6120cc | 583 | snd_soc_dapm_new_controls(dapm, wm8955_dapm_widgets, |
b35a28af | 584 | ARRAY_SIZE(wm8955_dapm_widgets)); |
ce6120cc | 585 | snd_soc_dapm_add_routes(dapm, wm8955_intercon, |
b35a28af MB |
586 | ARRAY_SIZE(wm8955_intercon)); |
587 | ||
588 | return 0; | |
589 | } | |
590 | ||
591 | static int wm8955_hw_params(struct snd_pcm_substream *substream, | |
592 | struct snd_pcm_hw_params *params, | |
593 | struct snd_soc_dai *dai) | |
594 | { | |
595 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 596 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
b35a28af MB |
597 | int ret; |
598 | int wl; | |
599 | ||
600 | switch (params_format(params)) { | |
601 | case SNDRV_PCM_FORMAT_S16_LE: | |
602 | wl = 0; | |
603 | break; | |
604 | case SNDRV_PCM_FORMAT_S20_3LE: | |
605 | wl = 0x4; | |
606 | break; | |
607 | case SNDRV_PCM_FORMAT_S24_LE: | |
608 | wl = 0x8; | |
609 | break; | |
610 | case SNDRV_PCM_FORMAT_S32_LE: | |
611 | wl = 0xc; | |
612 | break; | |
613 | default: | |
614 | return -EINVAL; | |
615 | } | |
616 | snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE, | |
617 | WM8955_WL_MASK, wl); | |
618 | ||
619 | wm8955->fs = params_rate(params); | |
620 | wm8955_set_deemph(codec); | |
621 | ||
622 | /* If the chip is clocked then disable the clocks and force a | |
623 | * reconfiguration, otherwise DAPM will power up the | |
624 | * clocks for us later. */ | |
625 | ret = snd_soc_read(codec, WM8955_POWER_MANAGEMENT_1); | |
626 | if (ret < 0) | |
627 | return ret; | |
628 | if (ret & WM8955_DIGENB) { | |
629 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, | |
630 | WM8955_DIGENB, 0); | |
631 | snd_soc_update_bits(codec, WM8955_CLOCKING_PLL, | |
632 | WM8955_PLL_RB | WM8955_PLLEN, 0); | |
633 | ||
634 | wm8955_configure_clocking(codec); | |
635 | } | |
636 | ||
637 | return 0; | |
638 | } | |
639 | ||
640 | ||
641 | static int wm8955_set_sysclk(struct snd_soc_dai *dai, int clk_id, | |
642 | unsigned int freq, int dir) | |
643 | { | |
644 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 645 | struct wm8955_priv *priv = snd_soc_codec_get_drvdata(codec); |
b35a28af MB |
646 | int div; |
647 | ||
648 | switch (clk_id) { | |
649 | case WM8955_CLK_MCLK: | |
650 | if (freq > 15000000) { | |
651 | priv->mclk_rate = freq /= 2; | |
652 | div = WM8955_MCLKDIV2; | |
653 | } else { | |
654 | priv->mclk_rate = freq; | |
655 | div = 0; | |
656 | } | |
657 | ||
658 | snd_soc_update_bits(codec, WM8955_SAMPLE_RATE, | |
659 | WM8955_MCLKDIV2, div); | |
660 | break; | |
661 | ||
662 | default: | |
663 | return -EINVAL; | |
664 | } | |
665 | ||
666 | dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); | |
667 | ||
668 | return 0; | |
669 | } | |
670 | ||
671 | static int wm8955_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
672 | { | |
673 | struct snd_soc_codec *codec = dai->codec; | |
674 | u16 aif = 0; | |
675 | ||
676 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
677 | case SND_SOC_DAIFMT_CBS_CFS: | |
678 | break; | |
679 | case SND_SOC_DAIFMT_CBM_CFM: | |
680 | aif |= WM8955_MS; | |
681 | break; | |
682 | default: | |
683 | return -EINVAL; | |
684 | } | |
685 | ||
686 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
687 | case SND_SOC_DAIFMT_DSP_B: | |
688 | aif |= WM8955_LRP; | |
689 | case SND_SOC_DAIFMT_DSP_A: | |
690 | aif |= 0x3; | |
691 | break; | |
692 | case SND_SOC_DAIFMT_I2S: | |
693 | aif |= 0x2; | |
694 | break; | |
695 | case SND_SOC_DAIFMT_RIGHT_J: | |
696 | break; | |
697 | case SND_SOC_DAIFMT_LEFT_J: | |
698 | aif |= 0x1; | |
699 | break; | |
700 | default: | |
701 | return -EINVAL; | |
702 | } | |
703 | ||
704 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
705 | case SND_SOC_DAIFMT_DSP_A: | |
706 | case SND_SOC_DAIFMT_DSP_B: | |
707 | /* frame inversion not valid for DSP modes */ | |
708 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
709 | case SND_SOC_DAIFMT_NB_NF: | |
710 | break; | |
711 | case SND_SOC_DAIFMT_IB_NF: | |
712 | aif |= WM8955_BCLKINV; | |
713 | break; | |
714 | default: | |
715 | return -EINVAL; | |
716 | } | |
717 | break; | |
718 | ||
719 | case SND_SOC_DAIFMT_I2S: | |
720 | case SND_SOC_DAIFMT_RIGHT_J: | |
721 | case SND_SOC_DAIFMT_LEFT_J: | |
722 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
723 | case SND_SOC_DAIFMT_NB_NF: | |
724 | break; | |
725 | case SND_SOC_DAIFMT_IB_IF: | |
726 | aif |= WM8955_BCLKINV | WM8955_LRP; | |
727 | break; | |
728 | case SND_SOC_DAIFMT_IB_NF: | |
729 | aif |= WM8955_BCLKINV; | |
730 | break; | |
731 | case SND_SOC_DAIFMT_NB_IF: | |
732 | aif |= WM8955_LRP; | |
733 | break; | |
734 | default: | |
735 | return -EINVAL; | |
736 | } | |
737 | break; | |
738 | default: | |
739 | return -EINVAL; | |
740 | } | |
741 | ||
742 | snd_soc_update_bits(codec, WM8955_AUDIO_INTERFACE, | |
743 | WM8955_MS | WM8955_FORMAT_MASK | WM8955_BCLKINV | | |
744 | WM8955_LRP, aif); | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
749 | ||
750 | static int wm8955_digital_mute(struct snd_soc_dai *codec_dai, int mute) | |
751 | { | |
752 | struct snd_soc_codec *codec = codec_dai->codec; | |
753 | int val; | |
754 | ||
755 | if (mute) | |
756 | val = WM8955_DACMU; | |
757 | else | |
758 | val = 0; | |
759 | ||
760 | snd_soc_update_bits(codec, WM8955_DAC_CONTROL, WM8955_DACMU, val); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static int wm8955_set_bias_level(struct snd_soc_codec *codec, | |
766 | enum snd_soc_bias_level level) | |
767 | { | |
b2c812e2 | 768 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
715920d0 | 769 | u16 *reg_cache = codec->reg_cache; |
b35a28af MB |
770 | int ret, i; |
771 | ||
772 | switch (level) { | |
773 | case SND_SOC_BIAS_ON: | |
774 | break; | |
775 | ||
776 | case SND_SOC_BIAS_PREPARE: | |
777 | /* VMID resistance 2*50k */ | |
778 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, | |
779 | WM8955_VMIDSEL_MASK, | |
780 | 0x1 << WM8955_VMIDSEL_SHIFT); | |
781 | ||
782 | /* Default bias current */ | |
783 | snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1, | |
784 | WM8955_VSEL_MASK, | |
785 | 0x2 << WM8955_VSEL_SHIFT); | |
786 | break; | |
787 | ||
788 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 789 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
b35a28af MB |
790 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), |
791 | wm8955->supplies); | |
792 | if (ret != 0) { | |
793 | dev_err(codec->dev, | |
794 | "Failed to enable supplies: %d\n", | |
795 | ret); | |
796 | return ret; | |
797 | } | |
798 | ||
799 | /* Sync back cached values if they're | |
800 | * different from the hardware default. | |
801 | */ | |
715920d0 | 802 | for (i = 0; i < codec->driver->reg_cache_size; i++) { |
b35a28af MB |
803 | if (i == WM8955_RESET) |
804 | continue; | |
805 | ||
715920d0 | 806 | if (reg_cache[i] == wm8955_reg[i]) |
b35a28af MB |
807 | continue; |
808 | ||
715920d0 | 809 | snd_soc_write(codec, i, reg_cache[i]); |
b35a28af MB |
810 | } |
811 | ||
812 | /* Enable VREF and VMID */ | |
813 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, | |
814 | WM8955_VREF | | |
815 | WM8955_VMIDSEL_MASK, | |
816 | WM8955_VREF | | |
817 | 0x3 << WM8955_VREF_SHIFT); | |
818 | ||
819 | /* Let VMID ramp */ | |
820 | msleep(500); | |
821 | ||
822 | /* High resistance VROI to maintain outputs */ | |
823 | snd_soc_update_bits(codec, | |
824 | WM8955_ADDITIONAL_CONTROL_3, | |
825 | WM8955_VROI, WM8955_VROI); | |
826 | } | |
827 | ||
828 | /* Maintain VMID with 2*250k */ | |
829 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, | |
830 | WM8955_VMIDSEL_MASK, | |
831 | 0x2 << WM8955_VMIDSEL_SHIFT); | |
832 | ||
833 | /* Minimum bias current */ | |
834 | snd_soc_update_bits(codec, WM8955_ADDITIONAL_CONTROL_1, | |
835 | WM8955_VSEL_MASK, 0); | |
836 | break; | |
837 | ||
838 | case SND_SOC_BIAS_OFF: | |
839 | /* Low resistance VROI to help discharge */ | |
840 | snd_soc_update_bits(codec, | |
841 | WM8955_ADDITIONAL_CONTROL_3, | |
842 | WM8955_VROI, 0); | |
843 | ||
844 | /* Turn off VMID and VREF */ | |
845 | snd_soc_update_bits(codec, WM8955_POWER_MANAGEMENT_1, | |
846 | WM8955_VREF | | |
847 | WM8955_VMIDSEL_MASK, 0); | |
848 | ||
849 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), | |
850 | wm8955->supplies); | |
851 | break; | |
852 | } | |
ce6120cc | 853 | codec->dapm.bias_level = level; |
b35a28af MB |
854 | return 0; |
855 | } | |
856 | ||
857 | #define WM8955_RATES SNDRV_PCM_RATE_8000_96000 | |
858 | ||
859 | #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
860 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
861 | ||
862 | static struct snd_soc_dai_ops wm8955_dai_ops = { | |
863 | .set_sysclk = wm8955_set_sysclk, | |
864 | .set_fmt = wm8955_set_fmt, | |
865 | .hw_params = wm8955_hw_params, | |
866 | .digital_mute = wm8955_digital_mute, | |
867 | }; | |
868 | ||
f0fba2ad LG |
869 | static struct snd_soc_dai_driver wm8955_dai = { |
870 | .name = "wm8955-hifi", | |
b35a28af MB |
871 | .playback = { |
872 | .stream_name = "Playback", | |
873 | .channels_min = 2, | |
874 | .channels_max = 2, | |
875 | .rates = WM8955_RATES, | |
876 | .formats = WM8955_FORMATS, | |
877 | }, | |
878 | .ops = &wm8955_dai_ops, | |
879 | }; | |
b35a28af MB |
880 | |
881 | #ifdef CONFIG_PM | |
f0fba2ad | 882 | static int wm8955_suspend(struct snd_soc_codec *codec, pm_message_t state) |
b35a28af | 883 | { |
b35a28af MB |
884 | wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF); |
885 | ||
886 | return 0; | |
887 | } | |
888 | ||
f0fba2ad | 889 | static int wm8955_resume(struct snd_soc_codec *codec) |
b35a28af | 890 | { |
b35a28af MB |
891 | wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
892 | ||
893 | return 0; | |
894 | } | |
895 | #else | |
896 | #define wm8955_suspend NULL | |
897 | #define wm8955_resume NULL | |
898 | #endif | |
899 | ||
f0fba2ad | 900 | static int wm8955_probe(struct snd_soc_codec *codec) |
b35a28af | 901 | { |
f0fba2ad LG |
902 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
903 | struct wm8955_pdata *pdata = dev_get_platdata(codec->dev); | |
715920d0 | 904 | u16 *reg_cache = codec->reg_cache; |
f0fba2ad | 905 | int ret, i; |
b35a28af | 906 | |
f0fba2ad | 907 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8955->control_type); |
b35a28af MB |
908 | if (ret != 0) { |
909 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 910 | return ret; |
b35a28af MB |
911 | } |
912 | ||
913 | for (i = 0; i < ARRAY_SIZE(wm8955->supplies); i++) | |
914 | wm8955->supplies[i].supply = wm8955_supply_names[i]; | |
915 | ||
916 | ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8955->supplies), | |
917 | wm8955->supplies); | |
918 | if (ret != 0) { | |
919 | dev_err(codec->dev, "Failed to request supplies: %d\n", ret); | |
f0fba2ad | 920 | return ret; |
b35a28af MB |
921 | } |
922 | ||
923 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8955->supplies), | |
924 | wm8955->supplies); | |
925 | if (ret != 0) { | |
926 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
927 | goto err_get; | |
928 | } | |
929 | ||
930 | ret = wm8955_reset(codec); | |
931 | if (ret < 0) { | |
932 | dev_err(codec->dev, "Failed to issue reset: %d\n", ret); | |
933 | goto err_enable; | |
934 | } | |
935 | ||
b35a28af | 936 | /* Change some default settings - latch VU and enable ZC */ |
a1b3b5ee MB |
937 | snd_soc_update_bits(codec, WM8955_LEFT_DAC_VOLUME, |
938 | WM8955_LDVU, WM8955_LDVU); | |
939 | snd_soc_update_bits(codec, WM8955_RIGHT_DAC_VOLUME, | |
940 | WM8955_RDVU, WM8955_RDVU); | |
941 | snd_soc_update_bits(codec, WM8955_LOUT1_VOLUME, | |
942 | WM8955_LO1VU | WM8955_LO1ZC, | |
943 | WM8955_LO1VU | WM8955_LO1ZC); | |
944 | snd_soc_update_bits(codec, WM8955_ROUT1_VOLUME, | |
945 | WM8955_RO1VU | WM8955_RO1ZC, | |
946 | WM8955_RO1VU | WM8955_RO1ZC); | |
947 | snd_soc_update_bits(codec, WM8955_LOUT2_VOLUME, | |
948 | WM8955_LO2VU | WM8955_LO2ZC, | |
949 | WM8955_LO2VU | WM8955_LO2ZC); | |
950 | snd_soc_update_bits(codec, WM8955_ROUT2_VOLUME, | |
951 | WM8955_RO2VU | WM8955_RO2ZC, | |
952 | WM8955_RO2VU | WM8955_RO2ZC); | |
953 | snd_soc_update_bits(codec, WM8955_MONOOUT_VOLUME, | |
954 | WM8955_MOZC, WM8955_MOZC); | |
b35a28af MB |
955 | |
956 | /* Also enable adaptive bass boost by default */ | |
a1b3b5ee | 957 | snd_soc_update_bits(codec, WM8955_BASS_CONTROL, WM8955_BB, WM8955_BB); |
b35a28af MB |
958 | |
959 | /* Set platform data values */ | |
f0fba2ad LG |
960 | if (pdata) { |
961 | if (pdata->out2_speaker) | |
715920d0 | 962 | reg_cache[WM8955_ADDITIONAL_CONTROL_2] |
b35a28af MB |
963 | |= WM8955_ROUT2INV; |
964 | ||
f0fba2ad | 965 | if (pdata->monoin_diff) |
715920d0 | 966 | reg_cache[WM8955_MONO_OUT_MIX_1] |
b35a28af MB |
967 | |= WM8955_DMEN; |
968 | } | |
969 | ||
970 | wm8955_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
971 | ||
972 | /* Bias level configuration will have done an extra enable */ | |
973 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); | |
974 | ||
f0fba2ad | 975 | wm8955_add_widgets(codec); |
b35a28af MB |
976 | return 0; |
977 | ||
978 | err_enable: | |
979 | regulator_bulk_disable(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); | |
980 | err_get: | |
981 | regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); | |
b35a28af MB |
982 | return ret; |
983 | } | |
984 | ||
f0fba2ad | 985 | static int wm8955_remove(struct snd_soc_codec *codec) |
b35a28af | 986 | { |
f0fba2ad LG |
987 | struct wm8955_priv *wm8955 = snd_soc_codec_get_drvdata(codec); |
988 | ||
989 | wm8955_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
b35a28af | 990 | regulator_bulk_free(ARRAY_SIZE(wm8955->supplies), wm8955->supplies); |
f0fba2ad | 991 | return 0; |
b35a28af MB |
992 | } |
993 | ||
f0fba2ad LG |
994 | static struct snd_soc_codec_driver soc_codec_dev_wm8955 = { |
995 | .probe = wm8955_probe, | |
996 | .remove = wm8955_remove, | |
997 | .suspend = wm8955_suspend, | |
998 | .resume = wm8955_resume, | |
999 | .set_bias_level = wm8955_set_bias_level, | |
1000 | .reg_cache_size = ARRAY_SIZE(wm8955_reg), | |
1001 | .reg_word_size = sizeof(u16), | |
1002 | .reg_cache_default = wm8955_reg, | |
1003 | }; | |
1004 | ||
b35a28af MB |
1005 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
1006 | static __devinit int wm8955_i2c_probe(struct i2c_client *i2c, | |
1007 | const struct i2c_device_id *id) | |
1008 | { | |
1009 | struct wm8955_priv *wm8955; | |
f0fba2ad | 1010 | int ret; |
b35a28af MB |
1011 | |
1012 | wm8955 = kzalloc(sizeof(struct wm8955_priv), GFP_KERNEL); | |
1013 | if (wm8955 == NULL) | |
1014 | return -ENOMEM; | |
1015 | ||
b35a28af | 1016 | i2c_set_clientdata(i2c, wm8955); |
7f984b55 | 1017 | wm8955->control_type = SND_SOC_I2C; |
b35a28af | 1018 | |
f0fba2ad LG |
1019 | ret = snd_soc_register_codec(&i2c->dev, |
1020 | &soc_codec_dev_wm8955, &wm8955_dai, 1); | |
1021 | if (ret < 0) | |
1022 | kfree(wm8955); | |
1023 | return ret; | |
b35a28af MB |
1024 | } |
1025 | ||
1026 | static __devexit int wm8955_i2c_remove(struct i2c_client *client) | |
1027 | { | |
f0fba2ad LG |
1028 | snd_soc_unregister_codec(&client->dev); |
1029 | kfree(i2c_get_clientdata(client)); | |
b35a28af MB |
1030 | return 0; |
1031 | } | |
1032 | ||
1033 | static const struct i2c_device_id wm8955_i2c_id[] = { | |
1034 | { "wm8955", 0 }, | |
1035 | { } | |
1036 | }; | |
1037 | MODULE_DEVICE_TABLE(i2c, wm8955_i2c_id); | |
1038 | ||
1039 | static struct i2c_driver wm8955_i2c_driver = { | |
1040 | .driver = { | |
f0fba2ad | 1041 | .name = "wm8955-codec", |
b35a28af MB |
1042 | .owner = THIS_MODULE, |
1043 | }, | |
1044 | .probe = wm8955_i2c_probe, | |
1045 | .remove = __devexit_p(wm8955_i2c_remove), | |
1046 | .id_table = wm8955_i2c_id, | |
1047 | }; | |
1048 | #endif | |
1049 | ||
1050 | static int __init wm8955_modinit(void) | |
1051 | { | |
f0fba2ad | 1052 | int ret = 0; |
b35a28af MB |
1053 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
1054 | ret = i2c_add_driver(&wm8955_i2c_driver); | |
1055 | if (ret != 0) { | |
1056 | printk(KERN_ERR "Failed to register WM8955 I2C driver: %d\n", | |
1057 | ret); | |
1058 | } | |
1059 | #endif | |
f0fba2ad | 1060 | return ret; |
b35a28af MB |
1061 | } |
1062 | module_init(wm8955_modinit); | |
1063 | ||
1064 | static void __exit wm8955_exit(void) | |
1065 | { | |
1066 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1067 | i2c_del_driver(&wm8955_i2c_driver); | |
1068 | #endif | |
1069 | } | |
1070 | module_exit(wm8955_exit); | |
1071 | ||
1072 | MODULE_DESCRIPTION("ASoC WM8955 driver"); | |
1073 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
1074 | MODULE_LICENSE("GPL"); |