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Merge tag 'keys-fixes-20150925' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / wm8960.c
CommitLineData
f2644a2c
MB		 1/*
2 * wm8960.c -- WM8960 ALSA SoC Audio driver
3 *
656baaeb
MB		 4 * Copyright 2007-11 Wolfson Microelectronics, plc
5 *
f2644a2c
MB		 6 * Author: Liam Girdwood
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
75aa8868 18#include <linux/clk.h>
f2644a2c 19#include <linux/i2c.h>
5a0e3ad6 20#include <linux/slab.h>
f2644a2c
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
f2644a2c
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
b6877a47 27#include <sound/wm8960.h>
f2644a2c
MB		 28
29#include "wm8960.h"
30
f2644a2c 31/* R25 - Power 1 */
913d7b4c 32#define WM8960_VMID_MASK 0x180
f2644a2c
MB		 33#define WM8960_VREF 0x40
34
913d7b4c
MB		 35/* R26 - Power 2 */
36#define WM8960_PWR2_LOUT1 0x40
37#define WM8960_PWR2_ROUT1 0x20
38#define WM8960_PWR2_OUT3 0x02
39
f2644a2c
MB		 40/* R28 - Anti-pop 1 */
41#define WM8960_POBCTRL 0x80
42#define WM8960_BUFDCOPEN 0x10
43#define WM8960_BUFIOEN 0x08
44#define WM8960_SOFT_ST 0x04
45#define WM8960_HPSTBY 0x01
46
47/* R29 - Anti-pop 2 */
48#define WM8960_DISOP 0x40
913d7b4c 49#define WM8960_DRES_MASK 0x30
f2644a2c 50
3176bf2d
ZW		 51static bool is_pll_freq_available(unsigned int source, unsigned int target);
52static int wm8960_set_pll(struct snd_soc_codec *codec,
53 unsigned int freq_in, unsigned int freq_out);
f2644a2c
MB		 54/*
55 * wm8960 register cache
56 * We can't read the WM8960 register space when we are
57 * using 2 wire for device control, so we cache them instead.
58 */
0ebe36c6 59static const struct reg_default wm8960_reg_defaults[] = {
b3df026e
MB		 60 { 0x0, 0x00a7 },
61 { 0x1, 0x00a7 },
0ebe36c6
MB		 62 { 0x2, 0x0000 },
63 { 0x3, 0x0000 },
64 { 0x4, 0x0000 },
65 { 0x5, 0x0008 },
66 { 0x6, 0x0000 },
67 { 0x7, 0x000a },
68 { 0x8, 0x01c0 },
69 { 0x9, 0x0000 },
70 { 0xa, 0x00ff },
71 { 0xb, 0x00ff },
72
73 { 0x10, 0x0000 },
74 { 0x11, 0x007b },
75 { 0x12, 0x0100 },
76 { 0x13, 0x0032 },
77 { 0x14, 0x0000 },
78 { 0x15, 0x00c3 },
79 { 0x16, 0x00c3 },
80 { 0x17, 0x01c0 },
81 { 0x18, 0x0000 },
82 { 0x19, 0x0000 },
83 { 0x1a, 0x0000 },
84 { 0x1b, 0x0000 },
85 { 0x1c, 0x0000 },
86 { 0x1d, 0x0000 },
87
88 { 0x20, 0x0100 },
89 { 0x21, 0x0100 },
90 { 0x22, 0x0050 },
91
92 { 0x25, 0x0050 },
93 { 0x26, 0x0000 },
94 { 0x27, 0x0000 },
95 { 0x28, 0x0000 },
96 { 0x29, 0x0000 },
97 { 0x2a, 0x0040 },
98 { 0x2b, 0x0000 },
99 { 0x2c, 0x0000 },
100 { 0x2d, 0x0050 },
101 { 0x2e, 0x0050 },
102 { 0x2f, 0x0000 },
103 { 0x30, 0x0002 },
104 { 0x31, 0x0037 },
105
106 { 0x33, 0x0080 },
107 { 0x34, 0x0008 },
108 { 0x35, 0x0031 },
109 { 0x36, 0x0026 },
110 { 0x37, 0x00e9 },
f2644a2c
MB		 111};
112
0ebe36c6
MB		 113static bool wm8960_volatile(struct device *dev, unsigned int reg)
114{
115 switch (reg) {
116 case WM8960_RESET:
117 return true;
118 default:
119 return false;
120 }
121}
122
f2644a2c 123struct wm8960_priv {
75aa8868 124 struct clk *mclk;
0ebe36c6 125 struct regmap *regmap;
f0fba2ad
LG		 126 int (*set_bias_level)(struct snd_soc_codec *,
127 enum snd_soc_bias_level level);
913d7b4c
MB		 128 struct snd_soc_dapm_widget *lout1;
129 struct snd_soc_dapm_widget *rout1;
130 struct snd_soc_dapm_widget *out3;
afd6d36a 131 bool deemph;
3176bf2d 132 int lrclk;
0e50b51a
ZW		 133 int bclk;
134 int sysclk;
3176bf2d
ZW		 135 int clk_id;
136 int freq_in;
137 bool is_stream_in_use[2];
e2280c90 138 struct wm8960_data pdata;
f2644a2c
MB		 139};
140
3ad5e861 141#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
f2644a2c
MB		 142
143/* enumerated controls */
f2644a2c
MB		 144static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
145 "Right Inverted", "Stereo Inversion"};
146static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
147static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
148static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
149static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
150
151static const struct soc_enum wm8960_enum[] = {
f2644a2c
MB		 152 SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
153 SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
154 SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
155 SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
156 SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
157 SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
158};
159
afd6d36a
MB		 160static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
161
162static int wm8960_set_deemph(struct snd_soc_codec *codec)
163{
164 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
165 int val, i, best;
166
167 /* If we're using deemphasis select the nearest available sample
168 * rate.
169 */
170 if (wm8960->deemph) {
171 best = 1;
172 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
3176bf2d
ZW		 173 if (abs(deemph_settings[i] - wm8960->lrclk) <
174 abs(deemph_settings[best] - wm8960->lrclk))
afd6d36a
MB		 175 best = i;
176 }
177
178 val = best << 1;
179 } else {
180 val = 0;
181 }
182
183 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
184
185 return snd_soc_update_bits(codec, WM8960_DACCTL1,
186 0x6, val);
187}
188
189static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
190 struct snd_ctl_elem_value *ucontrol)
191{
ea53bf77 192 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a
MB		 193 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
194
b4a18c8b 195 ucontrol->value.integer.value[0] = wm8960->deemph;
3f343f85 196 return 0;
afd6d36a
MB		 197}
198
199static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
200 struct snd_ctl_elem_value *ucontrol)
201{
ea53bf77 202 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a 203 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
b4a18c8b 204 int deemph = ucontrol->value.integer.value[0];
afd6d36a
MB		 205
206 if (deemph > 1)
207 return -EINVAL;
208
209 wm8960->deemph = deemph;
210
211 return wm8960_set_deemph(codec);
212}
213
3758ff5f 214static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
7e90f9b2 215static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0);
3758ff5f 216static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
f2644a2c
MB		 217static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
218static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
7e90f9b2
ZW		 219static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1);
220static const unsigned int micboost_tlv[] = {
221 TLV_DB_RANGE_HEAD(2),
222 0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0),
223 2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0),
224};
f2644a2c
MB		 225
226static const struct snd_kcontrol_new wm8960_snd_controls[] = {
227SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
7e90f9b2 228 0, 63, 0, inpga_tlv),
f2644a2c
MB		 229SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
230 6, 1, 0),
231SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
232 7, 1, 0),
233
21eb2693 234SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
7e90f9b2 235 WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv),
21eb2693 236SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
7e90f9b2 237 WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv),
21eb2693 238SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
7e90f9b2 239 WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv),
21eb2693 240SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
7e90f9b2
ZW		 241 WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv),
242SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume",
8524bb0c 243 WM8960_RINPATH, 4, 3, 0, micboost_tlv),
7e90f9b2 244SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume",
8524bb0c 245 WM8960_LINPATH, 4, 3, 0, micboost_tlv),
21eb2693 246
f2644a2c
MB		 247SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
248 0, 255, 0, dac_tlv),
249
250SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
251 0, 127, 0, out_tlv),
252SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
253 7, 1, 0),
254
255SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
256 0, 127, 0, out_tlv),
257SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
258 7, 1, 0),
259SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
260SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
261
262SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
4faaa8d9 263SOC_ENUM("ADC Polarity", wm8960_enum[0]),
f2644a2c
MB		 264SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
265
a077e81e 266SOC_ENUM("DAC Polarity", wm8960_enum[1]),
afd6d36a
MB		 267SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
268 wm8960_get_deemph, wm8960_put_deemph),
f2644a2c 269
4faaa8d9
MB		 270SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
271SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
f2644a2c
MB		 272SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
273SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
274
4faaa8d9 275SOC_ENUM("ALC Function", wm8960_enum[4]),
f2644a2c
MB		 276SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
277SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
278SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
279SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
4faaa8d9 280SOC_ENUM("ALC Mode", wm8960_enum[5]),
f2644a2c
MB		 281SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
282SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
283
284SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
285SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
286
c324aac0
MH		 287SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
288 0, 255, 0, adc_tlv),
f2644a2c
MB		 289
290SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
291 WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
292SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
293 WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
294SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
295 WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
296SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
297 WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
298};
299
300static const struct snd_kcontrol_new wm8960_lin_boost[] = {
301SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
302SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
303SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
304};
305
306static const struct snd_kcontrol_new wm8960_lin[] = {
307SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
308};
309
310static const struct snd_kcontrol_new wm8960_rin_boost[] = {
311SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
312SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
313SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
314};
315
316static const struct snd_kcontrol_new wm8960_rin[] = {
317SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
318};
319
320static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
321SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
322SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
323SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
324};
325
326static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
327SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
328SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
329SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
330};
331
332static const struct snd_kcontrol_new wm8960_mono_out[] = {
333SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
334SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
335};
336
337static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
338SND_SOC_DAPM_INPUT("LINPUT1"),
339SND_SOC_DAPM_INPUT("RINPUT1"),
340SND_SOC_DAPM_INPUT("LINPUT2"),
341SND_SOC_DAPM_INPUT("RINPUT2"),
342SND_SOC_DAPM_INPUT("LINPUT3"),
343SND_SOC_DAPM_INPUT("RINPUT3"),
344
187774cb 345SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
f2644a2c
MB		 346
347SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
348 wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
349SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
350 wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
351
352SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
353 wm8960_lin, ARRAY_SIZE(wm8960_lin)),
354SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
355 wm8960_rin, ARRAY_SIZE(wm8960_rin)),
356
44426de4
MB		 357SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
358SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
f2644a2c
MB		 359
360SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
361SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
362
363SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
364 &wm8960_loutput_mixer[0],
365 ARRAY_SIZE(wm8960_loutput_mixer)),
366SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
367 &wm8960_routput_mixer[0],
368 ARRAY_SIZE(wm8960_routput_mixer)),
369
f2644a2c
MB		 370SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
371SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
372
373SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
374SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
375
376SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
377SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
378
379SND_SOC_DAPM_OUTPUT("SPK_LP"),
380SND_SOC_DAPM_OUTPUT("SPK_LN"),
381SND_SOC_DAPM_OUTPUT("HP_L"),
382SND_SOC_DAPM_OUTPUT("HP_R"),
383SND_SOC_DAPM_OUTPUT("SPK_RP"),
384SND_SOC_DAPM_OUTPUT("SPK_RN"),
385SND_SOC_DAPM_OUTPUT("OUT3"),
386};
387
913d7b4c
MB		 388static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
389SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
390 &wm8960_mono_out[0],
391 ARRAY_SIZE(wm8960_mono_out)),
392};
393
394/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
395static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
396SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
397};
398
f2644a2c
MB		 399static const struct snd_soc_dapm_route audio_paths[] = {
400 { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
401 { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
402 { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
403
404 { "Left Input Mixer", "Boost Switch", "Left Boost Mixer", },
405 { "Left Input Mixer", NULL, "LINPUT1", }, /* Really Boost Switch */
406 { "Left Input Mixer", NULL, "LINPUT2" },
407 { "Left Input Mixer", NULL, "LINPUT3" },
408
409 { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
410 { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
411 { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
412
413 { "Right Input Mixer", "Boost Switch", "Right Boost Mixer", },
414 { "Right Input Mixer", NULL, "RINPUT1", }, /* Really Boost Switch */
415 { "Right Input Mixer", NULL, "RINPUT2" },
85e36a1f 416 { "Right Input Mixer", NULL, "RINPUT3" },
f2644a2c
MB		 417
418 { "Left ADC", NULL, "Left Input Mixer" },
419 { "Right ADC", NULL, "Right Input Mixer" },
420
421 { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
422 { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer"} ,
423 { "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
424
425 { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
426 { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" } ,
427 { "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
428
f2644a2c
MB		 429 { "LOUT1 PGA", NULL, "Left Output Mixer" },
430 { "ROUT1 PGA", NULL, "Right Output Mixer" },
431
432 { "HP_L", NULL, "LOUT1 PGA" },
433 { "HP_R", NULL, "ROUT1 PGA" },
434
435 { "Left Speaker PGA", NULL, "Left Output Mixer" },
436 { "Right Speaker PGA", NULL, "Right Output Mixer" },
437
438 { "Left Speaker Output", NULL, "Left Speaker PGA" },
439 { "Right Speaker Output", NULL, "Right Speaker PGA" },
440
441 { "SPK_LN", NULL, "Left Speaker Output" },
442 { "SPK_LP", NULL, "Left Speaker Output" },
443 { "SPK_RN", NULL, "Right Speaker Output" },
444 { "SPK_RP", NULL, "Right Speaker Output" },
913d7b4c
MB		 445};
446
447static const struct snd_soc_dapm_route audio_paths_out3[] = {
448 { "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
449 { "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
f2644a2c
MB		 450
451 { "OUT3", NULL, "Mono Output Mixer", }
452};
453
913d7b4c
MB		 454static const struct snd_soc_dapm_route audio_paths_capless[] = {
455 { "HP_L", NULL, "OUT3 VMID" },
456 { "HP_R", NULL, "OUT3 VMID" },
457
458 { "OUT3 VMID", NULL, "Left Output Mixer" },
459 { "OUT3 VMID", NULL, "Right Output Mixer" },
460};
461
f2644a2c
MB		 462static int wm8960_add_widgets(struct snd_soc_codec *codec)
463{
b2c812e2 464 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 465 struct wm8960_data *pdata = &wm8960->pdata;
93f32f53 466 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
913d7b4c
MB		 467 struct snd_soc_dapm_widget *w;
468
ce6120cc 469 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
f2644a2c
MB		 470 ARRAY_SIZE(wm8960_dapm_widgets));
471
ce6120cc 472 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
f2644a2c 473
913d7b4c
MB		 474 /* In capless mode OUT3 is used to provide VMID for the
475 * headphone outputs, otherwise it is used as a mono mixer.
476 */
477 if (pdata && pdata->capless) {
ce6120cc 478 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
913d7b4c
MB		 479 ARRAY_SIZE(wm8960_dapm_widgets_capless));
480
ce6120cc 481 snd_soc_dapm_add_routes(dapm, audio_paths_capless,
913d7b4c
MB		 482 ARRAY_SIZE(audio_paths_capless));
483 } else {
ce6120cc 484 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
913d7b4c
MB		 485 ARRAY_SIZE(wm8960_dapm_widgets_out3));
486
ce6120cc 487 snd_soc_dapm_add_routes(dapm, audio_paths_out3,
913d7b4c
MB		 488 ARRAY_SIZE(audio_paths_out3));
489 }
490
491 /* We need to power up the headphone output stage out of
492 * sequence for capless mode. To save scanning the widget
493 * list each time to find the desired power state do so now
494 * and save the result.
495 */
00200107 496 list_for_each_entry(w, &codec->component.card->widgets, list) {
93f32f53 497 if (w->dapm != dapm)
97c866de 498 continue;
913d7b4c
MB		 499 if (strcmp(w->name, "LOUT1 PGA") == 0)
500 wm8960->lout1 = w;
501 if (strcmp(w->name, "ROUT1 PGA") == 0)
502 wm8960->rout1 = w;
503 if (strcmp(w->name, "OUT3 VMID") == 0)
504 wm8960->out3 = w;
505 }
506
f2644a2c
MB		 507 return 0;
508}
509
510static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
511 unsigned int fmt)
512{
513 struct snd_soc_codec *codec = codec_dai->codec;
514 u16 iface = 0;
515
516 /* set master/slave audio interface */
517 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
518 case SND_SOC_DAIFMT_CBM_CFM:
519 iface |= 0x0040;
520 break;
521 case SND_SOC_DAIFMT_CBS_CFS:
522 break;
523 default:
524 return -EINVAL;
525 }
526
527 /* interface format */
528 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
529 case SND_SOC_DAIFMT_I2S:
530 iface |= 0x0002;
531 break;
532 case SND_SOC_DAIFMT_RIGHT_J:
533 break;
534 case SND_SOC_DAIFMT_LEFT_J:
535 iface |= 0x0001;
536 break;
537 case SND_SOC_DAIFMT_DSP_A:
538 iface |= 0x0003;
539 break;
540 case SND_SOC_DAIFMT_DSP_B:
541 iface |= 0x0013;
542 break;
543 default:
544 return -EINVAL;
545 }
546
547 /* clock inversion */
548 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
549 case SND_SOC_DAIFMT_NB_NF:
550 break;
551 case SND_SOC_DAIFMT_IB_IF:
552 iface |= 0x0090;
553 break;
554 case SND_SOC_DAIFMT_IB_NF:
555 iface |= 0x0080;
556 break;
557 case SND_SOC_DAIFMT_NB_IF:
558 iface |= 0x0010;
559 break;
560 default:
561 return -EINVAL;
562 }
563
564 /* set iface */
17a52fd6 565 snd_soc_write(codec, WM8960_IFACE1, iface);
f2644a2c
MB		 566 return 0;
567}
568
db059c0f
MB		 569static struct {
570 int rate;
571 unsigned int val;
572} alc_rates[] = {
573 { 48000, 0 },
574 { 44100, 0 },
575 { 32000, 1 },
576 { 22050, 2 },
577 { 24000, 2 },
578 { 16000, 3 },
22ee76da 579 { 11025, 4 },
db059c0f
MB		 580 { 12000, 4 },
581 { 8000, 5 },
582};
583
3176bf2d
ZW		 584/* -1 for reserved value */
585static const int sysclk_divs[] = { 1, -1, 2, -1 };
586
0e50b51a
ZW		 587/* Multiply 256 for internal 256 div */
588static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
589
590/* Multiply 10 to eliminate decimials */
591static const int bclk_divs[] = {
592 10, 15, 20, 30, 40, 55, 60, 80, 110,
593 120, 160, 220, 240, 320, 320, 320
594};
595
3176bf2d 596static int wm8960_configure_clocking(struct snd_soc_codec *codec)
0e50b51a
ZW		 597{
598 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 599 int sysclk, bclk, lrclk, freq_out, freq_in;
0e50b51a 600 u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
3176bf2d 601 int i, j, k;
0e50b51a
ZW		 602
603 if (!(iface1 & (1<<6))) {
604 dev_dbg(codec->dev,
605 "Codec is slave mode, no need to configure clock\n");
3176bf2d
ZW		 606 return 0;
607 }
608
609 if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
610 dev_err(codec->dev, "No MCLK configured\n");
611 return -EINVAL;
0e50b51a
ZW		 612 }
613
3176bf2d
ZW		 614 freq_in = wm8960->freq_in;
615 bclk = wm8960->bclk;
616 lrclk = wm8960->lrclk;
617 /*
618 * If it's sysclk auto mode, check if the MCLK can provide sysclk or
619 * not. If MCLK can provide sysclk, using MCLK to provide sysclk
620 * directly. Otherwise, auto select a available pll out frequency
621 * and set PLL.
622 */
623 if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
624 /* disable the PLL and using MCLK to provide sysclk */
625 wm8960_set_pll(codec, 0, 0);
626 freq_out = freq_in;
627 } else if (wm8960->sysclk) {
628 freq_out = wm8960->sysclk;
629 } else {
630 dev_err(codec->dev, "No SYSCLK configured\n");
631 return -EINVAL;
0e50b51a
ZW		 632 }
633
3176bf2d
ZW		 634 /* check if the sysclk frequency is available. */
635 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
636 if (sysclk_divs[i] == -1)
637 continue;
638 sysclk = freq_out / sysclk_divs[i];
639 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
640 if (sysclk == dac_divs[j] * lrclk) {
641 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k)
642 if (sysclk == bclk * bclk_divs[k] / 10)
643 break;
644 if (k != ARRAY_SIZE(bclk_divs))
645 break;
646 }
647 }
648 if (j != ARRAY_SIZE(dac_divs))
649 break;
0e50b51a
ZW		 650 }
651
3176bf2d
ZW		 652 if (i != ARRAY_SIZE(sysclk_divs)) {
653 goto configure_clock;
654 } else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
655 dev_err(codec->dev, "failed to configure clock\n");
656 return -EINVAL;
657 }
658 /* get a available pll out frequency and set pll */
659 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
660 if (sysclk_divs[i] == -1)
661 continue;
662 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
663 sysclk = lrclk * dac_divs[j];
664 freq_out = sysclk * sysclk_divs[i];
665
666 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
667 if (sysclk == bclk * bclk_divs[k] / 10 &&
668 is_pll_freq_available(freq_in, freq_out)) {
669 wm8960_set_pll(codec,
670 freq_in, freq_out);
0e50b51a 671 break;
3176bf2d
ZW		 672 } else {
673 continue;
674 }
0e50b51a 675 }
3176bf2d 676 if (k != ARRAY_SIZE(bclk_divs))
0e50b51a
ZW		 677 break;
678 }
3176bf2d
ZW		 679 if (j != ARRAY_SIZE(dac_divs))
680 break;
0e50b51a
ZW		 681 }
682
3176bf2d
ZW		 683 if (i == ARRAY_SIZE(sysclk_divs)) {
684 dev_err(codec->dev, "failed to configure clock\n");
685 return -EINVAL;
0e50b51a
ZW		 686 }
687
3176bf2d
ZW		 688configure_clock:
689 /* configure sysclk clock */
690 snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1);
691
692 /* configure frame clock */
693 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3);
694 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6);
0e50b51a
ZW		 695
696 /* configure bit clock */
3176bf2d
ZW		 697 snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k);
698
699 return 0;
0e50b51a
ZW		 700}
701
f2644a2c
MB		 702static int wm8960_hw_params(struct snd_pcm_substream *substream,
703 struct snd_pcm_hw_params *params,
704 struct snd_soc_dai *dai)
705{
e6968a17 706 struct snd_soc_codec *codec = dai->codec;
afd6d36a 707 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
17a52fd6 708 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
0e50b51a 709 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
db059c0f 710 int i;
f2644a2c 711
0e50b51a
ZW		 712 wm8960->bclk = snd_soc_params_to_bclk(params);
713 if (params_channels(params) == 1)
714 wm8960->bclk *= 2;
715
f2644a2c 716 /* bit size */
39e9cc46
MB		 717 switch (params_width(params)) {
718 case 16:
f2644a2c 719 break;
39e9cc46 720 case 20:
f2644a2c
MB		 721 iface |= 0x0004;
722 break;
39e9cc46 723 case 24:
f2644a2c
MB		 724 iface |= 0x0008;
725 break;
7a8c7867
ZW		 726 case 32:
727 /* right justify mode does not support 32 word length */
728 if ((iface & 0x3) != 0) {
729 iface |= 0x000c;
730 break;
731 }
4c2474c0 732 default:
39e9cc46
MB		 733 dev_err(codec->dev, "unsupported width %d\n",
734 params_width(params));
4c2474c0 735 return -EINVAL;
f2644a2c
MB		 736 }
737
3176bf2d 738 wm8960->lrclk = params_rate(params);
afd6d36a 739 /* Update filters for the new rate */
3176bf2d 740 if (tx) {
afd6d36a 741 wm8960_set_deemph(codec);
db059c0f
MB		 742 } else {
743 for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
744 if (alc_rates[i].rate == params_rate(params))
745 snd_soc_update_bits(codec,
746 WM8960_ADDCTL3, 0x7,
747 alc_rates[i].val);
afd6d36a
MB		 748 }
749
f2644a2c 750 /* set iface */
17a52fd6 751 snd_soc_write(codec, WM8960_IFACE1, iface);
0e50b51a 752
3176bf2d
ZW		 753 wm8960->is_stream_in_use[tx] = true;
754
755 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON &&
756 !wm8960->is_stream_in_use[!tx])
757 return wm8960_configure_clocking(codec);
758
759 return 0;
760}
761
762static int wm8960_hw_free(struct snd_pcm_substream *substream,
763 struct snd_soc_dai *dai)
764{
765 struct snd_soc_codec *codec = dai->codec;
766 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
767 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
768
769 wm8960->is_stream_in_use[tx] = false;
0e50b51a 770
f2644a2c
MB		 771 return 0;
772}
773
774static int wm8960_mute(struct snd_soc_dai *dai, int mute)
775{
776 struct snd_soc_codec *codec = dai->codec;
f2644a2c
MB		 777
778 if (mute)
16b24881 779 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8);
f2644a2c 780 else
16b24881 781 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0);
f2644a2c
MB		 782 return 0;
783}
784
913d7b4c
MB		 785static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
786 enum snd_soc_bias_level level)
f2644a2c 787{
0ebe36c6 788 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 789 u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
75aa8868 790 int ret;
0ebe36c6 791
f2644a2c
MB		 792 switch (level) {
793 case SND_SOC_BIAS_ON:
794 break;
795
796 case SND_SOC_BIAS_PREPARE:
93f32f53 797 switch (snd_soc_codec_get_bias_level(codec)) {
75aa8868
ZW		 798 case SND_SOC_BIAS_STANDBY:
799 if (!IS_ERR(wm8960->mclk)) {
800 ret = clk_prepare_enable(wm8960->mclk);
801 if (ret) {
802 dev_err(codec->dev,
803 "Failed to enable MCLK: %d\n",
804 ret);
805 return ret;
806 }
807 }
808
3176bf2d
ZW		 809 ret = wm8960_configure_clocking(codec);
810 if (ret)
811 return ret;
812
75aa8868
ZW		 813 /* Set VMID to 2x50k */
814 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
815 break;
816
817 case SND_SOC_BIAS_ON:
3176bf2d
ZW		 818 /*
819 * If it's sysclk auto mode, and the pll is enabled,
820 * disable the pll
821 */
822 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
823 wm8960_set_pll(codec, 0, 0);
824
75aa8868
ZW		 825 if (!IS_ERR(wm8960->mclk))
826 clk_disable_unprepare(wm8960->mclk);
827 break;
828
829 default:
830 break;
831 }
832
f2644a2c
MB		 833 break;
834
835 case SND_SOC_BIAS_STANDBY:
93f32f53 836 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
0ebe36c6 837 regcache_sync(wm8960->regmap);
bc45df2d 838
f2644a2c 839 /* Enable anti-pop features */
17a52fd6 840 snd_soc_write(codec, WM8960_APOP1,
913d7b4c
MB		 841 WM8960_POBCTRL | WM8960_SOFT_ST |
842 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
f2644a2c
MB		 843
844 /* Enable & ramp VMID at 2x50k */
16b24881 845 snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80);
f2644a2c
MB		 846 msleep(100);
847
848 /* Enable VREF */
16b24881
AL		 849 snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF,
850 WM8960_VREF);
f2644a2c
MB		 851
852 /* Disable anti-pop features */
17a52fd6 853 snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
f2644a2c
MB		 854 }
855
856 /* Set VMID to 2x250k */
16b24881 857 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
f2644a2c
MB		 858 break;
859
860 case SND_SOC_BIAS_OFF:
861 /* Enable anti-pop features */
17a52fd6 862 snd_soc_write(codec, WM8960_APOP1,
f2644a2c
MB		 863 WM8960_POBCTRL | WM8960_SOFT_ST |
864 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
865
866 /* Disable VMID and VREF, let them discharge */
17a52fd6 867 snd_soc_write(codec, WM8960_POWER1, 0);
f2644a2c 868 msleep(600);
913d7b4c
MB		 869 break;
870 }
871
913d7b4c
MB		 872 return 0;
873}
874
875static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
876 enum snd_soc_bias_level level)
877{
b2c812e2 878 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 879 u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
75aa8868 880 int reg, ret;
913d7b4c
MB		 881
882 switch (level) {
883 case SND_SOC_BIAS_ON:
884 break;
885
886 case SND_SOC_BIAS_PREPARE:
93f32f53 887 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 888 case SND_SOC_BIAS_STANDBY:
889 /* Enable anti pop mode */
890 snd_soc_update_bits(codec, WM8960_APOP1,
891 WM8960_POBCTRL | WM8960_SOFT_ST |
892 WM8960_BUFDCOPEN,
893 WM8960_POBCTRL | WM8960_SOFT_ST |
894 WM8960_BUFDCOPEN);
895
896 /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
897 reg = 0;
898 if (wm8960->lout1 && wm8960->lout1->power)
899 reg |= WM8960_PWR2_LOUT1;
900 if (wm8960->rout1 && wm8960->rout1->power)
901 reg |= WM8960_PWR2_ROUT1;
902 if (wm8960->out3 && wm8960->out3->power)
903 reg |= WM8960_PWR2_OUT3;
904 snd_soc_update_bits(codec, WM8960_POWER2,
905 WM8960_PWR2_LOUT1 |
906 WM8960_PWR2_ROUT1 |
907 WM8960_PWR2_OUT3, reg);
908
909 /* Enable VMID at 2*50k */
910 snd_soc_update_bits(codec, WM8960_POWER1,
911 WM8960_VMID_MASK, 0x80);
912
913 /* Ramp */
914 msleep(100);
915
916 /* Enable VREF */
917 snd_soc_update_bits(codec, WM8960_POWER1,
918 WM8960_VREF, WM8960_VREF);
919
920 msleep(100);
75aa8868
ZW		 921
922 if (!IS_ERR(wm8960->mclk)) {
923 ret = clk_prepare_enable(wm8960->mclk);
924 if (ret) {
925 dev_err(codec->dev,
926 "Failed to enable MCLK: %d\n",
927 ret);
928 return ret;
929 }
930 }
3176bf2d
ZW		 931
932 ret = wm8960_configure_clocking(codec);
933 if (ret)
934 return ret;
935
913d7b4c
MB		 936 break;
937
938 case SND_SOC_BIAS_ON:
3176bf2d
ZW		 939 /*
940 * If it's sysclk auto mode, and the pll is enabled,
941 * disable the pll
942 */
943 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
944 wm8960_set_pll(codec, 0, 0);
945
75aa8868
ZW		 946 if (!IS_ERR(wm8960->mclk))
947 clk_disable_unprepare(wm8960->mclk);
948
913d7b4c
MB		 949 /* Enable anti-pop mode */
950 snd_soc_update_bits(codec, WM8960_APOP1,
951 WM8960_POBCTRL | WM8960_SOFT_ST |
952 WM8960_BUFDCOPEN,
953 WM8960_POBCTRL | WM8960_SOFT_ST |
954 WM8960_BUFDCOPEN);
955
956 /* Disable VMID and VREF */
957 snd_soc_update_bits(codec, WM8960_POWER1,
958 WM8960_VREF | WM8960_VMID_MASK, 0);
959 break;
960
bc45df2d 961 case SND_SOC_BIAS_OFF:
0ebe36c6 962 regcache_sync(wm8960->regmap);
bc45df2d 963 break;
913d7b4c
MB		 964 default:
965 break;
966 }
967 break;
f2644a2c 968
913d7b4c 969 case SND_SOC_BIAS_STANDBY:
93f32f53 970 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 971 case SND_SOC_BIAS_PREPARE:
972 /* Disable HP discharge */
973 snd_soc_update_bits(codec, WM8960_APOP2,
974 WM8960_DISOP | WM8960_DRES_MASK,
975 0);
976
977 /* Disable anti-pop features */
978 snd_soc_update_bits(codec, WM8960_APOP1,
979 WM8960_POBCTRL | WM8960_SOFT_ST |
980 WM8960_BUFDCOPEN,
981 WM8960_POBCTRL | WM8960_SOFT_ST |
982 WM8960_BUFDCOPEN);
983 break;
984
985 default:
986 break;
987 }
988 break;
f2644a2c 989
913d7b4c 990 case SND_SOC_BIAS_OFF:
f2644a2c
MB		 991 break;
992 }
993
f2644a2c
MB		 994 return 0;
995}
996
997/* PLL divisors */
998struct _pll_div {
999 u32 pre_div:1;
1000 u32 n:4;
1001 u32 k:24;
1002};
1003
3176bf2d
ZW		 1004static bool is_pll_freq_available(unsigned int source, unsigned int target)
1005{
1006 unsigned int Ndiv;
1007
1008 if (source == 0 || target == 0)
1009 return false;
1010
1011 /* Scale up target to PLL operating frequency */
1012 target *= 4;
1013 Ndiv = target / source;
1014
1015 if (Ndiv < 6) {
1016 source >>= 1;
1017 Ndiv = target / source;
1018 }
1019
1020 if ((Ndiv < 6) || (Ndiv > 12))
1021 return false;
1022
1023 return true;
1024}
1025
f2644a2c
MB		 1026/* The size in bits of the pll divide multiplied by 10
1027 * to allow rounding later */
1028#define FIXED_PLL_SIZE ((1 << 24) * 10)
1029
1030static int pll_factors(unsigned int source, unsigned int target,
1031 struct _pll_div *pll_div)
1032{
1033 unsigned long long Kpart;
1034 unsigned int K, Ndiv, Nmod;
1035
1036 pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
1037
1038 /* Scale up target to PLL operating frequency */
1039 target *= 4;
1040
1041 Ndiv = target / source;
1042 if (Ndiv < 6) {
1043 source >>= 1;
1044 pll_div->pre_div = 1;
1045 Ndiv = target / source;
1046 } else
1047 pll_div->pre_div = 0;
1048
1049 if ((Ndiv < 6) || (Ndiv > 12)) {
1050 pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
1051 return -EINVAL;
1052 }
1053
1054 pll_div->n = Ndiv;
1055 Nmod = target % source;
1056 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1057
1058 do_div(Kpart, source);
1059
1060 K = Kpart & 0xFFFFFFFF;
1061
1062 /* Check if we need to round */
1063 if ((K % 10) >= 5)
1064 K += 5;
1065
1066 /* Move down to proper range now rounding is done */
1067 K /= 10;
1068
1069 pll_div->k = K;
1070
1071 pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
1072 pll_div->n, pll_div->k, pll_div->pre_div);
1073
1074 return 0;
1075}
1076
3176bf2d
ZW		 1077static int wm8960_set_pll(struct snd_soc_codec *codec,
1078 unsigned int freq_in, unsigned int freq_out)
f2644a2c 1079{
f2644a2c
MB		 1080 u16 reg;
1081 static struct _pll_div pll_div;
1082 int ret;
1083
1084 if (freq_in && freq_out) {
1085 ret = pll_factors(freq_in, freq_out, &pll_div);
1086 if (ret != 0)
1087 return ret;
1088 }
1089
1090 /* Disable the PLL: even if we are changing the frequency the
1091 * PLL needs to be disabled while we do so. */
16b24881
AL		 1092 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0);
1093 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0);
f2644a2c
MB		 1094
1095 if (!freq_in || !freq_out)
1096 return 0;
1097
17a52fd6 1098 reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
f2644a2c
MB		 1099 reg |= pll_div.pre_div << 4;
1100 reg |= pll_div.n;
1101
1102 if (pll_div.k) {
1103 reg |= 0x20;
1104
85fa532b
MD		 1105 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
1106 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
1107 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
f2644a2c 1108 }
17a52fd6 1109 snd_soc_write(codec, WM8960_PLL1, reg);
f2644a2c
MB		 1110
1111 /* Turn it on */
16b24881 1112 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1);
f2644a2c 1113 msleep(250);
16b24881 1114 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1);
f2644a2c
MB		 1115
1116 return 0;
1117}
1118
3176bf2d
ZW		 1119static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1120 int source, unsigned int freq_in, unsigned int freq_out)
1121{
1122 struct snd_soc_codec *codec = codec_dai->codec;
1123 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1124
1125 wm8960->freq_in = freq_in;
1126
1127 if (pll_id == WM8960_SYSCLK_AUTO)
1128 return 0;
1129
1130 return wm8960_set_pll(codec, freq_in, freq_out);
1131}
1132
f2644a2c
MB		 1133static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1134 int div_id, int div)
1135{
1136 struct snd_soc_codec *codec = codec_dai->codec;
1137 u16 reg;
1138
1139 switch (div_id) {
f2644a2c 1140 case WM8960_SYSCLKDIV:
17a52fd6
MB		 1141 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
1142 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1143 break;
1144 case WM8960_DACDIV:
17a52fd6
MB		 1145 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
1146 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1147 break;
1148 case WM8960_OPCLKDIV:
17a52fd6
MB		 1149 reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
1150 snd_soc_write(codec, WM8960_PLL1, reg | div);
f2644a2c
MB		 1151 break;
1152 case WM8960_DCLKDIV:
17a52fd6
MB		 1153 reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
1154 snd_soc_write(codec, WM8960_CLOCK2, reg | div);
f2644a2c
MB		 1155 break;
1156 case WM8960_TOCLKSEL:
17a52fd6
MB		 1157 reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
1158 snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
f2644a2c
MB		 1159 break;
1160 default:
1161 return -EINVAL;
1162 }
1163
1164 return 0;
1165}
1166
f0fba2ad
LG		 1167static int wm8960_set_bias_level(struct snd_soc_codec *codec,
1168 enum snd_soc_bias_level level)
1169{
1170 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1171
1172 return wm8960->set_bias_level(codec, level);
1173}
1174
0e50b51a
ZW		 1175static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1176 unsigned int freq, int dir)
1177{
1178 struct snd_soc_codec *codec = dai->codec;
1179 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1180
1181 switch (clk_id) {
1182 case WM8960_SYSCLK_MCLK:
1183 snd_soc_update_bits(codec, WM8960_CLOCK1,
1184 0x1, WM8960_SYSCLK_MCLK);
1185 break;
1186 case WM8960_SYSCLK_PLL:
1187 snd_soc_update_bits(codec, WM8960_CLOCK1,
1188 0x1, WM8960_SYSCLK_PLL);
1189 break;
3176bf2d
ZW		 1190 case WM8960_SYSCLK_AUTO:
1191 break;
0e50b51a
ZW		 1192 default:
1193 return -EINVAL;
1194 }
1195
1196 wm8960->sysclk = freq;
3176bf2d 1197 wm8960->clk_id = clk_id;
0e50b51a
ZW		 1198
1199 return 0;
1200}
1201
f2644a2c
MB		 1202#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
1203
1204#define WM8960_FORMATS \
1205 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
7a8c7867 1206 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
f2644a2c 1207
85e7652d 1208static const struct snd_soc_dai_ops wm8960_dai_ops = {
f2644a2c 1209 .hw_params = wm8960_hw_params,
3176bf2d 1210 .hw_free = wm8960_hw_free,
f2644a2c
MB		 1211 .digital_mute = wm8960_mute,
1212 .set_fmt = wm8960_set_dai_fmt,
1213 .set_clkdiv = wm8960_set_dai_clkdiv,
1214 .set_pll = wm8960_set_dai_pll,
0e50b51a 1215 .set_sysclk = wm8960_set_dai_sysclk,
f2644a2c
MB		 1216};
1217
f0fba2ad
LG		 1218static struct snd_soc_dai_driver wm8960_dai = {
1219 .name = "wm8960-hifi",
f2644a2c
MB		 1220 .playback = {
1221 .stream_name = "Playback",
1222 .channels_min = 1,
1223 .channels_max = 2,
1224 .rates = WM8960_RATES,
1225 .formats = WM8960_FORMATS,},
1226 .capture = {
1227 .stream_name = "Capture",
1228 .channels_min = 1,
1229 .channels_max = 2,
1230 .rates = WM8960_RATES,
1231 .formats = WM8960_FORMATS,},
1232 .ops = &wm8960_dai_ops,
1233 .symmetric_rates = 1,
1234};
f2644a2c 1235
f0fba2ad 1236static int wm8960_probe(struct snd_soc_codec *codec)
f2644a2c 1237{
f0fba2ad 1238 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 1239 struct wm8960_data *pdata = &wm8960->pdata;
f2644a2c 1240
e2280c90
ZW		 1241 if (pdata->capless)
1242 wm8960->set_bias_level = wm8960_set_bias_level_capless;
1243 else
1244 wm8960->set_bias_level = wm8960_set_bias_level_out3;
f2644a2c 1245
022658be 1246 snd_soc_add_codec_controls(codec, wm8960_snd_controls,
f0fba2ad
LG		 1247 ARRAY_SIZE(wm8960_snd_controls));
1248 wm8960_add_widgets(codec);
f2644a2c
MB		 1249
1250 return 0;
1251}
1252
f0fba2ad
LG		 1253static struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
1254 .probe = wm8960_probe,
f0fba2ad 1255 .set_bias_level = wm8960_set_bias_level,
0a87a6e1 1256 .suspend_bias_off = true,
0ebe36c6
MB		 1257};
1258
1259static const struct regmap_config wm8960_regmap = {
1260 .reg_bits = 7,
1261 .val_bits = 9,
1262 .max_register = WM8960_PLL4,
1263
1264 .reg_defaults = wm8960_reg_defaults,
1265 .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
1266 .cache_type = REGCACHE_RBTREE,
1267
1268 .volatile_reg = wm8960_volatile,
f0fba2ad
LG		 1269};
1270
e2280c90
ZW		 1271static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
1272 struct wm8960_data *pdata)
1273{
1274 const struct device_node *np = i2c->dev.of_node;
1275
1276 if (of_property_read_bool(np, "wlf,capless"))
1277 pdata->capless = true;
1278
1279 if (of_property_read_bool(np, "wlf,shared-lrclk"))
1280 pdata->shared_lrclk = true;
1281}
1282
7a79e94e
BP		 1283static int wm8960_i2c_probe(struct i2c_client *i2c,
1284 const struct i2c_device_id *id)
f2644a2c 1285{
37061631 1286 struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
f2644a2c 1287 struct wm8960_priv *wm8960;
f0fba2ad 1288 int ret;
f2644a2c 1289
b9791c01
MB		 1290 wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
1291 GFP_KERNEL);
f2644a2c
MB		 1292 if (wm8960 == NULL)
1293 return -ENOMEM;
1294
75aa8868
ZW		 1295 wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
1296 if (IS_ERR(wm8960->mclk)) {
1297 if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
1298 return -EPROBE_DEFER;
1299 }
1300
c5e6f5fa 1301 wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
0ebe36c6
MB		 1302 if (IS_ERR(wm8960->regmap))
1303 return PTR_ERR(wm8960->regmap);
1304
e2280c90
ZW		 1305 if (pdata)
1306 memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
1307 else if (i2c->dev.of_node)
1308 wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
1309
3ad5e861
ZW		 1310 ret = wm8960_reset(wm8960->regmap);
1311 if (ret != 0) {
1312 dev_err(&i2c->dev, "Failed to issue reset\n");
1313 return ret;
1314 }
1315
1316 if (wm8960->pdata.shared_lrclk) {
37061631
MB		 1317 ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
1318 0x4, 0x4);
1319 if (ret != 0) {
1320 dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
1321 ret);
1322 return ret;
1323 }
1324 }
1325
3ad5e861
ZW		 1326 /* Latch the update bits */
1327 regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
1328 regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
1329 regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
1330 regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
1331 regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
1332 regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
1333 regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
1334 regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
1335 regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
1336 regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
1337
f2644a2c 1338 i2c_set_clientdata(i2c, wm8960);
f2644a2c 1339
f0fba2ad
LG		 1340 ret = snd_soc_register_codec(&i2c->dev,
1341 &soc_codec_dev_wm8960, &wm8960_dai, 1);
b9791c01 1342
f0fba2ad 1343 return ret;
f2644a2c
MB		 1344}
1345
7a79e94e 1346static int wm8960_i2c_remove(struct i2c_client *client)
f2644a2c 1347{
f0fba2ad 1348 snd_soc_unregister_codec(&client->dev);
f2644a2c
MB		 1349 return 0;
1350}
1351
1352static const struct i2c_device_id wm8960_i2c_id[] = {
1353 { "wm8960", 0 },
1354 { }
1355};
1356MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
1357
e2280c90
ZW		 1358static const struct of_device_id wm8960_of_match[] = {
1359 { .compatible = "wlf,wm8960", },
1360 { }
1361};
1362MODULE_DEVICE_TABLE(of, wm8960_of_match);
1363
f2644a2c
MB		 1364static struct i2c_driver wm8960_i2c_driver = {
1365 .driver = {
091edccf 1366 .name = "wm8960",
e2280c90 1367 .of_match_table = wm8960_of_match,
f2644a2c
MB		 1368 },
1369 .probe = wm8960_i2c_probe,
7a79e94e 1370 .remove = wm8960_i2c_remove,
f2644a2c
MB		 1371 .id_table = wm8960_i2c_id,
1372};
1373
3c010e60 1374module_i2c_driver(wm8960_i2c_driver);
f2644a2c 1375
f2644a2c
MB		 1376MODULE_DESCRIPTION("ASoC WM8960 driver");
1377MODULE_AUTHOR("Liam Girdwood");
1378MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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