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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[deliverable/linux.git] / sound / soc / codecs / wm8960.c
CommitLineData
f2644a2c
MB		 1/*
2 * wm8960.c -- WM8960 ALSA SoC Audio driver
3 *
656baaeb
MB		 4 * Copyright 2007-11 Wolfson Microelectronics, plc
5 *
f2644a2c
MB		 6 * Author: Liam Girdwood
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
75aa8868 18#include <linux/clk.h>
f2644a2c 19#include <linux/i2c.h>
5a0e3ad6 20#include <linux/slab.h>
f2644a2c
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
f2644a2c
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
b6877a47 27#include <sound/wm8960.h>
f2644a2c
MB		 28
29#include "wm8960.h"
30
f2644a2c 31/* R25 - Power 1 */
913d7b4c 32#define WM8960_VMID_MASK 0x180
f2644a2c
MB		 33#define WM8960_VREF 0x40
34
913d7b4c
MB		 35/* R26 - Power 2 */
36#define WM8960_PWR2_LOUT1 0x40
37#define WM8960_PWR2_ROUT1 0x20
38#define WM8960_PWR2_OUT3 0x02
39
f2644a2c
MB		 40/* R28 - Anti-pop 1 */
41#define WM8960_POBCTRL 0x80
42#define WM8960_BUFDCOPEN 0x10
43#define WM8960_BUFIOEN 0x08
44#define WM8960_SOFT_ST 0x04
45#define WM8960_HPSTBY 0x01
46
47/* R29 - Anti-pop 2 */
48#define WM8960_DISOP 0x40
913d7b4c 49#define WM8960_DRES_MASK 0x30
f2644a2c 50
3176bf2d
ZW		 51static bool is_pll_freq_available(unsigned int source, unsigned int target);
52static int wm8960_set_pll(struct snd_soc_codec *codec,
53 unsigned int freq_in, unsigned int freq_out);
f2644a2c
MB		 54/*
55 * wm8960 register cache
56 * We can't read the WM8960 register space when we are
57 * using 2 wire for device control, so we cache them instead.
58 */
0ebe36c6 59static const struct reg_default wm8960_reg_defaults[] = {
b3df026e
MB		 60 { 0x0, 0x00a7 },
61 { 0x1, 0x00a7 },
0ebe36c6
MB		 62 { 0x2, 0x0000 },
63 { 0x3, 0x0000 },
64 { 0x4, 0x0000 },
65 { 0x5, 0x0008 },
66 { 0x6, 0x0000 },
67 { 0x7, 0x000a },
68 { 0x8, 0x01c0 },
69 { 0x9, 0x0000 },
70 { 0xa, 0x00ff },
71 { 0xb, 0x00ff },
72
73 { 0x10, 0x0000 },
74 { 0x11, 0x007b },
75 { 0x12, 0x0100 },
76 { 0x13, 0x0032 },
77 { 0x14, 0x0000 },
78 { 0x15, 0x00c3 },
79 { 0x16, 0x00c3 },
80 { 0x17, 0x01c0 },
81 { 0x18, 0x0000 },
82 { 0x19, 0x0000 },
83 { 0x1a, 0x0000 },
84 { 0x1b, 0x0000 },
85 { 0x1c, 0x0000 },
86 { 0x1d, 0x0000 },
87
88 { 0x20, 0x0100 },
89 { 0x21, 0x0100 },
90 { 0x22, 0x0050 },
91
92 { 0x25, 0x0050 },
93 { 0x26, 0x0000 },
94 { 0x27, 0x0000 },
95 { 0x28, 0x0000 },
96 { 0x29, 0x0000 },
97 { 0x2a, 0x0040 },
98 { 0x2b, 0x0000 },
99 { 0x2c, 0x0000 },
100 { 0x2d, 0x0050 },
101 { 0x2e, 0x0050 },
102 { 0x2f, 0x0000 },
103 { 0x30, 0x0002 },
104 { 0x31, 0x0037 },
105
106 { 0x33, 0x0080 },
107 { 0x34, 0x0008 },
108 { 0x35, 0x0031 },
109 { 0x36, 0x0026 },
110 { 0x37, 0x00e9 },
f2644a2c
MB		 111};
112
0ebe36c6
MB		 113static bool wm8960_volatile(struct device *dev, unsigned int reg)
114{
115 switch (reg) {
116 case WM8960_RESET:
117 return true;
118 default:
119 return false;
120 }
121}
122
f2644a2c 123struct wm8960_priv {
75aa8868 124 struct clk *mclk;
0ebe36c6 125 struct regmap *regmap;
f0fba2ad
LG		 126 int (*set_bias_level)(struct snd_soc_codec *,
127 enum snd_soc_bias_level level);
913d7b4c
MB		 128 struct snd_soc_dapm_widget *lout1;
129 struct snd_soc_dapm_widget *rout1;
130 struct snd_soc_dapm_widget *out3;
afd6d36a 131 bool deemph;
3176bf2d 132 int lrclk;
0e50b51a
ZW		 133 int bclk;
134 int sysclk;
3176bf2d
ZW		 135 int clk_id;
136 int freq_in;
137 bool is_stream_in_use[2];
e2280c90 138 struct wm8960_data pdata;
f2644a2c
MB		 139};
140
3ad5e861 141#define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0)
f2644a2c
MB		 142
143/* enumerated controls */
f2644a2c
MB		 144static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted",
145 "Right Inverted", "Stereo Inversion"};
146static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"};
147static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"};
148static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"};
149static const char *wm8960_alcmode[] = {"ALC", "Limiter"};
4a5893cf
ZW		 150static const char *wm8960_adc_data_output_sel[] = {
151 "Left Data = Left ADC; Right Data = Right ADC",
152 "Left Data = Left ADC; Right Data = Left ADC",
153 "Left Data = Right ADC; Right Data = Right ADC",
154 "Left Data = Right ADC; Right Data = Left ADC",
155};
defbf708 156static const char *wm8960_dmonomix[] = {"Stereo", "Mono"};
f2644a2c
MB		 157
158static const struct soc_enum wm8960_enum[] = {
f2644a2c
MB		 159 SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity),
160 SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity),
161 SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff),
162 SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff),
163 SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc),
164 SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode),
4a5893cf 165 SOC_ENUM_SINGLE(WM8960_ADDCTL1, 2, 4, wm8960_adc_data_output_sel),
defbf708 166 SOC_ENUM_SINGLE(WM8960_ADDCTL1, 4, 2, wm8960_dmonomix),
f2644a2c
MB		 167};
168
afd6d36a
MB		 169static const int deemph_settings[] = { 0, 32000, 44100, 48000 };
170
171static int wm8960_set_deemph(struct snd_soc_codec *codec)
172{
173 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
174 int val, i, best;
175
176 /* If we're using deemphasis select the nearest available sample
177 * rate.
178 */
179 if (wm8960->deemph) {
180 best = 1;
181 for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) {
3176bf2d
ZW		 182 if (abs(deemph_settings[i] - wm8960->lrclk) <
183 abs(deemph_settings[best] - wm8960->lrclk))
afd6d36a
MB		 184 best = i;
185 }
186
187 val = best << 1;
188 } else {
189 val = 0;
190 }
191
192 dev_dbg(codec->dev, "Set deemphasis %d\n", val);
193
194 return snd_soc_update_bits(codec, WM8960_DACCTL1,
195 0x6, val);
196}
197
198static int wm8960_get_deemph(struct snd_kcontrol *kcontrol,
199 struct snd_ctl_elem_value *ucontrol)
200{
ea53bf77 201 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a
MB		 202 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
203
b4a18c8b 204 ucontrol->value.integer.value[0] = wm8960->deemph;
3f343f85 205 return 0;
afd6d36a
MB		 206}
207
208static int wm8960_put_deemph(struct snd_kcontrol *kcontrol,
209 struct snd_ctl_elem_value *ucontrol)
210{
ea53bf77 211 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
afd6d36a 212 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
c1fe81f2 213 unsigned int deemph = ucontrol->value.integer.value[0];
afd6d36a
MB		 214
215 if (deemph > 1)
216 return -EINVAL;
217
218 wm8960->deemph = deemph;
219
220 return wm8960_set_deemph(codec);
221}
222
3758ff5f 223static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
7e90f9b2 224static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1725, 75, 0);
3758ff5f 225static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
f2644a2c
MB		 226static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0);
227static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
7e90f9b2
ZW		 228static const DECLARE_TLV_DB_SCALE(lineinboost_tlv, -1500, 300, 1);
229static const unsigned int micboost_tlv[] = {
230 TLV_DB_RANGE_HEAD(2),
231 0, 1, TLV_DB_SCALE_ITEM(0, 1300, 0),
232 2, 3, TLV_DB_SCALE_ITEM(2000, 900, 0),
233};
f2644a2c
MB		 234
235static const struct snd_kcontrol_new wm8960_snd_controls[] = {
236SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL,
7e90f9b2 237 0, 63, 0, inpga_tlv),
f2644a2c
MB		 238SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL,
239 6, 1, 0),
240SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL,
41a59cae 241 7, 1, 1),
f2644a2c 242
21eb2693 243SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume",
7e90f9b2 244 WM8960_INBMIX1, 4, 7, 0, lineinboost_tlv),
21eb2693 245SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume",
7e90f9b2 246 WM8960_INBMIX1, 1, 7, 0, lineinboost_tlv),
21eb2693 247SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume",
7e90f9b2 248 WM8960_INBMIX2, 4, 7, 0, lineinboost_tlv),
21eb2693 249SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume",
7e90f9b2
ZW		 250 WM8960_INBMIX2, 1, 7, 0, lineinboost_tlv),
251SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT1 Volume",
8524bb0c 252 WM8960_RINPATH, 4, 3, 0, micboost_tlv),
7e90f9b2 253SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT1 Volume",
8524bb0c 254 WM8960_LINPATH, 4, 3, 0, micboost_tlv),
21eb2693 255
f2644a2c
MB		 256SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC,
257 0, 255, 0, dac_tlv),
258
259SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1,
260 0, 127, 0, out_tlv),
261SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1,
262 7, 1, 0),
263
264SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2,
265 0, 127, 0, out_tlv),
266SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2,
267 7, 1, 0),
268SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0),
269SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0),
270
271SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0),
4faaa8d9 272SOC_ENUM("ADC Polarity", wm8960_enum[0]),
f2644a2c
MB		 273SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0),
274
a077e81e 275SOC_ENUM("DAC Polarity", wm8960_enum[1]),
afd6d36a
MB		 276SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
277 wm8960_get_deemph, wm8960_put_deemph),
f2644a2c 278
4faaa8d9
MB		 279SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]),
280SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]),
f2644a2c
MB		 281SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0),
282SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0),
283
4faaa8d9 284SOC_ENUM("ALC Function", wm8960_enum[4]),
f2644a2c
MB		 285SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0),
286SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1),
287SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0),
288SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0),
4faaa8d9 289SOC_ENUM("ALC Mode", wm8960_enum[5]),
f2644a2c
MB		 290SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0),
291SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0),
292
293SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0),
294SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0),
295
c324aac0
MH		 296SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC,
297 0, 255, 0, adc_tlv),
f2644a2c
MB		 298
299SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume",
300 WM8960_BYPASS1, 4, 7, 1, bypass_tlv),
301SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume",
302 WM8960_LOUTMIX, 4, 7, 1, bypass_tlv),
303SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume",
304 WM8960_BYPASS2, 4, 7, 1, bypass_tlv),
305SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume",
306 WM8960_ROUTMIX, 4, 7, 1, bypass_tlv),
4a5893cf
ZW		 307
308SOC_ENUM("ADC Data Output Select", wm8960_enum[6]),
defbf708 309SOC_ENUM("DAC Mono Mix", wm8960_enum[7]),
f2644a2c
MB		 310};
311
312static const struct snd_kcontrol_new wm8960_lin_boost[] = {
313SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0),
314SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0),
315SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0),
316};
317
318static const struct snd_kcontrol_new wm8960_lin[] = {
319SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0),
320};
321
322static const struct snd_kcontrol_new wm8960_rin_boost[] = {
323SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0),
324SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0),
325SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0),
326};
327
328static const struct snd_kcontrol_new wm8960_rin[] = {
329SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0),
330};
331
332static const struct snd_kcontrol_new wm8960_loutput_mixer[] = {
333SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0),
334SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0),
335SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0),
336};
337
338static const struct snd_kcontrol_new wm8960_routput_mixer[] = {
339SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0),
340SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0),
341SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0),
342};
343
344static const struct snd_kcontrol_new wm8960_mono_out[] = {
345SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0),
346SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0),
347};
348
349static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = {
350SND_SOC_DAPM_INPUT("LINPUT1"),
351SND_SOC_DAPM_INPUT("RINPUT1"),
352SND_SOC_DAPM_INPUT("LINPUT2"),
353SND_SOC_DAPM_INPUT("RINPUT2"),
354SND_SOC_DAPM_INPUT("LINPUT3"),
355SND_SOC_DAPM_INPUT("RINPUT3"),
356
187774cb 357SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0),
f2644a2c
MB		 358
359SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0,
360 wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)),
361SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0,
362 wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)),
363
364SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0,
365 wm8960_lin, ARRAY_SIZE(wm8960_lin)),
366SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0,
367 wm8960_rin, ARRAY_SIZE(wm8960_rin)),
368
44426de4
MB		 369SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0),
370SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0),
f2644a2c
MB		 371
372SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0),
373SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0),
374
375SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0,
376 &wm8960_loutput_mixer[0],
377 ARRAY_SIZE(wm8960_loutput_mixer)),
378SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0,
379 &wm8960_routput_mixer[0],
380 ARRAY_SIZE(wm8960_routput_mixer)),
381
f2644a2c
MB		 382SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0),
383SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0),
384
385SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0),
386SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0),
387
388SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0),
389SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0),
390
391SND_SOC_DAPM_OUTPUT("SPK_LP"),
392SND_SOC_DAPM_OUTPUT("SPK_LN"),
393SND_SOC_DAPM_OUTPUT("HP_L"),
394SND_SOC_DAPM_OUTPUT("HP_R"),
395SND_SOC_DAPM_OUTPUT("SPK_RP"),
396SND_SOC_DAPM_OUTPUT("SPK_RN"),
397SND_SOC_DAPM_OUTPUT("OUT3"),
398};
399
913d7b4c
MB		 400static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = {
401SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0,
402 &wm8960_mono_out[0],
403 ARRAY_SIZE(wm8960_mono_out)),
404};
405
406/* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */
407static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = {
408SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0),
409};
410
f2644a2c
MB		 411static const struct snd_soc_dapm_route audio_paths[] = {
412 { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" },
413 { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" },
414 { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" },
415
2d4a3260
ZW		 416 { "Left Input Mixer", "Boost Switch", "Left Boost Mixer" },
417 { "Left Input Mixer", "Boost Switch", "LINPUT1" }, /* Really Boost Switch */
f2644a2c
MB		 418 { "Left Input Mixer", NULL, "LINPUT2" },
419 { "Left Input Mixer", NULL, "LINPUT3" },
420
421 { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" },
422 { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" },
423 { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" },
424
2d4a3260
ZW		 425 { "Right Input Mixer", "Boost Switch", "Right Boost Mixer" },
426 { "Right Input Mixer", "Boost Switch", "RINPUT1" }, /* Really Boost Switch */
f2644a2c 427 { "Right Input Mixer", NULL, "RINPUT2" },
85e36a1f 428 { "Right Input Mixer", NULL, "RINPUT3" },
f2644a2c
MB		 429
430 { "Left ADC", NULL, "Left Input Mixer" },
431 { "Right ADC", NULL, "Right Input Mixer" },
432
433 { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" },
2d4a3260 434 { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer" },
f2644a2c
MB		 435 { "Left Output Mixer", "PCM Playback Switch", "Left DAC" },
436
437 { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" },
2d4a3260 438 { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" },
f2644a2c
MB		 439 { "Right Output Mixer", "PCM Playback Switch", "Right DAC" },
440
f2644a2c
MB		 441 { "LOUT1 PGA", NULL, "Left Output Mixer" },
442 { "ROUT1 PGA", NULL, "Right Output Mixer" },
443
444 { "HP_L", NULL, "LOUT1 PGA" },
445 { "HP_R", NULL, "ROUT1 PGA" },
446
447 { "Left Speaker PGA", NULL, "Left Output Mixer" },
448 { "Right Speaker PGA", NULL, "Right Output Mixer" },
449
450 { "Left Speaker Output", NULL, "Left Speaker PGA" },
451 { "Right Speaker Output", NULL, "Right Speaker PGA" },
452
453 { "SPK_LN", NULL, "Left Speaker Output" },
454 { "SPK_LP", NULL, "Left Speaker Output" },
455 { "SPK_RN", NULL, "Right Speaker Output" },
456 { "SPK_RP", NULL, "Right Speaker Output" },
913d7b4c
MB		 457};
458
459static const struct snd_soc_dapm_route audio_paths_out3[] = {
460 { "Mono Output Mixer", "Left Switch", "Left Output Mixer" },
461 { "Mono Output Mixer", "Right Switch", "Right Output Mixer" },
f2644a2c
MB		 462
463 { "OUT3", NULL, "Mono Output Mixer", }
464};
465
913d7b4c
MB		 466static const struct snd_soc_dapm_route audio_paths_capless[] = {
467 { "HP_L", NULL, "OUT3 VMID" },
468 { "HP_R", NULL, "OUT3 VMID" },
469
470 { "OUT3 VMID", NULL, "Left Output Mixer" },
471 { "OUT3 VMID", NULL, "Right Output Mixer" },
472};
473
f2644a2c
MB		 474static int wm8960_add_widgets(struct snd_soc_codec *codec)
475{
b2c812e2 476 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 477 struct wm8960_data *pdata = &wm8960->pdata;
93f32f53 478 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
913d7b4c
MB		 479 struct snd_soc_dapm_widget *w;
480
ce6120cc 481 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets,
f2644a2c
MB		 482 ARRAY_SIZE(wm8960_dapm_widgets));
483
ce6120cc 484 snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths));
f2644a2c 485
913d7b4c
MB		 486 /* In capless mode OUT3 is used to provide VMID for the
487 * headphone outputs, otherwise it is used as a mono mixer.
488 */
489 if (pdata && pdata->capless) {
ce6120cc 490 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless,
913d7b4c
MB		 491 ARRAY_SIZE(wm8960_dapm_widgets_capless));
492
ce6120cc 493 snd_soc_dapm_add_routes(dapm, audio_paths_capless,
913d7b4c
MB		 494 ARRAY_SIZE(audio_paths_capless));
495 } else {
ce6120cc 496 snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3,
913d7b4c
MB		 497 ARRAY_SIZE(wm8960_dapm_widgets_out3));
498
ce6120cc 499 snd_soc_dapm_add_routes(dapm, audio_paths_out3,
913d7b4c
MB		 500 ARRAY_SIZE(audio_paths_out3));
501 }
502
503 /* We need to power up the headphone output stage out of
504 * sequence for capless mode. To save scanning the widget
505 * list each time to find the desired power state do so now
506 * and save the result.
507 */
00200107 508 list_for_each_entry(w, &codec->component.card->widgets, list) {
93f32f53 509 if (w->dapm != dapm)
97c866de 510 continue;
913d7b4c
MB		 511 if (strcmp(w->name, "LOUT1 PGA") == 0)
512 wm8960->lout1 = w;
513 if (strcmp(w->name, "ROUT1 PGA") == 0)
514 wm8960->rout1 = w;
515 if (strcmp(w->name, "OUT3 VMID") == 0)
516 wm8960->out3 = w;
517 }
518
f2644a2c
MB		 519 return 0;
520}
521
522static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai,
523 unsigned int fmt)
524{
525 struct snd_soc_codec *codec = codec_dai->codec;
526 u16 iface = 0;
527
528 /* set master/slave audio interface */
529 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
530 case SND_SOC_DAIFMT_CBM_CFM:
531 iface |= 0x0040;
532 break;
533 case SND_SOC_DAIFMT_CBS_CFS:
534 break;
535 default:
536 return -EINVAL;
537 }
538
539 /* interface format */
540 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
541 case SND_SOC_DAIFMT_I2S:
542 iface |= 0x0002;
543 break;
544 case SND_SOC_DAIFMT_RIGHT_J:
545 break;
546 case SND_SOC_DAIFMT_LEFT_J:
547 iface |= 0x0001;
548 break;
549 case SND_SOC_DAIFMT_DSP_A:
550 iface |= 0x0003;
551 break;
552 case SND_SOC_DAIFMT_DSP_B:
553 iface |= 0x0013;
554 break;
555 default:
556 return -EINVAL;
557 }
558
559 /* clock inversion */
560 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
561 case SND_SOC_DAIFMT_NB_NF:
562 break;
563 case SND_SOC_DAIFMT_IB_IF:
564 iface |= 0x0090;
565 break;
566 case SND_SOC_DAIFMT_IB_NF:
567 iface |= 0x0080;
568 break;
569 case SND_SOC_DAIFMT_NB_IF:
570 iface |= 0x0010;
571 break;
572 default:
573 return -EINVAL;
574 }
575
576 /* set iface */
17a52fd6 577 snd_soc_write(codec, WM8960_IFACE1, iface);
f2644a2c
MB		 578 return 0;
579}
580
db059c0f
MB		 581static struct {
582 int rate;
583 unsigned int val;
584} alc_rates[] = {
585 { 48000, 0 },
586 { 44100, 0 },
587 { 32000, 1 },
588 { 22050, 2 },
589 { 24000, 2 },
590 { 16000, 3 },
22ee76da 591 { 11025, 4 },
db059c0f
MB		 592 { 12000, 4 },
593 { 8000, 5 },
594};
595
3176bf2d
ZW		 596/* -1 for reserved value */
597static const int sysclk_divs[] = { 1, -1, 2, -1 };
598
0e50b51a
ZW		 599/* Multiply 256 for internal 256 div */
600static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 };
601
602/* Multiply 10 to eliminate decimials */
603static const int bclk_divs[] = {
604 10, 15, 20, 30, 40, 55, 60, 80, 110,
605 120, 160, 220, 240, 320, 320, 320
606};
607
3176bf2d 608static int wm8960_configure_clocking(struct snd_soc_codec *codec)
0e50b51a
ZW		 609{
610 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 611 int sysclk, bclk, lrclk, freq_out, freq_in;
0e50b51a 612 u16 iface1 = snd_soc_read(codec, WM8960_IFACE1);
3176bf2d 613 int i, j, k;
0e50b51a
ZW		 614
615 if (!(iface1 & (1<<6))) {
616 dev_dbg(codec->dev,
617 "Codec is slave mode, no need to configure clock\n");
3176bf2d
ZW		 618 return 0;
619 }
620
621 if (wm8960->clk_id != WM8960_SYSCLK_MCLK && !wm8960->freq_in) {
622 dev_err(codec->dev, "No MCLK configured\n");
623 return -EINVAL;
0e50b51a
ZW		 624 }
625
3176bf2d
ZW		 626 freq_in = wm8960->freq_in;
627 bclk = wm8960->bclk;
628 lrclk = wm8960->lrclk;
629 /*
630 * If it's sysclk auto mode, check if the MCLK can provide sysclk or
631 * not. If MCLK can provide sysclk, using MCLK to provide sysclk
632 * directly. Otherwise, auto select a available pll out frequency
633 * and set PLL.
634 */
635 if (wm8960->clk_id == WM8960_SYSCLK_AUTO) {
636 /* disable the PLL and using MCLK to provide sysclk */
637 wm8960_set_pll(codec, 0, 0);
638 freq_out = freq_in;
639 } else if (wm8960->sysclk) {
640 freq_out = wm8960->sysclk;
641 } else {
642 dev_err(codec->dev, "No SYSCLK configured\n");
643 return -EINVAL;
0e50b51a
ZW		 644 }
645
3176bf2d
ZW		 646 /* check if the sysclk frequency is available. */
647 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
648 if (sysclk_divs[i] == -1)
649 continue;
650 sysclk = freq_out / sysclk_divs[i];
651 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
652 if (sysclk == dac_divs[j] * lrclk) {
653 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k)
654 if (sysclk == bclk * bclk_divs[k] / 10)
655 break;
656 if (k != ARRAY_SIZE(bclk_divs))
657 break;
658 }
659 }
660 if (j != ARRAY_SIZE(dac_divs))
661 break;
0e50b51a
ZW		 662 }
663
3176bf2d
ZW		 664 if (i != ARRAY_SIZE(sysclk_divs)) {
665 goto configure_clock;
666 } else if (wm8960->clk_id != WM8960_SYSCLK_AUTO) {
667 dev_err(codec->dev, "failed to configure clock\n");
668 return -EINVAL;
669 }
670 /* get a available pll out frequency and set pll */
671 for (i = 0; i < ARRAY_SIZE(sysclk_divs); ++i) {
672 if (sysclk_divs[i] == -1)
673 continue;
674 for (j = 0; j < ARRAY_SIZE(dac_divs); ++j) {
675 sysclk = lrclk * dac_divs[j];
676 freq_out = sysclk * sysclk_divs[i];
677
678 for (k = 0; k < ARRAY_SIZE(bclk_divs); ++k) {
679 if (sysclk == bclk * bclk_divs[k] / 10 &&
680 is_pll_freq_available(freq_in, freq_out)) {
681 wm8960_set_pll(codec,
682 freq_in, freq_out);
0e50b51a 683 break;
3176bf2d
ZW		 684 } else {
685 continue;
686 }
0e50b51a 687 }
3176bf2d 688 if (k != ARRAY_SIZE(bclk_divs))
0e50b51a
ZW		 689 break;
690 }
3176bf2d
ZW		 691 if (j != ARRAY_SIZE(dac_divs))
692 break;
0e50b51a
ZW		 693 }
694
3176bf2d
ZW		 695 if (i == ARRAY_SIZE(sysclk_divs)) {
696 dev_err(codec->dev, "failed to configure clock\n");
697 return -EINVAL;
0e50b51a
ZW		 698 }
699
3176bf2d
ZW		 700configure_clock:
701 /* configure sysclk clock */
702 snd_soc_update_bits(codec, WM8960_CLOCK1, 3 << 1, i << 1);
703
704 /* configure frame clock */
705 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, j << 3);
706 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, j << 6);
0e50b51a
ZW		 707
708 /* configure bit clock */
3176bf2d
ZW		 709 snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, k);
710
711 return 0;
0e50b51a
ZW		 712}
713
f2644a2c
MB		 714static int wm8960_hw_params(struct snd_pcm_substream *substream,
715 struct snd_pcm_hw_params *params,
716 struct snd_soc_dai *dai)
717{
e6968a17 718 struct snd_soc_codec *codec = dai->codec;
afd6d36a 719 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
17a52fd6 720 u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3;
0e50b51a 721 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
db059c0f 722 int i;
f2644a2c 723
0e50b51a
ZW		 724 wm8960->bclk = snd_soc_params_to_bclk(params);
725 if (params_channels(params) == 1)
726 wm8960->bclk *= 2;
727
f2644a2c 728 /* bit size */
39e9cc46
MB		 729 switch (params_width(params)) {
730 case 16:
f2644a2c 731 break;
39e9cc46 732 case 20:
f2644a2c
MB		 733 iface |= 0x0004;
734 break;
39e9cc46 735 case 24:
f2644a2c
MB		 736 iface |= 0x0008;
737 break;
7a8c7867
ZW		 738 case 32:
739 /* right justify mode does not support 32 word length */
740 if ((iface & 0x3) != 0) {
741 iface |= 0x000c;
742 break;
743 }
4c2474c0 744 default:
39e9cc46
MB		 745 dev_err(codec->dev, "unsupported width %d\n",
746 params_width(params));
4c2474c0 747 return -EINVAL;
f2644a2c
MB		 748 }
749
3176bf2d 750 wm8960->lrclk = params_rate(params);
afd6d36a 751 /* Update filters for the new rate */
3176bf2d 752 if (tx) {
afd6d36a 753 wm8960_set_deemph(codec);
db059c0f
MB		 754 } else {
755 for (i = 0; i < ARRAY_SIZE(alc_rates); i++)
756 if (alc_rates[i].rate == params_rate(params))
757 snd_soc_update_bits(codec,
758 WM8960_ADDCTL3, 0x7,
759 alc_rates[i].val);
afd6d36a
MB		 760 }
761
f2644a2c 762 /* set iface */
17a52fd6 763 snd_soc_write(codec, WM8960_IFACE1, iface);
0e50b51a 764
3176bf2d
ZW		 765 wm8960->is_stream_in_use[tx] = true;
766
767 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON &&
768 !wm8960->is_stream_in_use[!tx])
769 return wm8960_configure_clocking(codec);
770
771 return 0;
772}
773
774static int wm8960_hw_free(struct snd_pcm_substream *substream,
775 struct snd_soc_dai *dai)
776{
777 struct snd_soc_codec *codec = dai->codec;
778 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
779 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
780
781 wm8960->is_stream_in_use[tx] = false;
0e50b51a 782
f2644a2c
MB		 783 return 0;
784}
785
786static int wm8960_mute(struct snd_soc_dai *dai, int mute)
787{
788 struct snd_soc_codec *codec = dai->codec;
f2644a2c
MB		 789
790 if (mute)
16b24881 791 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8);
f2644a2c 792 else
16b24881 793 snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0);
f2644a2c
MB		 794 return 0;
795}
796
913d7b4c
MB		 797static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec,
798 enum snd_soc_bias_level level)
f2644a2c 799{
0ebe36c6 800 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 801 u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
75aa8868 802 int ret;
0ebe36c6 803
f2644a2c
MB		 804 switch (level) {
805 case SND_SOC_BIAS_ON:
806 break;
807
808 case SND_SOC_BIAS_PREPARE:
93f32f53 809 switch (snd_soc_codec_get_bias_level(codec)) {
75aa8868
ZW		 810 case SND_SOC_BIAS_STANDBY:
811 if (!IS_ERR(wm8960->mclk)) {
812 ret = clk_prepare_enable(wm8960->mclk);
813 if (ret) {
814 dev_err(codec->dev,
815 "Failed to enable MCLK: %d\n",
816 ret);
817 return ret;
818 }
819 }
820
3176bf2d
ZW		 821 ret = wm8960_configure_clocking(codec);
822 if (ret)
823 return ret;
824
75aa8868
ZW		 825 /* Set VMID to 2x50k */
826 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80);
827 break;
828
829 case SND_SOC_BIAS_ON:
3176bf2d
ZW		 830 /*
831 * If it's sysclk auto mode, and the pll is enabled,
832 * disable the pll
833 */
834 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
835 wm8960_set_pll(codec, 0, 0);
836
75aa8868
ZW		 837 if (!IS_ERR(wm8960->mclk))
838 clk_disable_unprepare(wm8960->mclk);
839 break;
840
841 default:
842 break;
843 }
844
f2644a2c
MB		 845 break;
846
847 case SND_SOC_BIAS_STANDBY:
93f32f53 848 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
0ebe36c6 849 regcache_sync(wm8960->regmap);
bc45df2d 850
f2644a2c 851 /* Enable anti-pop features */
17a52fd6 852 snd_soc_write(codec, WM8960_APOP1,
913d7b4c
MB		 853 WM8960_POBCTRL | WM8960_SOFT_ST |
854 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
f2644a2c
MB		 855
856 /* Enable & ramp VMID at 2x50k */
16b24881 857 snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80);
f2644a2c
MB		 858 msleep(100);
859
860 /* Enable VREF */
16b24881
AL		 861 snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF,
862 WM8960_VREF);
f2644a2c
MB		 863
864 /* Disable anti-pop features */
17a52fd6 865 snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN);
f2644a2c
MB		 866 }
867
868 /* Set VMID to 2x250k */
16b24881 869 snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100);
f2644a2c
MB		 870 break;
871
872 case SND_SOC_BIAS_OFF:
873 /* Enable anti-pop features */
17a52fd6 874 snd_soc_write(codec, WM8960_APOP1,
f2644a2c
MB		 875 WM8960_POBCTRL | WM8960_SOFT_ST |
876 WM8960_BUFDCOPEN | WM8960_BUFIOEN);
877
878 /* Disable VMID and VREF, let them discharge */
17a52fd6 879 snd_soc_write(codec, WM8960_POWER1, 0);
f2644a2c 880 msleep(600);
913d7b4c
MB		 881 break;
882 }
883
913d7b4c
MB		 884 return 0;
885}
886
887static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec,
888 enum snd_soc_bias_level level)
889{
b2c812e2 890 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
3176bf2d 891 u16 pm2 = snd_soc_read(codec, WM8960_POWER2);
75aa8868 892 int reg, ret;
913d7b4c
MB		 893
894 switch (level) {
895 case SND_SOC_BIAS_ON:
896 break;
897
898 case SND_SOC_BIAS_PREPARE:
93f32f53 899 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 900 case SND_SOC_BIAS_STANDBY:
901 /* Enable anti pop mode */
902 snd_soc_update_bits(codec, WM8960_APOP1,
903 WM8960_POBCTRL | WM8960_SOFT_ST |
904 WM8960_BUFDCOPEN,
905 WM8960_POBCTRL | WM8960_SOFT_ST |
906 WM8960_BUFDCOPEN);
907
908 /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */
909 reg = 0;
910 if (wm8960->lout1 && wm8960->lout1->power)
911 reg |= WM8960_PWR2_LOUT1;
912 if (wm8960->rout1 && wm8960->rout1->power)
913 reg |= WM8960_PWR2_ROUT1;
914 if (wm8960->out3 && wm8960->out3->power)
915 reg |= WM8960_PWR2_OUT3;
916 snd_soc_update_bits(codec, WM8960_POWER2,
917 WM8960_PWR2_LOUT1 |
918 WM8960_PWR2_ROUT1 |
919 WM8960_PWR2_OUT3, reg);
920
921 /* Enable VMID at 2*50k */
922 snd_soc_update_bits(codec, WM8960_POWER1,
923 WM8960_VMID_MASK, 0x80);
924
925 /* Ramp */
926 msleep(100);
927
928 /* Enable VREF */
929 snd_soc_update_bits(codec, WM8960_POWER1,
930 WM8960_VREF, WM8960_VREF);
931
932 msleep(100);
75aa8868
ZW		 933
934 if (!IS_ERR(wm8960->mclk)) {
935 ret = clk_prepare_enable(wm8960->mclk);
936 if (ret) {
937 dev_err(codec->dev,
938 "Failed to enable MCLK: %d\n",
939 ret);
940 return ret;
941 }
942 }
3176bf2d
ZW		 943
944 ret = wm8960_configure_clocking(codec);
945 if (ret)
946 return ret;
947
913d7b4c
MB		 948 break;
949
950 case SND_SOC_BIAS_ON:
3176bf2d
ZW		 951 /*
952 * If it's sysclk auto mode, and the pll is enabled,
953 * disable the pll
954 */
955 if (wm8960->clk_id == WM8960_SYSCLK_AUTO && (pm2 & 0x1))
956 wm8960_set_pll(codec, 0, 0);
957
75aa8868
ZW		 958 if (!IS_ERR(wm8960->mclk))
959 clk_disable_unprepare(wm8960->mclk);
960
913d7b4c
MB		 961 /* Enable anti-pop mode */
962 snd_soc_update_bits(codec, WM8960_APOP1,
963 WM8960_POBCTRL | WM8960_SOFT_ST |
964 WM8960_BUFDCOPEN,
965 WM8960_POBCTRL | WM8960_SOFT_ST |
966 WM8960_BUFDCOPEN);
967
968 /* Disable VMID and VREF */
969 snd_soc_update_bits(codec, WM8960_POWER1,
970 WM8960_VREF | WM8960_VMID_MASK, 0);
971 break;
972
bc45df2d 973 case SND_SOC_BIAS_OFF:
0ebe36c6 974 regcache_sync(wm8960->regmap);
bc45df2d 975 break;
913d7b4c
MB		 976 default:
977 break;
978 }
979 break;
f2644a2c 980
913d7b4c 981 case SND_SOC_BIAS_STANDBY:
93f32f53 982 switch (snd_soc_codec_get_bias_level(codec)) {
913d7b4c
MB		 983 case SND_SOC_BIAS_PREPARE:
984 /* Disable HP discharge */
985 snd_soc_update_bits(codec, WM8960_APOP2,
986 WM8960_DISOP | WM8960_DRES_MASK,
987 0);
988
989 /* Disable anti-pop features */
990 snd_soc_update_bits(codec, WM8960_APOP1,
991 WM8960_POBCTRL | WM8960_SOFT_ST |
992 WM8960_BUFDCOPEN,
993 WM8960_POBCTRL | WM8960_SOFT_ST |
994 WM8960_BUFDCOPEN);
995 break;
996
997 default:
998 break;
999 }
1000 break;
f2644a2c 1001
913d7b4c 1002 case SND_SOC_BIAS_OFF:
f2644a2c
MB		 1003 break;
1004 }
1005
f2644a2c
MB		 1006 return 0;
1007}
1008
1009/* PLL divisors */
1010struct _pll_div {
1011 u32 pre_div:1;
1012 u32 n:4;
1013 u32 k:24;
1014};
1015
3176bf2d
ZW		 1016static bool is_pll_freq_available(unsigned int source, unsigned int target)
1017{
1018 unsigned int Ndiv;
1019
1020 if (source == 0 || target == 0)
1021 return false;
1022
1023 /* Scale up target to PLL operating frequency */
1024 target *= 4;
1025 Ndiv = target / source;
1026
1027 if (Ndiv < 6) {
1028 source >>= 1;
1029 Ndiv = target / source;
1030 }
1031
1032 if ((Ndiv < 6) || (Ndiv > 12))
1033 return false;
1034
1035 return true;
1036}
1037
f2644a2c
MB		 1038/* The size in bits of the pll divide multiplied by 10
1039 * to allow rounding later */
1040#define FIXED_PLL_SIZE ((1 << 24) * 10)
1041
1042static int pll_factors(unsigned int source, unsigned int target,
1043 struct _pll_div *pll_div)
1044{
1045 unsigned long long Kpart;
1046 unsigned int K, Ndiv, Nmod;
1047
1048 pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target);
1049
1050 /* Scale up target to PLL operating frequency */
1051 target *= 4;
1052
1053 Ndiv = target / source;
1054 if (Ndiv < 6) {
1055 source >>= 1;
1056 pll_div->pre_div = 1;
1057 Ndiv = target / source;
1058 } else
1059 pll_div->pre_div = 0;
1060
1061 if ((Ndiv < 6) || (Ndiv > 12)) {
1062 pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv);
1063 return -EINVAL;
1064 }
1065
1066 pll_div->n = Ndiv;
1067 Nmod = target % source;
1068 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
1069
1070 do_div(Kpart, source);
1071
1072 K = Kpart & 0xFFFFFFFF;
1073
1074 /* Check if we need to round */
1075 if ((K % 10) >= 5)
1076 K += 5;
1077
1078 /* Move down to proper range now rounding is done */
1079 K /= 10;
1080
1081 pll_div->k = K;
1082
1083 pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n",
1084 pll_div->n, pll_div->k, pll_div->pre_div);
1085
1086 return 0;
1087}
1088
3176bf2d
ZW		 1089static int wm8960_set_pll(struct snd_soc_codec *codec,
1090 unsigned int freq_in, unsigned int freq_out)
f2644a2c 1091{
f2644a2c
MB		 1092 u16 reg;
1093 static struct _pll_div pll_div;
1094 int ret;
1095
1096 if (freq_in && freq_out) {
1097 ret = pll_factors(freq_in, freq_out, &pll_div);
1098 if (ret != 0)
1099 return ret;
1100 }
1101
1102 /* Disable the PLL: even if we are changing the frequency the
1103 * PLL needs to be disabled while we do so. */
16b24881
AL		 1104 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0);
1105 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0);
f2644a2c
MB		 1106
1107 if (!freq_in || !freq_out)
1108 return 0;
1109
17a52fd6 1110 reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f;
f2644a2c
MB		 1111 reg |= pll_div.pre_div << 4;
1112 reg |= pll_div.n;
1113
1114 if (pll_div.k) {
1115 reg |= 0x20;
1116
85fa532b
MD		 1117 snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff);
1118 snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff);
1119 snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff);
f2644a2c 1120 }
17a52fd6 1121 snd_soc_write(codec, WM8960_PLL1, reg);
f2644a2c
MB		 1122
1123 /* Turn it on */
16b24881 1124 snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1);
f2644a2c 1125 msleep(250);
16b24881 1126 snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1);
f2644a2c
MB		 1127
1128 return 0;
1129}
1130
3176bf2d
ZW		 1131static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1132 int source, unsigned int freq_in, unsigned int freq_out)
1133{
1134 struct snd_soc_codec *codec = codec_dai->codec;
1135 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1136
1137 wm8960->freq_in = freq_in;
1138
1139 if (pll_id == WM8960_SYSCLK_AUTO)
1140 return 0;
1141
1142 return wm8960_set_pll(codec, freq_in, freq_out);
1143}
1144
f2644a2c
MB		 1145static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1146 int div_id, int div)
1147{
1148 struct snd_soc_codec *codec = codec_dai->codec;
1149 u16 reg;
1150
1151 switch (div_id) {
f2644a2c 1152 case WM8960_SYSCLKDIV:
17a52fd6
MB		 1153 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9;
1154 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1155 break;
1156 case WM8960_DACDIV:
17a52fd6
MB		 1157 reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7;
1158 snd_soc_write(codec, WM8960_CLOCK1, reg | div);
f2644a2c
MB		 1159 break;
1160 case WM8960_OPCLKDIV:
17a52fd6
MB		 1161 reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f;
1162 snd_soc_write(codec, WM8960_PLL1, reg | div);
f2644a2c
MB		 1163 break;
1164 case WM8960_DCLKDIV:
17a52fd6
MB		 1165 reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f;
1166 snd_soc_write(codec, WM8960_CLOCK2, reg | div);
f2644a2c
MB		 1167 break;
1168 case WM8960_TOCLKSEL:
17a52fd6
MB		 1169 reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd;
1170 snd_soc_write(codec, WM8960_ADDCTL1, reg | div);
f2644a2c
MB		 1171 break;
1172 default:
1173 return -EINVAL;
1174 }
1175
1176 return 0;
1177}
1178
f0fba2ad
LG		 1179static int wm8960_set_bias_level(struct snd_soc_codec *codec,
1180 enum snd_soc_bias_level level)
1181{
1182 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1183
1184 return wm8960->set_bias_level(codec, level);
1185}
1186
0e50b51a
ZW		 1187static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1188 unsigned int freq, int dir)
1189{
1190 struct snd_soc_codec *codec = dai->codec;
1191 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
1192
1193 switch (clk_id) {
1194 case WM8960_SYSCLK_MCLK:
1195 snd_soc_update_bits(codec, WM8960_CLOCK1,
1196 0x1, WM8960_SYSCLK_MCLK);
1197 break;
1198 case WM8960_SYSCLK_PLL:
1199 snd_soc_update_bits(codec, WM8960_CLOCK1,
1200 0x1, WM8960_SYSCLK_PLL);
1201 break;
3176bf2d
ZW		 1202 case WM8960_SYSCLK_AUTO:
1203 break;
0e50b51a
ZW		 1204 default:
1205 return -EINVAL;
1206 }
1207
1208 wm8960->sysclk = freq;
3176bf2d 1209 wm8960->clk_id = clk_id;
0e50b51a
ZW		 1210
1211 return 0;
1212}
1213
f2644a2c
MB		 1214#define WM8960_RATES SNDRV_PCM_RATE_8000_48000
1215
1216#define WM8960_FORMATS \
1217 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
7a8c7867 1218 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
f2644a2c 1219
85e7652d 1220static const struct snd_soc_dai_ops wm8960_dai_ops = {
f2644a2c 1221 .hw_params = wm8960_hw_params,
3176bf2d 1222 .hw_free = wm8960_hw_free,
f2644a2c
MB		 1223 .digital_mute = wm8960_mute,
1224 .set_fmt = wm8960_set_dai_fmt,
1225 .set_clkdiv = wm8960_set_dai_clkdiv,
1226 .set_pll = wm8960_set_dai_pll,
0e50b51a 1227 .set_sysclk = wm8960_set_dai_sysclk,
f2644a2c
MB		 1228};
1229
f0fba2ad
LG		 1230static struct snd_soc_dai_driver wm8960_dai = {
1231 .name = "wm8960-hifi",
f2644a2c
MB		 1232 .playback = {
1233 .stream_name = "Playback",
1234 .channels_min = 1,
1235 .channels_max = 2,
1236 .rates = WM8960_RATES,
1237 .formats = WM8960_FORMATS,},
1238 .capture = {
1239 .stream_name = "Capture",
1240 .channels_min = 1,
1241 .channels_max = 2,
1242 .rates = WM8960_RATES,
1243 .formats = WM8960_FORMATS,},
1244 .ops = &wm8960_dai_ops,
1245 .symmetric_rates = 1,
1246};
f2644a2c 1247
f0fba2ad 1248static int wm8960_probe(struct snd_soc_codec *codec)
f2644a2c 1249{
f0fba2ad 1250 struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec);
e2280c90 1251 struct wm8960_data *pdata = &wm8960->pdata;
f2644a2c 1252
e2280c90
ZW		 1253 if (pdata->capless)
1254 wm8960->set_bias_level = wm8960_set_bias_level_capless;
1255 else
1256 wm8960->set_bias_level = wm8960_set_bias_level_out3;
f2644a2c 1257
022658be 1258 snd_soc_add_codec_controls(codec, wm8960_snd_controls,
f0fba2ad
LG		 1259 ARRAY_SIZE(wm8960_snd_controls));
1260 wm8960_add_widgets(codec);
f2644a2c
MB		 1261
1262 return 0;
1263}
1264
f0fba2ad
LG		 1265static struct snd_soc_codec_driver soc_codec_dev_wm8960 = {
1266 .probe = wm8960_probe,
f0fba2ad 1267 .set_bias_level = wm8960_set_bias_level,
0a87a6e1 1268 .suspend_bias_off = true,
0ebe36c6
MB		 1269};
1270
1271static const struct regmap_config wm8960_regmap = {
1272 .reg_bits = 7,
1273 .val_bits = 9,
1274 .max_register = WM8960_PLL4,
1275
1276 .reg_defaults = wm8960_reg_defaults,
1277 .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults),
1278 .cache_type = REGCACHE_RBTREE,
1279
1280 .volatile_reg = wm8960_volatile,
f0fba2ad
LG		 1281};
1282
e2280c90
ZW		 1283static void wm8960_set_pdata_from_of(struct i2c_client *i2c,
1284 struct wm8960_data *pdata)
1285{
1286 const struct device_node *np = i2c->dev.of_node;
1287
1288 if (of_property_read_bool(np, "wlf,capless"))
1289 pdata->capless = true;
1290
1291 if (of_property_read_bool(np, "wlf,shared-lrclk"))
1292 pdata->shared_lrclk = true;
1293}
1294
7a79e94e
BP		 1295static int wm8960_i2c_probe(struct i2c_client *i2c,
1296 const struct i2c_device_id *id)
f2644a2c 1297{
37061631 1298 struct wm8960_data *pdata = dev_get_platdata(&i2c->dev);
f2644a2c 1299 struct wm8960_priv *wm8960;
f0fba2ad 1300 int ret;
f2644a2c 1301
b9791c01
MB		 1302 wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv),
1303 GFP_KERNEL);
f2644a2c
MB		 1304 if (wm8960 == NULL)
1305 return -ENOMEM;
1306
75aa8868
ZW		 1307 wm8960->mclk = devm_clk_get(&i2c->dev, "mclk");
1308 if (IS_ERR(wm8960->mclk)) {
1309 if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER)
1310 return -EPROBE_DEFER;
1311 }
1312
c5e6f5fa 1313 wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap);
0ebe36c6
MB		 1314 if (IS_ERR(wm8960->regmap))
1315 return PTR_ERR(wm8960->regmap);
1316
e2280c90
ZW		 1317 if (pdata)
1318 memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data));
1319 else if (i2c->dev.of_node)
1320 wm8960_set_pdata_from_of(i2c, &wm8960->pdata);
1321
3ad5e861
ZW		 1322 ret = wm8960_reset(wm8960->regmap);
1323 if (ret != 0) {
1324 dev_err(&i2c->dev, "Failed to issue reset\n");
1325 return ret;
1326 }
1327
1328 if (wm8960->pdata.shared_lrclk) {
37061631
MB		 1329 ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2,
1330 0x4, 0x4);
1331 if (ret != 0) {
1332 dev_err(&i2c->dev, "Failed to enable LRCM: %d\n",
1333 ret);
1334 return ret;
1335 }
1336 }
1337
3ad5e861
ZW		 1338 /* Latch the update bits */
1339 regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100);
1340 regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100);
1341 regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100);
1342 regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100);
1343 regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100);
1344 regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100);
1345 regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100);
1346 regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100);
1347 regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100);
1348 regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100);
1349
f2644a2c 1350 i2c_set_clientdata(i2c, wm8960);
f2644a2c 1351
f0fba2ad
LG		 1352 ret = snd_soc_register_codec(&i2c->dev,
1353 &soc_codec_dev_wm8960, &wm8960_dai, 1);
b9791c01 1354
f0fba2ad 1355 return ret;
f2644a2c
MB		 1356}
1357
7a79e94e 1358static int wm8960_i2c_remove(struct i2c_client *client)
f2644a2c 1359{
f0fba2ad 1360 snd_soc_unregister_codec(&client->dev);
f2644a2c
MB		 1361 return 0;
1362}
1363
1364static const struct i2c_device_id wm8960_i2c_id[] = {
1365 { "wm8960", 0 },
1366 { }
1367};
1368MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id);
1369
e2280c90
ZW		 1370static const struct of_device_id wm8960_of_match[] = {
1371 { .compatible = "wlf,wm8960", },
1372 { }
1373};
1374MODULE_DEVICE_TABLE(of, wm8960_of_match);
1375
f2644a2c
MB		 1376static struct i2c_driver wm8960_i2c_driver = {
1377 .driver = {
091edccf 1378 .name = "wm8960",
e2280c90 1379 .of_match_table = wm8960_of_match,
f2644a2c
MB		 1380 },
1381 .probe = wm8960_i2c_probe,
7a79e94e 1382 .remove = wm8960_i2c_remove,
f2644a2c
MB		 1383 .id_table = wm8960_i2c_id,
1384};
1385
3c010e60 1386module_i2c_driver(wm8960_i2c_driver);
f2644a2c 1387
f2644a2c
MB		 1388MODULE_DESCRIPTION("ASoC WM8960 driver");
1389MODULE_AUTHOR("Liam Girdwood");
1390MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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