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f2644a2c MB |
1 | /* |
2 | * wm8960.c -- WM8960 ALSA SoC Audio driver | |
3 | * | |
656baaeb MB |
4 | * Copyright 2007-11 Wolfson Microelectronics, plc |
5 | * | |
f2644a2c MB |
6 | * Author: Liam Girdwood |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/pm.h> | |
75aa8868 | 18 | #include <linux/clk.h> |
f2644a2c | 19 | #include <linux/i2c.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
f2644a2c MB |
21 | #include <sound/core.h> |
22 | #include <sound/pcm.h> | |
23 | #include <sound/pcm_params.h> | |
24 | #include <sound/soc.h> | |
f2644a2c MB |
25 | #include <sound/initval.h> |
26 | #include <sound/tlv.h> | |
b6877a47 | 27 | #include <sound/wm8960.h> |
f2644a2c MB |
28 | |
29 | #include "wm8960.h" | |
30 | ||
f2644a2c | 31 | /* R25 - Power 1 */ |
913d7b4c | 32 | #define WM8960_VMID_MASK 0x180 |
f2644a2c MB |
33 | #define WM8960_VREF 0x40 |
34 | ||
913d7b4c MB |
35 | /* R26 - Power 2 */ |
36 | #define WM8960_PWR2_LOUT1 0x40 | |
37 | #define WM8960_PWR2_ROUT1 0x20 | |
38 | #define WM8960_PWR2_OUT3 0x02 | |
39 | ||
f2644a2c MB |
40 | /* R28 - Anti-pop 1 */ |
41 | #define WM8960_POBCTRL 0x80 | |
42 | #define WM8960_BUFDCOPEN 0x10 | |
43 | #define WM8960_BUFIOEN 0x08 | |
44 | #define WM8960_SOFT_ST 0x04 | |
45 | #define WM8960_HPSTBY 0x01 | |
46 | ||
47 | /* R29 - Anti-pop 2 */ | |
48 | #define WM8960_DISOP 0x40 | |
913d7b4c | 49 | #define WM8960_DRES_MASK 0x30 |
f2644a2c MB |
50 | |
51 | /* | |
52 | * wm8960 register cache | |
53 | * We can't read the WM8960 register space when we are | |
54 | * using 2 wire for device control, so we cache them instead. | |
55 | */ | |
0ebe36c6 | 56 | static const struct reg_default wm8960_reg_defaults[] = { |
b3df026e MB |
57 | { 0x0, 0x00a7 }, |
58 | { 0x1, 0x00a7 }, | |
0ebe36c6 MB |
59 | { 0x2, 0x0000 }, |
60 | { 0x3, 0x0000 }, | |
61 | { 0x4, 0x0000 }, | |
62 | { 0x5, 0x0008 }, | |
63 | { 0x6, 0x0000 }, | |
64 | { 0x7, 0x000a }, | |
65 | { 0x8, 0x01c0 }, | |
66 | { 0x9, 0x0000 }, | |
67 | { 0xa, 0x00ff }, | |
68 | { 0xb, 0x00ff }, | |
69 | ||
70 | { 0x10, 0x0000 }, | |
71 | { 0x11, 0x007b }, | |
72 | { 0x12, 0x0100 }, | |
73 | { 0x13, 0x0032 }, | |
74 | { 0x14, 0x0000 }, | |
75 | { 0x15, 0x00c3 }, | |
76 | { 0x16, 0x00c3 }, | |
77 | { 0x17, 0x01c0 }, | |
78 | { 0x18, 0x0000 }, | |
79 | { 0x19, 0x0000 }, | |
80 | { 0x1a, 0x0000 }, | |
81 | { 0x1b, 0x0000 }, | |
82 | { 0x1c, 0x0000 }, | |
83 | { 0x1d, 0x0000 }, | |
84 | ||
85 | { 0x20, 0x0100 }, | |
86 | { 0x21, 0x0100 }, | |
87 | { 0x22, 0x0050 }, | |
88 | ||
89 | { 0x25, 0x0050 }, | |
90 | { 0x26, 0x0000 }, | |
91 | { 0x27, 0x0000 }, | |
92 | { 0x28, 0x0000 }, | |
93 | { 0x29, 0x0000 }, | |
94 | { 0x2a, 0x0040 }, | |
95 | { 0x2b, 0x0000 }, | |
96 | { 0x2c, 0x0000 }, | |
97 | { 0x2d, 0x0050 }, | |
98 | { 0x2e, 0x0050 }, | |
99 | { 0x2f, 0x0000 }, | |
100 | { 0x30, 0x0002 }, | |
101 | { 0x31, 0x0037 }, | |
102 | ||
103 | { 0x33, 0x0080 }, | |
104 | { 0x34, 0x0008 }, | |
105 | { 0x35, 0x0031 }, | |
106 | { 0x36, 0x0026 }, | |
107 | { 0x37, 0x00e9 }, | |
f2644a2c MB |
108 | }; |
109 | ||
0ebe36c6 MB |
110 | static bool wm8960_volatile(struct device *dev, unsigned int reg) |
111 | { | |
112 | switch (reg) { | |
113 | case WM8960_RESET: | |
114 | return true; | |
115 | default: | |
116 | return false; | |
117 | } | |
118 | } | |
119 | ||
f2644a2c | 120 | struct wm8960_priv { |
75aa8868 | 121 | struct clk *mclk; |
0ebe36c6 | 122 | struct regmap *regmap; |
f0fba2ad LG |
123 | int (*set_bias_level)(struct snd_soc_codec *, |
124 | enum snd_soc_bias_level level); | |
913d7b4c MB |
125 | struct snd_soc_dapm_widget *lout1; |
126 | struct snd_soc_dapm_widget *rout1; | |
127 | struct snd_soc_dapm_widget *out3; | |
afd6d36a MB |
128 | bool deemph; |
129 | int playback_fs; | |
0e50b51a ZW |
130 | int bclk; |
131 | int sysclk; | |
e2280c90 | 132 | struct wm8960_data pdata; |
f2644a2c MB |
133 | }; |
134 | ||
3ad5e861 | 135 | #define wm8960_reset(c) regmap_write(c, WM8960_RESET, 0) |
f2644a2c MB |
136 | |
137 | /* enumerated controls */ | |
f2644a2c MB |
138 | static const char *wm8960_polarity[] = {"No Inversion", "Left Inverted", |
139 | "Right Inverted", "Stereo Inversion"}; | |
140 | static const char *wm8960_3d_upper_cutoff[] = {"High", "Low"}; | |
141 | static const char *wm8960_3d_lower_cutoff[] = {"Low", "High"}; | |
142 | static const char *wm8960_alcfunc[] = {"Off", "Right", "Left", "Stereo"}; | |
143 | static const char *wm8960_alcmode[] = {"ALC", "Limiter"}; | |
144 | ||
145 | static const struct soc_enum wm8960_enum[] = { | |
f2644a2c MB |
146 | SOC_ENUM_SINGLE(WM8960_DACCTL1, 5, 4, wm8960_polarity), |
147 | SOC_ENUM_SINGLE(WM8960_DACCTL2, 5, 4, wm8960_polarity), | |
148 | SOC_ENUM_SINGLE(WM8960_3D, 6, 2, wm8960_3d_upper_cutoff), | |
149 | SOC_ENUM_SINGLE(WM8960_3D, 5, 2, wm8960_3d_lower_cutoff), | |
150 | SOC_ENUM_SINGLE(WM8960_ALC1, 7, 4, wm8960_alcfunc), | |
151 | SOC_ENUM_SINGLE(WM8960_ALC3, 8, 2, wm8960_alcmode), | |
152 | }; | |
153 | ||
afd6d36a MB |
154 | static const int deemph_settings[] = { 0, 32000, 44100, 48000 }; |
155 | ||
156 | static int wm8960_set_deemph(struct snd_soc_codec *codec) | |
157 | { | |
158 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
159 | int val, i, best; | |
160 | ||
161 | /* If we're using deemphasis select the nearest available sample | |
162 | * rate. | |
163 | */ | |
164 | if (wm8960->deemph) { | |
165 | best = 1; | |
166 | for (i = 2; i < ARRAY_SIZE(deemph_settings); i++) { | |
167 | if (abs(deemph_settings[i] - wm8960->playback_fs) < | |
168 | abs(deemph_settings[best] - wm8960->playback_fs)) | |
169 | best = i; | |
170 | } | |
171 | ||
172 | val = best << 1; | |
173 | } else { | |
174 | val = 0; | |
175 | } | |
176 | ||
177 | dev_dbg(codec->dev, "Set deemphasis %d\n", val); | |
178 | ||
179 | return snd_soc_update_bits(codec, WM8960_DACCTL1, | |
180 | 0x6, val); | |
181 | } | |
182 | ||
183 | static int wm8960_get_deemph(struct snd_kcontrol *kcontrol, | |
184 | struct snd_ctl_elem_value *ucontrol) | |
185 | { | |
ea53bf77 | 186 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
afd6d36a MB |
187 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
188 | ||
b4a18c8b | 189 | ucontrol->value.integer.value[0] = wm8960->deemph; |
3f343f85 | 190 | return 0; |
afd6d36a MB |
191 | } |
192 | ||
193 | static int wm8960_put_deemph(struct snd_kcontrol *kcontrol, | |
194 | struct snd_ctl_elem_value *ucontrol) | |
195 | { | |
ea53bf77 | 196 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
afd6d36a | 197 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
b4a18c8b | 198 | int deemph = ucontrol->value.integer.value[0]; |
afd6d36a MB |
199 | |
200 | if (deemph > 1) | |
201 | return -EINVAL; | |
202 | ||
203 | wm8960->deemph = deemph; | |
204 | ||
205 | return wm8960_set_deemph(codec); | |
206 | } | |
207 | ||
3758ff5f ZW |
208 | static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1); |
209 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); | |
f2644a2c MB |
210 | static const DECLARE_TLV_DB_SCALE(bypass_tlv, -2100, 300, 0); |
211 | static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); | |
3758ff5f | 212 | static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); |
f2644a2c MB |
213 | |
214 | static const struct snd_kcontrol_new wm8960_snd_controls[] = { | |
215 | SOC_DOUBLE_R_TLV("Capture Volume", WM8960_LINVOL, WM8960_RINVOL, | |
216 | 0, 63, 0, adc_tlv), | |
217 | SOC_DOUBLE_R("Capture Volume ZC Switch", WM8960_LINVOL, WM8960_RINVOL, | |
218 | 6, 1, 0), | |
219 | SOC_DOUBLE_R("Capture Switch", WM8960_LINVOL, WM8960_RINVOL, | |
220 | 7, 1, 0), | |
221 | ||
21eb2693 MB |
222 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT3 Volume", |
223 | WM8960_INBMIX1, 4, 7, 0, boost_tlv), | |
224 | SOC_SINGLE_TLV("Right Input Boost Mixer RINPUT2 Volume", | |
225 | WM8960_INBMIX1, 1, 7, 0, boost_tlv), | |
226 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT3 Volume", | |
227 | WM8960_INBMIX2, 4, 7, 0, boost_tlv), | |
228 | SOC_SINGLE_TLV("Left Input Boost Mixer LINPUT2 Volume", | |
229 | WM8960_INBMIX2, 1, 7, 0, boost_tlv), | |
230 | ||
f2644a2c MB |
231 | SOC_DOUBLE_R_TLV("Playback Volume", WM8960_LDAC, WM8960_RDAC, |
232 | 0, 255, 0, dac_tlv), | |
233 | ||
234 | SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8960_LOUT1, WM8960_ROUT1, | |
235 | 0, 127, 0, out_tlv), | |
236 | SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8960_LOUT1, WM8960_ROUT1, | |
237 | 7, 1, 0), | |
238 | ||
239 | SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8960_LOUT2, WM8960_ROUT2, | |
240 | 0, 127, 0, out_tlv), | |
241 | SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8960_LOUT2, WM8960_ROUT2, | |
242 | 7, 1, 0), | |
243 | SOC_SINGLE("Speaker DC Volume", WM8960_CLASSD3, 3, 5, 0), | |
244 | SOC_SINGLE("Speaker AC Volume", WM8960_CLASSD3, 0, 5, 0), | |
245 | ||
246 | SOC_SINGLE("PCM Playback -6dB Switch", WM8960_DACCTL1, 7, 1, 0), | |
4faaa8d9 | 247 | SOC_ENUM("ADC Polarity", wm8960_enum[0]), |
f2644a2c MB |
248 | SOC_SINGLE("ADC High Pass Filter Switch", WM8960_DACCTL1, 0, 1, 0), |
249 | ||
a077e81e | 250 | SOC_ENUM("DAC Polarity", wm8960_enum[1]), |
afd6d36a MB |
251 | SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0, |
252 | wm8960_get_deemph, wm8960_put_deemph), | |
f2644a2c | 253 | |
4faaa8d9 MB |
254 | SOC_ENUM("3D Filter Upper Cut-Off", wm8960_enum[2]), |
255 | SOC_ENUM("3D Filter Lower Cut-Off", wm8960_enum[3]), | |
f2644a2c MB |
256 | SOC_SINGLE("3D Volume", WM8960_3D, 1, 15, 0), |
257 | SOC_SINGLE("3D Switch", WM8960_3D, 0, 1, 0), | |
258 | ||
4faaa8d9 | 259 | SOC_ENUM("ALC Function", wm8960_enum[4]), |
f2644a2c MB |
260 | SOC_SINGLE("ALC Max Gain", WM8960_ALC1, 4, 7, 0), |
261 | SOC_SINGLE("ALC Target", WM8960_ALC1, 0, 15, 1), | |
262 | SOC_SINGLE("ALC Min Gain", WM8960_ALC2, 4, 7, 0), | |
263 | SOC_SINGLE("ALC Hold Time", WM8960_ALC2, 0, 15, 0), | |
4faaa8d9 | 264 | SOC_ENUM("ALC Mode", wm8960_enum[5]), |
f2644a2c MB |
265 | SOC_SINGLE("ALC Decay", WM8960_ALC3, 4, 15, 0), |
266 | SOC_SINGLE("ALC Attack", WM8960_ALC3, 0, 15, 0), | |
267 | ||
268 | SOC_SINGLE("Noise Gate Threshold", WM8960_NOISEG, 3, 31, 0), | |
269 | SOC_SINGLE("Noise Gate Switch", WM8960_NOISEG, 0, 1, 0), | |
270 | ||
c324aac0 MH |
271 | SOC_DOUBLE_R_TLV("ADC PCM Capture Volume", WM8960_LADC, WM8960_RADC, |
272 | 0, 255, 0, adc_tlv), | |
f2644a2c MB |
273 | |
274 | SOC_SINGLE_TLV("Left Output Mixer Boost Bypass Volume", | |
275 | WM8960_BYPASS1, 4, 7, 1, bypass_tlv), | |
276 | SOC_SINGLE_TLV("Left Output Mixer LINPUT3 Volume", | |
277 | WM8960_LOUTMIX, 4, 7, 1, bypass_tlv), | |
278 | SOC_SINGLE_TLV("Right Output Mixer Boost Bypass Volume", | |
279 | WM8960_BYPASS2, 4, 7, 1, bypass_tlv), | |
280 | SOC_SINGLE_TLV("Right Output Mixer RINPUT3 Volume", | |
281 | WM8960_ROUTMIX, 4, 7, 1, bypass_tlv), | |
282 | }; | |
283 | ||
284 | static const struct snd_kcontrol_new wm8960_lin_boost[] = { | |
285 | SOC_DAPM_SINGLE("LINPUT2 Switch", WM8960_LINPATH, 6, 1, 0), | |
286 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LINPATH, 7, 1, 0), | |
287 | SOC_DAPM_SINGLE("LINPUT1 Switch", WM8960_LINPATH, 8, 1, 0), | |
288 | }; | |
289 | ||
290 | static const struct snd_kcontrol_new wm8960_lin[] = { | |
291 | SOC_DAPM_SINGLE("Boost Switch", WM8960_LINPATH, 3, 1, 0), | |
292 | }; | |
293 | ||
294 | static const struct snd_kcontrol_new wm8960_rin_boost[] = { | |
295 | SOC_DAPM_SINGLE("RINPUT2 Switch", WM8960_RINPATH, 6, 1, 0), | |
296 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_RINPATH, 7, 1, 0), | |
297 | SOC_DAPM_SINGLE("RINPUT1 Switch", WM8960_RINPATH, 8, 1, 0), | |
298 | }; | |
299 | ||
300 | static const struct snd_kcontrol_new wm8960_rin[] = { | |
301 | SOC_DAPM_SINGLE("Boost Switch", WM8960_RINPATH, 3, 1, 0), | |
302 | }; | |
303 | ||
304 | static const struct snd_kcontrol_new wm8960_loutput_mixer[] = { | |
305 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_LOUTMIX, 8, 1, 0), | |
306 | SOC_DAPM_SINGLE("LINPUT3 Switch", WM8960_LOUTMIX, 7, 1, 0), | |
307 | SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS1, 7, 1, 0), | |
308 | }; | |
309 | ||
310 | static const struct snd_kcontrol_new wm8960_routput_mixer[] = { | |
311 | SOC_DAPM_SINGLE("PCM Playback Switch", WM8960_ROUTMIX, 8, 1, 0), | |
312 | SOC_DAPM_SINGLE("RINPUT3 Switch", WM8960_ROUTMIX, 7, 1, 0), | |
313 | SOC_DAPM_SINGLE("Boost Bypass Switch", WM8960_BYPASS2, 7, 1, 0), | |
314 | }; | |
315 | ||
316 | static const struct snd_kcontrol_new wm8960_mono_out[] = { | |
317 | SOC_DAPM_SINGLE("Left Switch", WM8960_MONOMIX1, 7, 1, 0), | |
318 | SOC_DAPM_SINGLE("Right Switch", WM8960_MONOMIX2, 7, 1, 0), | |
319 | }; | |
320 | ||
321 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets[] = { | |
322 | SND_SOC_DAPM_INPUT("LINPUT1"), | |
323 | SND_SOC_DAPM_INPUT("RINPUT1"), | |
324 | SND_SOC_DAPM_INPUT("LINPUT2"), | |
325 | SND_SOC_DAPM_INPUT("RINPUT2"), | |
326 | SND_SOC_DAPM_INPUT("LINPUT3"), | |
327 | SND_SOC_DAPM_INPUT("RINPUT3"), | |
328 | ||
187774cb | 329 | SND_SOC_DAPM_SUPPLY("MICB", WM8960_POWER1, 1, 0, NULL, 0), |
f2644a2c MB |
330 | |
331 | SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8960_POWER1, 5, 0, | |
332 | wm8960_lin_boost, ARRAY_SIZE(wm8960_lin_boost)), | |
333 | SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8960_POWER1, 4, 0, | |
334 | wm8960_rin_boost, ARRAY_SIZE(wm8960_rin_boost)), | |
335 | ||
336 | SND_SOC_DAPM_MIXER("Left Input Mixer", WM8960_POWER3, 5, 0, | |
337 | wm8960_lin, ARRAY_SIZE(wm8960_lin)), | |
338 | SND_SOC_DAPM_MIXER("Right Input Mixer", WM8960_POWER3, 4, 0, | |
339 | wm8960_rin, ARRAY_SIZE(wm8960_rin)), | |
340 | ||
44426de4 MB |
341 | SND_SOC_DAPM_ADC("Left ADC", "Capture", WM8960_POWER1, 3, 0), |
342 | SND_SOC_DAPM_ADC("Right ADC", "Capture", WM8960_POWER1, 2, 0), | |
f2644a2c MB |
343 | |
344 | SND_SOC_DAPM_DAC("Left DAC", "Playback", WM8960_POWER2, 8, 0), | |
345 | SND_SOC_DAPM_DAC("Right DAC", "Playback", WM8960_POWER2, 7, 0), | |
346 | ||
347 | SND_SOC_DAPM_MIXER("Left Output Mixer", WM8960_POWER3, 3, 0, | |
348 | &wm8960_loutput_mixer[0], | |
349 | ARRAY_SIZE(wm8960_loutput_mixer)), | |
350 | SND_SOC_DAPM_MIXER("Right Output Mixer", WM8960_POWER3, 2, 0, | |
351 | &wm8960_routput_mixer[0], | |
352 | ARRAY_SIZE(wm8960_routput_mixer)), | |
353 | ||
f2644a2c MB |
354 | SND_SOC_DAPM_PGA("LOUT1 PGA", WM8960_POWER2, 6, 0, NULL, 0), |
355 | SND_SOC_DAPM_PGA("ROUT1 PGA", WM8960_POWER2, 5, 0, NULL, 0), | |
356 | ||
357 | SND_SOC_DAPM_PGA("Left Speaker PGA", WM8960_POWER2, 4, 0, NULL, 0), | |
358 | SND_SOC_DAPM_PGA("Right Speaker PGA", WM8960_POWER2, 3, 0, NULL, 0), | |
359 | ||
360 | SND_SOC_DAPM_PGA("Right Speaker Output", WM8960_CLASSD1, 7, 0, NULL, 0), | |
361 | SND_SOC_DAPM_PGA("Left Speaker Output", WM8960_CLASSD1, 6, 0, NULL, 0), | |
362 | ||
363 | SND_SOC_DAPM_OUTPUT("SPK_LP"), | |
364 | SND_SOC_DAPM_OUTPUT("SPK_LN"), | |
365 | SND_SOC_DAPM_OUTPUT("HP_L"), | |
366 | SND_SOC_DAPM_OUTPUT("HP_R"), | |
367 | SND_SOC_DAPM_OUTPUT("SPK_RP"), | |
368 | SND_SOC_DAPM_OUTPUT("SPK_RN"), | |
369 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
370 | }; | |
371 | ||
913d7b4c MB |
372 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets_out3[] = { |
373 | SND_SOC_DAPM_MIXER("Mono Output Mixer", WM8960_POWER2, 1, 0, | |
374 | &wm8960_mono_out[0], | |
375 | ARRAY_SIZE(wm8960_mono_out)), | |
376 | }; | |
377 | ||
378 | /* Represent OUT3 as a PGA so that it gets turned on with LOUT1/ROUT1 */ | |
379 | static const struct snd_soc_dapm_widget wm8960_dapm_widgets_capless[] = { | |
380 | SND_SOC_DAPM_PGA("OUT3 VMID", WM8960_POWER2, 1, 0, NULL, 0), | |
381 | }; | |
382 | ||
f2644a2c MB |
383 | static const struct snd_soc_dapm_route audio_paths[] = { |
384 | { "Left Boost Mixer", "LINPUT1 Switch", "LINPUT1" }, | |
385 | { "Left Boost Mixer", "LINPUT2 Switch", "LINPUT2" }, | |
386 | { "Left Boost Mixer", "LINPUT3 Switch", "LINPUT3" }, | |
387 | ||
388 | { "Left Input Mixer", "Boost Switch", "Left Boost Mixer", }, | |
389 | { "Left Input Mixer", NULL, "LINPUT1", }, /* Really Boost Switch */ | |
390 | { "Left Input Mixer", NULL, "LINPUT2" }, | |
391 | { "Left Input Mixer", NULL, "LINPUT3" }, | |
392 | ||
393 | { "Right Boost Mixer", "RINPUT1 Switch", "RINPUT1" }, | |
394 | { "Right Boost Mixer", "RINPUT2 Switch", "RINPUT2" }, | |
395 | { "Right Boost Mixer", "RINPUT3 Switch", "RINPUT3" }, | |
396 | ||
397 | { "Right Input Mixer", "Boost Switch", "Right Boost Mixer", }, | |
398 | { "Right Input Mixer", NULL, "RINPUT1", }, /* Really Boost Switch */ | |
399 | { "Right Input Mixer", NULL, "RINPUT2" }, | |
85e36a1f | 400 | { "Right Input Mixer", NULL, "RINPUT3" }, |
f2644a2c MB |
401 | |
402 | { "Left ADC", NULL, "Left Input Mixer" }, | |
403 | { "Right ADC", NULL, "Right Input Mixer" }, | |
404 | ||
405 | { "Left Output Mixer", "LINPUT3 Switch", "LINPUT3" }, | |
406 | { "Left Output Mixer", "Boost Bypass Switch", "Left Boost Mixer"} , | |
407 | { "Left Output Mixer", "PCM Playback Switch", "Left DAC" }, | |
408 | ||
409 | { "Right Output Mixer", "RINPUT3 Switch", "RINPUT3" }, | |
410 | { "Right Output Mixer", "Boost Bypass Switch", "Right Boost Mixer" } , | |
411 | { "Right Output Mixer", "PCM Playback Switch", "Right DAC" }, | |
412 | ||
f2644a2c MB |
413 | { "LOUT1 PGA", NULL, "Left Output Mixer" }, |
414 | { "ROUT1 PGA", NULL, "Right Output Mixer" }, | |
415 | ||
416 | { "HP_L", NULL, "LOUT1 PGA" }, | |
417 | { "HP_R", NULL, "ROUT1 PGA" }, | |
418 | ||
419 | { "Left Speaker PGA", NULL, "Left Output Mixer" }, | |
420 | { "Right Speaker PGA", NULL, "Right Output Mixer" }, | |
421 | ||
422 | { "Left Speaker Output", NULL, "Left Speaker PGA" }, | |
423 | { "Right Speaker Output", NULL, "Right Speaker PGA" }, | |
424 | ||
425 | { "SPK_LN", NULL, "Left Speaker Output" }, | |
426 | { "SPK_LP", NULL, "Left Speaker Output" }, | |
427 | { "SPK_RN", NULL, "Right Speaker Output" }, | |
428 | { "SPK_RP", NULL, "Right Speaker Output" }, | |
913d7b4c MB |
429 | }; |
430 | ||
431 | static const struct snd_soc_dapm_route audio_paths_out3[] = { | |
432 | { "Mono Output Mixer", "Left Switch", "Left Output Mixer" }, | |
433 | { "Mono Output Mixer", "Right Switch", "Right Output Mixer" }, | |
f2644a2c MB |
434 | |
435 | { "OUT3", NULL, "Mono Output Mixer", } | |
436 | }; | |
437 | ||
913d7b4c MB |
438 | static const struct snd_soc_dapm_route audio_paths_capless[] = { |
439 | { "HP_L", NULL, "OUT3 VMID" }, | |
440 | { "HP_R", NULL, "OUT3 VMID" }, | |
441 | ||
442 | { "OUT3 VMID", NULL, "Left Output Mixer" }, | |
443 | { "OUT3 VMID", NULL, "Right Output Mixer" }, | |
444 | }; | |
445 | ||
f2644a2c MB |
446 | static int wm8960_add_widgets(struct snd_soc_codec *codec) |
447 | { | |
b2c812e2 | 448 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
e2280c90 | 449 | struct wm8960_data *pdata = &wm8960->pdata; |
93f32f53 | 450 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
913d7b4c MB |
451 | struct snd_soc_dapm_widget *w; |
452 | ||
ce6120cc | 453 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets, |
f2644a2c MB |
454 | ARRAY_SIZE(wm8960_dapm_widgets)); |
455 | ||
ce6120cc | 456 | snd_soc_dapm_add_routes(dapm, audio_paths, ARRAY_SIZE(audio_paths)); |
f2644a2c | 457 | |
913d7b4c MB |
458 | /* In capless mode OUT3 is used to provide VMID for the |
459 | * headphone outputs, otherwise it is used as a mono mixer. | |
460 | */ | |
461 | if (pdata && pdata->capless) { | |
ce6120cc | 462 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_capless, |
913d7b4c MB |
463 | ARRAY_SIZE(wm8960_dapm_widgets_capless)); |
464 | ||
ce6120cc | 465 | snd_soc_dapm_add_routes(dapm, audio_paths_capless, |
913d7b4c MB |
466 | ARRAY_SIZE(audio_paths_capless)); |
467 | } else { | |
ce6120cc | 468 | snd_soc_dapm_new_controls(dapm, wm8960_dapm_widgets_out3, |
913d7b4c MB |
469 | ARRAY_SIZE(wm8960_dapm_widgets_out3)); |
470 | ||
ce6120cc | 471 | snd_soc_dapm_add_routes(dapm, audio_paths_out3, |
913d7b4c MB |
472 | ARRAY_SIZE(audio_paths_out3)); |
473 | } | |
474 | ||
475 | /* We need to power up the headphone output stage out of | |
476 | * sequence for capless mode. To save scanning the widget | |
477 | * list each time to find the desired power state do so now | |
478 | * and save the result. | |
479 | */ | |
00200107 | 480 | list_for_each_entry(w, &codec->component.card->widgets, list) { |
93f32f53 | 481 | if (w->dapm != dapm) |
97c866de | 482 | continue; |
913d7b4c MB |
483 | if (strcmp(w->name, "LOUT1 PGA") == 0) |
484 | wm8960->lout1 = w; | |
485 | if (strcmp(w->name, "ROUT1 PGA") == 0) | |
486 | wm8960->rout1 = w; | |
487 | if (strcmp(w->name, "OUT3 VMID") == 0) | |
488 | wm8960->out3 = w; | |
489 | } | |
490 | ||
f2644a2c MB |
491 | return 0; |
492 | } | |
493 | ||
494 | static int wm8960_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
495 | unsigned int fmt) | |
496 | { | |
497 | struct snd_soc_codec *codec = codec_dai->codec; | |
498 | u16 iface = 0; | |
499 | ||
500 | /* set master/slave audio interface */ | |
501 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
502 | case SND_SOC_DAIFMT_CBM_CFM: | |
503 | iface |= 0x0040; | |
504 | break; | |
505 | case SND_SOC_DAIFMT_CBS_CFS: | |
506 | break; | |
507 | default: | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
511 | /* interface format */ | |
512 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
513 | case SND_SOC_DAIFMT_I2S: | |
514 | iface |= 0x0002; | |
515 | break; | |
516 | case SND_SOC_DAIFMT_RIGHT_J: | |
517 | break; | |
518 | case SND_SOC_DAIFMT_LEFT_J: | |
519 | iface |= 0x0001; | |
520 | break; | |
521 | case SND_SOC_DAIFMT_DSP_A: | |
522 | iface |= 0x0003; | |
523 | break; | |
524 | case SND_SOC_DAIFMT_DSP_B: | |
525 | iface |= 0x0013; | |
526 | break; | |
527 | default: | |
528 | return -EINVAL; | |
529 | } | |
530 | ||
531 | /* clock inversion */ | |
532 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
533 | case SND_SOC_DAIFMT_NB_NF: | |
534 | break; | |
535 | case SND_SOC_DAIFMT_IB_IF: | |
536 | iface |= 0x0090; | |
537 | break; | |
538 | case SND_SOC_DAIFMT_IB_NF: | |
539 | iface |= 0x0080; | |
540 | break; | |
541 | case SND_SOC_DAIFMT_NB_IF: | |
542 | iface |= 0x0010; | |
543 | break; | |
544 | default: | |
545 | return -EINVAL; | |
546 | } | |
547 | ||
548 | /* set iface */ | |
17a52fd6 | 549 | snd_soc_write(codec, WM8960_IFACE1, iface); |
f2644a2c MB |
550 | return 0; |
551 | } | |
552 | ||
db059c0f MB |
553 | static struct { |
554 | int rate; | |
555 | unsigned int val; | |
556 | } alc_rates[] = { | |
557 | { 48000, 0 }, | |
558 | { 44100, 0 }, | |
559 | { 32000, 1 }, | |
560 | { 22050, 2 }, | |
561 | { 24000, 2 }, | |
562 | { 16000, 3 }, | |
22ee76da | 563 | { 11025, 4 }, |
db059c0f MB |
564 | { 12000, 4 }, |
565 | { 8000, 5 }, | |
566 | }; | |
567 | ||
0e50b51a ZW |
568 | /* Multiply 256 for internal 256 div */ |
569 | static const int dac_divs[] = { 256, 384, 512, 768, 1024, 1408, 1536 }; | |
570 | ||
571 | /* Multiply 10 to eliminate decimials */ | |
572 | static const int bclk_divs[] = { | |
573 | 10, 15, 20, 30, 40, 55, 60, 80, 110, | |
574 | 120, 160, 220, 240, 320, 320, 320 | |
575 | }; | |
576 | ||
577 | static void wm8960_configure_clocking(struct snd_soc_codec *codec, | |
578 | bool tx, int lrclk) | |
579 | { | |
580 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
581 | u16 iface1 = snd_soc_read(codec, WM8960_IFACE1); | |
582 | u16 iface2 = snd_soc_read(codec, WM8960_IFACE2); | |
583 | u32 sysclk; | |
584 | int i, j; | |
585 | ||
586 | if (!(iface1 & (1<<6))) { | |
587 | dev_dbg(codec->dev, | |
588 | "Codec is slave mode, no need to configure clock\n"); | |
589 | return; | |
590 | } | |
591 | ||
592 | if (!wm8960->sysclk) { | |
593 | dev_dbg(codec->dev, "No SYSCLK configured\n"); | |
594 | return; | |
595 | } | |
596 | ||
597 | if (!wm8960->bclk || !lrclk) { | |
598 | dev_dbg(codec->dev, "No audio clocks configured\n"); | |
599 | return; | |
600 | } | |
601 | ||
602 | for (i = 0; i < ARRAY_SIZE(dac_divs); ++i) { | |
603 | if (wm8960->sysclk == lrclk * dac_divs[i]) { | |
604 | for (j = 0; j < ARRAY_SIZE(bclk_divs); ++j) { | |
605 | sysclk = wm8960->bclk * bclk_divs[j] / 10; | |
606 | if (wm8960->sysclk == sysclk) | |
607 | break; | |
608 | } | |
609 | if(j != ARRAY_SIZE(bclk_divs)) | |
610 | break; | |
611 | } | |
612 | } | |
613 | ||
614 | if (i == ARRAY_SIZE(dac_divs)) { | |
615 | dev_err(codec->dev, "Unsupported sysclk %d\n", wm8960->sysclk); | |
616 | return; | |
617 | } | |
618 | ||
619 | /* | |
620 | * configure frame clock. If ADCLRC configure as GPIO pin, DACLRC | |
621 | * pin is used as a frame clock for ADCs and DACs. | |
622 | */ | |
623 | if (iface2 & (1<<6)) | |
624 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3); | |
625 | else if (tx) | |
626 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 3, i << 3); | |
627 | else if (!tx) | |
628 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x7 << 6, i << 6); | |
629 | ||
630 | /* configure bit clock */ | |
631 | snd_soc_update_bits(codec, WM8960_CLOCK2, 0xf, j); | |
632 | } | |
633 | ||
f2644a2c MB |
634 | static int wm8960_hw_params(struct snd_pcm_substream *substream, |
635 | struct snd_pcm_hw_params *params, | |
636 | struct snd_soc_dai *dai) | |
637 | { | |
e6968a17 | 638 | struct snd_soc_codec *codec = dai->codec; |
afd6d36a | 639 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
17a52fd6 | 640 | u16 iface = snd_soc_read(codec, WM8960_IFACE1) & 0xfff3; |
0e50b51a | 641 | bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK; |
db059c0f | 642 | int i; |
f2644a2c | 643 | |
0e50b51a ZW |
644 | wm8960->bclk = snd_soc_params_to_bclk(params); |
645 | if (params_channels(params) == 1) | |
646 | wm8960->bclk *= 2; | |
647 | ||
f2644a2c | 648 | /* bit size */ |
39e9cc46 MB |
649 | switch (params_width(params)) { |
650 | case 16: | |
f2644a2c | 651 | break; |
39e9cc46 | 652 | case 20: |
f2644a2c MB |
653 | iface |= 0x0004; |
654 | break; | |
39e9cc46 | 655 | case 24: |
f2644a2c MB |
656 | iface |= 0x0008; |
657 | break; | |
7a8c7867 ZW |
658 | case 32: |
659 | /* right justify mode does not support 32 word length */ | |
660 | if ((iface & 0x3) != 0) { | |
661 | iface |= 0x000c; | |
662 | break; | |
663 | } | |
4c2474c0 | 664 | default: |
39e9cc46 MB |
665 | dev_err(codec->dev, "unsupported width %d\n", |
666 | params_width(params)); | |
4c2474c0 | 667 | return -EINVAL; |
f2644a2c MB |
668 | } |
669 | ||
afd6d36a MB |
670 | /* Update filters for the new rate */ |
671 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
672 | wm8960->playback_fs = params_rate(params); | |
673 | wm8960_set_deemph(codec); | |
db059c0f MB |
674 | } else { |
675 | for (i = 0; i < ARRAY_SIZE(alc_rates); i++) | |
676 | if (alc_rates[i].rate == params_rate(params)) | |
677 | snd_soc_update_bits(codec, | |
678 | WM8960_ADDCTL3, 0x7, | |
679 | alc_rates[i].val); | |
afd6d36a MB |
680 | } |
681 | ||
f2644a2c | 682 | /* set iface */ |
17a52fd6 | 683 | snd_soc_write(codec, WM8960_IFACE1, iface); |
0e50b51a ZW |
684 | |
685 | wm8960_configure_clocking(codec, tx, params_rate(params)); | |
686 | ||
f2644a2c MB |
687 | return 0; |
688 | } | |
689 | ||
690 | static int wm8960_mute(struct snd_soc_dai *dai, int mute) | |
691 | { | |
692 | struct snd_soc_codec *codec = dai->codec; | |
f2644a2c MB |
693 | |
694 | if (mute) | |
16b24881 | 695 | snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0x8); |
f2644a2c | 696 | else |
16b24881 | 697 | snd_soc_update_bits(codec, WM8960_DACCTL1, 0x8, 0); |
f2644a2c MB |
698 | return 0; |
699 | } | |
700 | ||
913d7b4c MB |
701 | static int wm8960_set_bias_level_out3(struct snd_soc_codec *codec, |
702 | enum snd_soc_bias_level level) | |
f2644a2c | 703 | { |
0ebe36c6 | 704 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
75aa8868 | 705 | int ret; |
0ebe36c6 | 706 | |
f2644a2c MB |
707 | switch (level) { |
708 | case SND_SOC_BIAS_ON: | |
709 | break; | |
710 | ||
711 | case SND_SOC_BIAS_PREPARE: | |
93f32f53 | 712 | switch (snd_soc_codec_get_bias_level(codec)) { |
75aa8868 ZW |
713 | case SND_SOC_BIAS_STANDBY: |
714 | if (!IS_ERR(wm8960->mclk)) { | |
715 | ret = clk_prepare_enable(wm8960->mclk); | |
716 | if (ret) { | |
717 | dev_err(codec->dev, | |
718 | "Failed to enable MCLK: %d\n", | |
719 | ret); | |
720 | return ret; | |
721 | } | |
722 | } | |
723 | ||
724 | /* Set VMID to 2x50k */ | |
725 | snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x80); | |
726 | break; | |
727 | ||
728 | case SND_SOC_BIAS_ON: | |
729 | if (!IS_ERR(wm8960->mclk)) | |
730 | clk_disable_unprepare(wm8960->mclk); | |
731 | break; | |
732 | ||
733 | default: | |
734 | break; | |
735 | } | |
736 | ||
f2644a2c MB |
737 | break; |
738 | ||
739 | case SND_SOC_BIAS_STANDBY: | |
93f32f53 | 740 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { |
0ebe36c6 | 741 | regcache_sync(wm8960->regmap); |
bc45df2d | 742 | |
f2644a2c | 743 | /* Enable anti-pop features */ |
17a52fd6 | 744 | snd_soc_write(codec, WM8960_APOP1, |
913d7b4c MB |
745 | WM8960_POBCTRL | WM8960_SOFT_ST | |
746 | WM8960_BUFDCOPEN | WM8960_BUFIOEN); | |
f2644a2c MB |
747 | |
748 | /* Enable & ramp VMID at 2x50k */ | |
16b24881 | 749 | snd_soc_update_bits(codec, WM8960_POWER1, 0x80, 0x80); |
f2644a2c MB |
750 | msleep(100); |
751 | ||
752 | /* Enable VREF */ | |
16b24881 AL |
753 | snd_soc_update_bits(codec, WM8960_POWER1, WM8960_VREF, |
754 | WM8960_VREF); | |
f2644a2c MB |
755 | |
756 | /* Disable anti-pop features */ | |
17a52fd6 | 757 | snd_soc_write(codec, WM8960_APOP1, WM8960_BUFIOEN); |
f2644a2c MB |
758 | } |
759 | ||
760 | /* Set VMID to 2x250k */ | |
16b24881 | 761 | snd_soc_update_bits(codec, WM8960_POWER1, 0x180, 0x100); |
f2644a2c MB |
762 | break; |
763 | ||
764 | case SND_SOC_BIAS_OFF: | |
765 | /* Enable anti-pop features */ | |
17a52fd6 | 766 | snd_soc_write(codec, WM8960_APOP1, |
f2644a2c MB |
767 | WM8960_POBCTRL | WM8960_SOFT_ST | |
768 | WM8960_BUFDCOPEN | WM8960_BUFIOEN); | |
769 | ||
770 | /* Disable VMID and VREF, let them discharge */ | |
17a52fd6 | 771 | snd_soc_write(codec, WM8960_POWER1, 0); |
f2644a2c | 772 | msleep(600); |
913d7b4c MB |
773 | break; |
774 | } | |
775 | ||
913d7b4c MB |
776 | return 0; |
777 | } | |
778 | ||
779 | static int wm8960_set_bias_level_capless(struct snd_soc_codec *codec, | |
780 | enum snd_soc_bias_level level) | |
781 | { | |
b2c812e2 | 782 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
75aa8868 | 783 | int reg, ret; |
913d7b4c MB |
784 | |
785 | switch (level) { | |
786 | case SND_SOC_BIAS_ON: | |
787 | break; | |
788 | ||
789 | case SND_SOC_BIAS_PREPARE: | |
93f32f53 | 790 | switch (snd_soc_codec_get_bias_level(codec)) { |
913d7b4c MB |
791 | case SND_SOC_BIAS_STANDBY: |
792 | /* Enable anti pop mode */ | |
793 | snd_soc_update_bits(codec, WM8960_APOP1, | |
794 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
795 | WM8960_BUFDCOPEN, | |
796 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
797 | WM8960_BUFDCOPEN); | |
798 | ||
799 | /* Enable LOUT1, ROUT1 and OUT3 if they're enabled */ | |
800 | reg = 0; | |
801 | if (wm8960->lout1 && wm8960->lout1->power) | |
802 | reg |= WM8960_PWR2_LOUT1; | |
803 | if (wm8960->rout1 && wm8960->rout1->power) | |
804 | reg |= WM8960_PWR2_ROUT1; | |
805 | if (wm8960->out3 && wm8960->out3->power) | |
806 | reg |= WM8960_PWR2_OUT3; | |
807 | snd_soc_update_bits(codec, WM8960_POWER2, | |
808 | WM8960_PWR2_LOUT1 | | |
809 | WM8960_PWR2_ROUT1 | | |
810 | WM8960_PWR2_OUT3, reg); | |
811 | ||
812 | /* Enable VMID at 2*50k */ | |
813 | snd_soc_update_bits(codec, WM8960_POWER1, | |
814 | WM8960_VMID_MASK, 0x80); | |
815 | ||
816 | /* Ramp */ | |
817 | msleep(100); | |
818 | ||
819 | /* Enable VREF */ | |
820 | snd_soc_update_bits(codec, WM8960_POWER1, | |
821 | WM8960_VREF, WM8960_VREF); | |
822 | ||
823 | msleep(100); | |
75aa8868 ZW |
824 | |
825 | if (!IS_ERR(wm8960->mclk)) { | |
826 | ret = clk_prepare_enable(wm8960->mclk); | |
827 | if (ret) { | |
828 | dev_err(codec->dev, | |
829 | "Failed to enable MCLK: %d\n", | |
830 | ret); | |
831 | return ret; | |
832 | } | |
833 | } | |
913d7b4c MB |
834 | break; |
835 | ||
836 | case SND_SOC_BIAS_ON: | |
75aa8868 ZW |
837 | if (!IS_ERR(wm8960->mclk)) |
838 | clk_disable_unprepare(wm8960->mclk); | |
839 | ||
913d7b4c MB |
840 | /* Enable anti-pop mode */ |
841 | snd_soc_update_bits(codec, WM8960_APOP1, | |
842 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
843 | WM8960_BUFDCOPEN, | |
844 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
845 | WM8960_BUFDCOPEN); | |
846 | ||
847 | /* Disable VMID and VREF */ | |
848 | snd_soc_update_bits(codec, WM8960_POWER1, | |
849 | WM8960_VREF | WM8960_VMID_MASK, 0); | |
850 | break; | |
851 | ||
bc45df2d | 852 | case SND_SOC_BIAS_OFF: |
0ebe36c6 | 853 | regcache_sync(wm8960->regmap); |
bc45df2d | 854 | break; |
913d7b4c MB |
855 | default: |
856 | break; | |
857 | } | |
858 | break; | |
f2644a2c | 859 | |
913d7b4c | 860 | case SND_SOC_BIAS_STANDBY: |
93f32f53 | 861 | switch (snd_soc_codec_get_bias_level(codec)) { |
913d7b4c MB |
862 | case SND_SOC_BIAS_PREPARE: |
863 | /* Disable HP discharge */ | |
864 | snd_soc_update_bits(codec, WM8960_APOP2, | |
865 | WM8960_DISOP | WM8960_DRES_MASK, | |
866 | 0); | |
867 | ||
868 | /* Disable anti-pop features */ | |
869 | snd_soc_update_bits(codec, WM8960_APOP1, | |
870 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
871 | WM8960_BUFDCOPEN, | |
872 | WM8960_POBCTRL | WM8960_SOFT_ST | | |
873 | WM8960_BUFDCOPEN); | |
874 | break; | |
875 | ||
876 | default: | |
877 | break; | |
878 | } | |
879 | break; | |
f2644a2c | 880 | |
913d7b4c | 881 | case SND_SOC_BIAS_OFF: |
f2644a2c MB |
882 | break; |
883 | } | |
884 | ||
f2644a2c MB |
885 | return 0; |
886 | } | |
887 | ||
888 | /* PLL divisors */ | |
889 | struct _pll_div { | |
890 | u32 pre_div:1; | |
891 | u32 n:4; | |
892 | u32 k:24; | |
893 | }; | |
894 | ||
895 | /* The size in bits of the pll divide multiplied by 10 | |
896 | * to allow rounding later */ | |
897 | #define FIXED_PLL_SIZE ((1 << 24) * 10) | |
898 | ||
899 | static int pll_factors(unsigned int source, unsigned int target, | |
900 | struct _pll_div *pll_div) | |
901 | { | |
902 | unsigned long long Kpart; | |
903 | unsigned int K, Ndiv, Nmod; | |
904 | ||
905 | pr_debug("WM8960 PLL: setting %dHz->%dHz\n", source, target); | |
906 | ||
907 | /* Scale up target to PLL operating frequency */ | |
908 | target *= 4; | |
909 | ||
910 | Ndiv = target / source; | |
911 | if (Ndiv < 6) { | |
912 | source >>= 1; | |
913 | pll_div->pre_div = 1; | |
914 | Ndiv = target / source; | |
915 | } else | |
916 | pll_div->pre_div = 0; | |
917 | ||
918 | if ((Ndiv < 6) || (Ndiv > 12)) { | |
919 | pr_err("WM8960 PLL: Unsupported N=%d\n", Ndiv); | |
920 | return -EINVAL; | |
921 | } | |
922 | ||
923 | pll_div->n = Ndiv; | |
924 | Nmod = target % source; | |
925 | Kpart = FIXED_PLL_SIZE * (long long)Nmod; | |
926 | ||
927 | do_div(Kpart, source); | |
928 | ||
929 | K = Kpart & 0xFFFFFFFF; | |
930 | ||
931 | /* Check if we need to round */ | |
932 | if ((K % 10) >= 5) | |
933 | K += 5; | |
934 | ||
935 | /* Move down to proper range now rounding is done */ | |
936 | K /= 10; | |
937 | ||
938 | pll_div->k = K; | |
939 | ||
940 | pr_debug("WM8960 PLL: N=%x K=%x pre_div=%d\n", | |
941 | pll_div->n, pll_div->k, pll_div->pre_div); | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
85488037 MB |
946 | static int wm8960_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
947 | int source, unsigned int freq_in, unsigned int freq_out) | |
f2644a2c MB |
948 | { |
949 | struct snd_soc_codec *codec = codec_dai->codec; | |
950 | u16 reg; | |
951 | static struct _pll_div pll_div; | |
952 | int ret; | |
953 | ||
954 | if (freq_in && freq_out) { | |
955 | ret = pll_factors(freq_in, freq_out, &pll_div); | |
956 | if (ret != 0) | |
957 | return ret; | |
958 | } | |
959 | ||
960 | /* Disable the PLL: even if we are changing the frequency the | |
961 | * PLL needs to be disabled while we do so. */ | |
16b24881 AL |
962 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0); |
963 | snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0); | |
f2644a2c MB |
964 | |
965 | if (!freq_in || !freq_out) | |
966 | return 0; | |
967 | ||
17a52fd6 | 968 | reg = snd_soc_read(codec, WM8960_PLL1) & ~0x3f; |
f2644a2c MB |
969 | reg |= pll_div.pre_div << 4; |
970 | reg |= pll_div.n; | |
971 | ||
972 | if (pll_div.k) { | |
973 | reg |= 0x20; | |
974 | ||
85fa532b MD |
975 | snd_soc_write(codec, WM8960_PLL2, (pll_div.k >> 16) & 0xff); |
976 | snd_soc_write(codec, WM8960_PLL3, (pll_div.k >> 8) & 0xff); | |
977 | snd_soc_write(codec, WM8960_PLL4, pll_div.k & 0xff); | |
f2644a2c | 978 | } |
17a52fd6 | 979 | snd_soc_write(codec, WM8960_PLL1, reg); |
f2644a2c MB |
980 | |
981 | /* Turn it on */ | |
16b24881 | 982 | snd_soc_update_bits(codec, WM8960_POWER2, 0x1, 0x1); |
f2644a2c | 983 | msleep(250); |
16b24881 | 984 | snd_soc_update_bits(codec, WM8960_CLOCK1, 0x1, 0x1); |
f2644a2c MB |
985 | |
986 | return 0; | |
987 | } | |
988 | ||
989 | static int wm8960_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |
990 | int div_id, int div) | |
991 | { | |
992 | struct snd_soc_codec *codec = codec_dai->codec; | |
993 | u16 reg; | |
994 | ||
995 | switch (div_id) { | |
f2644a2c | 996 | case WM8960_SYSCLKDIV: |
17a52fd6 MB |
997 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1f9; |
998 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); | |
f2644a2c MB |
999 | break; |
1000 | case WM8960_DACDIV: | |
17a52fd6 MB |
1001 | reg = snd_soc_read(codec, WM8960_CLOCK1) & 0x1c7; |
1002 | snd_soc_write(codec, WM8960_CLOCK1, reg | div); | |
f2644a2c MB |
1003 | break; |
1004 | case WM8960_OPCLKDIV: | |
17a52fd6 MB |
1005 | reg = snd_soc_read(codec, WM8960_PLL1) & 0x03f; |
1006 | snd_soc_write(codec, WM8960_PLL1, reg | div); | |
f2644a2c MB |
1007 | break; |
1008 | case WM8960_DCLKDIV: | |
17a52fd6 MB |
1009 | reg = snd_soc_read(codec, WM8960_CLOCK2) & 0x03f; |
1010 | snd_soc_write(codec, WM8960_CLOCK2, reg | div); | |
f2644a2c MB |
1011 | break; |
1012 | case WM8960_TOCLKSEL: | |
17a52fd6 MB |
1013 | reg = snd_soc_read(codec, WM8960_ADDCTL1) & 0x1fd; |
1014 | snd_soc_write(codec, WM8960_ADDCTL1, reg | div); | |
f2644a2c MB |
1015 | break; |
1016 | default: | |
1017 | return -EINVAL; | |
1018 | } | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
f0fba2ad LG |
1023 | static int wm8960_set_bias_level(struct snd_soc_codec *codec, |
1024 | enum snd_soc_bias_level level) | |
1025 | { | |
1026 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
1027 | ||
1028 | return wm8960->set_bias_level(codec, level); | |
1029 | } | |
1030 | ||
0e50b51a ZW |
1031 | static int wm8960_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, |
1032 | unsigned int freq, int dir) | |
1033 | { | |
1034 | struct snd_soc_codec *codec = dai->codec; | |
1035 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); | |
1036 | ||
1037 | switch (clk_id) { | |
1038 | case WM8960_SYSCLK_MCLK: | |
1039 | snd_soc_update_bits(codec, WM8960_CLOCK1, | |
1040 | 0x1, WM8960_SYSCLK_MCLK); | |
1041 | break; | |
1042 | case WM8960_SYSCLK_PLL: | |
1043 | snd_soc_update_bits(codec, WM8960_CLOCK1, | |
1044 | 0x1, WM8960_SYSCLK_PLL); | |
1045 | break; | |
1046 | default: | |
1047 | return -EINVAL; | |
1048 | } | |
1049 | ||
1050 | wm8960->sysclk = freq; | |
1051 | ||
1052 | return 0; | |
1053 | } | |
1054 | ||
f2644a2c MB |
1055 | #define WM8960_RATES SNDRV_PCM_RATE_8000_48000 |
1056 | ||
1057 | #define WM8960_FORMATS \ | |
1058 | (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ | |
7a8c7867 | 1059 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
f2644a2c | 1060 | |
85e7652d | 1061 | static const struct snd_soc_dai_ops wm8960_dai_ops = { |
f2644a2c MB |
1062 | .hw_params = wm8960_hw_params, |
1063 | .digital_mute = wm8960_mute, | |
1064 | .set_fmt = wm8960_set_dai_fmt, | |
1065 | .set_clkdiv = wm8960_set_dai_clkdiv, | |
1066 | .set_pll = wm8960_set_dai_pll, | |
0e50b51a | 1067 | .set_sysclk = wm8960_set_dai_sysclk, |
f2644a2c MB |
1068 | }; |
1069 | ||
f0fba2ad LG |
1070 | static struct snd_soc_dai_driver wm8960_dai = { |
1071 | .name = "wm8960-hifi", | |
f2644a2c MB |
1072 | .playback = { |
1073 | .stream_name = "Playback", | |
1074 | .channels_min = 1, | |
1075 | .channels_max = 2, | |
1076 | .rates = WM8960_RATES, | |
1077 | .formats = WM8960_FORMATS,}, | |
1078 | .capture = { | |
1079 | .stream_name = "Capture", | |
1080 | .channels_min = 1, | |
1081 | .channels_max = 2, | |
1082 | .rates = WM8960_RATES, | |
1083 | .formats = WM8960_FORMATS,}, | |
1084 | .ops = &wm8960_dai_ops, | |
1085 | .symmetric_rates = 1, | |
1086 | }; | |
f2644a2c | 1087 | |
f0fba2ad | 1088 | static int wm8960_probe(struct snd_soc_codec *codec) |
f2644a2c | 1089 | { |
f0fba2ad | 1090 | struct wm8960_priv *wm8960 = snd_soc_codec_get_drvdata(codec); |
e2280c90 | 1091 | struct wm8960_data *pdata = &wm8960->pdata; |
f2644a2c | 1092 | |
e2280c90 ZW |
1093 | if (pdata->capless) |
1094 | wm8960->set_bias_level = wm8960_set_bias_level_capless; | |
1095 | else | |
1096 | wm8960->set_bias_level = wm8960_set_bias_level_out3; | |
f2644a2c | 1097 | |
022658be | 1098 | snd_soc_add_codec_controls(codec, wm8960_snd_controls, |
f0fba2ad LG |
1099 | ARRAY_SIZE(wm8960_snd_controls)); |
1100 | wm8960_add_widgets(codec); | |
f2644a2c MB |
1101 | |
1102 | return 0; | |
1103 | } | |
1104 | ||
f0fba2ad LG |
1105 | static struct snd_soc_codec_driver soc_codec_dev_wm8960 = { |
1106 | .probe = wm8960_probe, | |
f0fba2ad | 1107 | .set_bias_level = wm8960_set_bias_level, |
0a87a6e1 | 1108 | .suspend_bias_off = true, |
0ebe36c6 MB |
1109 | }; |
1110 | ||
1111 | static const struct regmap_config wm8960_regmap = { | |
1112 | .reg_bits = 7, | |
1113 | .val_bits = 9, | |
1114 | .max_register = WM8960_PLL4, | |
1115 | ||
1116 | .reg_defaults = wm8960_reg_defaults, | |
1117 | .num_reg_defaults = ARRAY_SIZE(wm8960_reg_defaults), | |
1118 | .cache_type = REGCACHE_RBTREE, | |
1119 | ||
1120 | .volatile_reg = wm8960_volatile, | |
f0fba2ad LG |
1121 | }; |
1122 | ||
e2280c90 ZW |
1123 | static void wm8960_set_pdata_from_of(struct i2c_client *i2c, |
1124 | struct wm8960_data *pdata) | |
1125 | { | |
1126 | const struct device_node *np = i2c->dev.of_node; | |
1127 | ||
1128 | if (of_property_read_bool(np, "wlf,capless")) | |
1129 | pdata->capless = true; | |
1130 | ||
1131 | if (of_property_read_bool(np, "wlf,shared-lrclk")) | |
1132 | pdata->shared_lrclk = true; | |
1133 | } | |
1134 | ||
7a79e94e BP |
1135 | static int wm8960_i2c_probe(struct i2c_client *i2c, |
1136 | const struct i2c_device_id *id) | |
f2644a2c | 1137 | { |
37061631 | 1138 | struct wm8960_data *pdata = dev_get_platdata(&i2c->dev); |
f2644a2c | 1139 | struct wm8960_priv *wm8960; |
f0fba2ad | 1140 | int ret; |
f2644a2c | 1141 | |
b9791c01 MB |
1142 | wm8960 = devm_kzalloc(&i2c->dev, sizeof(struct wm8960_priv), |
1143 | GFP_KERNEL); | |
f2644a2c MB |
1144 | if (wm8960 == NULL) |
1145 | return -ENOMEM; | |
1146 | ||
75aa8868 ZW |
1147 | wm8960->mclk = devm_clk_get(&i2c->dev, "mclk"); |
1148 | if (IS_ERR(wm8960->mclk)) { | |
1149 | if (PTR_ERR(wm8960->mclk) == -EPROBE_DEFER) | |
1150 | return -EPROBE_DEFER; | |
1151 | } | |
1152 | ||
c5e6f5fa | 1153 | wm8960->regmap = devm_regmap_init_i2c(i2c, &wm8960_regmap); |
0ebe36c6 MB |
1154 | if (IS_ERR(wm8960->regmap)) |
1155 | return PTR_ERR(wm8960->regmap); | |
1156 | ||
e2280c90 ZW |
1157 | if (pdata) |
1158 | memcpy(&wm8960->pdata, pdata, sizeof(struct wm8960_data)); | |
1159 | else if (i2c->dev.of_node) | |
1160 | wm8960_set_pdata_from_of(i2c, &wm8960->pdata); | |
1161 | ||
3ad5e861 ZW |
1162 | ret = wm8960_reset(wm8960->regmap); |
1163 | if (ret != 0) { | |
1164 | dev_err(&i2c->dev, "Failed to issue reset\n"); | |
1165 | return ret; | |
1166 | } | |
1167 | ||
1168 | if (wm8960->pdata.shared_lrclk) { | |
37061631 MB |
1169 | ret = regmap_update_bits(wm8960->regmap, WM8960_ADDCTL2, |
1170 | 0x4, 0x4); | |
1171 | if (ret != 0) { | |
1172 | dev_err(&i2c->dev, "Failed to enable LRCM: %d\n", | |
1173 | ret); | |
1174 | return ret; | |
1175 | } | |
1176 | } | |
1177 | ||
3ad5e861 ZW |
1178 | /* Latch the update bits */ |
1179 | regmap_update_bits(wm8960->regmap, WM8960_LINVOL, 0x100, 0x100); | |
1180 | regmap_update_bits(wm8960->regmap, WM8960_RINVOL, 0x100, 0x100); | |
1181 | regmap_update_bits(wm8960->regmap, WM8960_LADC, 0x100, 0x100); | |
1182 | regmap_update_bits(wm8960->regmap, WM8960_RADC, 0x100, 0x100); | |
1183 | regmap_update_bits(wm8960->regmap, WM8960_LDAC, 0x100, 0x100); | |
1184 | regmap_update_bits(wm8960->regmap, WM8960_RDAC, 0x100, 0x100); | |
1185 | regmap_update_bits(wm8960->regmap, WM8960_LOUT1, 0x100, 0x100); | |
1186 | regmap_update_bits(wm8960->regmap, WM8960_ROUT1, 0x100, 0x100); | |
1187 | regmap_update_bits(wm8960->regmap, WM8960_LOUT2, 0x100, 0x100); | |
1188 | regmap_update_bits(wm8960->regmap, WM8960_ROUT2, 0x100, 0x100); | |
1189 | ||
f2644a2c | 1190 | i2c_set_clientdata(i2c, wm8960); |
f2644a2c | 1191 | |
f0fba2ad LG |
1192 | ret = snd_soc_register_codec(&i2c->dev, |
1193 | &soc_codec_dev_wm8960, &wm8960_dai, 1); | |
b9791c01 | 1194 | |
f0fba2ad | 1195 | return ret; |
f2644a2c MB |
1196 | } |
1197 | ||
7a79e94e | 1198 | static int wm8960_i2c_remove(struct i2c_client *client) |
f2644a2c | 1199 | { |
f0fba2ad | 1200 | snd_soc_unregister_codec(&client->dev); |
f2644a2c MB |
1201 | return 0; |
1202 | } | |
1203 | ||
1204 | static const struct i2c_device_id wm8960_i2c_id[] = { | |
1205 | { "wm8960", 0 }, | |
1206 | { } | |
1207 | }; | |
1208 | MODULE_DEVICE_TABLE(i2c, wm8960_i2c_id); | |
1209 | ||
e2280c90 ZW |
1210 | static const struct of_device_id wm8960_of_match[] = { |
1211 | { .compatible = "wlf,wm8960", }, | |
1212 | { } | |
1213 | }; | |
1214 | MODULE_DEVICE_TABLE(of, wm8960_of_match); | |
1215 | ||
f2644a2c MB |
1216 | static struct i2c_driver wm8960_i2c_driver = { |
1217 | .driver = { | |
091edccf | 1218 | .name = "wm8960", |
f2644a2c | 1219 | .owner = THIS_MODULE, |
e2280c90 | 1220 | .of_match_table = wm8960_of_match, |
f2644a2c MB |
1221 | }, |
1222 | .probe = wm8960_i2c_probe, | |
7a79e94e | 1223 | .remove = wm8960_i2c_remove, |
f2644a2c MB |
1224 | .id_table = wm8960_i2c_id, |
1225 | }; | |
1226 | ||
3c010e60 | 1227 | module_i2c_driver(wm8960_i2c_driver); |
f2644a2c | 1228 | |
f2644a2c MB |
1229 | MODULE_DESCRIPTION("ASoC WM8960 driver"); |
1230 | MODULE_AUTHOR("Liam Girdwood"); | |
1231 | MODULE_LICENSE("GPL"); |