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1 | /* |
2 | * wm8961.h -- WM8961 Soc Audio driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef _WM8961_H | |
10 | #define _WM8961_H | |
11 | ||
12 | #include <sound/soc.h> | |
13 | ||
14 | extern struct snd_soc_codec_device soc_codec_dev_wm8961; | |
15 | extern struct snd_soc_dai wm8961_dai; | |
16 | ||
17 | #define WM8961_BCLK 1 | |
18 | #define WM8961_LRCLK 2 | |
19 | ||
20 | #define WM8961_BCLK_DIV_1 0 | |
21 | #define WM8961_BCLK_DIV_1_5 1 | |
22 | #define WM8961_BCLK_DIV_2 2 | |
23 | #define WM8961_BCLK_DIV_3 3 | |
24 | #define WM8961_BCLK_DIV_4 4 | |
25 | #define WM8961_BCLK_DIV_5_5 5 | |
26 | #define WM8961_BCLK_DIV_6 6 | |
27 | #define WM8961_BCLK_DIV_8 7 | |
28 | #define WM8961_BCLK_DIV_11 8 | |
29 | #define WM8961_BCLK_DIV_12 9 | |
30 | #define WM8961_BCLK_DIV_16 10 | |
31 | #define WM8961_BCLK_DIV_24 11 | |
32 | #define WM8961_BCLK_DIV_32 13 | |
33 | ||
34 | ||
35 | /* | |
36 | * Register values. | |
37 | */ | |
38 | #define WM8961_LEFT_INPUT_VOLUME 0x00 | |
39 | #define WM8961_RIGHT_INPUT_VOLUME 0x01 | |
40 | #define WM8961_LOUT1_VOLUME 0x02 | |
41 | #define WM8961_ROUT1_VOLUME 0x03 | |
42 | #define WM8961_CLOCKING1 0x04 | |
43 | #define WM8961_ADC_DAC_CONTROL_1 0x05 | |
44 | #define WM8961_ADC_DAC_CONTROL_2 0x06 | |
45 | #define WM8961_AUDIO_INTERFACE_0 0x07 | |
46 | #define WM8961_CLOCKING2 0x08 | |
47 | #define WM8961_AUDIO_INTERFACE_1 0x09 | |
48 | #define WM8961_LEFT_DAC_VOLUME 0x0A | |
49 | #define WM8961_RIGHT_DAC_VOLUME 0x0B | |
50 | #define WM8961_AUDIO_INTERFACE_2 0x0E | |
51 | #define WM8961_SOFTWARE_RESET 0x0F | |
52 | #define WM8961_ALC1 0x11 | |
53 | #define WM8961_ALC2 0x12 | |
54 | #define WM8961_ALC3 0x13 | |
55 | #define WM8961_NOISE_GATE 0x14 | |
56 | #define WM8961_LEFT_ADC_VOLUME 0x15 | |
57 | #define WM8961_RIGHT_ADC_VOLUME 0x16 | |
58 | #define WM8961_ADDITIONAL_CONTROL_1 0x17 | |
59 | #define WM8961_ADDITIONAL_CONTROL_2 0x18 | |
60 | #define WM8961_PWR_MGMT_1 0x19 | |
61 | #define WM8961_PWR_MGMT_2 0x1A | |
62 | #define WM8961_ADDITIONAL_CONTROL_3 0x1B | |
63 | #define WM8961_ANTI_POP 0x1C | |
64 | #define WM8961_CLOCKING_3 0x1E | |
65 | #define WM8961_ADCL_SIGNAL_PATH 0x20 | |
66 | #define WM8961_ADCR_SIGNAL_PATH 0x21 | |
67 | #define WM8961_LOUT2_VOLUME 0x28 | |
68 | #define WM8961_ROUT2_VOLUME 0x29 | |
69 | #define WM8961_PWR_MGMT_3 0x2F | |
70 | #define WM8961_ADDITIONAL_CONTROL_4 0x30 | |
71 | #define WM8961_CLASS_D_CONTROL_1 0x31 | |
72 | #define WM8961_CLASS_D_CONTROL_2 0x33 | |
73 | #define WM8961_CLOCKING_4 0x38 | |
74 | #define WM8961_DSP_SIDETONE_0 0x39 | |
75 | #define WM8961_DSP_SIDETONE_1 0x3A | |
76 | #define WM8961_DC_SERVO_0 0x3C | |
77 | #define WM8961_DC_SERVO_1 0x3D | |
78 | #define WM8961_DC_SERVO_3 0x3F | |
79 | #define WM8961_DC_SERVO_5 0x41 | |
80 | #define WM8961_ANALOGUE_PGA_BIAS 0x44 | |
81 | #define WM8961_ANALOGUE_HP_0 0x45 | |
82 | #define WM8961_ANALOGUE_HP_2 0x47 | |
83 | #define WM8961_CHARGE_PUMP_1 0x48 | |
84 | #define WM8961_CHARGE_PUMP_B 0x52 | |
85 | #define WM8961_WRITE_SEQUENCER_1 0x57 | |
86 | #define WM8961_WRITE_SEQUENCER_2 0x58 | |
87 | #define WM8961_WRITE_SEQUENCER_3 0x59 | |
88 | #define WM8961_WRITE_SEQUENCER_4 0x5A | |
89 | #define WM8961_WRITE_SEQUENCER_5 0x5B | |
90 | #define WM8961_WRITE_SEQUENCER_6 0x5C | |
91 | #define WM8961_WRITE_SEQUENCER_7 0x5D | |
92 | #define WM8961_GENERAL_TEST_1 0xFC | |
93 | ||
94 | ||
95 | /* | |
96 | * Field Definitions. | |
97 | */ | |
98 | ||
99 | /* | |
100 | * R0 (0x00) - Left Input volume | |
101 | */ | |
102 | #define WM8961_IPVU 0x0100 /* IPVU */ | |
103 | #define WM8961_IPVU_MASK 0x0100 /* IPVU */ | |
104 | #define WM8961_IPVU_SHIFT 8 /* IPVU */ | |
105 | #define WM8961_IPVU_WIDTH 1 /* IPVU */ | |
106 | #define WM8961_LINMUTE 0x0080 /* LINMUTE */ | |
107 | #define WM8961_LINMUTE_MASK 0x0080 /* LINMUTE */ | |
108 | #define WM8961_LINMUTE_SHIFT 7 /* LINMUTE */ | |
109 | #define WM8961_LINMUTE_WIDTH 1 /* LINMUTE */ | |
110 | #define WM8961_LIZC 0x0040 /* LIZC */ | |
111 | #define WM8961_LIZC_MASK 0x0040 /* LIZC */ | |
112 | #define WM8961_LIZC_SHIFT 6 /* LIZC */ | |
113 | #define WM8961_LIZC_WIDTH 1 /* LIZC */ | |
114 | #define WM8961_LINVOL_MASK 0x003F /* LINVOL - [5:0] */ | |
115 | #define WM8961_LINVOL_SHIFT 0 /* LINVOL - [5:0] */ | |
116 | #define WM8961_LINVOL_WIDTH 6 /* LINVOL - [5:0] */ | |
117 | ||
118 | /* | |
119 | * R1 (0x01) - Right Input volume | |
120 | */ | |
121 | #define WM8961_DEVICE_ID_MASK 0xF000 /* DEVICE_ID - [15:12] */ | |
122 | #define WM8961_DEVICE_ID_SHIFT 12 /* DEVICE_ID - [15:12] */ | |
123 | #define WM8961_DEVICE_ID_WIDTH 4 /* DEVICE_ID - [15:12] */ | |
124 | #define WM8961_CHIP_REV_MASK 0x0E00 /* CHIP_REV - [11:9] */ | |
125 | #define WM8961_CHIP_REV_SHIFT 9 /* CHIP_REV - [11:9] */ | |
126 | #define WM8961_CHIP_REV_WIDTH 3 /* CHIP_REV - [11:9] */ | |
127 | #define WM8961_IPVU 0x0100 /* IPVU */ | |
128 | #define WM8961_IPVU_MASK 0x0100 /* IPVU */ | |
129 | #define WM8961_IPVU_SHIFT 8 /* IPVU */ | |
130 | #define WM8961_IPVU_WIDTH 1 /* IPVU */ | |
131 | #define WM8961_RINMUTE 0x0080 /* RINMUTE */ | |
132 | #define WM8961_RINMUTE_MASK 0x0080 /* RINMUTE */ | |
133 | #define WM8961_RINMUTE_SHIFT 7 /* RINMUTE */ | |
134 | #define WM8961_RINMUTE_WIDTH 1 /* RINMUTE */ | |
135 | #define WM8961_RIZC 0x0040 /* RIZC */ | |
136 | #define WM8961_RIZC_MASK 0x0040 /* RIZC */ | |
137 | #define WM8961_RIZC_SHIFT 6 /* RIZC */ | |
138 | #define WM8961_RIZC_WIDTH 1 /* RIZC */ | |
139 | #define WM8961_RINVOL_MASK 0x003F /* RINVOL - [5:0] */ | |
140 | #define WM8961_RINVOL_SHIFT 0 /* RINVOL - [5:0] */ | |
141 | #define WM8961_RINVOL_WIDTH 6 /* RINVOL - [5:0] */ | |
142 | ||
143 | /* | |
144 | * R2 (0x02) - LOUT1 volume | |
145 | */ | |
146 | #define WM8961_OUT1VU 0x0100 /* OUT1VU */ | |
147 | #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ | |
148 | #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ | |
149 | #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ | |
150 | #define WM8961_LO1ZC 0x0080 /* LO1ZC */ | |
151 | #define WM8961_LO1ZC_MASK 0x0080 /* LO1ZC */ | |
152 | #define WM8961_LO1ZC_SHIFT 7 /* LO1ZC */ | |
153 | #define WM8961_LO1ZC_WIDTH 1 /* LO1ZC */ | |
154 | #define WM8961_LOUT1VOL_MASK 0x007F /* LOUT1VOL - [6:0] */ | |
155 | #define WM8961_LOUT1VOL_SHIFT 0 /* LOUT1VOL - [6:0] */ | |
156 | #define WM8961_LOUT1VOL_WIDTH 7 /* LOUT1VOL - [6:0] */ | |
157 | ||
158 | /* | |
159 | * R3 (0x03) - ROUT1 volume | |
160 | */ | |
161 | #define WM8961_OUT1VU 0x0100 /* OUT1VU */ | |
162 | #define WM8961_OUT1VU_MASK 0x0100 /* OUT1VU */ | |
163 | #define WM8961_OUT1VU_SHIFT 8 /* OUT1VU */ | |
164 | #define WM8961_OUT1VU_WIDTH 1 /* OUT1VU */ | |
165 | #define WM8961_RO1ZC 0x0080 /* RO1ZC */ | |
166 | #define WM8961_RO1ZC_MASK 0x0080 /* RO1ZC */ | |
167 | #define WM8961_RO1ZC_SHIFT 7 /* RO1ZC */ | |
168 | #define WM8961_RO1ZC_WIDTH 1 /* RO1ZC */ | |
169 | #define WM8961_ROUT1VOL_MASK 0x007F /* ROUT1VOL - [6:0] */ | |
170 | #define WM8961_ROUT1VOL_SHIFT 0 /* ROUT1VOL - [6:0] */ | |
171 | #define WM8961_ROUT1VOL_WIDTH 7 /* ROUT1VOL - [6:0] */ | |
172 | ||
173 | /* | |
174 | * R4 (0x04) - Clocking1 | |
175 | */ | |
176 | #define WM8961_ADCDIV_MASK 0x01C0 /* ADCDIV - [8:6] */ | |
177 | #define WM8961_ADCDIV_SHIFT 6 /* ADCDIV - [8:6] */ | |
178 | #define WM8961_ADCDIV_WIDTH 3 /* ADCDIV - [8:6] */ | |
179 | #define WM8961_DACDIV_MASK 0x0038 /* DACDIV - [5:3] */ | |
180 | #define WM8961_DACDIV_SHIFT 3 /* DACDIV - [5:3] */ | |
181 | #define WM8961_DACDIV_WIDTH 3 /* DACDIV - [5:3] */ | |
182 | #define WM8961_MCLKDIV 0x0004 /* MCLKDIV */ | |
183 | #define WM8961_MCLKDIV_MASK 0x0004 /* MCLKDIV */ | |
184 | #define WM8961_MCLKDIV_SHIFT 2 /* MCLKDIV */ | |
185 | #define WM8961_MCLKDIV_WIDTH 1 /* MCLKDIV */ | |
186 | ||
187 | /* | |
188 | * R5 (0x05) - ADC & DAC Control 1 | |
189 | */ | |
190 | #define WM8961_ADCPOL_MASK 0x0060 /* ADCPOL - [6:5] */ | |
191 | #define WM8961_ADCPOL_SHIFT 5 /* ADCPOL - [6:5] */ | |
192 | #define WM8961_ADCPOL_WIDTH 2 /* ADCPOL - [6:5] */ | |
193 | #define WM8961_DACMU 0x0008 /* DACMU */ | |
194 | #define WM8961_DACMU_MASK 0x0008 /* DACMU */ | |
195 | #define WM8961_DACMU_SHIFT 3 /* DACMU */ | |
196 | #define WM8961_DACMU_WIDTH 1 /* DACMU */ | |
197 | #define WM8961_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ | |
198 | #define WM8961_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ | |
199 | #define WM8961_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ | |
200 | #define WM8961_ADCHPD 0x0001 /* ADCHPD */ | |
201 | #define WM8961_ADCHPD_MASK 0x0001 /* ADCHPD */ | |
202 | #define WM8961_ADCHPD_SHIFT 0 /* ADCHPD */ | |
203 | #define WM8961_ADCHPD_WIDTH 1 /* ADCHPD */ | |
204 | ||
205 | /* | |
206 | * R6 (0x06) - ADC & DAC Control 2 | |
207 | */ | |
208 | #define WM8961_ADC_HPF_CUT_MASK 0x0180 /* ADC_HPF_CUT - [8:7] */ | |
209 | #define WM8961_ADC_HPF_CUT_SHIFT 7 /* ADC_HPF_CUT - [8:7] */ | |
210 | #define WM8961_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [8:7] */ | |
211 | #define WM8961_DACPOL_MASK 0x0060 /* DACPOL - [6:5] */ | |
212 | #define WM8961_DACPOL_SHIFT 5 /* DACPOL - [6:5] */ | |
213 | #define WM8961_DACPOL_WIDTH 2 /* DACPOL - [6:5] */ | |
214 | #define WM8961_DACSMM 0x0008 /* DACSMM */ | |
215 | #define WM8961_DACSMM_MASK 0x0008 /* DACSMM */ | |
216 | #define WM8961_DACSMM_SHIFT 3 /* DACSMM */ | |
217 | #define WM8961_DACSMM_WIDTH 1 /* DACSMM */ | |
218 | #define WM8961_DACMR 0x0004 /* DACMR */ | |
219 | #define WM8961_DACMR_MASK 0x0004 /* DACMR */ | |
220 | #define WM8961_DACMR_SHIFT 2 /* DACMR */ | |
221 | #define WM8961_DACMR_WIDTH 1 /* DACMR */ | |
222 | #define WM8961_DACSLOPE 0x0002 /* DACSLOPE */ | |
223 | #define WM8961_DACSLOPE_MASK 0x0002 /* DACSLOPE */ | |
224 | #define WM8961_DACSLOPE_SHIFT 1 /* DACSLOPE */ | |
225 | #define WM8961_DACSLOPE_WIDTH 1 /* DACSLOPE */ | |
226 | #define WM8961_DAC_OSR128 0x0001 /* DAC_OSR128 */ | |
227 | #define WM8961_DAC_OSR128_MASK 0x0001 /* DAC_OSR128 */ | |
228 | #define WM8961_DAC_OSR128_SHIFT 0 /* DAC_OSR128 */ | |
229 | #define WM8961_DAC_OSR128_WIDTH 1 /* DAC_OSR128 */ | |
230 | ||
231 | /* | |
232 | * R7 (0x07) - Audio Interface 0 | |
233 | */ | |
234 | #define WM8961_ALRSWAP 0x0100 /* ALRSWAP */ | |
235 | #define WM8961_ALRSWAP_MASK 0x0100 /* ALRSWAP */ | |
236 | #define WM8961_ALRSWAP_SHIFT 8 /* ALRSWAP */ | |
237 | #define WM8961_ALRSWAP_WIDTH 1 /* ALRSWAP */ | |
238 | #define WM8961_BCLKINV 0x0080 /* BCLKINV */ | |
239 | #define WM8961_BCLKINV_MASK 0x0080 /* BCLKINV */ | |
240 | #define WM8961_BCLKINV_SHIFT 7 /* BCLKINV */ | |
241 | #define WM8961_BCLKINV_WIDTH 1 /* BCLKINV */ | |
242 | #define WM8961_MS 0x0040 /* MS */ | |
243 | #define WM8961_MS_MASK 0x0040 /* MS */ | |
244 | #define WM8961_MS_SHIFT 6 /* MS */ | |
245 | #define WM8961_MS_WIDTH 1 /* MS */ | |
246 | #define WM8961_DLRSWAP 0x0020 /* DLRSWAP */ | |
247 | #define WM8961_DLRSWAP_MASK 0x0020 /* DLRSWAP */ | |
248 | #define WM8961_DLRSWAP_SHIFT 5 /* DLRSWAP */ | |
249 | #define WM8961_DLRSWAP_WIDTH 1 /* DLRSWAP */ | |
250 | #define WM8961_LRP 0x0010 /* LRP */ | |
251 | #define WM8961_LRP_MASK 0x0010 /* LRP */ | |
252 | #define WM8961_LRP_SHIFT 4 /* LRP */ | |
253 | #define WM8961_LRP_WIDTH 1 /* LRP */ | |
254 | #define WM8961_WL_MASK 0x000C /* WL - [3:2] */ | |
255 | #define WM8961_WL_SHIFT 2 /* WL - [3:2] */ | |
256 | #define WM8961_WL_WIDTH 2 /* WL - [3:2] */ | |
257 | #define WM8961_FORMAT_MASK 0x0003 /* FORMAT - [1:0] */ | |
258 | #define WM8961_FORMAT_SHIFT 0 /* FORMAT - [1:0] */ | |
259 | #define WM8961_FORMAT_WIDTH 2 /* FORMAT - [1:0] */ | |
260 | ||
261 | /* | |
262 | * R8 (0x08) - Clocking2 | |
263 | */ | |
264 | #define WM8961_DCLKDIV_MASK 0x01C0 /* DCLKDIV - [8:6] */ | |
265 | #define WM8961_DCLKDIV_SHIFT 6 /* DCLKDIV - [8:6] */ | |
266 | #define WM8961_DCLKDIV_WIDTH 3 /* DCLKDIV - [8:6] */ | |
267 | #define WM8961_CLK_SYS_ENA 0x0020 /* CLK_SYS_ENA */ | |
268 | #define WM8961_CLK_SYS_ENA_MASK 0x0020 /* CLK_SYS_ENA */ | |
269 | #define WM8961_CLK_SYS_ENA_SHIFT 5 /* CLK_SYS_ENA */ | |
270 | #define WM8961_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ | |
271 | #define WM8961_CLK_DSP_ENA 0x0010 /* CLK_DSP_ENA */ | |
272 | #define WM8961_CLK_DSP_ENA_MASK 0x0010 /* CLK_DSP_ENA */ | |
273 | #define WM8961_CLK_DSP_ENA_SHIFT 4 /* CLK_DSP_ENA */ | |
274 | #define WM8961_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ | |
275 | #define WM8961_BCLKDIV_MASK 0x000F /* BCLKDIV - [3:0] */ | |
276 | #define WM8961_BCLKDIV_SHIFT 0 /* BCLKDIV - [3:0] */ | |
277 | #define WM8961_BCLKDIV_WIDTH 4 /* BCLKDIV - [3:0] */ | |
278 | ||
279 | /* | |
280 | * R9 (0x09) - Audio Interface 1 | |
281 | */ | |
282 | #define WM8961_DACCOMP_MASK 0x0018 /* DACCOMP - [4:3] */ | |
283 | #define WM8961_DACCOMP_SHIFT 3 /* DACCOMP - [4:3] */ | |
284 | #define WM8961_DACCOMP_WIDTH 2 /* DACCOMP - [4:3] */ | |
285 | #define WM8961_ADCCOMP_MASK 0x0006 /* ADCCOMP - [2:1] */ | |
286 | #define WM8961_ADCCOMP_SHIFT 1 /* ADCCOMP - [2:1] */ | |
287 | #define WM8961_ADCCOMP_WIDTH 2 /* ADCCOMP - [2:1] */ | |
288 | #define WM8961_LOOPBACK 0x0001 /* LOOPBACK */ | |
289 | #define WM8961_LOOPBACK_MASK 0x0001 /* LOOPBACK */ | |
290 | #define WM8961_LOOPBACK_SHIFT 0 /* LOOPBACK */ | |
291 | #define WM8961_LOOPBACK_WIDTH 1 /* LOOPBACK */ | |
292 | ||
293 | /* | |
294 | * R10 (0x0A) - Left DAC volume | |
295 | */ | |
296 | #define WM8961_DACVU 0x0100 /* DACVU */ | |
297 | #define WM8961_DACVU_MASK 0x0100 /* DACVU */ | |
298 | #define WM8961_DACVU_SHIFT 8 /* DACVU */ | |
299 | #define WM8961_DACVU_WIDTH 1 /* DACVU */ | |
300 | #define WM8961_LDACVOL_MASK 0x00FF /* LDACVOL - [7:0] */ | |
301 | #define WM8961_LDACVOL_SHIFT 0 /* LDACVOL - [7:0] */ | |
302 | #define WM8961_LDACVOL_WIDTH 8 /* LDACVOL - [7:0] */ | |
303 | ||
304 | /* | |
305 | * R11 (0x0B) - Right DAC volume | |
306 | */ | |
307 | #define WM8961_DACVU 0x0100 /* DACVU */ | |
308 | #define WM8961_DACVU_MASK 0x0100 /* DACVU */ | |
309 | #define WM8961_DACVU_SHIFT 8 /* DACVU */ | |
310 | #define WM8961_DACVU_WIDTH 1 /* DACVU */ | |
311 | #define WM8961_RDACVOL_MASK 0x00FF /* RDACVOL - [7:0] */ | |
312 | #define WM8961_RDACVOL_SHIFT 0 /* RDACVOL - [7:0] */ | |
313 | #define WM8961_RDACVOL_WIDTH 8 /* RDACVOL - [7:0] */ | |
314 | ||
315 | /* | |
316 | * R14 (0x0E) - Audio Interface 2 | |
317 | */ | |
318 | #define WM8961_LRCLK_RATE_MASK 0x01FF /* LRCLK_RATE - [8:0] */ | |
319 | #define WM8961_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [8:0] */ | |
320 | #define WM8961_LRCLK_RATE_WIDTH 9 /* LRCLK_RATE - [8:0] */ | |
321 | ||
322 | /* | |
323 | * R15 (0x0F) - Software Reset | |
324 | */ | |
325 | #define WM8961_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */ | |
326 | #define WM8961_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */ | |
327 | #define WM8961_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */ | |
328 | ||
329 | /* | |
330 | * R17 (0x11) - ALC1 | |
331 | */ | |
332 | #define WM8961_ALCSEL_MASK 0x0180 /* ALCSEL - [8:7] */ | |
333 | #define WM8961_ALCSEL_SHIFT 7 /* ALCSEL - [8:7] */ | |
334 | #define WM8961_ALCSEL_WIDTH 2 /* ALCSEL - [8:7] */ | |
335 | #define WM8961_MAXGAIN_MASK 0x0070 /* MAXGAIN - [6:4] */ | |
336 | #define WM8961_MAXGAIN_SHIFT 4 /* MAXGAIN - [6:4] */ | |
337 | #define WM8961_MAXGAIN_WIDTH 3 /* MAXGAIN - [6:4] */ | |
338 | #define WM8961_ALCL_MASK 0x000F /* ALCL - [3:0] */ | |
339 | #define WM8961_ALCL_SHIFT 0 /* ALCL - [3:0] */ | |
340 | #define WM8961_ALCL_WIDTH 4 /* ALCL - [3:0] */ | |
341 | ||
342 | /* | |
343 | * R18 (0x12) - ALC2 | |
344 | */ | |
345 | #define WM8961_ALCZC 0x0080 /* ALCZC */ | |
346 | #define WM8961_ALCZC_MASK 0x0080 /* ALCZC */ | |
347 | #define WM8961_ALCZC_SHIFT 7 /* ALCZC */ | |
348 | #define WM8961_ALCZC_WIDTH 1 /* ALCZC */ | |
349 | #define WM8961_MINGAIN_MASK 0x0070 /* MINGAIN - [6:4] */ | |
350 | #define WM8961_MINGAIN_SHIFT 4 /* MINGAIN - [6:4] */ | |
351 | #define WM8961_MINGAIN_WIDTH 3 /* MINGAIN - [6:4] */ | |
352 | #define WM8961_HLD_MASK 0x000F /* HLD - [3:0] */ | |
353 | #define WM8961_HLD_SHIFT 0 /* HLD - [3:0] */ | |
354 | #define WM8961_HLD_WIDTH 4 /* HLD - [3:0] */ | |
355 | ||
356 | /* | |
357 | * R19 (0x13) - ALC3 | |
358 | */ | |
359 | #define WM8961_ALCMODE 0x0100 /* ALCMODE */ | |
360 | #define WM8961_ALCMODE_MASK 0x0100 /* ALCMODE */ | |
361 | #define WM8961_ALCMODE_SHIFT 8 /* ALCMODE */ | |
362 | #define WM8961_ALCMODE_WIDTH 1 /* ALCMODE */ | |
363 | #define WM8961_DCY_MASK 0x00F0 /* DCY - [7:4] */ | |
364 | #define WM8961_DCY_SHIFT 4 /* DCY - [7:4] */ | |
365 | #define WM8961_DCY_WIDTH 4 /* DCY - [7:4] */ | |
366 | #define WM8961_ATK_MASK 0x000F /* ATK - [3:0] */ | |
367 | #define WM8961_ATK_SHIFT 0 /* ATK - [3:0] */ | |
368 | #define WM8961_ATK_WIDTH 4 /* ATK - [3:0] */ | |
369 | ||
370 | /* | |
371 | * R20 (0x14) - Noise Gate | |
372 | */ | |
373 | #define WM8961_NGTH_MASK 0x00F8 /* NGTH - [7:3] */ | |
374 | #define WM8961_NGTH_SHIFT 3 /* NGTH - [7:3] */ | |
375 | #define WM8961_NGTH_WIDTH 5 /* NGTH - [7:3] */ | |
376 | #define WM8961_NGG 0x0002 /* NGG */ | |
377 | #define WM8961_NGG_MASK 0x0002 /* NGG */ | |
378 | #define WM8961_NGG_SHIFT 1 /* NGG */ | |
379 | #define WM8961_NGG_WIDTH 1 /* NGG */ | |
380 | #define WM8961_NGAT 0x0001 /* NGAT */ | |
381 | #define WM8961_NGAT_MASK 0x0001 /* NGAT */ | |
382 | #define WM8961_NGAT_SHIFT 0 /* NGAT */ | |
383 | #define WM8961_NGAT_WIDTH 1 /* NGAT */ | |
384 | ||
385 | /* | |
386 | * R21 (0x15) - Left ADC volume | |
387 | */ | |
388 | #define WM8961_ADCVU 0x0100 /* ADCVU */ | |
389 | #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ | |
390 | #define WM8961_ADCVU_SHIFT 8 /* ADCVU */ | |
391 | #define WM8961_ADCVU_WIDTH 1 /* ADCVU */ | |
392 | #define WM8961_LADCVOL_MASK 0x00FF /* LADCVOL - [7:0] */ | |
393 | #define WM8961_LADCVOL_SHIFT 0 /* LADCVOL - [7:0] */ | |
394 | #define WM8961_LADCVOL_WIDTH 8 /* LADCVOL - [7:0] */ | |
395 | ||
396 | /* | |
397 | * R22 (0x16) - Right ADC volume | |
398 | */ | |
399 | #define WM8961_ADCVU 0x0100 /* ADCVU */ | |
400 | #define WM8961_ADCVU_MASK 0x0100 /* ADCVU */ | |
401 | #define WM8961_ADCVU_SHIFT 8 /* ADCVU */ | |
402 | #define WM8961_ADCVU_WIDTH 1 /* ADCVU */ | |
403 | #define WM8961_RADCVOL_MASK 0x00FF /* RADCVOL - [7:0] */ | |
404 | #define WM8961_RADCVOL_SHIFT 0 /* RADCVOL - [7:0] */ | |
405 | #define WM8961_RADCVOL_WIDTH 8 /* RADCVOL - [7:0] */ | |
406 | ||
407 | /* | |
408 | * R23 (0x17) - Additional control(1) | |
409 | */ | |
410 | #define WM8961_TSDEN 0x0100 /* TSDEN */ | |
411 | #define WM8961_TSDEN_MASK 0x0100 /* TSDEN */ | |
412 | #define WM8961_TSDEN_SHIFT 8 /* TSDEN */ | |
413 | #define WM8961_TSDEN_WIDTH 1 /* TSDEN */ | |
414 | #define WM8961_DMONOMIX 0x0010 /* DMONOMIX */ | |
415 | #define WM8961_DMONOMIX_MASK 0x0010 /* DMONOMIX */ | |
416 | #define WM8961_DMONOMIX_SHIFT 4 /* DMONOMIX */ | |
417 | #define WM8961_DMONOMIX_WIDTH 1 /* DMONOMIX */ | |
418 | #define WM8961_TOEN 0x0001 /* TOEN */ | |
419 | #define WM8961_TOEN_MASK 0x0001 /* TOEN */ | |
420 | #define WM8961_TOEN_SHIFT 0 /* TOEN */ | |
421 | #define WM8961_TOEN_WIDTH 1 /* TOEN */ | |
422 | ||
423 | /* | |
424 | * R24 (0x18) - Additional control(2) | |
425 | */ | |
426 | #define WM8961_TRIS 0x0008 /* TRIS */ | |
427 | #define WM8961_TRIS_MASK 0x0008 /* TRIS */ | |
428 | #define WM8961_TRIS_SHIFT 3 /* TRIS */ | |
429 | #define WM8961_TRIS_WIDTH 1 /* TRIS */ | |
430 | ||
431 | /* | |
432 | * R25 (0x19) - Pwr Mgmt (1) | |
433 | */ | |
434 | #define WM8961_VMIDSEL_MASK 0x0180 /* VMIDSEL - [8:7] */ | |
435 | #define WM8961_VMIDSEL_SHIFT 7 /* VMIDSEL - [8:7] */ | |
436 | #define WM8961_VMIDSEL_WIDTH 2 /* VMIDSEL - [8:7] */ | |
437 | #define WM8961_VREF 0x0040 /* VREF */ | |
438 | #define WM8961_VREF_MASK 0x0040 /* VREF */ | |
439 | #define WM8961_VREF_SHIFT 6 /* VREF */ | |
440 | #define WM8961_VREF_WIDTH 1 /* VREF */ | |
441 | #define WM8961_AINL 0x0020 /* AINL */ | |
442 | #define WM8961_AINL_MASK 0x0020 /* AINL */ | |
443 | #define WM8961_AINL_SHIFT 5 /* AINL */ | |
444 | #define WM8961_AINL_WIDTH 1 /* AINL */ | |
445 | #define WM8961_AINR 0x0010 /* AINR */ | |
446 | #define WM8961_AINR_MASK 0x0010 /* AINR */ | |
447 | #define WM8961_AINR_SHIFT 4 /* AINR */ | |
448 | #define WM8961_AINR_WIDTH 1 /* AINR */ | |
449 | #define WM8961_ADCL 0x0008 /* ADCL */ | |
450 | #define WM8961_ADCL_MASK 0x0008 /* ADCL */ | |
451 | #define WM8961_ADCL_SHIFT 3 /* ADCL */ | |
452 | #define WM8961_ADCL_WIDTH 1 /* ADCL */ | |
453 | #define WM8961_ADCR 0x0004 /* ADCR */ | |
454 | #define WM8961_ADCR_MASK 0x0004 /* ADCR */ | |
455 | #define WM8961_ADCR_SHIFT 2 /* ADCR */ | |
456 | #define WM8961_ADCR_WIDTH 1 /* ADCR */ | |
457 | #define WM8961_MICB 0x0002 /* MICB */ | |
458 | #define WM8961_MICB_MASK 0x0002 /* MICB */ | |
459 | #define WM8961_MICB_SHIFT 1 /* MICB */ | |
460 | #define WM8961_MICB_WIDTH 1 /* MICB */ | |
461 | ||
462 | /* | |
463 | * R26 (0x1A) - Pwr Mgmt (2) | |
464 | */ | |
465 | #define WM8961_DACL 0x0100 /* DACL */ | |
466 | #define WM8961_DACL_MASK 0x0100 /* DACL */ | |
467 | #define WM8961_DACL_SHIFT 8 /* DACL */ | |
468 | #define WM8961_DACL_WIDTH 1 /* DACL */ | |
469 | #define WM8961_DACR 0x0080 /* DACR */ | |
470 | #define WM8961_DACR_MASK 0x0080 /* DACR */ | |
471 | #define WM8961_DACR_SHIFT 7 /* DACR */ | |
472 | #define WM8961_DACR_WIDTH 1 /* DACR */ | |
473 | #define WM8961_LOUT1_PGA 0x0040 /* LOUT1_PGA */ | |
474 | #define WM8961_LOUT1_PGA_MASK 0x0040 /* LOUT1_PGA */ | |
475 | #define WM8961_LOUT1_PGA_SHIFT 6 /* LOUT1_PGA */ | |
476 | #define WM8961_LOUT1_PGA_WIDTH 1 /* LOUT1_PGA */ | |
477 | #define WM8961_ROUT1_PGA 0x0020 /* ROUT1_PGA */ | |
478 | #define WM8961_ROUT1_PGA_MASK 0x0020 /* ROUT1_PGA */ | |
479 | #define WM8961_ROUT1_PGA_SHIFT 5 /* ROUT1_PGA */ | |
480 | #define WM8961_ROUT1_PGA_WIDTH 1 /* ROUT1_PGA */ | |
481 | #define WM8961_SPKL_PGA 0x0010 /* SPKL_PGA */ | |
482 | #define WM8961_SPKL_PGA_MASK 0x0010 /* SPKL_PGA */ | |
483 | #define WM8961_SPKL_PGA_SHIFT 4 /* SPKL_PGA */ | |
484 | #define WM8961_SPKL_PGA_WIDTH 1 /* SPKL_PGA */ | |
485 | #define WM8961_SPKR_PGA 0x0008 /* SPKR_PGA */ | |
486 | #define WM8961_SPKR_PGA_MASK 0x0008 /* SPKR_PGA */ | |
487 | #define WM8961_SPKR_PGA_SHIFT 3 /* SPKR_PGA */ | |
488 | #define WM8961_SPKR_PGA_WIDTH 1 /* SPKR_PGA */ | |
489 | ||
490 | /* | |
491 | * R27 (0x1B) - Additional Control (3) | |
492 | */ | |
493 | #define WM8961_SAMPLE_RATE_MASK 0x0007 /* SAMPLE_RATE - [2:0] */ | |
494 | #define WM8961_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [2:0] */ | |
495 | #define WM8961_SAMPLE_RATE_WIDTH 3 /* SAMPLE_RATE - [2:0] */ | |
496 | ||
497 | /* | |
498 | * R28 (0x1C) - Anti-pop | |
499 | */ | |
500 | #define WM8961_BUFDCOPEN 0x0010 /* BUFDCOPEN */ | |
501 | #define WM8961_BUFDCOPEN_MASK 0x0010 /* BUFDCOPEN */ | |
502 | #define WM8961_BUFDCOPEN_SHIFT 4 /* BUFDCOPEN */ | |
503 | #define WM8961_BUFDCOPEN_WIDTH 1 /* BUFDCOPEN */ | |
504 | #define WM8961_BUFIOEN 0x0008 /* BUFIOEN */ | |
505 | #define WM8961_BUFIOEN_MASK 0x0008 /* BUFIOEN */ | |
506 | #define WM8961_BUFIOEN_SHIFT 3 /* BUFIOEN */ | |
507 | #define WM8961_BUFIOEN_WIDTH 1 /* BUFIOEN */ | |
508 | #define WM8961_SOFT_ST 0x0004 /* SOFT_ST */ | |
509 | #define WM8961_SOFT_ST_MASK 0x0004 /* SOFT_ST */ | |
510 | #define WM8961_SOFT_ST_SHIFT 2 /* SOFT_ST */ | |
511 | #define WM8961_SOFT_ST_WIDTH 1 /* SOFT_ST */ | |
512 | ||
513 | /* | |
514 | * R30 (0x1E) - Clocking 3 | |
515 | */ | |
516 | #define WM8961_CLK_TO_DIV_MASK 0x0180 /* CLK_TO_DIV - [8:7] */ | |
517 | #define WM8961_CLK_TO_DIV_SHIFT 7 /* CLK_TO_DIV - [8:7] */ | |
518 | #define WM8961_CLK_TO_DIV_WIDTH 2 /* CLK_TO_DIV - [8:7] */ | |
519 | #define WM8961_CLK_256K_DIV_MASK 0x007E /* CLK_256K_DIV - [6:1] */ | |
520 | #define WM8961_CLK_256K_DIV_SHIFT 1 /* CLK_256K_DIV - [6:1] */ | |
521 | #define WM8961_CLK_256K_DIV_WIDTH 6 /* CLK_256K_DIV - [6:1] */ | |
522 | #define WM8961_MANUAL_MODE 0x0001 /* MANUAL_MODE */ | |
523 | #define WM8961_MANUAL_MODE_MASK 0x0001 /* MANUAL_MODE */ | |
524 | #define WM8961_MANUAL_MODE_SHIFT 0 /* MANUAL_MODE */ | |
525 | #define WM8961_MANUAL_MODE_WIDTH 1 /* MANUAL_MODE */ | |
526 | ||
527 | /* | |
528 | * R32 (0x20) - ADCL signal path | |
529 | */ | |
530 | #define WM8961_LMICBOOST_MASK 0x0030 /* LMICBOOST - [5:4] */ | |
531 | #define WM8961_LMICBOOST_SHIFT 4 /* LMICBOOST - [5:4] */ | |
532 | #define WM8961_LMICBOOST_WIDTH 2 /* LMICBOOST - [5:4] */ | |
533 | ||
534 | /* | |
535 | * R33 (0x21) - ADCR signal path | |
536 | */ | |
537 | #define WM8961_RMICBOOST_MASK 0x0030 /* RMICBOOST - [5:4] */ | |
538 | #define WM8961_RMICBOOST_SHIFT 4 /* RMICBOOST - [5:4] */ | |
539 | #define WM8961_RMICBOOST_WIDTH 2 /* RMICBOOST - [5:4] */ | |
540 | ||
541 | /* | |
542 | * R40 (0x28) - LOUT2 volume | |
543 | */ | |
544 | #define WM8961_SPKVU 0x0100 /* SPKVU */ | |
545 | #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ | |
546 | #define WM8961_SPKVU_SHIFT 8 /* SPKVU */ | |
547 | #define WM8961_SPKVU_WIDTH 1 /* SPKVU */ | |
548 | #define WM8961_SPKLZC 0x0080 /* SPKLZC */ | |
549 | #define WM8961_SPKLZC_MASK 0x0080 /* SPKLZC */ | |
550 | #define WM8961_SPKLZC_SHIFT 7 /* SPKLZC */ | |
551 | #define WM8961_SPKLZC_WIDTH 1 /* SPKLZC */ | |
552 | #define WM8961_SPKLVOL_MASK 0x007F /* SPKLVOL - [6:0] */ | |
553 | #define WM8961_SPKLVOL_SHIFT 0 /* SPKLVOL - [6:0] */ | |
554 | #define WM8961_SPKLVOL_WIDTH 7 /* SPKLVOL - [6:0] */ | |
555 | ||
556 | /* | |
557 | * R41 (0x29) - ROUT2 volume | |
558 | */ | |
559 | #define WM8961_SPKVU 0x0100 /* SPKVU */ | |
560 | #define WM8961_SPKVU_MASK 0x0100 /* SPKVU */ | |
561 | #define WM8961_SPKVU_SHIFT 8 /* SPKVU */ | |
562 | #define WM8961_SPKVU_WIDTH 1 /* SPKVU */ | |
563 | #define WM8961_SPKRZC 0x0080 /* SPKRZC */ | |
564 | #define WM8961_SPKRZC_MASK 0x0080 /* SPKRZC */ | |
565 | #define WM8961_SPKRZC_SHIFT 7 /* SPKRZC */ | |
566 | #define WM8961_SPKRZC_WIDTH 1 /* SPKRZC */ | |
567 | #define WM8961_SPKRVOL_MASK 0x007F /* SPKRVOL - [6:0] */ | |
568 | #define WM8961_SPKRVOL_SHIFT 0 /* SPKRVOL - [6:0] */ | |
569 | #define WM8961_SPKRVOL_WIDTH 7 /* SPKRVOL - [6:0] */ | |
570 | ||
571 | /* | |
572 | * R47 (0x2F) - Pwr Mgmt (3) | |
573 | */ | |
574 | #define WM8961_TEMP_SHUT 0x0002 /* TEMP_SHUT */ | |
575 | #define WM8961_TEMP_SHUT_MASK 0x0002 /* TEMP_SHUT */ | |
576 | #define WM8961_TEMP_SHUT_SHIFT 1 /* TEMP_SHUT */ | |
577 | #define WM8961_TEMP_SHUT_WIDTH 1 /* TEMP_SHUT */ | |
578 | #define WM8961_TEMP_WARN 0x0001 /* TEMP_WARN */ | |
579 | #define WM8961_TEMP_WARN_MASK 0x0001 /* TEMP_WARN */ | |
580 | #define WM8961_TEMP_WARN_SHIFT 0 /* TEMP_WARN */ | |
581 | #define WM8961_TEMP_WARN_WIDTH 1 /* TEMP_WARN */ | |
582 | ||
583 | /* | |
584 | * R48 (0x30) - Additional Control (4) | |
585 | */ | |
586 | #define WM8961_TSENSEN 0x0002 /* TSENSEN */ | |
587 | #define WM8961_TSENSEN_MASK 0x0002 /* TSENSEN */ | |
588 | #define WM8961_TSENSEN_SHIFT 1 /* TSENSEN */ | |
589 | #define WM8961_TSENSEN_WIDTH 1 /* TSENSEN */ | |
590 | #define WM8961_MBSEL 0x0001 /* MBSEL */ | |
591 | #define WM8961_MBSEL_MASK 0x0001 /* MBSEL */ | |
592 | #define WM8961_MBSEL_SHIFT 0 /* MBSEL */ | |
593 | #define WM8961_MBSEL_WIDTH 1 /* MBSEL */ | |
594 | ||
595 | /* | |
596 | * R49 (0x31) - Class D Control 1 | |
597 | */ | |
598 | #define WM8961_SPKR_ENA 0x0080 /* SPKR_ENA */ | |
599 | #define WM8961_SPKR_ENA_MASK 0x0080 /* SPKR_ENA */ | |
600 | #define WM8961_SPKR_ENA_SHIFT 7 /* SPKR_ENA */ | |
601 | #define WM8961_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ | |
602 | #define WM8961_SPKL_ENA 0x0040 /* SPKL_ENA */ | |
603 | #define WM8961_SPKL_ENA_MASK 0x0040 /* SPKL_ENA */ | |
604 | #define WM8961_SPKL_ENA_SHIFT 6 /* SPKL_ENA */ | |
605 | #define WM8961_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ | |
606 | ||
607 | /* | |
608 | * R51 (0x33) - Class D Control 2 | |
609 | */ | |
610 | #define WM8961_CLASSD_ACGAIN_MASK 0x0007 /* CLASSD_ACGAIN - [2:0] */ | |
611 | #define WM8961_CLASSD_ACGAIN_SHIFT 0 /* CLASSD_ACGAIN - [2:0] */ | |
612 | #define WM8961_CLASSD_ACGAIN_WIDTH 3 /* CLASSD_ACGAIN - [2:0] */ | |
613 | ||
614 | /* | |
615 | * R56 (0x38) - Clocking 4 | |
616 | */ | |
617 | #define WM8961_CLK_DCS_DIV_MASK 0x01E0 /* CLK_DCS_DIV - [8:5] */ | |
618 | #define WM8961_CLK_DCS_DIV_SHIFT 5 /* CLK_DCS_DIV - [8:5] */ | |
619 | #define WM8961_CLK_DCS_DIV_WIDTH 4 /* CLK_DCS_DIV - [8:5] */ | |
620 | #define WM8961_CLK_SYS_RATE_MASK 0x001E /* CLK_SYS_RATE - [4:1] */ | |
621 | #define WM8961_CLK_SYS_RATE_SHIFT 1 /* CLK_SYS_RATE - [4:1] */ | |
622 | #define WM8961_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [4:1] */ | |
623 | ||
624 | /* | |
625 | * R57 (0x39) - DSP Sidetone 0 | |
626 | */ | |
627 | #define WM8961_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ | |
628 | #define WM8961_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ | |
629 | #define WM8961_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ | |
630 | #define WM8961_ADC_TO_DACR_MASK 0x000C /* ADC_TO_DACR - [3:2] */ | |
631 | #define WM8961_ADC_TO_DACR_SHIFT 2 /* ADC_TO_DACR - [3:2] */ | |
632 | #define WM8961_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [3:2] */ | |
633 | ||
634 | /* | |
635 | * R58 (0x3A) - DSP Sidetone 1 | |
636 | */ | |
637 | #define WM8961_ADCL_DAC_SVOL_MASK 0x00F0 /* ADCL_DAC_SVOL - [7:4] */ | |
638 | #define WM8961_ADCL_DAC_SVOL_SHIFT 4 /* ADCL_DAC_SVOL - [7:4] */ | |
639 | #define WM8961_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [7:4] */ | |
640 | #define WM8961_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ | |
641 | #define WM8961_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ | |
642 | #define WM8961_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ | |
643 | ||
644 | /* | |
645 | * R60 (0x3C) - DC Servo 0 | |
646 | */ | |
647 | #define WM8961_DCS_ENA_CHAN_INL 0x0080 /* DCS_ENA_CHAN_INL */ | |
648 | #define WM8961_DCS_ENA_CHAN_INL_MASK 0x0080 /* DCS_ENA_CHAN_INL */ | |
649 | #define WM8961_DCS_ENA_CHAN_INL_SHIFT 7 /* DCS_ENA_CHAN_INL */ | |
650 | #define WM8961_DCS_ENA_CHAN_INL_WIDTH 1 /* DCS_ENA_CHAN_INL */ | |
651 | #define WM8961_DCS_TRIG_STARTUP_INL 0x0040 /* DCS_TRIG_STARTUP_INL */ | |
652 | #define WM8961_DCS_TRIG_STARTUP_INL_MASK 0x0040 /* DCS_TRIG_STARTUP_INL */ | |
653 | #define WM8961_DCS_TRIG_STARTUP_INL_SHIFT 6 /* DCS_TRIG_STARTUP_INL */ | |
654 | #define WM8961_DCS_TRIG_STARTUP_INL_WIDTH 1 /* DCS_TRIG_STARTUP_INL */ | |
655 | #define WM8961_DCS_TRIG_SERIES_INL 0x0010 /* DCS_TRIG_SERIES_INL */ | |
656 | #define WM8961_DCS_TRIG_SERIES_INL_MASK 0x0010 /* DCS_TRIG_SERIES_INL */ | |
657 | #define WM8961_DCS_TRIG_SERIES_INL_SHIFT 4 /* DCS_TRIG_SERIES_INL */ | |
658 | #define WM8961_DCS_TRIG_SERIES_INL_WIDTH 1 /* DCS_TRIG_SERIES_INL */ | |
659 | #define WM8961_DCS_ENA_CHAN_INR 0x0008 /* DCS_ENA_CHAN_INR */ | |
660 | #define WM8961_DCS_ENA_CHAN_INR_MASK 0x0008 /* DCS_ENA_CHAN_INR */ | |
661 | #define WM8961_DCS_ENA_CHAN_INR_SHIFT 3 /* DCS_ENA_CHAN_INR */ | |
662 | #define WM8961_DCS_ENA_CHAN_INR_WIDTH 1 /* DCS_ENA_CHAN_INR */ | |
663 | #define WM8961_DCS_TRIG_STARTUP_INR 0x0004 /* DCS_TRIG_STARTUP_INR */ | |
664 | #define WM8961_DCS_TRIG_STARTUP_INR_MASK 0x0004 /* DCS_TRIG_STARTUP_INR */ | |
665 | #define WM8961_DCS_TRIG_STARTUP_INR_SHIFT 2 /* DCS_TRIG_STARTUP_INR */ | |
666 | #define WM8961_DCS_TRIG_STARTUP_INR_WIDTH 1 /* DCS_TRIG_STARTUP_INR */ | |
667 | #define WM8961_DCS_TRIG_SERIES_INR 0x0001 /* DCS_TRIG_SERIES_INR */ | |
668 | #define WM8961_DCS_TRIG_SERIES_INR_MASK 0x0001 /* DCS_TRIG_SERIES_INR */ | |
669 | #define WM8961_DCS_TRIG_SERIES_INR_SHIFT 0 /* DCS_TRIG_SERIES_INR */ | |
670 | #define WM8961_DCS_TRIG_SERIES_INR_WIDTH 1 /* DCS_TRIG_SERIES_INR */ | |
671 | ||
672 | /* | |
673 | * R61 (0x3D) - DC Servo 1 | |
674 | */ | |
675 | #define WM8961_DCS_ENA_CHAN_HPL 0x0080 /* DCS_ENA_CHAN_HPL */ | |
676 | #define WM8961_DCS_ENA_CHAN_HPL_MASK 0x0080 /* DCS_ENA_CHAN_HPL */ | |
677 | #define WM8961_DCS_ENA_CHAN_HPL_SHIFT 7 /* DCS_ENA_CHAN_HPL */ | |
678 | #define WM8961_DCS_ENA_CHAN_HPL_WIDTH 1 /* DCS_ENA_CHAN_HPL */ | |
679 | #define WM8961_DCS_TRIG_STARTUP_HPL 0x0040 /* DCS_TRIG_STARTUP_HPL */ | |
680 | #define WM8961_DCS_TRIG_STARTUP_HPL_MASK 0x0040 /* DCS_TRIG_STARTUP_HPL */ | |
681 | #define WM8961_DCS_TRIG_STARTUP_HPL_SHIFT 6 /* DCS_TRIG_STARTUP_HPL */ | |
682 | #define WM8961_DCS_TRIG_STARTUP_HPL_WIDTH 1 /* DCS_TRIG_STARTUP_HPL */ | |
683 | #define WM8961_DCS_TRIG_SERIES_HPL 0x0010 /* DCS_TRIG_SERIES_HPL */ | |
684 | #define WM8961_DCS_TRIG_SERIES_HPL_MASK 0x0010 /* DCS_TRIG_SERIES_HPL */ | |
685 | #define WM8961_DCS_TRIG_SERIES_HPL_SHIFT 4 /* DCS_TRIG_SERIES_HPL */ | |
686 | #define WM8961_DCS_TRIG_SERIES_HPL_WIDTH 1 /* DCS_TRIG_SERIES_HPL */ | |
687 | #define WM8961_DCS_ENA_CHAN_HPR 0x0008 /* DCS_ENA_CHAN_HPR */ | |
688 | #define WM8961_DCS_ENA_CHAN_HPR_MASK 0x0008 /* DCS_ENA_CHAN_HPR */ | |
689 | #define WM8961_DCS_ENA_CHAN_HPR_SHIFT 3 /* DCS_ENA_CHAN_HPR */ | |
690 | #define WM8961_DCS_ENA_CHAN_HPR_WIDTH 1 /* DCS_ENA_CHAN_HPR */ | |
691 | #define WM8961_DCS_TRIG_STARTUP_HPR 0x0004 /* DCS_TRIG_STARTUP_HPR */ | |
692 | #define WM8961_DCS_TRIG_STARTUP_HPR_MASK 0x0004 /* DCS_TRIG_STARTUP_HPR */ | |
693 | #define WM8961_DCS_TRIG_STARTUP_HPR_SHIFT 2 /* DCS_TRIG_STARTUP_HPR */ | |
694 | #define WM8961_DCS_TRIG_STARTUP_HPR_WIDTH 1 /* DCS_TRIG_STARTUP_HPR */ | |
695 | #define WM8961_DCS_TRIG_SERIES_HPR 0x0001 /* DCS_TRIG_SERIES_HPR */ | |
696 | #define WM8961_DCS_TRIG_SERIES_HPR_MASK 0x0001 /* DCS_TRIG_SERIES_HPR */ | |
697 | #define WM8961_DCS_TRIG_SERIES_HPR_SHIFT 0 /* DCS_TRIG_SERIES_HPR */ | |
698 | #define WM8961_DCS_TRIG_SERIES_HPR_WIDTH 1 /* DCS_TRIG_SERIES_HPR */ | |
699 | ||
700 | /* | |
701 | * R63 (0x3F) - DC Servo 3 | |
702 | */ | |
703 | #define WM8961_DCS_FILT_BW_SERIES_MASK 0x0030 /* DCS_FILT_BW_SERIES - [5:4] */ | |
704 | #define WM8961_DCS_FILT_BW_SERIES_SHIFT 4 /* DCS_FILT_BW_SERIES - [5:4] */ | |
705 | #define WM8961_DCS_FILT_BW_SERIES_WIDTH 2 /* DCS_FILT_BW_SERIES - [5:4] */ | |
706 | ||
707 | /* | |
708 | * R65 (0x41) - DC Servo 5 | |
709 | */ | |
710 | #define WM8961_DCS_SERIES_NO_HP_MASK 0x007F /* DCS_SERIES_NO_HP - [6:0] */ | |
711 | #define WM8961_DCS_SERIES_NO_HP_SHIFT 0 /* DCS_SERIES_NO_HP - [6:0] */ | |
712 | #define WM8961_DCS_SERIES_NO_HP_WIDTH 7 /* DCS_SERIES_NO_HP - [6:0] */ | |
713 | ||
714 | /* | |
715 | * R68 (0x44) - Analogue PGA Bias | |
716 | */ | |
717 | #define WM8961_HP_PGAS_BIAS_MASK 0x0007 /* HP_PGAS_BIAS - [2:0] */ | |
718 | #define WM8961_HP_PGAS_BIAS_SHIFT 0 /* HP_PGAS_BIAS - [2:0] */ | |
719 | #define WM8961_HP_PGAS_BIAS_WIDTH 3 /* HP_PGAS_BIAS - [2:0] */ | |
720 | ||
721 | /* | |
722 | * R69 (0x45) - Analogue HP 0 | |
723 | */ | |
724 | #define WM8961_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ | |
725 | #define WM8961_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ | |
726 | #define WM8961_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ | |
727 | #define WM8961_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ | |
728 | #define WM8961_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ | |
729 | #define WM8961_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ | |
730 | #define WM8961_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ | |
731 | #define WM8961_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ | |
732 | #define WM8961_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ | |
733 | #define WM8961_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ | |
734 | #define WM8961_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ | |
735 | #define WM8961_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ | |
736 | #define WM8961_HPL_ENA 0x0010 /* HPL_ENA */ | |
737 | #define WM8961_HPL_ENA_MASK 0x0010 /* HPL_ENA */ | |
738 | #define WM8961_HPL_ENA_SHIFT 4 /* HPL_ENA */ | |
739 | #define WM8961_HPL_ENA_WIDTH 1 /* HPL_ENA */ | |
740 | #define WM8961_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ | |
741 | #define WM8961_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ | |
742 | #define WM8961_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ | |
743 | #define WM8961_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ | |
744 | #define WM8961_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ | |
745 | #define WM8961_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ | |
746 | #define WM8961_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ | |
747 | #define WM8961_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ | |
748 | #define WM8961_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */ | |
749 | #define WM8961_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ | |
750 | #define WM8961_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ | |
751 | #define WM8961_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ | |
752 | #define WM8961_HPR_ENA 0x0001 /* HPR_ENA */ | |
753 | #define WM8961_HPR_ENA_MASK 0x0001 /* HPR_ENA */ | |
754 | #define WM8961_HPR_ENA_SHIFT 0 /* HPR_ENA */ | |
755 | #define WM8961_HPR_ENA_WIDTH 1 /* HPR_ENA */ | |
756 | ||
757 | /* | |
758 | * R71 (0x47) - Analogue HP 2 | |
759 | */ | |
760 | #define WM8961_HPL_VOL_MASK 0x01C0 /* HPL_VOL - [8:6] */ | |
761 | #define WM8961_HPL_VOL_SHIFT 6 /* HPL_VOL - [8:6] */ | |
762 | #define WM8961_HPL_VOL_WIDTH 3 /* HPL_VOL - [8:6] */ | |
763 | #define WM8961_HPR_VOL_MASK 0x0038 /* HPR_VOL - [5:3] */ | |
764 | #define WM8961_HPR_VOL_SHIFT 3 /* HPR_VOL - [5:3] */ | |
765 | #define WM8961_HPR_VOL_WIDTH 3 /* HPR_VOL - [5:3] */ | |
766 | #define WM8961_HP_BIAS_BOOST_MASK 0x0007 /* HP_BIAS_BOOST - [2:0] */ | |
767 | #define WM8961_HP_BIAS_BOOST_SHIFT 0 /* HP_BIAS_BOOST - [2:0] */ | |
768 | #define WM8961_HP_BIAS_BOOST_WIDTH 3 /* HP_BIAS_BOOST - [2:0] */ | |
769 | ||
770 | /* | |
771 | * R72 (0x48) - Charge Pump 1 | |
772 | */ | |
773 | #define WM8961_CP_ENA 0x0001 /* CP_ENA */ | |
774 | #define WM8961_CP_ENA_MASK 0x0001 /* CP_ENA */ | |
775 | #define WM8961_CP_ENA_SHIFT 0 /* CP_ENA */ | |
776 | #define WM8961_CP_ENA_WIDTH 1 /* CP_ENA */ | |
777 | ||
778 | /* | |
779 | * R82 (0x52) - Charge Pump B | |
780 | */ | |
781 | #define WM8961_CP_DYN_PWR_MASK 0x0003 /* CP_DYN_PWR - [1:0] */ | |
782 | #define WM8961_CP_DYN_PWR_SHIFT 0 /* CP_DYN_PWR - [1:0] */ | |
783 | #define WM8961_CP_DYN_PWR_WIDTH 2 /* CP_DYN_PWR - [1:0] */ | |
784 | ||
785 | /* | |
786 | * R87 (0x57) - Write Sequencer 1 | |
787 | */ | |
788 | #define WM8961_WSEQ_ENA 0x0020 /* WSEQ_ENA */ | |
789 | #define WM8961_WSEQ_ENA_MASK 0x0020 /* WSEQ_ENA */ | |
790 | #define WM8961_WSEQ_ENA_SHIFT 5 /* WSEQ_ENA */ | |
791 | #define WM8961_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ | |
792 | #define WM8961_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ | |
793 | #define WM8961_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ | |
794 | #define WM8961_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ | |
795 | ||
796 | /* | |
797 | * R88 (0x58) - Write Sequencer 2 | |
798 | */ | |
799 | #define WM8961_WSEQ_EOS 0x0100 /* WSEQ_EOS */ | |
800 | #define WM8961_WSEQ_EOS_MASK 0x0100 /* WSEQ_EOS */ | |
801 | #define WM8961_WSEQ_EOS_SHIFT 8 /* WSEQ_EOS */ | |
802 | #define WM8961_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ | |
803 | #define WM8961_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ | |
804 | #define WM8961_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ | |
805 | #define WM8961_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ | |
806 | ||
807 | /* | |
808 | * R89 (0x59) - Write Sequencer 3 | |
809 | */ | |
810 | #define WM8961_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ | |
811 | #define WM8961_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ | |
812 | #define WM8961_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ | |
813 | ||
814 | /* | |
815 | * R90 (0x5A) - Write Sequencer 4 | |
816 | */ | |
817 | #define WM8961_WSEQ_ABORT 0x0100 /* WSEQ_ABORT */ | |
818 | #define WM8961_WSEQ_ABORT_MASK 0x0100 /* WSEQ_ABORT */ | |
819 | #define WM8961_WSEQ_ABORT_SHIFT 8 /* WSEQ_ABORT */ | |
820 | #define WM8961_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ | |
821 | #define WM8961_WSEQ_START 0x0080 /* WSEQ_START */ | |
822 | #define WM8961_WSEQ_START_MASK 0x0080 /* WSEQ_START */ | |
823 | #define WM8961_WSEQ_START_SHIFT 7 /* WSEQ_START */ | |
824 | #define WM8961_WSEQ_START_WIDTH 1 /* WSEQ_START */ | |
825 | #define WM8961_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ | |
826 | #define WM8961_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ | |
827 | #define WM8961_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ | |
828 | ||
829 | /* | |
830 | * R91 (0x5B) - Write Sequencer 5 | |
831 | */ | |
832 | #define WM8961_WSEQ_DATA_WIDTH_MASK 0x0070 /* WSEQ_DATA_WIDTH - [6:4] */ | |
833 | #define WM8961_WSEQ_DATA_WIDTH_SHIFT 4 /* WSEQ_DATA_WIDTH - [6:4] */ | |
834 | #define WM8961_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [6:4] */ | |
835 | #define WM8961_WSEQ_DATA_START_MASK 0x000F /* WSEQ_DATA_START - [3:0] */ | |
836 | #define WM8961_WSEQ_DATA_START_SHIFT 0 /* WSEQ_DATA_START - [3:0] */ | |
837 | #define WM8961_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [3:0] */ | |
838 | ||
839 | /* | |
840 | * R92 (0x5C) - Write Sequencer 6 | |
841 | */ | |
842 | #define WM8961_WSEQ_DELAY_MASK 0x000F /* WSEQ_DELAY - [3:0] */ | |
843 | #define WM8961_WSEQ_DELAY_SHIFT 0 /* WSEQ_DELAY - [3:0] */ | |
844 | #define WM8961_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [3:0] */ | |
845 | ||
846 | /* | |
847 | * R93 (0x5D) - Write Sequencer 7 | |
848 | */ | |
849 | #define WM8961_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ | |
850 | #define WM8961_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ | |
851 | #define WM8961_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ | |
852 | #define WM8961_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ | |
853 | ||
854 | /* | |
855 | * R252 (0xFC) - General test 1 | |
856 | */ | |
857 | #define WM8961_ARA_ENA 0x0002 /* ARA_ENA */ | |
858 | #define WM8961_ARA_ENA_MASK 0x0002 /* ARA_ENA */ | |
859 | #define WM8961_ARA_ENA_SHIFT 1 /* ARA_ENA */ | |
860 | #define WM8961_ARA_ENA_WIDTH 1 /* ARA_ENA */ | |
861 | #define WM8961_AUTO_INC 0x0001 /* AUTO_INC */ | |
862 | #define WM8961_AUTO_INC_MASK 0x0001 /* AUTO_INC */ | |
863 | #define WM8961_AUTO_INC_SHIFT 0 /* AUTO_INC */ | |
864 | #define WM8961_AUTO_INC_WIDTH 1 /* AUTO_INC */ | |
865 | ||
866 | #endif |