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ASoC: Remove -dai suffix from i.MX SSI driver
[deliverable/linux.git] / sound / soc / codecs / wm8962.c
CommitLineData
9a76f1ff
MB		 1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/i2c.h>
21#include <linux/input.h>
22#include <linux/platform_device.h>
23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <linux/workqueue.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/wm8962.h>
34
35#include "wm8962.h"
36
9a76f1ff
MB		 37#define WM8962_NUM_SUPPLIES 8
38static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
39 "DCVDD",
40 "DBVDD",
41 "AVDD",
42 "CPVDD",
43 "MICVDD",
44 "PLLVDD",
45 "SPKVDD1",
46 "SPKVDD2",
47};
48
49/* codec private data */
50struct wm8962_priv {
54d8d0ae
MB		 51 struct snd_soc_codec *codec;
52
9a76f1ff
MB		 53 u16 reg_cache[WM8962_MAX_REGISTER + 1];
54
55 int sysclk;
56 int sysclk_rate;
57
58 int bclk; /* Desired BCLK */
59 int lrclk;
60
61 int fll_src;
62 int fll_fref;
63 int fll_fout;
64
65 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
66 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
67
68#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
69 struct input_dev *beep;
70 struct work_struct beep_work;
71 int beep_rate;
72#endif
73};
74
75/* We can't use the same notifier block for more than one supply and
76 * there's no way I can see to get from a callback to the caller
77 * except container_of().
78 */
79#define WM8962_REGULATOR_EVENT(n) \
80static int wm8962_regulator_event_##n(struct notifier_block *nb, \
81 unsigned long event, void *data) \
82{ \
83 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
84 disable_nb[n]); \
85 if (event & REGULATOR_EVENT_DISABLE) { \
54d8d0ae 86 wm8962->codec->cache_sync = 1; \
9a76f1ff
MB		 87 } \
88 return 0; \
89}
90
91WM8962_REGULATOR_EVENT(0)
92WM8962_REGULATOR_EVENT(1)
93WM8962_REGULATOR_EVENT(2)
94WM8962_REGULATOR_EVENT(3)
95WM8962_REGULATOR_EVENT(4)
96WM8962_REGULATOR_EVENT(5)
97WM8962_REGULATOR_EVENT(6)
98WM8962_REGULATOR_EVENT(7)
99
100static int wm8962_volatile_register(unsigned int reg)
101{
102 if (wm8962_reg_access[reg].vol)
103 return 1;
104 else
105 return 0;
106}
107
54d8d0ae 108static int wm8962_readable_register(unsigned int reg)
9a76f1ff
MB		 109{
110 if (wm8962_reg_access[reg].read)
111 return 1;
112 else
113 return 0;
114}
115
116static int wm8962_reset(struct snd_soc_codec *codec)
117{
118 return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
119}
120
121static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
122static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
123static const unsigned int mixinpga_tlv[] = {
124 TLV_DB_RANGE_HEAD(7),
125 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
126 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
127 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
128 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
129 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
130};
131static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
132static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
133static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
134static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
135static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
136static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
137static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
138static const unsigned int classd_tlv[] = {
139 TLV_DB_RANGE_HEAD(7),
140 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
141 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
142};
143
144/* The VU bits for the headphones are in a different register to the mute
145 * bits and only take effect on the PGA if it is actually powered.
146 */
147static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
148 struct snd_ctl_elem_value *ucontrol)
149{
150 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
54d8d0ae
MB		 151 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
152 u16 *reg_cache = wm8962->reg_cache;
9a76f1ff
MB		 153 int ret;
154
155 /* Apply the update (if any) */
156 ret = snd_soc_put_volsw(kcontrol, ucontrol);
157 if (ret == 0)
158 return 0;
159
160 /* If the left PGA is enabled hit that VU bit... */
161 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
162 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
163 reg_cache[WM8962_HPOUTL_VOLUME]);
164
165 /* ...otherwise the right. The VU is stereo. */
166 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
167 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
168 reg_cache[WM8962_HPOUTR_VOLUME]);
169
170 return 0;
171}
172
173/* The VU bits for the speakers are in a different register to the mute
174 * bits and only take effect on the PGA if it is actually powered.
175 */
176static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
177 struct snd_ctl_elem_value *ucontrol)
178{
179 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
54d8d0ae
MB		 180 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
181 u16 *reg_cache = wm8962->reg_cache;
9a76f1ff
MB		 182 int ret;
183
184 /* Apply the update (if any) */
185 ret = snd_soc_put_volsw(kcontrol, ucontrol);
186 if (ret == 0)
187 return 0;
188
189 /* If the left PGA is enabled hit that VU bit... */
190 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
191 return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
192 reg_cache[WM8962_SPKOUTL_VOLUME]);
193
194 /* ...otherwise the right. The VU is stereo. */
195 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
196 return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
197 reg_cache[WM8962_SPKOUTR_VOLUME]);
198
199 return 0;
200}
201
202static const struct snd_kcontrol_new wm8962_snd_controls[] = {
203SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
204
205SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
206 mixin_tlv),
207SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
208 mixinpga_tlv),
209SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
210 mixin_tlv),
211
212SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
213 mixin_tlv),
214SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
215 mixinpga_tlv),
216SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
217 mixin_tlv),
218
219SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
220 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
221SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
222 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
223SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
224 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
225SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
226 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
227
228SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
229 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
230
231SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
232 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
233SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
234
235SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
236 5, 1, 0),
237
238SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
239
240SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
241 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
242SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
243 snd_soc_get_volsw, wm8962_put_hp_sw),
244SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
245 7, 1, 0),
246SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
247 hp_tlv),
248
249SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
250 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
251
252SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
253 3, 7, 0, bypass_tlv),
254SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
255 0, 7, 0, bypass_tlv),
256SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
257 7, 1, 1, inmix_tlv),
258SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
259 6, 1, 1, inmix_tlv),
260
261SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
262 3, 7, 0, bypass_tlv),
263SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
264 0, 7, 0, bypass_tlv),
265SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
266 7, 1, 1, inmix_tlv),
267SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
268 6, 1, 1, inmix_tlv),
269
270SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
271 classd_tlv),
272};
273
274static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
275SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
276SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
277 snd_soc_get_volsw, wm8962_put_spk_sw),
278SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
279
280SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
281SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
282 3, 7, 0, bypass_tlv),
283SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
284 0, 7, 0, bypass_tlv),
285SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
286 7, 1, 1, inmix_tlv),
287SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
288 6, 1, 1, inmix_tlv),
289SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
290 7, 1, 0, inmix_tlv),
291SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
292 6, 1, 0, inmix_tlv),
293};
294
295static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
296SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
297 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
298SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
299 snd_soc_get_volsw, wm8962_put_spk_sw),
300SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
301 7, 1, 0),
302
303SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
304 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
305
306SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
307 3, 7, 0, bypass_tlv),
308SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
309 0, 7, 0, bypass_tlv),
310SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
311 7, 1, 1, inmix_tlv),
312SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
313 6, 1, 1, inmix_tlv),
314SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
315 7, 1, 0, inmix_tlv),
316SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
317 6, 1, 0, inmix_tlv),
318
319SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
320 3, 7, 0, bypass_tlv),
321SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
322 0, 7, 0, bypass_tlv),
323SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
324 7, 1, 1, inmix_tlv),
325SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
326 6, 1, 1, inmix_tlv),
327SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
328 5, 1, 0, inmix_tlv),
329SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
330 4, 1, 0, inmix_tlv),
331};
332
333static int sysclk_event(struct snd_soc_dapm_widget *w,
334 struct snd_kcontrol *kcontrol, int event)
335{
336 struct snd_soc_codec *codec = w->codec;
337 int src;
338 int fll;
339
340 src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
341
342 switch (src) {
343 case 0: /* MCLK */
344 fll = 0;
345 break;
346 case 0x200: /* FLL */
347 fll = 1;
348 break;
349 default:
350 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
351 return -EINVAL;
352 }
353
354 switch (event) {
355 case SND_SOC_DAPM_PRE_PMU:
356 if (fll)
357 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
358 WM8962_FLL_ENA, WM8962_FLL_ENA);
359 break;
360
361 case SND_SOC_DAPM_POST_PMD:
362 if (fll)
363 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
364 WM8962_FLL_ENA, 0);
365 break;
366
367 default:
368 BUG();
369 return -EINVAL;
370 }
371
372 return 0;
373}
374
375static int cp_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377{
378 switch (event) {
379 case SND_SOC_DAPM_POST_PMU:
380 msleep(5);
381 break;
382
383 default:
384 BUG();
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
391static int hp_event(struct snd_soc_dapm_widget *w,
392 struct snd_kcontrol *kcontrol, int event)
393{
394 struct snd_soc_codec *codec = w->codec;
395 int timeout;
396 int reg;
397 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
398 WM8962_DCS_STARTUP_DONE_HP1R);
399
400 switch (event) {
401 case SND_SOC_DAPM_POST_PMU:
402 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
403 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
404 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
405 udelay(20);
406
407 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
408 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
409 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
410
411 /* Start the DC servo */
412 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
413 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
414 WM8962_HP1L_DCS_STARTUP |
415 WM8962_HP1R_DCS_STARTUP,
416 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
417 WM8962_HP1L_DCS_STARTUP |
418 WM8962_HP1R_DCS_STARTUP);
419
420 /* Wait for it to complete, should be well under 100ms */
421 timeout = 0;
422 do {
423 msleep(1);
424 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
425 if (reg < 0) {
426 dev_err(codec->dev,
427 "Failed to read DCS status: %d\n",
428 reg);
429 continue;
430 }
431 dev_dbg(codec->dev, "DCS status: %x\n", reg);
432 } while (++timeout < 200 && (reg & expected) != expected);
433
434 if ((reg & expected) != expected)
435 dev_err(codec->dev, "DC servo timed out\n");
436 else
437 dev_dbg(codec->dev, "DC servo complete after %dms\n",
438 timeout);
439
440 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
441 WM8962_HP1L_ENA_OUTP |
442 WM8962_HP1R_ENA_OUTP,
443 WM8962_HP1L_ENA_OUTP |
444 WM8962_HP1R_ENA_OUTP);
445 udelay(20);
446
447 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
448 WM8962_HP1L_RMV_SHORT |
449 WM8962_HP1R_RMV_SHORT,
450 WM8962_HP1L_RMV_SHORT |
451 WM8962_HP1R_RMV_SHORT);
452 break;
453
454 case SND_SOC_DAPM_PRE_PMD:
455 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
456 WM8962_HP1L_RMV_SHORT |
457 WM8962_HP1R_RMV_SHORT, 0);
458
459 udelay(20);
460
461 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
462 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
463 WM8962_HP1L_DCS_STARTUP |
464 WM8962_HP1R_DCS_STARTUP,
465 0);
466
467 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
468 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
469 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
470 WM8962_HP1L_ENA_OUTP |
471 WM8962_HP1R_ENA_OUTP, 0);
472
473 break;
474
475 default:
476 BUG();
477 return -EINVAL;
478
479 }
480
481 return 0;
482}
483
484/* VU bits for the output PGAs only take effect while the PGA is powered */
485static int out_pga_event(struct snd_soc_dapm_widget *w,
486 struct snd_kcontrol *kcontrol, int event)
487{
488 struct snd_soc_codec *codec = w->codec;
54d8d0ae
MB		 489 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
490 u16 *reg_cache = wm8962->reg_cache;
9a76f1ff
MB		 491 int reg;
492
493 switch (w->shift) {
494 case WM8962_HPOUTR_PGA_ENA_SHIFT:
495 reg = WM8962_HPOUTR_VOLUME;
496 break;
497 case WM8962_HPOUTL_PGA_ENA_SHIFT:
498 reg = WM8962_HPOUTL_VOLUME;
499 break;
500 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
501 reg = WM8962_SPKOUTR_VOLUME;
502 break;
503 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
504 reg = WM8962_SPKOUTL_VOLUME;
505 break;
506 default:
507 BUG();
508 return -EINVAL;
509 }
510
511 switch (event) {
512 case SND_SOC_DAPM_POST_PMU:
513 return snd_soc_write(codec, reg, reg_cache[reg]);
514 default:
515 BUG();
516 return -EINVAL;
517 }
518}
519
520static const char *st_text[] = { "None", "Right", "Left" };
521
522static const struct soc_enum str_enum =
523 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
524
525static const struct snd_kcontrol_new str_mux =
526 SOC_DAPM_ENUM("Right Sidetone", str_enum);
527
528static const struct soc_enum stl_enum =
529 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
530
531static const struct snd_kcontrol_new stl_mux =
532 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
533
534static const char *outmux_text[] = { "DAC", "Mixer" };
535
536static const struct soc_enum spkoutr_enum =
537 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
538
539static const struct snd_kcontrol_new spkoutr_mux =
540 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
541
542static const struct soc_enum spkoutl_enum =
543 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
544
545static const struct snd_kcontrol_new spkoutl_mux =
546 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
547
548static const struct soc_enum hpoutr_enum =
549 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
550
551static const struct snd_kcontrol_new hpoutr_mux =
552 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
553
554static const struct soc_enum hpoutl_enum =
555 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
556
557static const struct snd_kcontrol_new hpoutl_mux =
558 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
559
560static const struct snd_kcontrol_new inpgal[] = {
561SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
562SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
563SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
564SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
565};
566
567static const struct snd_kcontrol_new inpgar[] = {
568SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
569SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
570SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
571SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
572};
573
574static const struct snd_kcontrol_new mixinl[] = {
575SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
576SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
577SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
578};
579
580static const struct snd_kcontrol_new mixinr[] = {
581SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
582SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
583SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
584};
585
586static const struct snd_kcontrol_new hpmixl[] = {
587SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
588SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
589SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
590SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
591SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
592SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
593};
594
595static const struct snd_kcontrol_new hpmixr[] = {
596SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
597SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
598SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
599SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
600SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
601SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
602};
603
604static const struct snd_kcontrol_new spkmixl[] = {
605SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
606SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
607SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
608SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
609SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
610SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
611};
612
613static const struct snd_kcontrol_new spkmixr[] = {
614SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
615SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
616SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
617SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
618SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
619SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
620};
621
622static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
623SND_SOC_DAPM_INPUT("IN1L"),
624SND_SOC_DAPM_INPUT("IN1R"),
625SND_SOC_DAPM_INPUT("IN2L"),
626SND_SOC_DAPM_INPUT("IN2R"),
627SND_SOC_DAPM_INPUT("IN3L"),
628SND_SOC_DAPM_INPUT("IN3R"),
629SND_SOC_DAPM_INPUT("IN4L"),
630SND_SOC_DAPM_INPUT("IN4R"),
631SND_SOC_DAPM_INPUT("Beep"),
632
a4f28c00
MB		 633SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
634
9a76f1ff
MB		 635SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
636SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
637 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
638SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
639 SND_SOC_DAPM_POST_PMU),
640SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
641
642SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
643 inpgal, ARRAY_SIZE(inpgal)),
644SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
645 inpgar, ARRAY_SIZE(inpgar)),
646SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
647 mixinl, ARRAY_SIZE(mixinl)),
648SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
649 mixinr, ARRAY_SIZE(mixinr)),
650
651SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
652SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
653
654SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
655SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
656
657SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
658SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
659
660SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
661SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
662
663SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
664 hpmixl, ARRAY_SIZE(hpmixl)),
665SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
666 hpmixr, ARRAY_SIZE(hpmixr)),
667
668SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
669 out_pga_event, SND_SOC_DAPM_POST_PMU),
670SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
671 out_pga_event, SND_SOC_DAPM_POST_PMU),
672
673SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
674 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
675
676SND_SOC_DAPM_OUTPUT("HPOUTL"),
677SND_SOC_DAPM_OUTPUT("HPOUTR"),
678};
679
680static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
681SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
682 spkmixl, ARRAY_SIZE(spkmixl)),
683SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
684 out_pga_event, SND_SOC_DAPM_POST_PMU),
685SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
686SND_SOC_DAPM_OUTPUT("SPKOUT"),
687};
688
689static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
690SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
691 spkmixl, ARRAY_SIZE(spkmixl)),
692SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
693 spkmixr, ARRAY_SIZE(spkmixr)),
694
695SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
696 out_pga_event, SND_SOC_DAPM_POST_PMU),
697SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
698 out_pga_event, SND_SOC_DAPM_POST_PMU),
699
700SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
701SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
702
703SND_SOC_DAPM_OUTPUT("SPKOUTL"),
704SND_SOC_DAPM_OUTPUT("SPKOUTR"),
705};
706
707static const struct snd_soc_dapm_route wm8962_intercon[] = {
708 { "INPGAL", "IN1L Switch", "IN1L" },
709 { "INPGAL", "IN2L Switch", "IN2L" },
710 { "INPGAL", "IN3L Switch", "IN3L" },
711 { "INPGAL", "IN4L Switch", "IN4L" },
712
713 { "INPGAR", "IN1R Switch", "IN1R" },
714 { "INPGAR", "IN2R Switch", "IN2R" },
715 { "INPGAR", "IN3R Switch", "IN3R" },
716 { "INPGAR", "IN4R Switch", "IN4R" },
717
718 { "MIXINL", "IN2L Switch", "IN2L" },
719 { "MIXINL", "IN3L Switch", "IN3L" },
720 { "MIXINL", "PGA Switch", "INPGAL" },
721
722 { "MIXINR", "IN2R Switch", "IN2R" },
723 { "MIXINR", "IN3R Switch", "IN3R" },
724 { "MIXINR", "PGA Switch", "INPGAR" },
725
726 { "ADCL", NULL, "SYSCLK" },
727 { "ADCL", NULL, "TOCLK" },
728 { "ADCL", NULL, "MIXINL" },
729
730 { "ADCR", NULL, "SYSCLK" },
731 { "ADCR", NULL, "TOCLK" },
732 { "ADCR", NULL, "MIXINR" },
733
734 { "STL", "Left", "ADCL" },
735 { "STL", "Right", "ADCR" },
736
737 { "STR", "Left", "ADCL" },
738 { "STR", "Right", "ADCR" },
739
740 { "DACL", NULL, "SYSCLK" },
741 { "DACL", NULL, "TOCLK" },
742 { "DACL", NULL, "Beep" },
743 { "DACL", NULL, "STL" },
744
745 { "DACR", NULL, "SYSCLK" },
746 { "DACR", NULL, "TOCLK" },
747 { "DACR", NULL, "Beep" },
748 { "DACR", NULL, "STR" },
749
750 { "HPMIXL", "IN4L Switch", "IN4L" },
751 { "HPMIXL", "IN4R Switch", "IN4R" },
752 { "HPMIXL", "DACL Switch", "DACL" },
753 { "HPMIXL", "DACR Switch", "DACR" },
754 { "HPMIXL", "MIXINL Switch", "MIXINL" },
755 { "HPMIXL", "MIXINR Switch", "MIXINR" },
756
757 { "HPMIXR", "IN4L Switch", "IN4L" },
758 { "HPMIXR", "IN4R Switch", "IN4R" },
759 { "HPMIXR", "DACL Switch", "DACL" },
760 { "HPMIXR", "DACR Switch", "DACR" },
761 { "HPMIXR", "MIXINL Switch", "MIXINL" },
762 { "HPMIXR", "MIXINR Switch", "MIXINR" },
763
764 { "Left Bypass", NULL, "HPMIXL" },
765 { "Left Bypass", NULL, "Class G" },
766
767 { "Right Bypass", NULL, "HPMIXR" },
768 { "Right Bypass", NULL, "Class G" },
769
770 { "HPOUTL PGA", "Mixer", "Left Bypass" },
771 { "HPOUTL PGA", "DAC", "DACL" },
772
773 { "HPOUTR PGA", "Mixer", "Right Bypass" },
774 { "HPOUTR PGA", "DAC", "DACR" },
775
776 { "HPOUT", NULL, "HPOUTL PGA" },
777 { "HPOUT", NULL, "HPOUTR PGA" },
778 { "HPOUT", NULL, "Charge Pump" },
779 { "HPOUT", NULL, "SYSCLK" },
780 { "HPOUT", NULL, "TOCLK" },
781
782 { "HPOUTL", NULL, "HPOUT" },
783 { "HPOUTR", NULL, "HPOUT" },
784};
785
786static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
787 { "Speaker Mixer", "IN4L Switch", "IN4L" },
788 { "Speaker Mixer", "IN4R Switch", "IN4R" },
789 { "Speaker Mixer", "DACL Switch", "DACL" },
790 { "Speaker Mixer", "DACR Switch", "DACR" },
791 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
792 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
793
794 { "Speaker PGA", "Mixer", "Speaker Mixer" },
795 { "Speaker PGA", "DAC", "DACL" },
796
797 { "Speaker Output", NULL, "Speaker PGA" },
798 { "Speaker Output", NULL, "SYSCLK" },
799 { "Speaker Output", NULL, "TOCLK" },
800
801 { "SPKOUT", NULL, "Speaker Output" },
802};
803
804static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
805 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
806 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
807 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
808 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
809 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
810 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
811
812 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
813 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
814 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
815 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
816 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
817 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
818
819 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
820 { "SPKOUTL PGA", "DAC", "DACL" },
821
822 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
823 { "SPKOUTR PGA", "DAC", "DACR" },
824
825 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
826 { "SPKOUTL Output", NULL, "SYSCLK" },
827 { "SPKOUTL Output", NULL, "TOCLK" },
828
829 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
830 { "SPKOUTR Output", NULL, "SYSCLK" },
831 { "SPKOUTR Output", NULL, "TOCLK" },
832
833 { "SPKOUTL", NULL, "SPKOUTL Output" },
834 { "SPKOUTR", NULL, "SPKOUTR Output" },
835};
836
837static int wm8962_add_widgets(struct snd_soc_codec *codec)
838{
839 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
840
841 snd_soc_add_controls(codec, wm8962_snd_controls,
842 ARRAY_SIZE(wm8962_snd_controls));
843 if (pdata && pdata->spk_mono)
844 snd_soc_add_controls(codec, wm8962_spk_mono_controls,
845 ARRAY_SIZE(wm8962_spk_mono_controls));
846 else
847 snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
848 ARRAY_SIZE(wm8962_spk_stereo_controls));
849
850
851 snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
852 ARRAY_SIZE(wm8962_dapm_widgets));
853 if (pdata && pdata->spk_mono)
854 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
855 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
856 else
857 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
858 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
859
860 snd_soc_dapm_add_routes(codec, wm8962_intercon,
861 ARRAY_SIZE(wm8962_intercon));
862 if (pdata && pdata->spk_mono)
863 snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
864 ARRAY_SIZE(wm8962_spk_mono_intercon));
865 else
866 snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
867 ARRAY_SIZE(wm8962_spk_stereo_intercon));
868
869
870 snd_soc_dapm_disable_pin(codec, "Beep");
871
872 return 0;
873}
874
875static void wm8962_sync_cache(struct snd_soc_codec *codec)
876{
877 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
878 int i;
879
880 if (!codec->cache_sync)
881 return;
882
883 dev_dbg(codec->dev, "Syncing cache\n");
884
885 codec->cache_only = 0;
886
887 /* Sync back cached values if they're different from the
888 * hardware default.
889 */
890 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
891 if (i == WM8962_SOFTWARE_RESET)
892 continue;
893 if (wm8962->reg_cache[i] == wm8962_reg[i])
894 continue;
895
896 snd_soc_write(codec, i, wm8962->reg_cache[i]);
897 }
898
899 codec->cache_sync = 0;
900}
901
902/* -1 for reserved values */
903static const int bclk_divs[] = {
904 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
905};
906
907static void wm8962_configure_bclk(struct snd_soc_codec *codec)
908{
909 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
910 int dspclk, i;
911 int clocking2 = 0;
912 int aif2 = 0;
913
9a76f1ff
MB		 914 if (!wm8962->bclk) {
915 dev_dbg(codec->dev, "No BCLK rate configured\n");
916 return;
917 }
918
919 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
920 if (dspclk < 0) {
921 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
922 return;
923 }
924
925 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
926 switch (dspclk) {
927 case 0:
928 dspclk = wm8962->sysclk_rate;
929 break;
930 case 1:
931 dspclk = wm8962->sysclk_rate / 2;
932 break;
933 case 2:
934 dspclk = wm8962->sysclk_rate / 4;
935 break;
936 default:
937 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
938 dspclk = wm8962->sysclk;
939 }
940
941 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
942
943 /* We're expecting an exact match */
944 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
945 if (bclk_divs[i] < 0)
946 continue;
947
948 if (dspclk / bclk_divs[i] == wm8962->bclk) {
949 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
950 bclk_divs[i], wm8962->bclk);
951 clocking2 |= i;
952 break;
953 }
954 }
955 if (i == ARRAY_SIZE(bclk_divs)) {
956 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
957 dspclk / wm8962->bclk);
958 return;
959 }
960
961 aif2 |= wm8962->bclk / wm8962->lrclk;
962 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
963 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
964
965 snd_soc_update_bits(codec, WM8962_CLOCKING2,
966 WM8962_BCLK_DIV_MASK, clocking2);
967 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
968 WM8962_AIF_RATE_MASK, aif2);
969}
970
971static int wm8962_set_bias_level(struct snd_soc_codec *codec,
972 enum snd_soc_bias_level level)
973{
974 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
975 int ret;
976
977 if (level == codec->bias_level)
978 return 0;
979
980 switch (level) {
981 case SND_SOC_BIAS_ON:
982 break;
983
984 case SND_SOC_BIAS_PREPARE:
985 /* VMID 2*50k */
986 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
987 WM8962_VMID_SEL_MASK, 0x80);
988 break;
989
990 case SND_SOC_BIAS_STANDBY:
991 if (codec->bias_level == SND_SOC_BIAS_OFF) {
992 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
993 wm8962->supplies);
994 if (ret != 0) {
995 dev_err(codec->dev,
996 "Failed to enable supplies: %d\n",
997 ret);
998 return ret;
999 }
1000
1001 wm8962_sync_cache(codec);
1002
1003 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1004 WM8962_STARTUP_BIAS_ENA |
1005 WM8962_VMID_BUF_ENA,
1006 WM8962_STARTUP_BIAS_ENA |
1007 WM8962_VMID_BUF_ENA);
1008
1009 /* Bias enable at 2*50k for ramp */
1010 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1011 WM8962_VMID_SEL_MASK |
1012 WM8962_BIAS_ENA,
1013 WM8962_BIAS_ENA | 0x180);
1014
1015 msleep(5);
1016
1017 snd_soc_update_bits(codec, WM8962_CLOCKING2,
1018 WM8962_CLKREG_OVD,
1019 WM8962_CLKREG_OVD);
1020
1021 wm8962_configure_bclk(codec);
1022 }
1023
1024 /* VMID 2*250k */
1025 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1026 WM8962_VMID_SEL_MASK, 0x100);
1027 break;
1028
1029 case SND_SOC_BIAS_OFF:
1030 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1031 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
1032
1033 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1034 WM8962_STARTUP_BIAS_ENA |
1035 WM8962_VMID_BUF_ENA, 0);
1036
1037 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
1038 wm8962->supplies);
1039 break;
1040 }
1041 codec->bias_level = level;
1042 return 0;
1043}
1044
1045static const struct {
1046 int rate;
1047 int reg;
1048} sr_vals[] = {
1049 { 48000, 0 },
1050 { 44100, 0 },
1051 { 32000, 1 },
1052 { 22050, 2 },
1053 { 24000, 2 },
1054 { 16000, 3 },
1055 { 11025, 4 },
1056 { 12000, 4 },
1057 { 8000, 5 },
1058 { 88200, 6 },
1059 { 96000, 6 },
1060};
1061
1062static const int sysclk_rates[] = {
1063 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
1064};
1065
1066static int wm8962_hw_params(struct snd_pcm_substream *substream,
1067 struct snd_pcm_hw_params *params,
1068 struct snd_soc_dai *dai)
1069{
1070 struct snd_soc_pcm_runtime *rtd = substream->private_data;
54d8d0ae 1071 struct snd_soc_codec *codec = rtd->codec;
9a76f1ff
MB		 1072 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1073 int rate = params_rate(params);
1074 int i;
1075 int aif0 = 0;
1076 int adctl3 = 0;
1077 int clocking4 = 0;
1078
1079 wm8962->bclk = snd_soc_params_to_bclk(params);
1080 wm8962->lrclk = params_rate(params);
1081
1082 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
1083 if (sr_vals[i].rate == rate) {
1084 adctl3 |= sr_vals[i].reg;
1085 break;
1086 }
1087 }
1088 if (i == ARRAY_SIZE(sr_vals)) {
1089 dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
1090 return -EINVAL;
1091 }
1092
1093 if (rate % 8000 == 0)
1094 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
1095
1096 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
1097 if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
1098 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
1099 break;
1100 }
1101 }
1102 if (i == ARRAY_SIZE(sysclk_rates)) {
1103 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
1104 wm8962->sysclk_rate / rate);
1105 return -EINVAL;
1106 }
1107
1108 switch (params_format(params)) {
1109 case SNDRV_PCM_FORMAT_S16_LE:
1110 break;
1111 case SNDRV_PCM_FORMAT_S20_3LE:
1112 aif0 |= 0x40;
1113 break;
1114 case SNDRV_PCM_FORMAT_S24_LE:
1115 aif0 |= 0x80;
1116 break;
1117 case SNDRV_PCM_FORMAT_S32_LE:
1118 aif0 |= 0xc0;
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123
1124 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1125 WM8962_WL_MASK, aif0);
1126 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
1127 WM8962_SAMPLE_RATE_INT_MODE |
1128 WM8962_SAMPLE_RATE_MASK, adctl3);
1129 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
1130 WM8962_SYSCLK_RATE_MASK, clocking4);
1131
1132 wm8962_configure_bclk(codec);
1133
1134 return 0;
1135}
1136
1137static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1138 unsigned int freq, int dir)
1139{
1140 struct snd_soc_codec *codec = dai->codec;
1141 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1142 int src;
1143
1144 switch (clk_id) {
1145 case WM8962_SYSCLK_MCLK:
1146 wm8962->sysclk = WM8962_SYSCLK_MCLK;
1147 src = 0;
1148 break;
1149 case WM8962_SYSCLK_FLL:
1150 wm8962->sysclk = WM8962_SYSCLK_FLL;
1151 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
1152 WARN_ON(freq != wm8962->fll_fout);
1153 break;
1154 default:
1155 return -EINVAL;
1156 }
1157
1158 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
1159 src);
1160
1161 wm8962->sysclk_rate = freq;
1162
1163 return 0;
1164}
1165
1166static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1167{
1168 struct snd_soc_codec *codec = dai->codec;
1169 int aif0 = 0;
1170
1171 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1172 case SND_SOC_DAIFMT_DSP_A:
1173 aif0 |= WM8962_LRCLK_INV;
1174 case SND_SOC_DAIFMT_DSP_B:
1175 aif0 |= 3;
1176
1177 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1178 case SND_SOC_DAIFMT_NB_NF:
1179 case SND_SOC_DAIFMT_IB_NF:
1180 break;
1181 default:
1182 return -EINVAL;
1183 }
1184 break;
1185
1186 case SND_SOC_DAIFMT_RIGHT_J:
1187 break;
1188 case SND_SOC_DAIFMT_LEFT_J:
1189 aif0 |= 1;
1190 break;
1191 case SND_SOC_DAIFMT_I2S:
1192 aif0 |= 2;
1193 break;
1194 default:
1195 return -EINVAL;
1196 }
1197
1198 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1199 case SND_SOC_DAIFMT_NB_NF:
1200 break;
1201 case SND_SOC_DAIFMT_IB_NF:
1202 aif0 |= WM8962_BCLK_INV;
1203 break;
1204 case SND_SOC_DAIFMT_NB_IF:
1205 aif0 |= WM8962_LRCLK_INV;
1206 break;
1207 case SND_SOC_DAIFMT_IB_IF:
1208 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
1209 break;
1210 default:
1211 return -EINVAL;
1212 }
1213
1214 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1215 case SND_SOC_DAIFMT_CBM_CFM:
1216 aif0 |= WM8962_MSTR;
1217 break;
1218 case SND_SOC_DAIFMT_CBS_CFS:
1219 break;
1220 default:
1221 return -EINVAL;
1222 }
1223
1224 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1225 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
1226 WM8962_LRCLK_INV, aif0);
1227
1228 return 0;
1229}
1230
1231struct _fll_div {
1232 u16 fll_fratio;
1233 u16 fll_outdiv;
1234 u16 fll_refclk_div;
1235 u16 n;
1236 u16 theta;
1237 u16 lambda;
1238};
1239
1240/* The size in bits of the FLL divide multiplied by 10
1241 * to allow rounding later */
1242#define FIXED_FLL_SIZE ((1 << 16) * 10)
1243
1244static struct {
1245 unsigned int min;
1246 unsigned int max;
1247 u16 fll_fratio;
1248 int ratio;
1249} fll_fratios[] = {
1250 { 0, 64000, 4, 16 },
1251 { 64000, 128000, 3, 8 },
1252 { 128000, 256000, 2, 4 },
1253 { 256000, 1000000, 1, 2 },
1254 { 1000000, 13500000, 0, 1 },
1255};
1256
1257static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1258 unsigned int Fout)
1259{
1260 unsigned int target;
1261 unsigned int div;
1262 unsigned int fratio, gcd_fll;
1263 int i;
1264
1265 /* Fref must be <=13.5MHz */
1266 div = 1;
1267 fll_div->fll_refclk_div = 0;
1268 while ((Fref / div) > 13500000) {
1269 div *= 2;
1270 fll_div->fll_refclk_div++;
1271
1272 if (div > 4) {
1273 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1274 Fref);
1275 return -EINVAL;
1276 }
1277 }
1278
1279 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1280
1281 /* Apply the division for our remaining calculations */
1282 Fref /= div;
1283
1284 /* Fvco should be 90-100MHz; don't check the upper bound */
1285 div = 2;
1286 while (Fout * div < 90000000) {
1287 div++;
1288 if (div > 64) {
1289 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1290 Fout);
1291 return -EINVAL;
1292 }
1293 }
1294 target = Fout * div;
1295 fll_div->fll_outdiv = div - 1;
1296
1297 pr_debug("FLL Fvco=%dHz\n", target);
1298
1299 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1300 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1301 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1302 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1303 fratio = fll_fratios[i].ratio;
1304 break;
1305 }
1306 }
1307 if (i == ARRAY_SIZE(fll_fratios)) {
1308 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1309 return -EINVAL;
1310 }
1311
1312 fll_div->n = target / (fratio * Fref);
1313
1314 if (target % Fref == 0) {
1315 fll_div->theta = 0;
1316 fll_div->lambda = 0;
1317 } else {
1318 gcd_fll = gcd(target, fratio * Fref);
1319
1320 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1321 / gcd_fll;
1322 fll_div->lambda = (fratio * Fref) / gcd_fll;
1323 }
1324
1325 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1326 fll_div->n, fll_div->theta, fll_div->lambda);
1327 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1328 fll_div->fll_fratio, fll_div->fll_outdiv,
1329 fll_div->fll_refclk_div);
1330
1331 return 0;
1332}
1333
1334static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1335 unsigned int Fref, unsigned int Fout)
1336{
1337 struct snd_soc_codec *codec = dai->codec;
1338 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1339 struct _fll_div fll_div;
1340 int ret;
61371126 1341 int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
9a76f1ff
MB		 1342
1343 /* Any change? */
1344 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
1345 Fout == wm8962->fll_fout)
1346 return 0;
1347
1348 if (Fout == 0) {
1349 dev_dbg(codec->dev, "FLL disabled\n");
1350
1351 wm8962->fll_fref = 0;
1352 wm8962->fll_fout = 0;
1353
1354 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1355 WM8962_FLL_ENA, 0);
1356
1357 return 0;
1358 }
1359
1360 ret = fll_factors(&fll_div, Fref, Fout);
1361 if (ret != 0)
1362 return ret;
1363
1364 switch (fll_id) {
1365 case WM8962_FLL_MCLK:
1366 case WM8962_FLL_BCLK:
1367 case WM8962_FLL_OSC:
1368 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
1369 break;
1370 case WM8962_FLL_INT:
1371 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1372 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
1373 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
1374 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
1375 break;
1376 default:
1377 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
1378 return -EINVAL;
1379 }
1380
1381 if (fll_div.theta || fll_div.lambda)
1382 fll1 |= WM8962_FLL_FRAC;
1383
1384 /* Stop the FLL while we reconfigure */
1385 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
1386
1387 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
1388 WM8962_FLL_OUTDIV_MASK |
1389 WM8962_FLL_REFCLK_DIV_MASK,
1390 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
1391 (fll_div.fll_refclk_div));
1392
1393 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
1394 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
1395
1396 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
1397 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
1398 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
1399
1400 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1401 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
1402 WM8962_FLL_ENA, fll1);
1403
1404 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1405
1406 wm8962->fll_fref = Fref;
1407 wm8962->fll_fout = Fout;
1408 wm8962->fll_src = source;
1409
1410 return 0;
1411}
1412
1413static int wm8962_mute(struct snd_soc_dai *dai, int mute)
1414{
1415 struct snd_soc_codec *codec = dai->codec;
1416 int val;
1417
1418 if (mute)
1419 val = WM8962_DAC_MUTE;
1420 else
1421 val = 0;
1422
1423 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1424 WM8962_DAC_MUTE, val);
1425}
1426
1427#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
1428
1429#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1430 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1431
1432static struct snd_soc_dai_ops wm8962_dai_ops = {
1433 .hw_params = wm8962_hw_params,
1434 .set_sysclk = wm8962_set_dai_sysclk,
1435 .set_fmt = wm8962_set_dai_fmt,
1436 .set_pll = wm8962_set_fll,
1437 .digital_mute = wm8962_mute,
1438};
1439
54d8d0ae
MB		 1440static struct snd_soc_dai_driver wm8962_dai = {
1441 .name = "wm8962",
9a76f1ff
MB		 1442 .playback = {
1443 .stream_name = "Playback",
1444 .channels_min = 2,
1445 .channels_max = 2,
1446 .rates = WM8962_RATES,
1447 .formats = WM8962_FORMATS,
1448 },
1449 .capture = {
1450 .stream_name = "Capture",
1451 .channels_min = 2,
1452 .channels_max = 2,
1453 .rates = WM8962_RATES,
1454 .formats = WM8962_FORMATS,
1455 },
1456 .ops = &wm8962_dai_ops,
1457 .symmetric_rates = 1,
1458};
9a76f1ff 1459
45e65504
MB		 1460static irqreturn_t wm8962_irq(int irq, void *data)
1461{
1462 struct snd_soc_codec *codec = data;
1463 int mask;
1464 int active;
1465
1466 mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
1467
1468 active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
1469 active &= ~mask;
1470
1471 if (active & WM8962_FIFOS_ERR_EINT)
1472 dev_err(codec->dev, "FIFO error\n");
1473
1474 if (active & WM8962_TEMP_SHUT_EINT)
1475 dev_crit(codec->dev, "Thermal shutdown\n");
1476
1477 /* Acknowledge the interrupts */
1478 snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
1479
1480 return IRQ_HANDLED;
1481}
1482
9a76f1ff 1483#ifdef CONFIG_PM
54d8d0ae 1484static int wm8962_resume(struct snd_soc_codec *codec)
9a76f1ff 1485{
9a76f1ff
MB		 1486 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1487 u16 *reg_cache = codec->reg_cache;
1488 int i;
1489
1490 /* Restore the registers */
1491 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
1492 switch (i) {
1493 case WM8962_SOFTWARE_RESET:
1494 continue;
1495 default:
1496 break;
1497 }
1498
1499 if (reg_cache[i] != wm8962_reg[i])
1500 snd_soc_write(codec, i, reg_cache[i]);
1501 }
1502
1503 return 0;
1504}
1505#else
1506#define wm8962_resume NULL
1507#endif
1508
9a76f1ff
MB		 1509#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
1510static int beep_rates[] = {
1511 500, 1000, 2000, 4000,
1512};
1513
1514static void wm8962_beep_work(struct work_struct *work)
1515{
1516 struct wm8962_priv *wm8962 =
1517 container_of(work, struct wm8962_priv, beep_work);
54d8d0ae 1518 struct snd_soc_codec *codec = wm8962->codec;
9a76f1ff
MB		 1519 int i;
1520 int reg = 0;
1521 int best = 0;
1522
1523 if (wm8962->beep_rate) {
1524 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
1525 if (abs(wm8962->beep_rate - beep_rates[i]) <
1526 abs(wm8962->beep_rate - beep_rates[best]))
1527 best = i;
1528 }
1529
1530 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
1531 beep_rates[best], wm8962->beep_rate);
1532
1533 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
1534
1535 snd_soc_dapm_enable_pin(codec, "Beep");
1536 } else {
1537 dev_dbg(codec->dev, "Disabling beep\n");
1538 snd_soc_dapm_disable_pin(codec, "Beep");
1539 }
1540
1541 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
1542 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
1543
1544 snd_soc_dapm_sync(codec);
1545}
1546
1547/* For usability define a way of injecting beep events for the device -
1548 * many systems will not have a keyboard.
1549 */
1550static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
1551 unsigned int code, int hz)
1552{
1553 struct snd_soc_codec *codec = input_get_drvdata(dev);
1554 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1555
1556 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1557
1558 switch (code) {
1559 case SND_BELL:
1560 if (hz)
1561 hz = 1000;
1562 case SND_TONE:
1563 break;
1564 default:
1565 return -1;
1566 }
1567
1568 /* Kick the beep from a workqueue */
1569 wm8962->beep_rate = hz;
1570 schedule_work(&wm8962->beep_work);
1571 return 0;
1572}
1573
1574static ssize_t wm8962_beep_set(struct device *dev,
1575 struct device_attribute *attr,
1576 const char *buf, size_t count)
1577{
1578 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
1579 long int time;
1580
1581 strict_strtol(buf, 10, &time);
1582
1583 input_event(wm8962->beep, EV_SND, SND_TONE, time);
1584
1585 return count;
1586}
1587
1588static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
1589
1590static void wm8962_init_beep(struct snd_soc_codec *codec)
1591{
1592 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1593 int ret;
1594
1595 wm8962->beep = input_allocate_device();
1596 if (!wm8962->beep) {
1597 dev_err(codec->dev, "Failed to allocate beep device\n");
1598 return;
1599 }
1600
1601 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
1602 wm8962->beep_rate = 0;
1603
1604 wm8962->beep->name = "WM8962 Beep Generator";
1605 wm8962->beep->phys = dev_name(codec->dev);
1606 wm8962->beep->id.bustype = BUS_I2C;
1607
1608 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
1609 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1610 wm8962->beep->event = wm8962_beep_event;
1611 wm8962->beep->dev.parent = codec->dev;
1612 input_set_drvdata(wm8962->beep, codec);
1613
1614 ret = input_register_device(wm8962->beep);
1615 if (ret != 0) {
1616 input_free_device(wm8962->beep);
1617 wm8962->beep = NULL;
1618 dev_err(codec->dev, "Failed to register beep device\n");
1619 }
1620
1621 ret = device_create_file(codec->dev, &dev_attr_beep);
1622 if (ret != 0) {
1623 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1624 ret);
1625 }
1626}
1627
1628static void wm8962_free_beep(struct snd_soc_codec *codec)
1629{
1630 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1631
1632 device_remove_file(codec->dev, &dev_attr_beep);
1633 input_unregister_device(wm8962->beep);
1634 cancel_work_sync(&wm8962->beep_work);
1635 wm8962->beep = NULL;
1636
1637 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
1638}
1639#else
1640static void wm8962_init_beep(struct snd_soc_codec *codec)
1641{
1642}
1643
1644static void wm8962_free_beep(struct snd_soc_codec *codec)
1645{
1646}
1647#endif
1648
54d8d0ae 1649static int wm8962_probe(struct snd_soc_codec *codec)
9a76f1ff
MB		 1650{
1651 int ret;
54d8d0ae 1652 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
9a76f1ff 1653 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
45e65504
MB		 1654 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
1655 dev);
1656 int i, trigger, irq_pol;
9a76f1ff 1657
54d8d0ae 1658 wm8962->codec = codec;
9a76f1ff 1659
9a76f1ff
MB		 1660 codec->cache_sync = 1;
1661 codec->idle_bias_off = 1;
9a76f1ff 1662
54d8d0ae 1663 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
9a76f1ff
MB		 1664 if (ret != 0) {
1665 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1666 goto err;
1667 }
1668
1669 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1670 wm8962->supplies[i].supply = wm8962_supply_names[i];
1671
1672 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
1673 wm8962->supplies);
1674 if (ret != 0) {
1675 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1676 goto err;
1677 }
1678
1679 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
1680 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
1681 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
1682 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
1683 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
1684 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
1685 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
1686 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
1687
1688 /* This should really be moved into the regulator core */
1689 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
1690 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
1691 &wm8962->disable_nb[i]);
1692 if (ret != 0) {
1693 dev_err(codec->dev,
1694 "Failed to register regulator notifier: %d\n",
1695 ret);
1696 }
1697 }
1698
1699 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
1700 wm8962->supplies);
1701 if (ret != 0) {
1702 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1703 goto err_get;
1704 }
1705
1706 ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
1707 if (ret < 0) {
1708 dev_err(codec->dev, "Failed to read ID register\n");
1709 goto err_enable;
1710 }
1711 if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
1712 dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
1713 ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
1714 ret = -EINVAL;
1715 goto err_enable;
1716 }
1717
1718 ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
1719 if (ret < 0) {
1720 dev_err(codec->dev, "Failed to read device revision: %d\n",
1721 ret);
1722 goto err_enable;
1723 }
1724
1725 dev_info(codec->dev, "customer id %x revision %c\n",
1726 (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
1727 ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
1728 + 'A');
1729
1730 ret = wm8962_reset(codec);
1731 if (ret < 0) {
1732 dev_err(codec->dev, "Failed to issue reset\n");
1733 goto err_enable;
1734 }
1735
1736 /* SYSCLK defaults to on; make sure it is off so we can safely
1737 * write to registers if the device is declocked.
1738 */
1739 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
1740
1741 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1742
1743 if (pdata) {
1744 /* Apply static configuration for GPIOs */
1745 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
1746 if (pdata->gpio_init[i])
1747 snd_soc_write(codec, 0x200 + i,
1748 pdata->gpio_init[i] & 0xffff);
1749
1750 /* Put the speakers into mono mode? */
1751 if (pdata->spk_mono)
1752 wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
1753 |= WM8962_SPK_MONO;
a4f28c00
MB		 1754
1755 /* Micbias setup, detection enable and detection
1756 * threasholds. */
1757 if (pdata->mic_cfg)
1758 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
1759 WM8962_MICDET_ENA |
1760 WM8962_MICDET_THR_MASK |
1761 WM8962_MICSHORT_THR_MASK |
1762 WM8962_MICBIAS_LVL,
1763 pdata->mic_cfg);
9a76f1ff
MB		 1764 }
1765
1766 /* Latch volume update bits */
1767 wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
1768 wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
1769 wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
1770 wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
1771 wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
1772 wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
1773 wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
1774 wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
1775 wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
1776 wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
1777
54d8d0ae 1778 wm8962_add_widgets(codec);
9a76f1ff
MB		 1779
1780 wm8962_init_beep(codec);
1781
45e65504
MB		 1782 if (i2c->irq) {
1783 if (pdata && pdata->irq_active_low) {
1784 trigger = IRQF_TRIGGER_LOW;
1785 irq_pol = WM8962_IRQ_POL;
1786 } else {
1787 trigger = IRQF_TRIGGER_HIGH;
1788 irq_pol = 0;
1789 }
1790
1791 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
1792 WM8962_IRQ_POL, irq_pol);
1793
1794 ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq,
1795 trigger | IRQF_ONESHOT,
1796 "wm8962", codec);
1797 if (ret != 0) {
1798 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
1799 i2c->irq, ret);
1800 /* Non-fatal */
1801 } else {
1802 /* Enable error reporting IRQs by default */
1803 snd_soc_update_bits(codec,
1804 WM8962_INTERRUPT_STATUS_2_MASK,
1805 WM8962_TEMP_SHUT_EINT |
1806 WM8962_FIFOS_ERR_EINT, 0);
1807 }
1808 }
1809
9a76f1ff
MB		 1810 return 0;
1811
1812err_enable:
1813 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1814err_get:
1815 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1816err:
1817 kfree(wm8962);
1818 return ret;
1819}
1820
54d8d0ae 1821static int wm8962_remove(struct snd_soc_codec *codec)
9a76f1ff 1822{
54d8d0ae 1823 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
45e65504
MB		 1824 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
1825 dev);
9a76f1ff
MB		 1826 int i;
1827
45e65504
MB		 1828 if (i2c->irq)
1829 free_irq(i2c->irq, codec);
1830
54d8d0ae 1831 wm8962_free_beep(codec);
9a76f1ff
MB		 1832 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1833 regulator_unregister_notifier(wm8962->supplies[i].consumer,
1834 &wm8962->disable_nb[i]);
1835 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
54d8d0ae
MB		 1836
1837 return 0;
9a76f1ff
MB		 1838}
1839
54d8d0ae
MB		 1840static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
1841 .probe = wm8962_probe,
1842 .remove = wm8962_remove,
1843 .resume = wm8962_resume,
1844 .set_bias_level = wm8962_set_bias_level,
6946e037 1845 .reg_cache_size = WM8962_MAX_REGISTER + 1,
54d8d0ae
MB		 1846 .reg_word_size = sizeof(u16),
1847 .reg_cache_default = wm8962_reg,
1848 .volatile_register = wm8962_volatile_register,
1849 .readable_register = wm8962_readable_register,
1850};
1851
9a76f1ff
MB		 1852#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1853static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
1854 const struct i2c_device_id *id)
1855{
1856 struct wm8962_priv *wm8962;
54d8d0ae 1857 int ret;
9a76f1ff
MB		 1858
1859 wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
1860 if (wm8962 == NULL)
1861 return -ENOMEM;
1862
9a76f1ff 1863 i2c_set_clientdata(i2c, wm8962);
9a76f1ff 1864
54d8d0ae
MB		 1865 ret = snd_soc_register_codec(&i2c->dev,
1866 &soc_codec_dev_wm8962, &wm8962_dai, 1);
1867 if (ret < 0)
1868 kfree(wm8962);
9a76f1ff 1869
54d8d0ae 1870 return ret;
9a76f1ff
MB		 1871}
1872
1873static __devexit int wm8962_i2c_remove(struct i2c_client *client)
1874{
54d8d0ae
MB		 1875 snd_soc_unregister_codec(&client->dev);
1876 kfree(i2c_get_clientdata(client));
9a76f1ff
MB		 1877 return 0;
1878}
1879
1880static const struct i2c_device_id wm8962_i2c_id[] = {
1881 { "wm8962", 0 },
1882 { }
1883};
1884MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
1885
1886static struct i2c_driver wm8962_i2c_driver = {
1887 .driver = {
ea738bad 1888 .name = "wm8962",
9a76f1ff
MB		 1889 .owner = THIS_MODULE,
1890 },
1891 .probe = wm8962_i2c_probe,
1892 .remove = __devexit_p(wm8962_i2c_remove),
1893 .id_table = wm8962_i2c_id,
1894};
1895#endif
1896
1897static int __init wm8962_modinit(void)
1898{
1899 int ret;
1900#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1901 ret = i2c_add_driver(&wm8962_i2c_driver);
1902 if (ret != 0) {
1903 printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
1904 ret);
1905 }
1906#endif
1907 return 0;
1908}
1909module_init(wm8962_modinit);
1910
1911static void __exit wm8962_exit(void)
1912{
1913#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1914 i2c_del_driver(&wm8962_i2c_driver);
1915#endif
1916}
1917module_exit(wm8962_exit);
1918
1919MODULE_DESCRIPTION("ASoC WM8962 driver");
1920MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1921MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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