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ASoC: Put WM8962 GPIO2/3 into GPIO mode when configuring platform data too
[deliverable/linux.git] / sound / soc / codecs / wm8962.c
CommitLineData
9a76f1ff
MB		 1/*
2 * wm8962.c -- WM8962 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
3367b8d4 20#include <linux/gpio.h>
9a76f1ff
MB		 21#include <linux/i2c.h>
22#include <linux/input.h>
23#include <linux/platform_device.h>
24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
26#include <linux/workqueue.h>
27#include <sound/core.h>
7711308a 28#include <sound/jack.h>
9a76f1ff
MB		 29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
32#include <sound/soc-dapm.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/wm8962.h>
36
37#include "wm8962.h"
38
9a76f1ff
MB		 39#define WM8962_NUM_SUPPLIES 8
40static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
41 "DCVDD",
42 "DBVDD",
43 "AVDD",
44 "CPVDD",
45 "MICVDD",
46 "PLLVDD",
47 "SPKVDD1",
48 "SPKVDD2",
49};
50
51/* codec private data */
52struct wm8962_priv {
54d8d0ae
MB		 53 struct snd_soc_codec *codec;
54
9a76f1ff
MB		 55 u16 reg_cache[WM8962_MAX_REGISTER + 1];
56
57 int sysclk;
58 int sysclk_rate;
59
60 int bclk; /* Desired BCLK */
61 int lrclk;
62
63 int fll_src;
64 int fll_fref;
65 int fll_fout;
66
7711308a
MB		 67 struct delayed_work mic_work;
68 struct snd_soc_jack *jack;
69
9a76f1ff
MB		 70 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
71 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
72
73#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
74 struct input_dev *beep;
75 struct work_struct beep_work;
76 int beep_rate;
77#endif
3367b8d4
MB		 78
79#ifdef CONFIG_GPIOLIB
80 struct gpio_chip gpio_chip;
81#endif
9a76f1ff
MB		 82};
83
84/* We can't use the same notifier block for more than one supply and
85 * there's no way I can see to get from a callback to the caller
86 * except container_of().
87 */
88#define WM8962_REGULATOR_EVENT(n) \
89static int wm8962_regulator_event_##n(struct notifier_block *nb, \
90 unsigned long event, void *data) \
91{ \
92 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
93 disable_nb[n]); \
94 if (event & REGULATOR_EVENT_DISABLE) { \
54d8d0ae 95 wm8962->codec->cache_sync = 1; \
9a76f1ff
MB		 96 } \
97 return 0; \
98}
99
100WM8962_REGULATOR_EVENT(0)
101WM8962_REGULATOR_EVENT(1)
102WM8962_REGULATOR_EVENT(2)
103WM8962_REGULATOR_EVENT(3)
104WM8962_REGULATOR_EVENT(4)
105WM8962_REGULATOR_EVENT(5)
106WM8962_REGULATOR_EVENT(6)
107WM8962_REGULATOR_EVENT(7)
108
109static int wm8962_volatile_register(unsigned int reg)
110{
111 if (wm8962_reg_access[reg].vol)
112 return 1;
113 else
114 return 0;
115}
116
54d8d0ae 117static int wm8962_readable_register(unsigned int reg)
9a76f1ff
MB		 118{
119 if (wm8962_reg_access[reg].read)
120 return 1;
121 else
122 return 0;
123}
124
125static int wm8962_reset(struct snd_soc_codec *codec)
126{
127 return snd_soc_write(codec, WM8962_SOFTWARE_RESET, 0);
128}
129
130static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
131static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
132static const unsigned int mixinpga_tlv[] = {
133 TLV_DB_RANGE_HEAD(7),
134 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
135 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
136 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
137 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
138 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
139};
140static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
141static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
142static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
143static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
144static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
145static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
146static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
147static const unsigned int classd_tlv[] = {
148 TLV_DB_RANGE_HEAD(7),
149 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
150 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
151};
152
153/* The VU bits for the headphones are in a different register to the mute
154 * bits and only take effect on the PGA if it is actually powered.
155 */
156static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
157 struct snd_ctl_elem_value *ucontrol)
158{
159 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
54d8d0ae
MB		 160 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
161 u16 *reg_cache = wm8962->reg_cache;
9a76f1ff
MB		 162 int ret;
163
164 /* Apply the update (if any) */
165 ret = snd_soc_put_volsw(kcontrol, ucontrol);
166 if (ret == 0)
167 return 0;
168
169 /* If the left PGA is enabled hit that VU bit... */
170 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTL_PGA_ENA)
171 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
172 reg_cache[WM8962_HPOUTL_VOLUME]);
173
174 /* ...otherwise the right. The VU is stereo. */
175 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_HPOUTR_PGA_ENA)
176 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
177 reg_cache[WM8962_HPOUTR_VOLUME]);
178
179 return 0;
180}
181
182/* The VU bits for the speakers are in a different register to the mute
183 * bits and only take effect on the PGA if it is actually powered.
184 */
185static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
186 struct snd_ctl_elem_value *ucontrol)
187{
188 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
54d8d0ae
MB		 189 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
190 u16 *reg_cache = wm8962->reg_cache;
9a76f1ff
MB		 191 int ret;
192
193 /* Apply the update (if any) */
194 ret = snd_soc_put_volsw(kcontrol, ucontrol);
195 if (ret == 0)
196 return 0;
197
198 /* If the left PGA is enabled hit that VU bit... */
199 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTL_PGA_ENA)
200 return snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
201 reg_cache[WM8962_SPKOUTL_VOLUME]);
202
203 /* ...otherwise the right. The VU is stereo. */
204 if (reg_cache[WM8962_PWR_MGMT_2] & WM8962_SPKOUTR_PGA_ENA)
205 return snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
206 reg_cache[WM8962_SPKOUTR_VOLUME]);
207
208 return 0;
209}
210
211static const struct snd_kcontrol_new wm8962_snd_controls[] = {
212SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
213
214SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
215 mixin_tlv),
216SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
217 mixinpga_tlv),
218SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
219 mixin_tlv),
220
221SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
222 mixin_tlv),
223SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
224 mixinpga_tlv),
225SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
226 mixin_tlv),
227
228SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
229 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
230SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
231 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
232SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
233 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
234SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
235 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
236
237SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
238 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
239
240SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
241 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
242SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
243
244SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
245 5, 1, 0),
246
247SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
248
249SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
250 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
251SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
252 snd_soc_get_volsw, wm8962_put_hp_sw),
253SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
254 7, 1, 0),
255SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
256 hp_tlv),
257
258SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
259 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
260
261SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
262 3, 7, 0, bypass_tlv),
263SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
264 0, 7, 0, bypass_tlv),
265SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
266 7, 1, 1, inmix_tlv),
267SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
268 6, 1, 1, inmix_tlv),
269
270SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
271 3, 7, 0, bypass_tlv),
272SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
273 0, 7, 0, bypass_tlv),
274SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
275 7, 1, 1, inmix_tlv),
276SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
277 6, 1, 1, inmix_tlv),
278
279SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
280 classd_tlv),
281};
282
283static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
284SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
285SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
286 snd_soc_get_volsw, wm8962_put_spk_sw),
287SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
288
289SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
290SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
291 3, 7, 0, bypass_tlv),
292SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
293 0, 7, 0, bypass_tlv),
294SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
295 7, 1, 1, inmix_tlv),
296SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
297 6, 1, 1, inmix_tlv),
298SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
299 7, 1, 0, inmix_tlv),
300SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
301 6, 1, 0, inmix_tlv),
302};
303
304static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
305SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
306 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
307SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
308 snd_soc_get_volsw, wm8962_put_spk_sw),
309SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
310 7, 1, 0),
311
312SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
313 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
314
315SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
316 3, 7, 0, bypass_tlv),
317SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
318 0, 7, 0, bypass_tlv),
319SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
320 7, 1, 1, inmix_tlv),
321SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
322 6, 1, 1, inmix_tlv),
323SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
324 7, 1, 0, inmix_tlv),
325SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
326 6, 1, 0, inmix_tlv),
327
328SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
329 3, 7, 0, bypass_tlv),
330SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
331 0, 7, 0, bypass_tlv),
332SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
333 7, 1, 1, inmix_tlv),
334SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
335 6, 1, 1, inmix_tlv),
336SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
337 5, 1, 0, inmix_tlv),
338SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
339 4, 1, 0, inmix_tlv),
340};
341
342static int sysclk_event(struct snd_soc_dapm_widget *w,
343 struct snd_kcontrol *kcontrol, int event)
344{
345 struct snd_soc_codec *codec = w->codec;
346 int src;
347 int fll;
348
349 src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK;
350
351 switch (src) {
352 case 0: /* MCLK */
353 fll = 0;
354 break;
355 case 0x200: /* FLL */
356 fll = 1;
357 break;
358 default:
359 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src);
360 return -EINVAL;
361 }
362
363 switch (event) {
364 case SND_SOC_DAPM_PRE_PMU:
365 if (fll)
366 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
367 WM8962_FLL_ENA, WM8962_FLL_ENA);
368 break;
369
370 case SND_SOC_DAPM_POST_PMD:
371 if (fll)
372 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
373 WM8962_FLL_ENA, 0);
374 break;
375
376 default:
377 BUG();
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
384static int cp_event(struct snd_soc_dapm_widget *w,
385 struct snd_kcontrol *kcontrol, int event)
386{
387 switch (event) {
388 case SND_SOC_DAPM_POST_PMU:
389 msleep(5);
390 break;
391
392 default:
393 BUG();
394 return -EINVAL;
395 }
396
397 return 0;
398}
399
400static int hp_event(struct snd_soc_dapm_widget *w,
401 struct snd_kcontrol *kcontrol, int event)
402{
403 struct snd_soc_codec *codec = w->codec;
404 int timeout;
405 int reg;
406 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
407 WM8962_DCS_STARTUP_DONE_HP1R);
408
409 switch (event) {
410 case SND_SOC_DAPM_POST_PMU:
411 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
412 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
413 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
414 udelay(20);
415
416 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
417 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
418 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
419
420 /* Start the DC servo */
421 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
422 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
423 WM8962_HP1L_DCS_STARTUP |
424 WM8962_HP1R_DCS_STARTUP,
425 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
426 WM8962_HP1L_DCS_STARTUP |
427 WM8962_HP1R_DCS_STARTUP);
428
429 /* Wait for it to complete, should be well under 100ms */
430 timeout = 0;
431 do {
432 msleep(1);
433 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
434 if (reg < 0) {
435 dev_err(codec->dev,
436 "Failed to read DCS status: %d\n",
437 reg);
438 continue;
439 }
440 dev_dbg(codec->dev, "DCS status: %x\n", reg);
441 } while (++timeout < 200 && (reg & expected) != expected);
442
443 if ((reg & expected) != expected)
444 dev_err(codec->dev, "DC servo timed out\n");
445 else
446 dev_dbg(codec->dev, "DC servo complete after %dms\n",
447 timeout);
448
449 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
450 WM8962_HP1L_ENA_OUTP |
451 WM8962_HP1R_ENA_OUTP,
452 WM8962_HP1L_ENA_OUTP |
453 WM8962_HP1R_ENA_OUTP);
454 udelay(20);
455
456 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
457 WM8962_HP1L_RMV_SHORT |
458 WM8962_HP1R_RMV_SHORT,
459 WM8962_HP1L_RMV_SHORT |
460 WM8962_HP1R_RMV_SHORT);
461 break;
462
463 case SND_SOC_DAPM_PRE_PMD:
464 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
465 WM8962_HP1L_RMV_SHORT |
466 WM8962_HP1R_RMV_SHORT, 0);
467
468 udelay(20);
469
470 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
471 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
472 WM8962_HP1L_DCS_STARTUP |
473 WM8962_HP1R_DCS_STARTUP,
474 0);
475
476 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
477 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
478 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
479 WM8962_HP1L_ENA_OUTP |
480 WM8962_HP1R_ENA_OUTP, 0);
481
482 break;
483
484 default:
485 BUG();
486 return -EINVAL;
487
488 }
489
490 return 0;
491}
492
493/* VU bits for the output PGAs only take effect while the PGA is powered */
494static int out_pga_event(struct snd_soc_dapm_widget *w,
495 struct snd_kcontrol *kcontrol, int event)
496{
497 struct snd_soc_codec *codec = w->codec;
54d8d0ae
MB		 498 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
499 u16 *reg_cache = wm8962->reg_cache;
9a76f1ff
MB		 500 int reg;
501
502 switch (w->shift) {
503 case WM8962_HPOUTR_PGA_ENA_SHIFT:
504 reg = WM8962_HPOUTR_VOLUME;
505 break;
506 case WM8962_HPOUTL_PGA_ENA_SHIFT:
507 reg = WM8962_HPOUTL_VOLUME;
508 break;
509 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
510 reg = WM8962_SPKOUTR_VOLUME;
511 break;
512 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
513 reg = WM8962_SPKOUTL_VOLUME;
514 break;
515 default:
516 BUG();
517 return -EINVAL;
518 }
519
520 switch (event) {
521 case SND_SOC_DAPM_POST_PMU:
522 return snd_soc_write(codec, reg, reg_cache[reg]);
523 default:
524 BUG();
525 return -EINVAL;
526 }
527}
528
529static const char *st_text[] = { "None", "Right", "Left" };
530
531static const struct soc_enum str_enum =
532 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
533
534static const struct snd_kcontrol_new str_mux =
535 SOC_DAPM_ENUM("Right Sidetone", str_enum);
536
537static const struct soc_enum stl_enum =
538 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
539
540static const struct snd_kcontrol_new stl_mux =
541 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
542
543static const char *outmux_text[] = { "DAC", "Mixer" };
544
545static const struct soc_enum spkoutr_enum =
546 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
547
548static const struct snd_kcontrol_new spkoutr_mux =
549 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
550
551static const struct soc_enum spkoutl_enum =
552 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
553
554static const struct snd_kcontrol_new spkoutl_mux =
555 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
556
557static const struct soc_enum hpoutr_enum =
558 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
559
560static const struct snd_kcontrol_new hpoutr_mux =
561 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
562
563static const struct soc_enum hpoutl_enum =
564 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
565
566static const struct snd_kcontrol_new hpoutl_mux =
567 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
568
569static const struct snd_kcontrol_new inpgal[] = {
570SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
571SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
572SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
573SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
574};
575
576static const struct snd_kcontrol_new inpgar[] = {
577SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
578SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
579SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
580SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
581};
582
583static const struct snd_kcontrol_new mixinl[] = {
584SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
585SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
586SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
587};
588
589static const struct snd_kcontrol_new mixinr[] = {
590SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
591SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
592SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
593};
594
595static const struct snd_kcontrol_new hpmixl[] = {
596SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
597SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
598SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
599SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
600SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
601SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
602};
603
604static const struct snd_kcontrol_new hpmixr[] = {
605SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
606SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
607SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
608SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
609SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
610SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
611};
612
613static const struct snd_kcontrol_new spkmixl[] = {
614SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
615SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
616SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
617SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
618SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
619SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
620};
621
622static const struct snd_kcontrol_new spkmixr[] = {
623SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
624SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
625SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
626SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
627SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
628SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
629};
630
631static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
632SND_SOC_DAPM_INPUT("IN1L"),
633SND_SOC_DAPM_INPUT("IN1R"),
634SND_SOC_DAPM_INPUT("IN2L"),
635SND_SOC_DAPM_INPUT("IN2R"),
636SND_SOC_DAPM_INPUT("IN3L"),
637SND_SOC_DAPM_INPUT("IN3R"),
638SND_SOC_DAPM_INPUT("IN4L"),
639SND_SOC_DAPM_INPUT("IN4R"),
640SND_SOC_DAPM_INPUT("Beep"),
641
a4f28c00
MB		 642SND_SOC_DAPM_MICBIAS("MICBIAS", WM8962_PWR_MGMT_1, 1, 0),
643
9a76f1ff
MB		 644SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
645SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event,
646 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
647SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
648 SND_SOC_DAPM_POST_PMU),
649SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
650
651SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
652 inpgal, ARRAY_SIZE(inpgal)),
653SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
654 inpgar, ARRAY_SIZE(inpgar)),
655SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
656 mixinl, ARRAY_SIZE(mixinl)),
657SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
658 mixinr, ARRAY_SIZE(mixinr)),
659
660SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
661SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
662
663SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
664SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
665
666SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
667SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
668
669SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
670SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
671
672SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
673 hpmixl, ARRAY_SIZE(hpmixl)),
674SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
675 hpmixr, ARRAY_SIZE(hpmixr)),
676
677SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
678 out_pga_event, SND_SOC_DAPM_POST_PMU),
679SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
680 out_pga_event, SND_SOC_DAPM_POST_PMU),
681
682SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
683 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
684
685SND_SOC_DAPM_OUTPUT("HPOUTL"),
686SND_SOC_DAPM_OUTPUT("HPOUTR"),
687};
688
689static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
690SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
691 spkmixl, ARRAY_SIZE(spkmixl)),
692SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
693 out_pga_event, SND_SOC_DAPM_POST_PMU),
694SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
695SND_SOC_DAPM_OUTPUT("SPKOUT"),
696};
697
698static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
699SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
700 spkmixl, ARRAY_SIZE(spkmixl)),
701SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
702 spkmixr, ARRAY_SIZE(spkmixr)),
703
704SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
705 out_pga_event, SND_SOC_DAPM_POST_PMU),
706SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
707 out_pga_event, SND_SOC_DAPM_POST_PMU),
708
709SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
710SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
711
712SND_SOC_DAPM_OUTPUT("SPKOUTL"),
713SND_SOC_DAPM_OUTPUT("SPKOUTR"),
714};
715
716static const struct snd_soc_dapm_route wm8962_intercon[] = {
717 { "INPGAL", "IN1L Switch", "IN1L" },
718 { "INPGAL", "IN2L Switch", "IN2L" },
719 { "INPGAL", "IN3L Switch", "IN3L" },
720 { "INPGAL", "IN4L Switch", "IN4L" },
721
722 { "INPGAR", "IN1R Switch", "IN1R" },
723 { "INPGAR", "IN2R Switch", "IN2R" },
724 { "INPGAR", "IN3R Switch", "IN3R" },
725 { "INPGAR", "IN4R Switch", "IN4R" },
726
727 { "MIXINL", "IN2L Switch", "IN2L" },
728 { "MIXINL", "IN3L Switch", "IN3L" },
729 { "MIXINL", "PGA Switch", "INPGAL" },
730
731 { "MIXINR", "IN2R Switch", "IN2R" },
732 { "MIXINR", "IN3R Switch", "IN3R" },
733 { "MIXINR", "PGA Switch", "INPGAR" },
734
735 { "ADCL", NULL, "SYSCLK" },
736 { "ADCL", NULL, "TOCLK" },
737 { "ADCL", NULL, "MIXINL" },
738
739 { "ADCR", NULL, "SYSCLK" },
740 { "ADCR", NULL, "TOCLK" },
741 { "ADCR", NULL, "MIXINR" },
742
743 { "STL", "Left", "ADCL" },
744 { "STL", "Right", "ADCR" },
745
746 { "STR", "Left", "ADCL" },
747 { "STR", "Right", "ADCR" },
748
749 { "DACL", NULL, "SYSCLK" },
750 { "DACL", NULL, "TOCLK" },
751 { "DACL", NULL, "Beep" },
752 { "DACL", NULL, "STL" },
753
754 { "DACR", NULL, "SYSCLK" },
755 { "DACR", NULL, "TOCLK" },
756 { "DACR", NULL, "Beep" },
757 { "DACR", NULL, "STR" },
758
759 { "HPMIXL", "IN4L Switch", "IN4L" },
760 { "HPMIXL", "IN4R Switch", "IN4R" },
761 { "HPMIXL", "DACL Switch", "DACL" },
762 { "HPMIXL", "DACR Switch", "DACR" },
763 { "HPMIXL", "MIXINL Switch", "MIXINL" },
764 { "HPMIXL", "MIXINR Switch", "MIXINR" },
765
766 { "HPMIXR", "IN4L Switch", "IN4L" },
767 { "HPMIXR", "IN4R Switch", "IN4R" },
768 { "HPMIXR", "DACL Switch", "DACL" },
769 { "HPMIXR", "DACR Switch", "DACR" },
770 { "HPMIXR", "MIXINL Switch", "MIXINL" },
771 { "HPMIXR", "MIXINR Switch", "MIXINR" },
772
773 { "Left Bypass", NULL, "HPMIXL" },
774 { "Left Bypass", NULL, "Class G" },
775
776 { "Right Bypass", NULL, "HPMIXR" },
777 { "Right Bypass", NULL, "Class G" },
778
779 { "HPOUTL PGA", "Mixer", "Left Bypass" },
780 { "HPOUTL PGA", "DAC", "DACL" },
781
782 { "HPOUTR PGA", "Mixer", "Right Bypass" },
783 { "HPOUTR PGA", "DAC", "DACR" },
784
785 { "HPOUT", NULL, "HPOUTL PGA" },
786 { "HPOUT", NULL, "HPOUTR PGA" },
787 { "HPOUT", NULL, "Charge Pump" },
788 { "HPOUT", NULL, "SYSCLK" },
789 { "HPOUT", NULL, "TOCLK" },
790
791 { "HPOUTL", NULL, "HPOUT" },
792 { "HPOUTR", NULL, "HPOUT" },
793};
794
795static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
796 { "Speaker Mixer", "IN4L Switch", "IN4L" },
797 { "Speaker Mixer", "IN4R Switch", "IN4R" },
798 { "Speaker Mixer", "DACL Switch", "DACL" },
799 { "Speaker Mixer", "DACR Switch", "DACR" },
800 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
801 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
802
803 { "Speaker PGA", "Mixer", "Speaker Mixer" },
804 { "Speaker PGA", "DAC", "DACL" },
805
806 { "Speaker Output", NULL, "Speaker PGA" },
807 { "Speaker Output", NULL, "SYSCLK" },
808 { "Speaker Output", NULL, "TOCLK" },
809
810 { "SPKOUT", NULL, "Speaker Output" },
811};
812
813static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
814 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
815 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
816 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
817 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
818 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
819 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
820
821 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
822 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
823 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
824 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
825 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
826 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
827
828 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
829 { "SPKOUTL PGA", "DAC", "DACL" },
830
831 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
832 { "SPKOUTR PGA", "DAC", "DACR" },
833
834 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
835 { "SPKOUTL Output", NULL, "SYSCLK" },
836 { "SPKOUTL Output", NULL, "TOCLK" },
837
838 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
839 { "SPKOUTR Output", NULL, "SYSCLK" },
840 { "SPKOUTR Output", NULL, "TOCLK" },
841
842 { "SPKOUTL", NULL, "SPKOUTL Output" },
843 { "SPKOUTR", NULL, "SPKOUTR Output" },
844};
845
846static int wm8962_add_widgets(struct snd_soc_codec *codec)
847{
848 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
849
850 snd_soc_add_controls(codec, wm8962_snd_controls,
851 ARRAY_SIZE(wm8962_snd_controls));
852 if (pdata && pdata->spk_mono)
853 snd_soc_add_controls(codec, wm8962_spk_mono_controls,
854 ARRAY_SIZE(wm8962_spk_mono_controls));
855 else
856 snd_soc_add_controls(codec, wm8962_spk_stereo_controls,
857 ARRAY_SIZE(wm8962_spk_stereo_controls));
858
859
860 snd_soc_dapm_new_controls(codec, wm8962_dapm_widgets,
861 ARRAY_SIZE(wm8962_dapm_widgets));
862 if (pdata && pdata->spk_mono)
863 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_mono_widgets,
864 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
865 else
866 snd_soc_dapm_new_controls(codec, wm8962_dapm_spk_stereo_widgets,
867 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
868
869 snd_soc_dapm_add_routes(codec, wm8962_intercon,
870 ARRAY_SIZE(wm8962_intercon));
871 if (pdata && pdata->spk_mono)
872 snd_soc_dapm_add_routes(codec, wm8962_spk_mono_intercon,
873 ARRAY_SIZE(wm8962_spk_mono_intercon));
874 else
875 snd_soc_dapm_add_routes(codec, wm8962_spk_stereo_intercon,
876 ARRAY_SIZE(wm8962_spk_stereo_intercon));
877
878
879 snd_soc_dapm_disable_pin(codec, "Beep");
880
881 return 0;
882}
883
884static void wm8962_sync_cache(struct snd_soc_codec *codec)
885{
886 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
887 int i;
888
889 if (!codec->cache_sync)
890 return;
891
892 dev_dbg(codec->dev, "Syncing cache\n");
893
894 codec->cache_only = 0;
895
896 /* Sync back cached values if they're different from the
897 * hardware default.
898 */
899 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
900 if (i == WM8962_SOFTWARE_RESET)
901 continue;
902 if (wm8962->reg_cache[i] == wm8962_reg[i])
903 continue;
904
905 snd_soc_write(codec, i, wm8962->reg_cache[i]);
906 }
907
908 codec->cache_sync = 0;
909}
910
911/* -1 for reserved values */
912static const int bclk_divs[] = {
913 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
914};
915
916static void wm8962_configure_bclk(struct snd_soc_codec *codec)
917{
918 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
919 int dspclk, i;
920 int clocking2 = 0;
921 int aif2 = 0;
922
9a76f1ff
MB		 923 if (!wm8962->bclk) {
924 dev_dbg(codec->dev, "No BCLK rate configured\n");
925 return;
926 }
927
928 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
929 if (dspclk < 0) {
930 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
931 return;
932 }
933
934 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
935 switch (dspclk) {
936 case 0:
937 dspclk = wm8962->sysclk_rate;
938 break;
939 case 1:
940 dspclk = wm8962->sysclk_rate / 2;
941 break;
942 case 2:
943 dspclk = wm8962->sysclk_rate / 4;
944 break;
945 default:
946 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
947 dspclk = wm8962->sysclk;
948 }
949
950 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
951
952 /* We're expecting an exact match */
953 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
954 if (bclk_divs[i] < 0)
955 continue;
956
957 if (dspclk / bclk_divs[i] == wm8962->bclk) {
958 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
959 bclk_divs[i], wm8962->bclk);
960 clocking2 |= i;
961 break;
962 }
963 }
964 if (i == ARRAY_SIZE(bclk_divs)) {
965 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
966 dspclk / wm8962->bclk);
967 return;
968 }
969
970 aif2 |= wm8962->bclk / wm8962->lrclk;
971 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
972 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
973
974 snd_soc_update_bits(codec, WM8962_CLOCKING2,
975 WM8962_BCLK_DIV_MASK, clocking2);
976 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
977 WM8962_AIF_RATE_MASK, aif2);
978}
979
980static int wm8962_set_bias_level(struct snd_soc_codec *codec,
981 enum snd_soc_bias_level level)
982{
983 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
984 int ret;
985
986 if (level == codec->bias_level)
987 return 0;
988
989 switch (level) {
990 case SND_SOC_BIAS_ON:
991 break;
992
993 case SND_SOC_BIAS_PREPARE:
994 /* VMID 2*50k */
995 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
996 WM8962_VMID_SEL_MASK, 0x80);
997 break;
998
999 case SND_SOC_BIAS_STANDBY:
1000 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1001 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
1002 wm8962->supplies);
1003 if (ret != 0) {
1004 dev_err(codec->dev,
1005 "Failed to enable supplies: %d\n",
1006 ret);
1007 return ret;
1008 }
1009
1010 wm8962_sync_cache(codec);
1011
1012 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1013 WM8962_STARTUP_BIAS_ENA |
1014 WM8962_VMID_BUF_ENA,
1015 WM8962_STARTUP_BIAS_ENA |
1016 WM8962_VMID_BUF_ENA);
1017
1018 /* Bias enable at 2*50k for ramp */
1019 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1020 WM8962_VMID_SEL_MASK |
1021 WM8962_BIAS_ENA,
1022 WM8962_BIAS_ENA | 0x180);
1023
1024 msleep(5);
1025
1026 snd_soc_update_bits(codec, WM8962_CLOCKING2,
1027 WM8962_CLKREG_OVD,
1028 WM8962_CLKREG_OVD);
1029
1030 wm8962_configure_bclk(codec);
1031 }
1032
1033 /* VMID 2*250k */
1034 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1035 WM8962_VMID_SEL_MASK, 0x100);
1036 break;
1037
1038 case SND_SOC_BIAS_OFF:
1039 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
1040 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
1041
1042 snd_soc_update_bits(codec, WM8962_ANTI_POP,
1043 WM8962_STARTUP_BIAS_ENA |
1044 WM8962_VMID_BUF_ENA, 0);
1045
1046 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
1047 wm8962->supplies);
1048 break;
1049 }
1050 codec->bias_level = level;
1051 return 0;
1052}
1053
1054static const struct {
1055 int rate;
1056 int reg;
1057} sr_vals[] = {
1058 { 48000, 0 },
1059 { 44100, 0 },
1060 { 32000, 1 },
1061 { 22050, 2 },
1062 { 24000, 2 },
1063 { 16000, 3 },
1064 { 11025, 4 },
1065 { 12000, 4 },
1066 { 8000, 5 },
1067 { 88200, 6 },
1068 { 96000, 6 },
1069};
1070
1071static const int sysclk_rates[] = {
1072 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536,
1073};
1074
1075static int wm8962_hw_params(struct snd_pcm_substream *substream,
1076 struct snd_pcm_hw_params *params,
1077 struct snd_soc_dai *dai)
1078{
1079 struct snd_soc_pcm_runtime *rtd = substream->private_data;
54d8d0ae 1080 struct snd_soc_codec *codec = rtd->codec;
9a76f1ff
MB		 1081 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1082 int rate = params_rate(params);
1083 int i;
1084 int aif0 = 0;
1085 int adctl3 = 0;
1086 int clocking4 = 0;
1087
1088 wm8962->bclk = snd_soc_params_to_bclk(params);
1089 wm8962->lrclk = params_rate(params);
1090
1091 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
1092 if (sr_vals[i].rate == rate) {
1093 adctl3 |= sr_vals[i].reg;
1094 break;
1095 }
1096 }
1097 if (i == ARRAY_SIZE(sr_vals)) {
1098 dev_err(codec->dev, "Unsupported rate %dHz\n", rate);
1099 return -EINVAL;
1100 }
1101
1102 if (rate % 8000 == 0)
1103 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
1104
1105 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
1106 if (sysclk_rates[i] == wm8962->sysclk_rate / rate) {
1107 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
1108 break;
1109 }
1110 }
1111 if (i == ARRAY_SIZE(sysclk_rates)) {
1112 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
1113 wm8962->sysclk_rate / rate);
1114 return -EINVAL;
1115 }
1116
1117 switch (params_format(params)) {
1118 case SNDRV_PCM_FORMAT_S16_LE:
1119 break;
1120 case SNDRV_PCM_FORMAT_S20_3LE:
1121 aif0 |= 0x40;
1122 break;
1123 case SNDRV_PCM_FORMAT_S24_LE:
1124 aif0 |= 0x80;
1125 break;
1126 case SNDRV_PCM_FORMAT_S32_LE:
1127 aif0 |= 0xc0;
1128 break;
1129 default:
1130 return -EINVAL;
1131 }
1132
1133 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1134 WM8962_WL_MASK, aif0);
1135 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
1136 WM8962_SAMPLE_RATE_INT_MODE |
1137 WM8962_SAMPLE_RATE_MASK, adctl3);
1138 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
1139 WM8962_SYSCLK_RATE_MASK, clocking4);
1140
1141 wm8962_configure_bclk(codec);
1142
1143 return 0;
1144}
1145
1146static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
1147 unsigned int freq, int dir)
1148{
1149 struct snd_soc_codec *codec = dai->codec;
1150 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1151 int src;
1152
1153 switch (clk_id) {
1154 case WM8962_SYSCLK_MCLK:
1155 wm8962->sysclk = WM8962_SYSCLK_MCLK;
1156 src = 0;
1157 break;
1158 case WM8962_SYSCLK_FLL:
1159 wm8962->sysclk = WM8962_SYSCLK_FLL;
1160 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
1161 WARN_ON(freq != wm8962->fll_fout);
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166
1167 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
1168 src);
1169
1170 wm8962->sysclk_rate = freq;
1171
1172 return 0;
1173}
1174
1175static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1176{
1177 struct snd_soc_codec *codec = dai->codec;
1178 int aif0 = 0;
1179
1180 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1181 case SND_SOC_DAIFMT_DSP_A:
1182 aif0 |= WM8962_LRCLK_INV;
1183 case SND_SOC_DAIFMT_DSP_B:
1184 aif0 |= 3;
1185
1186 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1187 case SND_SOC_DAIFMT_NB_NF:
1188 case SND_SOC_DAIFMT_IB_NF:
1189 break;
1190 default:
1191 return -EINVAL;
1192 }
1193 break;
1194
1195 case SND_SOC_DAIFMT_RIGHT_J:
1196 break;
1197 case SND_SOC_DAIFMT_LEFT_J:
1198 aif0 |= 1;
1199 break;
1200 case SND_SOC_DAIFMT_I2S:
1201 aif0 |= 2;
1202 break;
1203 default:
1204 return -EINVAL;
1205 }
1206
1207 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1208 case SND_SOC_DAIFMT_NB_NF:
1209 break;
1210 case SND_SOC_DAIFMT_IB_NF:
1211 aif0 |= WM8962_BCLK_INV;
1212 break;
1213 case SND_SOC_DAIFMT_NB_IF:
1214 aif0 |= WM8962_LRCLK_INV;
1215 break;
1216 case SND_SOC_DAIFMT_IB_IF:
1217 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
1218 break;
1219 default:
1220 return -EINVAL;
1221 }
1222
1223 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1224 case SND_SOC_DAIFMT_CBM_CFM:
1225 aif0 |= WM8962_MSTR;
1226 break;
1227 case SND_SOC_DAIFMT_CBS_CFS:
1228 break;
1229 default:
1230 return -EINVAL;
1231 }
1232
1233 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
1234 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
1235 WM8962_LRCLK_INV, aif0);
1236
1237 return 0;
1238}
1239
1240struct _fll_div {
1241 u16 fll_fratio;
1242 u16 fll_outdiv;
1243 u16 fll_refclk_div;
1244 u16 n;
1245 u16 theta;
1246 u16 lambda;
1247};
1248
1249/* The size in bits of the FLL divide multiplied by 10
1250 * to allow rounding later */
1251#define FIXED_FLL_SIZE ((1 << 16) * 10)
1252
1253static struct {
1254 unsigned int min;
1255 unsigned int max;
1256 u16 fll_fratio;
1257 int ratio;
1258} fll_fratios[] = {
1259 { 0, 64000, 4, 16 },
1260 { 64000, 128000, 3, 8 },
1261 { 128000, 256000, 2, 4 },
1262 { 256000, 1000000, 1, 2 },
1263 { 1000000, 13500000, 0, 1 },
1264};
1265
1266static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1267 unsigned int Fout)
1268{
1269 unsigned int target;
1270 unsigned int div;
1271 unsigned int fratio, gcd_fll;
1272 int i;
1273
1274 /* Fref must be <=13.5MHz */
1275 div = 1;
1276 fll_div->fll_refclk_div = 0;
1277 while ((Fref / div) > 13500000) {
1278 div *= 2;
1279 fll_div->fll_refclk_div++;
1280
1281 if (div > 4) {
1282 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1283 Fref);
1284 return -EINVAL;
1285 }
1286 }
1287
1288 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1289
1290 /* Apply the division for our remaining calculations */
1291 Fref /= div;
1292
1293 /* Fvco should be 90-100MHz; don't check the upper bound */
1294 div = 2;
1295 while (Fout * div < 90000000) {
1296 div++;
1297 if (div > 64) {
1298 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1299 Fout);
1300 return -EINVAL;
1301 }
1302 }
1303 target = Fout * div;
1304 fll_div->fll_outdiv = div - 1;
1305
1306 pr_debug("FLL Fvco=%dHz\n", target);
1307
1308 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1309 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1310 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1311 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1312 fratio = fll_fratios[i].ratio;
1313 break;
1314 }
1315 }
1316 if (i == ARRAY_SIZE(fll_fratios)) {
1317 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1318 return -EINVAL;
1319 }
1320
1321 fll_div->n = target / (fratio * Fref);
1322
1323 if (target % Fref == 0) {
1324 fll_div->theta = 0;
1325 fll_div->lambda = 0;
1326 } else {
1327 gcd_fll = gcd(target, fratio * Fref);
1328
1329 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1330 / gcd_fll;
1331 fll_div->lambda = (fratio * Fref) / gcd_fll;
1332 }
1333
1334 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1335 fll_div->n, fll_div->theta, fll_div->lambda);
1336 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1337 fll_div->fll_fratio, fll_div->fll_outdiv,
1338 fll_div->fll_refclk_div);
1339
1340 return 0;
1341}
1342
1343static int wm8962_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
1344 unsigned int Fref, unsigned int Fout)
1345{
1346 struct snd_soc_codec *codec = dai->codec;
1347 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1348 struct _fll_div fll_div;
1349 int ret;
61371126 1350 int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA;
9a76f1ff
MB		 1351
1352 /* Any change? */
1353 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
1354 Fout == wm8962->fll_fout)
1355 return 0;
1356
1357 if (Fout == 0) {
1358 dev_dbg(codec->dev, "FLL disabled\n");
1359
1360 wm8962->fll_fref = 0;
1361 wm8962->fll_fout = 0;
1362
1363 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1364 WM8962_FLL_ENA, 0);
1365
1366 return 0;
1367 }
1368
1369 ret = fll_factors(&fll_div, Fref, Fout);
1370 if (ret != 0)
1371 return ret;
1372
1373 switch (fll_id) {
1374 case WM8962_FLL_MCLK:
1375 case WM8962_FLL_BCLK:
1376 case WM8962_FLL_OSC:
1377 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
1378 break;
1379 case WM8962_FLL_INT:
1380 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1381 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
1382 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
1383 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
1384 break;
1385 default:
1386 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
1387 return -EINVAL;
1388 }
1389
1390 if (fll_div.theta || fll_div.lambda)
1391 fll1 |= WM8962_FLL_FRAC;
1392
1393 /* Stop the FLL while we reconfigure */
1394 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
1395
1396 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
1397 WM8962_FLL_OUTDIV_MASK |
1398 WM8962_FLL_REFCLK_DIV_MASK,
1399 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
1400 (fll_div.fll_refclk_div));
1401
1402 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
1403 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
1404
1405 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
1406 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
1407 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
1408
1409 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
1410 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
1411 WM8962_FLL_ENA, fll1);
1412
1413 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
1414
1415 wm8962->fll_fref = Fref;
1416 wm8962->fll_fout = Fout;
1417 wm8962->fll_src = source;
1418
1419 return 0;
1420}
1421
1422static int wm8962_mute(struct snd_soc_dai *dai, int mute)
1423{
1424 struct snd_soc_codec *codec = dai->codec;
1425 int val;
1426
1427 if (mute)
1428 val = WM8962_DAC_MUTE;
1429 else
1430 val = 0;
1431
1432 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1433 WM8962_DAC_MUTE, val);
1434}
1435
1436#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
1437
1438#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1439 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1440
1441static struct snd_soc_dai_ops wm8962_dai_ops = {
1442 .hw_params = wm8962_hw_params,
1443 .set_sysclk = wm8962_set_dai_sysclk,
1444 .set_fmt = wm8962_set_dai_fmt,
1445 .set_pll = wm8962_set_fll,
1446 .digital_mute = wm8962_mute,
1447};
1448
54d8d0ae
MB		 1449static struct snd_soc_dai_driver wm8962_dai = {
1450 .name = "wm8962",
9a76f1ff
MB		 1451 .playback = {
1452 .stream_name = "Playback",
1453 .channels_min = 2,
1454 .channels_max = 2,
1455 .rates = WM8962_RATES,
1456 .formats = WM8962_FORMATS,
1457 },
1458 .capture = {
1459 .stream_name = "Capture",
1460 .channels_min = 2,
1461 .channels_max = 2,
1462 .rates = WM8962_RATES,
1463 .formats = WM8962_FORMATS,
1464 },
1465 .ops = &wm8962_dai_ops,
1466 .symmetric_rates = 1,
1467};
9a76f1ff 1468
7711308a
MB		 1469static void wm8962_mic_work(struct work_struct *work)
1470{
1471 struct wm8962_priv *wm8962 = container_of(work,
1472 struct wm8962_priv,
1473 mic_work.work);
1474 struct snd_soc_codec *codec = wm8962->codec;
1475 int status = 0;
1476 int irq_pol = 0;
1477 int reg;
1478
1479 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
1480
1481 if (reg & WM8962_MICDET_STS) {
1482 status |= SND_JACK_MICROPHONE;
1483 irq_pol |= WM8962_MICD_IRQ_POL;
1484 }
1485
1486 if (reg & WM8962_MICSHORT_STS) {
1487 status |= SND_JACK_BTN_0;
1488 irq_pol |= WM8962_MICSCD_IRQ_POL;
1489 }
1490
1491 snd_soc_jack_report(wm8962->jack, status,
1492 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
1493
1494 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
1495 WM8962_MICSCD_IRQ_POL |
1496 WM8962_MICD_IRQ_POL, irq_pol);
1497}
1498
45e65504
MB		 1499static irqreturn_t wm8962_irq(int irq, void *data)
1500{
1501 struct snd_soc_codec *codec = data;
7711308a 1502 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
45e65504
MB		 1503 int mask;
1504 int active;
1505
1506 mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
1507
1508 active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2);
1509 active &= ~mask;
1510
1511 if (active & WM8962_FIFOS_ERR_EINT)
1512 dev_err(codec->dev, "FIFO error\n");
1513
1514 if (active & WM8962_TEMP_SHUT_EINT)
1515 dev_crit(codec->dev, "Thermal shutdown\n");
1516
7711308a
MB		 1517 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
1518 dev_dbg(codec->dev, "Microphone event detected\n");
1519
1520 schedule_delayed_work(&wm8962->mic_work,
1521 msecs_to_jiffies(250));
1522 }
1523
45e65504
MB		 1524 /* Acknowledge the interrupts */
1525 snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active);
1526
1527 return IRQ_HANDLED;
1528}
1529
7711308a
MB		 1530/**
1531 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ
1532 *
1533 * @codec: WM8962 codec
1534 * @jack: jack to report detection events on
1535 *
1536 * Enable microphone detection via IRQ on the WM8962. If GPIOs are
1537 * being used to bring out signals to the processor then only platform
1538 * data configuration is needed for WM8962 and processor GPIOs should
1539 * be configured using snd_soc_jack_add_gpios() instead.
1540 *
1541 * If no jack is supplied detection will be disabled.
1542 */
1543int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
1544{
1545 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1546 int irq_mask, enable;
1547
1548 wm8962->jack = jack;
1549 if (jack) {
1550 irq_mask = 0;
1551 enable = WM8962_MICDET_ENA;
1552 } else {
1553 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
1554 enable = 0;
1555 }
1556
1557 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
1558 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
1559 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
1560 WM8962_MICDET_ENA, enable);
1561
1562 /* Send an initial empty report */
1563 snd_soc_jack_report(wm8962->jack, 0,
1564 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
1565
1566 return 0;
1567}
1568EXPORT_SYMBOL_GPL(wm8962_mic_detect);
1569
9a76f1ff 1570#ifdef CONFIG_PM
54d8d0ae 1571static int wm8962_resume(struct snd_soc_codec *codec)
9a76f1ff 1572{
9a76f1ff
MB		 1573 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1574 u16 *reg_cache = codec->reg_cache;
1575 int i;
1576
1577 /* Restore the registers */
1578 for (i = 1; i < ARRAY_SIZE(wm8962->reg_cache); i++) {
1579 switch (i) {
1580 case WM8962_SOFTWARE_RESET:
1581 continue;
1582 default:
1583 break;
1584 }
1585
1586 if (reg_cache[i] != wm8962_reg[i])
1587 snd_soc_write(codec, i, reg_cache[i]);
1588 }
1589
1590 return 0;
1591}
1592#else
1593#define wm8962_resume NULL
1594#endif
1595
9a76f1ff
MB		 1596#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
1597static int beep_rates[] = {
1598 500, 1000, 2000, 4000,
1599};
1600
1601static void wm8962_beep_work(struct work_struct *work)
1602{
1603 struct wm8962_priv *wm8962 =
1604 container_of(work, struct wm8962_priv, beep_work);
54d8d0ae 1605 struct snd_soc_codec *codec = wm8962->codec;
9a76f1ff
MB		 1606 int i;
1607 int reg = 0;
1608 int best = 0;
1609
1610 if (wm8962->beep_rate) {
1611 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
1612 if (abs(wm8962->beep_rate - beep_rates[i]) <
1613 abs(wm8962->beep_rate - beep_rates[best]))
1614 best = i;
1615 }
1616
1617 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
1618 beep_rates[best], wm8962->beep_rate);
1619
1620 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
1621
1622 snd_soc_dapm_enable_pin(codec, "Beep");
1623 } else {
1624 dev_dbg(codec->dev, "Disabling beep\n");
1625 snd_soc_dapm_disable_pin(codec, "Beep");
1626 }
1627
1628 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
1629 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
1630
1631 snd_soc_dapm_sync(codec);
1632}
1633
1634/* For usability define a way of injecting beep events for the device -
1635 * many systems will not have a keyboard.
1636 */
1637static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
1638 unsigned int code, int hz)
1639{
1640 struct snd_soc_codec *codec = input_get_drvdata(dev);
1641 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1642
1643 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
1644
1645 switch (code) {
1646 case SND_BELL:
1647 if (hz)
1648 hz = 1000;
1649 case SND_TONE:
1650 break;
1651 default:
1652 return -1;
1653 }
1654
1655 /* Kick the beep from a workqueue */
1656 wm8962->beep_rate = hz;
1657 schedule_work(&wm8962->beep_work);
1658 return 0;
1659}
1660
1661static ssize_t wm8962_beep_set(struct device *dev,
1662 struct device_attribute *attr,
1663 const char *buf, size_t count)
1664{
1665 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
1666 long int time;
1667
1668 strict_strtol(buf, 10, &time);
1669
1670 input_event(wm8962->beep, EV_SND, SND_TONE, time);
1671
1672 return count;
1673}
1674
1675static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
1676
1677static void wm8962_init_beep(struct snd_soc_codec *codec)
1678{
1679 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1680 int ret;
1681
1682 wm8962->beep = input_allocate_device();
1683 if (!wm8962->beep) {
1684 dev_err(codec->dev, "Failed to allocate beep device\n");
1685 return;
1686 }
1687
1688 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
1689 wm8962->beep_rate = 0;
1690
1691 wm8962->beep->name = "WM8962 Beep Generator";
1692 wm8962->beep->phys = dev_name(codec->dev);
1693 wm8962->beep->id.bustype = BUS_I2C;
1694
1695 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
1696 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1697 wm8962->beep->event = wm8962_beep_event;
1698 wm8962->beep->dev.parent = codec->dev;
1699 input_set_drvdata(wm8962->beep, codec);
1700
1701 ret = input_register_device(wm8962->beep);
1702 if (ret != 0) {
1703 input_free_device(wm8962->beep);
1704 wm8962->beep = NULL;
1705 dev_err(codec->dev, "Failed to register beep device\n");
1706 }
1707
1708 ret = device_create_file(codec->dev, &dev_attr_beep);
1709 if (ret != 0) {
1710 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
1711 ret);
1712 }
1713}
1714
1715static void wm8962_free_beep(struct snd_soc_codec *codec)
1716{
1717 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1718
1719 device_remove_file(codec->dev, &dev_attr_beep);
1720 input_unregister_device(wm8962->beep);
1721 cancel_work_sync(&wm8962->beep_work);
1722 wm8962->beep = NULL;
1723
1724 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
1725}
1726#else
1727static void wm8962_init_beep(struct snd_soc_codec *codec)
1728{
1729}
1730
1731static void wm8962_free_beep(struct snd_soc_codec *codec)
1732{
1733}
1734#endif
1735
8ca2aa9c
MB		 1736static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
1737{
1738 int mask = 0;
1739 int val = 0;
1740
1741 /* Some of the GPIOs are behind MFP configuration and need to
1742 * be put into GPIO mode. */
1743 switch (gpio) {
1744 case 2:
1745 mask = WM8962_CLKOUT2_SEL_MASK;
1746 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
1747 break;
1748 case 3:
1749 mask = WM8962_CLKOUT3_SEL_MASK;
1750 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
1751 break;
1752 default:
1753 break;
1754 }
1755
1756 if (mask)
1757 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
1758 mask, val);
1759}
1760
3367b8d4
MB		 1761#ifdef CONFIG_GPIOLIB
1762static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
1763{
1764 return container_of(chip, struct wm8962_priv, gpio_chip);
1765}
1766
1767static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
1768{
1769 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
1770 struct snd_soc_codec *codec = wm8962->codec;
3367b8d4
MB		 1771
1772 /* The WM8962 GPIOs aren't linearly numbered. For simplicity
1773 * we export linear numbers and error out if the unsupported
1774 * ones are requsted.
1775 */
1776 switch (offset + 1) {
1777 case 2:
3367b8d4 1778 case 3:
3367b8d4
MB		 1779 case 5:
1780 case 6:
1781 break;
1782 default:
1783 return -EINVAL;
1784 }
1785
8ca2aa9c 1786 wm8962_set_gpio_mode(codec, offset + 1);
3367b8d4
MB		 1787
1788 return 0;
1789}
1790
1791static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1792{
1793 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
1794 struct snd_soc_codec *codec = wm8962->codec;
1795
1796 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
1797 WM8962_GP2_LVL, value << WM8962_GP2_LVL_SHIFT);
1798}
1799
1800static int wm8962_gpio_direction_out(struct gpio_chip *chip,
1801 unsigned offset, int value)
1802{
1803 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
1804 struct snd_soc_codec *codec = wm8962->codec;
1805 int val;
1806
1807 /* Force function 1 (logic output) */
1808 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
1809
1810 return snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
1811 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
1812}
1813
1814static struct gpio_chip wm8962_template_chip = {
1815 .label = "wm8962",
1816 .owner = THIS_MODULE,
1817 .request = wm8962_gpio_request,
1818 .direction_output = wm8962_gpio_direction_out,
1819 .set = wm8962_gpio_set,
1820 .can_sleep = 1,
1821};
1822
1823static void wm8962_init_gpio(struct snd_soc_codec *codec)
1824{
1825 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1826 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
1827 int ret;
1828
1829 wm8962->gpio_chip = wm8962_template_chip;
1830 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
1831 wm8962->gpio_chip.dev = codec->dev;
1832
1833 if (pdata && pdata->gpio_base)
1834 wm8962->gpio_chip.base = pdata->gpio_base;
1835 else
1836 wm8962->gpio_chip.base = -1;
1837
1838 ret = gpiochip_add(&wm8962->gpio_chip);
1839 if (ret != 0)
1840 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1841}
1842
1843static void wm8962_free_gpio(struct snd_soc_codec *codec)
1844{
1845 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1846 int ret;
1847
1848 ret = gpiochip_remove(&wm8962->gpio_chip);
1849 if (ret != 0)
1850 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1851}
1852#else
1853static void wm8962_init_gpio(struct snd_soc_codec *codec)
1854{
1855}
1856
1857static void wm8962_free_gpio(struct snd_soc_codec *codec)
1858{
1859}
1860#endif
1861
54d8d0ae 1862static int wm8962_probe(struct snd_soc_codec *codec)
9a76f1ff
MB		 1863{
1864 int ret;
54d8d0ae 1865 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
9a76f1ff 1866 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
45e65504
MB		 1867 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
1868 dev);
1869 int i, trigger, irq_pol;
9a76f1ff 1870
54d8d0ae 1871 wm8962->codec = codec;
7711308a 1872 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
9a76f1ff 1873
9a76f1ff
MB		 1874 codec->cache_sync = 1;
1875 codec->idle_bias_off = 1;
9a76f1ff 1876
54d8d0ae 1877 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
9a76f1ff
MB		 1878 if (ret != 0) {
1879 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1880 goto err;
1881 }
1882
1883 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
1884 wm8962->supplies[i].supply = wm8962_supply_names[i];
1885
1886 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8962->supplies),
1887 wm8962->supplies);
1888 if (ret != 0) {
1889 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1890 goto err;
1891 }
1892
1893 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
1894 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
1895 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
1896 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
1897 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
1898 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
1899 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
1900 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
1901
1902 /* This should really be moved into the regulator core */
1903 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
1904 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
1905 &wm8962->disable_nb[i]);
1906 if (ret != 0) {
1907 dev_err(codec->dev,
1908 "Failed to register regulator notifier: %d\n",
1909 ret);
1910 }
1911 }
1912
1913 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
1914 wm8962->supplies);
1915 if (ret != 0) {
1916 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
1917 goto err_get;
1918 }
1919
1920 ret = snd_soc_read(codec, WM8962_SOFTWARE_RESET);
1921 if (ret < 0) {
1922 dev_err(codec->dev, "Failed to read ID register\n");
1923 goto err_enable;
1924 }
1925 if (ret != wm8962_reg[WM8962_SOFTWARE_RESET]) {
1926 dev_err(codec->dev, "Device is not a WM8962, ID %x != %x\n",
1927 ret, wm8962_reg[WM8962_SOFTWARE_RESET]);
1928 ret = -EINVAL;
1929 goto err_enable;
1930 }
1931
1932 ret = snd_soc_read(codec, WM8962_RIGHT_INPUT_VOLUME);
1933 if (ret < 0) {
1934 dev_err(codec->dev, "Failed to read device revision: %d\n",
1935 ret);
1936 goto err_enable;
1937 }
1938
1939 dev_info(codec->dev, "customer id %x revision %c\n",
1940 (ret & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
1941 ((ret & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
1942 + 'A');
1943
1944 ret = wm8962_reset(codec);
1945 if (ret < 0) {
1946 dev_err(codec->dev, "Failed to issue reset\n");
1947 goto err_enable;
1948 }
1949
1950 /* SYSCLK defaults to on; make sure it is off so we can safely
1951 * write to registers if the device is declocked.
1952 */
1953 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
1954
1955 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
1956
1957 if (pdata) {
1958 /* Apply static configuration for GPIOs */
1959 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
8ca2aa9c
MB		 1960 if (pdata->gpio_init[i]) {
1961 wm8962_set_gpio_mode(codec, i + 1);
9a76f1ff
MB		 1962 snd_soc_write(codec, 0x200 + i,
1963 pdata->gpio_init[i] & 0xffff);
8ca2aa9c 1964 }
9a76f1ff
MB		 1965
1966 /* Put the speakers into mono mode? */
1967 if (pdata->spk_mono)
1968 wm8962->reg_cache[WM8962_CLASS_D_CONTROL_2]
1969 |= WM8962_SPK_MONO;
a4f28c00
MB		 1970
1971 /* Micbias setup, detection enable and detection
1972 * threasholds. */
1973 if (pdata->mic_cfg)
1974 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
1975 WM8962_MICDET_ENA |
1976 WM8962_MICDET_THR_MASK |
1977 WM8962_MICSHORT_THR_MASK |
1978 WM8962_MICBIAS_LVL,
1979 pdata->mic_cfg);
9a76f1ff
MB		 1980 }
1981
1982 /* Latch volume update bits */
1983 wm8962->reg_cache[WM8962_LEFT_INPUT_VOLUME] |= WM8962_IN_VU;
1984 wm8962->reg_cache[WM8962_RIGHT_INPUT_VOLUME] |= WM8962_IN_VU;
1985 wm8962->reg_cache[WM8962_LEFT_ADC_VOLUME] |= WM8962_ADC_VU;
1986 wm8962->reg_cache[WM8962_RIGHT_ADC_VOLUME] |= WM8962_ADC_VU;
1987 wm8962->reg_cache[WM8962_LEFT_DAC_VOLUME] |= WM8962_DAC_VU;
1988 wm8962->reg_cache[WM8962_RIGHT_DAC_VOLUME] |= WM8962_DAC_VU;
1989 wm8962->reg_cache[WM8962_SPKOUTL_VOLUME] |= WM8962_SPKOUT_VU;
1990 wm8962->reg_cache[WM8962_SPKOUTR_VOLUME] |= WM8962_SPKOUT_VU;
1991 wm8962->reg_cache[WM8962_HPOUTL_VOLUME] |= WM8962_HPOUT_VU;
1992 wm8962->reg_cache[WM8962_HPOUTR_VOLUME] |= WM8962_HPOUT_VU;
1993
54d8d0ae 1994 wm8962_add_widgets(codec);
9a76f1ff
MB		 1995
1996 wm8962_init_beep(codec);
3367b8d4 1997 wm8962_init_gpio(codec);
9a76f1ff 1998
45e65504
MB		 1999 if (i2c->irq) {
2000 if (pdata && pdata->irq_active_low) {
2001 trigger = IRQF_TRIGGER_LOW;
2002 irq_pol = WM8962_IRQ_POL;
2003 } else {
2004 trigger = IRQF_TRIGGER_HIGH;
2005 irq_pol = 0;
2006 }
2007
2008 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
2009 WM8962_IRQ_POL, irq_pol);
2010
2011 ret = request_threaded_irq(i2c->irq, NULL, wm8962_irq,
2012 trigger | IRQF_ONESHOT,
2013 "wm8962", codec);
2014 if (ret != 0) {
2015 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
2016 i2c->irq, ret);
2017 /* Non-fatal */
2018 } else {
2019 /* Enable error reporting IRQs by default */
2020 snd_soc_update_bits(codec,
2021 WM8962_INTERRUPT_STATUS_2_MASK,
2022 WM8962_TEMP_SHUT_EINT |
2023 WM8962_FIFOS_ERR_EINT, 0);
2024 }
2025 }
2026
9a76f1ff
MB		 2027 return 0;
2028
2029err_enable:
2030 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
2031err_get:
2032 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
2033err:
2034 kfree(wm8962);
2035 return ret;
2036}
2037
54d8d0ae 2038static int wm8962_remove(struct snd_soc_codec *codec)
9a76f1ff 2039{
54d8d0ae 2040 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
45e65504
MB		 2041 struct i2c_client *i2c = container_of(codec->dev, struct i2c_client,
2042 dev);
9a76f1ff
MB		 2043 int i;
2044
45e65504
MB		 2045 if (i2c->irq)
2046 free_irq(i2c->irq, codec);
2047
7711308a
MB		 2048 cancel_delayed_work_sync(&wm8962->mic_work);
2049
3367b8d4 2050 wm8962_free_gpio(codec);
54d8d0ae 2051 wm8962_free_beep(codec);
9a76f1ff
MB		 2052 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
2053 regulator_unregister_notifier(wm8962->supplies[i].consumer,
2054 &wm8962->disable_nb[i]);
2055 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
54d8d0ae
MB		 2056
2057 return 0;
9a76f1ff
MB		 2058}
2059
54d8d0ae
MB		 2060static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
2061 .probe = wm8962_probe,
2062 .remove = wm8962_remove,
2063 .resume = wm8962_resume,
2064 .set_bias_level = wm8962_set_bias_level,
6946e037 2065 .reg_cache_size = WM8962_MAX_REGISTER + 1,
54d8d0ae
MB		 2066 .reg_word_size = sizeof(u16),
2067 .reg_cache_default = wm8962_reg,
2068 .volatile_register = wm8962_volatile_register,
2069 .readable_register = wm8962_readable_register,
2070};
2071
9a76f1ff
MB		 2072#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2073static __devinit int wm8962_i2c_probe(struct i2c_client *i2c,
2074 const struct i2c_device_id *id)
2075{
2076 struct wm8962_priv *wm8962;
54d8d0ae 2077 int ret;
9a76f1ff
MB		 2078
2079 wm8962 = kzalloc(sizeof(struct wm8962_priv), GFP_KERNEL);
2080 if (wm8962 == NULL)
2081 return -ENOMEM;
2082
9a76f1ff 2083 i2c_set_clientdata(i2c, wm8962);
9a76f1ff 2084
54d8d0ae
MB		 2085 ret = snd_soc_register_codec(&i2c->dev,
2086 &soc_codec_dev_wm8962, &wm8962_dai, 1);
2087 if (ret < 0)
2088 kfree(wm8962);
9a76f1ff 2089
54d8d0ae 2090 return ret;
9a76f1ff
MB		 2091}
2092
2093static __devexit int wm8962_i2c_remove(struct i2c_client *client)
2094{
54d8d0ae
MB		 2095 snd_soc_unregister_codec(&client->dev);
2096 kfree(i2c_get_clientdata(client));
9a76f1ff
MB		 2097 return 0;
2098}
2099
2100static const struct i2c_device_id wm8962_i2c_id[] = {
2101 { "wm8962", 0 },
2102 { }
2103};
2104MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
2105
2106static struct i2c_driver wm8962_i2c_driver = {
2107 .driver = {
ea738bad 2108 .name = "wm8962",
9a76f1ff
MB		 2109 .owner = THIS_MODULE,
2110 },
2111 .probe = wm8962_i2c_probe,
2112 .remove = __devexit_p(wm8962_i2c_remove),
2113 .id_table = wm8962_i2c_id,
2114};
2115#endif
2116
2117static int __init wm8962_modinit(void)
2118{
2119 int ret;
2120#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2121 ret = i2c_add_driver(&wm8962_i2c_driver);
2122 if (ret != 0) {
2123 printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n",
2124 ret);
2125 }
2126#endif
2127 return 0;
2128}
2129module_init(wm8962_modinit);
2130
2131static void __exit wm8962_exit(void)
2132{
2133#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2134 i2c_del_driver(&wm8962_i2c_driver);
2135#endif
2136}
2137module_exit(wm8962_exit);
2138
2139MODULE_DESCRIPTION("ASoC WM8962 driver");
2140MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2141MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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