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ASoC: Convert wm8978 to table based DAPM and control init
[deliverable/linux.git] / sound / soc / codecs / wm8978.c
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0d34e915
GL		 1/*
2 * wm8978.c -- WM8978 ALSA SoC Audio Codec driver
3 *
4 * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 * Copyright (C) 2007 Carlos Munoz <carlos@kenati.com>
6 * Copyright 2006-2009 Wolfson Microelectronics PLC.
7 * Based on wm8974 and wm8990 by Liam Girdwood <lrg@slimlogic.co.uk>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
5a0e3ad6 21#include <linux/slab.h>
0d34e915
GL		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
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GL		 26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <asm/div64.h>
29
30#include "wm8978.h"
31
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GL		 32/* wm8978 register cache. Note that register 0 is not included in the cache. */
33static const u16 wm8978_reg[WM8978_CACHEREGNUM] = {
34 0x0000, 0x0000, 0x0000, 0x0000, /* 0x00...0x03 */
35 0x0050, 0x0000, 0x0140, 0x0000, /* 0x04...0x07 */
36 0x0000, 0x0000, 0x0000, 0x00ff, /* 0x08...0x0b */
37 0x00ff, 0x0000, 0x0100, 0x00ff, /* 0x0c...0x0f */
38 0x00ff, 0x0000, 0x012c, 0x002c, /* 0x10...0x13 */
39 0x002c, 0x002c, 0x002c, 0x0000, /* 0x14...0x17 */
40 0x0032, 0x0000, 0x0000, 0x0000, /* 0x18...0x1b */
41 0x0000, 0x0000, 0x0000, 0x0000, /* 0x1c...0x1f */
42 0x0038, 0x000b, 0x0032, 0x0000, /* 0x20...0x23 */
43 0x0008, 0x000c, 0x0093, 0x00e9, /* 0x24...0x27 */
44 0x0000, 0x0000, 0x0000, 0x0000, /* 0x28...0x2b */
45 0x0033, 0x0010, 0x0010, 0x0100, /* 0x2c...0x2f */
46 0x0100, 0x0002, 0x0001, 0x0001, /* 0x30...0x33 */
47 0x0039, 0x0039, 0x0039, 0x0039, /* 0x34...0x37 */
48 0x0001, 0x0001, /* 0x38...0x3b */
49};
50
51/* codec private data */
52struct wm8978_priv {
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GL		 53 unsigned int f_pllout;
54 unsigned int f_mclk;
55 unsigned int f_256fs;
56 unsigned int f_opclk;
b0580913 57 int mclk_idx;
0d34e915 58 enum wm8978_sysclk_src sysclk;
0d34e915
GL		 59};
60
61static const char *wm8978_companding[] = {"Off", "NC", "u-law", "A-law"};
62static const char *wm8978_eqmode[] = {"Capture", "Playback"};
63static const char *wm8978_bw[] = {"Narrow", "Wide"};
64static const char *wm8978_eq1[] = {"80Hz", "105Hz", "135Hz", "175Hz"};
65static const char *wm8978_eq2[] = {"230Hz", "300Hz", "385Hz", "500Hz"};
66static const char *wm8978_eq3[] = {"650Hz", "850Hz", "1.1kHz", "1.4kHz"};
67static const char *wm8978_eq4[] = {"1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"};
68static const char *wm8978_eq5[] = {"5.3kHz", "6.9kHz", "9kHz", "11.7kHz"};
69static const char *wm8978_alc3[] = {"ALC", "Limiter"};
70static const char *wm8978_alc1[] = {"Off", "Right", "Left", "Both"};
71
72static const SOC_ENUM_SINGLE_DECL(adc_compand, WM8978_COMPANDING_CONTROL, 1,
73 wm8978_companding);
74static const SOC_ENUM_SINGLE_DECL(dac_compand, WM8978_COMPANDING_CONTROL, 3,
75 wm8978_companding);
76static const SOC_ENUM_SINGLE_DECL(eqmode, WM8978_EQ1, 8, wm8978_eqmode);
77static const SOC_ENUM_SINGLE_DECL(eq1, WM8978_EQ1, 5, wm8978_eq1);
78static const SOC_ENUM_SINGLE_DECL(eq2bw, WM8978_EQ2, 8, wm8978_bw);
79static const SOC_ENUM_SINGLE_DECL(eq2, WM8978_EQ2, 5, wm8978_eq2);
80static const SOC_ENUM_SINGLE_DECL(eq3bw, WM8978_EQ3, 8, wm8978_bw);
81static const SOC_ENUM_SINGLE_DECL(eq3, WM8978_EQ3, 5, wm8978_eq3);
82static const SOC_ENUM_SINGLE_DECL(eq4bw, WM8978_EQ4, 8, wm8978_bw);
83static const SOC_ENUM_SINGLE_DECL(eq4, WM8978_EQ4, 5, wm8978_eq4);
84static const SOC_ENUM_SINGLE_DECL(eq5, WM8978_EQ5, 5, wm8978_eq5);
85static const SOC_ENUM_SINGLE_DECL(alc3, WM8978_ALC_CONTROL_3, 8, wm8978_alc3);
86static const SOC_ENUM_SINGLE_DECL(alc1, WM8978_ALC_CONTROL_1, 7, wm8978_alc1);
87
88static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
89static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
90static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
91static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
92static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
1916a2aa 93static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
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GL		 94
95static const struct snd_kcontrol_new wm8978_snd_controls[] = {
96
97 SOC_SINGLE("Digital Loopback Switch",
98 WM8978_COMPANDING_CONTROL, 0, 1, 0),
99
100 SOC_ENUM("ADC Companding", adc_compand),
101 SOC_ENUM("DAC Companding", dac_compand),
102
103 SOC_DOUBLE("DAC Inversion Switch", WM8978_DAC_CONTROL, 0, 1, 1, 0),
104
105 SOC_DOUBLE_R_TLV("PCM Volume",
106 WM8978_LEFT_DAC_DIGITAL_VOLUME, WM8978_RIGHT_DAC_DIGITAL_VOLUME,
107 0, 255, 0, digital_tlv),
108
109 SOC_SINGLE("High Pass Filter Switch", WM8978_ADC_CONTROL, 8, 1, 0),
110 SOC_SINGLE("High Pass Cut Off", WM8978_ADC_CONTROL, 4, 7, 0),
111 SOC_DOUBLE("ADC Inversion Switch", WM8978_ADC_CONTROL, 0, 1, 1, 0),
112
113 SOC_DOUBLE_R_TLV("ADC Volume",
114 WM8978_LEFT_ADC_DIGITAL_VOLUME, WM8978_RIGHT_ADC_DIGITAL_VOLUME,
115 0, 255, 0, digital_tlv),
116
117 SOC_ENUM("Equaliser Function", eqmode),
118 SOC_ENUM("EQ1 Cut Off", eq1),
119 SOC_SINGLE_TLV("EQ1 Volume", WM8978_EQ1, 0, 24, 1, eq_tlv),
120
121 SOC_ENUM("Equaliser EQ2 Bandwith", eq2bw),
122 SOC_ENUM("EQ2 Cut Off", eq2),
123 SOC_SINGLE_TLV("EQ2 Volume", WM8978_EQ2, 0, 24, 1, eq_tlv),
124
125 SOC_ENUM("Equaliser EQ3 Bandwith", eq3bw),
126 SOC_ENUM("EQ3 Cut Off", eq3),
127 SOC_SINGLE_TLV("EQ3 Volume", WM8978_EQ3, 0, 24, 1, eq_tlv),
128
129 SOC_ENUM("Equaliser EQ4 Bandwith", eq4bw),
130 SOC_ENUM("EQ4 Cut Off", eq4),
131 SOC_SINGLE_TLV("EQ4 Volume", WM8978_EQ4, 0, 24, 1, eq_tlv),
132
133 SOC_ENUM("EQ5 Cut Off", eq5),
134 SOC_SINGLE_TLV("EQ5 Volume", WM8978_EQ5, 0, 24, 1, eq_tlv),
135
136 SOC_SINGLE("DAC Playback Limiter Switch",
137 WM8978_DAC_LIMITER_1, 8, 1, 0),
138 SOC_SINGLE("DAC Playback Limiter Decay",
139 WM8978_DAC_LIMITER_1, 4, 15, 0),
140 SOC_SINGLE("DAC Playback Limiter Attack",
141 WM8978_DAC_LIMITER_1, 0, 15, 0),
142
143 SOC_SINGLE("DAC Playback Limiter Threshold",
144 WM8978_DAC_LIMITER_2, 4, 7, 0),
1916a2aa
MB		 145 SOC_SINGLE_TLV("DAC Playback Limiter Volume",
146 WM8978_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
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GL		 147
148 SOC_ENUM("ALC Enable Switch", alc1),
149 SOC_SINGLE("ALC Capture Min Gain", WM8978_ALC_CONTROL_1, 0, 7, 0),
150 SOC_SINGLE("ALC Capture Max Gain", WM8978_ALC_CONTROL_1, 3, 7, 0),
151
c8fb034c 152 SOC_SINGLE("ALC Capture Hold", WM8978_ALC_CONTROL_2, 4, 10, 0),
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GL		 153 SOC_SINGLE("ALC Capture Target", WM8978_ALC_CONTROL_2, 0, 15, 0),
154
155 SOC_ENUM("ALC Capture Mode", alc3),
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MB		 156 SOC_SINGLE("ALC Capture Decay", WM8978_ALC_CONTROL_3, 4, 10, 0),
157 SOC_SINGLE("ALC Capture Attack", WM8978_ALC_CONTROL_3, 0, 10, 0),
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GL		 158
159 SOC_SINGLE("ALC Capture Noise Gate Switch", WM8978_NOISE_GATE, 3, 1, 0),
160 SOC_SINGLE("ALC Capture Noise Gate Threshold",
161 WM8978_NOISE_GATE, 0, 7, 0),
162
163 SOC_DOUBLE_R("Capture PGA ZC Switch",
164 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
165 7, 1, 0),
166
167 /* OUT1 - Headphones */
168 SOC_DOUBLE_R("Headphone Playback ZC Switch",
169 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 7, 1, 0),
170
171 SOC_DOUBLE_R_TLV("Headphone Playback Volume",
172 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL,
173 0, 63, 0, spk_tlv),
174
175 /* OUT2 - Speakers */
176 SOC_DOUBLE_R("Speaker Playback ZC Switch",
177 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 7, 1, 0),
178
179 SOC_DOUBLE_R_TLV("Speaker Playback Volume",
180 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL,
181 0, 63, 0, spk_tlv),
182
183 /* OUT3/4 - Line Output */
184 SOC_DOUBLE_R("Line Playback Switch",
185 WM8978_OUT3_MIXER_CONTROL, WM8978_OUT4_MIXER_CONTROL, 6, 1, 1),
186
187 /* Mixer #3: Boost (Input) mixer */
188 SOC_DOUBLE_R("PGA Boost (+20dB)",
189 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
190 8, 1, 0),
191 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
192 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
193 4, 7, 0, boost_tlv),
194 SOC_DOUBLE_R_TLV("Aux Boost Volume",
195 WM8978_LEFT_ADC_BOOST_CONTROL, WM8978_RIGHT_ADC_BOOST_CONTROL,
196 0, 7, 0, boost_tlv),
197
198 /* Input PGA volume */
199 SOC_DOUBLE_R_TLV("Input PGA Volume",
200 WM8978_LEFT_INP_PGA_CONTROL, WM8978_RIGHT_INP_PGA_CONTROL,
201 0, 63, 0, inpga_tlv),
202
203 /* Headphone */
204 SOC_DOUBLE_R("Headphone Switch",
205 WM8978_LOUT1_HP_CONTROL, WM8978_ROUT1_HP_CONTROL, 6, 1, 1),
206
207 /* Speaker */
208 SOC_DOUBLE_R("Speaker Switch",
209 WM8978_LOUT2_SPK_CONTROL, WM8978_ROUT2_SPK_CONTROL, 6, 1, 1),
b2c3e923
GL		 210
211 /* DAC / ADC oversampling */
c8fb034c
MB		 212 SOC_SINGLE("DAC 128x Oversampling Switch", WM8978_DAC_CONTROL,
213 5, 1, 0),
214 SOC_SINGLE("ADC 128x Oversampling Switch", WM8978_ADC_CONTROL,
215 5, 1, 0),
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GL		 216};
217
218/* Mixer #1: Output (OUT1, OUT2) Mixer: mix AUX, Input mixer output and DAC */
219static const struct snd_kcontrol_new wm8978_left_out_mixer[] = {
220 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_LEFT_MIXER_CONTROL, 1, 1, 0),
221 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_LEFT_MIXER_CONTROL, 5, 1, 0),
222 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_LEFT_MIXER_CONTROL, 0, 1, 0),
223};
224
225static const struct snd_kcontrol_new wm8978_right_out_mixer[] = {
226 SOC_DAPM_SINGLE("Line Bypass Switch", WM8978_RIGHT_MIXER_CONTROL, 1, 1, 0),
227 SOC_DAPM_SINGLE("Aux Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 5, 1, 0),
228 SOC_DAPM_SINGLE("PCM Playback Switch", WM8978_RIGHT_MIXER_CONTROL, 0, 1, 0),
229};
230
231/* OUT3/OUT4 Mixer not implemented */
232
233/* Mixer #2: Input PGA Mute */
234static const struct snd_kcontrol_new wm8978_left_input_mixer[] = {
235 SOC_DAPM_SINGLE("L2 Switch", WM8978_INPUT_CONTROL, 2, 1, 0),
236 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 1, 1, 0),
237 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 0, 1, 0),
238};
239static const struct snd_kcontrol_new wm8978_right_input_mixer[] = {
240 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
241 SOC_DAPM_SINGLE("MicN Switch", WM8978_INPUT_CONTROL, 5, 1, 0),
242 SOC_DAPM_SINGLE("MicP Switch", WM8978_INPUT_CONTROL, 4, 1, 0),
243};
244
245static const struct snd_soc_dapm_widget wm8978_dapm_widgets[] = {
246 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
247 WM8978_POWER_MANAGEMENT_3, 0, 0),
248 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
249 WM8978_POWER_MANAGEMENT_3, 1, 0),
250 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
251 WM8978_POWER_MANAGEMENT_2, 0, 0),
252 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
253 WM8978_POWER_MANAGEMENT_2, 1, 0),
254
255 /* Mixer #1: OUT1,2 */
256 SOC_MIXER_ARRAY("Left Output Mixer", WM8978_POWER_MANAGEMENT_3,
257 2, 0, wm8978_left_out_mixer),
258 SOC_MIXER_ARRAY("Right Output Mixer", WM8978_POWER_MANAGEMENT_3,
259 3, 0, wm8978_right_out_mixer),
260
261 SOC_MIXER_ARRAY("Left Input Mixer", WM8978_POWER_MANAGEMENT_2,
262 2, 0, wm8978_left_input_mixer),
263 SOC_MIXER_ARRAY("Right Input Mixer", WM8978_POWER_MANAGEMENT_2,
264 3, 0, wm8978_right_input_mixer),
265
266 SND_SOC_DAPM_PGA("Left Boost Mixer", WM8978_POWER_MANAGEMENT_2,
267 4, 0, NULL, 0),
268 SND_SOC_DAPM_PGA("Right Boost Mixer", WM8978_POWER_MANAGEMENT_2,
269 5, 0, NULL, 0),
270
271 SND_SOC_DAPM_PGA("Left Capture PGA", WM8978_LEFT_INP_PGA_CONTROL,
272 6, 1, NULL, 0),
273 SND_SOC_DAPM_PGA("Right Capture PGA", WM8978_RIGHT_INP_PGA_CONTROL,
274 6, 1, NULL, 0),
275
276 SND_SOC_DAPM_PGA("Left Headphone Out", WM8978_POWER_MANAGEMENT_2,
277 7, 0, NULL, 0),
278 SND_SOC_DAPM_PGA("Right Headphone Out", WM8978_POWER_MANAGEMENT_2,
279 8, 0, NULL, 0),
280
281 SND_SOC_DAPM_PGA("Left Speaker Out", WM8978_POWER_MANAGEMENT_3,
282 6, 0, NULL, 0),
283 SND_SOC_DAPM_PGA("Right Speaker Out", WM8978_POWER_MANAGEMENT_3,
284 5, 0, NULL, 0),
285
286 SND_SOC_DAPM_MIXER("OUT4 VMID", WM8978_POWER_MANAGEMENT_3,
287 8, 0, NULL, 0),
288
289 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8978_POWER_MANAGEMENT_1, 4, 0),
290
291 SND_SOC_DAPM_INPUT("LMICN"),
292 SND_SOC_DAPM_INPUT("LMICP"),
293 SND_SOC_DAPM_INPUT("RMICN"),
294 SND_SOC_DAPM_INPUT("RMICP"),
295 SND_SOC_DAPM_INPUT("LAUX"),
296 SND_SOC_DAPM_INPUT("RAUX"),
297 SND_SOC_DAPM_INPUT("L2"),
298 SND_SOC_DAPM_INPUT("R2"),
299 SND_SOC_DAPM_OUTPUT("LHP"),
300 SND_SOC_DAPM_OUTPUT("RHP"),
301 SND_SOC_DAPM_OUTPUT("LSPK"),
302 SND_SOC_DAPM_OUTPUT("RSPK"),
303};
304
803b3788 305static const struct snd_soc_dapm_route wm8978_dapm_routes[] = {
0d34e915
GL		 306 /* Output mixer */
307 {"Right Output Mixer", "PCM Playback Switch", "Right DAC"},
308 {"Right Output Mixer", "Aux Playback Switch", "RAUX"},
309 {"Right Output Mixer", "Line Bypass Switch", "Right Boost Mixer"},
310
311 {"Left Output Mixer", "PCM Playback Switch", "Left DAC"},
312 {"Left Output Mixer", "Aux Playback Switch", "LAUX"},
313 {"Left Output Mixer", "Line Bypass Switch", "Left Boost Mixer"},
314
315 /* Outputs */
316 {"Right Headphone Out", NULL, "Right Output Mixer"},
317 {"RHP", NULL, "Right Headphone Out"},
318
319 {"Left Headphone Out", NULL, "Left Output Mixer"},
320 {"LHP", NULL, "Left Headphone Out"},
321
322 {"Right Speaker Out", NULL, "Right Output Mixer"},
323 {"RSPK", NULL, "Right Speaker Out"},
324
325 {"Left Speaker Out", NULL, "Left Output Mixer"},
326 {"LSPK", NULL, "Left Speaker Out"},
327
328 /* Boost Mixer */
329 {"Right ADC", NULL, "Right Boost Mixer"},
330
331 {"Right Boost Mixer", NULL, "RAUX"},
332 {"Right Boost Mixer", NULL, "Right Capture PGA"},
333 {"Right Boost Mixer", NULL, "R2"},
334
335 {"Left ADC", NULL, "Left Boost Mixer"},
336
337 {"Left Boost Mixer", NULL, "LAUX"},
338 {"Left Boost Mixer", NULL, "Left Capture PGA"},
339 {"Left Boost Mixer", NULL, "L2"},
340
341 /* Input PGA */
342 {"Right Capture PGA", NULL, "Right Input Mixer"},
343 {"Left Capture PGA", NULL, "Left Input Mixer"},
344
345 {"Right Input Mixer", "R2 Switch", "R2"},
346 {"Right Input Mixer", "MicN Switch", "RMICN"},
347 {"Right Input Mixer", "MicP Switch", "RMICP"},
348
349 {"Left Input Mixer", "L2 Switch", "L2"},
350 {"Left Input Mixer", "MicN Switch", "LMICN"},
351 {"Left Input Mixer", "MicP Switch", "LMICP"},
352};
353
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GL		 354/* PLL divisors */
355struct wm8978_pll_div {
356 u32 k;
357 u8 n;
358 u8 div2;
359};
360
361#define FIXED_PLL_SIZE (1 << 24)
362
f0fba2ad
LG		 363static void pll_factors(struct snd_soc_codec *codec,
364 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source)
0d34e915
GL		 365{
366 u64 k_part;
367 unsigned int k, n_div, n_mod;
368
369 n_div = target / source;
370 if (n_div < 6) {
371 source >>= 1;
372 pll_div->div2 = 1;
373 n_div = target / source;
374 } else {
375 pll_div->div2 = 0;
376 }
377
378 if (n_div < 6 || n_div > 12)
f0fba2ad 379 dev_warn(codec->dev,
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GL		 380 "WM8978 N value exceeds recommended range! N = %u\n",
381 n_div);
382
383 pll_div->n = n_div;
384 n_mod = target - source * n_div;
385 k_part = FIXED_PLL_SIZE * (long long)n_mod + source / 2;
386
387 do_div(k_part, source);
388
389 k = k_part & 0xFFFFFFFF;
390
391 pll_div->k = k;
392}
b0580913
GL		 393
394/* MCLK dividers */
395static const int mclk_numerator[] = {1, 3, 2, 3, 4, 6, 8, 12};
396static const int mclk_denominator[] = {1, 2, 1, 1, 1, 1, 1, 1};
397
398/*
399 * find index >= idx, such that, for a given f_out,
400 * 3 * f_mclk / 4 <= f_PLLOUT < 13 * f_mclk / 4
401 * f_out can be f_256fs or f_opclk, currently only used for f_256fs. Can be
402 * generalised for f_opclk with suitable coefficient arrays, but currently
403 * the OPCLK divisor is calculated directly, not iteratively.
404 */
405static int wm8978_enum_mclk(unsigned int f_out, unsigned int f_mclk,
406 unsigned int *f_pllout)
407{
408 int i;
409
410 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
411 unsigned int f_pllout_x4 = 4 * f_out * mclk_numerator[i] /
412 mclk_denominator[i];
413 if (3 * f_mclk <= f_pllout_x4 && f_pllout_x4 < 13 * f_mclk) {
414 *f_pllout = f_pllout_x4 / 4;
415 return i;
416 }
417 }
418
419 return -EINVAL;
420}
421
0d34e915
GL		 422/*
423 * Calculate internal frequencies and dividers, according to Figure 40
424 * "PLL and Clock Select Circuit" in WM8978 datasheet Rev. 2.6
425 */
426static int wm8978_configure_pll(struct snd_soc_codec *codec)
427{
b2c812e2 428 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
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GL		 429 struct wm8978_pll_div pll_div;
430 unsigned int f_opclk = wm8978->f_opclk, f_mclk = wm8978->f_mclk,
431 f_256fs = wm8978->f_256fs;
b0580913 432 unsigned int f2;
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GL		 433
434 if (!f_mclk)
435 return -EINVAL;
436
437 if (f_opclk) {
b0580913
GL		 438 unsigned int opclk_div;
439 /* Cannot set up MCLK divider now, do later */
440 wm8978->mclk_idx = -1;
441
0d34e915
GL		 442 /*
443 * The user needs OPCLK. Choose OPCLKDIV to put
444 * 6 <= R = f2 / f1 < 13, 1 <= OPCLKDIV <= 4.
445 * f_opclk = f_mclk * prescale * R / 4 / OPCLKDIV, where
446 * prescale = 1, or prescale = 2. Prescale is calculated inside
447 * pll_factors(). We have to select f_PLLOUT, such that
448 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
449 * f_mclk * 3 / 16 <= f_opclk < f_mclk * 13 / 4.
450 */
451 if (16 * f_opclk < 3 * f_mclk || 4 * f_opclk >= 13 * f_mclk)
452 return -EINVAL;
453
454 if (4 * f_opclk < 3 * f_mclk)
455 /* Have to use OPCLKDIV */
456 opclk_div = (3 * f_mclk / 4 + f_opclk - 1) / f_opclk;
457 else
458 opclk_div = 1;
459
460 dev_dbg(codec->dev, "%s: OPCLKDIV=%d\n", __func__, opclk_div);
461
462 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 0x30,
463 (opclk_div - 1) << 4);
464
465 wm8978->f_pllout = f_opclk * opclk_div;
466 } else if (f_256fs) {
467 /*
b0580913 468 * Not using OPCLK, but PLL is used for the codec, choose R:
0d34e915
GL		 469 * 6 <= R = f2 / f1 < 13, to put 1 <= MCLKDIV <= 12.
470 * f_256fs = f_mclk * prescale * R / 4 / MCLKDIV, where
471 * prescale = 1, or prescale = 2. Prescale is calculated inside
472 * pll_factors(). We have to select f_PLLOUT, such that
473 * f_mclk * 3 / 4 <= f_PLLOUT < f_mclk * 13 / 4. Must be
474 * f_mclk * 3 / 48 <= f_256fs < f_mclk * 13 / 4. This means MCLK
475 * must be 3.781MHz <= f_MCLK <= 32.768MHz
476 */
b0580913
GL		 477 int idx = wm8978_enum_mclk(f_256fs, f_mclk, &wm8978->f_pllout);
478 if (idx < 0)
479 return idx;
0d34e915 480
b0580913 481 wm8978->mclk_idx = idx;
0d34e915
GL		 482
483 /* GPIO1 into default mode as input - before configuring PLL */
484 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
485 } else {
486 return -EINVAL;
487 }
488
489 f2 = wm8978->f_pllout * 4;
490
491 dev_dbg(codec->dev, "%s: f_MCLK=%uHz, f_PLLOUT=%uHz\n", __func__,
492 wm8978->f_mclk, wm8978->f_pllout);
493
f0fba2ad 494 pll_factors(codec, &pll_div, f2, wm8978->f_mclk);
0d34e915
GL		 495
496 dev_dbg(codec->dev, "%s: calculated PLL N=0x%x, K=0x%x, div2=%d\n",
497 __func__, pll_div.n, pll_div.k, pll_div.div2);
498
499 /* Turn PLL off for configuration... */
500 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
501
502 snd_soc_write(codec, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n);
503 snd_soc_write(codec, WM8978_PLL_K1, pll_div.k >> 18);
504 snd_soc_write(codec, WM8978_PLL_K2, (pll_div.k >> 9) & 0x1ff);
505 snd_soc_write(codec, WM8978_PLL_K3, pll_div.k & 0x1ff);
506
507 /* ...and on again */
508 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
509
510 if (f_opclk)
511 /* Output PLL (OPCLK) to GPIO1 */
512 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 4);
513
514 return 0;
515}
516
517/*
518 * Configure WM8978 clock dividers.
519 */
520static int wm8978_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
521 int div_id, int div)
522{
523 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 524 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 525 int ret = 0;
526
527 switch (div_id) {
528 case WM8978_OPCLKRATE:
529 wm8978->f_opclk = div;
530
531 if (wm8978->f_mclk)
b0580913
GL		 532 /*
533 * We know the MCLK frequency, the user has requested
534 * OPCLK, configure the PLL based on that and start it
535 * and OPCLK immediately. We will configure PLL to match
536 * user-requested OPCLK frquency as good as possible.
537 * In fact, it is likely, that matching the sampling
538 * rate, when it becomes known, is more important, and
539 * we will not be reconfiguring PLL then, because we
540 * must not interrupt OPCLK. But it should be fine,
541 * because typically the user will request OPCLK to run
542 * at 256fs or 512fs, and for these cases we will also
543 * find an exact MCLK divider configuration - it will
544 * be equal to or double the OPCLK divisor.
545 */
0d34e915
GL		 546 ret = wm8978_configure_pll(codec);
547 break;
0d34e915
GL		 548 case WM8978_BCLKDIV:
549 if (div & ~0x1c)
550 return -EINVAL;
551 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x1c, div);
552 break;
553 default:
554 return -EINVAL;
555 }
556
557 dev_dbg(codec->dev, "%s: ID %d, value %u\n", __func__, div_id, div);
558
559 return ret;
560}
561
562/*
563 * @freq: when .set_pll() us not used, freq is codec MCLK input frequency
564 */
565static int wm8978_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id,
566 unsigned int freq, int dir)
567{
568 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 569 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 570 int ret = 0;
571
572 dev_dbg(codec->dev, "%s: ID %d, freq %u\n", __func__, clk_id, freq);
573
574 if (freq) {
575 wm8978->f_mclk = freq;
576
577 /* Even if MCLK is used for system clock, might have to drive OPCLK */
578 if (wm8978->f_opclk)
579 ret = wm8978_configure_pll(codec);
580
581 /* Our sysclk is fixed to 256 * fs, will configure in .hw_params() */
582
583 if (!ret)
584 wm8978->sysclk = clk_id;
585 }
586
587 if (wm8978->sysclk == WM8978_PLL && (!freq || clk_id == WM8978_MCLK)) {
588 /* Clock CODEC directly from MCLK */
589 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
590
591 /* GPIO1 into default mode as input - before configuring PLL */
592 snd_soc_update_bits(codec, WM8978_GPIO_CONTROL, 7, 0);
593
594 /* Turn off PLL */
595 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0);
596 wm8978->sysclk = WM8978_MCLK;
597 wm8978->f_pllout = 0;
598 wm8978->f_opclk = 0;
599 }
600
601 return ret;
602}
603
604/*
605 * Set ADC and Voice DAC format.
606 */
607static int wm8978_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
608{
609 struct snd_soc_codec *codec = codec_dai->codec;
610 /*
611 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80,
612 * Data Format mask = 0x18: all will be calculated anew
613 */
614 u16 iface = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x198;
615 u16 clk = snd_soc_read(codec, WM8978_CLOCKING);
616
617 dev_dbg(codec->dev, "%s\n", __func__);
618
619 /* set master/slave audio interface */
620 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
621 case SND_SOC_DAIFMT_CBM_CFM:
622 clk |= 1;
623 break;
624 case SND_SOC_DAIFMT_CBS_CFS:
625 clk &= ~1;
626 break;
627 default:
628 return -EINVAL;
629 }
630
631 /* interface format */
632 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
633 case SND_SOC_DAIFMT_I2S:
634 iface |= 0x10;
635 break;
636 case SND_SOC_DAIFMT_RIGHT_J:
637 break;
638 case SND_SOC_DAIFMT_LEFT_J:
639 iface |= 0x8;
640 break;
641 case SND_SOC_DAIFMT_DSP_A:
642 iface |= 0x18;
643 break;
644 default:
645 return -EINVAL;
646 }
647
648 /* clock inversion */
649 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
650 case SND_SOC_DAIFMT_NB_NF:
651 break;
652 case SND_SOC_DAIFMT_IB_IF:
653 iface |= 0x180;
654 break;
655 case SND_SOC_DAIFMT_IB_NF:
656 iface |= 0x100;
657 break;
658 case SND_SOC_DAIFMT_NB_IF:
659 iface |= 0x80;
660 break;
661 default:
662 return -EINVAL;
663 }
664
665 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface);
666 snd_soc_write(codec, WM8978_CLOCKING, clk);
667
668 return 0;
669}
670
0d34e915
GL		 671/*
672 * Set PCM DAI bit size and sample rate.
673 */
674static int wm8978_hw_params(struct snd_pcm_substream *substream,
675 struct snd_pcm_hw_params *params,
676 struct snd_soc_dai *dai)
677{
678 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 679 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 680 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 681 /* Word length mask = 0x60 */
682 u16 iface_ctl = snd_soc_read(codec, WM8978_AUDIO_INTERFACE) & ~0x60;
683 /* Sampling rate mask = 0xe (for filters) */
684 u16 add_ctl = snd_soc_read(codec, WM8978_ADDITIONAL_CONTROL) & ~0xe;
685 u16 clking = snd_soc_read(codec, WM8978_CLOCKING);
686 enum wm8978_sysclk_src current_clk_id = clking & 0x100 ?
687 WM8978_PLL : WM8978_MCLK;
688 unsigned int f_sel, diff, diff_best = INT_MAX;
689 int i, best = 0;
690
691 if (!wm8978->f_mclk)
692 return -EINVAL;
693
694 /* bit size */
695 switch (params_format(params)) {
696 case SNDRV_PCM_FORMAT_S16_LE:
697 break;
698 case SNDRV_PCM_FORMAT_S20_3LE:
699 iface_ctl |= 0x20;
700 break;
701 case SNDRV_PCM_FORMAT_S24_LE:
702 iface_ctl |= 0x40;
703 break;
704 case SNDRV_PCM_FORMAT_S32_LE:
705 iface_ctl |= 0x60;
706 break;
707 }
708
709 /* filter coefficient */
710 switch (params_rate(params)) {
711 case 8000:
712 add_ctl |= 0x5 << 1;
713 break;
714 case 11025:
715 add_ctl |= 0x4 << 1;
716 break;
717 case 16000:
718 add_ctl |= 0x3 << 1;
719 break;
720 case 22050:
721 add_ctl |= 0x2 << 1;
722 break;
723 case 32000:
724 add_ctl |= 0x1 << 1;
725 break;
726 case 44100:
727 case 48000:
728 break;
729 }
730
731 /* Sampling rate is known now, can configure the MCLK divider */
732 wm8978->f_256fs = params_rate(params) * 256;
733
734 if (wm8978->sysclk == WM8978_MCLK) {
b0580913 735 wm8978->mclk_idx = -1;
0d34e915
GL		 736 f_sel = wm8978->f_mclk;
737 } else {
738 if (!wm8978->f_pllout) {
b0580913 739 /* We only enter here, if OPCLK is not used */
0d34e915
GL		 740 int ret = wm8978_configure_pll(codec);
741 if (ret < 0)
742 return ret;
743 }
744 f_sel = wm8978->f_pllout;
745 }
746
b0580913
GL		 747 if (wm8978->mclk_idx < 0) {
748 /* Either MCLK is used directly, or OPCLK is used */
749 if (f_sel < wm8978->f_256fs || f_sel > 12 * wm8978->f_256fs)
750 return -EINVAL;
0d34e915 751
b0580913
GL		 752 for (i = 0; i < ARRAY_SIZE(mclk_numerator); i++) {
753 diff = abs(wm8978->f_256fs * 3 -
754 f_sel * 3 * mclk_denominator[i] / mclk_numerator[i]);
0d34e915 755
b0580913
GL		 756 if (diff < diff_best) {
757 diff_best = diff;
758 best = i;
759 }
0d34e915 760
b0580913
GL		 761 if (!diff)
762 break;
763 }
764 } else {
765 /* OPCLK not used, codec driven by PLL */
766 best = wm8978->mclk_idx;
767 diff = 0;
0d34e915
GL		 768 }
769
770 if (diff)
b0580913
GL		 771 dev_warn(codec->dev, "Imprecise sampling rate: %uHz%s\n",
772 f_sel * mclk_denominator[best] / mclk_numerator[best] / 256,
773 wm8978->sysclk == WM8978_MCLK ?
774 ", consider using PLL" : "");
0d34e915
GL		 775
776 dev_dbg(codec->dev, "%s: fmt %d, rate %u, MCLK divisor #%d\n", __func__,
777 params_format(params), params_rate(params), best);
778
779 /* MCLK divisor mask = 0xe0 */
780 snd_soc_update_bits(codec, WM8978_CLOCKING, 0xe0, best << 5);
781
782 snd_soc_write(codec, WM8978_AUDIO_INTERFACE, iface_ctl);
783 snd_soc_write(codec, WM8978_ADDITIONAL_CONTROL, add_ctl);
784
785 if (wm8978->sysclk != current_clk_id) {
786 if (wm8978->sysclk == WM8978_PLL)
787 /* Run CODEC from PLL instead of MCLK */
788 snd_soc_update_bits(codec, WM8978_CLOCKING,
789 0x100, 0x100);
790 else
791 /* Clock CODEC directly from MCLK */
792 snd_soc_update_bits(codec, WM8978_CLOCKING, 0x100, 0);
793 }
794
795 return 0;
796}
797
798static int wm8978_mute(struct snd_soc_dai *dai, int mute)
799{
800 struct snd_soc_codec *codec = dai->codec;
801
802 dev_dbg(codec->dev, "%s: %d\n", __func__, mute);
803
804 if (mute)
805 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0x40);
806 else
807 snd_soc_update_bits(codec, WM8978_DAC_CONTROL, 0x40, 0);
808
809 return 0;
810}
811
812static int wm8978_set_bias_level(struct snd_soc_codec *codec,
813 enum snd_soc_bias_level level)
814{
815 u16 power1 = snd_soc_read(codec, WM8978_POWER_MANAGEMENT_1) & ~3;
816
817 switch (level) {
818 case SND_SOC_BIAS_ON:
819 case SND_SOC_BIAS_PREPARE:
820 power1 |= 1; /* VMID 75k */
821 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
822 break;
823 case SND_SOC_BIAS_STANDBY:
824 /* bit 3: enable bias, bit 2: enable I/O tie off buffer */
825 power1 |= 0xc;
826
ce6120cc 827 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0d34e915
GL		 828 /* Initial cap charge at VMID 5k */
829 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1,
830 power1 | 0x3);
831 mdelay(100);
832 }
833
834 power1 |= 0x2; /* VMID 500k */
835 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, power1);
836 break;
837 case SND_SOC_BIAS_OFF:
838 /* Preserve PLL - OPCLK may be used by someone */
839 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, ~0x20, 0);
840 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_2, 0);
841 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_3, 0);
842 break;
843 }
844
845 dev_dbg(codec->dev, "%s: %d, %x\n", __func__, level, power1);
846
ce6120cc 847 codec->dapm.bias_level = level;
0d34e915
GL		 848 return 0;
849}
850
851#define WM8978_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
852 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
853
85e7652d 854static const struct snd_soc_dai_ops wm8978_dai_ops = {
0d34e915
GL		 855 .hw_params = wm8978_hw_params,
856 .digital_mute = wm8978_mute,
857 .set_fmt = wm8978_set_dai_fmt,
858 .set_clkdiv = wm8978_set_dai_clkdiv,
859 .set_sysclk = wm8978_set_dai_sysclk,
860};
861
862/* Also supports 12kHz */
f0fba2ad
LG		 863static struct snd_soc_dai_driver wm8978_dai = {
864 .name = "wm8978-hifi",
0d34e915
GL		 865 .playback = {
866 .stream_name = "Playback",
867 .channels_min = 1,
868 .channels_max = 2,
869 .rates = SNDRV_PCM_RATE_8000_48000,
870 .formats = WM8978_FORMATS,
871 },
872 .capture = {
873 .stream_name = "Capture",
874 .channels_min = 1,
875 .channels_max = 2,
876 .rates = SNDRV_PCM_RATE_8000_48000,
877 .formats = WM8978_FORMATS,
878 },
879 .ops = &wm8978_dai_ops,
880};
0d34e915 881
84b315ee 882static int wm8978_suspend(struct snd_soc_codec *codec)
0d34e915 883{
0d34e915
GL		 884 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
885 /* Also switch PLL off */
886 snd_soc_write(codec, WM8978_POWER_MANAGEMENT_1, 0);
0d34e915
GL		 887
888 return 0;
889}
890
f0fba2ad 891static int wm8978_resume(struct snd_soc_codec *codec)
0d34e915 892{
b2c812e2 893 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
0d34e915
GL		 894 int i;
895 u16 *cache = codec->reg_cache;
896
0d34e915
GL		 897 /* Sync reg_cache with the hardware */
898 for (i = 0; i < ARRAY_SIZE(wm8978_reg); i++) {
899 if (i == WM8978_RESET)
900 continue;
901 if (cache[i] != wm8978_reg[i])
902 snd_soc_write(codec, i, cache[i]);
903 }
904
905 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
906
907 if (wm8978->f_pllout)
908 /* Switch PLL on */
909 snd_soc_update_bits(codec, WM8978_POWER_MANAGEMENT_1, 0x20, 0x20);
910
911 return 0;
912}
913
0d34e915
GL		 914/*
915 * These registers contain an "update" bit - bit 8. This means, for example,
916 * that one can write new DAC digital volume for both channels, but only when
917 * the update bit is set, will also the volume be updated - simultaneously for
918 * both channels.
919 */
920static const int update_reg[] = {
921 WM8978_LEFT_DAC_DIGITAL_VOLUME,
922 WM8978_RIGHT_DAC_DIGITAL_VOLUME,
923 WM8978_LEFT_ADC_DIGITAL_VOLUME,
924 WM8978_RIGHT_ADC_DIGITAL_VOLUME,
925 WM8978_LEFT_INP_PGA_CONTROL,
926 WM8978_RIGHT_INP_PGA_CONTROL,
927 WM8978_LOUT1_HP_CONTROL,
928 WM8978_ROUT1_HP_CONTROL,
929 WM8978_LOUT2_SPK_CONTROL,
930 WM8978_ROUT2_SPK_CONTROL,
931};
932
f0fba2ad 933static int wm8978_probe(struct snd_soc_codec *codec)
0d34e915 934{
f0fba2ad
LG		 935 struct wm8978_priv *wm8978 = snd_soc_codec_get_drvdata(codec);
936 int ret = 0, i;
0d34e915
GL		 937
938 /*
939 * Set default system clock to PLL, it is more precise, this is also the
940 * default hardware setting
941 */
942 wm8978->sysclk = WM8978_PLL;
0d34e915
GL		 943 ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_I2C);
944 if (ret < 0) {
945 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 946 return ret;
0d34e915
GL		 947 }
948
0d34e915
GL		 949 /*
950 * Set the update bit in all registers, that have one. This way all
951 * writes to those registers will also cause the update bit to be
952 * written.
953 */
954 for (i = 0; i < ARRAY_SIZE(update_reg); i++)
a1b3b5ee 955 snd_soc_update_bits(codec, update_reg[i], 0x100, 0x100);
0d34e915
GL		 956
957 /* Reset the codec */
958 ret = snd_soc_write(codec, WM8978_RESET, 0);
959 if (ret < 0) {
960 dev_err(codec->dev, "Failed to issue reset\n");
f0fba2ad 961 return ret;
0d34e915
GL		 962 }
963
0d34e915
GL		 964 wm8978_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
965
0d34e915 966 return 0;
0d34e915
GL		 967}
968
f0fba2ad
LG		 969/* power down chip */
970static int wm8978_remove(struct snd_soc_codec *codec)
0d34e915 971{
f0fba2ad
LG		 972 wm8978_set_bias_level(codec, SND_SOC_BIAS_OFF);
973 return 0;
0d34e915
GL		 974}
975
f0fba2ad
LG		 976static struct snd_soc_codec_driver soc_codec_dev_wm8978 = {
977 .probe = wm8978_probe,
978 .remove = wm8978_remove,
979 .suspend = wm8978_suspend,
980 .resume = wm8978_resume,
981 .set_bias_level = wm8978_set_bias_level,
982 .reg_cache_size = ARRAY_SIZE(wm8978_reg),
983 .reg_word_size = sizeof(u16),
984 .reg_cache_default = wm8978_reg,
803b3788
MB		 985
986 .controls = wm8978_snd_controls,
987 .num_controls = ARRAY_SIZE(wm8978_snd_controls),
988 .dapm_widgets = wm8978_dapm_widgets,
989 .num_dapm_widgets = ARRAY_SIZE(wm8978_dapm_widgets),
990 .dapm_routes = wm8978_dapm_routes,
991 .num_dapm_routes = ARRAY_SIZE(wm8978_dapm_routes),
f0fba2ad
LG		 992};
993
0d34e915
GL		 994static __devinit int wm8978_i2c_probe(struct i2c_client *i2c,
995 const struct i2c_device_id *id)
996{
997 struct wm8978_priv *wm8978;
f0fba2ad 998 int ret;
0d34e915
GL		 999
1000 wm8978 = kzalloc(sizeof(struct wm8978_priv), GFP_KERNEL);
1001 if (wm8978 == NULL)
1002 return -ENOMEM;
1003
0d34e915 1004 i2c_set_clientdata(i2c, wm8978);
0d34e915 1005
f0fba2ad
LG		 1006 ret = snd_soc_register_codec(&i2c->dev,
1007 &soc_codec_dev_wm8978, &wm8978_dai, 1);
d484366b
AL		 1008 if (ret < 0)
1009 kfree(wm8978);
d484366b 1010 return ret;
0d34e915
GL		 1011}
1012
1013static __devexit int wm8978_i2c_remove(struct i2c_client *client)
1014{
f0fba2ad
LG		 1015 snd_soc_unregister_codec(&client->dev);
1016 kfree(i2c_get_clientdata(client));
0d34e915
GL		 1017 return 0;
1018}
1019
1020static const struct i2c_device_id wm8978_i2c_id[] = {
1021 { "wm8978", 0 },
1022 { }
1023};
1024MODULE_DEVICE_TABLE(i2c, wm8978_i2c_id);
1025
1026static struct i2c_driver wm8978_i2c_driver = {
1027 .driver = {
5250a503 1028 .name = "wm8978",
0d34e915
GL		 1029 .owner = THIS_MODULE,
1030 },
1031 .probe = wm8978_i2c_probe,
1032 .remove = __devexit_p(wm8978_i2c_remove),
1033 .id_table = wm8978_i2c_id,
1034};
1035
1036static int __init wm8978_modinit(void)
1037{
f0fba2ad 1038 int ret = 0;
f0fba2ad
LG		 1039 ret = i2c_add_driver(&wm8978_i2c_driver);
1040 if (ret != 0) {
1041 printk(KERN_ERR "Failed to register WM8978 I2C driver: %d\n",
1042 ret);
1043 }
f0fba2ad 1044 return ret;
0d34e915
GL		 1045}
1046module_init(wm8978_modinit);
1047
1048static void __exit wm8978_exit(void)
1049{
1050 i2c_del_driver(&wm8978_i2c_driver);
1051}
1052module_exit(wm8978_exit);
1053
1054MODULE_DESCRIPTION("ASoC WM8978 codec driver");
1055MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1056MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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