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ASoC: wm8985 Don't directly reference the cache data structure
[deliverable/linux.git] / sound / soc / codecs / wm8985.c
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6d6f8b83
DP		 1/*
2 * wm8985.c -- WM8985 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * o Add OUT3/OUT4 mixer controls.
14 */
15
16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/pm.h>
21#include <linux/i2c.h>
22#include <linux/regulator/consumer.h>
23#include <linux/spi/spi.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
6d6f8b83
DP		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include "wm8985.h"
33
34#define WM8985_NUM_SUPPLIES 4
35static const char *wm8985_supply_names[WM8985_NUM_SUPPLIES] = {
36 "DCVDD",
37 "DBVDD",
38 "AVDD1",
39 "AVDD2"
40};
41
42static const u16 wm8985_reg_defs[] = {
43 0x0000, /* R0 - Software Reset */
44 0x0000, /* R1 - Power management 1 */
45 0x0000, /* R2 - Power management 2 */
46 0x0000, /* R3 - Power management 3 */
47 0x0050, /* R4 - Audio Interface */
48 0x0000, /* R5 - Companding control */
49 0x0140, /* R6 - Clock Gen control */
50 0x0000, /* R7 - Additional control */
51 0x0000, /* R8 - GPIO Control */
52 0x0000, /* R9 - Jack Detect Control 1 */
53 0x0000, /* R10 - DAC Control */
54 0x00FF, /* R11 - Left DAC digital Vol */
55 0x00FF, /* R12 - Right DAC digital vol */
56 0x0000, /* R13 - Jack Detect Control 2 */
57 0x0100, /* R14 - ADC Control */
58 0x00FF, /* R15 - Left ADC Digital Vol */
59 0x00FF, /* R16 - Right ADC Digital Vol */
60 0x0000, /* R17 */
61 0x012C, /* R18 - EQ1 - low shelf */
62 0x002C, /* R19 - EQ2 - peak 1 */
63 0x002C, /* R20 - EQ3 - peak 2 */
64 0x002C, /* R21 - EQ4 - peak 3 */
65 0x002C, /* R22 - EQ5 - high shelf */
66 0x0000, /* R23 */
67 0x0032, /* R24 - DAC Limiter 1 */
68 0x0000, /* R25 - DAC Limiter 2 */
69 0x0000, /* R26 */
70 0x0000, /* R27 - Notch Filter 1 */
71 0x0000, /* R28 - Notch Filter 2 */
72 0x0000, /* R29 - Notch Filter 3 */
73 0x0000, /* R30 - Notch Filter 4 */
74 0x0000, /* R31 */
75 0x0038, /* R32 - ALC control 1 */
76 0x000B, /* R33 - ALC control 2 */
77 0x0032, /* R34 - ALC control 3 */
78 0x0000, /* R35 - Noise Gate */
79 0x0008, /* R36 - PLL N */
80 0x000C, /* R37 - PLL K 1 */
81 0x0093, /* R38 - PLL K 2 */
82 0x00E9, /* R39 - PLL K 3 */
83 0x0000, /* R40 */
84 0x0000, /* R41 - 3D control */
85 0x0000, /* R42 - OUT4 to ADC */
86 0x0000, /* R43 - Beep control */
87 0x0033, /* R44 - Input ctrl */
88 0x0010, /* R45 - Left INP PGA gain ctrl */
89 0x0010, /* R46 - Right INP PGA gain ctrl */
90 0x0100, /* R47 - Left ADC BOOST ctrl */
91 0x0100, /* R48 - Right ADC BOOST ctrl */
92 0x0002, /* R49 - Output ctrl */
93 0x0001, /* R50 - Left mixer ctrl */
94 0x0001, /* R51 - Right mixer ctrl */
95 0x0039, /* R52 - LOUT1 (HP) volume ctrl */
96 0x0039, /* R53 - ROUT1 (HP) volume ctrl */
97 0x0039, /* R54 - LOUT2 (SPK) volume ctrl */
98 0x0039, /* R55 - ROUT2 (SPK) volume ctrl */
99 0x0001, /* R56 - OUT3 mixer ctrl */
100 0x0001, /* R57 - OUT4 (MONO) mix ctrl */
101 0x0001, /* R58 */
102 0x0000, /* R59 */
103 0x0004, /* R60 - OUTPUT ctrl */
104 0x0000, /* R61 - BIAS CTRL */
105 0x0180, /* R62 */
106 0x0000 /* R63 */
107};
108
109/*
110 * latch bit 8 of these registers to ensure instant
111 * volume updates
112 */
113static const int volume_update_regs[] = {
114 WM8985_LEFT_DAC_DIGITAL_VOL,
115 WM8985_RIGHT_DAC_DIGITAL_VOL,
116 WM8985_LEFT_ADC_DIGITAL_VOL,
117 WM8985_RIGHT_ADC_DIGITAL_VOL,
118 WM8985_LOUT2_SPK_VOLUME_CTRL,
119 WM8985_ROUT2_SPK_VOLUME_CTRL,
120 WM8985_LOUT1_HP_VOLUME_CTRL,
121 WM8985_ROUT1_HP_VOLUME_CTRL,
122 WM8985_LEFT_INP_PGA_GAIN_CTRL,
123 WM8985_RIGHT_INP_PGA_GAIN_CTRL
124};
125
126struct wm8985_priv {
127 enum snd_soc_control_type control_type;
128 struct regulator_bulk_data supplies[WM8985_NUM_SUPPLIES];
129 unsigned int sysclk;
130 unsigned int bclk;
131};
132
133static const struct {
134 int div;
135 int ratio;
136} fs_ratios[] = {
137 { 10, 128 },
138 { 15, 192 },
139 { 20, 256 },
140 { 30, 384 },
141 { 40, 512 },
142 { 60, 768 },
143 { 80, 1024 },
144 { 120, 1536 }
145};
146
147static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
148
149static const int bclk_divs[] = {
150 1, 2, 4, 8, 16, 32
151};
152
153static int eqmode_get(struct snd_kcontrol *kcontrol,
154 struct snd_ctl_elem_value *ucontrol);
155static int eqmode_put(struct snd_kcontrol *kcontrol,
156 struct snd_ctl_elem_value *ucontrol);
157
158static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
159static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
160static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
161static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
162static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
163static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
164static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
165static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
166static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
167static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
168static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
169static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
170static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
171static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
172
173static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
174static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8985_ALC_CONTROL_1, 7,
175 alc_sel_text);
176
177static const char *alc_mode_text[] = { "ALC", "Limiter" };
178static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8985_ALC_CONTROL_3, 8,
179 alc_mode_text);
180
181static const char *filter_mode_text[] = { "Audio", "Application" };
182static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8985_ADC_CONTROL, 7,
183 filter_mode_text);
184
185static const char *eq_bw_text[] = { "Narrow", "Wide" };
186static const char *eqmode_text[] = { "Capture", "Playback" };
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DP		 187static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
188
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DP		 189static const char *eq1_cutoff_text[] = {
190 "80Hz", "105Hz", "135Hz", "175Hz"
191};
192static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8985_EQ1_LOW_SHELF, 5,
193 eq1_cutoff_text);
194static const char *eq2_cutoff_text[] = {
195 "230Hz", "300Hz", "385Hz", "500Hz"
196};
197static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8985_EQ2_PEAK_1, 8, eq_bw_text);
198static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8985_EQ2_PEAK_1, 5,
199 eq2_cutoff_text);
200static const char *eq3_cutoff_text[] = {
201 "650Hz", "850Hz", "1.1kHz", "1.4kHz"
202};
203static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8985_EQ3_PEAK_2, 8, eq_bw_text);
204static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8985_EQ3_PEAK_2, 5,
205 eq3_cutoff_text);
206static const char *eq4_cutoff_text[] = {
207 "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
208};
209static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8985_EQ4_PEAK_3, 8, eq_bw_text);
210static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8985_EQ4_PEAK_3, 5,
211 eq4_cutoff_text);
212static const char *eq5_cutoff_text[] = {
213 "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
214};
215static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8985_EQ5_HIGH_SHELF, 5,
216 eq5_cutoff_text);
217
218static const char *speaker_mode_text[] = { "Class A/B", "Class D" };
219static const SOC_ENUM_SINGLE_DECL(speaker_mode, 0x17, 8, speaker_mode_text);
220
221static const char *depth_3d_text[] = {
222 "Off",
223 "6.67%",
224 "13.3%",
225 "20%",
226 "26.7%",
227 "33.3%",
228 "40%",
229 "46.6%",
230 "53.3%",
231 "60%",
232 "66.7%",
233 "73.3%",
234 "80%",
235 "86.7%",
236 "93.3%",
237 "100%"
238};
239static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8985_3D_CONTROL, 0,
240 depth_3d_text);
241
242static const struct snd_kcontrol_new wm8985_snd_controls[] = {
243 SOC_SINGLE("Digital Loopback Switch", WM8985_COMPANDING_CONTROL,
244 0, 1, 0),
245
246 SOC_ENUM("ALC Capture Function", alc_sel),
247 SOC_SINGLE_TLV("ALC Capture Max Volume", WM8985_ALC_CONTROL_1,
248 3, 7, 0, alc_max_tlv),
249 SOC_SINGLE_TLV("ALC Capture Min Volume", WM8985_ALC_CONTROL_1,
250 0, 7, 0, alc_min_tlv),
251 SOC_SINGLE_TLV("ALC Capture Target Volume", WM8985_ALC_CONTROL_2,
252 0, 15, 0, alc_tar_tlv),
253 SOC_SINGLE("ALC Capture Attack", WM8985_ALC_CONTROL_3, 0, 10, 0),
254 SOC_SINGLE("ALC Capture Hold", WM8985_ALC_CONTROL_2, 4, 10, 0),
255 SOC_SINGLE("ALC Capture Decay", WM8985_ALC_CONTROL_3, 4, 10, 0),
256 SOC_ENUM("ALC Mode", alc_mode),
257 SOC_SINGLE("ALC Capture NG Switch", WM8985_NOISE_GATE,
258 3, 1, 0),
259 SOC_SINGLE("ALC Capture NG Threshold", WM8985_NOISE_GATE,
260 0, 7, 1),
261
262 SOC_DOUBLE_R_TLV("Capture Volume", WM8985_LEFT_ADC_DIGITAL_VOL,
263 WM8985_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
264 SOC_DOUBLE_R("Capture PGA ZC Switch", WM8985_LEFT_INP_PGA_GAIN_CTRL,
265 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
266 SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8985_LEFT_INP_PGA_GAIN_CTRL,
267 WM8985_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
268
269 SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
270 WM8985_LEFT_ADC_BOOST_CTRL, WM8985_RIGHT_ADC_BOOST_CTRL,
271 8, 1, 0, pga_boost_tlv),
272
273 SOC_DOUBLE("ADC Inversion Switch", WM8985_ADC_CONTROL, 0, 1, 1, 0),
274 SOC_SINGLE("ADC 128x Oversampling Switch", WM8985_ADC_CONTROL, 8, 1, 0),
275
276 SOC_DOUBLE_R_TLV("Playback Volume", WM8985_LEFT_DAC_DIGITAL_VOL,
277 WM8985_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
278
279 SOC_SINGLE("DAC Playback Limiter Switch", WM8985_DAC_LIMITER_1, 8, 1, 0),
280 SOC_SINGLE("DAC Playback Limiter Decay", WM8985_DAC_LIMITER_1, 4, 10, 0),
281 SOC_SINGLE("DAC Playback Limiter Attack", WM8985_DAC_LIMITER_1, 0, 11, 0),
282 SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8985_DAC_LIMITER_2,
283 4, 7, 1, lim_thresh_tlv),
284 SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8985_DAC_LIMITER_2,
285 0, 12, 0, lim_boost_tlv),
286 SOC_DOUBLE("DAC Inversion Switch", WM8985_DAC_CONTROL, 0, 1, 1, 0),
287 SOC_SINGLE("DAC Auto Mute Switch", WM8985_DAC_CONTROL, 2, 1, 0),
288 SOC_SINGLE("DAC 128x Oversampling Switch", WM8985_DAC_CONTROL, 3, 1, 0),
289
290 SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8985_LOUT1_HP_VOLUME_CTRL,
291 WM8985_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
292 SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
293 WM8985_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
294 SOC_DOUBLE_R("Headphone Switch", WM8985_LOUT1_HP_VOLUME_CTRL,
295 WM8985_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
296
297 SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8985_LOUT2_SPK_VOLUME_CTRL,
298 WM8985_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
299 SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
300 WM8985_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
301 SOC_DOUBLE_R("Speaker Switch", WM8985_LOUT2_SPK_VOLUME_CTRL,
302 WM8985_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
303
304 SOC_SINGLE("High Pass Filter Switch", WM8985_ADC_CONTROL, 8, 1, 0),
305 SOC_ENUM("High Pass Filter Mode", filter_mode),
306 SOC_SINGLE("High Pass Filter Cutoff", WM8985_ADC_CONTROL, 4, 7, 0),
307
308 SOC_DOUBLE_R_TLV("Aux Bypass Volume",
309 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 6, 7, 0,
310 aux_tlv),
311
312 SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
313 WM8985_LEFT_MIXER_CTRL, WM8985_RIGHT_MIXER_CTRL, 2, 7, 0,
314 bypass_tlv),
315
316 SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
317 SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
318 SOC_SINGLE_TLV("EQ1 Volume", WM8985_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
319 SOC_ENUM("EQ2 Bandwith", eq2_bw),
320 SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
321 SOC_SINGLE_TLV("EQ2 Volume", WM8985_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
322 SOC_ENUM("EQ3 Bandwith", eq3_bw),
323 SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
324 SOC_SINGLE_TLV("EQ3 Volume", WM8985_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
325 SOC_ENUM("EQ4 Bandwith", eq4_bw),
326 SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
327 SOC_SINGLE_TLV("EQ4 Volume", WM8985_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
328 SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
329 SOC_SINGLE_TLV("EQ5 Volume", WM8985_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
330
331 SOC_ENUM("3D Depth", depth_3d),
332
333 SOC_ENUM("Speaker Mode", speaker_mode)
334};
335
336static const struct snd_kcontrol_new left_out_mixer[] = {
337 SOC_DAPM_SINGLE("Line Switch", WM8985_LEFT_MIXER_CTRL, 1, 1, 0),
338 SOC_DAPM_SINGLE("Aux Switch", WM8985_LEFT_MIXER_CTRL, 5, 1, 0),
339 SOC_DAPM_SINGLE("PCM Switch", WM8985_LEFT_MIXER_CTRL, 0, 1, 0),
340};
341
342static const struct snd_kcontrol_new right_out_mixer[] = {
343 SOC_DAPM_SINGLE("Line Switch", WM8985_RIGHT_MIXER_CTRL, 1, 1, 0),
344 SOC_DAPM_SINGLE("Aux Switch", WM8985_RIGHT_MIXER_CTRL, 5, 1, 0),
345 SOC_DAPM_SINGLE("PCM Switch", WM8985_RIGHT_MIXER_CTRL, 0, 1, 0),
346};
347
348static const struct snd_kcontrol_new left_input_mixer[] = {
349 SOC_DAPM_SINGLE("L2 Switch", WM8985_INPUT_CTRL, 2, 1, 0),
350 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 1, 1, 0),
351 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 0, 1, 0),
352};
353
354static const struct snd_kcontrol_new right_input_mixer[] = {
355 SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
356 SOC_DAPM_SINGLE("MicN Switch", WM8985_INPUT_CTRL, 5, 1, 0),
357 SOC_DAPM_SINGLE("MicP Switch", WM8985_INPUT_CTRL, 4, 1, 0),
358};
359
360static const struct snd_kcontrol_new left_boost_mixer[] = {
361 SOC_DAPM_SINGLE_TLV("L2 Volume", WM8985_LEFT_ADC_BOOST_CTRL,
362 4, 7, 0, boost_tlv),
363 SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8985_LEFT_ADC_BOOST_CTRL,
364 0, 7, 0, boost_tlv)
365};
366
367static const struct snd_kcontrol_new right_boost_mixer[] = {
368 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
369 4, 7, 0, boost_tlv),
370 SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
371 0, 7, 0, boost_tlv)
372};
373
374static const struct snd_soc_dapm_widget wm8985_dapm_widgets[] = {
375 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8985_POWER_MANAGEMENT_3,
376 0, 0),
377 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8985_POWER_MANAGEMENT_3,
378 1, 0),
379 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8985_POWER_MANAGEMENT_2,
380 0, 0),
381 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8985_POWER_MANAGEMENT_2,
382 1, 0),
383
384 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8985_POWER_MANAGEMENT_3,
385 2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
386 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8985_POWER_MANAGEMENT_3,
387 3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
388
389 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8985_POWER_MANAGEMENT_2,
390 2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
391 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8985_POWER_MANAGEMENT_2,
392 3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
393
394 SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8985_POWER_MANAGEMENT_2,
395 4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
396 SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8985_POWER_MANAGEMENT_2,
397 5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
398
399 SND_SOC_DAPM_PGA("Left Capture PGA", WM8985_LEFT_INP_PGA_GAIN_CTRL,
400 6, 1, NULL, 0),
401 SND_SOC_DAPM_PGA("Right Capture PGA", WM8985_RIGHT_INP_PGA_GAIN_CTRL,
402 6, 1, NULL, 0),
403
404 SND_SOC_DAPM_PGA("Left Headphone Out", WM8985_POWER_MANAGEMENT_2,
405 7, 0, NULL, 0),
406 SND_SOC_DAPM_PGA("Right Headphone Out", WM8985_POWER_MANAGEMENT_2,
407 8, 0, NULL, 0),
408
409 SND_SOC_DAPM_PGA("Left Speaker Out", WM8985_POWER_MANAGEMENT_3,
410 5, 0, NULL, 0),
411 SND_SOC_DAPM_PGA("Right Speaker Out", WM8985_POWER_MANAGEMENT_3,
412 6, 0, NULL, 0),
413
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MB		 414 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8985_POWER_MANAGEMENT_1, 4, 0,
415 NULL, 0),
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DP		 416
417 SND_SOC_DAPM_INPUT("LIN"),
418 SND_SOC_DAPM_INPUT("LIP"),
419 SND_SOC_DAPM_INPUT("RIN"),
420 SND_SOC_DAPM_INPUT("RIP"),
421 SND_SOC_DAPM_INPUT("AUXL"),
422 SND_SOC_DAPM_INPUT("AUXR"),
423 SND_SOC_DAPM_INPUT("L2"),
424 SND_SOC_DAPM_INPUT("R2"),
425 SND_SOC_DAPM_OUTPUT("HPL"),
426 SND_SOC_DAPM_OUTPUT("HPR"),
427 SND_SOC_DAPM_OUTPUT("SPKL"),
428 SND_SOC_DAPM_OUTPUT("SPKR")
429};
430
eb8f7693 431static const struct snd_soc_dapm_route wm8985_dapm_routes[] = {
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DP		 432 { "Right Output Mixer", "PCM Switch", "Right DAC" },
433 { "Right Output Mixer", "Aux Switch", "AUXR" },
434 { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
435
436 { "Left Output Mixer", "PCM Switch", "Left DAC" },
437 { "Left Output Mixer", "Aux Switch", "AUXL" },
438 { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
439
440 { "Right Headphone Out", NULL, "Right Output Mixer" },
441 { "HPR", NULL, "Right Headphone Out" },
442
443 { "Left Headphone Out", NULL, "Left Output Mixer" },
444 { "HPL", NULL, "Left Headphone Out" },
445
446 { "Right Speaker Out", NULL, "Right Output Mixer" },
447 { "SPKR", NULL, "Right Speaker Out" },
448
449 { "Left Speaker Out", NULL, "Left Output Mixer" },
450 { "SPKL", NULL, "Left Speaker Out" },
451
452 { "Right ADC", NULL, "Right Boost Mixer" },
453
454 { "Right Boost Mixer", "AUXR Volume", "AUXR" },
455 { "Right Boost Mixer", NULL, "Right Capture PGA" },
456 { "Right Boost Mixer", "R2 Volume", "R2" },
457
458 { "Left ADC", NULL, "Left Boost Mixer" },
459
460 { "Left Boost Mixer", "AUXL Volume", "AUXL" },
461 { "Left Boost Mixer", NULL, "Left Capture PGA" },
462 { "Left Boost Mixer", "L2 Volume", "L2" },
463
464 { "Right Capture PGA", NULL, "Right Input Mixer" },
465 { "Left Capture PGA", NULL, "Left Input Mixer" },
466
467 { "Right Input Mixer", "R2 Switch", "R2" },
468 { "Right Input Mixer", "MicN Switch", "RIN" },
469 { "Right Input Mixer", "MicP Switch", "RIP" },
470
471 { "Left Input Mixer", "L2 Switch", "L2" },
472 { "Left Input Mixer", "MicN Switch", "LIN" },
473 { "Left Input Mixer", "MicP Switch", "LIP" },
474};
475
476static int eqmode_get(struct snd_kcontrol *kcontrol,
477 struct snd_ctl_elem_value *ucontrol)
478{
479 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
480 unsigned int reg;
481
482 reg = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
483 if (reg & WM8985_EQ3DMODE)
484 ucontrol->value.integer.value[0] = 1;
485 else
486 ucontrol->value.integer.value[0] = 0;
487
488 return 0;
489}
490
491static int eqmode_put(struct snd_kcontrol *kcontrol,
492 struct snd_ctl_elem_value *ucontrol)
493{
494 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
495 unsigned int regpwr2, regpwr3;
496 unsigned int reg_eq;
497
498 if (ucontrol->value.integer.value[0] != 0
499 && ucontrol->value.integer.value[0] != 1)
500 return -EINVAL;
501
502 reg_eq = snd_soc_read(codec, WM8985_EQ1_LOW_SHELF);
503 switch ((reg_eq & WM8985_EQ3DMODE) >> WM8985_EQ3DMODE_SHIFT) {
504 case 0:
505 if (!ucontrol->value.integer.value[0])
506 return 0;
507 break;
508 case 1:
509 if (ucontrol->value.integer.value[0])
510 return 0;
511 break;
512 }
513
514 regpwr2 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_2);
515 regpwr3 = snd_soc_read(codec, WM8985_POWER_MANAGEMENT_3);
516 /* disable the DACs and ADCs */
517 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_2,
518 WM8985_ADCENR_MASK | WM8985_ADCENL_MASK, 0);
519 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_3,
520 WM8985_DACENR_MASK | WM8985_DACENL_MASK, 0);
521 snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
522 WM8985_M128ENB_MASK, WM8985_M128ENB);
523 /* set the desired eqmode */
524 snd_soc_update_bits(codec, WM8985_EQ1_LOW_SHELF,
525 WM8985_EQ3DMODE_MASK,
526 ucontrol->value.integer.value[0]
527 << WM8985_EQ3DMODE_SHIFT);
528 /* restore DAC/ADC configuration */
529 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, regpwr2);
530 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, regpwr3);
531 return 0;
532}
533
6d6f8b83
DP		 534static int wm8985_reset(struct snd_soc_codec *codec)
535{
536 return snd_soc_write(codec, WM8985_SOFTWARE_RESET, 0x0);
537}
538
539static int wm8985_dac_mute(struct snd_soc_dai *dai, int mute)
540{
541 struct snd_soc_codec *codec = dai->codec;
542
543 return snd_soc_update_bits(codec, WM8985_DAC_CONTROL,
544 WM8985_SOFTMUTE_MASK,
545 !!mute << WM8985_SOFTMUTE_SHIFT);
546}
547
548static int wm8985_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
549{
6d6f8b83
DP		 550 struct snd_soc_codec *codec;
551 u16 format, master, bcp, lrp;
552
553 codec = dai->codec;
6d6f8b83
DP		 554
555 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
556 case SND_SOC_DAIFMT_I2S:
557 format = 0x2;
558 break;
559 case SND_SOC_DAIFMT_RIGHT_J:
560 format = 0x0;
561 break;
562 case SND_SOC_DAIFMT_LEFT_J:
563 format = 0x1;
564 break;
565 case SND_SOC_DAIFMT_DSP_A:
566 case SND_SOC_DAIFMT_DSP_B:
567 format = 0x3;
568 break;
569 default:
570 dev_err(dai->dev, "Unknown dai format\n");
571 return -EINVAL;
572 }
573
574 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
575 WM8985_FMT_MASK, format << WM8985_FMT_SHIFT);
576
577 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
578 case SND_SOC_DAIFMT_CBM_CFM:
579 master = 1;
580 break;
581 case SND_SOC_DAIFMT_CBS_CFS:
582 master = 0;
583 break;
584 default:
585 dev_err(dai->dev, "Unknown master/slave configuration\n");
586 return -EINVAL;
587 }
588
589 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
590 WM8985_MS_MASK, master << WM8985_MS_SHIFT);
591
592 /* frame inversion is not valid for dsp modes */
593 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
594 case SND_SOC_DAIFMT_DSP_A:
595 case SND_SOC_DAIFMT_DSP_B:
596 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
597 case SND_SOC_DAIFMT_IB_IF:
598 case SND_SOC_DAIFMT_NB_IF:
599 return -EINVAL;
600 default:
601 break;
602 }
603 break;
604 default:
605 break;
606 }
607
608 bcp = lrp = 0;
609 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
610 case SND_SOC_DAIFMT_NB_NF:
611 break;
612 case SND_SOC_DAIFMT_IB_IF:
613 bcp = lrp = 1;
614 break;
615 case SND_SOC_DAIFMT_IB_NF:
616 bcp = 1;
617 break;
618 case SND_SOC_DAIFMT_NB_IF:
619 lrp = 1;
620 break;
621 default:
622 dev_err(dai->dev, "Unknown polarity configuration\n");
623 return -EINVAL;
624 }
625
626 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
627 WM8985_LRP_MASK, lrp << WM8985_LRP_SHIFT);
628 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
629 WM8985_BCP_MASK, bcp << WM8985_BCP_SHIFT);
630 return 0;
631}
632
633static int wm8985_hw_params(struct snd_pcm_substream *substream,
634 struct snd_pcm_hw_params *params,
635 struct snd_soc_dai *dai)
636{
cf1ff501 637 int i;
6d6f8b83
DP		 638 struct snd_soc_codec *codec;
639 struct wm8985_priv *wm8985;
640 u16 blen, srate_idx;
641 unsigned int tmp;
642 int srate_best;
643
644 codec = dai->codec;
645 wm8985 = snd_soc_codec_get_drvdata(codec);
646
647 wm8985->bclk = snd_soc_params_to_bclk(params);
648 if ((int)wm8985->bclk < 0)
649 return wm8985->bclk;
650
651 switch (params_format(params)) {
652 case SNDRV_PCM_FORMAT_S16_LE:
653 blen = 0x0;
654 break;
655 case SNDRV_PCM_FORMAT_S20_3LE:
656 blen = 0x1;
657 break;
658 case SNDRV_PCM_FORMAT_S24_LE:
659 blen = 0x2;
660 break;
661 case SNDRV_PCM_FORMAT_S32_LE:
662 blen = 0x3;
663 break;
664 default:
665 dev_err(dai->dev, "Unsupported word length %u\n",
666 params_format(params));
667 return -EINVAL;
668 }
669
670 snd_soc_update_bits(codec, WM8985_AUDIO_INTERFACE,
671 WM8985_WL_MASK, blen << WM8985_WL_SHIFT);
672
673 /*
674 * match to the nearest possible sample rate and rely
675 * on the array index to configure the SR register
676 */
677 srate_idx = 0;
678 srate_best = abs(srates[0] - params_rate(params));
679 for (i = 1; i < ARRAY_SIZE(srates); ++i) {
680 if (abs(srates[i] - params_rate(params)) >= srate_best)
681 continue;
682 srate_idx = i;
683 srate_best = abs(srates[i] - params_rate(params));
684 }
685
686 dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
687 snd_soc_update_bits(codec, WM8985_ADDITIONAL_CONTROL,
688 WM8985_SR_MASK, srate_idx << WM8985_SR_SHIFT);
689
690 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk);
691 dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8985->sysclk);
692
693 for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
694 if (wm8985->sysclk / params_rate(params)
695 == fs_ratios[i].ratio)
696 break;
697 }
698
699 if (i == ARRAY_SIZE(fs_ratios)) {
700 dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
701 wm8985->sysclk, params_rate(params));
702 return -EINVAL;
703 }
704
705 dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
706 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
707 WM8985_MCLKDIV_MASK, i << WM8985_MCLKDIV_SHIFT);
708
709 /* select the appropriate bclk divider */
710 tmp = (wm8985->sysclk / fs_ratios[i].div) * 10;
711 for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
712 if (wm8985->bclk == tmp / bclk_divs[i])
713 break;
714 }
715
716 if (i == ARRAY_SIZE(bclk_divs)) {
717 dev_err(dai->dev, "No matching BCLK divider found\n");
718 return -EINVAL;
719 }
720
721 dev_dbg(dai->dev, "BCLK div = %d\n", i);
722 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
723 WM8985_BCLKDIV_MASK, i << WM8985_BCLKDIV_SHIFT);
724 return 0;
725}
726
727struct pll_div {
728 u32 div2:1;
729 u32 n:4;
730 u32 k:24;
731};
732
733#define FIXED_PLL_SIZE ((1ULL << 24) * 10)
734static int pll_factors(struct pll_div *pll_div, unsigned int target,
735 unsigned int source)
736{
737 u64 Kpart;
738 unsigned long int K, Ndiv, Nmod;
739
740 pll_div->div2 = 0;
741 Ndiv = target / source;
742 if (Ndiv < 6) {
743 source >>= 1;
744 pll_div->div2 = 1;
745 Ndiv = target / source;
746 }
747
748 if (Ndiv < 6 || Ndiv > 12) {
749 printk(KERN_ERR "%s: WM8985 N value is not within"
750 " the recommended range: %lu\n", __func__, Ndiv);
751 return -EINVAL;
752 }
753 pll_div->n = Ndiv;
754
755 Nmod = target % source;
756 Kpart = FIXED_PLL_SIZE * (u64)Nmod;
757
758 do_div(Kpart, source);
759
760 K = Kpart & 0xffffffff;
761 if ((K % 10) >= 5)
762 K += 5;
763 K /= 10;
764 pll_div->k = K;
765
766 return 0;
767}
768
769static int wm8985_set_pll(struct snd_soc_dai *dai, int pll_id,
770 int source, unsigned int freq_in,
771 unsigned int freq_out)
772{
773 int ret;
774 struct snd_soc_codec *codec;
775 struct pll_div pll_div;
776
777 codec = dai->codec;
778 if (freq_in && freq_out) {
779 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
780 if (ret)
781 return ret;
782 }
783
784 /* disable the PLL before reprogramming it */
785 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
786 WM8985_PLLEN_MASK, 0);
787
788 if (!freq_in || !freq_out)
789 return 0;
790
791 /* set PLLN and PRESCALE */
792 snd_soc_write(codec, WM8985_PLL_N,
793 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT)
794 | pll_div.n);
795 /* set PLLK */
796 snd_soc_write(codec, WM8985_PLL_K_3, pll_div.k & 0x1ff);
797 snd_soc_write(codec, WM8985_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
798 snd_soc_write(codec, WM8985_PLL_K_1, (pll_div.k >> 18));
799 /* set the source of the clock to be the PLL */
800 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
801 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
802 /* enable the PLL */
803 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
804 WM8985_PLLEN_MASK, WM8985_PLLEN);
805 return 0;
806}
807
808static int wm8985_set_sysclk(struct snd_soc_dai *dai,
809 int clk_id, unsigned int freq, int dir)
810{
811 struct snd_soc_codec *codec;
812 struct wm8985_priv *wm8985;
813
814 codec = dai->codec;
815 wm8985 = snd_soc_codec_get_drvdata(codec);
816
817 switch (clk_id) {
818 case WM8985_CLKSRC_MCLK:
819 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
820 WM8985_CLKSEL_MASK, 0);
821 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
822 WM8985_PLLEN_MASK, 0);
823 break;
824 case WM8985_CLKSRC_PLL:
825 snd_soc_update_bits(codec, WM8985_CLOCK_GEN_CONTROL,
826 WM8985_CLKSEL_MASK, WM8985_CLKSEL);
827 break;
828 default:
829 dev_err(dai->dev, "Unknown clock source %d\n", clk_id);
830 return -EINVAL;
831 }
832
833 wm8985->sysclk = freq;
834 return 0;
835}
836
6d6f8b83
DP		 837static int wm8985_set_bias_level(struct snd_soc_codec *codec,
838 enum snd_soc_bias_level level)
839{
840 int ret;
841 struct wm8985_priv *wm8985;
842
843 wm8985 = snd_soc_codec_get_drvdata(codec);
844 switch (level) {
845 case SND_SOC_BIAS_ON:
846 case SND_SOC_BIAS_PREPARE:
847 /* VMID at 75k */
848 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
849 WM8985_VMIDSEL_MASK,
850 1 << WM8985_VMIDSEL_SHIFT);
851 break;
852 case SND_SOC_BIAS_STANDBY:
ce6120cc 853 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
6d6f8b83
DP		 854 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
855 wm8985->supplies);
856 if (ret) {
857 dev_err(codec->dev,
858 "Failed to enable supplies: %d\n",
859 ret);
860 return ret;
861 }
862
8b71d441 863 snd_soc_cache_sync(codec);
6d6f8b83
DP		 864
865 /* enable anti-pop features */
866 snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
867 WM8985_POBCTRL_MASK,
868 WM8985_POBCTRL);
869 /* enable thermal shutdown */
870 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
871 WM8985_TSDEN_MASK, WM8985_TSDEN);
872 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
873 WM8985_TSOPCTRL_MASK,
874 WM8985_TSOPCTRL);
875 /* enable BIASEN */
876 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
877 WM8985_BIASEN_MASK, WM8985_BIASEN);
878 /* VMID at 75k */
879 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
880 WM8985_VMIDSEL_MASK,
881 1 << WM8985_VMIDSEL_SHIFT);
882 msleep(500);
883 /* disable anti-pop features */
884 snd_soc_update_bits(codec, WM8985_OUT4_TO_ADC,
885 WM8985_POBCTRL_MASK, 0);
886 }
887 /* VMID at 300k */
888 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
889 WM8985_VMIDSEL_MASK,
890 2 << WM8985_VMIDSEL_SHIFT);
891 break;
892 case SND_SOC_BIAS_OFF:
893 /* disable thermal shutdown */
894 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
895 WM8985_TSOPCTRL_MASK, 0);
896 snd_soc_update_bits(codec, WM8985_OUTPUT_CTRL0,
897 WM8985_TSDEN_MASK, 0);
898 /* disable VMIDSEL and BIASEN */
899 snd_soc_update_bits(codec, WM8985_POWER_MANAGEMENT_1,
900 WM8985_VMIDSEL_MASK | WM8985_BIASEN_MASK,
901 0);
902 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_1, 0);
903 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_2, 0);
904 snd_soc_write(codec, WM8985_POWER_MANAGEMENT_3, 0);
905
906 codec->cache_sync = 1;
907
908 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies),
909 wm8985->supplies);
910 break;
911 }
912
ce6120cc 913 codec->dapm.bias_level = level;
6d6f8b83
DP		 914 return 0;
915}
916
917#ifdef CONFIG_PM
84b315ee 918static int wm8985_suspend(struct snd_soc_codec *codec)
6d6f8b83
DP		 919{
920 wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
921 return 0;
922}
923
924static int wm8985_resume(struct snd_soc_codec *codec)
925{
926 wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
927 return 0;
928}
929#else
930#define wm8985_suspend NULL
931#define wm8985_resume NULL
932#endif
933
934static int wm8985_remove(struct snd_soc_codec *codec)
935{
936 struct wm8985_priv *wm8985;
937
938 wm8985 = snd_soc_codec_get_drvdata(codec);
939 wm8985_set_bias_level(codec, SND_SOC_BIAS_OFF);
940 regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
941 return 0;
942}
943
944static int wm8985_probe(struct snd_soc_codec *codec)
945{
946 size_t i;
947 struct wm8985_priv *wm8985;
948 int ret;
6d6f8b83
DP		 949
950 wm8985 = snd_soc_codec_get_drvdata(codec);
951
952 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8985->control_type);
953 if (ret < 0) {
954 dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
955 return ret;
956 }
957
958 for (i = 0; i < ARRAY_SIZE(wm8985->supplies); i++)
959 wm8985->supplies[i].supply = wm8985_supply_names[i];
960
961 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8985->supplies),
962 wm8985->supplies);
963 if (ret) {
964 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
965 return ret;
966 }
967
968 ret = regulator_bulk_enable(ARRAY_SIZE(wm8985->supplies),
969 wm8985->supplies);
970 if (ret) {
971 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
972 goto err_reg_get;
973 }
974
975 ret = wm8985_reset(codec);
976 if (ret < 0) {
977 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
978 goto err_reg_enable;
979 }
980
6d6f8b83
DP		 981 /* latch volume update bits */
982 for (i = 0; i < ARRAY_SIZE(volume_update_regs); ++i)
9f8cbae4
MB		 983 snd_soc_update_bits(codec, volume_update_regs[i],
984 0x100, 0x100);
6d6f8b83 985 /* enable BIASCUT */
9f8cbae4
MB		 986 snd_soc_update_bits(codec, WM8985_BIAS_CTRL, WM8985_BIASCUT,
987 WM8985_BIASCUT);
6d6f8b83 988
6d6f8b83
DP		 989 wm8985_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
990 return 0;
991
992err_reg_enable:
993 regulator_bulk_disable(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
994err_reg_get:
995 regulator_bulk_free(ARRAY_SIZE(wm8985->supplies), wm8985->supplies);
996 return ret;
997}
998
85e7652d 999static const struct snd_soc_dai_ops wm8985_dai_ops = {
6d6f8b83
DP		 1000 .digital_mute = wm8985_dac_mute,
1001 .hw_params = wm8985_hw_params,
1002 .set_fmt = wm8985_set_fmt,
1003 .set_sysclk = wm8985_set_sysclk,
1004 .set_pll = wm8985_set_pll
1005};
1006
1007#define WM8985_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1008 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1009
1010static struct snd_soc_dai_driver wm8985_dai = {
1011 .name = "wm8985-hifi",
1012 .playback = {
1013 .stream_name = "Playback",
1014 .channels_min = 2,
1015 .channels_max = 2,
1016 .rates = SNDRV_PCM_RATE_8000_48000,
1017 .formats = WM8985_FORMATS,
1018 },
1019 .capture = {
1020 .stream_name = "Capture",
1021 .channels_min = 2,
1022 .channels_max = 2,
1023 .rates = SNDRV_PCM_RATE_8000_48000,
1024 .formats = WM8985_FORMATS,
1025 },
1026 .ops = &wm8985_dai_ops,
1027 .symmetric_rates = 1
1028};
1029
1030static struct snd_soc_codec_driver soc_codec_dev_wm8985 = {
1031 .probe = wm8985_probe,
1032 .remove = wm8985_remove,
1033 .suspend = wm8985_suspend,
1034 .resume = wm8985_resume,
1035 .set_bias_level = wm8985_set_bias_level,
eb8f7693
MB		 1036
1037 .controls = wm8985_snd_controls,
1038 .num_controls = ARRAY_SIZE(wm8985_snd_controls),
1039 .dapm_widgets = wm8985_dapm_widgets,
6d6f8b83
DP		 1040 .reg_cache_size = ARRAY_SIZE(wm8985_reg_defs),
1041 .reg_word_size = sizeof(u16),
1042 .reg_cache_default = wm8985_reg_defs
eb8f7693
MB		 1043 .num_dapm_widgets = ARRAY_SIZE(wm8985_dapm_widgets),
1044 .dapm_routes = wm8985_dapm_routes,
1045 .num_dapm_routes = ARRAY_SIZE(wm8985_dapm_routes),
6d6f8b83
DP		 1046};
1047
1048#if defined(CONFIG_SPI_MASTER)
1049static int __devinit wm8985_spi_probe(struct spi_device *spi)
1050{
1051 struct wm8985_priv *wm8985;
1052 int ret;
1053
a1fea940 1054 wm8985 = devm_kzalloc(&spi->dev, sizeof *wm8985, GFP_KERNEL);
fe3e2e7f
DC		 1055 if (!wm8985)
1056 return -ENOMEM;
6d6f8b83
DP		 1057
1058 wm8985->control_type = SND_SOC_SPI;
1059 spi_set_drvdata(spi, wm8985);
1060
1061 ret = snd_soc_register_codec(&spi->dev,
1062 &soc_codec_dev_wm8985, &wm8985_dai, 1);
6d6f8b83
DP		 1063 return ret;
1064}
1065
1066static int __devexit wm8985_spi_remove(struct spi_device *spi)
1067{
1068 snd_soc_unregister_codec(&spi->dev);
6d6f8b83
DP		 1069 return 0;
1070}
1071
1072static struct spi_driver wm8985_spi_driver = {
1073 .driver = {
1074 .name = "wm8985",
6d6f8b83
DP		 1075 .owner = THIS_MODULE,
1076 },
1077 .probe = wm8985_spi_probe,
1078 .remove = __devexit_p(wm8985_spi_remove)
1079};
1080#endif
1081
1082#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1083static __devinit int wm8985_i2c_probe(struct i2c_client *i2c,
1084 const struct i2c_device_id *id)
1085{
1086 struct wm8985_priv *wm8985;
1087 int ret;
1088
a1fea940 1089 wm8985 = devm_kzalloc(&i2c->dev, sizeof *wm8985, GFP_KERNEL);
fe3e2e7f
DC		 1090 if (!wm8985)
1091 return -ENOMEM;
6d6f8b83
DP		 1092
1093 wm8985->control_type = SND_SOC_I2C;
1094 i2c_set_clientdata(i2c, wm8985);
1095
1096 ret = snd_soc_register_codec(&i2c->dev,
1097 &soc_codec_dev_wm8985, &wm8985_dai, 1);
6d6f8b83
DP		 1098 return ret;
1099}
1100
1101static __devexit int wm8985_i2c_remove(struct i2c_client *client)
1102{
1103 snd_soc_unregister_codec(&client->dev);
6d6f8b83
DP		 1104 return 0;
1105}
1106
1107static const struct i2c_device_id wm8985_i2c_id[] = {
1108 { "wm8985", 0 },
1109 { }
1110};
1111MODULE_DEVICE_TABLE(i2c, wm8985_i2c_id);
1112
1113static struct i2c_driver wm8985_i2c_driver = {
1114 .driver = {
1115 .name = "wm8985",
1116 .owner = THIS_MODULE,
1117 },
1118 .probe = wm8985_i2c_probe,
1119 .remove = __devexit_p(wm8985_i2c_remove),
1120 .id_table = wm8985_i2c_id
1121};
1122#endif
1123
1124static int __init wm8985_modinit(void)
1125{
1126 int ret = 0;
1127
1128#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1129 ret = i2c_add_driver(&wm8985_i2c_driver);
1130 if (ret) {
1131 printk(KERN_ERR "Failed to register wm8985 I2C driver: %d\n",
1132 ret);
1133 }
1134#endif
1135#if defined(CONFIG_SPI_MASTER)
1136 ret = spi_register_driver(&wm8985_spi_driver);
1137 if (ret != 0) {
1138 printk(KERN_ERR "Failed to register wm8985 SPI driver: %d\n",
1139 ret);
1140 }
1141#endif
1142 return ret;
1143}
1144module_init(wm8985_modinit);
1145
1146static void __exit wm8985_exit(void)
1147{
1148#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1149 i2c_del_driver(&wm8985_i2c_driver);
1150#endif
1151#if defined(CONFIG_SPI_MASTER)
1152 spi_unregister_driver(&wm8985_spi_driver);
1153#endif
1154}
1155module_exit(wm8985_exit);
1156
1157MODULE_DESCRIPTION("ASoC WM8985 driver");
1158MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
1159MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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