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ASoC: One more x86 typo fix
[deliverable/linux.git] / sound / soc / codecs / wm8988.c
CommitLineData
5409fb4e
MB		 1/*
2 * wm8988.c -- WM8988 ALSA SoC audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 * Copyright 2005 Openedhand Ltd.
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/spi/spi.h>
21#include <linux/platform_device.h>
5a0e3ad6 22#include <linux/slab.h>
5409fb4e
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/tlv.h>
27#include <sound/soc.h>
5409fb4e
MB		 28#include <sound/initval.h>
29
30#include "wm8988.h"
31
32/*
33 * wm8988 register cache
34 * We can't read the WM8988 register space when we
35 * are using 2 wire for device control, so we cache them instead.
36 */
37static const u16 wm8988_reg[] = {
38 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
39 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
40 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
41 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
42 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
43 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
44 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
45 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
46 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
47 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
48 0x0079, 0x0079, 0x0079, /* 40 */
49};
50
51/* codec private data */
52struct wm8988_priv {
53 unsigned int sysclk;
f0fba2ad 54 enum snd_soc_control_type control_type;
5409fb4e
MB		 55 struct snd_pcm_hw_constraint_list *sysclk_constraints;
56 u16 reg_cache[WM8988_NUM_REG];
57};
58
59
17a52fd6 60#define wm8988_reset(c) snd_soc_write(c, WM8988_RESET, 0)
5409fb4e
MB		 61
62/*
63 * WM8988 Controls
64 */
65
66static const char *bass_boost_txt[] = {"Linear Control", "Adaptive Boost"};
67static const struct soc_enum bass_boost =
68 SOC_ENUM_SINGLE(WM8988_BASS, 7, 2, bass_boost_txt);
69
70static const char *bass_filter_txt[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
71static const struct soc_enum bass_filter =
72 SOC_ENUM_SINGLE(WM8988_BASS, 6, 2, bass_filter_txt);
73
74static const char *treble_txt[] = {"8kHz", "4kHz"};
75static const struct soc_enum treble =
76 SOC_ENUM_SINGLE(WM8988_TREBLE, 6, 2, treble_txt);
77
78static const char *stereo_3d_lc_txt[] = {"200Hz", "500Hz"};
79static const struct soc_enum stereo_3d_lc =
80 SOC_ENUM_SINGLE(WM8988_3D, 5, 2, stereo_3d_lc_txt);
81
82static const char *stereo_3d_uc_txt[] = {"2.2kHz", "1.5kHz"};
83static const struct soc_enum stereo_3d_uc =
84 SOC_ENUM_SINGLE(WM8988_3D, 6, 2, stereo_3d_uc_txt);
85
86static const char *stereo_3d_func_txt[] = {"Capture", "Playback"};
87static const struct soc_enum stereo_3d_func =
88 SOC_ENUM_SINGLE(WM8988_3D, 7, 2, stereo_3d_func_txt);
89
90static const char *alc_func_txt[] = {"Off", "Right", "Left", "Stereo"};
91static const struct soc_enum alc_func =
92 SOC_ENUM_SINGLE(WM8988_ALC1, 7, 4, alc_func_txt);
93
94static const char *ng_type_txt[] = {"Constant PGA Gain",
95 "Mute ADC Output"};
96static const struct soc_enum ng_type =
97 SOC_ENUM_SINGLE(WM8988_NGATE, 1, 2, ng_type_txt);
98
99static const char *deemph_txt[] = {"None", "32Khz", "44.1Khz", "48Khz"};
100static const struct soc_enum deemph =
101 SOC_ENUM_SINGLE(WM8988_ADCDAC, 1, 4, deemph_txt);
102
103static const char *adcpol_txt[] = {"Normal", "L Invert", "R Invert",
104 "L + R Invert"};
105static const struct soc_enum adcpol =
106 SOC_ENUM_SINGLE(WM8988_ADCDAC, 5, 4, adcpol_txt);
107
108static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
109static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
110static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
111static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
112static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
113
114static const struct snd_kcontrol_new wm8988_snd_controls[] = {
115
116SOC_ENUM("Bass Boost", bass_boost),
117SOC_ENUM("Bass Filter", bass_filter),
118SOC_SINGLE("Bass Volume", WM8988_BASS, 0, 15, 1),
119
120SOC_SINGLE("Treble Volume", WM8988_TREBLE, 0, 15, 0),
121SOC_ENUM("Treble Cut-off", treble),
122
123SOC_SINGLE("3D Switch", WM8988_3D, 0, 1, 0),
124SOC_SINGLE("3D Volume", WM8988_3D, 1, 15, 0),
125SOC_ENUM("3D Lower Cut-off", stereo_3d_lc),
126SOC_ENUM("3D Upper Cut-off", stereo_3d_uc),
127SOC_ENUM("3D Mode", stereo_3d_func),
128
129SOC_SINGLE("ALC Capture Target Volume", WM8988_ALC1, 0, 7, 0),
130SOC_SINGLE("ALC Capture Max Volume", WM8988_ALC1, 4, 7, 0),
131SOC_ENUM("ALC Capture Function", alc_func),
132SOC_SINGLE("ALC Capture ZC Switch", WM8988_ALC2, 7, 1, 0),
133SOC_SINGLE("ALC Capture Hold Time", WM8988_ALC2, 0, 15, 0),
134SOC_SINGLE("ALC Capture Decay Time", WM8988_ALC3, 4, 15, 0),
135SOC_SINGLE("ALC Capture Attack Time", WM8988_ALC3, 0, 15, 0),
136SOC_SINGLE("ALC Capture NG Threshold", WM8988_NGATE, 3, 31, 0),
137SOC_ENUM("ALC Capture NG Type", ng_type),
138SOC_SINGLE("ALC Capture NG Switch", WM8988_NGATE, 0, 1, 0),
139
140SOC_SINGLE("ZC Timeout Switch", WM8988_ADCTL1, 0, 1, 0),
141
142SOC_DOUBLE_R_TLV("Capture Digital Volume", WM8988_LADC, WM8988_RADC,
143 0, 255, 0, adc_tlv),
144SOC_DOUBLE_R_TLV("Capture Volume", WM8988_LINVOL, WM8988_RINVOL,
145 0, 63, 0, pga_tlv),
146SOC_DOUBLE_R("Capture ZC Switch", WM8988_LINVOL, WM8988_RINVOL, 6, 1, 0),
147SOC_DOUBLE_R("Capture Switch", WM8988_LINVOL, WM8988_RINVOL, 7, 1, 1),
148
149SOC_ENUM("Playback De-emphasis", deemph),
150
151SOC_ENUM("Capture Polarity", adcpol),
152SOC_SINGLE("Playback 6dB Attenuate", WM8988_ADCDAC, 7, 1, 0),
153SOC_SINGLE("Capture 6dB Attenuate", WM8988_ADCDAC, 8, 1, 0),
154
155SOC_DOUBLE_R_TLV("PCM Volume", WM8988_LDAC, WM8988_RDAC, 0, 255, 0, dac_tlv),
156
157SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", WM8988_LOUTM1, 4, 7, 1,
158 bypass_tlv),
159SOC_SINGLE_TLV("Left Mixer Right Bypass Volume", WM8988_LOUTM2, 4, 7, 1,
160 bypass_tlv),
161SOC_SINGLE_TLV("Right Mixer Left Bypass Volume", WM8988_ROUTM1, 4, 7, 1,
162 bypass_tlv),
163SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", WM8988_ROUTM2, 4, 7, 1,
164 bypass_tlv),
165
166SOC_DOUBLE_R("Output 1 Playback ZC Switch", WM8988_LOUT1V,
167 WM8988_ROUT1V, 7, 1, 0),
168SOC_DOUBLE_R_TLV("Output 1 Playback Volume", WM8988_LOUT1V, WM8988_ROUT1V,
169 0, 127, 0, out_tlv),
170
171SOC_DOUBLE_R("Output 2 Playback ZC Switch", WM8988_LOUT2V,
172 WM8988_ROUT2V, 7, 1, 0),
173SOC_DOUBLE_R_TLV("Output 2 Playback Volume", WM8988_LOUT2V, WM8988_ROUT2V,
174 0, 127, 0, out_tlv),
175
176};
177
178/*
179 * DAPM Controls
180 */
181
182static int wm8988_lrc_control(struct snd_soc_dapm_widget *w,
183 struct snd_kcontrol *kcontrol, int event)
184{
185 struct snd_soc_codec *codec = w->codec;
17a52fd6 186 u16 adctl2 = snd_soc_read(codec, WM8988_ADCTL2);
5409fb4e
MB		 187
188 /* Use the DAC to gate LRC if active, otherwise use ADC */
17a52fd6 189 if (snd_soc_read(codec, WM8988_PWR2) & 0x180)
5409fb4e
MB		 190 adctl2 &= ~0x4;
191 else
192 adctl2 |= 0x4;
193
17a52fd6 194 return snd_soc_write(codec, WM8988_ADCTL2, adctl2);
5409fb4e
MB		 195}
196
197static const char *wm8988_line_texts[] = {
198 "Line 1", "Line 2", "PGA", "Differential"};
199
200static const unsigned int wm8988_line_values[] = {
201 0, 1, 3, 4};
202
203static const struct soc_enum wm8988_lline_enum =
204 SOC_VALUE_ENUM_SINGLE(WM8988_LOUTM1, 0, 7,
205 ARRAY_SIZE(wm8988_line_texts),
206 wm8988_line_texts,
207 wm8988_line_values);
208static const struct snd_kcontrol_new wm8988_left_line_controls =
209 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
210
211static const struct soc_enum wm8988_rline_enum =
212 SOC_VALUE_ENUM_SINGLE(WM8988_ROUTM1, 0, 7,
213 ARRAY_SIZE(wm8988_line_texts),
214 wm8988_line_texts,
215 wm8988_line_values);
216static const struct snd_kcontrol_new wm8988_right_line_controls =
217 SOC_DAPM_VALUE_ENUM("Route", wm8988_lline_enum);
218
219/* Left Mixer */
220static const struct snd_kcontrol_new wm8988_left_mixer_controls[] = {
221 SOC_DAPM_SINGLE("Playback Switch", WM8988_LOUTM1, 8, 1, 0),
222 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_LOUTM1, 7, 1, 0),
223 SOC_DAPM_SINGLE("Right Playback Switch", WM8988_LOUTM2, 8, 1, 0),
224 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_LOUTM2, 7, 1, 0),
225};
226
227/* Right Mixer */
228static const struct snd_kcontrol_new wm8988_right_mixer_controls[] = {
229 SOC_DAPM_SINGLE("Left Playback Switch", WM8988_ROUTM1, 8, 1, 0),
230 SOC_DAPM_SINGLE("Left Bypass Switch", WM8988_ROUTM1, 7, 1, 0),
231 SOC_DAPM_SINGLE("Playback Switch", WM8988_ROUTM2, 8, 1, 0),
232 SOC_DAPM_SINGLE("Right Bypass Switch", WM8988_ROUTM2, 7, 1, 0),
233};
234
235static const char *wm8988_pga_sel[] = {"Line 1", "Line 2", "Differential"};
236static const unsigned int wm8988_pga_val[] = { 0, 1, 3 };
237
238/* Left PGA Mux */
239static const struct soc_enum wm8988_lpga_enum =
240 SOC_VALUE_ENUM_SINGLE(WM8988_LADCIN, 6, 3,
241 ARRAY_SIZE(wm8988_pga_sel),
242 wm8988_pga_sel,
243 wm8988_pga_val);
244static const struct snd_kcontrol_new wm8988_left_pga_controls =
245 SOC_DAPM_VALUE_ENUM("Route", wm8988_lpga_enum);
246
247/* Right PGA Mux */
248static const struct soc_enum wm8988_rpga_enum =
249 SOC_VALUE_ENUM_SINGLE(WM8988_RADCIN, 6, 3,
250 ARRAY_SIZE(wm8988_pga_sel),
251 wm8988_pga_sel,
252 wm8988_pga_val);
253static const struct snd_kcontrol_new wm8988_right_pga_controls =
254 SOC_DAPM_VALUE_ENUM("Route", wm8988_rpga_enum);
255
256/* Differential Mux */
257static const char *wm8988_diff_sel[] = {"Line 1", "Line 2"};
258static const struct soc_enum diffmux =
259 SOC_ENUM_SINGLE(WM8988_ADCIN, 8, 2, wm8988_diff_sel);
260static const struct snd_kcontrol_new wm8988_diffmux_controls =
261 SOC_DAPM_ENUM("Route", diffmux);
262
263/* Mono ADC Mux */
264static const char *wm8988_mono_mux[] = {"Stereo", "Mono (Left)",
265 "Mono (Right)", "Digital Mono"};
266static const struct soc_enum monomux =
267 SOC_ENUM_SINGLE(WM8988_ADCIN, 6, 4, wm8988_mono_mux);
268static const struct snd_kcontrol_new wm8988_monomux_controls =
269 SOC_DAPM_ENUM("Route", monomux);
270
271static const struct snd_soc_dapm_widget wm8988_dapm_widgets[] = {
272 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8988_PWR1, 1, 0),
273
274 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
275 &wm8988_diffmux_controls),
276 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
277 &wm8988_monomux_controls),
278 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
279 &wm8988_monomux_controls),
280
281 SND_SOC_DAPM_MUX("Left PGA Mux", WM8988_PWR1, 5, 0,
282 &wm8988_left_pga_controls),
283 SND_SOC_DAPM_MUX("Right PGA Mux", WM8988_PWR1, 4, 0,
284 &wm8988_right_pga_controls),
285
286 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
287 &wm8988_left_line_controls),
288 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
289 &wm8988_right_line_controls),
290
291 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8988_PWR1, 2, 0),
292 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8988_PWR1, 3, 0),
293
294 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8988_PWR2, 7, 0),
295 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8988_PWR2, 8, 0),
296
297 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
298 &wm8988_left_mixer_controls[0],
299 ARRAY_SIZE(wm8988_left_mixer_controls)),
300 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
301 &wm8988_right_mixer_controls[0],
302 ARRAY_SIZE(wm8988_right_mixer_controls)),
303
304 SND_SOC_DAPM_PGA("Right Out 2", WM8988_PWR2, 3, 0, NULL, 0),
305 SND_SOC_DAPM_PGA("Left Out 2", WM8988_PWR2, 4, 0, NULL, 0),
306 SND_SOC_DAPM_PGA("Right Out 1", WM8988_PWR2, 5, 0, NULL, 0),
307 SND_SOC_DAPM_PGA("Left Out 1", WM8988_PWR2, 6, 0, NULL, 0),
308
309 SND_SOC_DAPM_POST("LRC control", wm8988_lrc_control),
310
311 SND_SOC_DAPM_OUTPUT("LOUT1"),
312 SND_SOC_DAPM_OUTPUT("ROUT1"),
313 SND_SOC_DAPM_OUTPUT("LOUT2"),
314 SND_SOC_DAPM_OUTPUT("ROUT2"),
315 SND_SOC_DAPM_OUTPUT("VREF"),
316
317 SND_SOC_DAPM_INPUT("LINPUT1"),
318 SND_SOC_DAPM_INPUT("LINPUT2"),
319 SND_SOC_DAPM_INPUT("RINPUT1"),
320 SND_SOC_DAPM_INPUT("RINPUT2"),
321};
322
323static const struct snd_soc_dapm_route audio_map[] = {
324
325 { "Left Line Mux", "Line 1", "LINPUT1" },
326 { "Left Line Mux", "Line 2", "LINPUT2" },
327 { "Left Line Mux", "PGA", "Left PGA Mux" },
328 { "Left Line Mux", "Differential", "Differential Mux" },
329
330 { "Right Line Mux", "Line 1", "RINPUT1" },
331 { "Right Line Mux", "Line 2", "RINPUT2" },
332 { "Right Line Mux", "PGA", "Right PGA Mux" },
333 { "Right Line Mux", "Differential", "Differential Mux" },
334
335 { "Left PGA Mux", "Line 1", "LINPUT1" },
336 { "Left PGA Mux", "Line 2", "LINPUT2" },
337 { "Left PGA Mux", "Differential", "Differential Mux" },
338
339 { "Right PGA Mux", "Line 1", "RINPUT1" },
340 { "Right PGA Mux", "Line 2", "RINPUT2" },
341 { "Right PGA Mux", "Differential", "Differential Mux" },
342
343 { "Differential Mux", "Line 1", "LINPUT1" },
344 { "Differential Mux", "Line 1", "RINPUT1" },
345 { "Differential Mux", "Line 2", "LINPUT2" },
346 { "Differential Mux", "Line 2", "RINPUT2" },
347
348 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
349 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
350 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
351
352 { "Right ADC Mux", "Stereo", "Right PGA Mux" },
353 { "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
354 { "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
355
356 { "Left ADC", NULL, "Left ADC Mux" },
357 { "Right ADC", NULL, "Right ADC Mux" },
358
359 { "Left Line Mux", "Line 1", "LINPUT1" },
360 { "Left Line Mux", "Line 2", "LINPUT2" },
361 { "Left Line Mux", "PGA", "Left PGA Mux" },
362 { "Left Line Mux", "Differential", "Differential Mux" },
363
364 { "Right Line Mux", "Line 1", "RINPUT1" },
365 { "Right Line Mux", "Line 2", "RINPUT2" },
366 { "Right Line Mux", "PGA", "Right PGA Mux" },
367 { "Right Line Mux", "Differential", "Differential Mux" },
368
369 { "Left Mixer", "Playback Switch", "Left DAC" },
370 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
371 { "Left Mixer", "Right Playback Switch", "Right DAC" },
372 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
373
374 { "Right Mixer", "Left Playback Switch", "Left DAC" },
375 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
376 { "Right Mixer", "Playback Switch", "Right DAC" },
377 { "Right Mixer", "Right Bypass Switch", "Right Line Mux" },
378
379 { "Left Out 1", NULL, "Left Mixer" },
380 { "LOUT1", NULL, "Left Out 1" },
381 { "Right Out 1", NULL, "Right Mixer" },
382 { "ROUT1", NULL, "Right Out 1" },
383
384 { "Left Out 2", NULL, "Left Mixer" },
385 { "LOUT2", NULL, "Left Out 2" },
386 { "Right Out 2", NULL, "Right Mixer" },
387 { "ROUT2", NULL, "Right Out 2" },
388};
389
390struct _coeff_div {
391 u32 mclk;
392 u32 rate;
393 u16 fs;
394 u8 sr:5;
395 u8 usb:1;
396};
397
398/* codec hifi mclk clock divider coefficients */
399static const struct _coeff_div coeff_div[] = {
400 /* 8k */
401 {12288000, 8000, 1536, 0x6, 0x0},
402 {11289600, 8000, 1408, 0x16, 0x0},
403 {18432000, 8000, 2304, 0x7, 0x0},
404 {16934400, 8000, 2112, 0x17, 0x0},
405 {12000000, 8000, 1500, 0x6, 0x1},
406
407 /* 11.025k */
408 {11289600, 11025, 1024, 0x18, 0x0},
409 {16934400, 11025, 1536, 0x19, 0x0},
410 {12000000, 11025, 1088, 0x19, 0x1},
411
412 /* 16k */
413 {12288000, 16000, 768, 0xa, 0x0},
414 {18432000, 16000, 1152, 0xb, 0x0},
415 {12000000, 16000, 750, 0xa, 0x1},
416
417 /* 22.05k */
418 {11289600, 22050, 512, 0x1a, 0x0},
419 {16934400, 22050, 768, 0x1b, 0x0},
420 {12000000, 22050, 544, 0x1b, 0x1},
421
422 /* 32k */
423 {12288000, 32000, 384, 0xc, 0x0},
424 {18432000, 32000, 576, 0xd, 0x0},
425 {12000000, 32000, 375, 0xa, 0x1},
426
427 /* 44.1k */
428 {11289600, 44100, 256, 0x10, 0x0},
429 {16934400, 44100, 384, 0x11, 0x0},
430 {12000000, 44100, 272, 0x11, 0x1},
431
432 /* 48k */
433 {12288000, 48000, 256, 0x0, 0x0},
434 {18432000, 48000, 384, 0x1, 0x0},
435 {12000000, 48000, 250, 0x0, 0x1},
436
437 /* 88.2k */
438 {11289600, 88200, 128, 0x1e, 0x0},
439 {16934400, 88200, 192, 0x1f, 0x0},
440 {12000000, 88200, 136, 0x1f, 0x1},
441
442 /* 96k */
443 {12288000, 96000, 128, 0xe, 0x0},
444 {18432000, 96000, 192, 0xf, 0x0},
445 {12000000, 96000, 125, 0xe, 0x1},
446};
447
448static inline int get_coeff(int mclk, int rate)
449{
450 int i;
451
452 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
453 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
454 return i;
455 }
456
457 return -EINVAL;
458}
459
460/* The set of rates we can generate from the above for each SYSCLK */
461
462static unsigned int rates_12288[] = {
463 8000, 12000, 16000, 24000, 24000, 32000, 48000, 96000,
464};
465
466static struct snd_pcm_hw_constraint_list constraints_12288 = {
467 .count = ARRAY_SIZE(rates_12288),
468 .list = rates_12288,
469};
470
471static unsigned int rates_112896[] = {
472 8000, 11025, 22050, 44100,
473};
474
475static struct snd_pcm_hw_constraint_list constraints_112896 = {
476 .count = ARRAY_SIZE(rates_112896),
477 .list = rates_112896,
478};
479
480static unsigned int rates_12[] = {
481 8000, 11025, 12000, 16000, 22050, 2400, 32000, 41100, 48000,
482 48000, 88235, 96000,
483};
484
485static struct snd_pcm_hw_constraint_list constraints_12 = {
486 .count = ARRAY_SIZE(rates_12),
487 .list = rates_12,
488};
489
490/*
491 * Note that this should be called from init rather than from hw_params.
492 */
493static int wm8988_set_dai_sysclk(struct snd_soc_dai *codec_dai,
494 int clk_id, unsigned int freq, int dir)
495{
496 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 497 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e
MB		 498
499 switch (freq) {
500 case 11289600:
501 case 18432000:
502 case 22579200:
503 case 36864000:
504 wm8988->sysclk_constraints = &constraints_112896;
505 wm8988->sysclk = freq;
506 return 0;
507
508 case 12288000:
509 case 16934400:
510 case 24576000:
511 case 33868800:
512 wm8988->sysclk_constraints = &constraints_12288;
513 wm8988->sysclk = freq;
514 return 0;
515
516 case 12000000:
517 case 24000000:
518 wm8988->sysclk_constraints = &constraints_12;
519 wm8988->sysclk = freq;
520 return 0;
521 }
522 return -EINVAL;
523}
524
525static int wm8988_set_dai_fmt(struct snd_soc_dai *codec_dai,
526 unsigned int fmt)
527{
528 struct snd_soc_codec *codec = codec_dai->codec;
529 u16 iface = 0;
530
531 /* set master/slave audio interface */
532 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
533 case SND_SOC_DAIFMT_CBM_CFM:
534 iface = 0x0040;
535 break;
536 case SND_SOC_DAIFMT_CBS_CFS:
537 break;
538 default:
539 return -EINVAL;
540 }
541
542 /* interface format */
543 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
544 case SND_SOC_DAIFMT_I2S:
545 iface |= 0x0002;
546 break;
547 case SND_SOC_DAIFMT_RIGHT_J:
548 break;
549 case SND_SOC_DAIFMT_LEFT_J:
550 iface |= 0x0001;
551 break;
552 case SND_SOC_DAIFMT_DSP_A:
553 iface |= 0x0003;
554 break;
555 case SND_SOC_DAIFMT_DSP_B:
556 iface |= 0x0013;
557 break;
558 default:
559 return -EINVAL;
560 }
561
562 /* clock inversion */
563 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
564 case SND_SOC_DAIFMT_NB_NF:
565 break;
566 case SND_SOC_DAIFMT_IB_IF:
567 iface |= 0x0090;
568 break;
569 case SND_SOC_DAIFMT_IB_NF:
570 iface |= 0x0080;
571 break;
572 case SND_SOC_DAIFMT_NB_IF:
573 iface |= 0x0010;
574 break;
575 default:
576 return -EINVAL;
577 }
578
17a52fd6 579 snd_soc_write(codec, WM8988_IFACE, iface);
5409fb4e
MB		 580 return 0;
581}
582
583static int wm8988_pcm_startup(struct snd_pcm_substream *substream,
584 struct snd_soc_dai *dai)
585{
586 struct snd_soc_codec *codec = dai->codec;
b2c812e2 587 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
5409fb4e
MB		 588
589 /* The set of sample rates that can be supported depends on the
590 * MCLK supplied to the CODEC - enforce this.
591 */
592 if (!wm8988->sysclk) {
593 dev_err(codec->dev,
594 "No MCLK configured, call set_sysclk() on init\n");
595 return -EINVAL;
596 }
597
598 snd_pcm_hw_constraint_list(substream->runtime, 0,
599 SNDRV_PCM_HW_PARAM_RATE,
600 wm8988->sysclk_constraints);
601
602 return 0;
603}
604
605static int wm8988_pcm_hw_params(struct snd_pcm_substream *substream,
606 struct snd_pcm_hw_params *params,
607 struct snd_soc_dai *dai)
608{
609 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 610 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 611 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
17a52fd6
MB		 612 u16 iface = snd_soc_read(codec, WM8988_IFACE) & 0x1f3;
613 u16 srate = snd_soc_read(codec, WM8988_SRATE) & 0x180;
5409fb4e
MB		 614 int coeff;
615
616 coeff = get_coeff(wm8988->sysclk, params_rate(params));
617 if (coeff < 0) {
618 coeff = get_coeff(wm8988->sysclk / 2, params_rate(params));
619 srate |= 0x40;
620 }
621 if (coeff < 0) {
622 dev_err(codec->dev,
623 "Unable to configure sample rate %dHz with %dHz MCLK\n",
624 params_rate(params), wm8988->sysclk);
625 return coeff;
626 }
627
628 /* bit size */
629 switch (params_format(params)) {
630 case SNDRV_PCM_FORMAT_S16_LE:
631 break;
632 case SNDRV_PCM_FORMAT_S20_3LE:
633 iface |= 0x0004;
634 break;
635 case SNDRV_PCM_FORMAT_S24_LE:
636 iface |= 0x0008;
637 break;
638 case SNDRV_PCM_FORMAT_S32_LE:
639 iface |= 0x000c;
640 break;
641 }
642
643 /* set iface & srate */
17a52fd6 644 snd_soc_write(codec, WM8988_IFACE, iface);
5409fb4e 645 if (coeff >= 0)
17a52fd6 646 snd_soc_write(codec, WM8988_SRATE, srate |
5409fb4e
MB		 647 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
648
649 return 0;
650}
651
652static int wm8988_mute(struct snd_soc_dai *dai, int mute)
653{
654 struct snd_soc_codec *codec = dai->codec;
17a52fd6 655 u16 mute_reg = snd_soc_read(codec, WM8988_ADCDAC) & 0xfff7;
5409fb4e
MB		 656
657 if (mute)
17a52fd6 658 snd_soc_write(codec, WM8988_ADCDAC, mute_reg | 0x8);
5409fb4e 659 else
17a52fd6 660 snd_soc_write(codec, WM8988_ADCDAC, mute_reg);
5409fb4e
MB		 661 return 0;
662}
663
664static int wm8988_set_bias_level(struct snd_soc_codec *codec,
665 enum snd_soc_bias_level level)
666{
17a52fd6 667 u16 pwr_reg = snd_soc_read(codec, WM8988_PWR1) & ~0x1c1;
5409fb4e
MB		 668
669 switch (level) {
670 case SND_SOC_BIAS_ON:
671 break;
672
673 case SND_SOC_BIAS_PREPARE:
674 /* VREF, VMID=2x50k, digital enabled */
17a52fd6 675 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x00c0);
5409fb4e
MB		 676 break;
677
678 case SND_SOC_BIAS_STANDBY:
ce6120cc 679 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
5409fb4e 680 /* VREF, VMID=2x5k */
17a52fd6 681 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x1c1);
5409fb4e
MB		 682
683 /* Charge caps */
684 msleep(100);
685 }
686
687 /* VREF, VMID=2*500k, digital stopped */
17a52fd6 688 snd_soc_write(codec, WM8988_PWR1, pwr_reg | 0x0141);
5409fb4e
MB		 689 break;
690
691 case SND_SOC_BIAS_OFF:
17a52fd6 692 snd_soc_write(codec, WM8988_PWR1, 0x0000);
5409fb4e
MB		 693 break;
694 }
ce6120cc 695 codec->dapm.bias_level = level;
5409fb4e
MB		 696 return 0;
697}
698
699#define WM8988_RATES SNDRV_PCM_RATE_8000_96000
700
701#define WM8988_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
702 SNDRV_PCM_FMTBIT_S24_LE)
703
704static struct snd_soc_dai_ops wm8988_ops = {
705 .startup = wm8988_pcm_startup,
706 .hw_params = wm8988_pcm_hw_params,
707 .set_fmt = wm8988_set_dai_fmt,
708 .set_sysclk = wm8988_set_dai_sysclk,
709 .digital_mute = wm8988_mute,
710};
711
f0fba2ad
LG		 712static struct snd_soc_dai_driver wm8988_dai = {
713 .name = "wm8988-hifi",
5409fb4e
MB		 714 .playback = {
715 .stream_name = "Playback",
716 .channels_min = 1,
717 .channels_max = 2,
718 .rates = WM8988_RATES,
719 .formats = WM8988_FORMATS,
720 },
721 .capture = {
722 .stream_name = "Capture",
723 .channels_min = 1,
724 .channels_max = 2,
725 .rates = WM8988_RATES,
726 .formats = WM8988_FORMATS,
727 },
728 .ops = &wm8988_ops,
729 .symmetric_rates = 1,
730};
5409fb4e 731
f0fba2ad 732static int wm8988_suspend(struct snd_soc_codec *codec, pm_message_t state)
5409fb4e 733{
5409fb4e
MB		 734 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
735 return 0;
736}
737
f0fba2ad 738static int wm8988_resume(struct snd_soc_codec *codec)
5409fb4e 739{
5409fb4e
MB		 740 int i;
741 u8 data[2];
742 u16 *cache = codec->reg_cache;
743
744 /* Sync reg_cache with the hardware */
745 for (i = 0; i < WM8988_NUM_REG; i++) {
746 if (i == WM8988_RESET)
747 continue;
748 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
749 data[1] = cache[i] & 0x00ff;
750 codec->hw_write(codec->control_data, data, 2);
751 }
752
753 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
754
755 return 0;
756}
757
f0fba2ad 758static int wm8988_probe(struct snd_soc_codec *codec)
5409fb4e 759{
f0fba2ad 760 struct wm8988_priv *wm8988 = snd_soc_codec_get_drvdata(codec);
ce6120cc 761 struct snd_soc_dapm_context *dapm = &codec->dapm;
5409fb4e 762 int ret = 0;
5409fb4e
MB		 763 u16 reg;
764
f0fba2ad 765 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8988->control_type);
17a52fd6
MB		 766 if (ret < 0) {
767 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 768 return ret;
17a52fd6
MB		 769 }
770
5409fb4e
MB		 771 ret = wm8988_reset(codec);
772 if (ret < 0) {
773 dev_err(codec->dev, "Failed to issue reset\n");
f0fba2ad 774 return ret;
5409fb4e
MB		 775 }
776
777 /* set the update bits (we always update left then right) */
17a52fd6
MB		 778 reg = snd_soc_read(codec, WM8988_RADC);
779 snd_soc_write(codec, WM8988_RADC, reg | 0x100);
780 reg = snd_soc_read(codec, WM8988_RDAC);
781 snd_soc_write(codec, WM8988_RDAC, reg | 0x0100);
782 reg = snd_soc_read(codec, WM8988_ROUT1V);
783 snd_soc_write(codec, WM8988_ROUT1V, reg | 0x0100);
784 reg = snd_soc_read(codec, WM8988_ROUT2V);
785 snd_soc_write(codec, WM8988_ROUT2V, reg | 0x0100);
786 reg = snd_soc_read(codec, WM8988_RINVOL);
787 snd_soc_write(codec, WM8988_RINVOL, reg | 0x0100);
5409fb4e 788
f0fba2ad 789 wm8988_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
5409fb4e 790
f0fba2ad
LG		 791 snd_soc_add_controls(codec, wm8988_snd_controls,
792 ARRAY_SIZE(wm8988_snd_controls));
ce6120cc 793 snd_soc_dapm_new_controls(dapm, wm8988_dapm_widgets,
f0fba2ad 794 ARRAY_SIZE(wm8988_dapm_widgets));
ce6120cc 795 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
5409fb4e
MB		 796
797 return 0;
5409fb4e
MB		 798}
799
f0fba2ad 800static int wm8988_remove(struct snd_soc_codec *codec)
5409fb4e 801{
f0fba2ad
LG		 802 wm8988_set_bias_level(codec, SND_SOC_BIAS_OFF);
803 return 0;
5409fb4e
MB		 804}
805
f0fba2ad
LG		 806static struct snd_soc_codec_driver soc_codec_dev_wm8988 = {
807 .probe = wm8988_probe,
808 .remove = wm8988_remove,
809 .suspend = wm8988_suspend,
810 .resume = wm8988_resume,
811 .set_bias_level = wm8988_set_bias_level,
e5eec34c 812 .reg_cache_size = ARRAY_SIZE(wm8988_reg),
f0fba2ad
LG		 813 .reg_word_size = sizeof(u16),
814 .reg_cache_default = wm8988_reg,
815};
816
817#if defined(CONFIG_SPI_MASTER)
818static int __devinit wm8988_spi_probe(struct spi_device *spi)
5409fb4e
MB		 819{
820 struct wm8988_priv *wm8988;
f0fba2ad 821 int ret;
5409fb4e
MB		 822
823 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
824 if (wm8988 == NULL)
825 return -ENOMEM;
826
f0fba2ad
LG		 827 wm8988->control_type = SND_SOC_SPI;
828 spi_set_drvdata(spi, wm8988);
5409fb4e 829
f0fba2ad
LG		 830 ret = snd_soc_register_codec(&spi->dev,
831 &soc_codec_dev_wm8988, &wm8988_dai, 1);
832 if (ret < 0)
833 kfree(wm8988);
834 return ret;
5409fb4e
MB		 835}
836
f0fba2ad 837static int __devexit wm8988_spi_remove(struct spi_device *spi)
5409fb4e 838{
f0fba2ad
LG		 839 snd_soc_unregister_codec(&spi->dev);
840 kfree(spi_get_drvdata(spi));
5409fb4e
MB		 841 return 0;
842}
843
f0fba2ad 844static struct spi_driver wm8988_spi_driver = {
5409fb4e 845 .driver = {
f0fba2ad 846 .name = "wm8988-codec",
f0fba2ad 847 .owner = THIS_MODULE,
5409fb4e 848 },
f0fba2ad
LG		 849 .probe = wm8988_spi_probe,
850 .remove = __devexit_p(wm8988_spi_remove),
5409fb4e 851};
f0fba2ad 852#endif /* CONFIG_SPI_MASTER */
5409fb4e 853
f0fba2ad
LG		 854#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
855static __devinit int wm8988_i2c_probe(struct i2c_client *i2c,
856 const struct i2c_device_id *id)
5409fb4e
MB		 857{
858 struct wm8988_priv *wm8988;
f0fba2ad 859 int ret;
5409fb4e
MB		 860
861 wm8988 = kzalloc(sizeof(struct wm8988_priv), GFP_KERNEL);
862 if (wm8988 == NULL)
863 return -ENOMEM;
864
f0fba2ad 865 i2c_set_clientdata(i2c, wm8988);
f0fba2ad 866 wm8988->control_type = SND_SOC_I2C;
5409fb4e 867
f0fba2ad
LG		 868 ret = snd_soc_register_codec(&i2c->dev,
869 &soc_codec_dev_wm8988, &wm8988_dai, 1);
870 if (ret < 0)
871 kfree(wm8988);
872 return ret;
5409fb4e
MB		 873}
874
f0fba2ad 875static __devexit int wm8988_i2c_remove(struct i2c_client *client)
5409fb4e 876{
f0fba2ad
LG		 877 snd_soc_unregister_codec(&client->dev);
878 kfree(i2c_get_clientdata(client));
5409fb4e
MB		 879 return 0;
880}
881
f0fba2ad
LG		 882static const struct i2c_device_id wm8988_i2c_id[] = {
883 { "wm8988", 0 },
884 { }
885};
886MODULE_DEVICE_TABLE(i2c, wm8988_i2c_id);
887
888static struct i2c_driver wm8988_i2c_driver = {
5409fb4e 889 .driver = {
f0fba2ad
LG		 890 .name = "wm8988-codec",
891 .owner = THIS_MODULE,
5409fb4e 892 },
f0fba2ad
LG		 893 .probe = wm8988_i2c_probe,
894 .remove = __devexit_p(wm8988_i2c_remove),
895 .id_table = wm8988_i2c_id,
5409fb4e
MB		 896};
897#endif
898
899static int __init wm8988_modinit(void)
900{
f0fba2ad 901 int ret = 0;
5409fb4e
MB		 902#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
903 ret = i2c_add_driver(&wm8988_i2c_driver);
f0fba2ad
LG		 904 if (ret != 0) {
905 printk(KERN_ERR "Failed to register WM8988 I2C driver: %d\n",
906 ret);
907 }
5409fb4e
MB		 908#endif
909#if defined(CONFIG_SPI_MASTER)
910 ret = spi_register_driver(&wm8988_spi_driver);
f0fba2ad
LG		 911 if (ret != 0) {
912 printk(KERN_ERR "Failed to register WM8988 SPI driver: %d\n",
913 ret);
914 }
5409fb4e
MB		 915#endif
916 return ret;
917}
918module_init(wm8988_modinit);
919
920static void __exit wm8988_exit(void)
921{
922#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
923 i2c_del_driver(&wm8988_i2c_driver);
924#endif
925#if defined(CONFIG_SPI_MASTER)
926 spi_unregister_driver(&wm8988_spi_driver);
927#endif
928}
929module_exit(wm8988_exit);
930
931
932MODULE_DESCRIPTION("ASoC WM8988 driver");
933MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
934MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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