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ASoC: wm8962: Replace direct snd_soc_codec dapm field access
[deliverable/linux.git] / sound / soc / codecs / wm8990.c
CommitLineData
f10485e7
MB		 1/*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
64ca0404 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
f10485e7
MB		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
0112b62b 20#include <linux/regmap.h>
5a0e3ad6 21#include <linux/slab.h>
f10485e7
MB		 22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
f10485e7
MB		 26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <asm/div64.h>
29
30#include "wm8990.h"
31
f10485e7
MB		 32/* codec private data */
33struct wm8990_priv {
0112b62b 34 struct regmap *regmap;
f10485e7
MB		 35 unsigned int sysclk;
36 unsigned int pcmclk;
37};
38
0112b62b 39static bool wm8990_volatile_register(struct device *dev, unsigned int reg)
416a0ce5
AL		 40{
41 switch (reg) {
42 case WM8990_RESET:
43 return 1;
44 default:
45 return 0;
46 }
47}
48
0112b62b
MB		 49static const struct reg_default wm8990_reg_defaults[] = {
50 { 1, 0x0000 }, /* R1 - Power Management (1) */
51 { 2, 0x6000 }, /* R2 - Power Management (2) */
52 { 3, 0x0000 }, /* R3 - Power Management (3) */
53 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
54 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
55 { 6, 0x01C8 }, /* R6 - Clocking (1) */
56 { 7, 0x0000 }, /* R7 - Clocking (2) */
57 { 8, 0x0040 }, /* R8 - Audio Interface (3) */
58 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
59 { 10, 0x0004 }, /* R10 - DAC CTRL */
60 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
61 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
62 { 13, 0x0000 }, /* R13 - Digital Side Tone */
63 { 14, 0x0100 }, /* R14 - ADC CTRL */
64 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
65 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
66
67 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
68 { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */
69 { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */
70 { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */
71 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
72 { 23, 0x0800 }, /* R23 - GPIO_POL */
73 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
74 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
75 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
76 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
77 { 28, 0x0000 }, /* R28 - Left Output Volume */
78 { 29, 0x0000 }, /* R29 - Right Output Volume */
79 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
80 { 31, 0x0022 }, /* R31 - Out3/4 Volume */
81 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
82 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
83 { 34, 0x0003 }, /* R34 - Speaker Volume */
84 { 35, 0x0003 }, /* R35 - ClassD1 */
85
86 { 37, 0x0100 }, /* R37 - ClassD3 */
87 { 38, 0x0079 }, /* R38 - ClassD4 */
88 { 39, 0x0000 }, /* R39 - Input Mixer1 */
89 { 40, 0x0000 }, /* R40 - Input Mixer2 */
90 { 41, 0x0000 }, /* R41 - Input Mixer3 */
91 { 42, 0x0000 }, /* R42 - Input Mixer4 */
92 { 43, 0x0000 }, /* R43 - Input Mixer5 */
93 { 44, 0x0000 }, /* R44 - Input Mixer6 */
94 { 45, 0x0000 }, /* R45 - Output Mixer1 */
95 { 46, 0x0000 }, /* R46 - Output Mixer2 */
96 { 47, 0x0000 }, /* R47 - Output Mixer3 */
97 { 48, 0x0000 }, /* R48 - Output Mixer4 */
98 { 49, 0x0000 }, /* R49 - Output Mixer5 */
99 { 50, 0x0000 }, /* R50 - Output Mixer6 */
100 { 51, 0x0180 }, /* R51 - Out3/4 Mixer */
101 { 52, 0x0000 }, /* R52 - Line Mixer1 */
102 { 53, 0x0000 }, /* R53 - Line Mixer2 */
103 { 54, 0x0000 }, /* R54 - Speaker Mixer */
104 { 55, 0x0000 }, /* R55 - Additional Control */
105 { 56, 0x0000 }, /* R56 - AntiPOP1 */
106 { 57, 0x0000 }, /* R57 - AntiPOP2 */
107 { 58, 0x0000 }, /* R58 - MICBIAS */
108
109 { 60, 0x0008 }, /* R60 - PLL1 */
110 { 61, 0x0031 }, /* R61 - PLL2 */
111 { 62, 0x0026 }, /* R62 - PLL3 */
f10485e7
MB		 112};
113
8d50e447 114#define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
f10485e7 115
021f80cc 116static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
f10485e7 117
021f80cc 118static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
f10485e7 119
021f80cc 120static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
f10485e7 121
021f80cc 122static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
f10485e7 123
021f80cc 124static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
f10485e7 125
021f80cc 126static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
f10485e7 127
021f80cc 128static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
f10485e7 129
021f80cc 130static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
f10485e7
MB		 131
132static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
133 struct snd_ctl_elem_value *ucontrol)
134{
ea53bf77 135 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
397d5aee
JN		 136 struct soc_mixer_control *mc =
137 (struct soc_mixer_control *)kcontrol->private_value;
138 int reg = mc->reg;
f10485e7
MB		 139 int ret;
140 u16 val;
141
142 ret = snd_soc_put_volsw(kcontrol, ucontrol);
143 if (ret < 0)
144 return ret;
145
146 /* now hit the volume update bits (always bit 8) */
8d50e447
MB		 147 val = snd_soc_read(codec, reg);
148 return snd_soc_write(codec, reg, val | 0x0100);
f10485e7
MB		 149}
150
151#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
fc99adc3
LPC		 152 tlv_array) \
153 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
154 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
f10485e7
MB		 155
156
157static const char *wm8990_digital_sidetone[] =
158 {"None", "Left ADC", "Right ADC", "Reserved"};
159
830b5011
TI		 160static SOC_ENUM_SINGLE_DECL(wm8990_left_digital_sidetone_enum,
161 WM8990_DIGITAL_SIDE_TONE,
162 WM8990_ADC_TO_DACL_SHIFT,
163 wm8990_digital_sidetone);
164
165static SOC_ENUM_SINGLE_DECL(wm8990_right_digital_sidetone_enum,
166 WM8990_DIGITAL_SIDE_TONE,
167 WM8990_ADC_TO_DACR_SHIFT,
168 wm8990_digital_sidetone);
f10485e7
MB		 169
170static const char *wm8990_adcmode[] =
171 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
172
830b5011
TI		 173static SOC_ENUM_SINGLE_DECL(wm8990_right_adcmode_enum,
174 WM8990_ADC_CTRL,
175 WM8990_ADC_HPF_CUT_SHIFT,
176 wm8990_adcmode);
f10485e7
MB		 177
178static const struct snd_kcontrol_new wm8990_snd_controls[] = {
179/* INMIXL */
180SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
181SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
182/* INMIXR */
183SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
184SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
185
186/* LOMIX */
187SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
188 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
189SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
190 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
191SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
192 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
193SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
194 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
195SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
196 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
197SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
198 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
199
200/* ROMIX */
201SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
202 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
203SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
204 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
205SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
206 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
207SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
208 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
209SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
210 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
211SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
212 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
213
214/* LOUT */
215SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
216 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
217SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
218
219/* ROUT */
220SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
221 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
222SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
223
224/* LOPGA */
225SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
226 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
227SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
228 WM8990_LOPGAZC_BIT, 1, 0),
229
230/* ROPGA */
231SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
232 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
233SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
234 WM8990_ROPGAZC_BIT, 1, 0),
235
236SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
237 WM8990_LONMUTE_BIT, 1, 0),
238SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
239 WM8990_LOPMUTE_BIT, 1, 0),
240SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
241 WM8990_LOATTN_BIT, 1, 0),
242SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
243 WM8990_RONMUTE_BIT, 1, 0),
244SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
245 WM8990_ROPMUTE_BIT, 1, 0),
246SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
247 WM8990_ROATTN_BIT, 1, 0),
248
249SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
250 WM8990_OUT3MUTE_BIT, 1, 0),
251SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
252 WM8990_OUT3ATTN_BIT, 1, 0),
253
254SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
255 WM8990_OUT4MUTE_BIT, 1, 0),
256SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
257 WM8990_OUT4ATTN_BIT, 1, 0),
258
259SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
260 WM8990_CDMODE_BIT, 1, 0),
261
262SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
97bb8129 263 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
f10485e7
MB		 264SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
265 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
266SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
267 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
97bb8129
MB		 268SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
269 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
270SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
271 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
f10485e7
MB		 272
273SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
274 WM8990_LEFT_DAC_DIGITAL_VOLUME,
275 WM8990_DACL_VOL_SHIFT,
276 WM8990_DACL_VOL_MASK,
277 0,
278 out_dac_tlv),
279
280SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
281 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
282 WM8990_DACR_VOL_SHIFT,
283 WM8990_DACR_VOL_MASK,
284 0,
285 out_dac_tlv),
286
287SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
288SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
289
290SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
291 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
292 out_sidetone_tlv),
293SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
294 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
295 out_sidetone_tlv),
296
297SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
298 WM8990_ADC_HPF_ENA_BIT, 1, 0),
299
300SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
301
302SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
303 WM8990_LEFT_ADC_DIGITAL_VOLUME,
304 WM8990_ADCL_VOL_SHIFT,
305 WM8990_ADCL_VOL_MASK,
306 0,
307 in_adc_tlv),
308
309SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
310 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
311 WM8990_ADCR_VOL_SHIFT,
312 WM8990_ADCR_VOL_MASK,
313 0,
314 in_adc_tlv),
315
316SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
317 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
318 WM8990_LIN12VOL_SHIFT,
319 WM8990_LIN12VOL_MASK,
320 0,
321 in_pga_tlv),
322
323SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
324 WM8990_LI12ZC_BIT, 1, 0),
325
326SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
327 WM8990_LI12MUTE_BIT, 1, 0),
328
329SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
330 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
331 WM8990_LIN34VOL_SHIFT,
332 WM8990_LIN34VOL_MASK,
333 0,
334 in_pga_tlv),
335
336SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
337 WM8990_LI34ZC_BIT, 1, 0),
338
339SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
340 WM8990_LI34MUTE_BIT, 1, 0),
341
342SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
343 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
344 WM8990_RIN12VOL_SHIFT,
345 WM8990_RIN12VOL_MASK,
346 0,
347 in_pga_tlv),
348
349SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
350 WM8990_RI12ZC_BIT, 1, 0),
351
352SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
353 WM8990_RI12MUTE_BIT, 1, 0),
354
355SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
356 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
357 WM8990_RIN34VOL_SHIFT,
358 WM8990_RIN34VOL_MASK,
359 0,
360 in_pga_tlv),
361
362SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
363 WM8990_RI34ZC_BIT, 1, 0),
364
365SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
366 WM8990_RI34MUTE_BIT, 1, 0),
367
368};
369
f10485e7
MB		 370/*
371 * _DAPM_ Controls
372 */
373
f10485e7
MB		 374static int outmixer_event(struct snd_soc_dapm_widget *w,
375 struct snd_kcontrol *kcontrol, int event)
376{
68ca2f68 377 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
f10485e7
MB		 378 u32 reg_shift = kcontrol->private_value & 0xfff;
379 int ret = 0;
380 u16 reg;
381
382 switch (reg_shift) {
383 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
68ca2f68 384 reg = snd_soc_read(codec, WM8990_OUTPUT_MIXER1);
f10485e7
MB		 385 if (reg & WM8990_LDLO) {
386 printk(KERN_WARNING
387 "Cannot set as Output Mixer 1 LDLO Set\n");
388 ret = -1;
389 }
390 break;
391 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
68ca2f68 392 reg = snd_soc_read(codec, WM8990_OUTPUT_MIXER2);
f10485e7
MB		 393 if (reg & WM8990_RDRO) {
394 printk(KERN_WARNING
395 "Cannot set as Output Mixer 2 RDRO Set\n");
396 ret = -1;
397 }
398 break;
399 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
68ca2f68 400 reg = snd_soc_read(codec, WM8990_SPEAKER_MIXER);
f10485e7
MB		 401 if (reg & WM8990_LDSPK) {
402 printk(KERN_WARNING
403 "Cannot set as Speaker Mixer LDSPK Set\n");
404 ret = -1;
405 }
406 break;
407 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
68ca2f68 408 reg = snd_soc_read(codec, WM8990_SPEAKER_MIXER);
f10485e7
MB		 409 if (reg & WM8990_RDSPK) {
410 printk(KERN_WARNING
411 "Cannot set as Speaker Mixer RDSPK Set\n");
412 ret = -1;
413 }
414 break;
415 }
416
417 return ret;
418}
419
420/* INMIX dB values */
421static const unsigned int in_mix_tlv[] = {
422 TLV_DB_RANGE_HEAD(1),
021f80cc 423 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
f10485e7
MB		 424};
425
426/* Left In PGA Connections */
427static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
428SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
429SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
430};
431
432static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
433SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
434SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
435};
436
437/* Right In PGA Connections */
438static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
439SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
440SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
441};
442
443static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
444SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
445SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
446};
447
448/* INMIXL */
449static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
450SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
451 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
452SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
453 7, 0, in_mix_tlv),
454SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
455 1, 0),
456SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
457 1, 0),
458};
459
460/* INMIXR */
461static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
462SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
463 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
464SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
465 7, 0, in_mix_tlv),
466SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
467 1, 0),
468SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
469 1, 0),
470};
471
472/* AINLMUX */
473static const char *wm8990_ainlmux[] =
474 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
475
830b5011
TI		 476static SOC_ENUM_SINGLE_DECL(wm8990_ainlmux_enum,
477 WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
478 wm8990_ainlmux);
f10485e7
MB		 479
480static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
481SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
482
483/* DIFFINL */
484
485/* AINRMUX */
486static const char *wm8990_ainrmux[] =
487 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
488
830b5011
TI		 489static SOC_ENUM_SINGLE_DECL(wm8990_ainrmux_enum,
490 WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
491 wm8990_ainrmux);
f10485e7
MB		 492
493static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
494SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
495
496/* RXVOICE */
497static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
498SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
499 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
500SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
501 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
502};
503
504/* LOMIX */
505static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
506SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
507 WM8990_LRBLO_BIT, 1, 0),
508SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
509 WM8990_LLBLO_BIT, 1, 0),
510SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
511 WM8990_LRI3LO_BIT, 1, 0),
512SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
513 WM8990_LLI3LO_BIT, 1, 0),
514SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
515 WM8990_LR12LO_BIT, 1, 0),
516SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
517 WM8990_LL12LO_BIT, 1, 0),
518SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
519 WM8990_LDLO_BIT, 1, 0),
520};
521
522/* ROMIX */
523static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
524SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
525 WM8990_RLBRO_BIT, 1, 0),
526SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
527 WM8990_RRBRO_BIT, 1, 0),
528SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
529 WM8990_RLI3RO_BIT, 1, 0),
530SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
531 WM8990_RRI3RO_BIT, 1, 0),
532SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
533 WM8990_RL12RO_BIT, 1, 0),
534SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
535 WM8990_RR12RO_BIT, 1, 0),
536SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
537 WM8990_RDRO_BIT, 1, 0),
538};
539
540/* LONMIX */
541static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
542SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
543 WM8990_LLOPGALON_BIT, 1, 0),
544SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
545 WM8990_LROPGALON_BIT, 1, 0),
546SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
547 WM8990_LOPLON_BIT, 1, 0),
548};
549
550/* LOPMIX */
551static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
552SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
553 WM8990_LR12LOP_BIT, 1, 0),
554SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
555 WM8990_LL12LOP_BIT, 1, 0),
556SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
557 WM8990_LLOPGALOP_BIT, 1, 0),
558};
559
560/* RONMIX */
561static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
562SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
563 WM8990_RROPGARON_BIT, 1, 0),
564SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
565 WM8990_RLOPGARON_BIT, 1, 0),
566SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
567 WM8990_ROPRON_BIT, 1, 0),
568};
569
570/* ROPMIX */
571static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
572SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
573 WM8990_RL12ROP_BIT, 1, 0),
574SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
575 WM8990_RR12ROP_BIT, 1, 0),
576SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
577 WM8990_RROPGAROP_BIT, 1, 0),
578};
579
580/* OUT3MIX */
581static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
582SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
583 WM8990_LI4O3_BIT, 1, 0),
584SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
585 WM8990_LPGAO3_BIT, 1, 0),
586};
587
588/* OUT4MIX */
589static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
590SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
591 WM8990_RPGAO4_BIT, 1, 0),
592SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
593 WM8990_RI4O4_BIT, 1, 0),
594};
595
596/* SPKMIX */
597static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
598SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
599 WM8990_LI2SPK_BIT, 1, 0),
600SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
601 WM8990_LB2SPK_BIT, 1, 0),
602SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
603 WM8990_LOPGASPK_BIT, 1, 0),
604SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
605 WM8990_LDSPK_BIT, 1, 0),
606SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
607 WM8990_RDSPK_BIT, 1, 0),
608SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
609 WM8990_ROPGASPK_BIT, 1, 0),
610SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
611 WM8990_RL12ROP_BIT, 1, 0),
612SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
613 WM8990_RI2SPK_BIT, 1, 0),
614};
615
616static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
617/* Input Side */
618/* Input Lines */
619SND_SOC_DAPM_INPUT("LIN1"),
620SND_SOC_DAPM_INPUT("LIN2"),
621SND_SOC_DAPM_INPUT("LIN3"),
622SND_SOC_DAPM_INPUT("LIN4/RXN"),
623SND_SOC_DAPM_INPUT("RIN3"),
624SND_SOC_DAPM_INPUT("RIN4/RXP"),
625SND_SOC_DAPM_INPUT("RIN1"),
626SND_SOC_DAPM_INPUT("RIN2"),
627SND_SOC_DAPM_INPUT("Internal ADC Source"),
628
d2fd5fe7
MB		 629SND_SOC_DAPM_SUPPLY("INL", WM8990_POWER_MANAGEMENT_2, WM8990_AINL_ENA_BIT, 0,
630 NULL, 0),
631SND_SOC_DAPM_SUPPLY("INR", WM8990_POWER_MANAGEMENT_2, WM8990_AINR_ENA_BIT, 0,
632 NULL, 0),
633
f10485e7
MB		 634/* DACs */
635SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
636 WM8990_ADCL_ENA_BIT, 0),
637SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
638 WM8990_ADCR_ENA_BIT, 0),
639
640/* Input PGAs */
641SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
642 0, &wm8990_dapm_lin12_pga_controls[0],
643 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
644SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
645 0, &wm8990_dapm_lin34_pga_controls[0],
646 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
647SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
648 0, &wm8990_dapm_rin12_pga_controls[0],
649 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
650SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
651 0, &wm8990_dapm_rin34_pga_controls[0],
652 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
653
654/* INMIXL */
d2fd5fe7 655SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
f10485e7 656 &wm8990_dapm_inmixl_controls[0],
d2fd5fe7 657 ARRAY_SIZE(wm8990_dapm_inmixl_controls)),
f10485e7
MB		 658
659/* AINLMUX */
d2fd5fe7 660SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainlmux_controls),
f10485e7
MB		 661
662/* INMIXR */
d2fd5fe7 663SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
f10485e7 664 &wm8990_dapm_inmixr_controls[0],
d2fd5fe7 665 ARRAY_SIZE(wm8990_dapm_inmixr_controls)),
f10485e7
MB		 666
667/* AINRMUX */
d2fd5fe7 668SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, &wm8990_dapm_ainrmux_controls),
f10485e7
MB		 669
670/* Output Side */
671/* DACs */
672SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
673 WM8990_DACL_ENA_BIT, 0),
674SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
675 WM8990_DACR_ENA_BIT, 0),
676
677/* LOMIX */
678SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
679 0, &wm8990_dapm_lomix_controls[0],
680 ARRAY_SIZE(wm8990_dapm_lomix_controls),
681 outmixer_event, SND_SOC_DAPM_PRE_REG),
682
683/* LONMIX */
684SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
685 &wm8990_dapm_lonmix_controls[0],
686 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
687
688/* LOPMIX */
689SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
690 &wm8990_dapm_lopmix_controls[0],
691 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
692
693/* OUT3MIX */
694SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
695 &wm8990_dapm_out3mix_controls[0],
696 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
697
698/* SPKMIX */
699SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
700 &wm8990_dapm_spkmix_controls[0],
701 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
702 SND_SOC_DAPM_PRE_REG),
703
704/* OUT4MIX */
705SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
706 &wm8990_dapm_out4mix_controls[0],
707 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
708
709/* ROPMIX */
710SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
711 &wm8990_dapm_ropmix_controls[0],
712 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
713
714/* RONMIX */
715SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
716 &wm8990_dapm_ronmix_controls[0],
717 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
718
719/* ROMIX */
720SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
721 0, &wm8990_dapm_romix_controls[0],
722 ARRAY_SIZE(wm8990_dapm_romix_controls),
723 outmixer_event, SND_SOC_DAPM_PRE_REG),
724
725/* LOUT PGA */
726SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
727 NULL, 0),
728
729/* ROUT PGA */
730SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
731 NULL, 0),
732
733/* LOPGA */
734SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
735 NULL, 0),
736
737/* ROPGA */
738SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
739 NULL, 0),
740
741/* MICBIAS */
e1fc3f21
MB		 742SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
743 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
f10485e7
MB		 744
745SND_SOC_DAPM_OUTPUT("LON"),
746SND_SOC_DAPM_OUTPUT("LOP"),
747SND_SOC_DAPM_OUTPUT("OUT3"),
748SND_SOC_DAPM_OUTPUT("LOUT"),
749SND_SOC_DAPM_OUTPUT("SPKN"),
750SND_SOC_DAPM_OUTPUT("SPKP"),
751SND_SOC_DAPM_OUTPUT("ROUT"),
752SND_SOC_DAPM_OUTPUT("OUT4"),
753SND_SOC_DAPM_OUTPUT("ROP"),
754SND_SOC_DAPM_OUTPUT("RON"),
755
756SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
757};
758
f6b415b6 759static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
f10485e7
MB		 760 /* Make DACs turn on when playing even if not mixed into any outputs */
761 {"Internal DAC Sink", NULL, "Left DAC"},
762 {"Internal DAC Sink", NULL, "Right DAC"},
763
764 /* Make ADCs turn on when recording even if not mixed from any inputs */
765 {"Left ADC", NULL, "Internal ADC Source"},
766 {"Right ADC", NULL, "Internal ADC Source"},
767
d2fd5fe7
MB		 768 {"AINLMUX", NULL, "INL"},
769 {"INMIXL", NULL, "INL"},
770 {"AINRMUX", NULL, "INR"},
771 {"INMIXR", NULL, "INR"},
772
f10485e7
MB		 773 /* Input Side */
774 /* LIN12 PGA */
775 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
776 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
777 /* LIN34 PGA */
778 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
97a775c4 779 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
f10485e7
MB		 780 /* INMIXL */
781 {"INMIXL", "Record Left Volume", "LOMIX"},
782 {"INMIXL", "LIN2 Volume", "LIN2"},
783 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
784 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
97a775c4
JP		 785 /* AINLMUX */
786 {"AINLMUX", "INMIXL Mix", "INMIXL"},
787 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
788 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
789 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
790 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
f10485e7 791 /* ADC */
97a775c4 792 {"Left ADC", NULL, "AINLMUX"},
f10485e7
MB		 793
794 /* RIN12 PGA */
795 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
796 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
797 /* RIN34 PGA */
798 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
97a775c4 799 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
f10485e7
MB		 800 /* INMIXL */
801 {"INMIXR", "Record Right Volume", "ROMIX"},
802 {"INMIXR", "RIN2 Volume", "RIN2"},
803 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
804 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
97a775c4
JP		 805 /* AINRMUX */
806 {"AINRMUX", "INMIXR Mix", "INMIXR"},
807 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
808 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
809 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
810 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
f10485e7 811 /* ADC */
97a775c4 812 {"Right ADC", NULL, "AINRMUX"},
f10485e7
MB		 813
814 /* LOMIX */
815 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
816 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
817 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
818 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
819 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
820 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
821 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
822
823 /* ROMIX */
824 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
825 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
826 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
827 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
828 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
829 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
830 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
831
832 /* SPKMIX */
833 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
834 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
835 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
836 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
837 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
838 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
839 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
436a7459 840 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
f10485e7
MB		 841
842 /* LONMIX */
843 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
844 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
845 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
846
847 /* LOPMIX */
848 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
849 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
850 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
851
852 /* OUT3MIX */
97a775c4 853 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
f10485e7
MB		 854 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
855
856 /* OUT4MIX */
857 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
858 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
859
860 /* RONMIX */
861 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
862 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
863 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
864
865 /* ROPMIX */
866 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
867 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
868 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
869
870 /* Out Mixer PGAs */
871 {"LOPGA", NULL, "LOMIX"},
872 {"ROPGA", NULL, "ROMIX"},
873
874 {"LOUT PGA", NULL, "LOMIX"},
875 {"ROUT PGA", NULL, "ROMIX"},
876
877 /* Output Pins */
878 {"LON", NULL, "LONMIX"},
879 {"LOP", NULL, "LOPMIX"},
97a775c4 880 {"OUT3", NULL, "OUT3MIX"},
f10485e7
MB		 881 {"LOUT", NULL, "LOUT PGA"},
882 {"SPKN", NULL, "SPKMIX"},
883 {"ROUT", NULL, "ROUT PGA"},
884 {"OUT4", NULL, "OUT4MIX"},
885 {"ROP", NULL, "ROPMIX"},
886 {"RON", NULL, "RONMIX"},
887};
888
f10485e7
MB		 889/* PLL divisors */
890struct _pll_div {
891 u32 div2;
892 u32 n;
893 u32 k;
894};
895
896/* The size in bits of the pll divide multiplied by 10
897 * to allow rounding later */
898#define FIXED_PLL_SIZE ((1 << 16) * 10)
899
900static void pll_factors(struct _pll_div *pll_div, unsigned int target,
901 unsigned int source)
902{
903 u64 Kpart;
904 unsigned int K, Ndiv, Nmod;
905
906
907 Ndiv = target / source;
908 if (Ndiv < 6) {
909 source >>= 1;
910 pll_div->div2 = 1;
911 Ndiv = target / source;
912 } else
913 pll_div->div2 = 0;
914
915 if ((Ndiv < 6) || (Ndiv > 12))
916 printk(KERN_WARNING
449bd54d 917 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
f10485e7
MB		 918
919 pll_div->n = Ndiv;
920 Nmod = target % source;
921 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
922
923 do_div(Kpart, source);
924
925 K = Kpart & 0xFFFFFFFF;
926
927 /* Check if we need to round */
928 if ((K % 10) >= 5)
929 K += 5;
930
931 /* Move down to proper range now rounding is done */
932 K /= 10;
933
934 pll_div->k = K;
935}
936
85488037
MB		 937static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
938 int source, unsigned int freq_in, unsigned int freq_out)
f10485e7 939{
f10485e7
MB		 940 struct snd_soc_codec *codec = codec_dai->codec;
941 struct _pll_div pll_div;
942
943 if (freq_in && freq_out) {
944 pll_factors(&pll_div, freq_out * 4, freq_in);
945
946 /* Turn on PLL */
79d07265
AL		 947 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
948 WM8990_PLL_ENA, WM8990_PLL_ENA);
f10485e7
MB		 949
950 /* sysclk comes from PLL */
79d07265
AL		 951 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
952 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
f10485e7 953
3ad2f3fb 954 /* set up N , fractional mode and pre-divisor if necessary */
8d50e447 955 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
f10485e7 956 (pll_div.div2?WM8990_PRESCALE:0));
8d50e447
MB		 957 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
958 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
f10485e7 959 } else {
79d07265
AL		 960 /* Turn off PLL */
961 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
962 WM8990_PLL_ENA, 0);
f10485e7
MB		 963 }
964 return 0;
965}
966
967/*
968 * Clock after PLL and dividers
969 */
e550e17f 970static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
f10485e7
MB		 971 int clk_id, unsigned int freq, int dir)
972{
973 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 974 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
f10485e7
MB		 975
976 wm8990->sysclk = freq;
977 return 0;
978}
979
980/*
981 * Set's ADC and Voice DAC format.
982 */
e550e17f 983static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
f10485e7
MB		 984 unsigned int fmt)
985{
986 struct snd_soc_codec *codec = codec_dai->codec;
987 u16 audio1, audio3;
988
8d50e447
MB		 989 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
990 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
f10485e7
MB		 991
992 /* set master/slave audio interface */
993 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
994 case SND_SOC_DAIFMT_CBS_CFS:
995 audio3 &= ~WM8990_AIF_MSTR1;
996 break;
997 case SND_SOC_DAIFMT_CBM_CFM:
998 audio3 |= WM8990_AIF_MSTR1;
999 break;
1000 default:
1001 return -EINVAL;
1002 }
1003
1004 audio1 &= ~WM8990_AIF_FMT_MASK;
1005
1006 /* interface format */
1007 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1008 case SND_SOC_DAIFMT_I2S:
1009 audio1 |= WM8990_AIF_TMF_I2S;
1010 audio1 &= ~WM8990_AIF_LRCLK_INV;
1011 break;
1012 case SND_SOC_DAIFMT_RIGHT_J:
1013 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1014 audio1 &= ~WM8990_AIF_LRCLK_INV;
1015 break;
1016 case SND_SOC_DAIFMT_LEFT_J:
1017 audio1 |= WM8990_AIF_TMF_LEFTJ;
1018 audio1 &= ~WM8990_AIF_LRCLK_INV;
1019 break;
1020 case SND_SOC_DAIFMT_DSP_A:
1021 audio1 |= WM8990_AIF_TMF_DSP;
1022 audio1 &= ~WM8990_AIF_LRCLK_INV;
1023 break;
1024 case SND_SOC_DAIFMT_DSP_B:
1025 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1026 break;
1027 default:
1028 return -EINVAL;
1029 }
1030
8d50e447
MB		 1031 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1032 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
f10485e7
MB		 1033 return 0;
1034}
1035
e550e17f 1036static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
f10485e7
MB		 1037 int div_id, int div)
1038{
1039 struct snd_soc_codec *codec = codec_dai->codec;
f10485e7
MB		 1040
1041 switch (div_id) {
1042 case WM8990_MCLK_DIV:
79d07265
AL		 1043 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1044 WM8990_MCLK_DIV_MASK, div);
f10485e7
MB		 1045 break;
1046 case WM8990_DACCLK_DIV:
79d07265
AL		 1047 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1048 WM8990_DAC_CLKDIV_MASK, div);
f10485e7
MB		 1049 break;
1050 case WM8990_ADCCLK_DIV:
79d07265
AL		 1051 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1052 WM8990_ADC_CLKDIV_MASK, div);
f10485e7
MB		 1053 break;
1054 case WM8990_BCLK_DIV:
79d07265
AL		 1055 snd_soc_update_bits(codec, WM8990_CLOCKING_1,
1056 WM8990_BCLK_DIV_MASK, div);
f10485e7
MB		 1057 break;
1058 default:
1059 return -EINVAL;
1060 }
1061
1062 return 0;
1063}
1064
1065/*
1066 * Set PCM DAI bit size and sample rate.
1067 */
1068static int wm8990_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1069 struct snd_pcm_hw_params *params,
1070 struct snd_soc_dai *dai)
f10485e7 1071{
e6968a17 1072 struct snd_soc_codec *codec = dai->codec;
8d50e447 1073 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
f10485e7
MB		 1074
1075 audio1 &= ~WM8990_AIF_WL_MASK;
1076 /* bit size */
a351901d
MB		 1077 switch (params_width(params)) {
1078 case 16:
f10485e7 1079 break;
a351901d 1080 case 20:
f10485e7
MB		 1081 audio1 |= WM8990_AIF_WL_20BITS;
1082 break;
a351901d 1083 case 24:
f10485e7
MB		 1084 audio1 |= WM8990_AIF_WL_24BITS;
1085 break;
a351901d 1086 case 32:
f10485e7
MB		 1087 audio1 |= WM8990_AIF_WL_32BITS;
1088 break;
1089 }
1090
8d50e447 1091 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
f10485e7
MB		 1092 return 0;
1093}
1094
e550e17f 1095static int wm8990_mute(struct snd_soc_dai *dai, int mute)
f10485e7
MB		 1096{
1097 struct snd_soc_codec *codec = dai->codec;
1098 u16 val;
1099
8d50e447 1100 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
f10485e7
MB		 1101
1102 if (mute)
8d50e447 1103 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
f10485e7 1104 else
8d50e447 1105 snd_soc_write(codec, WM8990_DAC_CTRL, val);
f10485e7
MB		 1106
1107 return 0;
1108}
1109
1110static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1111 enum snd_soc_bias_level level)
1112{
0112b62b 1113 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
416a0ce5 1114 int ret;
f10485e7
MB		 1115
1116 switch (level) {
1117 case SND_SOC_BIAS_ON:
1118 break;
2adb9833 1119
f10485e7 1120 case SND_SOC_BIAS_PREPARE:
2adb9833 1121 /* VMID=2*50k */
79d07265
AL		 1122 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1123 WM8990_VMID_MODE_MASK, 0x2);
f10485e7 1124 break;
2adb9833 1125
f10485e7 1126 case SND_SOC_BIAS_STANDBY:
ce6120cc 1127 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0112b62b 1128 ret = regcache_sync(wm8990->regmap);
416a0ce5
AL		 1129 if (ret < 0) {
1130 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1131 return ret;
1132 }
1133
f10485e7 1134 /* Enable all output discharge bits */
8d50e447 1135 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
f10485e7
MB		 1136 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1137 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1138 WM8990_DIS_ROUT);
1139
1140 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
8d50e447 1141 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1142 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1143 WM8990_VMIDTOG);
1144
1145 /* Delay to allow output caps to discharge */
7ebcf5d6 1146 msleep(300);
f10485e7
MB		 1147
1148 /* Disable VMIDTOG */
8d50e447 1149 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1150 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1151
1152 /* disable all output discharge bits */
8d50e447 1153 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
f10485e7
MB		 1154
1155 /* Enable outputs */
8d50e447 1156 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
f10485e7 1157
7ebcf5d6 1158 msleep(50);
f10485e7
MB		 1159
1160 /* Enable VMID at 2x50k */
8d50e447 1161 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
f10485e7 1162
7ebcf5d6 1163 msleep(100);
f10485e7
MB		 1164
1165 /* Enable VREF */
8d50e447 1166 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
f10485e7 1167
7ebcf5d6 1168 msleep(600);
f10485e7
MB		 1169
1170 /* Enable BUFIOEN */
8d50e447 1171 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1172 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1173 WM8990_BUFIOEN);
1174
1175 /* Disable outputs */
8d50e447 1176 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
f10485e7
MB		 1177
1178 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1179 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
f10485e7 1180
be1b87c7 1181 /* Enable workaround for ADC clocking issue. */
8d50e447
MB		 1182 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1183 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1184 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
f10485e7 1185 }
2adb9833
MB		 1186
1187 /* VMID=2*250k */
79d07265
AL		 1188 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1189 WM8990_VMID_MODE_MASK, 0x4);
f10485e7
MB		 1190 break;
1191
1192 case SND_SOC_BIAS_OFF:
1193 /* Enable POBCTRL and SOFT_ST */
8d50e447 1194 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1195 WM8990_POBCTRL | WM8990_BUFIOEN);
1196
1197 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1198 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1199 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1200 WM8990_BUFIOEN);
1201
1202 /* mute DAC */
79d07265
AL		 1203 snd_soc_update_bits(codec, WM8990_DAC_CTRL,
1204 WM8990_DAC_MUTE, WM8990_DAC_MUTE);
f10485e7
MB		 1205
1206 /* Enable any disabled outputs */
8d50e447 1207 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
f10485e7
MB		 1208
1209 /* Disable VMID */
8d50e447 1210 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
f10485e7 1211
7ebcf5d6 1212 msleep(300);
f10485e7
MB		 1213
1214 /* Enable all output discharge bits */
8d50e447 1215 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
f10485e7
MB		 1216 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1217 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1218 WM8990_DIS_ROUT);
1219
1220 /* Disable VREF */
8d50e447 1221 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
f10485e7
MB		 1222
1223 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1224 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
2ab2b742 1225
0112b62b 1226 regcache_mark_dirty(wm8990->regmap);
f10485e7
MB		 1227 break;
1228 }
1229
f10485e7
MB		 1230 return 0;
1231}
1232
1233#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1234 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1235 SNDRV_PCM_RATE_48000)
1236
1237#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1238 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1239
1240/*
1241 * The WM8990 supports 2 different and mutually exclusive DAI
1242 * configurations.
1243 *
1244 * 1. ADC/DAC on Primary Interface
1245 * 2. ADC on Primary Interface/DAC on secondary
1246 */
85e7652d 1247static const struct snd_soc_dai_ops wm8990_dai_ops = {
6335d055
EM		 1248 .hw_params = wm8990_hw_params,
1249 .digital_mute = wm8990_mute,
1250 .set_fmt = wm8990_set_dai_fmt,
1251 .set_clkdiv = wm8990_set_dai_clkdiv,
1252 .set_pll = wm8990_set_dai_pll,
1253 .set_sysclk = wm8990_set_dai_sysclk,
1254};
1255
f0fba2ad 1256static struct snd_soc_dai_driver wm8990_dai = {
f10485e7 1257/* ADC/DAC on primary */
f0fba2ad 1258 .name = "wm8990-hifi",
f10485e7
MB		 1259 .playback = {
1260 .stream_name = "Playback",
1261 .channels_min = 1,
1262 .channels_max = 2,
1263 .rates = WM8990_RATES,
1264 .formats = WM8990_FORMATS,},
1265 .capture = {
1266 .stream_name = "Capture",
1267 .channels_min = 1,
1268 .channels_max = 2,
1269 .rates = WM8990_RATES,
1270 .formats = WM8990_FORMATS,},
6335d055 1271 .ops = &wm8990_dai_ops,
f10485e7 1272};
f10485e7 1273
f10485e7
MB		 1274/*
1275 * initialise the WM8990 driver
1276 * register the mixer and dsp interfaces with the kernel
1277 */
f0fba2ad 1278static int wm8990_probe(struct snd_soc_codec *codec)
f10485e7 1279{
f10485e7
MB		 1280 wm8990_reset(codec);
1281
f10485e7 1282 /* charge output caps */
bd1204cb 1283 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
f10485e7 1284
79d07265
AL		 1285 snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4,
1286 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
f10485e7 1287
79d07265
AL		 1288 snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2,
1289 WM8990_GPIO1_SEL_MASK, 1);
f10485e7 1290
79d07265
AL		 1291 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1292 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
f10485e7 1293
8d50e447
MB		 1294 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1295 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
f10485e7 1296
f0fba2ad
LG		 1297 return 0;
1298}
f10485e7 1299
f0fba2ad
LG		 1300static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1301 .probe = wm8990_probe,
f0fba2ad 1302 .set_bias_level = wm8990_set_bias_level,
955efc8f
LPC		 1303 .suspend_bias_off = true,
1304
f6b415b6
MB		 1305 .controls = wm8990_snd_controls,
1306 .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1307 .dapm_widgets = wm8990_dapm_widgets,
1308 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1309 .dapm_routes = wm8990_dapm_routes,
1310 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
f0fba2ad 1311};
f10485e7 1312
0112b62b
MB		 1313static const struct regmap_config wm8990_regmap = {
1314 .reg_bits = 8,
1315 .val_bits = 16,
1316
1317 .max_register = WM8990_PLL3,
1318 .volatile_reg = wm8990_volatile_register,
1319 .reg_defaults = wm8990_reg_defaults,
1320 .num_reg_defaults = ARRAY_SIZE(wm8990_reg_defaults),
1321 .cache_type = REGCACHE_RBTREE,
1322};
1323
7a79e94e
BP		 1324static int wm8990_i2c_probe(struct i2c_client *i2c,
1325 const struct i2c_device_id *id)
f10485e7 1326{
f0fba2ad 1327 struct wm8990_priv *wm8990;
f10485e7
MB		 1328 int ret;
1329
587cbbb3
MB		 1330 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1331 GFP_KERNEL);
f0fba2ad
LG		 1332 if (wm8990 == NULL)
1333 return -ENOMEM;
f10485e7 1334
f0fba2ad 1335 i2c_set_clientdata(i2c, wm8990);
f10485e7 1336
f0fba2ad
LG		 1337 ret = snd_soc_register_codec(&i2c->dev,
1338 &soc_codec_dev_wm8990, &wm8990_dai, 1);
587cbbb3 1339
f10485e7
MB		 1340 return ret;
1341}
1342
7a79e94e 1343static int wm8990_i2c_remove(struct i2c_client *client)
f10485e7 1344{
f0fba2ad 1345 snd_soc_unregister_codec(&client->dev);
587cbbb3 1346
f10485e7
MB		 1347 return 0;
1348}
1349
e5d3fd38
JD		 1350static const struct i2c_device_id wm8990_i2c_id[] = {
1351 { "wm8990", 0 },
1352 { }
1353};
1354MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
f10485e7
MB		 1355
1356static struct i2c_driver wm8990_i2c_driver = {
1357 .driver = {
091edccf 1358 .name = "wm8990",
f10485e7
MB		 1359 .owner = THIS_MODULE,
1360 },
e5d3fd38 1361 .probe = wm8990_i2c_probe,
7a79e94e 1362 .remove = wm8990_i2c_remove,
e5d3fd38 1363 .id_table = wm8990_i2c_id,
f10485e7 1364};
f10485e7 1365
93818c9a 1366module_i2c_driver(wm8990_i2c_driver);
64089b84 1367
f10485e7
MB		 1368MODULE_DESCRIPTION("ASoC WM8990 driver");
1369MODULE_AUTHOR("Liam Girdwood");
1370MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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