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ASoC: Fix dB scales for WM8990
[deliverable/linux.git] / sound / soc / codecs / wm8990.c
CommitLineData
f10485e7
MB		 1/*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
64ca0404 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
f10485e7
MB		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <asm/div64.h>
29
30#include "wm8990.h"
31
f10485e7
MB		 32/* codec private data */
33struct wm8990_priv {
34 unsigned int sysclk;
35 unsigned int pcmclk;
36};
37
38/*
39 * wm8990 register cache. Note that register 0 is not included in the
40 * cache.
41 */
42static const u16 wm8990_reg[] = {
43 0x8990, /* R0 - Reset */
44 0x0000, /* R1 - Power Management (1) */
45 0x6000, /* R2 - Power Management (2) */
46 0x0000, /* R3 - Power Management (3) */
47 0x4050, /* R4 - Audio Interface (1) */
48 0x4000, /* R5 - Audio Interface (2) */
49 0x01C8, /* R6 - Clocking (1) */
50 0x0000, /* R7 - Clocking (2) */
51 0x0040, /* R8 - Audio Interface (3) */
52 0x0040, /* R9 - Audio Interface (4) */
53 0x0004, /* R10 - DAC CTRL */
54 0x00C0, /* R11 - Left DAC Digital Volume */
55 0x00C0, /* R12 - Right DAC Digital Volume */
56 0x0000, /* R13 - Digital Side Tone */
57 0x0100, /* R14 - ADC CTRL */
58 0x00C0, /* R15 - Left ADC Digital Volume */
59 0x00C0, /* R16 - Right ADC Digital Volume */
60 0x0000, /* R17 */
61 0x0000, /* R18 - GPIO CTRL 1 */
62 0x1000, /* R19 - GPIO1 & GPIO2 */
63 0x1010, /* R20 - GPIO3 & GPIO4 */
64 0x1010, /* R21 - GPIO5 & GPIO6 */
65 0x8000, /* R22 - GPIOCTRL 2 */
66 0x0800, /* R23 - GPIO_POL */
67 0x008B, /* R24 - Left Line Input 1&2 Volume */
68 0x008B, /* R25 - Left Line Input 3&4 Volume */
69 0x008B, /* R26 - Right Line Input 1&2 Volume */
70 0x008B, /* R27 - Right Line Input 3&4 Volume */
71 0x0000, /* R28 - Left Output Volume */
72 0x0000, /* R29 - Right Output Volume */
73 0x0066, /* R30 - Line Outputs Volume */
74 0x0022, /* R31 - Out3/4 Volume */
75 0x0079, /* R32 - Left OPGA Volume */
76 0x0079, /* R33 - Right OPGA Volume */
77 0x0003, /* R34 - Speaker Volume */
78 0x0003, /* R35 - ClassD1 */
79 0x0000, /* R36 */
80 0x0100, /* R37 - ClassD3 */
97bb8129 81 0x0079, /* R38 - ClassD4 */
f10485e7
MB		 82 0x0000, /* R39 - Input Mixer1 */
83 0x0000, /* R40 - Input Mixer2 */
84 0x0000, /* R41 - Input Mixer3 */
85 0x0000, /* R42 - Input Mixer4 */
86 0x0000, /* R43 - Input Mixer5 */
87 0x0000, /* R44 - Input Mixer6 */
88 0x0000, /* R45 - Output Mixer1 */
89 0x0000, /* R46 - Output Mixer2 */
90 0x0000, /* R47 - Output Mixer3 */
91 0x0000, /* R48 - Output Mixer4 */
92 0x0000, /* R49 - Output Mixer5 */
93 0x0000, /* R50 - Output Mixer6 */
94 0x0180, /* R51 - Out3/4 Mixer */
95 0x0000, /* R52 - Line Mixer1 */
96 0x0000, /* R53 - Line Mixer2 */
97 0x0000, /* R54 - Speaker Mixer */
98 0x0000, /* R55 - Additional Control */
99 0x0000, /* R56 - AntiPOP1 */
100 0x0000, /* R57 - AntiPOP2 */
101 0x0000, /* R58 - MICBIAS */
102 0x0000, /* R59 */
103 0x0008, /* R60 - PLL1 */
104 0x0031, /* R61 - PLL2 */
105 0x0026, /* R62 - PLL3 */
ba533e95 106 0x0000, /* R63 - Driver internal */
f10485e7
MB		 107};
108
8d50e447 109#define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
f10485e7 110
021f80cc 111static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
f10485e7 112
021f80cc 113static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
f10485e7 114
021f80cc 115static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
f10485e7 116
021f80cc 117static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
f10485e7 118
021f80cc 119static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
f10485e7 120
021f80cc 121static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
f10485e7 122
021f80cc 123static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
f10485e7 124
021f80cc 125static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
f10485e7
MB		 126
127static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
128 struct snd_ctl_elem_value *ucontrol)
129{
130 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
397d5aee
JN		 131 struct soc_mixer_control *mc =
132 (struct soc_mixer_control *)kcontrol->private_value;
133 int reg = mc->reg;
f10485e7
MB		 134 int ret;
135 u16 val;
136
137 ret = snd_soc_put_volsw(kcontrol, ucontrol);
138 if (ret < 0)
139 return ret;
140
141 /* now hit the volume update bits (always bit 8) */
8d50e447
MB		 142 val = snd_soc_read(codec, reg);
143 return snd_soc_write(codec, reg, val | 0x0100);
f10485e7
MB		 144}
145
146#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
147 tlv_array) {\
148 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
149 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
150 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
151 .tlv.p = (tlv_array), \
152 .info = snd_soc_info_volsw, \
153 .get = snd_soc_get_volsw, .put = wm899x_outpga_put_volsw_vu, \
154 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
155
156
157static const char *wm8990_digital_sidetone[] =
158 {"None", "Left ADC", "Right ADC", "Reserved"};
159
160static const struct soc_enum wm8990_left_digital_sidetone_enum =
161SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
162 WM8990_ADC_TO_DACL_SHIFT,
163 WM8990_ADC_TO_DACL_MASK,
164 wm8990_digital_sidetone);
165
166static const struct soc_enum wm8990_right_digital_sidetone_enum =
167SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
168 WM8990_ADC_TO_DACR_SHIFT,
169 WM8990_ADC_TO_DACR_MASK,
170 wm8990_digital_sidetone);
171
172static const char *wm8990_adcmode[] =
173 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
174
175static const struct soc_enum wm8990_right_adcmode_enum =
176SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
177 WM8990_ADC_HPF_CUT_SHIFT,
178 WM8990_ADC_HPF_CUT_MASK,
179 wm8990_adcmode);
180
181static const struct snd_kcontrol_new wm8990_snd_controls[] = {
182/* INMIXL */
183SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
184SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
185/* INMIXR */
186SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
187SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
188
189/* LOMIX */
190SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
191 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
192SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
193 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
194SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
195 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
196SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
197 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
198SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
199 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
200SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
201 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
202
203/* ROMIX */
204SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
205 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
206SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
207 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
208SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
209 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
210SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
211 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
212SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
213 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
214SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
215 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
216
217/* LOUT */
218SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
219 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
220SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
221
222/* ROUT */
223SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
224 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
225SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
226
227/* LOPGA */
228SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
229 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
230SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
231 WM8990_LOPGAZC_BIT, 1, 0),
232
233/* ROPGA */
234SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
235 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
236SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
237 WM8990_ROPGAZC_BIT, 1, 0),
238
239SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
240 WM8990_LONMUTE_BIT, 1, 0),
241SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
242 WM8990_LOPMUTE_BIT, 1, 0),
243SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
244 WM8990_LOATTN_BIT, 1, 0),
245SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
246 WM8990_RONMUTE_BIT, 1, 0),
247SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
248 WM8990_ROPMUTE_BIT, 1, 0),
249SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
250 WM8990_ROATTN_BIT, 1, 0),
251
252SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
253 WM8990_OUT3MUTE_BIT, 1, 0),
254SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
255 WM8990_OUT3ATTN_BIT, 1, 0),
256
257SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
258 WM8990_OUT4MUTE_BIT, 1, 0),
259SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
260 WM8990_OUT4ATTN_BIT, 1, 0),
261
262SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
263 WM8990_CDMODE_BIT, 1, 0),
264
265SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
97bb8129 266 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
f10485e7
MB		 267SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
268 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
269SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
270 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
97bb8129
MB		 271SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
272 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
273SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
274 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
f10485e7
MB		 275
276SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
277 WM8990_LEFT_DAC_DIGITAL_VOLUME,
278 WM8990_DACL_VOL_SHIFT,
279 WM8990_DACL_VOL_MASK,
280 0,
281 out_dac_tlv),
282
283SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
284 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
285 WM8990_DACR_VOL_SHIFT,
286 WM8990_DACR_VOL_MASK,
287 0,
288 out_dac_tlv),
289
290SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
291SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
292
293SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
294 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
295 out_sidetone_tlv),
296SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
297 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
298 out_sidetone_tlv),
299
300SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
301 WM8990_ADC_HPF_ENA_BIT, 1, 0),
302
303SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
304
305SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
306 WM8990_LEFT_ADC_DIGITAL_VOLUME,
307 WM8990_ADCL_VOL_SHIFT,
308 WM8990_ADCL_VOL_MASK,
309 0,
310 in_adc_tlv),
311
312SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
313 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
314 WM8990_ADCR_VOL_SHIFT,
315 WM8990_ADCR_VOL_MASK,
316 0,
317 in_adc_tlv),
318
319SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
320 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
321 WM8990_LIN12VOL_SHIFT,
322 WM8990_LIN12VOL_MASK,
323 0,
324 in_pga_tlv),
325
326SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
327 WM8990_LI12ZC_BIT, 1, 0),
328
329SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
330 WM8990_LI12MUTE_BIT, 1, 0),
331
332SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
333 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
334 WM8990_LIN34VOL_SHIFT,
335 WM8990_LIN34VOL_MASK,
336 0,
337 in_pga_tlv),
338
339SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
340 WM8990_LI34ZC_BIT, 1, 0),
341
342SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
343 WM8990_LI34MUTE_BIT, 1, 0),
344
345SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
346 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
347 WM8990_RIN12VOL_SHIFT,
348 WM8990_RIN12VOL_MASK,
349 0,
350 in_pga_tlv),
351
352SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
353 WM8990_RI12ZC_BIT, 1, 0),
354
355SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
356 WM8990_RI12MUTE_BIT, 1, 0),
357
358SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
359 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
360 WM8990_RIN34VOL_SHIFT,
361 WM8990_RIN34VOL_MASK,
362 0,
363 in_pga_tlv),
364
365SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
366 WM8990_RI34ZC_BIT, 1, 0),
367
368SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
369 WM8990_RI34MUTE_BIT, 1, 0),
370
371};
372
f10485e7
MB		 373/*
374 * _DAPM_ Controls
375 */
376
377static int inmixer_event(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event)
379{
380 u16 reg, fakepower;
381
8d50e447
MB		 382 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
383 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
f10485e7
MB		 384
385 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
386 (1 << WM8990_AINLMUX_PWR_BIT))) {
387 reg |= WM8990_AINL_ENA;
388 } else {
389 reg &= ~WM8990_AINL_ENA;
390 }
391
392 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
393 (1 << WM8990_AINRMUX_PWR_BIT))) {
394 reg |= WM8990_AINR_ENA;
395 } else {
396 reg &= ~WM8990_AINL_ENA;
397 }
8d50e447 398 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
f10485e7
MB		 399
400 return 0;
401}
402
403static int outmixer_event(struct snd_soc_dapm_widget *w,
404 struct snd_kcontrol *kcontrol, int event)
405{
406 u32 reg_shift = kcontrol->private_value & 0xfff;
407 int ret = 0;
408 u16 reg;
409
410 switch (reg_shift) {
411 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
8d50e447 412 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
f10485e7
MB		 413 if (reg & WM8990_LDLO) {
414 printk(KERN_WARNING
415 "Cannot set as Output Mixer 1 LDLO Set\n");
416 ret = -1;
417 }
418 break;
419 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
8d50e447 420 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
f10485e7
MB		 421 if (reg & WM8990_RDRO) {
422 printk(KERN_WARNING
423 "Cannot set as Output Mixer 2 RDRO Set\n");
424 ret = -1;
425 }
426 break;
427 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
8d50e447 428 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
f10485e7
MB		 429 if (reg & WM8990_LDSPK) {
430 printk(KERN_WARNING
431 "Cannot set as Speaker Mixer LDSPK Set\n");
432 ret = -1;
433 }
434 break;
435 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
8d50e447 436 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
f10485e7
MB		 437 if (reg & WM8990_RDSPK) {
438 printk(KERN_WARNING
439 "Cannot set as Speaker Mixer RDSPK Set\n");
440 ret = -1;
441 }
442 break;
443 }
444
445 return ret;
446}
447
448/* INMIX dB values */
449static const unsigned int in_mix_tlv[] = {
450 TLV_DB_RANGE_HEAD(1),
021f80cc 451 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
f10485e7
MB		 452};
453
454/* Left In PGA Connections */
455static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
456SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
457SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
458};
459
460static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
461SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
462SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
463};
464
465/* Right In PGA Connections */
466static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
467SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
468SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
469};
470
471static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
472SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
473SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
474};
475
476/* INMIXL */
477static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
478SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
479 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
480SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
481 7, 0, in_mix_tlv),
482SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
483 1, 0),
484SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
485 1, 0),
486};
487
488/* INMIXR */
489static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
490SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
491 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
492SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
493 7, 0, in_mix_tlv),
494SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
495 1, 0),
496SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
497 1, 0),
498};
499
500/* AINLMUX */
501static const char *wm8990_ainlmux[] =
502 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
503
504static const struct soc_enum wm8990_ainlmux_enum =
505SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
506 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
507
508static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
509SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
510
511/* DIFFINL */
512
513/* AINRMUX */
514static const char *wm8990_ainrmux[] =
515 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
516
517static const struct soc_enum wm8990_ainrmux_enum =
518SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
519 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
520
521static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
522SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
523
524/* RXVOICE */
525static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
526SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
527 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
528SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
529 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
530};
531
532/* LOMIX */
533static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
534SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
535 WM8990_LRBLO_BIT, 1, 0),
536SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
537 WM8990_LLBLO_BIT, 1, 0),
538SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
539 WM8990_LRI3LO_BIT, 1, 0),
540SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
541 WM8990_LLI3LO_BIT, 1, 0),
542SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
543 WM8990_LR12LO_BIT, 1, 0),
544SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
545 WM8990_LL12LO_BIT, 1, 0),
546SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
547 WM8990_LDLO_BIT, 1, 0),
548};
549
550/* ROMIX */
551static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
552SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
553 WM8990_RLBRO_BIT, 1, 0),
554SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
555 WM8990_RRBRO_BIT, 1, 0),
556SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
557 WM8990_RLI3RO_BIT, 1, 0),
558SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
559 WM8990_RRI3RO_BIT, 1, 0),
560SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
561 WM8990_RL12RO_BIT, 1, 0),
562SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
563 WM8990_RR12RO_BIT, 1, 0),
564SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
565 WM8990_RDRO_BIT, 1, 0),
566};
567
568/* LONMIX */
569static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
570SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
571 WM8990_LLOPGALON_BIT, 1, 0),
572SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
573 WM8990_LROPGALON_BIT, 1, 0),
574SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
575 WM8990_LOPLON_BIT, 1, 0),
576};
577
578/* LOPMIX */
579static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
580SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
581 WM8990_LR12LOP_BIT, 1, 0),
582SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
583 WM8990_LL12LOP_BIT, 1, 0),
584SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
585 WM8990_LLOPGALOP_BIT, 1, 0),
586};
587
588/* RONMIX */
589static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
590SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
591 WM8990_RROPGARON_BIT, 1, 0),
592SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
593 WM8990_RLOPGARON_BIT, 1, 0),
594SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
595 WM8990_ROPRON_BIT, 1, 0),
596};
597
598/* ROPMIX */
599static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
600SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
601 WM8990_RL12ROP_BIT, 1, 0),
602SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
603 WM8990_RR12ROP_BIT, 1, 0),
604SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
605 WM8990_RROPGAROP_BIT, 1, 0),
606};
607
608/* OUT3MIX */
609static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
610SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
611 WM8990_LI4O3_BIT, 1, 0),
612SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
613 WM8990_LPGAO3_BIT, 1, 0),
614};
615
616/* OUT4MIX */
617static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
618SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
619 WM8990_RPGAO4_BIT, 1, 0),
620SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
621 WM8990_RI4O4_BIT, 1, 0),
622};
623
624/* SPKMIX */
625static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
626SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
627 WM8990_LI2SPK_BIT, 1, 0),
628SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
629 WM8990_LB2SPK_BIT, 1, 0),
630SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
631 WM8990_LOPGASPK_BIT, 1, 0),
632SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
633 WM8990_LDSPK_BIT, 1, 0),
634SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
635 WM8990_RDSPK_BIT, 1, 0),
636SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
637 WM8990_ROPGASPK_BIT, 1, 0),
638SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
639 WM8990_RL12ROP_BIT, 1, 0),
640SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
641 WM8990_RI2SPK_BIT, 1, 0),
642};
643
644static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
645/* Input Side */
646/* Input Lines */
647SND_SOC_DAPM_INPUT("LIN1"),
648SND_SOC_DAPM_INPUT("LIN2"),
649SND_SOC_DAPM_INPUT("LIN3"),
650SND_SOC_DAPM_INPUT("LIN4/RXN"),
651SND_SOC_DAPM_INPUT("RIN3"),
652SND_SOC_DAPM_INPUT("RIN4/RXP"),
653SND_SOC_DAPM_INPUT("RIN1"),
654SND_SOC_DAPM_INPUT("RIN2"),
655SND_SOC_DAPM_INPUT("Internal ADC Source"),
656
657/* DACs */
658SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
659 WM8990_ADCL_ENA_BIT, 0),
660SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
661 WM8990_ADCR_ENA_BIT, 0),
662
663/* Input PGAs */
664SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
665 0, &wm8990_dapm_lin12_pga_controls[0],
666 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
667SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
668 0, &wm8990_dapm_lin34_pga_controls[0],
669 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
670SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
671 0, &wm8990_dapm_rin12_pga_controls[0],
672 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
673SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
674 0, &wm8990_dapm_rin34_pga_controls[0],
675 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
676
677/* INMIXL */
678SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
679 &wm8990_dapm_inmixl_controls[0],
680 ARRAY_SIZE(wm8990_dapm_inmixl_controls),
681 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
682
683/* AINLMUX */
97a775c4 684SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
f10485e7
MB		 685 &wm8990_dapm_ainlmux_controls, inmixer_event,
686 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
687
688/* INMIXR */
689SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
690 &wm8990_dapm_inmixr_controls[0],
691 ARRAY_SIZE(wm8990_dapm_inmixr_controls),
692 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
693
694/* AINRMUX */
97a775c4 695SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
f10485e7
MB		 696 &wm8990_dapm_ainrmux_controls, inmixer_event,
697 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
698
699/* Output Side */
700/* DACs */
701SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
702 WM8990_DACL_ENA_BIT, 0),
703SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
704 WM8990_DACR_ENA_BIT, 0),
705
706/* LOMIX */
707SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
708 0, &wm8990_dapm_lomix_controls[0],
709 ARRAY_SIZE(wm8990_dapm_lomix_controls),
710 outmixer_event, SND_SOC_DAPM_PRE_REG),
711
712/* LONMIX */
713SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
714 &wm8990_dapm_lonmix_controls[0],
715 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
716
717/* LOPMIX */
718SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
719 &wm8990_dapm_lopmix_controls[0],
720 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
721
722/* OUT3MIX */
723SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
724 &wm8990_dapm_out3mix_controls[0],
725 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
726
727/* SPKMIX */
728SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
729 &wm8990_dapm_spkmix_controls[0],
730 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
731 SND_SOC_DAPM_PRE_REG),
732
733/* OUT4MIX */
734SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
735 &wm8990_dapm_out4mix_controls[0],
736 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
737
738/* ROPMIX */
739SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
740 &wm8990_dapm_ropmix_controls[0],
741 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
742
743/* RONMIX */
744SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
745 &wm8990_dapm_ronmix_controls[0],
746 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
747
748/* ROMIX */
749SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
750 0, &wm8990_dapm_romix_controls[0],
751 ARRAY_SIZE(wm8990_dapm_romix_controls),
752 outmixer_event, SND_SOC_DAPM_PRE_REG),
753
754/* LOUT PGA */
755SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
756 NULL, 0),
757
758/* ROUT PGA */
759SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
760 NULL, 0),
761
762/* LOPGA */
763SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
764 NULL, 0),
765
766/* ROPGA */
767SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
768 NULL, 0),
769
770/* MICBIAS */
771SND_SOC_DAPM_MICBIAS("MICBIAS", WM8990_POWER_MANAGEMENT_1,
772 WM8990_MICBIAS_ENA_BIT, 0),
773
774SND_SOC_DAPM_OUTPUT("LON"),
775SND_SOC_DAPM_OUTPUT("LOP"),
776SND_SOC_DAPM_OUTPUT("OUT3"),
777SND_SOC_DAPM_OUTPUT("LOUT"),
778SND_SOC_DAPM_OUTPUT("SPKN"),
779SND_SOC_DAPM_OUTPUT("SPKP"),
780SND_SOC_DAPM_OUTPUT("ROUT"),
781SND_SOC_DAPM_OUTPUT("OUT4"),
782SND_SOC_DAPM_OUTPUT("ROP"),
783SND_SOC_DAPM_OUTPUT("RON"),
784
785SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
786};
787
788static const struct snd_soc_dapm_route audio_map[] = {
789 /* Make DACs turn on when playing even if not mixed into any outputs */
790 {"Internal DAC Sink", NULL, "Left DAC"},
791 {"Internal DAC Sink", NULL, "Right DAC"},
792
793 /* Make ADCs turn on when recording even if not mixed from any inputs */
794 {"Left ADC", NULL, "Internal ADC Source"},
795 {"Right ADC", NULL, "Internal ADC Source"},
796
797 /* Input Side */
798 /* LIN12 PGA */
799 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
800 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
801 /* LIN34 PGA */
802 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
97a775c4 803 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
f10485e7
MB		 804 /* INMIXL */
805 {"INMIXL", "Record Left Volume", "LOMIX"},
806 {"INMIXL", "LIN2 Volume", "LIN2"},
807 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
808 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
97a775c4
JP		 809 /* AINLMUX */
810 {"AINLMUX", "INMIXL Mix", "INMIXL"},
811 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
812 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
813 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
814 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
f10485e7 815 /* ADC */
97a775c4 816 {"Left ADC", NULL, "AINLMUX"},
f10485e7
MB		 817
818 /* RIN12 PGA */
819 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
820 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
821 /* RIN34 PGA */
822 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
97a775c4 823 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
f10485e7
MB		 824 /* INMIXL */
825 {"INMIXR", "Record Right Volume", "ROMIX"},
826 {"INMIXR", "RIN2 Volume", "RIN2"},
827 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
828 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
97a775c4
JP		 829 /* AINRMUX */
830 {"AINRMUX", "INMIXR Mix", "INMIXR"},
831 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
832 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
833 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
834 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
f10485e7 835 /* ADC */
97a775c4 836 {"Right ADC", NULL, "AINRMUX"},
f10485e7
MB		 837
838 /* LOMIX */
839 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
840 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
841 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
842 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
843 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
844 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
845 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
846
847 /* ROMIX */
848 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
849 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
850 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
851 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
852 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
853 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
854 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
855
856 /* SPKMIX */
857 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
858 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
859 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
860 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
861 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
862 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
863 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
436a7459 864 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
f10485e7
MB		 865
866 /* LONMIX */
867 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
868 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
869 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
870
871 /* LOPMIX */
872 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
873 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
874 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
875
876 /* OUT3MIX */
97a775c4 877 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
f10485e7
MB		 878 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
879
880 /* OUT4MIX */
881 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
882 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
883
884 /* RONMIX */
885 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
886 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
887 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
888
889 /* ROPMIX */
890 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
891 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
892 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
893
894 /* Out Mixer PGAs */
895 {"LOPGA", NULL, "LOMIX"},
896 {"ROPGA", NULL, "ROMIX"},
897
898 {"LOUT PGA", NULL, "LOMIX"},
899 {"ROUT PGA", NULL, "ROMIX"},
900
901 /* Output Pins */
902 {"LON", NULL, "LONMIX"},
903 {"LOP", NULL, "LOPMIX"},
97a775c4 904 {"OUT3", NULL, "OUT3MIX"},
f10485e7
MB		 905 {"LOUT", NULL, "LOUT PGA"},
906 {"SPKN", NULL, "SPKMIX"},
907 {"ROUT", NULL, "ROUT PGA"},
908 {"OUT4", NULL, "OUT4MIX"},
909 {"ROP", NULL, "ROPMIX"},
910 {"RON", NULL, "RONMIX"},
911};
912
913static int wm8990_add_widgets(struct snd_soc_codec *codec)
914{
915 snd_soc_dapm_new_controls(codec, wm8990_dapm_widgets,
916 ARRAY_SIZE(wm8990_dapm_widgets));
917
918 /* set up the WM8990 audio map */
919 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
920
f10485e7
MB		 921 return 0;
922}
923
924/* PLL divisors */
925struct _pll_div {
926 u32 div2;
927 u32 n;
928 u32 k;
929};
930
931/* The size in bits of the pll divide multiplied by 10
932 * to allow rounding later */
933#define FIXED_PLL_SIZE ((1 << 16) * 10)
934
935static void pll_factors(struct _pll_div *pll_div, unsigned int target,
936 unsigned int source)
937{
938 u64 Kpart;
939 unsigned int K, Ndiv, Nmod;
940
941
942 Ndiv = target / source;
943 if (Ndiv < 6) {
944 source >>= 1;
945 pll_div->div2 = 1;
946 Ndiv = target / source;
947 } else
948 pll_div->div2 = 0;
949
950 if ((Ndiv < 6) || (Ndiv > 12))
951 printk(KERN_WARNING
449bd54d 952 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
f10485e7
MB		 953
954 pll_div->n = Ndiv;
955 Nmod = target % source;
956 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
957
958 do_div(Kpart, source);
959
960 K = Kpart & 0xFFFFFFFF;
961
962 /* Check if we need to round */
963 if ((K % 10) >= 5)
964 K += 5;
965
966 /* Move down to proper range now rounding is done */
967 K /= 10;
968
969 pll_div->k = K;
970}
971
85488037
MB		 972static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
973 int source, unsigned int freq_in, unsigned int freq_out)
f10485e7
MB		 974{
975 u16 reg;
976 struct snd_soc_codec *codec = codec_dai->codec;
977 struct _pll_div pll_div;
978
979 if (freq_in && freq_out) {
980 pll_factors(&pll_div, freq_out * 4, freq_in);
981
982 /* Turn on PLL */
8d50e447 983 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
f10485e7 984 reg |= WM8990_PLL_ENA;
8d50e447 985 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
f10485e7
MB		 986
987 /* sysclk comes from PLL */
8d50e447
MB		 988 reg = snd_soc_read(codec, WM8990_CLOCKING_2);
989 snd_soc_write(codec, WM8990_CLOCKING_2, reg | WM8990_SYSCLK_SRC);
f10485e7 990
3ad2f3fb 991 /* set up N , fractional mode and pre-divisor if necessary */
8d50e447 992 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
f10485e7 993 (pll_div.div2?WM8990_PRESCALE:0));
8d50e447
MB		 994 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
995 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
f10485e7
MB		 996 } else {
997 /* Turn on PLL */
8d50e447 998 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
f10485e7 999 reg &= ~WM8990_PLL_ENA;
8d50e447 1000 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg);
f10485e7
MB		 1001 }
1002 return 0;
1003}
1004
1005/*
1006 * Clock after PLL and dividers
1007 */
e550e17f 1008static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
f10485e7
MB		 1009 int clk_id, unsigned int freq, int dir)
1010{
1011 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1012 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
f10485e7
MB		 1013
1014 wm8990->sysclk = freq;
1015 return 0;
1016}
1017
1018/*
1019 * Set's ADC and Voice DAC format.
1020 */
e550e17f 1021static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
f10485e7
MB		 1022 unsigned int fmt)
1023{
1024 struct snd_soc_codec *codec = codec_dai->codec;
1025 u16 audio1, audio3;
1026
8d50e447
MB		 1027 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1028 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
f10485e7
MB		 1029
1030 /* set master/slave audio interface */
1031 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1032 case SND_SOC_DAIFMT_CBS_CFS:
1033 audio3 &= ~WM8990_AIF_MSTR1;
1034 break;
1035 case SND_SOC_DAIFMT_CBM_CFM:
1036 audio3 |= WM8990_AIF_MSTR1;
1037 break;
1038 default:
1039 return -EINVAL;
1040 }
1041
1042 audio1 &= ~WM8990_AIF_FMT_MASK;
1043
1044 /* interface format */
1045 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1046 case SND_SOC_DAIFMT_I2S:
1047 audio1 |= WM8990_AIF_TMF_I2S;
1048 audio1 &= ~WM8990_AIF_LRCLK_INV;
1049 break;
1050 case SND_SOC_DAIFMT_RIGHT_J:
1051 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1052 audio1 &= ~WM8990_AIF_LRCLK_INV;
1053 break;
1054 case SND_SOC_DAIFMT_LEFT_J:
1055 audio1 |= WM8990_AIF_TMF_LEFTJ;
1056 audio1 &= ~WM8990_AIF_LRCLK_INV;
1057 break;
1058 case SND_SOC_DAIFMT_DSP_A:
1059 audio1 |= WM8990_AIF_TMF_DSP;
1060 audio1 &= ~WM8990_AIF_LRCLK_INV;
1061 break;
1062 case SND_SOC_DAIFMT_DSP_B:
1063 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1064 break;
1065 default:
1066 return -EINVAL;
1067 }
1068
8d50e447
MB		 1069 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1070 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
f10485e7
MB		 1071 return 0;
1072}
1073
e550e17f 1074static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
f10485e7
MB		 1075 int div_id, int div)
1076{
1077 struct snd_soc_codec *codec = codec_dai->codec;
1078 u16 reg;
1079
1080 switch (div_id) {
1081 case WM8990_MCLK_DIV:
8d50e447 1082 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
f10485e7 1083 ~WM8990_MCLK_DIV_MASK;
8d50e447 1084 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
f10485e7
MB		 1085 break;
1086 case WM8990_DACCLK_DIV:
8d50e447 1087 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
f10485e7 1088 ~WM8990_DAC_CLKDIV_MASK;
8d50e447 1089 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
f10485e7
MB		 1090 break;
1091 case WM8990_ADCCLK_DIV:
8d50e447 1092 reg = snd_soc_read(codec, WM8990_CLOCKING_2) &
f10485e7 1093 ~WM8990_ADC_CLKDIV_MASK;
8d50e447 1094 snd_soc_write(codec, WM8990_CLOCKING_2, reg | div);
f10485e7
MB		 1095 break;
1096 case WM8990_BCLK_DIV:
8d50e447 1097 reg = snd_soc_read(codec, WM8990_CLOCKING_1) &
f10485e7 1098 ~WM8990_BCLK_DIV_MASK;
8d50e447 1099 snd_soc_write(codec, WM8990_CLOCKING_1, reg | div);
f10485e7
MB		 1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104
1105 return 0;
1106}
1107
1108/*
1109 * Set PCM DAI bit size and sample rate.
1110 */
1111static int wm8990_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1112 struct snd_pcm_hw_params *params,
1113 struct snd_soc_dai *dai)
f10485e7
MB		 1114{
1115 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1116 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1117 struct snd_soc_codec *codec = socdev->card->codec;
8d50e447 1118 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
f10485e7
MB		 1119
1120 audio1 &= ~WM8990_AIF_WL_MASK;
1121 /* bit size */
1122 switch (params_format(params)) {
1123 case SNDRV_PCM_FORMAT_S16_LE:
1124 break;
1125 case SNDRV_PCM_FORMAT_S20_3LE:
1126 audio1 |= WM8990_AIF_WL_20BITS;
1127 break;
1128 case SNDRV_PCM_FORMAT_S24_LE:
1129 audio1 |= WM8990_AIF_WL_24BITS;
1130 break;
1131 case SNDRV_PCM_FORMAT_S32_LE:
1132 audio1 |= WM8990_AIF_WL_32BITS;
1133 break;
1134 }
1135
8d50e447 1136 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
f10485e7
MB		 1137 return 0;
1138}
1139
e550e17f 1140static int wm8990_mute(struct snd_soc_dai *dai, int mute)
f10485e7
MB		 1141{
1142 struct snd_soc_codec *codec = dai->codec;
1143 u16 val;
1144
8d50e447 1145 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
f10485e7
MB		 1146
1147 if (mute)
8d50e447 1148 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
f10485e7 1149 else
8d50e447 1150 snd_soc_write(codec, WM8990_DAC_CTRL, val);
f10485e7
MB		 1151
1152 return 0;
1153}
1154
1155static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1156 enum snd_soc_bias_level level)
1157{
1158 u16 val;
1159
1160 switch (level) {
1161 case SND_SOC_BIAS_ON:
1162 break;
2adb9833 1163
f10485e7 1164 case SND_SOC_BIAS_PREPARE:
2adb9833 1165 /* VMID=2*50k */
8d50e447 1166 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
2adb9833 1167 ~WM8990_VMID_MODE_MASK;
8d50e447 1168 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x2);
f10485e7 1169 break;
2adb9833 1170
f10485e7
MB		 1171 case SND_SOC_BIAS_STANDBY:
1172 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1173 /* Enable all output discharge bits */
8d50e447 1174 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
f10485e7
MB		 1175 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1176 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1177 WM8990_DIS_ROUT);
1178
1179 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
8d50e447 1180 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1181 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1182 WM8990_VMIDTOG);
1183
1184 /* Delay to allow output caps to discharge */
1185 msleep(msecs_to_jiffies(300));
1186
1187 /* Disable VMIDTOG */
8d50e447 1188 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1189 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1190
1191 /* disable all output discharge bits */
8d50e447 1192 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
f10485e7
MB		 1193
1194 /* Enable outputs */
8d50e447 1195 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
f10485e7
MB		 1196
1197 msleep(msecs_to_jiffies(50));
1198
1199 /* Enable VMID at 2x50k */
8d50e447 1200 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
f10485e7
MB		 1201
1202 msleep(msecs_to_jiffies(100));
1203
1204 /* Enable VREF */
8d50e447 1205 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
f10485e7
MB		 1206
1207 msleep(msecs_to_jiffies(600));
1208
1209 /* Enable BUFIOEN */
8d50e447 1210 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1211 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1212 WM8990_BUFIOEN);
1213
1214 /* Disable outputs */
8d50e447 1215 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
f10485e7
MB		 1216
1217 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1218 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
f10485e7 1219
be1b87c7 1220 /* Enable workaround for ADC clocking issue. */
8d50e447
MB		 1221 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1222 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1223 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
f10485e7 1224 }
2adb9833
MB		 1225
1226 /* VMID=2*250k */
8d50e447 1227 val = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_1) &
2adb9833 1228 ~WM8990_VMID_MODE_MASK;
8d50e447 1229 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, val | 0x4);
f10485e7
MB		 1230 break;
1231
1232 case SND_SOC_BIAS_OFF:
1233 /* Enable POBCTRL and SOFT_ST */
8d50e447 1234 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1235 WM8990_POBCTRL | WM8990_BUFIOEN);
1236
1237 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1238 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1239 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1240 WM8990_BUFIOEN);
1241
1242 /* mute DAC */
8d50e447
MB		 1243 val = snd_soc_read(codec, WM8990_DAC_CTRL);
1244 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
f10485e7
MB		 1245
1246 /* Enable any disabled outputs */
8d50e447 1247 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
f10485e7
MB		 1248
1249 /* Disable VMID */
8d50e447 1250 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
f10485e7
MB		 1251
1252 msleep(msecs_to_jiffies(300));
1253
1254 /* Enable all output discharge bits */
8d50e447 1255 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
f10485e7
MB		 1256 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1257 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1258 WM8990_DIS_ROUT);
1259
1260 /* Disable VREF */
8d50e447 1261 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
f10485e7
MB		 1262
1263 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1264 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
f10485e7
MB		 1265 break;
1266 }
1267
1268 codec->bias_level = level;
1269 return 0;
1270}
1271
1272#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1273 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1274 SNDRV_PCM_RATE_48000)
1275
1276#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1277 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1278
1279/*
1280 * The WM8990 supports 2 different and mutually exclusive DAI
1281 * configurations.
1282 *
1283 * 1. ADC/DAC on Primary Interface
1284 * 2. ADC on Primary Interface/DAC on secondary
1285 */
6335d055
EM		 1286static struct snd_soc_dai_ops wm8990_dai_ops = {
1287 .hw_params = wm8990_hw_params,
1288 .digital_mute = wm8990_mute,
1289 .set_fmt = wm8990_set_dai_fmt,
1290 .set_clkdiv = wm8990_set_dai_clkdiv,
1291 .set_pll = wm8990_set_dai_pll,
1292 .set_sysclk = wm8990_set_dai_sysclk,
1293};
1294
e550e17f 1295struct snd_soc_dai wm8990_dai = {
f10485e7
MB		 1296/* ADC/DAC on primary */
1297 .name = "WM8990 ADC/DAC Primary",
1298 .id = 1,
1299 .playback = {
1300 .stream_name = "Playback",
1301 .channels_min = 1,
1302 .channels_max = 2,
1303 .rates = WM8990_RATES,
1304 .formats = WM8990_FORMATS,},
1305 .capture = {
1306 .stream_name = "Capture",
1307 .channels_min = 1,
1308 .channels_max = 2,
1309 .rates = WM8990_RATES,
1310 .formats = WM8990_FORMATS,},
6335d055 1311 .ops = &wm8990_dai_ops,
f10485e7
MB		 1312};
1313EXPORT_SYMBOL_GPL(wm8990_dai);
1314
1315static int wm8990_suspend(struct platform_device *pdev, pm_message_t state)
1316{
1317 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1318 struct snd_soc_codec *codec = socdev->card->codec;
f10485e7 1319
f10485e7
MB		 1320 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1321 return 0;
1322}
1323
1324static int wm8990_resume(struct platform_device *pdev)
1325{
1326 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1327 struct snd_soc_codec *codec = socdev->card->codec;
f10485e7
MB		 1328 int i;
1329 u8 data[2];
1330 u16 *cache = codec->reg_cache;
1331
f10485e7
MB		 1332 /* Sync reg_cache with the hardware */
1333 for (i = 0; i < ARRAY_SIZE(wm8990_reg); i++) {
1334 if (i + 1 == WM8990_RESET)
1335 continue;
1336 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1337 data[1] = cache[i] & 0x00ff;
1338 codec->hw_write(codec->control_data, data, 2);
1339 }
1340
1341 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1342 return 0;
1343}
1344
1345/*
1346 * initialise the WM8990 driver
1347 * register the mixer and dsp interfaces with the kernel
1348 */
1349static int wm8990_init(struct snd_soc_device *socdev)
1350{
6627a653 1351 struct snd_soc_codec *codec = socdev->card->codec;
f10485e7
MB		 1352 u16 reg;
1353 int ret = 0;
1354
1355 codec->name = "WM8990";
1356 codec->owner = THIS_MODULE;
f10485e7
MB		 1357 codec->set_bias_level = wm8990_set_bias_level;
1358 codec->dai = &wm8990_dai;
1359 codec->num_dai = 2;
1360 codec->reg_cache_size = ARRAY_SIZE(wm8990_reg);
1361 codec->reg_cache = kmemdup(wm8990_reg, sizeof(wm8990_reg), GFP_KERNEL);
1362
1363 if (codec->reg_cache == NULL)
1364 return -ENOMEM;
1365
8d50e447
MB		 1366 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1367 if (ret < 0) {
1368 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
1369 goto pcm_err;
1370 }
1371
f10485e7
MB		 1372 wm8990_reset(codec);
1373
1374 /* register pcms */
1375 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1376 if (ret < 0) {
1377 printk(KERN_ERR "wm8990: failed to create pcms\n");
1378 goto pcm_err;
1379 }
1380
1381 /* charge output caps */
1382 codec->bias_level = SND_SOC_BIAS_OFF;
1383 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1384
8d50e447
MB		 1385 reg = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_4);
1386 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_4, reg | WM8990_ALRCGPIO1);
f10485e7 1387
8d50e447 1388 reg = snd_soc_read(codec, WM8990_GPIO1_GPIO2) &
f10485e7 1389 ~WM8990_GPIO1_SEL_MASK;
8d50e447 1390 snd_soc_write(codec, WM8990_GPIO1_GPIO2, reg | 1);
f10485e7 1391
8d50e447
MB		 1392 reg = snd_soc_read(codec, WM8990_POWER_MANAGEMENT_2);
1393 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_2, reg | WM8990_OPCLK_ENA);
f10485e7 1394
8d50e447
MB		 1395 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1396 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
f10485e7 1397
3e8e1952
IM		 1398 snd_soc_add_controls(codec, wm8990_snd_controls,
1399 ARRAY_SIZE(wm8990_snd_controls));
f10485e7 1400 wm8990_add_widgets(codec);
fe3e78e0 1401
f10485e7
MB		 1402 return ret;
1403
f10485e7
MB		 1404pcm_err:
1405 kfree(codec->reg_cache);
1406 return ret;
1407}
1408
1409/* If the i2c layer weren't so broken, we could pass this kind of data
1410 around */
1411static struct snd_soc_device *wm8990_socdev;
1412
1413#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1414
1415/*
1416 * WM891 2 wire address is determined by GPIO5
1417 * state during powerup.
1418 * low = 0x34
1419 * high = 0x36
1420 */
f10485e7 1421
e5d3fd38
JD		 1422static int wm8990_i2c_probe(struct i2c_client *i2c,
1423 const struct i2c_device_id *id)
f10485e7
MB		 1424{
1425 struct snd_soc_device *socdev = wm8990_socdev;
6627a653 1426 struct snd_soc_codec *codec = socdev->card->codec;
f10485e7
MB		 1427 int ret;
1428
f10485e7
MB		 1429 i2c_set_clientdata(i2c, codec);
1430 codec->control_data = i2c;
1431
f10485e7 1432 ret = wm8990_init(socdev);
e5d3fd38 1433 if (ret < 0)
a5c95e90 1434 pr_err("failed to initialise WM8990\n");
f10485e7 1435
f10485e7
MB		 1436 return ret;
1437}
1438
e5d3fd38 1439static int wm8990_i2c_remove(struct i2c_client *client)
f10485e7
MB		 1440{
1441 struct snd_soc_codec *codec = i2c_get_clientdata(client);
f10485e7 1442 kfree(codec->reg_cache);
f10485e7
MB		 1443 return 0;
1444}
1445
e5d3fd38
JD		 1446static const struct i2c_device_id wm8990_i2c_id[] = {
1447 { "wm8990", 0 },
1448 { }
1449};
1450MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
f10485e7
MB		 1451
1452static struct i2c_driver wm8990_i2c_driver = {
1453 .driver = {
1454 .name = "WM8990 I2C Codec",
1455 .owner = THIS_MODULE,
1456 },
e5d3fd38
JD		 1457 .probe = wm8990_i2c_probe,
1458 .remove = wm8990_i2c_remove,
1459 .id_table = wm8990_i2c_id,
f10485e7
MB		 1460};
1461
e5d3fd38
JD		 1462static int wm8990_add_i2c_device(struct platform_device *pdev,
1463 const struct wm8990_setup_data *setup)
1464{
1465 struct i2c_board_info info;
1466 struct i2c_adapter *adapter;
1467 struct i2c_client *client;
1468 int ret;
1469
1470 ret = i2c_add_driver(&wm8990_i2c_driver);
1471 if (ret != 0) {
1472 dev_err(&pdev->dev, "can't add i2c driver\n");
1473 return ret;
1474 }
1475
1476 memset(&info, 0, sizeof(struct i2c_board_info));
1477 info.addr = setup->i2c_address;
1478 strlcpy(info.type, "wm8990", I2C_NAME_SIZE);
1479
1480 adapter = i2c_get_adapter(setup->i2c_bus);
1481 if (!adapter) {
1482 dev_err(&pdev->dev, "can't get i2c adapter %d\n",
1483 setup->i2c_bus);
1484 goto err_driver;
1485 }
1486
1487 client = i2c_new_device(adapter, &info);
1488 i2c_put_adapter(adapter);
1489 if (!client) {
1490 dev_err(&pdev->dev, "can't add i2c device at 0x%x\n",
1491 (unsigned int)info.addr);
1492 goto err_driver;
1493 }
1494
1495 return 0;
1496
1497err_driver:
1498 i2c_del_driver(&wm8990_i2c_driver);
1499 return -ENODEV;
1500}
f10485e7
MB		 1501#endif
1502
1503static int wm8990_probe(struct platform_device *pdev)
1504{
1505 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1506 struct wm8990_setup_data *setup;
1507 struct snd_soc_codec *codec;
1508 struct wm8990_priv *wm8990;
b7c9d852 1509 int ret;
f10485e7 1510
f10485e7
MB		 1511 setup = socdev->codec_data;
1512 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1513 if (codec == NULL)
1514 return -ENOMEM;
1515
1516 wm8990 = kzalloc(sizeof(struct wm8990_priv), GFP_KERNEL);
1517 if (wm8990 == NULL) {
1518 kfree(codec);
1519 return -ENOMEM;
1520 }
1521
b2c812e2 1522 snd_soc_codec_set_drvdata(codec, wm8990);
6627a653 1523 socdev->card->codec = codec;
f10485e7
MB		 1524 mutex_init(&codec->mutex);
1525 INIT_LIST_HEAD(&codec->dapm_widgets);
1526 INIT_LIST_HEAD(&codec->dapm_paths);
1527 wm8990_socdev = socdev;
1528
b7c9d852
MB		 1529 ret = -ENODEV;
1530
f10485e7
MB		 1531#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1532 if (setup->i2c_address) {
f10485e7 1533 codec->hw_write = (hw_write_t)i2c_master_send;
e5d3fd38 1534 ret = wm8990_add_i2c_device(pdev, setup);
f10485e7 1535 }
f10485e7 1536#endif
3051e41a
JD		 1537
1538 if (ret != 0) {
b2c812e2 1539 kfree(snd_soc_codec_get_drvdata(codec));
3051e41a
JD		 1540 kfree(codec);
1541 }
f10485e7
MB		 1542 return ret;
1543}
1544
1545/* power down chip */
1546static int wm8990_remove(struct platform_device *pdev)
1547{
1548 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1549 struct snd_soc_codec *codec = socdev->card->codec;
f10485e7
MB		 1550
1551 if (codec->control_data)
1552 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1553 snd_soc_free_pcms(socdev);
1554 snd_soc_dapm_free(socdev);
1555#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
e5d3fd38 1556 i2c_unregister_device(codec->control_data);
f10485e7
MB		 1557 i2c_del_driver(&wm8990_i2c_driver);
1558#endif
b2c812e2 1559 kfree(snd_soc_codec_get_drvdata(codec));
f10485e7
MB		 1560 kfree(codec);
1561
1562 return 0;
1563}
1564
1565struct snd_soc_codec_device soc_codec_dev_wm8990 = {
1566 .probe = wm8990_probe,
1567 .remove = wm8990_remove,
1568 .suspend = wm8990_suspend,
1569 .resume = wm8990_resume,
1570};
1571EXPORT_SYMBOL_GPL(soc_codec_dev_wm8990);
1572
c9b3a40f 1573static int __init wm8990_modinit(void)
64089b84
MB		 1574{
1575 return snd_soc_register_dai(&wm8990_dai);
1576}
1577module_init(wm8990_modinit);
1578
1579static void __exit wm8990_exit(void)
1580{
1581 snd_soc_unregister_dai(&wm8990_dai);
1582}
1583module_exit(wm8990_exit);
1584
f10485e7
MB		 1585MODULE_DESCRIPTION("ASoC WM8990 driver");
1586MODULE_AUTHOR("Liam Girdwood");
1587MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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