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ASoC: wm8990: Convert to table based control and DAPM init
[deliverable/linux.git] / sound / soc / codecs / wm8990.c
CommitLineData
f10485e7
MB		 1/*
2 * wm8990.c -- WM8990 ALSA Soc Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics PLC.
64ca0404 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
f10485e7
MB		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
5a0e3ad6 20#include <linux/slab.h>
f10485e7
MB		 21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
f10485e7
MB		 25#include <sound/initval.h>
26#include <sound/tlv.h>
27#include <asm/div64.h>
28
29#include "wm8990.h"
30
f10485e7
MB		 31/* codec private data */
32struct wm8990_priv {
f0fba2ad 33 enum snd_soc_control_type control_type;
f10485e7
MB		 34 unsigned int sysclk;
35 unsigned int pcmclk;
36};
37
416a0ce5
AL		 38static int wm8990_volatile_register(struct snd_soc_codec *codec,
39 unsigned int reg)
40{
41 switch (reg) {
42 case WM8990_RESET:
43 return 1;
44 default:
45 return 0;
46 }
47}
48
f10485e7
MB		 49static const u16 wm8990_reg[] = {
50 0x8990, /* R0 - Reset */
51 0x0000, /* R1 - Power Management (1) */
52 0x6000, /* R2 - Power Management (2) */
53 0x0000, /* R3 - Power Management (3) */
54 0x4050, /* R4 - Audio Interface (1) */
55 0x4000, /* R5 - Audio Interface (2) */
56 0x01C8, /* R6 - Clocking (1) */
57 0x0000, /* R7 - Clocking (2) */
58 0x0040, /* R8 - Audio Interface (3) */
59 0x0040, /* R9 - Audio Interface (4) */
60 0x0004, /* R10 - DAC CTRL */
61 0x00C0, /* R11 - Left DAC Digital Volume */
62 0x00C0, /* R12 - Right DAC Digital Volume */
63 0x0000, /* R13 - Digital Side Tone */
64 0x0100, /* R14 - ADC CTRL */
65 0x00C0, /* R15 - Left ADC Digital Volume */
66 0x00C0, /* R16 - Right ADC Digital Volume */
67 0x0000, /* R17 */
68 0x0000, /* R18 - GPIO CTRL 1 */
69 0x1000, /* R19 - GPIO1 & GPIO2 */
70 0x1010, /* R20 - GPIO3 & GPIO4 */
71 0x1010, /* R21 - GPIO5 & GPIO6 */
72 0x8000, /* R22 - GPIOCTRL 2 */
73 0x0800, /* R23 - GPIO_POL */
74 0x008B, /* R24 - Left Line Input 1&2 Volume */
75 0x008B, /* R25 - Left Line Input 3&4 Volume */
76 0x008B, /* R26 - Right Line Input 1&2 Volume */
77 0x008B, /* R27 - Right Line Input 3&4 Volume */
78 0x0000, /* R28 - Left Output Volume */
79 0x0000, /* R29 - Right Output Volume */
80 0x0066, /* R30 - Line Outputs Volume */
81 0x0022, /* R31 - Out3/4 Volume */
82 0x0079, /* R32 - Left OPGA Volume */
83 0x0079, /* R33 - Right OPGA Volume */
84 0x0003, /* R34 - Speaker Volume */
85 0x0003, /* R35 - ClassD1 */
86 0x0000, /* R36 */
87 0x0100, /* R37 - ClassD3 */
97bb8129 88 0x0079, /* R38 - ClassD4 */
f10485e7
MB		 89 0x0000, /* R39 - Input Mixer1 */
90 0x0000, /* R40 - Input Mixer2 */
91 0x0000, /* R41 - Input Mixer3 */
92 0x0000, /* R42 - Input Mixer4 */
93 0x0000, /* R43 - Input Mixer5 */
94 0x0000, /* R44 - Input Mixer6 */
95 0x0000, /* R45 - Output Mixer1 */
96 0x0000, /* R46 - Output Mixer2 */
97 0x0000, /* R47 - Output Mixer3 */
98 0x0000, /* R48 - Output Mixer4 */
99 0x0000, /* R49 - Output Mixer5 */
100 0x0000, /* R50 - Output Mixer6 */
101 0x0180, /* R51 - Out3/4 Mixer */
102 0x0000, /* R52 - Line Mixer1 */
103 0x0000, /* R53 - Line Mixer2 */
104 0x0000, /* R54 - Speaker Mixer */
105 0x0000, /* R55 - Additional Control */
106 0x0000, /* R56 - AntiPOP1 */
107 0x0000, /* R57 - AntiPOP2 */
108 0x0000, /* R58 - MICBIAS */
109 0x0000, /* R59 */
110 0x0008, /* R60 - PLL1 */
111 0x0031, /* R61 - PLL2 */
112 0x0026, /* R62 - PLL3 */
ba533e95 113 0x0000, /* R63 - Driver internal */
f10485e7
MB		 114};
115
8d50e447 116#define wm8990_reset(c) snd_soc_write(c, WM8990_RESET, 0)
f10485e7 117
021f80cc 118static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
f10485e7 119
021f80cc 120static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
f10485e7 121
021f80cc 122static const DECLARE_TLV_DB_SCALE(out_mix_tlv, 0, -2100, 0);
f10485e7 123
021f80cc 124static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
f10485e7 125
021f80cc 126static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
f10485e7 127
021f80cc 128static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
f10485e7 129
021f80cc 130static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
f10485e7 131
021f80cc 132static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
f10485e7
MB		 133
134static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
135 struct snd_ctl_elem_value *ucontrol)
136{
137 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
397d5aee
JN		 138 struct soc_mixer_control *mc =
139 (struct soc_mixer_control *)kcontrol->private_value;
140 int reg = mc->reg;
f10485e7
MB		 141 int ret;
142 u16 val;
143
144 ret = snd_soc_put_volsw(kcontrol, ucontrol);
145 if (ret < 0)
146 return ret;
147
148 /* now hit the volume update bits (always bit 8) */
8d50e447
MB		 149 val = snd_soc_read(codec, reg);
150 return snd_soc_write(codec, reg, val | 0x0100);
f10485e7
MB		 151}
152
153#define SOC_WM899X_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert,\
fc99adc3
LPC		 154 tlv_array) \
155 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
156 snd_soc_get_volsw, wm899x_outpga_put_volsw_vu, tlv_array)
f10485e7
MB		 157
158
159static const char *wm8990_digital_sidetone[] =
160 {"None", "Left ADC", "Right ADC", "Reserved"};
161
162static const struct soc_enum wm8990_left_digital_sidetone_enum =
163SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
164 WM8990_ADC_TO_DACL_SHIFT,
165 WM8990_ADC_TO_DACL_MASK,
166 wm8990_digital_sidetone);
167
168static const struct soc_enum wm8990_right_digital_sidetone_enum =
169SOC_ENUM_SINGLE(WM8990_DIGITAL_SIDE_TONE,
170 WM8990_ADC_TO_DACR_SHIFT,
171 WM8990_ADC_TO_DACR_MASK,
172 wm8990_digital_sidetone);
173
174static const char *wm8990_adcmode[] =
175 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
176
177static const struct soc_enum wm8990_right_adcmode_enum =
178SOC_ENUM_SINGLE(WM8990_ADC_CTRL,
179 WM8990_ADC_HPF_CUT_SHIFT,
180 WM8990_ADC_HPF_CUT_MASK,
181 wm8990_adcmode);
182
183static const struct snd_kcontrol_new wm8990_snd_controls[] = {
184/* INMIXL */
185SOC_SINGLE("LIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L12MNBST_BIT, 1, 0),
186SOC_SINGLE("LIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_L34MNBST_BIT, 1, 0),
187/* INMIXR */
188SOC_SINGLE("RIN12 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R12MNBST_BIT, 1, 0),
189SOC_SINGLE("RIN34 PGA Boost", WM8990_INPUT_MIXER3, WM8990_R34MNBST_BIT, 1, 0),
190
191/* LOMIX */
192SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER3,
193 WM8990_LLI3LOVOL_SHIFT, WM8990_LLI3LOVOL_MASK, 1, out_mix_tlv),
194SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
195 WM8990_LR12LOVOL_SHIFT, WM8990_LR12LOVOL_MASK, 1, out_mix_tlv),
196SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER3,
197 WM8990_LL12LOVOL_SHIFT, WM8990_LL12LOVOL_MASK, 1, out_mix_tlv),
198SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER5,
199 WM8990_LRI3LOVOL_SHIFT, WM8990_LRI3LOVOL_MASK, 1, out_mix_tlv),
200SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
201 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
202SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER5,
203 WM8990_LRBLOVOL_SHIFT, WM8990_LRBLOVOL_MASK, 1, out_mix_tlv),
204
205/* ROMIX */
206SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8990_OUTPUT_MIXER4,
207 WM8990_RRI3ROVOL_SHIFT, WM8990_RRI3ROVOL_MASK, 1, out_mix_tlv),
208SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
209 WM8990_RL12ROVOL_SHIFT, WM8990_RL12ROVOL_MASK, 1, out_mix_tlv),
210SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8990_OUTPUT_MIXER4,
211 WM8990_RR12ROVOL_SHIFT, WM8990_RR12ROVOL_MASK, 1, out_mix_tlv),
212SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8990_OUTPUT_MIXER6,
213 WM8990_RLI3ROVOL_SHIFT, WM8990_RLI3ROVOL_MASK, 1, out_mix_tlv),
214SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
215 WM8990_RLBROVOL_SHIFT, WM8990_RLBROVOL_MASK, 1, out_mix_tlv),
216SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8990_OUTPUT_MIXER6,
217 WM8990_RRBROVOL_SHIFT, WM8990_RRBROVOL_MASK, 1, out_mix_tlv),
218
219/* LOUT */
220SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8990_LEFT_OUTPUT_VOLUME,
221 WM8990_LOUTVOL_SHIFT, WM8990_LOUTVOL_MASK, 0, out_pga_tlv),
222SOC_SINGLE("LOUT ZC", WM8990_LEFT_OUTPUT_VOLUME, WM8990_LOZC_BIT, 1, 0),
223
224/* ROUT */
225SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8990_RIGHT_OUTPUT_VOLUME,
226 WM8990_ROUTVOL_SHIFT, WM8990_ROUTVOL_MASK, 0, out_pga_tlv),
227SOC_SINGLE("ROUT ZC", WM8990_RIGHT_OUTPUT_VOLUME, WM8990_ROZC_BIT, 1, 0),
228
229/* LOPGA */
230SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8990_LEFT_OPGA_VOLUME,
231 WM8990_LOPGAVOL_SHIFT, WM8990_LOPGAVOL_MASK, 0, out_pga_tlv),
232SOC_SINGLE("LOPGA ZC Switch", WM8990_LEFT_OPGA_VOLUME,
233 WM8990_LOPGAZC_BIT, 1, 0),
234
235/* ROPGA */
236SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8990_RIGHT_OPGA_VOLUME,
237 WM8990_ROPGAVOL_SHIFT, WM8990_ROPGAVOL_MASK, 0, out_pga_tlv),
238SOC_SINGLE("ROPGA ZC Switch", WM8990_RIGHT_OPGA_VOLUME,
239 WM8990_ROPGAZC_BIT, 1, 0),
240
241SOC_SINGLE("LON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
242 WM8990_LONMUTE_BIT, 1, 0),
243SOC_SINGLE("LOP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
244 WM8990_LOPMUTE_BIT, 1, 0),
245SOC_SINGLE("LOP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
246 WM8990_LOATTN_BIT, 1, 0),
247SOC_SINGLE("RON Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
248 WM8990_RONMUTE_BIT, 1, 0),
249SOC_SINGLE("ROP Mute Switch", WM8990_LINE_OUTPUTS_VOLUME,
250 WM8990_ROPMUTE_BIT, 1, 0),
251SOC_SINGLE("ROP Attenuation Switch", WM8990_LINE_OUTPUTS_VOLUME,
252 WM8990_ROATTN_BIT, 1, 0),
253
254SOC_SINGLE("OUT3 Mute Switch", WM8990_OUT3_4_VOLUME,
255 WM8990_OUT3MUTE_BIT, 1, 0),
256SOC_SINGLE("OUT3 Attenuation Switch", WM8990_OUT3_4_VOLUME,
257 WM8990_OUT3ATTN_BIT, 1, 0),
258
259SOC_SINGLE("OUT4 Mute Switch", WM8990_OUT3_4_VOLUME,
260 WM8990_OUT4MUTE_BIT, 1, 0),
261SOC_SINGLE("OUT4 Attenuation Switch", WM8990_OUT3_4_VOLUME,
262 WM8990_OUT4ATTN_BIT, 1, 0),
263
264SOC_SINGLE("Speaker Mode Switch", WM8990_CLASSD1,
265 WM8990_CDMODE_BIT, 1, 0),
266
267SOC_SINGLE("Speaker Output Attenuation Volume", WM8990_SPEAKER_VOLUME,
97bb8129 268 WM8990_SPKATTN_SHIFT, WM8990_SPKATTN_MASK, 0),
f10485e7
MB		 269SOC_SINGLE("Speaker DC Boost Volume", WM8990_CLASSD3,
270 WM8990_DCGAIN_SHIFT, WM8990_DCGAIN_MASK, 0),
271SOC_SINGLE("Speaker AC Boost Volume", WM8990_CLASSD3,
272 WM8990_ACGAIN_SHIFT, WM8990_ACGAIN_MASK, 0),
97bb8129
MB		 273SOC_SINGLE_TLV("Speaker Volume", WM8990_CLASSD4,
274 WM8990_SPKVOL_SHIFT, WM8990_SPKVOL_MASK, 0, out_pga_tlv),
275SOC_SINGLE("Speaker ZC Switch", WM8990_CLASSD4,
276 WM8990_SPKZC_SHIFT, WM8990_SPKZC_MASK, 0),
f10485e7
MB		 277
278SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
279 WM8990_LEFT_DAC_DIGITAL_VOLUME,
280 WM8990_DACL_VOL_SHIFT,
281 WM8990_DACL_VOL_MASK,
282 0,
283 out_dac_tlv),
284
285SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
286 WM8990_RIGHT_DAC_DIGITAL_VOLUME,
287 WM8990_DACR_VOL_SHIFT,
288 WM8990_DACR_VOL_MASK,
289 0,
290 out_dac_tlv),
291
292SOC_ENUM("Left Digital Sidetone", wm8990_left_digital_sidetone_enum),
293SOC_ENUM("Right Digital Sidetone", wm8990_right_digital_sidetone_enum),
294
295SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
296 WM8990_ADCL_DAC_SVOL_SHIFT, WM8990_ADCL_DAC_SVOL_MASK, 0,
297 out_sidetone_tlv),
298SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8990_DIGITAL_SIDE_TONE,
299 WM8990_ADCR_DAC_SVOL_SHIFT, WM8990_ADCR_DAC_SVOL_MASK, 0,
300 out_sidetone_tlv),
301
302SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8990_ADC_CTRL,
303 WM8990_ADC_HPF_ENA_BIT, 1, 0),
304
305SOC_ENUM("ADC HPF Mode", wm8990_right_adcmode_enum),
306
307SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
308 WM8990_LEFT_ADC_DIGITAL_VOLUME,
309 WM8990_ADCL_VOL_SHIFT,
310 WM8990_ADCL_VOL_MASK,
311 0,
312 in_adc_tlv),
313
314SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
315 WM8990_RIGHT_ADC_DIGITAL_VOLUME,
316 WM8990_ADCR_VOL_SHIFT,
317 WM8990_ADCR_VOL_MASK,
318 0,
319 in_adc_tlv),
320
321SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
322 WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
323 WM8990_LIN12VOL_SHIFT,
324 WM8990_LIN12VOL_MASK,
325 0,
326 in_pga_tlv),
327
328SOC_SINGLE("LIN12 ZC Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
329 WM8990_LI12ZC_BIT, 1, 0),
330
331SOC_SINGLE("LIN12 Mute Switch", WM8990_LEFT_LINE_INPUT_1_2_VOLUME,
332 WM8990_LI12MUTE_BIT, 1, 0),
333
334SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
335 WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
336 WM8990_LIN34VOL_SHIFT,
337 WM8990_LIN34VOL_MASK,
338 0,
339 in_pga_tlv),
340
341SOC_SINGLE("LIN34 ZC Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
342 WM8990_LI34ZC_BIT, 1, 0),
343
344SOC_SINGLE("LIN34 Mute Switch", WM8990_LEFT_LINE_INPUT_3_4_VOLUME,
345 WM8990_LI34MUTE_BIT, 1, 0),
346
347SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
348 WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
349 WM8990_RIN12VOL_SHIFT,
350 WM8990_RIN12VOL_MASK,
351 0,
352 in_pga_tlv),
353
354SOC_SINGLE("RIN12 ZC Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
355 WM8990_RI12ZC_BIT, 1, 0),
356
357SOC_SINGLE("RIN12 Mute Switch", WM8990_RIGHT_LINE_INPUT_1_2_VOLUME,
358 WM8990_RI12MUTE_BIT, 1, 0),
359
360SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
361 WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
362 WM8990_RIN34VOL_SHIFT,
363 WM8990_RIN34VOL_MASK,
364 0,
365 in_pga_tlv),
366
367SOC_SINGLE("RIN34 ZC Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
368 WM8990_RI34ZC_BIT, 1, 0),
369
370SOC_SINGLE("RIN34 Mute Switch", WM8990_RIGHT_LINE_INPUT_3_4_VOLUME,
371 WM8990_RI34MUTE_BIT, 1, 0),
372
373};
374
f10485e7
MB		 375/*
376 * _DAPM_ Controls
377 */
378
379static int inmixer_event(struct snd_soc_dapm_widget *w,
380 struct snd_kcontrol *kcontrol, int event)
381{
382 u16 reg, fakepower;
383
8d50e447
MB		 384 reg = snd_soc_read(w->codec, WM8990_POWER_MANAGEMENT_2);
385 fakepower = snd_soc_read(w->codec, WM8990_INTDRIVBITS);
f10485e7
MB		 386
387 if (fakepower & ((1 << WM8990_INMIXL_PWR_BIT) |
388 (1 << WM8990_AINLMUX_PWR_BIT))) {
389 reg |= WM8990_AINL_ENA;
390 } else {
391 reg &= ~WM8990_AINL_ENA;
392 }
393
394 if (fakepower & ((1 << WM8990_INMIXR_PWR_BIT) |
395 (1 << WM8990_AINRMUX_PWR_BIT))) {
396 reg |= WM8990_AINR_ENA;
397 } else {
790f9325 398 reg &= ~WM8990_AINR_ENA;
f10485e7 399 }
8d50e447 400 snd_soc_write(w->codec, WM8990_POWER_MANAGEMENT_2, reg);
f10485e7
MB		 401
402 return 0;
403}
404
405static int outmixer_event(struct snd_soc_dapm_widget *w,
406 struct snd_kcontrol *kcontrol, int event)
407{
408 u32 reg_shift = kcontrol->private_value & 0xfff;
409 int ret = 0;
410 u16 reg;
411
412 switch (reg_shift) {
413 case WM8990_SPEAKER_MIXER | (WM8990_LDSPK_BIT << 8) :
8d50e447 414 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER1);
f10485e7
MB		 415 if (reg & WM8990_LDLO) {
416 printk(KERN_WARNING
417 "Cannot set as Output Mixer 1 LDLO Set\n");
418 ret = -1;
419 }
420 break;
421 case WM8990_SPEAKER_MIXER | (WM8990_RDSPK_BIT << 8):
8d50e447 422 reg = snd_soc_read(w->codec, WM8990_OUTPUT_MIXER2);
f10485e7
MB		 423 if (reg & WM8990_RDRO) {
424 printk(KERN_WARNING
425 "Cannot set as Output Mixer 2 RDRO Set\n");
426 ret = -1;
427 }
428 break;
429 case WM8990_OUTPUT_MIXER1 | (WM8990_LDLO_BIT << 8):
8d50e447 430 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
f10485e7
MB		 431 if (reg & WM8990_LDSPK) {
432 printk(KERN_WARNING
433 "Cannot set as Speaker Mixer LDSPK Set\n");
434 ret = -1;
435 }
436 break;
437 case WM8990_OUTPUT_MIXER2 | (WM8990_RDRO_BIT << 8):
8d50e447 438 reg = snd_soc_read(w->codec, WM8990_SPEAKER_MIXER);
f10485e7
MB		 439 if (reg & WM8990_RDSPK) {
440 printk(KERN_WARNING
441 "Cannot set as Speaker Mixer RDSPK Set\n");
442 ret = -1;
443 }
444 break;
445 }
446
447 return ret;
448}
449
450/* INMIX dB values */
451static const unsigned int in_mix_tlv[] = {
452 TLV_DB_RANGE_HEAD(1),
021f80cc 453 0, 7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
f10485e7
MB		 454};
455
456/* Left In PGA Connections */
457static const struct snd_kcontrol_new wm8990_dapm_lin12_pga_controls[] = {
458SOC_DAPM_SINGLE("LIN1 Switch", WM8990_INPUT_MIXER2, WM8990_LMN1_BIT, 1, 0),
459SOC_DAPM_SINGLE("LIN2 Switch", WM8990_INPUT_MIXER2, WM8990_LMP2_BIT, 1, 0),
460};
461
462static const struct snd_kcontrol_new wm8990_dapm_lin34_pga_controls[] = {
463SOC_DAPM_SINGLE("LIN3 Switch", WM8990_INPUT_MIXER2, WM8990_LMN3_BIT, 1, 0),
464SOC_DAPM_SINGLE("LIN4 Switch", WM8990_INPUT_MIXER2, WM8990_LMP4_BIT, 1, 0),
465};
466
467/* Right In PGA Connections */
468static const struct snd_kcontrol_new wm8990_dapm_rin12_pga_controls[] = {
469SOC_DAPM_SINGLE("RIN1 Switch", WM8990_INPUT_MIXER2, WM8990_RMN1_BIT, 1, 0),
470SOC_DAPM_SINGLE("RIN2 Switch", WM8990_INPUT_MIXER2, WM8990_RMP2_BIT, 1, 0),
471};
472
473static const struct snd_kcontrol_new wm8990_dapm_rin34_pga_controls[] = {
474SOC_DAPM_SINGLE("RIN3 Switch", WM8990_INPUT_MIXER2, WM8990_RMN3_BIT, 1, 0),
475SOC_DAPM_SINGLE("RIN4 Switch", WM8990_INPUT_MIXER2, WM8990_RMP4_BIT, 1, 0),
476};
477
478/* INMIXL */
479static const struct snd_kcontrol_new wm8990_dapm_inmixl_controls[] = {
480SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8990_INPUT_MIXER3,
481 WM8990_LDBVOL_SHIFT, WM8990_LDBVOL_MASK, 0, in_mix_tlv),
482SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8990_INPUT_MIXER5, WM8990_LI2BVOL_SHIFT,
483 7, 0, in_mix_tlv),
484SOC_DAPM_SINGLE("LINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
485 1, 0),
486SOC_DAPM_SINGLE("LINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
487 1, 0),
488};
489
490/* INMIXR */
491static const struct snd_kcontrol_new wm8990_dapm_inmixr_controls[] = {
492SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8990_INPUT_MIXER4,
493 WM8990_RDBVOL_SHIFT, WM8990_RDBVOL_MASK, 0, in_mix_tlv),
494SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8990_INPUT_MIXER6, WM8990_RI2BVOL_SHIFT,
495 7, 0, in_mix_tlv),
496SOC_DAPM_SINGLE("RINPGA12 Switch", WM8990_INPUT_MIXER3, WM8990_L12MNB_BIT,
497 1, 0),
498SOC_DAPM_SINGLE("RINPGA34 Switch", WM8990_INPUT_MIXER3, WM8990_L34MNB_BIT,
499 1, 0),
500};
501
502/* AINLMUX */
503static const char *wm8990_ainlmux[] =
504 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
505
506static const struct soc_enum wm8990_ainlmux_enum =
507SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINLMODE_SHIFT,
508 ARRAY_SIZE(wm8990_ainlmux), wm8990_ainlmux);
509
510static const struct snd_kcontrol_new wm8990_dapm_ainlmux_controls =
511SOC_DAPM_ENUM("Route", wm8990_ainlmux_enum);
512
513/* DIFFINL */
514
515/* AINRMUX */
516static const char *wm8990_ainrmux[] =
517 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
518
519static const struct soc_enum wm8990_ainrmux_enum =
520SOC_ENUM_SINGLE(WM8990_INPUT_MIXER1, WM8990_AINRMODE_SHIFT,
521 ARRAY_SIZE(wm8990_ainrmux), wm8990_ainrmux);
522
523static const struct snd_kcontrol_new wm8990_dapm_ainrmux_controls =
524SOC_DAPM_ENUM("Route", wm8990_ainrmux_enum);
525
526/* RXVOICE */
527static const struct snd_kcontrol_new wm8990_dapm_rxvoice_controls[] = {
528SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8990_INPUT_MIXER5, WM8990_LR4BVOL_SHIFT,
529 WM8990_LR4BVOL_MASK, 0, in_mix_tlv),
530SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8990_INPUT_MIXER6, WM8990_RL4BVOL_SHIFT,
531 WM8990_RL4BVOL_MASK, 0, in_mix_tlv),
532};
533
534/* LOMIX */
535static const struct snd_kcontrol_new wm8990_dapm_lomix_controls[] = {
536SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
537 WM8990_LRBLO_BIT, 1, 0),
538SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER1,
539 WM8990_LLBLO_BIT, 1, 0),
540SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
541 WM8990_LRI3LO_BIT, 1, 0),
542SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER1,
543 WM8990_LLI3LO_BIT, 1, 0),
544SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
545 WM8990_LR12LO_BIT, 1, 0),
546SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER1,
547 WM8990_LL12LO_BIT, 1, 0),
548SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8990_OUTPUT_MIXER1,
549 WM8990_LDLO_BIT, 1, 0),
550};
551
552/* ROMIX */
553static const struct snd_kcontrol_new wm8990_dapm_romix_controls[] = {
554SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
555 WM8990_RLBRO_BIT, 1, 0),
556SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8990_OUTPUT_MIXER2,
557 WM8990_RRBRO_BIT, 1, 0),
558SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
559 WM8990_RLI3RO_BIT, 1, 0),
560SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8990_OUTPUT_MIXER2,
561 WM8990_RRI3RO_BIT, 1, 0),
562SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
563 WM8990_RL12RO_BIT, 1, 0),
564SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8990_OUTPUT_MIXER2,
565 WM8990_RR12RO_BIT, 1, 0),
566SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8990_OUTPUT_MIXER2,
567 WM8990_RDRO_BIT, 1, 0),
568};
569
570/* LONMIX */
571static const struct snd_kcontrol_new wm8990_dapm_lonmix_controls[] = {
572SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
573 WM8990_LLOPGALON_BIT, 1, 0),
574SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER1,
575 WM8990_LROPGALON_BIT, 1, 0),
576SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8990_LINE_MIXER1,
577 WM8990_LOPLON_BIT, 1, 0),
578};
579
580/* LOPMIX */
581static const struct snd_kcontrol_new wm8990_dapm_lopmix_controls[] = {
582SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER1,
583 WM8990_LR12LOP_BIT, 1, 0),
584SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER1,
585 WM8990_LL12LOP_BIT, 1, 0),
586SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8990_LINE_MIXER1,
587 WM8990_LLOPGALOP_BIT, 1, 0),
588};
589
590/* RONMIX */
591static const struct snd_kcontrol_new wm8990_dapm_ronmix_controls[] = {
592SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
593 WM8990_RROPGARON_BIT, 1, 0),
594SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8990_LINE_MIXER2,
595 WM8990_RLOPGARON_BIT, 1, 0),
596SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8990_LINE_MIXER2,
597 WM8990_ROPRON_BIT, 1, 0),
598};
599
600/* ROPMIX */
601static const struct snd_kcontrol_new wm8990_dapm_ropmix_controls[] = {
602SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8990_LINE_MIXER2,
603 WM8990_RL12ROP_BIT, 1, 0),
604SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8990_LINE_MIXER2,
605 WM8990_RR12ROP_BIT, 1, 0),
606SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8990_LINE_MIXER2,
607 WM8990_RROPGAROP_BIT, 1, 0),
608};
609
610/* OUT3MIX */
611static const struct snd_kcontrol_new wm8990_dapm_out3mix_controls[] = {
612SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
613 WM8990_LI4O3_BIT, 1, 0),
614SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8990_OUT3_4_MIXER,
615 WM8990_LPGAO3_BIT, 1, 0),
616};
617
618/* OUT4MIX */
619static const struct snd_kcontrol_new wm8990_dapm_out4mix_controls[] = {
620SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8990_OUT3_4_MIXER,
621 WM8990_RPGAO4_BIT, 1, 0),
622SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8990_OUT3_4_MIXER,
623 WM8990_RI4O4_BIT, 1, 0),
624};
625
626/* SPKMIX */
627static const struct snd_kcontrol_new wm8990_dapm_spkmix_controls[] = {
628SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
629 WM8990_LI2SPK_BIT, 1, 0),
630SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8990_SPEAKER_MIXER,
631 WM8990_LB2SPK_BIT, 1, 0),
632SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8990_SPEAKER_MIXER,
633 WM8990_LOPGASPK_BIT, 1, 0),
634SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8990_SPEAKER_MIXER,
635 WM8990_LDSPK_BIT, 1, 0),
636SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8990_SPEAKER_MIXER,
637 WM8990_RDSPK_BIT, 1, 0),
638SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8990_SPEAKER_MIXER,
639 WM8990_ROPGASPK_BIT, 1, 0),
640SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8990_SPEAKER_MIXER,
641 WM8990_RL12ROP_BIT, 1, 0),
642SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8990_SPEAKER_MIXER,
643 WM8990_RI2SPK_BIT, 1, 0),
644};
645
646static const struct snd_soc_dapm_widget wm8990_dapm_widgets[] = {
647/* Input Side */
648/* Input Lines */
649SND_SOC_DAPM_INPUT("LIN1"),
650SND_SOC_DAPM_INPUT("LIN2"),
651SND_SOC_DAPM_INPUT("LIN3"),
652SND_SOC_DAPM_INPUT("LIN4/RXN"),
653SND_SOC_DAPM_INPUT("RIN3"),
654SND_SOC_DAPM_INPUT("RIN4/RXP"),
655SND_SOC_DAPM_INPUT("RIN1"),
656SND_SOC_DAPM_INPUT("RIN2"),
657SND_SOC_DAPM_INPUT("Internal ADC Source"),
658
659/* DACs */
660SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8990_POWER_MANAGEMENT_2,
661 WM8990_ADCL_ENA_BIT, 0),
662SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8990_POWER_MANAGEMENT_2,
663 WM8990_ADCR_ENA_BIT, 0),
664
665/* Input PGAs */
666SND_SOC_DAPM_MIXER("LIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN12_ENA_BIT,
667 0, &wm8990_dapm_lin12_pga_controls[0],
668 ARRAY_SIZE(wm8990_dapm_lin12_pga_controls)),
669SND_SOC_DAPM_MIXER("LIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_LIN34_ENA_BIT,
670 0, &wm8990_dapm_lin34_pga_controls[0],
671 ARRAY_SIZE(wm8990_dapm_lin34_pga_controls)),
672SND_SOC_DAPM_MIXER("RIN12 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN12_ENA_BIT,
673 0, &wm8990_dapm_rin12_pga_controls[0],
674 ARRAY_SIZE(wm8990_dapm_rin12_pga_controls)),
675SND_SOC_DAPM_MIXER("RIN34 PGA", WM8990_POWER_MANAGEMENT_2, WM8990_RIN34_ENA_BIT,
676 0, &wm8990_dapm_rin34_pga_controls[0],
677 ARRAY_SIZE(wm8990_dapm_rin34_pga_controls)),
678
679/* INMIXL */
680SND_SOC_DAPM_MIXER_E("INMIXL", WM8990_INTDRIVBITS, WM8990_INMIXL_PWR_BIT, 0,
681 &wm8990_dapm_inmixl_controls[0],
682 ARRAY_SIZE(wm8990_dapm_inmixl_controls),
683 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
684
685/* AINLMUX */
97a775c4 686SND_SOC_DAPM_MUX_E("AINLMUX", WM8990_INTDRIVBITS, WM8990_AINLMUX_PWR_BIT, 0,
f10485e7
MB		 687 &wm8990_dapm_ainlmux_controls, inmixer_event,
688 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
689
690/* INMIXR */
691SND_SOC_DAPM_MIXER_E("INMIXR", WM8990_INTDRIVBITS, WM8990_INMIXR_PWR_BIT, 0,
692 &wm8990_dapm_inmixr_controls[0],
693 ARRAY_SIZE(wm8990_dapm_inmixr_controls),
694 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
695
696/* AINRMUX */
97a775c4 697SND_SOC_DAPM_MUX_E("AINRMUX", WM8990_INTDRIVBITS, WM8990_AINRMUX_PWR_BIT, 0,
f10485e7
MB		 698 &wm8990_dapm_ainrmux_controls, inmixer_event,
699 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
700
701/* Output Side */
702/* DACs */
703SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8990_POWER_MANAGEMENT_3,
704 WM8990_DACL_ENA_BIT, 0),
705SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8990_POWER_MANAGEMENT_3,
706 WM8990_DACR_ENA_BIT, 0),
707
708/* LOMIX */
709SND_SOC_DAPM_MIXER_E("LOMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOMIX_ENA_BIT,
710 0, &wm8990_dapm_lomix_controls[0],
711 ARRAY_SIZE(wm8990_dapm_lomix_controls),
712 outmixer_event, SND_SOC_DAPM_PRE_REG),
713
714/* LONMIX */
715SND_SOC_DAPM_MIXER("LONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LON_ENA_BIT, 0,
716 &wm8990_dapm_lonmix_controls[0],
717 ARRAY_SIZE(wm8990_dapm_lonmix_controls)),
718
719/* LOPMIX */
720SND_SOC_DAPM_MIXER("LOPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_LOP_ENA_BIT, 0,
721 &wm8990_dapm_lopmix_controls[0],
722 ARRAY_SIZE(wm8990_dapm_lopmix_controls)),
723
724/* OUT3MIX */
725SND_SOC_DAPM_MIXER("OUT3MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT3_ENA_BIT, 0,
726 &wm8990_dapm_out3mix_controls[0],
727 ARRAY_SIZE(wm8990_dapm_out3mix_controls)),
728
729/* SPKMIX */
730SND_SOC_DAPM_MIXER_E("SPKMIX", WM8990_POWER_MANAGEMENT_1, WM8990_SPK_ENA_BIT, 0,
731 &wm8990_dapm_spkmix_controls[0],
732 ARRAY_SIZE(wm8990_dapm_spkmix_controls), outmixer_event,
733 SND_SOC_DAPM_PRE_REG),
734
735/* OUT4MIX */
736SND_SOC_DAPM_MIXER("OUT4MIX", WM8990_POWER_MANAGEMENT_1, WM8990_OUT4_ENA_BIT, 0,
737 &wm8990_dapm_out4mix_controls[0],
738 ARRAY_SIZE(wm8990_dapm_out4mix_controls)),
739
740/* ROPMIX */
741SND_SOC_DAPM_MIXER("ROPMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROP_ENA_BIT, 0,
742 &wm8990_dapm_ropmix_controls[0],
743 ARRAY_SIZE(wm8990_dapm_ropmix_controls)),
744
745/* RONMIX */
746SND_SOC_DAPM_MIXER("RONMIX", WM8990_POWER_MANAGEMENT_3, WM8990_RON_ENA_BIT, 0,
747 &wm8990_dapm_ronmix_controls[0],
748 ARRAY_SIZE(wm8990_dapm_ronmix_controls)),
749
750/* ROMIX */
751SND_SOC_DAPM_MIXER_E("ROMIX", WM8990_POWER_MANAGEMENT_3, WM8990_ROMIX_ENA_BIT,
752 0, &wm8990_dapm_romix_controls[0],
753 ARRAY_SIZE(wm8990_dapm_romix_controls),
754 outmixer_event, SND_SOC_DAPM_PRE_REG),
755
756/* LOUT PGA */
757SND_SOC_DAPM_PGA("LOUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_LOUT_ENA_BIT, 0,
758 NULL, 0),
759
760/* ROUT PGA */
761SND_SOC_DAPM_PGA("ROUT PGA", WM8990_POWER_MANAGEMENT_1, WM8990_ROUT_ENA_BIT, 0,
762 NULL, 0),
763
764/* LOPGA */
765SND_SOC_DAPM_PGA("LOPGA", WM8990_POWER_MANAGEMENT_3, WM8990_LOPGA_ENA_BIT, 0,
766 NULL, 0),
767
768/* ROPGA */
769SND_SOC_DAPM_PGA("ROPGA", WM8990_POWER_MANAGEMENT_3, WM8990_ROPGA_ENA_BIT, 0,
770 NULL, 0),
771
772/* MICBIAS */
e1fc3f21
MB		 773SND_SOC_DAPM_SUPPLY("MICBIAS", WM8990_POWER_MANAGEMENT_1,
774 WM8990_MICBIAS_ENA_BIT, 0, NULL, 0),
f10485e7
MB		 775
776SND_SOC_DAPM_OUTPUT("LON"),
777SND_SOC_DAPM_OUTPUT("LOP"),
778SND_SOC_DAPM_OUTPUT("OUT3"),
779SND_SOC_DAPM_OUTPUT("LOUT"),
780SND_SOC_DAPM_OUTPUT("SPKN"),
781SND_SOC_DAPM_OUTPUT("SPKP"),
782SND_SOC_DAPM_OUTPUT("ROUT"),
783SND_SOC_DAPM_OUTPUT("OUT4"),
784SND_SOC_DAPM_OUTPUT("ROP"),
785SND_SOC_DAPM_OUTPUT("RON"),
786
787SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
788};
789
f6b415b6 790static const struct snd_soc_dapm_route wm8990_dapm_routes[] = {
f10485e7
MB		 791 /* Make DACs turn on when playing even if not mixed into any outputs */
792 {"Internal DAC Sink", NULL, "Left DAC"},
793 {"Internal DAC Sink", NULL, "Right DAC"},
794
795 /* Make ADCs turn on when recording even if not mixed from any inputs */
796 {"Left ADC", NULL, "Internal ADC Source"},
797 {"Right ADC", NULL, "Internal ADC Source"},
798
799 /* Input Side */
800 /* LIN12 PGA */
801 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
802 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
803 /* LIN34 PGA */
804 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
97a775c4 805 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
f10485e7
MB		 806 /* INMIXL */
807 {"INMIXL", "Record Left Volume", "LOMIX"},
808 {"INMIXL", "LIN2 Volume", "LIN2"},
809 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
810 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
97a775c4
JP		 811 /* AINLMUX */
812 {"AINLMUX", "INMIXL Mix", "INMIXL"},
813 {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"},
814 {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"},
815 {"AINLMUX", "RXVOICE Mix", "LIN4/RXN"},
816 {"AINLMUX", "RXVOICE Mix", "RIN4/RXP"},
f10485e7 817 /* ADC */
97a775c4 818 {"Left ADC", NULL, "AINLMUX"},
f10485e7
MB		 819
820 /* RIN12 PGA */
821 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
822 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
823 /* RIN34 PGA */
824 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
97a775c4 825 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
f10485e7
MB		 826 /* INMIXL */
827 {"INMIXR", "Record Right Volume", "ROMIX"},
828 {"INMIXR", "RIN2 Volume", "RIN2"},
829 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
830 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
97a775c4
JP		 831 /* AINRMUX */
832 {"AINRMUX", "INMIXR Mix", "INMIXR"},
833 {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"},
834 {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"},
835 {"AINRMUX", "RXVOICE Mix", "LIN4/RXN"},
836 {"AINRMUX", "RXVOICE Mix", "RIN4/RXP"},
f10485e7 837 /* ADC */
97a775c4 838 {"Right ADC", NULL, "AINRMUX"},
f10485e7
MB		 839
840 /* LOMIX */
841 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
842 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
843 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
844 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
845 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"},
846 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"},
847 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
848
849 /* ROMIX */
850 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
851 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
852 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
853 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
854 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"},
855 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"},
856 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
857
858 /* SPKMIX */
859 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
860 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
861 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"},
862 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"},
863 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
864 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
865 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
436a7459 866 {"SPKMIX", "SPKMIX Left DAC Switch", "Left DAC"},
f10485e7
MB		 867
868 /* LONMIX */
869 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
870 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
871 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
872
873 /* LOPMIX */
874 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
875 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
876 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
877
878 /* OUT3MIX */
97a775c4 879 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
f10485e7
MB		 880 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
881
882 /* OUT4MIX */
883 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
884 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
885
886 /* RONMIX */
887 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
888 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
889 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
890
891 /* ROPMIX */
892 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
893 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
894 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
895
896 /* Out Mixer PGAs */
897 {"LOPGA", NULL, "LOMIX"},
898 {"ROPGA", NULL, "ROMIX"},
899
900 {"LOUT PGA", NULL, "LOMIX"},
901 {"ROUT PGA", NULL, "ROMIX"},
902
903 /* Output Pins */
904 {"LON", NULL, "LONMIX"},
905 {"LOP", NULL, "LOPMIX"},
97a775c4 906 {"OUT3", NULL, "OUT3MIX"},
f10485e7
MB		 907 {"LOUT", NULL, "LOUT PGA"},
908 {"SPKN", NULL, "SPKMIX"},
909 {"ROUT", NULL, "ROUT PGA"},
910 {"OUT4", NULL, "OUT4MIX"},
911 {"ROP", NULL, "ROPMIX"},
912 {"RON", NULL, "RONMIX"},
913};
914
f10485e7
MB		 915/* PLL divisors */
916struct _pll_div {
917 u32 div2;
918 u32 n;
919 u32 k;
920};
921
922/* The size in bits of the pll divide multiplied by 10
923 * to allow rounding later */
924#define FIXED_PLL_SIZE ((1 << 16) * 10)
925
926static void pll_factors(struct _pll_div *pll_div, unsigned int target,
927 unsigned int source)
928{
929 u64 Kpart;
930 unsigned int K, Ndiv, Nmod;
931
932
933 Ndiv = target / source;
934 if (Ndiv < 6) {
935 source >>= 1;
936 pll_div->div2 = 1;
937 Ndiv = target / source;
938 } else
939 pll_div->div2 = 0;
940
941 if ((Ndiv < 6) || (Ndiv > 12))
942 printk(KERN_WARNING
449bd54d 943 "WM8990 N value outwith recommended range! N = %u\n", Ndiv);
f10485e7
MB		 944
945 pll_div->n = Ndiv;
946 Nmod = target % source;
947 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
948
949 do_div(Kpart, source);
950
951 K = Kpart & 0xFFFFFFFF;
952
953 /* Check if we need to round */
954 if ((K % 10) >= 5)
955 K += 5;
956
957 /* Move down to proper range now rounding is done */
958 K /= 10;
959
960 pll_div->k = K;
961}
962
85488037
MB		 963static int wm8990_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
964 int source, unsigned int freq_in, unsigned int freq_out)
f10485e7 965{
f10485e7
MB		 966 struct snd_soc_codec *codec = codec_dai->codec;
967 struct _pll_div pll_div;
968
969 if (freq_in && freq_out) {
970 pll_factors(&pll_div, freq_out * 4, freq_in);
971
972 /* Turn on PLL */
79d07265
AL		 973 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
974 WM8990_PLL_ENA, WM8990_PLL_ENA);
f10485e7
MB		 975
976 /* sysclk comes from PLL */
79d07265
AL		 977 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
978 WM8990_SYSCLK_SRC, WM8990_SYSCLK_SRC);
f10485e7 979
3ad2f3fb 980 /* set up N , fractional mode and pre-divisor if necessary */
8d50e447 981 snd_soc_write(codec, WM8990_PLL1, pll_div.n | WM8990_SDM |
f10485e7 982 (pll_div.div2?WM8990_PRESCALE:0));
8d50e447
MB		 983 snd_soc_write(codec, WM8990_PLL2, (u8)(pll_div.k>>8));
984 snd_soc_write(codec, WM8990_PLL3, (u8)(pll_div.k & 0xFF));
f10485e7 985 } else {
79d07265
AL		 986 /* Turn off PLL */
987 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
988 WM8990_PLL_ENA, 0);
f10485e7
MB		 989 }
990 return 0;
991}
992
993/*
994 * Clock after PLL and dividers
995 */
e550e17f 996static int wm8990_set_dai_sysclk(struct snd_soc_dai *codec_dai,
f10485e7
MB		 997 int clk_id, unsigned int freq, int dir)
998{
999 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1000 struct wm8990_priv *wm8990 = snd_soc_codec_get_drvdata(codec);
f10485e7
MB		 1001
1002 wm8990->sysclk = freq;
1003 return 0;
1004}
1005
1006/*
1007 * Set's ADC and Voice DAC format.
1008 */
e550e17f 1009static int wm8990_set_dai_fmt(struct snd_soc_dai *codec_dai,
f10485e7
MB		 1010 unsigned int fmt)
1011{
1012 struct snd_soc_codec *codec = codec_dai->codec;
1013 u16 audio1, audio3;
1014
8d50e447
MB		 1015 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
1016 audio3 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_3);
f10485e7
MB		 1017
1018 /* set master/slave audio interface */
1019 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1020 case SND_SOC_DAIFMT_CBS_CFS:
1021 audio3 &= ~WM8990_AIF_MSTR1;
1022 break;
1023 case SND_SOC_DAIFMT_CBM_CFM:
1024 audio3 |= WM8990_AIF_MSTR1;
1025 break;
1026 default:
1027 return -EINVAL;
1028 }
1029
1030 audio1 &= ~WM8990_AIF_FMT_MASK;
1031
1032 /* interface format */
1033 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1034 case SND_SOC_DAIFMT_I2S:
1035 audio1 |= WM8990_AIF_TMF_I2S;
1036 audio1 &= ~WM8990_AIF_LRCLK_INV;
1037 break;
1038 case SND_SOC_DAIFMT_RIGHT_J:
1039 audio1 |= WM8990_AIF_TMF_RIGHTJ;
1040 audio1 &= ~WM8990_AIF_LRCLK_INV;
1041 break;
1042 case SND_SOC_DAIFMT_LEFT_J:
1043 audio1 |= WM8990_AIF_TMF_LEFTJ;
1044 audio1 &= ~WM8990_AIF_LRCLK_INV;
1045 break;
1046 case SND_SOC_DAIFMT_DSP_A:
1047 audio1 |= WM8990_AIF_TMF_DSP;
1048 audio1 &= ~WM8990_AIF_LRCLK_INV;
1049 break;
1050 case SND_SOC_DAIFMT_DSP_B:
1051 audio1 |= WM8990_AIF_TMF_DSP | WM8990_AIF_LRCLK_INV;
1052 break;
1053 default:
1054 return -EINVAL;
1055 }
1056
8d50e447
MB		 1057 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
1058 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_3, audio3);
f10485e7
MB		 1059 return 0;
1060}
1061
e550e17f 1062static int wm8990_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
f10485e7
MB		 1063 int div_id, int div)
1064{
1065 struct snd_soc_codec *codec = codec_dai->codec;
f10485e7
MB		 1066
1067 switch (div_id) {
1068 case WM8990_MCLK_DIV:
79d07265
AL		 1069 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1070 WM8990_MCLK_DIV_MASK, div);
f10485e7
MB		 1071 break;
1072 case WM8990_DACCLK_DIV:
79d07265
AL		 1073 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1074 WM8990_DAC_CLKDIV_MASK, div);
f10485e7
MB		 1075 break;
1076 case WM8990_ADCCLK_DIV:
79d07265
AL		 1077 snd_soc_update_bits(codec, WM8990_CLOCKING_2,
1078 WM8990_ADC_CLKDIV_MASK, div);
f10485e7
MB		 1079 break;
1080 case WM8990_BCLK_DIV:
79d07265
AL		 1081 snd_soc_update_bits(codec, WM8990_CLOCKING_1,
1082 WM8990_BCLK_DIV_MASK, div);
f10485e7
MB		 1083 break;
1084 default:
1085 return -EINVAL;
1086 }
1087
1088 return 0;
1089}
1090
1091/*
1092 * Set PCM DAI bit size and sample rate.
1093 */
1094static int wm8990_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1095 struct snd_pcm_hw_params *params,
1096 struct snd_soc_dai *dai)
f10485e7 1097{
e6968a17 1098 struct snd_soc_codec *codec = dai->codec;
8d50e447 1099 u16 audio1 = snd_soc_read(codec, WM8990_AUDIO_INTERFACE_1);
f10485e7
MB		 1100
1101 audio1 &= ~WM8990_AIF_WL_MASK;
1102 /* bit size */
1103 switch (params_format(params)) {
1104 case SNDRV_PCM_FORMAT_S16_LE:
1105 break;
1106 case SNDRV_PCM_FORMAT_S20_3LE:
1107 audio1 |= WM8990_AIF_WL_20BITS;
1108 break;
1109 case SNDRV_PCM_FORMAT_S24_LE:
1110 audio1 |= WM8990_AIF_WL_24BITS;
1111 break;
1112 case SNDRV_PCM_FORMAT_S32_LE:
1113 audio1 |= WM8990_AIF_WL_32BITS;
1114 break;
1115 }
1116
8d50e447 1117 snd_soc_write(codec, WM8990_AUDIO_INTERFACE_1, audio1);
f10485e7
MB		 1118 return 0;
1119}
1120
e550e17f 1121static int wm8990_mute(struct snd_soc_dai *dai, int mute)
f10485e7
MB		 1122{
1123 struct snd_soc_codec *codec = dai->codec;
1124 u16 val;
1125
8d50e447 1126 val = snd_soc_read(codec, WM8990_DAC_CTRL) & ~WM8990_DAC_MUTE;
f10485e7
MB		 1127
1128 if (mute)
8d50e447 1129 snd_soc_write(codec, WM8990_DAC_CTRL, val | WM8990_DAC_MUTE);
f10485e7 1130 else
8d50e447 1131 snd_soc_write(codec, WM8990_DAC_CTRL, val);
f10485e7
MB		 1132
1133 return 0;
1134}
1135
1136static int wm8990_set_bias_level(struct snd_soc_codec *codec,
1137 enum snd_soc_bias_level level)
1138{
416a0ce5 1139 int ret;
f10485e7
MB		 1140
1141 switch (level) {
1142 case SND_SOC_BIAS_ON:
1143 break;
2adb9833 1144
f10485e7 1145 case SND_SOC_BIAS_PREPARE:
2adb9833 1146 /* VMID=2*50k */
79d07265
AL		 1147 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1148 WM8990_VMID_MODE_MASK, 0x2);
f10485e7 1149 break;
2adb9833 1150
f10485e7 1151 case SND_SOC_BIAS_STANDBY:
ce6120cc 1152 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
416a0ce5
AL		 1153 ret = snd_soc_cache_sync(codec);
1154 if (ret < 0) {
1155 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
1156 return ret;
1157 }
1158
f10485e7 1159 /* Enable all output discharge bits */
8d50e447 1160 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
f10485e7
MB		 1161 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1162 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1163 WM8990_DIS_ROUT);
1164
1165 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
8d50e447 1166 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1167 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1168 WM8990_VMIDTOG);
1169
1170 /* Delay to allow output caps to discharge */
7ebcf5d6 1171 msleep(300);
f10485e7
MB		 1172
1173 /* Disable VMIDTOG */
8d50e447 1174 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1175 WM8990_BUFDCOPEN | WM8990_POBCTRL);
1176
1177 /* disable all output discharge bits */
8d50e447 1178 snd_soc_write(codec, WM8990_ANTIPOP1, 0);
f10485e7
MB		 1179
1180 /* Enable outputs */
8d50e447 1181 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1b00);
f10485e7 1182
7ebcf5d6 1183 msleep(50);
f10485e7
MB		 1184
1185 /* Enable VMID at 2x50k */
8d50e447 1186 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f02);
f10485e7 1187
7ebcf5d6 1188 msleep(100);
f10485e7
MB		 1189
1190 /* Enable VREF */
8d50e447 1191 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
f10485e7 1192
7ebcf5d6 1193 msleep(600);
f10485e7
MB		 1194
1195 /* Enable BUFIOEN */
8d50e447 1196 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1197 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1198 WM8990_BUFIOEN);
1199
1200 /* Disable outputs */
8d50e447 1201 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x3);
f10485e7
MB		 1202
1203 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1204 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_BUFIOEN);
f10485e7 1205
be1b87c7 1206 /* Enable workaround for ADC clocking issue. */
8d50e447
MB		 1207 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0x2);
1208 snd_soc_write(codec, WM8990_EXT_CTL1, 0xa003);
1209 snd_soc_write(codec, WM8990_EXT_ACCESS_ENA, 0);
f10485e7 1210 }
2adb9833
MB		 1211
1212 /* VMID=2*250k */
79d07265
AL		 1213 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_1,
1214 WM8990_VMID_MODE_MASK, 0x4);
f10485e7
MB		 1215 break;
1216
1217 case SND_SOC_BIAS_OFF:
1218 /* Enable POBCTRL and SOFT_ST */
8d50e447 1219 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1220 WM8990_POBCTRL | WM8990_BUFIOEN);
1221
1222 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1223 snd_soc_write(codec, WM8990_ANTIPOP2, WM8990_SOFTST |
f10485e7
MB		 1224 WM8990_BUFDCOPEN | WM8990_POBCTRL |
1225 WM8990_BUFIOEN);
1226
1227 /* mute DAC */
79d07265
AL		 1228 snd_soc_update_bits(codec, WM8990_DAC_CTRL,
1229 WM8990_DAC_MUTE, WM8990_DAC_MUTE);
f10485e7
MB		 1230
1231 /* Enable any disabled outputs */
8d50e447 1232 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f03);
f10485e7
MB		 1233
1234 /* Disable VMID */
8d50e447 1235 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x1f01);
f10485e7 1236
7ebcf5d6 1237 msleep(300);
f10485e7
MB		 1238
1239 /* Enable all output discharge bits */
8d50e447 1240 snd_soc_write(codec, WM8990_ANTIPOP1, WM8990_DIS_LLINE |
f10485e7
MB		 1241 WM8990_DIS_RLINE | WM8990_DIS_OUT3 |
1242 WM8990_DIS_OUT4 | WM8990_DIS_LOUT |
1243 WM8990_DIS_ROUT);
1244
1245 /* Disable VREF */
8d50e447 1246 snd_soc_write(codec, WM8990_POWER_MANAGEMENT_1, 0x0);
f10485e7
MB		 1247
1248 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
8d50e447 1249 snd_soc_write(codec, WM8990_ANTIPOP2, 0x0);
2ab2b742
MB		 1250
1251 codec->cache_sync = 1;
f10485e7
MB		 1252 break;
1253 }
1254
ce6120cc 1255 codec->dapm.bias_level = level;
f10485e7
MB		 1256 return 0;
1257}
1258
1259#define WM8990_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1260 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
1261 SNDRV_PCM_RATE_48000)
1262
1263#define WM8990_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1264 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1265
1266/*
1267 * The WM8990 supports 2 different and mutually exclusive DAI
1268 * configurations.
1269 *
1270 * 1. ADC/DAC on Primary Interface
1271 * 2. ADC on Primary Interface/DAC on secondary
1272 */
85e7652d 1273static const struct snd_soc_dai_ops wm8990_dai_ops = {
6335d055
EM		 1274 .hw_params = wm8990_hw_params,
1275 .digital_mute = wm8990_mute,
1276 .set_fmt = wm8990_set_dai_fmt,
1277 .set_clkdiv = wm8990_set_dai_clkdiv,
1278 .set_pll = wm8990_set_dai_pll,
1279 .set_sysclk = wm8990_set_dai_sysclk,
1280};
1281
f0fba2ad 1282static struct snd_soc_dai_driver wm8990_dai = {
f10485e7 1283/* ADC/DAC on primary */
f0fba2ad 1284 .name = "wm8990-hifi",
f10485e7
MB		 1285 .playback = {
1286 .stream_name = "Playback",
1287 .channels_min = 1,
1288 .channels_max = 2,
1289 .rates = WM8990_RATES,
1290 .formats = WM8990_FORMATS,},
1291 .capture = {
1292 .stream_name = "Capture",
1293 .channels_min = 1,
1294 .channels_max = 2,
1295 .rates = WM8990_RATES,
1296 .formats = WM8990_FORMATS,},
6335d055 1297 .ops = &wm8990_dai_ops,
f10485e7 1298};
f10485e7 1299
84b315ee 1300static int wm8990_suspend(struct snd_soc_codec *codec)
f10485e7 1301{
f10485e7
MB		 1302 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1303 return 0;
1304}
1305
f0fba2ad 1306static int wm8990_resume(struct snd_soc_codec *codec)
f10485e7 1307{
f10485e7
MB		 1308 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1309 return 0;
1310}
1311
1312/*
1313 * initialise the WM8990 driver
1314 * register the mixer and dsp interfaces with the kernel
1315 */
f0fba2ad 1316static int wm8990_probe(struct snd_soc_codec *codec)
f10485e7 1317{
f0fba2ad 1318 int ret;
f10485e7 1319
8d50e447
MB		 1320 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1321 if (ret < 0) {
1322 printk(KERN_ERR "wm8990: failed to set cache I/O: %d\n", ret);
f0fba2ad 1323 return ret;
8d50e447
MB		 1324 }
1325
f10485e7
MB		 1326 wm8990_reset(codec);
1327
f10485e7 1328 /* charge output caps */
f10485e7
MB		 1329 wm8990_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1330
79d07265
AL		 1331 snd_soc_update_bits(codec, WM8990_AUDIO_INTERFACE_4,
1332 WM8990_ALRCGPIO1, WM8990_ALRCGPIO1);
f10485e7 1333
79d07265
AL		 1334 snd_soc_update_bits(codec, WM8990_GPIO1_GPIO2,
1335 WM8990_GPIO1_SEL_MASK, 1);
f10485e7 1336
79d07265
AL		 1337 snd_soc_update_bits(codec, WM8990_POWER_MANAGEMENT_2,
1338 WM8990_OPCLK_ENA, WM8990_OPCLK_ENA);
f10485e7 1339
8d50e447
MB		 1340 snd_soc_write(codec, WM8990_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1341 snd_soc_write(codec, WM8990_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
f10485e7 1342
f0fba2ad
LG		 1343 return 0;
1344}
f10485e7 1345
f0fba2ad
LG		 1346/* power down chip */
1347static int wm8990_remove(struct snd_soc_codec *codec)
1348{
1349 wm8990_set_bias_level(codec, SND_SOC_BIAS_OFF);
1350 return 0;
f10485e7
MB		 1351}
1352
f0fba2ad
LG		 1353static struct snd_soc_codec_driver soc_codec_dev_wm8990 = {
1354 .probe = wm8990_probe,
1355 .remove = wm8990_remove,
1356 .suspend = wm8990_suspend,
1357 .resume = wm8990_resume,
1358 .set_bias_level = wm8990_set_bias_level,
1359 .reg_cache_size = ARRAY_SIZE(wm8990_reg),
1360 .reg_word_size = sizeof(u16),
1361 .reg_cache_default = wm8990_reg,
416a0ce5 1362 .volatile_register = wm8990_volatile_register,
f6b415b6
MB		 1363 .controls = wm8990_snd_controls,
1364 .num_controls = ARRAY_SIZE(wm8990_snd_controls),
1365 .dapm_widgets = wm8990_dapm_widgets,
1366 .num_dapm_widgets = ARRAY_SIZE(wm8990_dapm_widgets),
1367 .dapm_routes = wm8990_dapm_routes,
1368 .num_dapm_routes = ARRAY_SIZE(wm8990_dapm_routes),
f0fba2ad 1369};
f10485e7 1370
7a79e94e
BP		 1371static int wm8990_i2c_probe(struct i2c_client *i2c,
1372 const struct i2c_device_id *id)
f10485e7 1373{
f0fba2ad 1374 struct wm8990_priv *wm8990;
f10485e7
MB		 1375 int ret;
1376
587cbbb3
MB		 1377 wm8990 = devm_kzalloc(&i2c->dev, sizeof(struct wm8990_priv),
1378 GFP_KERNEL);
f0fba2ad
LG		 1379 if (wm8990 == NULL)
1380 return -ENOMEM;
f10485e7 1381
f0fba2ad 1382 i2c_set_clientdata(i2c, wm8990);
f10485e7 1383
f0fba2ad
LG		 1384 ret = snd_soc_register_codec(&i2c->dev,
1385 &soc_codec_dev_wm8990, &wm8990_dai, 1);
587cbbb3 1386
f10485e7
MB		 1387 return ret;
1388}
1389
7a79e94e 1390static int wm8990_i2c_remove(struct i2c_client *client)
f10485e7 1391{
f0fba2ad 1392 snd_soc_unregister_codec(&client->dev);
587cbbb3 1393
f10485e7
MB		 1394 return 0;
1395}
1396
e5d3fd38
JD		 1397static const struct i2c_device_id wm8990_i2c_id[] = {
1398 { "wm8990", 0 },
1399 { }
1400};
1401MODULE_DEVICE_TABLE(i2c, wm8990_i2c_id);
f10485e7
MB		 1402
1403static struct i2c_driver wm8990_i2c_driver = {
1404 .driver = {
091edccf 1405 .name = "wm8990",
f10485e7
MB		 1406 .owner = THIS_MODULE,
1407 },
e5d3fd38 1408 .probe = wm8990_i2c_probe,
7a79e94e 1409 .remove = wm8990_i2c_remove,
e5d3fd38 1410 .id_table = wm8990_i2c_id,
f10485e7 1411};
f10485e7 1412
93818c9a 1413module_i2c_driver(wm8990_i2c_driver);
64089b84 1414
f10485e7
MB		 1415MODULE_DESCRIPTION("ASoC WM8990 driver");
1416MODULE_AUTHOR("Liam Girdwood");
1417MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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