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203db220 DP |
1 | /* |
2 | * wm8991.c -- WM8991 ALSA Soc Audio driver | |
3 | * | |
4 | * Copyright 2007-2010 Wolfson Microelectronics PLC. | |
5 | * Author: Graeme Gregory | |
9a185b9a | 6 | * Graeme.Gregory@wolfsonmicro.com |
203db220 DP |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
203db220 DP |
16 | #include <linux/kernel.h> |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/i2c.h> | |
a86652e5 | 21 | #include <linux/regmap.h> |
203db220 DP |
22 | #include <linux/slab.h> |
23 | #include <sound/core.h> | |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/soc-dapm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | #include <asm/div64.h> | |
31 | ||
32 | #include "wm8991.h" | |
33 | ||
34 | struct wm8991_priv { | |
a86652e5 | 35 | struct regmap *regmap; |
203db220 DP |
36 | unsigned int pcmclk; |
37 | }; | |
38 | ||
a86652e5 MB |
39 | static const struct reg_default wm8991_reg_defaults[] = { |
40 | { 1, 0x0000 }, /* R1 - Power Management (1) */ | |
41 | { 2, 0x6000 }, /* R2 - Power Management (2) */ | |
42 | { 3, 0x0000 }, /* R3 - Power Management (3) */ | |
43 | { 4, 0x4050 }, /* R4 - Audio Interface (1) */ | |
44 | { 5, 0x4000 }, /* R5 - Audio Interface (2) */ | |
45 | { 6, 0x01C8 }, /* R6 - Clocking (1) */ | |
46 | { 7, 0x0000 }, /* R7 - Clocking (2) */ | |
47 | { 8, 0x0040 }, /* R8 - Audio Interface (3) */ | |
48 | { 9, 0x0040 }, /* R9 - Audio Interface (4) */ | |
49 | { 10, 0x0004 }, /* R10 - DAC CTRL */ | |
50 | { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */ | |
51 | { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */ | |
52 | { 13, 0x0000 }, /* R13 - Digital Side Tone */ | |
53 | { 14, 0x0100 }, /* R14 - ADC CTRL */ | |
54 | { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */ | |
55 | { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */ | |
56 | ||
57 | { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */ | |
58 | { 19, 0x1000 }, /* R19 - GPIO1 & GPIO2 */ | |
59 | { 20, 0x1010 }, /* R20 - GPIO3 & GPIO4 */ | |
60 | { 21, 0x1010 }, /* R21 - GPIO5 & GPIO6 */ | |
61 | { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */ | |
62 | { 23, 0x0800 }, /* R23 - GPIO_POL */ | |
63 | { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */ | |
64 | { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */ | |
65 | { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */ | |
66 | { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */ | |
67 | { 28, 0x0000 }, /* R28 - Left Output Volume */ | |
68 | { 29, 0x0000 }, /* R29 - Right Output Volume */ | |
69 | { 30, 0x0066 }, /* R30 - Line Outputs Volume */ | |
70 | { 31, 0x0022 }, /* R31 - Out3/4 Volume */ | |
71 | { 32, 0x0079 }, /* R32 - Left OPGA Volume */ | |
72 | { 33, 0x0079 }, /* R33 - Right OPGA Volume */ | |
73 | { 34, 0x0003 }, /* R34 - Speaker Volume */ | |
74 | { 35, 0x0003 }, /* R35 - ClassD1 */ | |
75 | ||
76 | { 37, 0x0100 }, /* R37 - ClassD3 */ | |
77 | ||
78 | { 39, 0x0000 }, /* R39 - Input Mixer1 */ | |
79 | { 40, 0x0000 }, /* R40 - Input Mixer2 */ | |
80 | { 41, 0x0000 }, /* R41 - Input Mixer3 */ | |
81 | { 42, 0x0000 }, /* R42 - Input Mixer4 */ | |
82 | { 43, 0x0000 }, /* R43 - Input Mixer5 */ | |
83 | { 44, 0x0000 }, /* R44 - Input Mixer6 */ | |
84 | { 45, 0x0000 }, /* R45 - Output Mixer1 */ | |
85 | { 46, 0x0000 }, /* R46 - Output Mixer2 */ | |
86 | { 47, 0x0000 }, /* R47 - Output Mixer3 */ | |
87 | { 48, 0x0000 }, /* R48 - Output Mixer4 */ | |
88 | { 49, 0x0000 }, /* R49 - Output Mixer5 */ | |
89 | { 50, 0x0000 }, /* R50 - Output Mixer6 */ | |
90 | { 51, 0x0180 }, /* R51 - Out3/4 Mixer */ | |
91 | { 52, 0x0000 }, /* R52 - Line Mixer1 */ | |
92 | { 53, 0x0000 }, /* R53 - Line Mixer2 */ | |
93 | { 54, 0x0000 }, /* R54 - Speaker Mixer */ | |
94 | { 55, 0x0000 }, /* R55 - Additional Control */ | |
95 | { 56, 0x0000 }, /* R56 - AntiPOP1 */ | |
96 | { 57, 0x0000 }, /* R57 - AntiPOP2 */ | |
97 | { 58, 0x0000 }, /* R58 - MICBIAS */ | |
98 | ||
99 | { 60, 0x0008 }, /* R60 - PLL1 */ | |
100 | { 61, 0x0031 }, /* R61 - PLL2 */ | |
101 | { 62, 0x0026 }, /* R62 - PLL3 */ | |
203db220 DP |
102 | }; |
103 | ||
a86652e5 MB |
104 | static bool wm8991_volatile(struct device *dev, unsigned int reg) |
105 | { | |
106 | switch (reg) { | |
107 | case WM8991_RESET: | |
108 | return true; | |
109 | default: | |
110 | return false; | |
111 | } | |
112 | } | |
113 | ||
00769dbe LPC |
114 | static const DECLARE_TLV_DB_LINEAR(rec_mix_tlv, -1500, 600); |
115 | static const DECLARE_TLV_DB_LINEAR(in_pga_tlv, -1650, 3000); | |
116 | static const DECLARE_TLV_DB_LINEAR(out_mix_tlv, 0, -2100); | |
117 | static const DECLARE_TLV_DB_LINEAR(out_pga_tlv, -7300, 600); | |
118 | static const DECLARE_TLV_DB_LINEAR(out_omix_tlv, -600, 0); | |
119 | static const DECLARE_TLV_DB_LINEAR(out_dac_tlv, -7163, 0); | |
120 | static const DECLARE_TLV_DB_LINEAR(in_adc_tlv, -7163, 1763); | |
121 | static const DECLARE_TLV_DB_LINEAR(out_sidetone_tlv, -3600, 0); | |
203db220 DP |
122 | |
123 | static int wm899x_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, | |
124 | struct snd_ctl_elem_value *ucontrol) | |
125 | { | |
ea53bf77 | 126 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
203db220 DP |
127 | int reg = kcontrol->private_value & 0xff; |
128 | int ret; | |
129 | u16 val; | |
130 | ||
131 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
132 | if (ret < 0) | |
133 | return ret; | |
134 | ||
135 | /* now hit the volume update bits (always bit 8) */ | |
136 | val = snd_soc_read(codec, reg); | |
137 | return snd_soc_write(codec, reg, val | 0x0100); | |
138 | } | |
139 | ||
140 | static const char *wm8991_digital_sidetone[] = | |
141 | {"None", "Left ADC", "Right ADC", "Reserved"}; | |
142 | ||
d07338b0 TI |
143 | static SOC_ENUM_SINGLE_DECL(wm8991_left_digital_sidetone_enum, |
144 | WM8991_DIGITAL_SIDE_TONE, | |
145 | WM8991_ADC_TO_DACL_SHIFT, | |
146 | wm8991_digital_sidetone); | |
147 | ||
148 | static SOC_ENUM_SINGLE_DECL(wm8991_right_digital_sidetone_enum, | |
149 | WM8991_DIGITAL_SIDE_TONE, | |
150 | WM8991_ADC_TO_DACR_SHIFT, | |
151 | wm8991_digital_sidetone); | |
203db220 DP |
152 | |
153 | static const char *wm8991_adcmode[] = | |
154 | {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; | |
155 | ||
d07338b0 TI |
156 | static SOC_ENUM_SINGLE_DECL(wm8991_right_adcmode_enum, |
157 | WM8991_ADC_CTRL, | |
158 | WM8991_ADC_HPF_CUT_SHIFT, | |
159 | wm8991_adcmode); | |
203db220 DP |
160 | |
161 | static const struct snd_kcontrol_new wm8991_snd_controls[] = { | |
162 | /* INMIXL */ | |
163 | SOC_SINGLE("LIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L12MNBST_BIT, 1, 0), | |
164 | SOC_SINGLE("LIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_L34MNBST_BIT, 1, 0), | |
165 | /* INMIXR */ | |
166 | SOC_SINGLE("RIN12 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R12MNBST_BIT, 1, 0), | |
167 | SOC_SINGLE("RIN34 PGA Boost", WM8991_INPUT_MIXER3, WM8991_R34MNBST_BIT, 1, 0), | |
168 | ||
169 | /* LOMIX */ | |
170 | SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER3, | |
171 | WM8991_LLI3LOVOL_SHIFT, WM8991_LLI3LOVOL_MASK, 1, out_mix_tlv), | |
172 | SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, | |
173 | WM8991_LR12LOVOL_SHIFT, WM8991_LR12LOVOL_MASK, 1, out_mix_tlv), | |
174 | SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER3, | |
175 | WM8991_LL12LOVOL_SHIFT, WM8991_LL12LOVOL_MASK, 1, out_mix_tlv), | |
176 | SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER5, | |
177 | WM8991_LRI3LOVOL_SHIFT, WM8991_LRI3LOVOL_MASK, 1, out_mix_tlv), | |
178 | SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER5, | |
179 | WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), | |
180 | SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER5, | |
181 | WM8991_LRBLOVOL_SHIFT, WM8991_LRBLOVOL_MASK, 1, out_mix_tlv), | |
182 | ||
183 | /* ROMIX */ | |
184 | SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8991_OUTPUT_MIXER4, | |
185 | WM8991_RRI3ROVOL_SHIFT, WM8991_RRI3ROVOL_MASK, 1, out_mix_tlv), | |
186 | SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, | |
187 | WM8991_RL12ROVOL_SHIFT, WM8991_RL12ROVOL_MASK, 1, out_mix_tlv), | |
188 | SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8991_OUTPUT_MIXER4, | |
189 | WM8991_RR12ROVOL_SHIFT, WM8991_RR12ROVOL_MASK, 1, out_mix_tlv), | |
190 | SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8991_OUTPUT_MIXER6, | |
191 | WM8991_RLI3ROVOL_SHIFT, WM8991_RLI3ROVOL_MASK, 1, out_mix_tlv), | |
192 | SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8991_OUTPUT_MIXER6, | |
193 | WM8991_RLBROVOL_SHIFT, WM8991_RLBROVOL_MASK, 1, out_mix_tlv), | |
194 | SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8991_OUTPUT_MIXER6, | |
195 | WM8991_RRBROVOL_SHIFT, WM8991_RRBROVOL_MASK, 1, out_mix_tlv), | |
196 | ||
197 | /* LOUT */ | |
198 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8991_LEFT_OUTPUT_VOLUME, | |
199 | WM8991_LOUTVOL_SHIFT, WM8991_LOUTVOL_MASK, 0, out_pga_tlv), | |
200 | SOC_SINGLE("LOUT ZC", WM8991_LEFT_OUTPUT_VOLUME, WM8991_LOZC_BIT, 1, 0), | |
201 | ||
202 | /* ROUT */ | |
203 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8991_RIGHT_OUTPUT_VOLUME, | |
204 | WM8991_ROUTVOL_SHIFT, WM8991_ROUTVOL_MASK, 0, out_pga_tlv), | |
205 | SOC_SINGLE("ROUT ZC", WM8991_RIGHT_OUTPUT_VOLUME, WM8991_ROZC_BIT, 1, 0), | |
206 | ||
207 | /* LOPGA */ | |
208 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8991_LEFT_OPGA_VOLUME, | |
209 | WM8991_LOPGAVOL_SHIFT, WM8991_LOPGAVOL_MASK, 0, out_pga_tlv), | |
210 | SOC_SINGLE("LOPGA ZC Switch", WM8991_LEFT_OPGA_VOLUME, | |
211 | WM8991_LOPGAZC_BIT, 1, 0), | |
212 | ||
213 | /* ROPGA */ | |
214 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8991_RIGHT_OPGA_VOLUME, | |
215 | WM8991_ROPGAVOL_SHIFT, WM8991_ROPGAVOL_MASK, 0, out_pga_tlv), | |
216 | SOC_SINGLE("ROPGA ZC Switch", WM8991_RIGHT_OPGA_VOLUME, | |
217 | WM8991_ROPGAZC_BIT, 1, 0), | |
218 | ||
219 | SOC_SINGLE("LON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, | |
220 | WM8991_LONMUTE_BIT, 1, 0), | |
221 | SOC_SINGLE("LOP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, | |
222 | WM8991_LOPMUTE_BIT, 1, 0), | |
223 | SOC_SINGLE("LOP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, | |
224 | WM8991_LOATTN_BIT, 1, 0), | |
225 | SOC_SINGLE("RON Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, | |
226 | WM8991_RONMUTE_BIT, 1, 0), | |
227 | SOC_SINGLE("ROP Mute Switch", WM8991_LINE_OUTPUTS_VOLUME, | |
228 | WM8991_ROPMUTE_BIT, 1, 0), | |
229 | SOC_SINGLE("ROP Attenuation Switch", WM8991_LINE_OUTPUTS_VOLUME, | |
230 | WM8991_ROATTN_BIT, 1, 0), | |
231 | ||
232 | SOC_SINGLE("OUT3 Mute Switch", WM8991_OUT3_4_VOLUME, | |
233 | WM8991_OUT3MUTE_BIT, 1, 0), | |
234 | SOC_SINGLE("OUT3 Attenuation Switch", WM8991_OUT3_4_VOLUME, | |
235 | WM8991_OUT3ATTN_BIT, 1, 0), | |
236 | ||
237 | SOC_SINGLE("OUT4 Mute Switch", WM8991_OUT3_4_VOLUME, | |
238 | WM8991_OUT4MUTE_BIT, 1, 0), | |
239 | SOC_SINGLE("OUT4 Attenuation Switch", WM8991_OUT3_4_VOLUME, | |
240 | WM8991_OUT4ATTN_BIT, 1, 0), | |
241 | ||
242 | SOC_SINGLE("Speaker Mode Switch", WM8991_CLASSD1, | |
243 | WM8991_CDMODE_BIT, 1, 0), | |
244 | ||
245 | SOC_SINGLE("Speaker Output Attenuation Volume", WM8991_SPEAKER_VOLUME, | |
246 | WM8991_SPKVOL_SHIFT, WM8991_SPKVOL_MASK, 0), | |
247 | SOC_SINGLE("Speaker DC Boost Volume", WM8991_CLASSD3, | |
248 | WM8991_DCGAIN_SHIFT, WM8991_DCGAIN_MASK, 0), | |
249 | SOC_SINGLE("Speaker AC Boost Volume", WM8991_CLASSD3, | |
250 | WM8991_ACGAIN_SHIFT, WM8991_ACGAIN_MASK, 0), | |
251 | ||
252 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", | |
253 | WM8991_LEFT_DAC_DIGITAL_VOLUME, | |
254 | WM8991_DACL_VOL_SHIFT, | |
255 | WM8991_DACL_VOL_MASK, | |
256 | 0, | |
257 | out_dac_tlv), | |
258 | ||
259 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", | |
260 | WM8991_RIGHT_DAC_DIGITAL_VOLUME, | |
261 | WM8991_DACR_VOL_SHIFT, | |
262 | WM8991_DACR_VOL_MASK, | |
263 | 0, | |
264 | out_dac_tlv), | |
265 | ||
266 | SOC_ENUM("Left Digital Sidetone", wm8991_left_digital_sidetone_enum), | |
267 | SOC_ENUM("Right Digital Sidetone", wm8991_right_digital_sidetone_enum), | |
268 | ||
269 | SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, | |
270 | WM8991_ADCL_DAC_SVOL_SHIFT, WM8991_ADCL_DAC_SVOL_MASK, 0, | |
271 | out_sidetone_tlv), | |
272 | SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8991_DIGITAL_SIDE_TONE, | |
273 | WM8991_ADCR_DAC_SVOL_SHIFT, WM8991_ADCR_DAC_SVOL_MASK, 0, | |
274 | out_sidetone_tlv), | |
275 | ||
276 | SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8991_ADC_CTRL, | |
277 | WM8991_ADC_HPF_ENA_BIT, 1, 0), | |
278 | ||
279 | SOC_ENUM("ADC HPF Mode", wm8991_right_adcmode_enum), | |
280 | ||
281 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", | |
282 | WM8991_LEFT_ADC_DIGITAL_VOLUME, | |
283 | WM8991_ADCL_VOL_SHIFT, | |
284 | WM8991_ADCL_VOL_MASK, | |
285 | 0, | |
286 | in_adc_tlv), | |
287 | ||
288 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", | |
289 | WM8991_RIGHT_ADC_DIGITAL_VOLUME, | |
290 | WM8991_ADCR_VOL_SHIFT, | |
291 | WM8991_ADCR_VOL_MASK, | |
292 | 0, | |
293 | in_adc_tlv), | |
294 | ||
295 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN12 Volume", | |
296 | WM8991_LEFT_LINE_INPUT_1_2_VOLUME, | |
297 | WM8991_LIN12VOL_SHIFT, | |
298 | WM8991_LIN12VOL_MASK, | |
299 | 0, | |
300 | in_pga_tlv), | |
301 | ||
302 | SOC_SINGLE("LIN12 ZC Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, | |
303 | WM8991_LI12ZC_BIT, 1, 0), | |
304 | ||
305 | SOC_SINGLE("LIN12 Mute Switch", WM8991_LEFT_LINE_INPUT_1_2_VOLUME, | |
306 | WM8991_LI12MUTE_BIT, 1, 0), | |
307 | ||
308 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("LIN34 Volume", | |
309 | WM8991_LEFT_LINE_INPUT_3_4_VOLUME, | |
310 | WM8991_LIN34VOL_SHIFT, | |
311 | WM8991_LIN34VOL_MASK, | |
312 | 0, | |
313 | in_pga_tlv), | |
314 | ||
315 | SOC_SINGLE("LIN34 ZC Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, | |
316 | WM8991_LI34ZC_BIT, 1, 0), | |
317 | ||
318 | SOC_SINGLE("LIN34 Mute Switch", WM8991_LEFT_LINE_INPUT_3_4_VOLUME, | |
319 | WM8991_LI34MUTE_BIT, 1, 0), | |
320 | ||
321 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN12 Volume", | |
322 | WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, | |
323 | WM8991_RIN12VOL_SHIFT, | |
324 | WM8991_RIN12VOL_MASK, | |
325 | 0, | |
326 | in_pga_tlv), | |
327 | ||
328 | SOC_SINGLE("RIN12 ZC Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, | |
329 | WM8991_RI12ZC_BIT, 1, 0), | |
330 | ||
331 | SOC_SINGLE("RIN12 Mute Switch", WM8991_RIGHT_LINE_INPUT_1_2_VOLUME, | |
332 | WM8991_RI12MUTE_BIT, 1, 0), | |
333 | ||
334 | SOC_WM899X_OUTPGA_SINGLE_R_TLV("RIN34 Volume", | |
335 | WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, | |
336 | WM8991_RIN34VOL_SHIFT, | |
337 | WM8991_RIN34VOL_MASK, | |
338 | 0, | |
339 | in_pga_tlv), | |
340 | ||
341 | SOC_SINGLE("RIN34 ZC Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, | |
342 | WM8991_RI34ZC_BIT, 1, 0), | |
343 | ||
344 | SOC_SINGLE("RIN34 Mute Switch", WM8991_RIGHT_LINE_INPUT_3_4_VOLUME, | |
345 | WM8991_RI34MUTE_BIT, 1, 0), | |
346 | }; | |
347 | ||
348 | /* | |
349 | * _DAPM_ Controls | |
350 | */ | |
203db220 DP |
351 | static int outmixer_event(struct snd_soc_dapm_widget *w, |
352 | struct snd_kcontrol *kcontrol, int event) | |
353 | { | |
f3b4d68f | 354 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
203db220 DP |
355 | u32 reg_shift = kcontrol->private_value & 0xfff; |
356 | int ret = 0; | |
357 | u16 reg; | |
358 | ||
359 | switch (reg_shift) { | |
360 | case WM8991_SPEAKER_MIXER | (WM8991_LDSPK_BIT << 8): | |
f3b4d68f | 361 | reg = snd_soc_read(codec, WM8991_OUTPUT_MIXER1); |
203db220 DP |
362 | if (reg & WM8991_LDLO) { |
363 | printk(KERN_WARNING | |
364 | "Cannot set as Output Mixer 1 LDLO Set\n"); | |
365 | ret = -1; | |
366 | } | |
367 | break; | |
368 | ||
369 | case WM8991_SPEAKER_MIXER | (WM8991_RDSPK_BIT << 8): | |
f3b4d68f | 370 | reg = snd_soc_read(codec, WM8991_OUTPUT_MIXER2); |
203db220 DP |
371 | if (reg & WM8991_RDRO) { |
372 | printk(KERN_WARNING | |
373 | "Cannot set as Output Mixer 2 RDRO Set\n"); | |
374 | ret = -1; | |
375 | } | |
376 | break; | |
377 | ||
378 | case WM8991_OUTPUT_MIXER1 | (WM8991_LDLO_BIT << 8): | |
f3b4d68f | 379 | reg = snd_soc_read(codec, WM8991_SPEAKER_MIXER); |
203db220 DP |
380 | if (reg & WM8991_LDSPK) { |
381 | printk(KERN_WARNING | |
382 | "Cannot set as Speaker Mixer LDSPK Set\n"); | |
383 | ret = -1; | |
384 | } | |
385 | break; | |
386 | ||
387 | case WM8991_OUTPUT_MIXER2 | (WM8991_RDRO_BIT << 8): | |
f3b4d68f | 388 | reg = snd_soc_read(codec, WM8991_SPEAKER_MIXER); |
203db220 DP |
389 | if (reg & WM8991_RDSPK) { |
390 | printk(KERN_WARNING | |
391 | "Cannot set as Speaker Mixer RDSPK Set\n"); | |
392 | ret = -1; | |
393 | } | |
394 | break; | |
395 | } | |
396 | ||
397 | return ret; | |
398 | } | |
399 | ||
400 | /* INMIX dB values */ | |
00769dbe | 401 | static const DECLARE_TLV_DB_LINEAR(in_mix_tlv, -1200, 600); |
203db220 DP |
402 | |
403 | /* Left In PGA Connections */ | |
404 | static const struct snd_kcontrol_new wm8991_dapm_lin12_pga_controls[] = { | |
405 | SOC_DAPM_SINGLE("LIN1 Switch", WM8991_INPUT_MIXER2, WM8991_LMN1_BIT, 1, 0), | |
406 | SOC_DAPM_SINGLE("LIN2 Switch", WM8991_INPUT_MIXER2, WM8991_LMP2_BIT, 1, 0), | |
407 | }; | |
408 | ||
409 | static const struct snd_kcontrol_new wm8991_dapm_lin34_pga_controls[] = { | |
410 | SOC_DAPM_SINGLE("LIN3 Switch", WM8991_INPUT_MIXER2, WM8991_LMN3_BIT, 1, 0), | |
411 | SOC_DAPM_SINGLE("LIN4 Switch", WM8991_INPUT_MIXER2, WM8991_LMP4_BIT, 1, 0), | |
412 | }; | |
413 | ||
414 | /* Right In PGA Connections */ | |
415 | static const struct snd_kcontrol_new wm8991_dapm_rin12_pga_controls[] = { | |
416 | SOC_DAPM_SINGLE("RIN1 Switch", WM8991_INPUT_MIXER2, WM8991_RMN1_BIT, 1, 0), | |
417 | SOC_DAPM_SINGLE("RIN2 Switch", WM8991_INPUT_MIXER2, WM8991_RMP2_BIT, 1, 0), | |
418 | }; | |
419 | ||
420 | static const struct snd_kcontrol_new wm8991_dapm_rin34_pga_controls[] = { | |
421 | SOC_DAPM_SINGLE("RIN3 Switch", WM8991_INPUT_MIXER2, WM8991_RMN3_BIT, 1, 0), | |
422 | SOC_DAPM_SINGLE("RIN4 Switch", WM8991_INPUT_MIXER2, WM8991_RMP4_BIT, 1, 0), | |
423 | }; | |
424 | ||
425 | /* INMIXL */ | |
426 | static const struct snd_kcontrol_new wm8991_dapm_inmixl_controls[] = { | |
427 | SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8991_INPUT_MIXER3, | |
428 | WM8991_LDBVOL_SHIFT, WM8991_LDBVOL_MASK, 0, in_mix_tlv), | |
429 | SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8991_INPUT_MIXER5, WM8991_LI2BVOL_SHIFT, | |
430 | 7, 0, in_mix_tlv), | |
431 | SOC_DAPM_SINGLE("LINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, | |
432 | 1, 0), | |
433 | SOC_DAPM_SINGLE("LINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, | |
434 | 1, 0), | |
435 | }; | |
436 | ||
437 | /* INMIXR */ | |
438 | static const struct snd_kcontrol_new wm8991_dapm_inmixr_controls[] = { | |
439 | SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8991_INPUT_MIXER4, | |
440 | WM8991_RDBVOL_SHIFT, WM8991_RDBVOL_MASK, 0, in_mix_tlv), | |
441 | SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8991_INPUT_MIXER6, WM8991_RI2BVOL_SHIFT, | |
442 | 7, 0, in_mix_tlv), | |
443 | SOC_DAPM_SINGLE("RINPGA12 Switch", WM8991_INPUT_MIXER3, WM8991_L12MNB_BIT, | |
444 | 1, 0), | |
445 | SOC_DAPM_SINGLE("RINPGA34 Switch", WM8991_INPUT_MIXER3, WM8991_L34MNB_BIT, | |
446 | 1, 0), | |
447 | }; | |
448 | ||
449 | /* AINLMUX */ | |
450 | static const char *wm8991_ainlmux[] = | |
451 | {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; | |
452 | ||
d07338b0 TI |
453 | static SOC_ENUM_SINGLE_DECL(wm8991_ainlmux_enum, |
454 | WM8991_INPUT_MIXER1, WM8991_AINLMODE_SHIFT, | |
455 | wm8991_ainlmux); | |
203db220 DP |
456 | |
457 | static const struct snd_kcontrol_new wm8991_dapm_ainlmux_controls = | |
458 | SOC_DAPM_ENUM("Route", wm8991_ainlmux_enum); | |
459 | ||
460 | /* DIFFINL */ | |
461 | ||
462 | /* AINRMUX */ | |
463 | static const char *wm8991_ainrmux[] = | |
464 | {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; | |
465 | ||
d07338b0 TI |
466 | static SOC_ENUM_SINGLE_DECL(wm8991_ainrmux_enum, |
467 | WM8991_INPUT_MIXER1, WM8991_AINRMODE_SHIFT, | |
468 | wm8991_ainrmux); | |
203db220 DP |
469 | |
470 | static const struct snd_kcontrol_new wm8991_dapm_ainrmux_controls = | |
471 | SOC_DAPM_ENUM("Route", wm8991_ainrmux_enum); | |
472 | ||
473 | /* RXVOICE */ | |
474 | static const struct snd_kcontrol_new wm8991_dapm_rxvoice_controls[] = { | |
475 | SOC_DAPM_SINGLE_TLV("LIN4RXN", WM8991_INPUT_MIXER5, WM8991_LR4BVOL_SHIFT, | |
476 | WM8991_LR4BVOL_MASK, 0, in_mix_tlv), | |
477 | SOC_DAPM_SINGLE_TLV("RIN4RXP", WM8991_INPUT_MIXER6, WM8991_RL4BVOL_SHIFT, | |
478 | WM8991_RL4BVOL_MASK, 0, in_mix_tlv), | |
479 | }; | |
480 | ||
481 | /* LOMIX */ | |
482 | static const struct snd_kcontrol_new wm8991_dapm_lomix_controls[] = { | |
483 | SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER1, | |
484 | WM8991_LRBLO_BIT, 1, 0), | |
485 | SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER1, | |
486 | WM8991_LLBLO_BIT, 1, 0), | |
487 | SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, | |
488 | WM8991_LRI3LO_BIT, 1, 0), | |
489 | SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER1, | |
490 | WM8991_LLI3LO_BIT, 1, 0), | |
491 | SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, | |
492 | WM8991_LR12LO_BIT, 1, 0), | |
493 | SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER1, | |
494 | WM8991_LL12LO_BIT, 1, 0), | |
495 | SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8991_OUTPUT_MIXER1, | |
496 | WM8991_LDLO_BIT, 1, 0), | |
497 | }; | |
498 | ||
499 | /* ROMIX */ | |
500 | static const struct snd_kcontrol_new wm8991_dapm_romix_controls[] = { | |
501 | SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8991_OUTPUT_MIXER2, | |
502 | WM8991_RLBRO_BIT, 1, 0), | |
503 | SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8991_OUTPUT_MIXER2, | |
504 | WM8991_RRBRO_BIT, 1, 0), | |
505 | SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, | |
506 | WM8991_RLI3RO_BIT, 1, 0), | |
507 | SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8991_OUTPUT_MIXER2, | |
508 | WM8991_RRI3RO_BIT, 1, 0), | |
509 | SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, | |
510 | WM8991_RL12RO_BIT, 1, 0), | |
511 | SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8991_OUTPUT_MIXER2, | |
512 | WM8991_RR12RO_BIT, 1, 0), | |
513 | SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8991_OUTPUT_MIXER2, | |
514 | WM8991_RDRO_BIT, 1, 0), | |
515 | }; | |
516 | ||
517 | /* LONMIX */ | |
518 | static const struct snd_kcontrol_new wm8991_dapm_lonmix_controls[] = { | |
519 | SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, | |
520 | WM8991_LLOPGALON_BIT, 1, 0), | |
521 | SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER1, | |
522 | WM8991_LROPGALON_BIT, 1, 0), | |
523 | SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8991_LINE_MIXER1, | |
524 | WM8991_LOPLON_BIT, 1, 0), | |
525 | }; | |
526 | ||
527 | /* LOPMIX */ | |
528 | static const struct snd_kcontrol_new wm8991_dapm_lopmix_controls[] = { | |
529 | SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER1, | |
530 | WM8991_LR12LOP_BIT, 1, 0), | |
531 | SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER1, | |
532 | WM8991_LL12LOP_BIT, 1, 0), | |
533 | SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8991_LINE_MIXER1, | |
534 | WM8991_LLOPGALOP_BIT, 1, 0), | |
535 | }; | |
536 | ||
537 | /* RONMIX */ | |
538 | static const struct snd_kcontrol_new wm8991_dapm_ronmix_controls[] = { | |
539 | SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, | |
540 | WM8991_RROPGARON_BIT, 1, 0), | |
541 | SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8991_LINE_MIXER2, | |
542 | WM8991_RLOPGARON_BIT, 1, 0), | |
543 | SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8991_LINE_MIXER2, | |
544 | WM8991_ROPRON_BIT, 1, 0), | |
545 | }; | |
546 | ||
547 | /* ROPMIX */ | |
548 | static const struct snd_kcontrol_new wm8991_dapm_ropmix_controls[] = { | |
549 | SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8991_LINE_MIXER2, | |
550 | WM8991_RL12ROP_BIT, 1, 0), | |
551 | SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8991_LINE_MIXER2, | |
552 | WM8991_RR12ROP_BIT, 1, 0), | |
553 | SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8991_LINE_MIXER2, | |
554 | WM8991_RROPGAROP_BIT, 1, 0), | |
555 | }; | |
556 | ||
557 | /* OUT3MIX */ | |
558 | static const struct snd_kcontrol_new wm8991_dapm_out3mix_controls[] = { | |
559 | SOC_DAPM_SINGLE("OUT3MIX LIN4RXN Bypass Switch", WM8991_OUT3_4_MIXER, | |
560 | WM8991_LI4O3_BIT, 1, 0), | |
561 | SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8991_OUT3_4_MIXER, | |
562 | WM8991_LPGAO3_BIT, 1, 0), | |
563 | }; | |
564 | ||
565 | /* OUT4MIX */ | |
566 | static const struct snd_kcontrol_new wm8991_dapm_out4mix_controls[] = { | |
567 | SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8991_OUT3_4_MIXER, | |
568 | WM8991_RPGAO4_BIT, 1, 0), | |
569 | SOC_DAPM_SINGLE("OUT4MIX RIN4RXP Bypass Switch", WM8991_OUT3_4_MIXER, | |
570 | WM8991_RI4O4_BIT, 1, 0), | |
571 | }; | |
572 | ||
573 | /* SPKMIX */ | |
574 | static const struct snd_kcontrol_new wm8991_dapm_spkmix_controls[] = { | |
575 | SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8991_SPEAKER_MIXER, | |
576 | WM8991_LI2SPK_BIT, 1, 0), | |
577 | SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8991_SPEAKER_MIXER, | |
578 | WM8991_LB2SPK_BIT, 1, 0), | |
579 | SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8991_SPEAKER_MIXER, | |
580 | WM8991_LOPGASPK_BIT, 1, 0), | |
581 | SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8991_SPEAKER_MIXER, | |
582 | WM8991_LDSPK_BIT, 1, 0), | |
583 | SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8991_SPEAKER_MIXER, | |
584 | WM8991_RDSPK_BIT, 1, 0), | |
585 | SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8991_SPEAKER_MIXER, | |
586 | WM8991_ROPGASPK_BIT, 1, 0), | |
587 | SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8991_SPEAKER_MIXER, | |
588 | WM8991_RL12ROP_BIT, 1, 0), | |
589 | SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8991_SPEAKER_MIXER, | |
590 | WM8991_RI2SPK_BIT, 1, 0), | |
591 | }; | |
592 | ||
593 | static const struct snd_soc_dapm_widget wm8991_dapm_widgets[] = { | |
594 | /* Input Side */ | |
595 | /* Input Lines */ | |
596 | SND_SOC_DAPM_INPUT("LIN1"), | |
597 | SND_SOC_DAPM_INPUT("LIN2"), | |
598 | SND_SOC_DAPM_INPUT("LIN3"), | |
599 | SND_SOC_DAPM_INPUT("LIN4RXN"), | |
600 | SND_SOC_DAPM_INPUT("RIN3"), | |
601 | SND_SOC_DAPM_INPUT("RIN4RXP"), | |
602 | SND_SOC_DAPM_INPUT("RIN1"), | |
603 | SND_SOC_DAPM_INPUT("RIN2"), | |
604 | SND_SOC_DAPM_INPUT("Internal ADC Source"), | |
605 | ||
6a077336 MB |
606 | SND_SOC_DAPM_SUPPLY("INL", WM8991_POWER_MANAGEMENT_2, |
607 | WM8991_AINL_ENA_BIT, 0, NULL, 0), | |
608 | SND_SOC_DAPM_SUPPLY("INR", WM8991_POWER_MANAGEMENT_2, | |
609 | WM8991_AINR_ENA_BIT, 0, NULL, 0), | |
610 | ||
203db220 DP |
611 | /* DACs */ |
612 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8991_POWER_MANAGEMENT_2, | |
613 | WM8991_ADCL_ENA_BIT, 0), | |
614 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8991_POWER_MANAGEMENT_2, | |
615 | WM8991_ADCR_ENA_BIT, 0), | |
616 | ||
617 | /* Input PGAs */ | |
618 | SND_SOC_DAPM_MIXER("LIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN12_ENA_BIT, | |
619 | 0, &wm8991_dapm_lin12_pga_controls[0], | |
620 | ARRAY_SIZE(wm8991_dapm_lin12_pga_controls)), | |
621 | SND_SOC_DAPM_MIXER("LIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_LIN34_ENA_BIT, | |
622 | 0, &wm8991_dapm_lin34_pga_controls[0], | |
623 | ARRAY_SIZE(wm8991_dapm_lin34_pga_controls)), | |
624 | SND_SOC_DAPM_MIXER("RIN12 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN12_ENA_BIT, | |
625 | 0, &wm8991_dapm_rin12_pga_controls[0], | |
626 | ARRAY_SIZE(wm8991_dapm_rin12_pga_controls)), | |
627 | SND_SOC_DAPM_MIXER("RIN34 PGA", WM8991_POWER_MANAGEMENT_2, WM8991_RIN34_ENA_BIT, | |
628 | 0, &wm8991_dapm_rin34_pga_controls[0], | |
629 | ARRAY_SIZE(wm8991_dapm_rin34_pga_controls)), | |
630 | ||
631 | /* INMIXL */ | |
6a077336 | 632 | SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0, |
203db220 | 633 | &wm8991_dapm_inmixl_controls[0], |
6a077336 | 634 | ARRAY_SIZE(wm8991_dapm_inmixl_controls)), |
203db220 DP |
635 | |
636 | /* AINLMUX */ | |
6a077336 MB |
637 | SND_SOC_DAPM_MUX("AINLMUX", SND_SOC_NOPM, 0, 0, |
638 | &wm8991_dapm_ainlmux_controls), | |
203db220 DP |
639 | |
640 | /* INMIXR */ | |
6a077336 | 641 | SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0, |
203db220 | 642 | &wm8991_dapm_inmixr_controls[0], |
6a077336 | 643 | ARRAY_SIZE(wm8991_dapm_inmixr_controls)), |
203db220 DP |
644 | |
645 | /* AINRMUX */ | |
6a077336 MB |
646 | SND_SOC_DAPM_MUX("AINRMUX", SND_SOC_NOPM, 0, 0, |
647 | &wm8991_dapm_ainrmux_controls), | |
203db220 DP |
648 | |
649 | /* Output Side */ | |
650 | /* DACs */ | |
651 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8991_POWER_MANAGEMENT_3, | |
652 | WM8991_DACL_ENA_BIT, 0), | |
653 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8991_POWER_MANAGEMENT_3, | |
654 | WM8991_DACR_ENA_BIT, 0), | |
655 | ||
656 | /* LOMIX */ | |
657 | SND_SOC_DAPM_MIXER_E("LOMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOMIX_ENA_BIT, | |
658 | 0, &wm8991_dapm_lomix_controls[0], | |
659 | ARRAY_SIZE(wm8991_dapm_lomix_controls), | |
660 | outmixer_event, SND_SOC_DAPM_PRE_REG), | |
661 | ||
662 | /* LONMIX */ | |
663 | SND_SOC_DAPM_MIXER("LONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LON_ENA_BIT, 0, | |
664 | &wm8991_dapm_lonmix_controls[0], | |
665 | ARRAY_SIZE(wm8991_dapm_lonmix_controls)), | |
666 | ||
667 | /* LOPMIX */ | |
668 | SND_SOC_DAPM_MIXER("LOPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_LOP_ENA_BIT, 0, | |
669 | &wm8991_dapm_lopmix_controls[0], | |
670 | ARRAY_SIZE(wm8991_dapm_lopmix_controls)), | |
671 | ||
672 | /* OUT3MIX */ | |
673 | SND_SOC_DAPM_MIXER("OUT3MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT3_ENA_BIT, 0, | |
674 | &wm8991_dapm_out3mix_controls[0], | |
675 | ARRAY_SIZE(wm8991_dapm_out3mix_controls)), | |
676 | ||
677 | /* SPKMIX */ | |
678 | SND_SOC_DAPM_MIXER_E("SPKMIX", WM8991_POWER_MANAGEMENT_1, WM8991_SPK_ENA_BIT, 0, | |
679 | &wm8991_dapm_spkmix_controls[0], | |
680 | ARRAY_SIZE(wm8991_dapm_spkmix_controls), outmixer_event, | |
681 | SND_SOC_DAPM_PRE_REG), | |
682 | ||
683 | /* OUT4MIX */ | |
684 | SND_SOC_DAPM_MIXER("OUT4MIX", WM8991_POWER_MANAGEMENT_1, WM8991_OUT4_ENA_BIT, 0, | |
685 | &wm8991_dapm_out4mix_controls[0], | |
686 | ARRAY_SIZE(wm8991_dapm_out4mix_controls)), | |
687 | ||
688 | /* ROPMIX */ | |
689 | SND_SOC_DAPM_MIXER("ROPMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROP_ENA_BIT, 0, | |
690 | &wm8991_dapm_ropmix_controls[0], | |
691 | ARRAY_SIZE(wm8991_dapm_ropmix_controls)), | |
692 | ||
693 | /* RONMIX */ | |
694 | SND_SOC_DAPM_MIXER("RONMIX", WM8991_POWER_MANAGEMENT_3, WM8991_RON_ENA_BIT, 0, | |
695 | &wm8991_dapm_ronmix_controls[0], | |
696 | ARRAY_SIZE(wm8991_dapm_ronmix_controls)), | |
697 | ||
698 | /* ROMIX */ | |
699 | SND_SOC_DAPM_MIXER_E("ROMIX", WM8991_POWER_MANAGEMENT_3, WM8991_ROMIX_ENA_BIT, | |
700 | 0, &wm8991_dapm_romix_controls[0], | |
701 | ARRAY_SIZE(wm8991_dapm_romix_controls), | |
702 | outmixer_event, SND_SOC_DAPM_PRE_REG), | |
703 | ||
704 | /* LOUT PGA */ | |
705 | SND_SOC_DAPM_PGA("LOUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_LOUT_ENA_BIT, 0, | |
706 | NULL, 0), | |
707 | ||
708 | /* ROUT PGA */ | |
709 | SND_SOC_DAPM_PGA("ROUT PGA", WM8991_POWER_MANAGEMENT_1, WM8991_ROUT_ENA_BIT, 0, | |
710 | NULL, 0), | |
711 | ||
712 | /* LOPGA */ | |
713 | SND_SOC_DAPM_PGA("LOPGA", WM8991_POWER_MANAGEMENT_3, WM8991_LOPGA_ENA_BIT, 0, | |
714 | NULL, 0), | |
715 | ||
716 | /* ROPGA */ | |
717 | SND_SOC_DAPM_PGA("ROPGA", WM8991_POWER_MANAGEMENT_3, WM8991_ROPGA_ENA_BIT, 0, | |
718 | NULL, 0), | |
719 | ||
720 | /* MICBIAS */ | |
b6406a80 MB |
721 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8991_POWER_MANAGEMENT_1, |
722 | WM8991_MICBIAS_ENA_BIT, 0, NULL, 0), | |
203db220 DP |
723 | |
724 | SND_SOC_DAPM_OUTPUT("LON"), | |
725 | SND_SOC_DAPM_OUTPUT("LOP"), | |
726 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
727 | SND_SOC_DAPM_OUTPUT("LOUT"), | |
728 | SND_SOC_DAPM_OUTPUT("SPKN"), | |
729 | SND_SOC_DAPM_OUTPUT("SPKP"), | |
730 | SND_SOC_DAPM_OUTPUT("ROUT"), | |
731 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
732 | SND_SOC_DAPM_OUTPUT("ROP"), | |
733 | SND_SOC_DAPM_OUTPUT("RON"), | |
734 | SND_SOC_DAPM_OUTPUT("OUT"), | |
735 | ||
736 | SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), | |
737 | }; | |
738 | ||
89824995 | 739 | static const struct snd_soc_dapm_route wm8991_dapm_routes[] = { |
203db220 DP |
740 | /* Make DACs turn on when playing even if not mixed into any outputs */ |
741 | {"Internal DAC Sink", NULL, "Left DAC"}, | |
742 | {"Internal DAC Sink", NULL, "Right DAC"}, | |
743 | ||
744 | /* Make ADCs turn on when recording even if not mixed from any inputs */ | |
745 | {"Left ADC", NULL, "Internal ADC Source"}, | |
746 | {"Right ADC", NULL, "Internal ADC Source"}, | |
747 | ||
748 | /* Input Side */ | |
6a077336 MB |
749 | {"INMIXL", NULL, "INL"}, |
750 | {"AINLMUX", NULL, "INL"}, | |
751 | {"INMIXR", NULL, "INR"}, | |
752 | {"AINRMUX", NULL, "INR"}, | |
203db220 DP |
753 | /* LIN12 PGA */ |
754 | {"LIN12 PGA", "LIN1 Switch", "LIN1"}, | |
755 | {"LIN12 PGA", "LIN2 Switch", "LIN2"}, | |
756 | /* LIN34 PGA */ | |
757 | {"LIN34 PGA", "LIN3 Switch", "LIN3"}, | |
758 | {"LIN34 PGA", "LIN4 Switch", "LIN4RXN"}, | |
759 | /* INMIXL */ | |
760 | {"INMIXL", "Record Left Volume", "LOMIX"}, | |
761 | {"INMIXL", "LIN2 Volume", "LIN2"}, | |
762 | {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, | |
763 | {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, | |
764 | /* AINLMUX */ | |
765 | {"AINLMUX", "INMIXL Mix", "INMIXL"}, | |
766 | {"AINLMUX", "DIFFINL Mix", "LIN12 PGA"}, | |
767 | {"AINLMUX", "DIFFINL Mix", "LIN34 PGA"}, | |
768 | {"AINLMUX", "RXVOICE Mix", "LIN4RXN"}, | |
769 | {"AINLMUX", "RXVOICE Mix", "RIN4RXP"}, | |
770 | /* ADC */ | |
771 | {"Left ADC", NULL, "AINLMUX"}, | |
772 | ||
773 | /* RIN12 PGA */ | |
774 | {"RIN12 PGA", "RIN1 Switch", "RIN1"}, | |
775 | {"RIN12 PGA", "RIN2 Switch", "RIN2"}, | |
776 | /* RIN34 PGA */ | |
777 | {"RIN34 PGA", "RIN3 Switch", "RIN3"}, | |
778 | {"RIN34 PGA", "RIN4 Switch", "RIN4RXP"}, | |
779 | /* INMIXL */ | |
780 | {"INMIXR", "Record Right Volume", "ROMIX"}, | |
781 | {"INMIXR", "RIN2 Volume", "RIN2"}, | |
782 | {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, | |
783 | {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, | |
784 | /* AINRMUX */ | |
785 | {"AINRMUX", "INMIXR Mix", "INMIXR"}, | |
786 | {"AINRMUX", "DIFFINR Mix", "RIN12 PGA"}, | |
787 | {"AINRMUX", "DIFFINR Mix", "RIN34 PGA"}, | |
788 | {"AINRMUX", "RXVOICE Mix", "LIN4RXN"}, | |
789 | {"AINRMUX", "RXVOICE Mix", "RIN4RXP"}, | |
790 | /* ADC */ | |
791 | {"Right ADC", NULL, "AINRMUX"}, | |
792 | ||
793 | /* LOMIX */ | |
794 | {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, | |
795 | {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, | |
796 | {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, | |
797 | {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, | |
798 | {"LOMIX", "LOMIX Right ADC Bypass Switch", "AINRMUX"}, | |
799 | {"LOMIX", "LOMIX Left ADC Bypass Switch", "AINLMUX"}, | |
800 | {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, | |
801 | ||
802 | /* ROMIX */ | |
803 | {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, | |
804 | {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, | |
805 | {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, | |
806 | {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, | |
807 | {"ROMIX", "ROMIX Right ADC Bypass Switch", "AINRMUX"}, | |
808 | {"ROMIX", "ROMIX Left ADC Bypass Switch", "AINLMUX"}, | |
809 | {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, | |
810 | ||
811 | /* SPKMIX */ | |
812 | {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, | |
813 | {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, | |
814 | {"SPKMIX", "SPKMIX LADC Bypass Switch", "AINLMUX"}, | |
815 | {"SPKMIX", "SPKMIX RADC Bypass Switch", "AINRMUX"}, | |
816 | {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, | |
817 | {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, | |
818 | {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, | |
819 | {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, | |
820 | ||
821 | /* LONMIX */ | |
822 | {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, | |
823 | {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, | |
824 | {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, | |
825 | ||
826 | /* LOPMIX */ | |
827 | {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, | |
828 | {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, | |
829 | {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, | |
830 | ||
831 | /* OUT3MIX */ | |
832 | {"OUT3MIX", "OUT3MIX LIN4RXN Bypass Switch", "LIN4RXN"}, | |
833 | {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, | |
834 | ||
835 | /* OUT4MIX */ | |
836 | {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, | |
837 | {"OUT4MIX", "OUT4MIX RIN4RXP Bypass Switch", "RIN4RXP"}, | |
838 | ||
839 | /* RONMIX */ | |
840 | {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, | |
841 | {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, | |
842 | {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, | |
843 | ||
844 | /* ROPMIX */ | |
845 | {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, | |
846 | {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, | |
847 | {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, | |
848 | ||
849 | /* Out Mixer PGAs */ | |
850 | {"LOPGA", NULL, "LOMIX"}, | |
851 | {"ROPGA", NULL, "ROMIX"}, | |
852 | ||
853 | {"LOUT PGA", NULL, "LOMIX"}, | |
854 | {"ROUT PGA", NULL, "ROMIX"}, | |
855 | ||
856 | /* Output Pins */ | |
857 | {"LON", NULL, "LONMIX"}, | |
858 | {"LOP", NULL, "LOPMIX"}, | |
859 | {"OUT", NULL, "OUT3MIX"}, | |
860 | {"LOUT", NULL, "LOUT PGA"}, | |
861 | {"SPKN", NULL, "SPKMIX"}, | |
862 | {"ROUT", NULL, "ROUT PGA"}, | |
863 | {"OUT4", NULL, "OUT4MIX"}, | |
864 | {"ROP", NULL, "ROPMIX"}, | |
865 | {"RON", NULL, "RONMIX"}, | |
866 | }; | |
867 | ||
868 | /* PLL divisors */ | |
869 | struct _pll_div { | |
870 | u32 div2; | |
871 | u32 n; | |
872 | u32 k; | |
873 | }; | |
874 | ||
875 | /* The size in bits of the pll divide multiplied by 10 | |
876 | * to allow rounding later */ | |
877 | #define FIXED_PLL_SIZE ((1 << 16) * 10) | |
878 | ||
879 | static void pll_factors(struct _pll_div *pll_div, unsigned int target, | |
880 | unsigned int source) | |
881 | { | |
882 | u64 Kpart; | |
883 | unsigned int K, Ndiv, Nmod; | |
884 | ||
885 | ||
886 | Ndiv = target / source; | |
887 | if (Ndiv < 6) { | |
888 | source >>= 1; | |
889 | pll_div->div2 = 1; | |
890 | Ndiv = target / source; | |
891 | } else | |
892 | pll_div->div2 = 0; | |
893 | ||
894 | if ((Ndiv < 6) || (Ndiv > 12)) | |
895 | printk(KERN_WARNING | |
896 | "WM8991 N value outwith recommended range! N = %d\n", Ndiv); | |
897 | ||
898 | pll_div->n = Ndiv; | |
899 | Nmod = target % source; | |
900 | Kpart = FIXED_PLL_SIZE * (long long)Nmod; | |
901 | ||
902 | do_div(Kpart, source); | |
903 | ||
904 | K = Kpart & 0xFFFFFFFF; | |
905 | ||
906 | /* Check if we need to round */ | |
907 | if ((K % 10) >= 5) | |
908 | K += 5; | |
909 | ||
910 | /* Move down to proper range now rounding is done */ | |
911 | K /= 10; | |
912 | ||
913 | pll_div->k = K; | |
914 | } | |
915 | ||
916 | static int wm8991_set_dai_pll(struct snd_soc_dai *codec_dai, | |
917 | int pll_id, int src, unsigned int freq_in, unsigned int freq_out) | |
918 | { | |
919 | u16 reg; | |
920 | struct snd_soc_codec *codec = codec_dai->codec; | |
921 | struct _pll_div pll_div; | |
922 | ||
923 | if (freq_in && freq_out) { | |
924 | pll_factors(&pll_div, freq_out * 4, freq_in); | |
925 | ||
926 | /* Turn on PLL */ | |
927 | reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2); | |
928 | reg |= WM8991_PLL_ENA; | |
929 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg); | |
930 | ||
931 | /* sysclk comes from PLL */ | |
932 | reg = snd_soc_read(codec, WM8991_CLOCKING_2); | |
933 | snd_soc_write(codec, WM8991_CLOCKING_2, reg | WM8991_SYSCLK_SRC); | |
934 | ||
25985edc | 935 | /* set up N , fractional mode and pre-divisor if necessary */ |
203db220 DP |
936 | snd_soc_write(codec, WM8991_PLL1, pll_div.n | WM8991_SDM | |
937 | (pll_div.div2 ? WM8991_PRESCALE : 0)); | |
938 | snd_soc_write(codec, WM8991_PLL2, (u8)(pll_div.k>>8)); | |
939 | snd_soc_write(codec, WM8991_PLL3, (u8)(pll_div.k & 0xFF)); | |
940 | } else { | |
941 | /* Turn on PLL */ | |
942 | reg = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_2); | |
943 | reg &= ~WM8991_PLL_ENA; | |
944 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_2, reg); | |
945 | } | |
946 | return 0; | |
947 | } | |
948 | ||
949 | /* | |
950 | * Set's ADC and Voice DAC format. | |
951 | */ | |
952 | static int wm8991_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
953 | unsigned int fmt) | |
954 | { | |
955 | struct snd_soc_codec *codec = codec_dai->codec; | |
956 | u16 audio1, audio3; | |
957 | ||
958 | audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1); | |
959 | audio3 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_3); | |
960 | ||
961 | /* set master/slave audio interface */ | |
962 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
963 | case SND_SOC_DAIFMT_CBS_CFS: | |
964 | audio3 &= ~WM8991_AIF_MSTR1; | |
965 | break; | |
966 | case SND_SOC_DAIFMT_CBM_CFM: | |
967 | audio3 |= WM8991_AIF_MSTR1; | |
968 | break; | |
969 | default: | |
970 | return -EINVAL; | |
971 | } | |
972 | ||
973 | audio1 &= ~WM8991_AIF_FMT_MASK; | |
974 | ||
975 | /* interface format */ | |
976 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
977 | case SND_SOC_DAIFMT_I2S: | |
978 | audio1 |= WM8991_AIF_TMF_I2S; | |
979 | audio1 &= ~WM8991_AIF_LRCLK_INV; | |
980 | break; | |
981 | case SND_SOC_DAIFMT_RIGHT_J: | |
982 | audio1 |= WM8991_AIF_TMF_RIGHTJ; | |
983 | audio1 &= ~WM8991_AIF_LRCLK_INV; | |
984 | break; | |
985 | case SND_SOC_DAIFMT_LEFT_J: | |
986 | audio1 |= WM8991_AIF_TMF_LEFTJ; | |
987 | audio1 &= ~WM8991_AIF_LRCLK_INV; | |
988 | break; | |
989 | case SND_SOC_DAIFMT_DSP_A: | |
990 | audio1 |= WM8991_AIF_TMF_DSP; | |
991 | audio1 &= ~WM8991_AIF_LRCLK_INV; | |
992 | break; | |
993 | case SND_SOC_DAIFMT_DSP_B: | |
994 | audio1 |= WM8991_AIF_TMF_DSP | WM8991_AIF_LRCLK_INV; | |
995 | break; | |
996 | default: | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
1000 | snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1); | |
1001 | snd_soc_write(codec, WM8991_AUDIO_INTERFACE_3, audio3); | |
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static int wm8991_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |
1006 | int div_id, int div) | |
1007 | { | |
1008 | struct snd_soc_codec *codec = codec_dai->codec; | |
1009 | u16 reg; | |
1010 | ||
1011 | switch (div_id) { | |
1012 | case WM8991_MCLK_DIV: | |
1013 | reg = snd_soc_read(codec, WM8991_CLOCKING_2) & | |
1014 | ~WM8991_MCLK_DIV_MASK; | |
1015 | snd_soc_write(codec, WM8991_CLOCKING_2, reg | div); | |
1016 | break; | |
1017 | case WM8991_DACCLK_DIV: | |
1018 | reg = snd_soc_read(codec, WM8991_CLOCKING_2) & | |
1019 | ~WM8991_DAC_CLKDIV_MASK; | |
1020 | snd_soc_write(codec, WM8991_CLOCKING_2, reg | div); | |
1021 | break; | |
1022 | case WM8991_ADCCLK_DIV: | |
1023 | reg = snd_soc_read(codec, WM8991_CLOCKING_2) & | |
1024 | ~WM8991_ADC_CLKDIV_MASK; | |
1025 | snd_soc_write(codec, WM8991_CLOCKING_2, reg | div); | |
1026 | break; | |
1027 | case WM8991_BCLK_DIV: | |
1028 | reg = snd_soc_read(codec, WM8991_CLOCKING_1) & | |
1029 | ~WM8991_BCLK_DIV_MASK; | |
1030 | snd_soc_write(codec, WM8991_CLOCKING_1, reg | div); | |
1031 | break; | |
1032 | default: | |
1033 | return -EINVAL; | |
1034 | } | |
1035 | ||
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | /* | |
1040 | * Set PCM DAI bit size and sample rate. | |
1041 | */ | |
1042 | static int wm8991_hw_params(struct snd_pcm_substream *substream, | |
1043 | struct snd_pcm_hw_params *params, | |
1044 | struct snd_soc_dai *dai) | |
1045 | { | |
1046 | struct snd_soc_codec *codec = dai->codec; | |
1047 | u16 audio1 = snd_soc_read(codec, WM8991_AUDIO_INTERFACE_1); | |
1048 | ||
1049 | audio1 &= ~WM8991_AIF_WL_MASK; | |
1050 | /* bit size */ | |
20a77bbd MB |
1051 | switch (params_width(params)) { |
1052 | case 16: | |
203db220 | 1053 | break; |
20a77bbd | 1054 | case 20: |
203db220 DP |
1055 | audio1 |= WM8991_AIF_WL_20BITS; |
1056 | break; | |
20a77bbd | 1057 | case 24: |
203db220 DP |
1058 | audio1 |= WM8991_AIF_WL_24BITS; |
1059 | break; | |
20a77bbd | 1060 | case 32: |
203db220 DP |
1061 | audio1 |= WM8991_AIF_WL_32BITS; |
1062 | break; | |
1063 | } | |
1064 | ||
1065 | snd_soc_write(codec, WM8991_AUDIO_INTERFACE_1, audio1); | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static int wm8991_mute(struct snd_soc_dai *dai, int mute) | |
1070 | { | |
1071 | struct snd_soc_codec *codec = dai->codec; | |
1072 | u16 val; | |
1073 | ||
1074 | val = snd_soc_read(codec, WM8991_DAC_CTRL) & ~WM8991_DAC_MUTE; | |
1075 | if (mute) | |
1076 | snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); | |
1077 | else | |
1078 | snd_soc_write(codec, WM8991_DAC_CTRL, val); | |
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | static int wm8991_set_bias_level(struct snd_soc_codec *codec, | |
1083 | enum snd_soc_bias_level level) | |
1084 | { | |
a86652e5 | 1085 | struct wm8991_priv *wm8991 = snd_soc_codec_get_drvdata(codec); |
203db220 DP |
1086 | u16 val; |
1087 | ||
1088 | switch (level) { | |
1089 | case SND_SOC_BIAS_ON: | |
1090 | break; | |
1091 | ||
1092 | case SND_SOC_BIAS_PREPARE: | |
1093 | /* VMID=2*50k */ | |
1094 | val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) & | |
1095 | ~WM8991_VMID_MODE_MASK; | |
1096 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x2); | |
1097 | break; | |
1098 | ||
1099 | case SND_SOC_BIAS_STANDBY: | |
bfdd20a4 | 1100 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { |
a86652e5 | 1101 | regcache_sync(wm8991->regmap); |
203db220 DP |
1102 | /* Enable all output discharge bits */ |
1103 | snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE | | |
1104 | WM8991_DIS_RLINE | WM8991_DIS_OUT3 | | |
1105 | WM8991_DIS_OUT4 | WM8991_DIS_LOUT | | |
1106 | WM8991_DIS_ROUT); | |
1107 | ||
1108 | /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ | |
1109 | snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | | |
1110 | WM8991_BUFDCOPEN | WM8991_POBCTRL | | |
1111 | WM8991_VMIDTOG); | |
1112 | ||
1113 | /* Delay to allow output caps to discharge */ | |
1114 | msleep(300); | |
1115 | ||
1116 | /* Disable VMIDTOG */ | |
1117 | snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | | |
1118 | WM8991_BUFDCOPEN | WM8991_POBCTRL); | |
1119 | ||
1120 | /* disable all output discharge bits */ | |
1121 | snd_soc_write(codec, WM8991_ANTIPOP1, 0); | |
1122 | ||
1123 | /* Enable outputs */ | |
1124 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1b00); | |
1125 | ||
1126 | msleep(50); | |
1127 | ||
1128 | /* Enable VMID at 2x50k */ | |
1129 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f02); | |
1130 | ||
1131 | msleep(100); | |
1132 | ||
1133 | /* Enable VREF */ | |
1134 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03); | |
1135 | ||
1136 | msleep(600); | |
1137 | ||
1138 | /* Enable BUFIOEN */ | |
1139 | snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | | |
1140 | WM8991_BUFDCOPEN | WM8991_POBCTRL | | |
1141 | WM8991_BUFIOEN); | |
1142 | ||
1143 | /* Disable outputs */ | |
1144 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x3); | |
1145 | ||
1146 | /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ | |
1147 | snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_BUFIOEN); | |
1148 | } | |
1149 | ||
1150 | /* VMID=2*250k */ | |
1151 | val = snd_soc_read(codec, WM8991_POWER_MANAGEMENT_1) & | |
1152 | ~WM8991_VMID_MODE_MASK; | |
1153 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, val | 0x4); | |
1154 | break; | |
1155 | ||
1156 | case SND_SOC_BIAS_OFF: | |
1157 | /* Enable POBCTRL and SOFT_ST */ | |
1158 | snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | | |
1159 | WM8991_POBCTRL | WM8991_BUFIOEN); | |
1160 | ||
1161 | /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ | |
1162 | snd_soc_write(codec, WM8991_ANTIPOP2, WM8991_SOFTST | | |
1163 | WM8991_BUFDCOPEN | WM8991_POBCTRL | | |
1164 | WM8991_BUFIOEN); | |
1165 | ||
1166 | /* mute DAC */ | |
1167 | val = snd_soc_read(codec, WM8991_DAC_CTRL); | |
1168 | snd_soc_write(codec, WM8991_DAC_CTRL, val | WM8991_DAC_MUTE); | |
1169 | ||
1170 | /* Enable any disabled outputs */ | |
1171 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f03); | |
1172 | ||
1173 | /* Disable VMID */ | |
1174 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x1f01); | |
1175 | ||
1176 | msleep(300); | |
1177 | ||
1178 | /* Enable all output discharge bits */ | |
1179 | snd_soc_write(codec, WM8991_ANTIPOP1, WM8991_DIS_LLINE | | |
1180 | WM8991_DIS_RLINE | WM8991_DIS_OUT3 | | |
1181 | WM8991_DIS_OUT4 | WM8991_DIS_LOUT | | |
1182 | WM8991_DIS_ROUT); | |
1183 | ||
1184 | /* Disable VREF */ | |
1185 | snd_soc_write(codec, WM8991_POWER_MANAGEMENT_1, 0x0); | |
1186 | ||
1187 | /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ | |
1188 | snd_soc_write(codec, WM8991_ANTIPOP2, 0x0); | |
a86652e5 | 1189 | regcache_mark_dirty(wm8991->regmap); |
203db220 DP |
1190 | break; |
1191 | } | |
1192 | ||
203db220 DP |
1193 | return 0; |
1194 | } | |
1195 | ||
203db220 DP |
1196 | #define WM8991_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ |
1197 | SNDRV_PCM_FMTBIT_S24_LE) | |
1198 | ||
85e7652d | 1199 | static const struct snd_soc_dai_ops wm8991_ops = { |
203db220 DP |
1200 | .hw_params = wm8991_hw_params, |
1201 | .digital_mute = wm8991_mute, | |
1202 | .set_fmt = wm8991_set_dai_fmt, | |
1203 | .set_clkdiv = wm8991_set_dai_clkdiv, | |
1204 | .set_pll = wm8991_set_dai_pll | |
1205 | }; | |
1206 | ||
1207 | /* | |
1208 | * The WM8991 supports 2 different and mutually exclusive DAI | |
1209 | * configurations. | |
1210 | * | |
1211 | * 1. ADC/DAC on Primary Interface | |
1212 | * 2. ADC on Primary Interface/DAC on secondary | |
1213 | */ | |
1214 | static struct snd_soc_dai_driver wm8991_dai = { | |
1215 | /* ADC/DAC on primary */ | |
1216 | .name = "wm8991", | |
1217 | .id = 1, | |
1218 | .playback = { | |
1219 | .stream_name = "Playback", | |
1220 | .channels_min = 1, | |
1221 | .channels_max = 2, | |
1222 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1223 | .formats = WM8991_FORMATS | |
1224 | }, | |
1225 | .capture = { | |
1226 | .stream_name = "Capture", | |
1227 | .channels_min = 1, | |
1228 | .channels_max = 2, | |
1229 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1230 | .formats = WM8991_FORMATS | |
1231 | }, | |
1232 | .ops = &wm8991_ops | |
1233 | }; | |
1234 | ||
1235 | static struct snd_soc_codec_driver soc_codec_dev_wm8991 = { | |
203db220 | 1236 | .set_bias_level = wm8991_set_bias_level, |
497b900f LPC |
1237 | .suspend_bias_off = true, |
1238 | ||
89824995 MB |
1239 | .controls = wm8991_snd_controls, |
1240 | .num_controls = ARRAY_SIZE(wm8991_snd_controls), | |
1241 | .dapm_widgets = wm8991_dapm_widgets, | |
1242 | .num_dapm_widgets = ARRAY_SIZE(wm8991_dapm_widgets), | |
1243 | .dapm_routes = wm8991_dapm_routes, | |
1244 | .num_dapm_routes = ARRAY_SIZE(wm8991_dapm_routes), | |
a86652e5 MB |
1245 | }; |
1246 | ||
1247 | static const struct regmap_config wm8991_regmap = { | |
1248 | .reg_bits = 8, | |
1249 | .val_bits = 16, | |
1250 | ||
1251 | .max_register = WM8991_PLL3, | |
1252 | .volatile_reg = wm8991_volatile, | |
1253 | .reg_defaults = wm8991_reg_defaults, | |
1254 | .num_reg_defaults = ARRAY_SIZE(wm8991_reg_defaults), | |
1255 | .cache_type = REGCACHE_RBTREE, | |
203db220 DP |
1256 | }; |
1257 | ||
7a79e94e BP |
1258 | static int wm8991_i2c_probe(struct i2c_client *i2c, |
1259 | const struct i2c_device_id *id) | |
203db220 DP |
1260 | { |
1261 | struct wm8991_priv *wm8991; | |
a0a05916 | 1262 | unsigned int val; |
203db220 DP |
1263 | int ret; |
1264 | ||
046d4f02 | 1265 | wm8991 = devm_kzalloc(&i2c->dev, sizeof(*wm8991), GFP_KERNEL); |
203db220 DP |
1266 | if (!wm8991) |
1267 | return -ENOMEM; | |
1268 | ||
a86652e5 MB |
1269 | wm8991->regmap = devm_regmap_init_i2c(i2c, &wm8991_regmap); |
1270 | if (IS_ERR(wm8991->regmap)) | |
1271 | return PTR_ERR(wm8991->regmap); | |
1272 | ||
203db220 DP |
1273 | i2c_set_clientdata(i2c, wm8991); |
1274 | ||
a0a05916 MB |
1275 | ret = regmap_read(wm8991->regmap, WM8991_RESET, &val); |
1276 | if (ret != 0) { | |
1277 | dev_err(&i2c->dev, "Failed to read device ID: %d\n", ret); | |
1278 | return ret; | |
1279 | } | |
1280 | if (val != 0x8991) { | |
1281 | dev_err(&i2c->dev, "Device with ID %x is not a WM8991\n", val); | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
e4634804 MB |
1285 | ret = regmap_write(wm8991->regmap, WM8991_RESET, 0); |
1286 | if (ret < 0) { | |
1287 | dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); | |
1288 | return ret; | |
1289 | } | |
1290 | ||
1291 | regmap_update_bits(wm8991->regmap, WM8991_AUDIO_INTERFACE_4, | |
1292 | WM8991_ALRCGPIO1, WM8991_ALRCGPIO1); | |
1293 | ||
1294 | regmap_update_bits(wm8991->regmap, WM8991_GPIO1_GPIO2, | |
1295 | WM8991_GPIO1_SEL_MASK, 1); | |
1296 | ||
1297 | regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_1, | |
1298 | WM8991_VREF_ENA | WM8991_VMID_MODE_MASK, | |
1299 | WM8991_VREF_ENA | WM8991_VMID_MODE_MASK); | |
1300 | ||
1301 | regmap_update_bits(wm8991->regmap, WM8991_POWER_MANAGEMENT_2, | |
1302 | WM8991_OPCLK_ENA, WM8991_OPCLK_ENA); | |
1303 | ||
1304 | regmap_write(wm8991->regmap, WM8991_DAC_CTRL, 0); | |
1305 | regmap_write(wm8991->regmap, WM8991_LEFT_OUTPUT_VOLUME, | |
1306 | 0x50 | (1<<8)); | |
1307 | regmap_write(wm8991->regmap, WM8991_RIGHT_OUTPUT_VOLUME, | |
1308 | 0x50 | (1<<8)); | |
1309 | ||
203db220 DP |
1310 | ret = snd_soc_register_codec(&i2c->dev, |
1311 | &soc_codec_dev_wm8991, &wm8991_dai, 1); | |
046d4f02 | 1312 | |
203db220 DP |
1313 | return ret; |
1314 | } | |
1315 | ||
7a79e94e | 1316 | static int wm8991_i2c_remove(struct i2c_client *client) |
203db220 DP |
1317 | { |
1318 | snd_soc_unregister_codec(&client->dev); | |
046d4f02 | 1319 | |
203db220 DP |
1320 | return 0; |
1321 | } | |
1322 | ||
1323 | static const struct i2c_device_id wm8991_i2c_id[] = { | |
1324 | { "wm8991", 0 }, | |
1325 | { } | |
1326 | }; | |
1327 | MODULE_DEVICE_TABLE(i2c, wm8991_i2c_id); | |
1328 | ||
1329 | static struct i2c_driver wm8991_i2c_driver = { | |
1330 | .driver = { | |
1331 | .name = "wm8991", | |
203db220 DP |
1332 | }, |
1333 | .probe = wm8991_i2c_probe, | |
7a79e94e | 1334 | .remove = wm8991_i2c_remove, |
203db220 DP |
1335 | .id_table = wm8991_i2c_id, |
1336 | }; | |
1337 | ||
38ece8db | 1338 | module_i2c_driver(wm8991_i2c_driver); |
203db220 DP |
1339 | |
1340 | MODULE_DESCRIPTION("ASoC WM8991 driver"); | |
1341 | MODULE_AUTHOR("Graeme Gregory"); | |
1342 | MODULE_LICENSE("GPL"); |