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ASoC: wm8994: Ensure lambda is zeroed for WM8994
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
d1a0a299 19#include <linux/gcd.h>
9e6e96a1
MB		 20#include <linux/i2c.h>
21#include <linux/platform_device.h>
39fb51a1 22#include <linux/pm_runtime.h>
9e6e96a1 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
9e6e96a1 25#include <sound/core.h>
821edd2f 26#include <sound/jack.h>
9e6e96a1
MB		 27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
9e6e96a1
MB		 30#include <sound/initval.h>
31#include <sound/tlv.h>
2bbb5d66 32#include <trace/events/asoc.h>
9e6e96a1
MB		 33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
af6b6fe4
MB		 42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
9e6e96a1
MB		 47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
bfd37bb5
MB		 50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
9e6e96a1
MB		 83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
af6b6fe4 95static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
604533de
MB		 98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 100};
101
af6b6fe4
MB		 102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
e9d9a968
MB		 105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 107};
108
b00adf76
MB		 109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 112 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 113 int best, i, sysclk, val;
114 bool idle;
af6b6fe4
MB		 115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
b00adf76
MB		 118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
d9dd4ada
MB		 126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
cd1707a9 129 } else if (wm8994->jackdet) {
af6b6fe4
MB		 130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
b00adf76 137 best = 0;
af6b6fe4
MB		 138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
b00adf76 140 continue;
af6b6fe4
MB		 141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
b00adf76 143 best = i;
af6b6fe4 144 else if (rates[best].idle != idle)
b00adf76
MB		 145 best = i;
146 }
147
af6b6fe4
MB		 148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 150
3a334ada
MB		 151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
b00adf76
MB		 155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
9e6e96a1
MB		 160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
b2c812e2 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
5e5e2bef 203
9e6e96a1
MB		 204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
b2c812e2 215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 216 int change, new;
9e6e96a1
MB		 217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
9e6e96a1 231 return 0;
b00adf76 232 }
9e6e96a1
MB		 233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
04f45c49
AL		 239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 243
b00adf76
MB		 244 wm8958_micd_set_rate(codec);
245
9e6e96a1
MB		 246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262}
263
264static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266};
267
268static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270
146fd574
UK		 271static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273};
274
275static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277
278static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280
281static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283
9e6e96a1
MB		 284static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 289static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 290static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 291
292#define WM8994_DRC_SWITCH(xname, reg, shift) \
293{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
294 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
295 .put = wm8994_put_drc_sw, \
296 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
297
298static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
300{
301 struct soc_mixer_control *mc =
302 (struct soc_mixer_control *)kcontrol->private_value;
303 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
304 int mask, ret;
305
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
308 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
309 WM8994_AIF1ADC1R_DRC_ENA_MASK;
310 else
311 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
312
313 ret = snd_soc_read(codec, mc->reg);
314 if (ret < 0)
315 return ret;
316 if (ret & mask)
317 return -EINVAL;
318
319 return snd_soc_put_volsw(kcontrol, ucontrol);
320}
321
9e6e96a1
MB		 322static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
323{
b2c812e2 324 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 325 struct wm8994 *control = wm8994->wm8994;
326 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 327 int base = wm8994_drc_base[drc];
328 int cfg = wm8994->drc_cfg[drc];
329 int save, i;
330
331 /* Save any enables; the configuration should clear them. */
332 save = snd_soc_read(codec, base);
333 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA;
335
336 for (i = 0; i < WM8994_DRC_REGS; i++)
337 snd_soc_update_bits(codec, base + i, 0xffff,
338 pdata->drc_cfgs[cfg].regs[i]);
339
340 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
341 WM8994_AIF1ADC1L_DRC_ENA |
342 WM8994_AIF1ADC1R_DRC_ENA, save);
343}
344
345/* Icky as hell but saves code duplication */
346static int wm8994_get_drc(const char *name)
347{
348 if (strcmp(name, "AIF1DRC1 Mode") == 0)
349 return 0;
350 if (strcmp(name, "AIF1DRC2 Mode") == 0)
351 return 1;
352 if (strcmp(name, "AIF2DRC Mode") == 0)
353 return 2;
354 return -EINVAL;
355}
356
357static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
358 struct snd_ctl_elem_value *ucontrol)
359{
360 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 361 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 362 struct wm8994 *control = wm8994->wm8994;
363 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.integer.value[0];
366
367 if (drc < 0)
368 return drc;
369
370 if (value >= pdata->num_drc_cfgs)
371 return -EINVAL;
372
373 wm8994->drc_cfg[drc] = value;
374
375 wm8994_set_drc(codec, drc);
376
377 return 0;
378}
379
380static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382{
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 385 int drc = wm8994_get_drc(kcontrol->id.name);
386
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 438 * current configuration.
9e6e96a1
MB		 439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448}
449
450/* Icky as hell but saves code duplication */
451static int wm8994_get_retune_mobile_block(const char *name)
452{
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460}
461
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495}
496
96b101ef 497static const char *aif_chan_src_text[] = {
f554885f
MB		 498 "Left", "Right"
499};
500
96b101ef
MB		 501static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
f554885f 513static const struct soc_enum aif1dacl_src =
96b101ef 514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 515
516static const struct soc_enum aif1dacr_src =
96b101ef 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 518
519static const struct soc_enum aif2dacl_src =
96b101ef 520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 521
522static const struct soc_enum aif2dacr_src =
96b101ef 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 524
154b26aa
MB		 525static const char *osr_text[] = {
526 "Low Power", "High Performance",
527};
528
529static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
9e6e96a1
MB		 535static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
96b101ef
MB		 546SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 548SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 550
f554885f
MB		 551SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 553SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 555
9e6e96a1
MB		 556SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
146fd574
UK		 593SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
154b26aa
MB		 602SOC_ENUM("ADC OSR", adc_osr),
603SOC_ENUM("DAC OSR", dac_osr),
604
9e6e96a1
MB		 605SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
458350b3 627SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 628 8, 1, 0),
629SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
458350b3 633SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 634 10, 15, 0, wm8994_3d_tlv),
458350b3 635SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 636 8, 1, 0),
637};
638
639static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672};
673
45a690f6
MB		 674static const struct snd_kcontrol_new wm8994_drc_controls[] = {
675SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
676 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
677 WM8994_AIF1ADC1R_DRC_ENA),
678SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
679 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
680 WM8994_AIF1ADC2R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
682 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
683 WM8994_AIF2ADCR_DRC_ENA),
684};
685
1ddc07d0
MB		 686static const char *wm8958_ng_text[] = {
687 "30ms", "125ms", "250ms", "500ms",
688};
689
690static const struct soc_enum wm8958_aif1dac1_ng_hold =
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
692 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
693
694static const struct soc_enum wm8958_aif1dac2_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
696 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698static const struct soc_enum wm8958_aif2dac_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
700 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
701
c4431df0
MB		 702static const struct snd_kcontrol_new wm8958_snd_controls[] = {
703SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 704
705SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
707SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
708SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
710 7, 1, ng_tlv),
711
712SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
714SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
715SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
720 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
721SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
722SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
724 7, 1, ng_tlv),
c4431df0
MB		 725};
726
81204c84
MB		 727static const struct snd_kcontrol_new wm1811_snd_controls[] = {
728SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
729 mixin_boost_tlv),
730SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
731 mixin_boost_tlv),
732};
733
af6b6fe4
MB		 734/* We run all mode setting through a function to enforce audio mode */
735static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
736{
737 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
738
78b76dbe 739 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
MB		 740 return;
741
af6b6fe4
MB		 742 if (wm8994->active_refcount)
743 mode = WM1811_JACKDET_MODE_AUDIO;
744
4752a887 745 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 746 return;
747
4752a887 748 wm8994->jackdet_mode = mode;
1defde2a 749
4752a887
MB		 750 /* Always use audio mode to detect while the system is active */
751 if (mode != WM1811_JACKDET_MODE_NONE)
752 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 753
4752a887
MB		 754 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
755 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 756}
757
758static void active_reference(struct snd_soc_codec *codec)
759{
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762 mutex_lock(&wm8994->accdet_lock);
763
764 wm8994->active_refcount++;
765
766 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
767 wm8994->active_refcount);
768
1defde2a
MB		 769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 771
772 mutex_unlock(&wm8994->accdet_lock);
773}
774
775static void active_dereference(struct snd_soc_codec *codec)
776{
777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778 u16 mode;
779
780 mutex_lock(&wm8994->accdet_lock);
781
782 wm8994->active_refcount--;
783
784 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
785 wm8994->active_refcount);
786
787 if (wm8994->active_refcount == 0) {
788 /* Go into appropriate detection only mode */
1defde2a
MB		 789 if (wm8994->jack_mic || wm8994->mic_detecting)
790 mode = WM1811_JACKDET_MODE_MIC;
791 else
792 mode = WM1811_JACKDET_MODE_JACK;
793
794 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 795 }
796
797 mutex_unlock(&wm8994->accdet_lock);
798}
799
9e6e96a1
MB		 800static int clk_sys_event(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802{
803 struct snd_soc_codec *codec = w->codec;
99af79df 804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 return configure_clock(codec);
809
99af79df
MB		 810 case SND_SOC_DAPM_POST_PMU:
811 /*
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
817 */
818 if (wm8994->jackdet && !wm8994->clk_has_run) {
819 schedule_delayed_work(&wm8994->jackdet_bootstrap,
820 msecs_to_jiffies(1000));
821 wm8994->clk_has_run = true;
822 }
823 break;
824
9e6e96a1
MB		 825 case SND_SOC_DAPM_POST_PMD:
826 configure_clock(codec);
827 break;
828 }
829
830 return 0;
831}
832
4b7ed83a
MB		 833static void vmid_reference(struct snd_soc_codec *codec)
834{
835 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
836
db966f8a
MB		 837 pm_runtime_get_sync(codec->dev);
838
4b7ed83a
MB		 839 wm8994->vmid_refcount++;
840
841 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
842 wm8994->vmid_refcount);
843
844 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 845 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 846 WM8994_LINEOUT1_DISCH |
22f8d055 847 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 848
f7085641
MB		 849 wm_hubs_vmid_ena(codec);
850
22f8d055
MB		 851 switch (wm8994->vmid_mode) {
852 default:
cbd71f30 853 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 854 case WM8994_VMID_NORMAL:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
857 WM8994_BIAS_SRC |
858 WM8994_VMID_DISCH |
859 WM8994_STARTUP_BIAS_ENA |
860 WM8994_VMID_BUF_ENA |
861 WM8994_VMID_RAMP_MASK,
862 WM8994_BIAS_SRC |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
a3a1d9d2 865 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 866
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
869 WM8994_BIAS_ENA |
870 WM8994_VMID_SEL_MASK,
871 WM8994_BIAS_ENA | 0x2);
872
a3a1d9d2 873 msleep(300);
22f8d055
MB		 874
875 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
876 WM8994_VMID_RAMP_MASK |
877 WM8994_BIAS_SRC,
878 0);
879 break;
cc6d5a8c 880
22f8d055
MB		 881 case WM8994_VMID_FORCE:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_BIAS_SRC |
885 WM8994_VMID_DISCH |
886 WM8994_STARTUP_BIAS_ENA |
887 WM8994_VMID_BUF_ENA |
888 WM8994_VMID_RAMP_MASK,
889 WM8994_BIAS_SRC |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 (0x2 << WM8994_VMID_RAMP_SHIFT));
893
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
896 WM8994_BIAS_ENA |
897 WM8994_VMID_SEL_MASK,
898 WM8994_BIAS_ENA | 0x2);
899
900 msleep(400);
901
902 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
903 WM8994_VMID_RAMP_MASK |
904 WM8994_BIAS_SRC,
905 0);
906 break;
907 }
4b7ed83a
MB		 908 }
909}
910
911static void vmid_dereference(struct snd_soc_codec *codec)
912{
913 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
914
915 wm8994->vmid_refcount--;
916
917 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
918 wm8994->vmid_refcount);
919
920 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 921 if (wm8994->hubs.lineout1_se)
922 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
923 WM8994_LINEOUT1N_ENA |
924 WM8994_LINEOUT1P_ENA,
925 WM8994_LINEOUT1N_ENA |
926 WM8994_LINEOUT1P_ENA);
927
928 if (wm8994->hubs.lineout2_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT2N_ENA |
931 WM8994_LINEOUT2P_ENA,
932 WM8994_LINEOUT2N_ENA |
933 WM8994_LINEOUT2P_ENA);
934
935 /* Start discharging VMID */
4b7ed83a
MB		 936 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
937 WM8994_BIAS_SRC |
22f8d055 938 WM8994_VMID_DISCH,
4b7ed83a 939 WM8994_BIAS_SRC |
22f8d055 940 WM8994_VMID_DISCH);
4b7ed83a 941
f95be9d6
MB		 942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
943 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 944
f95be9d6 945 msleep(400);
e85b26ce 946
22f8d055 947 /* Active discharge */
4b7ed83a
MB		 948 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
949 WM8994_LINEOUT1_DISCH |
950 WM8994_LINEOUT2_DISCH,
951 WM8994_LINEOUT1_DISCH |
952 WM8994_LINEOUT2_DISCH);
953
22f8d055
MB		 954 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
955 WM8994_LINEOUT1N_ENA |
956 WM8994_LINEOUT1P_ENA |
957 WM8994_LINEOUT2N_ENA |
958 WM8994_LINEOUT2P_ENA, 0);
959
4b7ed83a
MB		 960 /* Switch off startup biases */
961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
962 WM8994_BIAS_SRC |
963 WM8994_STARTUP_BIAS_ENA |
964 WM8994_VMID_BUF_ENA |
965 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 966
967 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 968 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 969 }
db966f8a
MB		 970
971 pm_runtime_put(codec->dev);
4b7ed83a
MB		 972}
973
974static int vmid_event(struct snd_soc_dapm_widget *w,
975 struct snd_kcontrol *kcontrol, int event)
976{
977 struct snd_soc_codec *codec = w->codec;
978
979 switch (event) {
980 case SND_SOC_DAPM_PRE_PMU:
981 vmid_reference(codec);
982 break;
983
984 case SND_SOC_DAPM_POST_PMD:
985 vmid_dereference(codec);
986 break;
987 }
988
989 return 0;
990}
991
c340304d 992static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 993{
9e6e96a1
MB		 994 int source = 0; /* GCC flow analysis can't track enable */
995 int reg, reg_r;
996
c340304d 997 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 998 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
999 switch (reg) {
1000 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1001 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1002 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003 break;
1004 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1005 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1006 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1009 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1010 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 default:
ee839a21 1013 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1014 return false;
9e6e96a1
MB		 1015 }
1016
1017 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1018 if (reg_r != reg) {
ee839a21 1019 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1020 return false;
9e6e96a1
MB		 1021 }
1022
c340304d
MB		 1023 /* Set the source up */
1024 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1025 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1026
c340304d 1027 return true;
9e6e96a1
MB		 1028}
1029
1a38336b
MB		 1030static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1031 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1032{
1033 struct snd_soc_codec *codec = w->codec;
79748cdb 1034 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1a38336b
MB		 1035 struct wm8994 *control = codec->control_data;
1036 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1037 int i;
1a38336b
MB		 1038 int dac;
1039 int adc;
1040 int val;
1041
1042 switch (control->type) {
1043 case WM8994:
1044 case WM8958:
1045 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1046 break;
1047 default:
1048 break;
1049 }
173efa09
DP		 1050
1051 switch (event) {
1052 case SND_SOC_DAPM_PRE_PMU:
79748cdb
MB		 1053 /* Don't enable timeslot 2 if not in use */
1054 if (wm8994->channels[0] <= 2)
1055 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1056
1a38336b
MB		 1057 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1058 if ((val & WM8994_AIF1ADCL_SRC) &&
1059 (val & WM8994_AIF1ADCR_SRC))
1060 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1061 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1062 !(val & WM8994_AIF1ADCR_SRC))
1063 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1064 else
1065 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1066 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1067
1068 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1069 if ((val & WM8994_AIF1DACL_SRC) &&
1070 (val & WM8994_AIF1DACR_SRC))
1071 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1072 else if (!(val & WM8994_AIF1DACL_SRC) &&
1073 !(val & WM8994_AIF1DACR_SRC))
1074 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1075 else
1076 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1077 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1078
1079 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1080 mask, adc);
1081 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1082 mask, dac);
1083 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1084 WM8994_AIF1DSPCLK_ENA |
1085 WM8994_SYSDSPCLK_ENA,
1086 WM8994_AIF1DSPCLK_ENA |
1087 WM8994_SYSDSPCLK_ENA);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1089 WM8994_AIF1ADC1R_ENA |
1090 WM8994_AIF1ADC1L_ENA |
1091 WM8994_AIF1ADC2R_ENA |
1092 WM8994_AIF1ADC2L_ENA);
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1094 WM8994_AIF1DAC1R_ENA |
1095 WM8994_AIF1DAC1L_ENA |
1096 WM8994_AIF1DAC2R_ENA |
1097 WM8994_AIF1DAC2L_ENA);
173efa09 1098 break;
173efa09 1099
bfd37bb5
MB		 1100 case SND_SOC_DAPM_POST_PMU:
1101 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1102 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1103 snd_soc_read(codec,
1104 wm8994_vu_bits[i].reg));
1105 break;
1106
1a38336b
MB		 1107 case SND_SOC_DAPM_PRE_PMD:
1108 case SND_SOC_DAPM_POST_PMD:
1109 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1110 mask, 0);
1111 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1112 mask, 0);
1113
1114 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1115 if (val & WM8994_AIF2DSPCLK_ENA)
1116 val = WM8994_SYSDSPCLK_ENA;
1117 else
1118 val = 0;
1119 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1120 WM8994_SYSDSPCLK_ENA |
1121 WM8994_AIF1DSPCLK_ENA, val);
1122 break;
1123 }
c6b7b570 1124
173efa09
DP		 1125 return 0;
1126}
1127
1a38336b
MB		 1128static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1129 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1130{
1131 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1132 int i;
1a38336b
MB		 1133 int dac;
1134 int adc;
1135 int val;
173efa09
DP		 1136
1137 switch (event) {
1a38336b
MB		 1138 case SND_SOC_DAPM_PRE_PMU:
1139 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1140 if ((val & WM8994_AIF2ADCL_SRC) &&
1141 (val & WM8994_AIF2ADCR_SRC))
1142 adc = WM8994_AIF2ADCR_ENA;
1143 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1144 !(val & WM8994_AIF2ADCR_SRC))
1145 adc = WM8994_AIF2ADCL_ENA;
1146 else
1147 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1148
1149
1150 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1151 if ((val & WM8994_AIF2DACL_SRC) &&
1152 (val & WM8994_AIF2DACR_SRC))
1153 dac = WM8994_AIF2DACR_ENA;
1154 else if (!(val & WM8994_AIF2DACL_SRC) &&
1155 !(val & WM8994_AIF2DACR_SRC))
1156 dac = WM8994_AIF2DACL_ENA;
1157 else
1158 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1159
1160 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1161 WM8994_AIF2ADCL_ENA |
1162 WM8994_AIF2ADCR_ENA, adc);
1163 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1164 WM8994_AIF2DACL_ENA |
1165 WM8994_AIF2DACR_ENA, dac);
1166 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1167 WM8994_AIF2DSPCLK_ENA |
1168 WM8994_SYSDSPCLK_ENA,
1169 WM8994_AIF2DSPCLK_ENA |
1170 WM8994_SYSDSPCLK_ENA);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1172 WM8994_AIF2ADCL_ENA |
1173 WM8994_AIF2ADCR_ENA,
1174 WM8994_AIF2ADCL_ENA |
1175 WM8994_AIF2ADCR_ENA);
1176 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1177 WM8994_AIF2DACL_ENA |
1178 WM8994_AIF2DACR_ENA,
1179 WM8994_AIF2DACL_ENA |
1180 WM8994_AIF2DACR_ENA);
1181 break;
1182
bfd37bb5
MB		 1183 case SND_SOC_DAPM_POST_PMU:
1184 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1185 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1186 snd_soc_read(codec,
1187 wm8994_vu_bits[i].reg));
1188 break;
1189
1a38336b 1190 case SND_SOC_DAPM_PRE_PMD:
173efa09 1191 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1192 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1193 WM8994_AIF2DACL_ENA |
1194 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1195 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1196 WM8994_AIF2ADCL_ENA |
1197 WM8994_AIF2ADCR_ENA, 0);
1198
1199 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1200 if (val & WM8994_AIF1DSPCLK_ENA)
1201 val = WM8994_SYSDSPCLK_ENA;
1202 else
1203 val = 0;
1204 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1205 WM8994_SYSDSPCLK_ENA |
1206 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1207 break;
1208 }
1209
1210 return 0;
1211}
1212
1a38336b
MB		 1213static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1214 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1215{
1216 struct snd_soc_codec *codec = w->codec;
1217 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1218
1219 switch (event) {
1220 case SND_SOC_DAPM_PRE_PMU:
1221 wm8994->aif1clk_enable = 1;
1222 break;
a3cff81a
DP		 1223 case SND_SOC_DAPM_POST_PMD:
1224 wm8994->aif1clk_disable = 1;
1225 break;
173efa09
DP		 1226 }
1227
1228 return 0;
1229}
1230
1a38336b
MB		 1231static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1232 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1233{
1234 struct snd_soc_codec *codec = w->codec;
1235 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1236
1237 switch (event) {
1238 case SND_SOC_DAPM_PRE_PMU:
1239 wm8994->aif2clk_enable = 1;
1240 break;
a3cff81a
DP		 1241 case SND_SOC_DAPM_POST_PMD:
1242 wm8994->aif2clk_disable = 1;
1243 break;
173efa09
DP		 1244 }
1245
1246 return 0;
1247}
1248
1a38336b
MB		 1249static int late_enable_ev(struct snd_soc_dapm_widget *w,
1250 struct snd_kcontrol *kcontrol, int event)
1251{
1252 struct snd_soc_codec *codec = w->codec;
1253 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1254
1255 switch (event) {
1256 case SND_SOC_DAPM_PRE_PMU:
1257 if (wm8994->aif1clk_enable) {
c8fdc1b5 1258 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1259 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1260 WM8994_AIF1CLK_ENA_MASK,
1261 WM8994_AIF1CLK_ENA);
c8fdc1b5 1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1263 wm8994->aif1clk_enable = 0;
1264 }
1265 if (wm8994->aif2clk_enable) {
c8fdc1b5 1266 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1267 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1268 WM8994_AIF2CLK_ENA_MASK,
1269 WM8994_AIF2CLK_ENA);
c8fdc1b5 1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1271 wm8994->aif2clk_enable = 0;
1272 }
1273 break;
1274 }
1275
1276 /* We may also have postponed startup of DSP, handle that. */
1277 wm8958_aif_ev(w, kcontrol, event);
1278
1279 return 0;
1280}
1281
1282static int late_disable_ev(struct snd_soc_dapm_widget *w,
1283 struct snd_kcontrol *kcontrol, int event)
1284{
1285 struct snd_soc_codec *codec = w->codec;
1286 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1287
1288 switch (event) {
1289 case SND_SOC_DAPM_POST_PMD:
1290 if (wm8994->aif1clk_disable) {
c8fdc1b5 1291 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1292 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1293 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1294 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1295 wm8994->aif1clk_disable = 0;
1296 }
1297 if (wm8994->aif2clk_disable) {
c8fdc1b5 1298 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1299 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1300 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1301 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1302 wm8994->aif2clk_disable = 0;
1303 }
1304 break;
1305 }
1306
1307 return 0;
1308}
1309
04d28681
DP		 1310static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1311 struct snd_kcontrol *kcontrol, int event)
1312{
1313 late_enable_ev(w, kcontrol, event);
1314 return 0;
1315}
1316
b462c6e6
DP		 1317static int micbias_ev(struct snd_soc_dapm_widget *w,
1318 struct snd_kcontrol *kcontrol, int event)
1319{
1320 late_enable_ev(w, kcontrol, event);
1321 return 0;
1322}
1323
c52fd021
DP		 1324static int dac_ev(struct snd_soc_dapm_widget *w,
1325 struct snd_kcontrol *kcontrol, int event)
1326{
1327 struct snd_soc_codec *codec = w->codec;
1328 unsigned int mask = 1 << w->shift;
1329
1330 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1331 mask, mask);
1332 return 0;
1333}
1334
9e6e96a1
MB		 1335static const char *adc_mux_text[] = {
1336 "ADC",
1337 "DMIC",
1338};
1339
1340static const struct soc_enum adc_enum =
1341 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1342
1343static const struct snd_kcontrol_new adcl_mux =
1344 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1345
1346static const struct snd_kcontrol_new adcr_mux =
1347 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1348
1349static const struct snd_kcontrol_new left_speaker_mixer[] = {
1350SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1351SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1352SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1353SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1354SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1355};
1356
1357static const struct snd_kcontrol_new right_speaker_mixer[] = {
1358SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1359SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1360SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1361SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1362SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1363};
1364
1365/* Debugging; dump chip status after DAPM transitions */
1366static int post_ev(struct snd_soc_dapm_widget *w,
1367 struct snd_kcontrol *kcontrol, int event)
1368{
1369 struct snd_soc_codec *codec = w->codec;
1370 dev_dbg(codec->dev, "SRC status: %x\n",
1371 snd_soc_read(codec,
1372 WM8994_RATE_STATUS));
1373 return 0;
1374}
1375
1376static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1377SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1378 1, 1, 0),
1379SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1380 0, 1, 0),
1381};
1382
1383static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1384SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1385 1, 1, 0),
1386SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1387 0, 1, 0),
1388};
1389
a3257ba8
MB		 1390static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1391SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1392 1, 1, 0),
1393SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1394 0, 1, 0),
1395};
1396
1397static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1398SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1399 1, 1, 0),
1400SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1401 0, 1, 0),
1402};
1403
9e6e96a1
MB		 1404static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1405SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1406 5, 1, 0),
1407SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1408 4, 1, 0),
1409SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410 2, 1, 0),
1411SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 1, 1, 0),
1413SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 0, 1, 0),
1415};
1416
1417static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1418SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1419 5, 1, 0),
1420SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1421 4, 1, 0),
1422SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423 2, 1, 0),
1424SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 1, 1, 0),
1426SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 0, 1, 0),
1428};
1429
1430#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1431{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1432 .info = snd_soc_info_volsw, \
1433 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1434 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1435
1436static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1437 struct snd_ctl_elem_value *ucontrol)
1438{
9d03545d
JN		 1439 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1440 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1441 struct snd_soc_codec *codec = w->codec;
1442 int ret;
1443
1444 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1445
c340304d 1446 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1447
1448 return ret;
1449}
1450
1451static const struct snd_kcontrol_new dac1l_mix[] = {
1452WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453 5, 1, 0),
1454WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 4, 1, 0),
1456WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457 2, 1, 0),
1458WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 1, 1, 0),
1460WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 0, 1, 0),
1462};
1463
1464static const struct snd_kcontrol_new dac1r_mix[] = {
1465WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466 5, 1, 0),
1467WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 4, 1, 0),
1469WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470 2, 1, 0),
1471WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 1, 1, 0),
1473WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 0, 1, 0),
1475};
1476
1477static const char *sidetone_text[] = {
1478 "ADC/DMIC1", "DMIC2",
1479};
1480
1481static const struct soc_enum sidetone1_enum =
1482 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1483
1484static const struct snd_kcontrol_new sidetone1_mux =
1485 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1486
1487static const struct soc_enum sidetone2_enum =
1488 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1489
1490static const struct snd_kcontrol_new sidetone2_mux =
1491 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1492
1493static const char *aif1dac_text[] = {
1494 "AIF1DACDAT", "AIF3DACDAT",
1495};
1496
1497static const struct soc_enum aif1dac_enum =
1498 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1499
1500static const struct snd_kcontrol_new aif1dac_mux =
1501 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1502
1503static const char *aif2dac_text[] = {
1504 "AIF2DACDAT", "AIF3DACDAT",
1505};
1506
1507static const struct soc_enum aif2dac_enum =
1508 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1509
1510static const struct snd_kcontrol_new aif2dac_mux =
1511 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1512
1513static const char *aif2adc_text[] = {
1514 "AIF2ADCDAT", "AIF3DACDAT",
1515};
1516
1517static const struct soc_enum aif2adc_enum =
1518 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1519
1520static const struct snd_kcontrol_new aif2adc_mux =
1521 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1522
1523static const char *aif3adc_text[] = {
c4431df0 1524 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1525};
1526
c4431df0 1527static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1528 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1529
c4431df0
MB		 1530static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1531 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1532
1533static const struct soc_enum wm8958_aif3adc_enum =
1534 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1535
1536static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1537 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1538
1539static const char *mono_pcm_out_text[] = {
c1a4ecd9 1540 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1541};
1542
1543static const struct soc_enum mono_pcm_out_enum =
1544 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1545
1546static const struct snd_kcontrol_new mono_pcm_out_mux =
1547 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1548
1549static const char *aif2dac_src_text[] = {
1550 "AIF2", "AIF3",
1551};
1552
1553/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1554static const struct soc_enum aif2dacl_src_enum =
1555 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1556
1557static const struct snd_kcontrol_new aif2dacl_src_mux =
1558 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1559
1560static const struct soc_enum aif2dacr_src_enum =
1561 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1562
1563static const struct snd_kcontrol_new aif2dacr_src_mux =
1564 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1565
173efa09 1566static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1567SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1568 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1569SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1570 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1571
1572SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1573 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1574SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1575 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1576SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1577 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1578SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1579 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1580SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1581 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1582
1583SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1584 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1585 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1586SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1587 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1588 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1589SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1590 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1591SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1592 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1593
1594SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1595};
1596
1597static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1598SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1599 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1600 SND_SOC_DAPM_PRE_PMD),
1a38336b 1601SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1602 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1603 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1604SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1605SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1607SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1608 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1609SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1610SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1611};
1612
c52fd021
DP		 1613static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1614SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1615 dac_ev, SND_SOC_DAPM_PRE_PMU),
1616SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1617 dac_ev, SND_SOC_DAPM_PRE_PMU),
1618SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1619 dac_ev, SND_SOC_DAPM_PRE_PMU),
1620SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1621 dac_ev, SND_SOC_DAPM_PRE_PMU),
1622};
1623
1624static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1625SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1626SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1627SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1628SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1629};
1630
04d28681 1631static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1632SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1633 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1634SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1635 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1636};
1637
1638static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1639SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1640SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1641};
1642
9e6e96a1
MB		 1643static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1644SND_SOC_DAPM_INPUT("DMIC1DAT"),
1645SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1646SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1647
b462c6e6
DP		 1648SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1649 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1650SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1651 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1652
9e6e96a1 1653SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1654 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1655 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1656
1a38336b
MB		 1657SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1658SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1659SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1660
7f94de48 1661SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1662 0, SND_SOC_NOPM, 9, 0),
7f94de48 1663SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1664 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1665SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1666 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1667 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1668SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1669 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1670 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1671
7f94de48 1672SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1673 0, SND_SOC_NOPM, 11, 0),
7f94de48 1674SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1675 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1676SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1677 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1678 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1679SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1680 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1681 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1682
1683SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1684 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1685SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1686 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1687
a3257ba8
MB		 1688SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1689 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1690SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1691 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1692
9e6e96a1
MB		 1693SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1694 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1695SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1696 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1697
1698SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1699SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1700
1701SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1702 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1703SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1704 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1705
1706SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1707 SND_SOC_NOPM, 13, 0),
9e6e96a1 1708SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1709 SND_SOC_NOPM, 12, 0),
d6addcc9 1710SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1711 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1712 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1713SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1714 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1715 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1716
5567d8c6
MB		 1717SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1718SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1719SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1720SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1721
1722SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1723SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1724SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1725
5567d8c6
MB		 1726SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1727SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1728
1729SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1730
1731SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1732SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1733SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1734SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1735
1736/* Power is done with the muxes since the ADC power also controls the
1737 * downsampling chain, the chip will automatically manage the analogue
1738 * specific portions.
1739 */
1740SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1741SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1742
9e6e96a1
MB		 1743SND_SOC_DAPM_POST("Debug log", post_ev),
1744};
1745
c4431df0
MB		 1746static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1747SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1748};
9e6e96a1 1749
c4431df0 1750static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1751SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1752SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1753SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1754SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1755SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1756};
1757
1758static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1759 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1760 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1761
1762 { "DSP1CLK", NULL, "CLK_SYS" },
1763 { "DSP2CLK", NULL, "CLK_SYS" },
1764 { "DSPINTCLK", NULL, "CLK_SYS" },
1765
1766 { "AIF1ADC1L", NULL, "AIF1CLK" },
1767 { "AIF1ADC1L", NULL, "DSP1CLK" },
1768 { "AIF1ADC1R", NULL, "AIF1CLK" },
1769 { "AIF1ADC1R", NULL, "DSP1CLK" },
1770 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1771
1772 { "AIF1DAC1L", NULL, "AIF1CLK" },
1773 { "AIF1DAC1L", NULL, "DSP1CLK" },
1774 { "AIF1DAC1R", NULL, "AIF1CLK" },
1775 { "AIF1DAC1R", NULL, "DSP1CLK" },
1776 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1777
1778 { "AIF1ADC2L", NULL, "AIF1CLK" },
1779 { "AIF1ADC2L", NULL, "DSP1CLK" },
1780 { "AIF1ADC2R", NULL, "AIF1CLK" },
1781 { "AIF1ADC2R", NULL, "DSP1CLK" },
1782 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1783
1784 { "AIF1DAC2L", NULL, "AIF1CLK" },
1785 { "AIF1DAC2L", NULL, "DSP1CLK" },
1786 { "AIF1DAC2R", NULL, "AIF1CLK" },
1787 { "AIF1DAC2R", NULL, "DSP1CLK" },
1788 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1789
1790 { "AIF2ADCL", NULL, "AIF2CLK" },
1791 { "AIF2ADCL", NULL, "DSP2CLK" },
1792 { "AIF2ADCR", NULL, "AIF2CLK" },
1793 { "AIF2ADCR", NULL, "DSP2CLK" },
1794 { "AIF2ADCR", NULL, "DSPINTCLK" },
1795
1796 { "AIF2DACL", NULL, "AIF2CLK" },
1797 { "AIF2DACL", NULL, "DSP2CLK" },
1798 { "AIF2DACR", NULL, "AIF2CLK" },
1799 { "AIF2DACR", NULL, "DSP2CLK" },
1800 { "AIF2DACR", NULL, "DSPINTCLK" },
1801
1802 { "DMIC1L", NULL, "DMIC1DAT" },
1803 { "DMIC1L", NULL, "CLK_SYS" },
1804 { "DMIC1R", NULL, "DMIC1DAT" },
1805 { "DMIC1R", NULL, "CLK_SYS" },
1806 { "DMIC2L", NULL, "DMIC2DAT" },
1807 { "DMIC2L", NULL, "CLK_SYS" },
1808 { "DMIC2R", NULL, "DMIC2DAT" },
1809 { "DMIC2R", NULL, "CLK_SYS" },
1810
1811 { "ADCL", NULL, "AIF1CLK" },
1812 { "ADCL", NULL, "DSP1CLK" },
1813 { "ADCL", NULL, "DSPINTCLK" },
1814
1815 { "ADCR", NULL, "AIF1CLK" },
1816 { "ADCR", NULL, "DSP1CLK" },
1817 { "ADCR", NULL, "DSPINTCLK" },
1818
1819 { "ADCL Mux", "ADC", "ADCL" },
1820 { "ADCL Mux", "DMIC", "DMIC1L" },
1821 { "ADCR Mux", "ADC", "ADCR" },
1822 { "ADCR Mux", "DMIC", "DMIC1R" },
1823
1824 { "DAC1L", NULL, "AIF1CLK" },
1825 { "DAC1L", NULL, "DSP1CLK" },
1826 { "DAC1L", NULL, "DSPINTCLK" },
1827
1828 { "DAC1R", NULL, "AIF1CLK" },
1829 { "DAC1R", NULL, "DSP1CLK" },
1830 { "DAC1R", NULL, "DSPINTCLK" },
1831
1832 { "DAC2L", NULL, "AIF2CLK" },
1833 { "DAC2L", NULL, "DSP2CLK" },
1834 { "DAC2L", NULL, "DSPINTCLK" },
1835
1836 { "DAC2R", NULL, "AIF2DACR" },
1837 { "DAC2R", NULL, "AIF2CLK" },
1838 { "DAC2R", NULL, "DSP2CLK" },
1839 { "DAC2R", NULL, "DSPINTCLK" },
1840
1841 { "TOCLK", NULL, "CLK_SYS" },
1842
5567d8c6
MB		 1843 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1844 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1845 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1846
1847 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1848 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1849 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1850
9e6e96a1
MB		 1851 /* AIF1 outputs */
1852 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1853 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1854 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1855
1856 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1857 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1858 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1859
a3257ba8
MB		 1860 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1861 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1862 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1863
1864 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1865 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1866 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1867
9e6e96a1
MB		 1868 /* Pin level routing for AIF3 */
1869 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1870 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1871 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1872 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1873
9e6e96a1
MB		 1874 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1875 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1876 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1877 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1879 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1880 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1881
1882 /* DAC1 inputs */
9e6e96a1
MB		 1883 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1884 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1885 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1886 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1887 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1888
9e6e96a1
MB		 1889 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1890 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1891 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1892 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1893 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1894
1895 /* DAC2/AIF2 outputs */
1896 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1897 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1898 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1899 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1900 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1901 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1902
1903 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1904 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1905 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1906 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1907 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909
7f94de48
MB		 1910 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1911 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1912 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1913 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1914
9e6e96a1
MB		 1915 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1916
1917 /* AIF3 output */
1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1921 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1923 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1925 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1926
1927 /* Sidetone */
1928 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1929 { "Left Sidetone", "DMIC2", "DMIC2L" },
1930 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1931 { "Right Sidetone", "DMIC2", "DMIC2R" },
1932
1933 /* Output stages */
1934 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1935 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1936
1937 { "SPKL", "DAC1 Switch", "DAC1L" },
1938 { "SPKL", "DAC2 Switch", "DAC2L" },
1939
1940 { "SPKR", "DAC1 Switch", "DAC1R" },
1941 { "SPKR", "DAC2 Switch", "DAC2R" },
1942
1943 { "Left Headphone Mux", "DAC", "DAC1L" },
1944 { "Right Headphone Mux", "DAC", "DAC1R" },
1945};
1946
173efa09
DP		 1947static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1948 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1949 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1950 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1951 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1952 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1953 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1954 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1955 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1956};
1957
1958static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1959 { "DAC1L", NULL, "DAC1L Mixer" },
1960 { "DAC1R", NULL, "DAC1R Mixer" },
1961 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1962 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1963};
1964
6ed8f148
MB		 1965static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1966 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1967 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1968 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1969 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1970 { "MICBIAS1", NULL, "CLK_SYS" },
1971 { "MICBIAS1", NULL, "MICBIAS Supply" },
1972 { "MICBIAS2", NULL, "CLK_SYS" },
1973 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1974};
1975
c4431df0
MB		 1976static const struct snd_soc_dapm_route wm8994_intercon[] = {
1977 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1978 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1979 { "MICBIAS1", NULL, "VMID" },
1980 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1981};
1982
1983static const struct snd_soc_dapm_route wm8958_intercon[] = {
1984 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1985 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1986
1987 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1988 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1989 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1990 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1991
8c5b842b
MB		 1992 { "AIF3DACDAT", NULL, "AIF3" },
1993 { "AIF3ADCDAT", NULL, "AIF3" },
1994
c4431df0
MB		 1995 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1996 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1997
1998 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1999};
2000
9e6e96a1
MB		 2001/* The size in bits of the FLL divide multiplied by 10
2002 * to allow rounding later */
2003#define FIXED_FLL_SIZE ((1 << 16) * 10)
2004
2005struct fll_div {
2006 u16 outdiv;
2007 u16 n;
2008 u16 k;
d1a0a299 2009 u16 lambda;
9e6e96a1
MB		 2010 u16 clk_ref_div;
2011 u16 fll_fratio;
2012};
2013
d1a0a299 2014static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
9e6e96a1
MB		 2015 int freq_in, int freq_out)
2016{
2017 u64 Kpart;
d1a0a299 2018 unsigned int K, Ndiv, Nmod, gcd_fll;
9e6e96a1
MB		 2019
2020 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2021
2022 /* Scale the input frequency down to <= 13.5MHz */
2023 fll->clk_ref_div = 0;
2024 while (freq_in > 13500000) {
2025 fll->clk_ref_div++;
2026 freq_in /= 2;
2027
2028 if (fll->clk_ref_div > 3)
2029 return -EINVAL;
2030 }
2031 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2032
2033 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2034 fll->outdiv = 3;
2035 while (freq_out * (fll->outdiv + 1) < 90000000) {
2036 fll->outdiv++;
2037 if (fll->outdiv > 63)
2038 return -EINVAL;
2039 }
2040 freq_out *= fll->outdiv + 1;
2041 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2042
2043 if (freq_in > 1000000) {
2044 fll->fll_fratio = 0;
7d48a6ac
MB		 2045 } else if (freq_in > 256000) {
2046 fll->fll_fratio = 1;
2047 freq_in *= 2;
2048 } else if (freq_in > 128000) {
2049 fll->fll_fratio = 2;
2050 freq_in *= 4;
2051 } else if (freq_in > 64000) {
9e6e96a1
MB		 2052 fll->fll_fratio = 3;
2053 freq_in *= 8;
7d48a6ac
MB		 2054 } else {
2055 fll->fll_fratio = 4;
2056 freq_in *= 16;
9e6e96a1
MB		 2057 }
2058 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2059
2060 /* Now, calculate N.K */
2061 Ndiv = freq_out / freq_in;
2062
2063 fll->n = Ndiv;
2064 Nmod = freq_out % freq_in;
2065 pr_debug("Nmod=%d\n", Nmod);
2066
d1a0a299
MB		 2067 switch (control->type) {
2068 case WM8994:
2069 /* Calculate fractional part - scale up so we can round. */
2070 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
9e6e96a1 2071
d1a0a299 2072 do_div(Kpart, freq_in);
9e6e96a1 2073
d1a0a299 2074 K = Kpart & 0xFFFFFFFF;
9e6e96a1 2075
d1a0a299
MB		 2076 if ((K % 10) >= 5)
2077 K += 5;
9e6e96a1 2078
d1a0a299
MB		 2079 /* Move down to proper range now rounding is done */
2080 fll->k = K / 10;
f7dbd399 2081 fll->lambda = 0;
9e6e96a1 2082
d1a0a299 2083 pr_debug("N=%x K=%x\n", fll->n, fll->k);
571ab6c6 2084 break;
d1a0a299
MB		 2085
2086 default:
2087 gcd_fll = gcd(freq_out, freq_in);
2088
2089 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2090 fll->lambda = freq_in / gcd_fll;
2091
2092 }
9e6e96a1
MB		 2093
2094 return 0;
2095}
2096
f0fba2ad 2097static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2098 unsigned int freq_in, unsigned int freq_out)
2099{
b2c812e2 2100 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2101 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2102 int reg_offset, ret;
2103 struct fll_div fll;
e413ba88 2104 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2105 unsigned long timeout;
4b7ed83a 2106 bool was_enabled;
9e6e96a1 2107
9e6e96a1
MB		 2108 switch (id) {
2109 case WM8994_FLL1:
2110 reg_offset = 0;
2111 id = 0;
e413ba88 2112 aif_src = 0x10;
9e6e96a1
MB		 2113 break;
2114 case WM8994_FLL2:
2115 reg_offset = 0x20;
2116 id = 1;
e413ba88 2117 aif_src = 0x18;
9e6e96a1
MB		 2118 break;
2119 default:
2120 return -EINVAL;
2121 }
2122
4b7ed83a
MB		 2123 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2124 was_enabled = reg & WM8994_FLL1_ENA;
2125
136ff2a2 2126 switch (src) {
7add84aa
MB		 2127 case 0:
2128 /* Allow no source specification when stopping */
2129 if (freq_out)
2130 return -EINVAL;
4514e899 2131 src = wm8994->fll[id].src;
7add84aa 2132 break;
136ff2a2
MB		 2133 case WM8994_FLL_SRC_MCLK1:
2134 case WM8994_FLL_SRC_MCLK2:
2135 case WM8994_FLL_SRC_LRCLK:
2136 case WM8994_FLL_SRC_BCLK:
2137 break;
fbfe6983
MB		 2138 case WM8994_FLL_SRC_INTERNAL:
2139 freq_in = 12000000;
2140 freq_out = 12000000;
2141 break;
136ff2a2
MB		 2142 default:
2143 return -EINVAL;
2144 }
2145
9e6e96a1
MB		 2146 /* Are we changing anything? */
2147 if (wm8994->fll[id].src == src &&
2148 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2149 return 0;
2150
2151 /* If we're stopping the FLL redo the old config - no
2152 * registers will actually be written but we avoid GCC flow
2153 * analysis bugs spewing warnings.
2154 */
2155 if (freq_out)
d1a0a299 2156 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
9e6e96a1 2157 else
d1a0a299 2158 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
9e6e96a1
MB		 2159 wm8994->fll[id].out);
2160 if (ret < 0)
2161 return ret;
2162
e413ba88
MB		 2163 /* Make sure that we're not providing SYSCLK right now */
2164 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2165 if (clk1 & WM8994_SYSCLK_SRC)
2166 aif_reg = WM8994_AIF2_CLOCKING_1;
2167 else
2168 aif_reg = WM8994_AIF1_CLOCKING_1;
2169 reg = snd_soc_read(codec, aif_reg);
2170
2171 if ((reg & WM8994_AIF1CLK_ENA) &&
2172 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2173 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2174 id + 1);
2175 return -EBUSY;
2176 }
9e6e96a1
MB		 2177
2178 /* We always need to disable the FLL while reconfiguring */
2179 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2180 WM8994_FLL1_ENA, 0);
2181
20dc24a9 2182 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2183 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2184 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2185 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2186 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2187 goto out;
2188 }
2189
9e6e96a1
MB		 2190 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2191 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2192 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2193 WM8994_FLL1_OUTDIV_MASK |
2194 WM8994_FLL1_FRATIO_MASK, reg);
2195
b16db745
MB		 2196 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2197 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2198
2199 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2200 WM8994_FLL1_N_MASK,
7435d4ee 2201 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1 2202
d1a0a299
MB		 2203 if (fll.lambda) {
2204 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2205 WM8958_FLL1_LAMBDA_MASK,
2206 fll.lambda);
2207 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2208 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2209 } else {
2210 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2211 WM8958_FLL1_EFS_ENA, 0);
2212 }
2213
9e6e96a1 2214 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2215 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2216 WM8994_FLL1_REFCLK_DIV_MASK |
2217 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2218 ((src == WM8994_FLL_SRC_INTERNAL)
2219 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2220 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2221 (src - 1));
9e6e96a1 2222
f0f5039c
MB		 2223 /* Clear any pending completion from a previous failure */
2224 try_wait_for_completion(&wm8994->fll_locked[id]);
2225
9e6e96a1
MB		 2226 /* Enable (with fractional mode if required) */
2227 if (freq_out) {
4b7ed83a
MB		 2228 /* Enable VMID if we need it */
2229 if (!was_enabled) {
af6b6fe4
MB		 2230 active_reference(codec);
2231
4b7ed83a
MB		 2232 switch (control->type) {
2233 case WM8994:
2234 vmid_reference(codec);
2235 break;
2236 case WM8958:
da445afe 2237 if (control->revision < 1)
4b7ed83a
MB		 2238 vmid_reference(codec);
2239 break;
2240 default:
2241 break;
2242 }
2243 }
2244
fbfe6983
MB		 2245 reg = WM8994_FLL1_ENA;
2246
9e6e96a1 2247 if (fll.k)
fbfe6983
MB		 2248 reg |= WM8994_FLL1_FRAC;
2249 if (src == WM8994_FLL_SRC_INTERNAL)
2250 reg |= WM8994_FLL1_OSC_ENA;
2251
9e6e96a1 2252 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2253 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2254 WM8994_FLL1_FRAC, reg);
8e9ddf81 2255
c7ebf932
MB		 2256 if (wm8994->fll_locked_irq) {
2257 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2258 msecs_to_jiffies(10));
2259 if (timeout == 0)
2260 dev_warn(codec->dev,
2261 "Timed out waiting for FLL lock\n");
2262 } else {
2263 msleep(5);
2264 }
4b7ed83a
MB		 2265 } else {
2266 if (was_enabled) {
2267 switch (control->type) {
2268 case WM8994:
2269 vmid_dereference(codec);
2270 break;
2271 case WM8958:
da445afe 2272 if (control->revision < 1)
4b7ed83a
MB		 2273 vmid_dereference(codec);
2274 break;
2275 default:
2276 break;
2277 }
af6b6fe4
MB		 2278
2279 active_dereference(codec);
4b7ed83a 2280 }
9e6e96a1
MB		 2281 }
2282
20dc24a9 2283out:
9e6e96a1
MB		 2284 wm8994->fll[id].in = freq_in;
2285 wm8994->fll[id].out = freq_out;
136ff2a2 2286 wm8994->fll[id].src = src;
9e6e96a1 2287
9e6e96a1
MB		 2288 configure_clock(codec);
2289
cd22000a
MB		 2290 /*
2291 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2292 * for detection.
2293 */
2294 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2295 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2296
2297 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2298 & WM8994_AIF1CLK_RATE_MASK;
2299 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2300 & WM8994_AIF1CLK_RATE_MASK;
2301
cd22000a
MB		 2302 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2303 WM8994_AIF1CLK_RATE_MASK, 0x1);
2304 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2305 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2306 } else if (wm8994->aifdiv[0]) {
2307 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2308 WM8994_AIF1CLK_RATE_MASK,
2309 wm8994->aifdiv[0]);
2310 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2311 WM8994_AIF2CLK_RATE_MASK,
2312 wm8994->aifdiv[1]);
2313
2314 wm8994->aifdiv[0] = 0;
2315 wm8994->aifdiv[1] = 0;
cd22000a
MB		 2316 }
2317
9e6e96a1
MB		 2318 return 0;
2319}
2320
c7ebf932
MB		 2321static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2322{
2323 struct completion *completion = data;
2324
2325 complete(completion);
2326
2327 return IRQ_HANDLED;
2328}
f0fba2ad 2329
66b47fdb
MB		 2330static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2331
f0fba2ad
LG		 2332static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2333 unsigned int freq_in, unsigned int freq_out)
2334{
2335 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2336}
2337
9e6e96a1
MB		 2338static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2339 int clk_id, unsigned int freq, int dir)
2340{
2341 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2342 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2343 int i;
9e6e96a1
MB		 2344
2345 switch (dai->id) {
2346 case 1:
2347 case 2:
2348 break;
2349
2350 default:
2351 /* AIF3 shares clocking with AIF1/2 */
2352 return -EINVAL;
2353 }
2354
2355 switch (clk_id) {
2356 case WM8994_SYSCLK_MCLK1:
2357 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2358 wm8994->mclk[0] = freq;
2359 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2360 dai->id, freq);
2361 break;
2362
2363 case WM8994_SYSCLK_MCLK2:
2364 /* TODO: Set GPIO AF */
2365 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2366 wm8994->mclk[1] = freq;
2367 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2368 dai->id, freq);
2369 break;
2370
2371 case WM8994_SYSCLK_FLL1:
2372 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2373 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2374 break;
2375
2376 case WM8994_SYSCLK_FLL2:
2377 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2378 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2379 break;
2380
66b47fdb
MB		 2381 case WM8994_SYSCLK_OPCLK:
2382 /* Special case - a division (times 10) is given and
c1a4ecd9 2383 * no effect on main clocking.
66b47fdb
MB		 2384 */
2385 if (freq) {
2386 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2387 if (opclk_divs[i] == freq)
2388 break;
2389 if (i == ARRAY_SIZE(opclk_divs))
2390 return -EINVAL;
2391 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2392 WM8994_OPCLK_DIV_MASK, i);
2393 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2394 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2395 } else {
2396 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2397 WM8994_OPCLK_ENA, 0);
2398 }
2399
9e6e96a1
MB		 2400 default:
2401 return -EINVAL;
2402 }
2403
2404 configure_clock(codec);
2405
6730049a
MB		 2406 /*
2407 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2408 * for detection.
2409 */
2410 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2411 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2412
2413 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2414 & WM8994_AIF1CLK_RATE_MASK;
2415 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2416 & WM8994_AIF1CLK_RATE_MASK;
2417
6730049a
MB		 2418 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2419 WM8994_AIF1CLK_RATE_MASK, 0x1);
2420 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2421 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2422 } else if (wm8994->aifdiv[0]) {
2423 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2424 WM8994_AIF1CLK_RATE_MASK,
2425 wm8994->aifdiv[0]);
2426 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2427 WM8994_AIF2CLK_RATE_MASK,
2428 wm8994->aifdiv[1]);
2429
2430 wm8994->aifdiv[0] = 0;
2431 wm8994->aifdiv[1] = 0;
6730049a
MB		 2432 }
2433
9e6e96a1
MB		 2434 return 0;
2435}
2436
2437static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2438 enum snd_soc_bias_level level)
2439{
b6b05691 2440 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2441 struct wm8994 *control = wm8994->wm8994;
b6b05691 2442
5f2f3890
MB		 2443 wm_hubs_set_bias_level(codec, level);
2444
9e6e96a1
MB		 2445 switch (level) {
2446 case SND_SOC_BIAS_ON:
2447 break;
2448
2449 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2450 /* MICBIAS into regulating mode */
2451 switch (control->type) {
2452 case WM8958:
2453 case WM1811:
2454 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2455 WM8958_MICB1_MODE, 0);
2456 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2457 WM8958_MICB2_MODE, 0);
2458 break;
2459 default:
2460 break;
2461 }
af6b6fe4
MB		 2462
2463 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2464 active_reference(codec);
9e6e96a1
MB		 2465 break;
2466
2467 case SND_SOC_BIAS_STANDBY:
ce6120cc 2468 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2469 switch (control->type) {
8bc3c2c2 2470 case WM8958:
da445afe 2471 if (control->revision == 0) {
8bc3c2c2 2472 /* Optimise performance for rev A */
8bc3c2c2
MB		 2473 snd_soc_update_bits(codec,
2474 WM8958_CHARGE_PUMP_2,
2475 WM8958_CP_DISCH,
2476 WM8958_CP_DISCH);
2477 }
2478 break;
81204c84 2479
462835e4 2480 default:
81204c84 2481 break;
b6b05691 2482 }
9e6e96a1
MB		 2483
2484 /* Discharge LINEOUT1 & 2 */
2485 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2486 WM8994_LINEOUT1_DISCH |
2487 WM8994_LINEOUT2_DISCH,
2488 WM8994_LINEOUT1_DISCH |
2489 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2490 }
2491
af6b6fe4
MB		 2492 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2493 active_dereference(codec);
2494
500fa30e
MB		 2495 /* MICBIAS into bypass mode on newer devices */
2496 switch (control->type) {
2497 case WM8958:
2498 case WM1811:
2499 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2500 WM8958_MICB1_MODE,
2501 WM8958_MICB1_MODE);
2502 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2503 WM8958_MICB2_MODE,
2504 WM8958_MICB2_MODE);
2505 break;
2506 default:
2507 break;
2508 }
9e6e96a1
MB		 2509 break;
2510
2511 case SND_SOC_BIAS_OFF:
4105ab84 2512 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2513 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2514 break;
2515 }
5f2f3890 2516
ce6120cc 2517 codec->dapm.bias_level = level;
af6b6fe4 2518
22f8d055
MB		 2519 return 0;
2520}
2521
2522int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2523{
2524 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2525
2526 switch (mode) {
2527 case WM8994_VMID_NORMAL:
2528 if (wm8994->hubs.lineout1_se) {
2529 snd_soc_dapm_disable_pin(&codec->dapm,
2530 "LINEOUT1N Driver");
2531 snd_soc_dapm_disable_pin(&codec->dapm,
2532 "LINEOUT1P Driver");
2533 }
2534 if (wm8994->hubs.lineout2_se) {
2535 snd_soc_dapm_disable_pin(&codec->dapm,
2536 "LINEOUT2N Driver");
2537 snd_soc_dapm_disable_pin(&codec->dapm,
2538 "LINEOUT2P Driver");
2539 }
2540
2541 /* Do the sync with the old mode to allow it to clean up */
2542 snd_soc_dapm_sync(&codec->dapm);
2543 wm8994->vmid_mode = mode;
2544 break;
2545
2546 case WM8994_VMID_FORCE:
2547 if (wm8994->hubs.lineout1_se) {
2548 snd_soc_dapm_force_enable_pin(&codec->dapm,
2549 "LINEOUT1N Driver");
2550 snd_soc_dapm_force_enable_pin(&codec->dapm,
2551 "LINEOUT1P Driver");
2552 }
2553 if (wm8994->hubs.lineout2_se) {
2554 snd_soc_dapm_force_enable_pin(&codec->dapm,
2555 "LINEOUT2N Driver");
2556 snd_soc_dapm_force_enable_pin(&codec->dapm,
2557 "LINEOUT2P Driver");
2558 }
2559
2560 wm8994->vmid_mode = mode;
2561 snd_soc_dapm_sync(&codec->dapm);
2562 break;
2563
2564 default:
2565 return -EINVAL;
2566 }
2567
9e6e96a1
MB		 2568 return 0;
2569}
2570
2571static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2572{
2573 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2574 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2575 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2576 int ms_reg;
2577 int aif1_reg;
435705e8
MB		 2578 int dac_reg;
2579 int adc_reg;
9e6e96a1
MB		 2580 int ms = 0;
2581 int aif1 = 0;
435705e8 2582 int lrclk = 0;
9e6e96a1
MB		 2583
2584 switch (dai->id) {
2585 case 1:
2586 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2587 aif1_reg = WM8994_AIF1_CONTROL_1;
435705e8
MB		 2588 dac_reg = WM8994_AIF1DAC_LRCLK;
2589 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2590 break;
2591 case 2:
2592 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2593 aif1_reg = WM8994_AIF2_CONTROL_1;
435705e8
MB		 2594 dac_reg = WM8994_AIF1DAC_LRCLK;
2595 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2596 break;
2597 default:
2598 return -EINVAL;
2599 }
2600
2601 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2602 case SND_SOC_DAIFMT_CBS_CFS:
2603 break;
2604 case SND_SOC_DAIFMT_CBM_CFM:
2605 ms = WM8994_AIF1_MSTR;
2606 break;
2607 default:
2608 return -EINVAL;
2609 }
2610
2611 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2612 case SND_SOC_DAIFMT_DSP_B:
2613 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2614 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2615 case SND_SOC_DAIFMT_DSP_A:
2616 aif1 |= 0x18;
2617 break;
2618 case SND_SOC_DAIFMT_I2S:
2619 aif1 |= 0x10;
2620 break;
2621 case SND_SOC_DAIFMT_RIGHT_J:
2622 break;
2623 case SND_SOC_DAIFMT_LEFT_J:
2624 aif1 |= 0x8;
2625 break;
2626 default:
2627 return -EINVAL;
2628 }
2629
2630 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2631 case SND_SOC_DAIFMT_DSP_A:
2632 case SND_SOC_DAIFMT_DSP_B:
2633 /* frame inversion not valid for DSP modes */
2634 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2635 case SND_SOC_DAIFMT_NB_NF:
2636 break;
2637 case SND_SOC_DAIFMT_IB_NF:
2638 aif1 |= WM8994_AIF1_BCLK_INV;
2639 break;
2640 default:
2641 return -EINVAL;
2642 }
2643 break;
2644
2645 case SND_SOC_DAIFMT_I2S:
2646 case SND_SOC_DAIFMT_RIGHT_J:
2647 case SND_SOC_DAIFMT_LEFT_J:
2648 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2649 case SND_SOC_DAIFMT_NB_NF:
2650 break;
2651 case SND_SOC_DAIFMT_IB_IF:
2652 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
435705e8 2653 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2654 break;
2655 case SND_SOC_DAIFMT_IB_NF:
2656 aif1 |= WM8994_AIF1_BCLK_INV;
2657 break;
2658 case SND_SOC_DAIFMT_NB_IF:
2659 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2660 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2661 break;
2662 default:
2663 return -EINVAL;
2664 }
2665 break;
2666 default:
2667 return -EINVAL;
2668 }
2669
c4431df0
MB		 2670 /* The AIF2 format configuration needs to be mirrored to AIF3
2671 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2672 switch (control->type) {
2673 case WM1811:
2674 case WM8958:
2675 if (dai->id == 2)
2676 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2677 WM8994_AIF1_LRCLK_INV |
2678 WM8958_AIF3_FMT_MASK, aif1);
2679 break;
2680
2681 default:
2682 break;
2683 }
c4431df0 2684
9e6e96a1
MB		 2685 snd_soc_update_bits(codec, aif1_reg,
2686 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2687 WM8994_AIF1_FMT_MASK,
2688 aif1);
2689 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2690 ms);
435705e8
MB		 2691 snd_soc_update_bits(codec, dac_reg,
2692 WM8958_AIF1_LRCLK_INV, lrclk);
2693 snd_soc_update_bits(codec, adc_reg,
2694 WM8958_AIF1_LRCLK_INV, lrclk);
9e6e96a1
MB		 2695
2696 return 0;
2697}
2698
2699static struct {
2700 int val, rate;
2701} srs[] = {
2702 { 0, 8000 },
2703 { 1, 11025 },
2704 { 2, 12000 },
2705 { 3, 16000 },
2706 { 4, 22050 },
2707 { 5, 24000 },
2708 { 6, 32000 },
2709 { 7, 44100 },
2710 { 8, 48000 },
2711 { 9, 88200 },
2712 { 10, 96000 },
2713};
2714
2715static int fs_ratios[] = {
2716 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2717};
2718
2719static int bclk_divs[] = {
2720 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2721 640, 880, 960, 1280, 1760, 1920
2722};
2723
2724static int wm8994_hw_params(struct snd_pcm_substream *substream,
2725 struct snd_pcm_hw_params *params,
2726 struct snd_soc_dai *dai)
2727{
2728 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2729 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3cf956ee
MB		 2730 struct wm8994 *control = wm8994->wm8994;
2731 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1 2732 int aif1_reg;
b1e43d93 2733 int aif2_reg;
9e6e96a1
MB		 2734 int bclk_reg;
2735 int lrclk_reg;
2736 int rate_reg;
2737 int aif1 = 0;
b1e43d93 2738 int aif2 = 0;
9e6e96a1
MB		 2739 int bclk = 0;
2740 int lrclk = 0;
2741 int rate_val = 0;
2742 int id = dai->id - 1;
2743
2744 int i, cur_val, best_val, bclk_rate, best;
2745
2746 switch (dai->id) {
2747 case 1:
2748 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2749 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2750 bclk_reg = WM8994_AIF1_BCLK;
2751 rate_reg = WM8994_AIF1_RATE;
2752 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2753 wm8994->lrclk_shared[0]) {
9e6e96a1 2754 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2755 } else {
9e6e96a1 2756 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2757 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2758 }
9e6e96a1
MB		 2759 break;
2760 case 2:
2761 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2762 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2763 bclk_reg = WM8994_AIF2_BCLK;
2764 rate_reg = WM8994_AIF2_RATE;
2765 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2766 wm8994->lrclk_shared[1]) {
9e6e96a1 2767 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2768 } else {
9e6e96a1 2769 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2770 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2771 }
9e6e96a1
MB		 2772 break;
2773 default:
2774 return -EINVAL;
2775 }
2776
79748cdb 2777 bclk_rate = params_rate(params);
9e6e96a1
MB		 2778 switch (params_format(params)) {
2779 case SNDRV_PCM_FORMAT_S16_LE:
2780 bclk_rate *= 16;
2781 break;
2782 case SNDRV_PCM_FORMAT_S20_3LE:
2783 bclk_rate *= 20;
2784 aif1 |= 0x20;
2785 break;
2786 case SNDRV_PCM_FORMAT_S24_LE:
2787 bclk_rate *= 24;
2788 aif1 |= 0x40;
2789 break;
2790 case SNDRV_PCM_FORMAT_S32_LE:
2791 bclk_rate *= 32;
2792 aif1 |= 0x60;
2793 break;
2794 default:
2795 return -EINVAL;
2796 }
2797
79748cdb 2798 wm8994->channels[id] = params_channels(params);
3cf956ee
MB		 2799 if (pdata->max_channels_clocked[id] &&
2800 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2801 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2802 pdata->max_channels_clocked[id], wm8994->channels[id]);
2803 wm8994->channels[id] = pdata->max_channels_clocked[id];
2804 }
2805
2806 switch (wm8994->channels[id]) {
79748cdb
MB		 2807 case 1:
2808 case 2:
2809 bclk_rate *= 2;
2810 break;
2811 default:
2812 bclk_rate *= 4;
2813 break;
2814 }
2815
9e6e96a1
MB		 2816 /* Try to find an appropriate sample rate; look for an exact match. */
2817 for (i = 0; i < ARRAY_SIZE(srs); i++)
2818 if (srs[i].rate == params_rate(params))
2819 break;
2820 if (i == ARRAY_SIZE(srs))
2821 return -EINVAL;
2822 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2823
2824 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2825 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2826 dai->id, wm8994->aifclk[id], bclk_rate);
2827
3cf956ee 2828 if (wm8994->channels[id] == 1 &&
b1e43d93
MB		 2829 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2830 aif2 |= WM8994_AIF1_MONO;
2831
9e6e96a1
MB		 2832 if (wm8994->aifclk[id] == 0) {
2833 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2834 return -EINVAL;
2835 }
2836
2837 /* AIFCLK/fs ratio; look for a close match in either direction */
2838 best = 0;
2839 best_val = abs((fs_ratios[0] * params_rate(params))
2840 - wm8994->aifclk[id]);
2841 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2842 cur_val = abs((fs_ratios[i] * params_rate(params))
2843 - wm8994->aifclk[id]);
2844 if (cur_val >= best_val)
2845 continue;
2846 best = i;
2847 best_val = cur_val;
2848 }
2849 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2850 dai->id, fs_ratios[best]);
2851 rate_val |= best;
2852
2853 /* We may not get quite the right frequency if using
2854 * approximate clocks so look for the closest match that is
2855 * higher than the target (we need to ensure that there enough
2856 * BCLKs to clock out the samples).
2857 */
2858 best = 0;
2859 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2860 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2861 if (cur_val < 0) /* BCLK table is sorted */
2862 break;
2863 best = i;
2864 }
07cd8ada 2865 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2866 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2867 bclk_divs[best], bclk_rate);
2868 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2869
2870 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2871 if (!lrclk) {
2872 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2873 bclk_rate);
2874 return -EINVAL;
2875 }
9e6e96a1
MB		 2876 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2877 lrclk, bclk_rate / lrclk);
2878
2879 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2880 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2881 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2882 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2883 lrclk);
2884 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2885 WM8994_AIF1CLK_RATE_MASK, rate_val);
2886
2887 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2888 switch (dai->id) {
2889 case 1:
2890 wm8994->dac_rates[0] = params_rate(params);
2891 wm8994_set_retune_mobile(codec, 0);
2892 wm8994_set_retune_mobile(codec, 1);
2893 break;
2894 case 2:
2895 wm8994->dac_rates[1] = params_rate(params);
2896 wm8994_set_retune_mobile(codec, 2);
2897 break;
2898 }
2899 }
2900
2901 return 0;
2902}
2903
c4431df0
MB		 2904static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2905 struct snd_pcm_hw_params *params,
2906 struct snd_soc_dai *dai)
2907{
2908 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2909 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2910 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2911 int aif1_reg;
2912 int aif1 = 0;
2913
2914 switch (dai->id) {
2915 case 3:
2916 switch (control->type) {
81204c84 2917 case WM1811:
c4431df0
MB		 2918 case WM8958:
2919 aif1_reg = WM8958_AIF3_CONTROL_1;
2920 break;
2921 default:
2922 return 0;
2923 }
4495e46f 2924 break;
c4431df0
MB		 2925 default:
2926 return 0;
2927 }
2928
2929 switch (params_format(params)) {
2930 case SNDRV_PCM_FORMAT_S16_LE:
2931 break;
2932 case SNDRV_PCM_FORMAT_S20_3LE:
2933 aif1 |= 0x20;
2934 break;
2935 case SNDRV_PCM_FORMAT_S24_LE:
2936 aif1 |= 0x40;
2937 break;
2938 case SNDRV_PCM_FORMAT_S32_LE:
2939 aif1 |= 0x60;
2940 break;
2941 default:
2942 return -EINVAL;
2943 }
2944
2945 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2946}
2947
9e6e96a1
MB		 2948static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2949{
2950 struct snd_soc_codec *codec = codec_dai->codec;
2951 int mute_reg;
2952 int reg;
2953
2954 switch (codec_dai->id) {
2955 case 1:
2956 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2957 break;
2958 case 2:
2959 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2960 break;
2961 default:
2962 return -EINVAL;
2963 }
2964
2965 if (mute)
2966 reg = WM8994_AIF1DAC1_MUTE;
2967 else
2968 reg = 0;
2969
2970 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2971
2972 return 0;
2973}
2974
778a76e2
MB		 2975static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2976{
2977 struct snd_soc_codec *codec = codec_dai->codec;
2978 int reg, val, mask;
2979
2980 switch (codec_dai->id) {
2981 case 1:
2982 reg = WM8994_AIF1_MASTER_SLAVE;
2983 mask = WM8994_AIF1_TRI;
2984 break;
2985 case 2:
2986 reg = WM8994_AIF2_MASTER_SLAVE;
2987 mask = WM8994_AIF2_TRI;
2988 break;
778a76e2
MB		 2989 default:
2990 return -EINVAL;
2991 }
2992
2993 if (tristate)
2994 val = mask;
2995 else
2996 val = 0;
2997
78b3fb46 2998 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2999}
3000
d09f3ecf
MB		 3001static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3002{
3003 struct snd_soc_codec *codec = dai->codec;
3004
3005 /* Disable the pulls on the AIF if we're using it to save power. */
3006 snd_soc_update_bits(codec, WM8994_GPIO_3,
3007 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3008 snd_soc_update_bits(codec, WM8994_GPIO_4,
3009 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3010 snd_soc_update_bits(codec, WM8994_GPIO_5,
3011 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3012
3013 return 0;
3014}
3015
9e6e96a1
MB		 3016#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3017
3018#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 3019 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 3020
85e7652d 3021static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 3022 .set_sysclk = wm8994_set_dai_sysclk,
3023 .set_fmt = wm8994_set_dai_fmt,
3024 .hw_params = wm8994_hw_params,
3025 .digital_mute = wm8994_aif_mute,
3026 .set_pll = wm8994_set_fll,
778a76e2 3027 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 3028};
3029
85e7652d 3030static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 3031 .set_sysclk = wm8994_set_dai_sysclk,
3032 .set_fmt = wm8994_set_dai_fmt,
3033 .hw_params = wm8994_hw_params,
3034 .digital_mute = wm8994_aif_mute,
3035 .set_pll = wm8994_set_fll,
778a76e2
MB		 3036 .set_tristate = wm8994_set_tristate,
3037};
3038
85e7652d 3039static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 3040 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 3041};
3042
f0fba2ad 3043static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 3044 {
f0fba2ad 3045 .name = "wm8994-aif1",
8c7f78b3 3046 .id = 1,
9e6e96a1
MB		 3047 .playback = {
3048 .stream_name = "AIF1 Playback",
b1e43d93 3049 .channels_min = 1,
9e6e96a1
MB		 3050 .channels_max = 2,
3051 .rates = WM8994_RATES,
3052 .formats = WM8994_FORMATS,
99b0292d 3053 .sig_bits = 24,
9e6e96a1
MB		 3054 },
3055 .capture = {
3056 .stream_name = "AIF1 Capture",
b1e43d93 3057 .channels_min = 1,
9e6e96a1
MB		 3058 .channels_max = 2,
3059 .rates = WM8994_RATES,
3060 .formats = WM8994_FORMATS,
99b0292d 3061 .sig_bits = 24,
9e6e96a1
MB		 3062 },
3063 .ops = &wm8994_aif1_dai_ops,
3064 },
3065 {
f0fba2ad 3066 .name = "wm8994-aif2",
8c7f78b3 3067 .id = 2,
9e6e96a1
MB		 3068 .playback = {
3069 .stream_name = "AIF2 Playback",
b1e43d93 3070 .channels_min = 1,
9e6e96a1
MB		 3071 .channels_max = 2,
3072 .rates = WM8994_RATES,
3073 .formats = WM8994_FORMATS,
99b0292d 3074 .sig_bits = 24,
9e6e96a1
MB		 3075 },
3076 .capture = {
3077 .stream_name = "AIF2 Capture",
b1e43d93 3078 .channels_min = 1,
9e6e96a1
MB		 3079 .channels_max = 2,
3080 .rates = WM8994_RATES,
3081 .formats = WM8994_FORMATS,
99b0292d 3082 .sig_bits = 24,
9e6e96a1 3083 },
d09f3ecf 3084 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 3085 .ops = &wm8994_aif2_dai_ops,
3086 },
3087 {
f0fba2ad 3088 .name = "wm8994-aif3",
8c7f78b3 3089 .id = 3,
9e6e96a1
MB		 3090 .playback = {
3091 .stream_name = "AIF3 Playback",
b1e43d93 3092 .channels_min = 1,
9e6e96a1
MB		 3093 .channels_max = 2,
3094 .rates = WM8994_RATES,
3095 .formats = WM8994_FORMATS,
99b0292d 3096 .sig_bits = 24,
9e6e96a1 3097 },
a8462bde 3098 .capture = {
9e6e96a1 3099 .stream_name = "AIF3 Capture",
b1e43d93 3100 .channels_min = 1,
9e6e96a1
MB		 3101 .channels_max = 2,
3102 .rates = WM8994_RATES,
3103 .formats = WM8994_FORMATS,
99b0292d
MB		 3104 .sig_bits = 24,
3105 },
778a76e2 3106 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3107 }
3108};
9e6e96a1
MB		 3109
3110#ifdef CONFIG_PM
4752a887 3111static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3112{
b2c812e2 3113 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3114 int i, ret;
3115
3116 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3117 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3118 sizeof(struct wm8994_fll_config));
f0fba2ad 3119 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3120 if (ret < 0)
3121 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3122 i + 1, ret);
3123 }
3124
3125 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3126
3127 return 0;
3128}
3129
4752a887 3130static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3131{
b2c812e2 3132 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3133 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 3134 int i, ret;
3135
9e6e96a1 3136 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3137 if (!wm8994->fll_suspend[i].out)
3138 continue;
3139
f0fba2ad 3140 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3141 wm8994->fll_suspend[i].src,
3142 wm8994->fll_suspend[i].in,
3143 wm8994->fll_suspend[i].out);
3144 if (ret < 0)
3145 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3146 i + 1, ret);
3147 }
3148
3149 return 0;
3150}
3151#else
4752a887
MB		 3152#define wm8994_codec_suspend NULL
3153#define wm8994_codec_resume NULL
9e6e96a1
MB		 3154#endif
3155
3156static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3157{
8cb8e83b 3158 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3159 struct wm8994 *control = wm8994->wm8994;
3160 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3161 struct snd_kcontrol_new controls[] = {
3162 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3163 wm8994->retune_mobile_enum,
3164 wm8994_get_retune_mobile_enum,
3165 wm8994_put_retune_mobile_enum),
3166 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3167 wm8994->retune_mobile_enum,
3168 wm8994_get_retune_mobile_enum,
3169 wm8994_put_retune_mobile_enum),
3170 SOC_ENUM_EXT("AIF2 EQ Mode",
3171 wm8994->retune_mobile_enum,
3172 wm8994_get_retune_mobile_enum,
3173 wm8994_put_retune_mobile_enum),
3174 };
3175 int ret, i, j;
3176 const char **t;
3177
3178 /* We need an array of texts for the enum API but the number
3179 * of texts is likely to be less than the number of
3180 * configurations due to the sample rate dependency of the
3181 * configurations. */
3182 wm8994->num_retune_mobile_texts = 0;
3183 wm8994->retune_mobile_texts = NULL;
3184 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3185 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3186 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3187 wm8994->retune_mobile_texts[j]) == 0)
3188 break;
3189 }
3190
3191 if (j != wm8994->num_retune_mobile_texts)
3192 continue;
3193
3194 /* Expand the array... */
3195 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3196 sizeof(char *) *
9e6e96a1
MB		 3197 (wm8994->num_retune_mobile_texts + 1),
3198 GFP_KERNEL);
3199 if (t == NULL)
3200 continue;
3201
3202 /* ...store the new entry... */
c1a4ecd9 3203 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3204 pdata->retune_mobile_cfgs[i].name;
3205
3206 /* ...and remember the new version. */
3207 wm8994->num_retune_mobile_texts++;
3208 wm8994->retune_mobile_texts = t;
3209 }
3210
3211 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3212 wm8994->num_retune_mobile_texts);
3213
3214 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3215 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3216
8cb8e83b 3217 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3218 ARRAY_SIZE(controls));
3219 if (ret != 0)
8cb8e83b 3220 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3221 "Failed to add ReTune Mobile controls: %d\n", ret);
3222}
3223
3224static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3225{
8cb8e83b 3226 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3227 struct wm8994 *control = wm8994->wm8994;
3228 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3229 int ret, i;
3230
3231 if (!pdata)
3232 return;
3233
3234 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3235 pdata->lineout2_diff,
3236 pdata->lineout1fb,
3237 pdata->lineout2fb,
3238 pdata->jd_scthr,
3239 pdata->jd_thr,
02e79476
MB		 3240 pdata->micb1_delay,
3241 pdata->micb2_delay,
9e6e96a1
MB		 3242 pdata->micbias1_lvl,
3243 pdata->micbias2_lvl);
3244
3245 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3246
3247 if (pdata->num_drc_cfgs) {
3248 struct snd_kcontrol_new controls[] = {
3249 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3250 wm8994_get_drc_enum, wm8994_put_drc_enum),
3251 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3252 wm8994_get_drc_enum, wm8994_put_drc_enum),
3253 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3254 wm8994_get_drc_enum, wm8994_put_drc_enum),
3255 };
3256
3257 /* We need an array of texts for the enum API */
8cb8e83b 3258 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3259 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3260 if (!wm8994->drc_texts) {
8cb8e83b 3261 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3262 "Failed to allocate %d DRC config texts\n",
3263 pdata->num_drc_cfgs);
3264 return;
3265 }
3266
3267 for (i = 0; i < pdata->num_drc_cfgs; i++)
3268 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3269
3270 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3271 wm8994->drc_enum.texts = wm8994->drc_texts;
3272
8cb8e83b 3273 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3274 ARRAY_SIZE(controls));
9e6e96a1
MB		 3275 for (i = 0; i < WM8994_NUM_DRC; i++)
3276 wm8994_set_drc(codec, i);
45a690f6
MB		 3277 } else {
3278 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3279 wm8994_drc_controls,
3280 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3281 }
3282
45a690f6
MB		 3283 if (ret != 0)
3284 dev_err(wm8994->hubs.codec->dev,
3285 "Failed to add DRC mode controls: %d\n", ret);
3286
3287
9e6e96a1
MB		 3288 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3289 pdata->num_retune_mobile_cfgs);
3290
3291 if (pdata->num_retune_mobile_cfgs)
3292 wm8994_handle_retune_mobile_pdata(wm8994);
3293 else
8cb8e83b 3294 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3295 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3296
3297 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3298 if (pdata->micbias[i]) {
3299 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3300 pdata->micbias[i] & 0xffff);
3301 }
3302 }
9e6e96a1
MB		 3303}
3304
88766984
MB		 3305/**
3306 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3307 *
3308 * @codec: WM8994 codec
3309 * @jack: jack to report detection events on
3310 * @micbias: microphone bias to detect on
88766984
MB		 3311 *
3312 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3313 * being used to bring out signals to the processor then only platform
5ab230a7 3314 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3315 * be configured using snd_soc_jack_add_gpios() instead.
3316 *
3317 * Configuration of detection levels is available via the micbias1_lvl
3318 * and micbias2_lvl platform data members.
3319 */
3320int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3321 int micbias)
88766984 3322{
b2c812e2 3323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3324 struct wm8994_micdet *micdet;
2a8a856d 3325 struct wm8994 *control = wm8994->wm8994;
87092e3c 3326 int reg, ret;
88766984 3327
87092e3c
MB		 3328 if (control->type != WM8994) {
3329 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3330 return -EINVAL;
87092e3c 3331 }
3a423157 3332
88766984
MB		 3333 switch (micbias) {
3334 case 1:
3335 micdet = &wm8994->micdet[0];
87092e3c
MB		 3336 if (jack)
3337 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3338 "MICBIAS1");
3339 else
3340 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3341 "MICBIAS1");
88766984
MB		 3342 break;
3343 case 2:
3344 micdet = &wm8994->micdet[1];
87092e3c
MB		 3345 if (jack)
3346 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3347 "MICBIAS1");
3348 else
3349 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3350 "MICBIAS1");
88766984
MB		 3351 break;
3352 default:
87092e3c 3353 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3354 return -EINVAL;
87092e3c 3355 }
88766984 3356
87092e3c
MB		 3357 if (ret != 0)
3358 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3359 micbias, ret);
3360
3361 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3362 micbias, jack);
88766984
MB		 3363
3364 /* Store the configuration */
3365 micdet->jack = jack;
87092e3c 3366 micdet->detecting = true;
88766984
MB		 3367
3368 /* If either of the jacks is set up then enable detection */
3369 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3370 reg = WM8994_MICD_ENA;
87092e3c 3371 else
88766984
MB		 3372 reg = 0;
3373
3374 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3375
d9f34df7
CR		 3376 /* enable MICDET and MICSHRT deboune */
3377 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3378 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3379 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3380 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3381
87092e3c
MB		 3382 snd_soc_dapm_sync(&codec->dapm);
3383
88766984
MB		 3384 return 0;
3385}
3386EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3387
e9b54de4 3388static void wm8994_mic_work(struct work_struct *work)
88766984 3389{
e9b54de4
MB		 3390 struct wm8994_priv *priv = container_of(work,
3391 struct wm8994_priv,
3392 mic_work.work);
fdfc4f3e
MB		 3393 struct regmap *regmap = priv->wm8994->regmap;
3394 struct device *dev = priv->wm8994->dev;
3395 unsigned int reg;
3396 int ret;
88766984
MB		 3397 int report;
3398
b8176627
MB		 3399 pm_runtime_get_sync(dev);
3400
fdfc4f3e
MB		 3401 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3402 if (ret < 0) {
3403 dev_err(dev, "Failed to read microphone status: %d\n",
3404 ret);
b8176627 3405 pm_runtime_put(dev);
e9b54de4 3406 return;
88766984
MB		 3407 }
3408
fdfc4f3e 3409 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3410
3411 report = 0;
87092e3c
MB		 3412 if (reg & WM8994_MIC1_DET_STS) {
3413 if (priv->micdet[0].detecting)
3414 report = SND_JACK_HEADSET;
3415 }
3416 if (reg & WM8994_MIC1_SHRT_STS) {
3417 if (priv->micdet[0].detecting)
3418 report = SND_JACK_HEADPHONE;
3419 else
3420 report |= SND_JACK_BTN_0;
3421 }
3422 if (report)
3423 priv->micdet[0].detecting = false;
3424 else
3425 priv->micdet[0].detecting = true;
3426
88766984 3427 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3428 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3429
3430 report = 0;
87092e3c
MB		 3431 if (reg & WM8994_MIC2_DET_STS) {
3432 if (priv->micdet[1].detecting)
3433 report = SND_JACK_HEADSET;
3434 }
3435 if (reg & WM8994_MIC2_SHRT_STS) {
3436 if (priv->micdet[1].detecting)
3437 report = SND_JACK_HEADPHONE;
3438 else
3439 report |= SND_JACK_BTN_0;
3440 }
3441 if (report)
3442 priv->micdet[1].detecting = false;
3443 else
3444 priv->micdet[1].detecting = true;
3445
88766984 3446 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3447 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3448
3449 pm_runtime_put(dev);
e9b54de4
MB		 3450}
3451
3452static irqreturn_t wm8994_mic_irq(int irq, void *data)
3453{
3454 struct wm8994_priv *priv = data;
8cb8e83b 3455 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3456
3457#ifndef CONFIG_SND_SOC_WM8994_MODULE
3458 trace_snd_soc_jack_irq(dev_name(codec->dev));
3459#endif
3460
3461 pm_wakeup_event(codec->dev, 300);
3462
3463 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3464
3465 return IRQ_HANDLED;
3466}
3467
f02b0de0
MB		 3468static void wm1811_micd_stop(struct snd_soc_codec *codec)
3469{
3470 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3471
3472 if (!wm8994->jackdet)
3473 return;
3474
3475 mutex_lock(&wm8994->accdet_lock);
3476
3477 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3478
3479 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3480
3481 mutex_unlock(&wm8994->accdet_lock);
3482
3483 if (wm8994->wm8994->pdata.jd_ext_cap)
3484 snd_soc_dapm_disable_pin(&codec->dapm,
3485 "MICBIAS2");
3486}
3487
78b76dbe 3488static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3489{
821edd2f 3490 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3491 int report;
821edd2f 3492
78b76dbe
MB		 3493 report = 0;
3494 if (status & 0x4)
3495 report |= SND_JACK_BTN_0;
3496
3497 if (status & 0x8)
3498 report |= SND_JACK_BTN_1;
3499
3500 if (status & 0x10)
3501 report |= SND_JACK_BTN_2;
3502
3503 if (status & 0x20)
3504 report |= SND_JACK_BTN_3;
3505
3506 if (status & 0x40)
3507 report |= SND_JACK_BTN_4;
3508
3509 if (status & 0x80)
3510 report |= SND_JACK_BTN_5;
3511
3512 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3513 wm8994->btn_mask);
3514}
3515
98869f68 3516static void wm8958_mic_id(void *data, u16 status)
78b76dbe 3517{
98869f68 3518 struct snd_soc_codec *codec = data;
78b76dbe 3519 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3520
af6b6fe4 3521 /* Either nothing present or just starting detection */
b00adf76 3522 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB		 3523 /* If nothing present then clear our statuses */
3524 dev_dbg(codec->dev, "Detected open circuit\n");
3525 wm8994->jack_mic = false;
3526 wm8994->mic_detecting = true;
b00adf76 3527
f02b0de0 3528 wm1811_micd_stop(codec);
b00adf76 3529
f02b0de0
MB		 3530 wm8958_micd_set_rate(codec);
3531
3532 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3533 wm8994->btn_mask |
3534 SND_JACK_HEADSET);
b00adf76
MB		 3535 return;
3536 }
821edd2f 3537
b00adf76
MB		 3538 /* If the measurement is showing a high impedence we've got a
3539 * microphone.
3540 */
78b76dbe 3541 if (status & 0x600) {
b00adf76
MB		 3542 dev_dbg(codec->dev, "Detected microphone\n");
3543
157a75e6 3544 wm8994->mic_detecting = false;
b00adf76
MB		 3545 wm8994->jack_mic = true;
3546
3547 wm8958_micd_set_rate(codec);
3548
3549 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3550 SND_JACK_HEADSET);
3551 }
821edd2f 3552
b00adf76 3553
78b76dbe 3554 if (status & 0xfc) {
b00adf76 3555 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3556 wm8994->mic_detecting = false;
b00adf76
MB		 3557
3558 wm8958_micd_set_rate(codec);
3559
af6b6fe4 3560 /* If we have jackdet that will detect removal */
f02b0de0 3561 wm1811_micd_stop(codec);
ecd1732f
MB		 3562
3563 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3564 SND_JACK_HEADSET);
b00adf76 3565 }
821edd2f 3566}
b00adf76 3567
c0cc3f16
MB		 3568/* Deferred mic detection to allow for extra settling time */
3569static void wm1811_mic_work(struct work_struct *work)
3570{
3571 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3572 mic_work.work);
d9dd4ada 3573 struct wm8994 *control = wm8994->wm8994;
c0cc3f16 3574 struct snd_soc_codec *codec = wm8994->hubs.codec;
4585790d 3575
c0cc3f16 3576 pm_runtime_get_sync(codec->dev);
4585790d 3577
c0cc3f16 3578 /* If required for an external cap force MICBIAS on */
d9dd4ada 3579 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3580 snd_soc_dapm_force_enable_pin(&codec->dapm,
3581 "MICBIAS2");
3582 snd_soc_dapm_sync(&codec->dapm);
3583 }
4585790d 3584
c0cc3f16 3585 mutex_lock(&wm8994->accdet_lock);
4585790d 3586
c0cc3f16 3587 dev_dbg(codec->dev, "Starting mic detection\n");
4585790d 3588
63dd5452
MB		 3589 /* Use a user-supplied callback if we have one */
3590 if (wm8994->micd_cb) {
3591 wm8994->micd_cb(wm8994->micd_cb_data);
3592 } else {
3593 /*
3594 * Start off measument of microphone impedence to find out
3595 * what's actually there.
3596 */
3597 wm8994->mic_detecting = true;
3598 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
4585790d 3599
63dd5452
MB		 3600 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3601 WM8958_MICD_ENA, WM8958_MICD_ENA);
b00adf76 3602 }
c0cc3f16
MB		 3603
3604 mutex_unlock(&wm8994->accdet_lock);
3605
3606 pm_runtime_put(codec->dev);
821edd2f
MB		 3607}
3608
af6b6fe4
MB		 3609static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3610{
3611 struct wm8994_priv *wm8994 = data;
d9dd4ada 3612 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3613 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3614 int reg, delay;
c986564b 3615 bool present;
af6b6fe4 3616
b8176627
MB		 3617 pm_runtime_get_sync(codec->dev);
3618
af6b6fe4
MB		 3619 mutex_lock(&wm8994->accdet_lock);
3620
3621 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3622 if (reg < 0) {
3623 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3624 mutex_unlock(&wm8994->accdet_lock);
b8176627 3625 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3626 return IRQ_NONE;
3627 }
3628
3629 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3630
c986564b 3631 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3632
c986564b
MB		 3633 if (present) {
3634 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3635
e9d9a968
MB		 3636 wm8958_micd_set_rate(codec);
3637
55a27786
MB		 3638 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3639 WM8958_MICB2_DISCH, 0);
3640
378ec0ca
MB		 3641 /* Disable debounce while inserted */
3642 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3643 WM1811_JACKDET_DB, 0);
3644
d9dd4ada 3645 delay = control->pdata.micdet_delay;
c0cc3f16
MB		 3646 schedule_delayed_work(&wm8994->mic_work,
3647 msecs_to_jiffies(delay));
af6b6fe4
MB		 3648 } else {
3649 dev_dbg(codec->dev, "Jack not detected\n");
3650
c0cc3f16
MB		 3651 cancel_delayed_work_sync(&wm8994->mic_work);
3652
55a27786
MB		 3653 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3654 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3655
378ec0ca
MB		 3656 /* Enable debounce while removed */
3657 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3658 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3659
af6b6fe4
MB		 3660 wm8994->mic_detecting = false;
3661 wm8994->jack_mic = false;
3662 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3663 WM8958_MICD_ENA, 0);
3664 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3665 }
3666
3667 mutex_unlock(&wm8994->accdet_lock);
3668
c0cc3f16 3669 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3670 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3671 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3672
3673 if (present)
3674 snd_soc_jack_report(wm8994->micdet[0].jack,
3675 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3676 else
3677 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3678 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3679 wm8994->btn_mask);
3680
99af79df
MB		 3681 /* Since we only report deltas force an update, ensures we
3682 * avoid bootstrapping issues with the core. */
3683 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3684
b8176627 3685 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3686 return IRQ_HANDLED;
3687}
3688
99af79df
MB		 3689static void wm1811_jackdet_bootstrap(struct work_struct *work)
3690{
3691 struct wm8994_priv *wm8994 = container_of(work,
3692 struct wm8994_priv,
3693 jackdet_bootstrap.work);
3694 wm1811_jackdet_irq(0, wm8994);
3695}
3696
821edd2f
MB		 3697/**
3698 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3699 *
3700 * @codec: WM8958 codec
3701 * @jack: jack to report detection events on
3702 *
3703 * Enable microphone detection functionality for the WM8958. By
3704 * default simple detection which supports the detection of up to 6
3705 * buttons plus video and microphone functionality is supported.
3706 *
3707 * The WM8958 has an advanced jack detection facility which is able to
3708 * support complex accessory detection, especially when used in
3709 * conjunction with external circuitry. In order to provide maximum
3710 * flexiblity a callback is provided which allows a completely custom
3711 * detection algorithm.
3712 */
3713int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
98869f68
MB		 3714 wm1811_micdet_cb det_cb, void *det_cb_data,
3715 wm1811_mic_id_cb id_cb, void *id_cb_data)
821edd2f
MB		 3716{
3717 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3718 struct wm8994 *control = wm8994->wm8994;
4585790d 3719 u16 micd_lvl_sel;
821edd2f 3720
81204c84
MB		 3721 switch (control->type) {
3722 case WM1811:
3723 case WM8958:
3724 break;
3725 default:
821edd2f 3726 return -EINVAL;
81204c84 3727 }
821edd2f
MB		 3728
3729 if (jack) {
4cdf5e49 3730 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3731 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3732
821edd2f 3733 wm8994->micdet[0].jack = jack;
821edd2f 3734
98869f68
MB		 3735 if (det_cb) {
3736 wm8994->micd_cb = det_cb;
3737 wm8994->micd_cb_data = det_cb_data;
63dd5452
MB		 3738 } else {
3739 wm8994->mic_detecting = true;
3740 wm8994->jack_mic = false;
3741 }
b00adf76 3742
98869f68
MB		 3743 if (id_cb) {
3744 wm8994->mic_id_cb = id_cb;
3745 wm8994->mic_id_cb_data = id_cb_data;
3746 } else {
3747 wm8994->mic_id_cb = wm8958_mic_id;
3748 wm8994->mic_id_cb_data = codec;
3749 }
b00adf76
MB		 3750
3751 wm8958_micd_set_rate(codec);
3752
4585790d 3753 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3754 if (control->pdata.micd_lvl_sel)
3755 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3756 else
3757 micd_lvl_sel = 0x41;
3758
3759 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3760 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3761 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3762
b00adf76 3763 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3764 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3765
af6b6fe4
MB		 3766 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3767
3768 /*
3769 * If we can use jack detection start off with that,
3770 * otherwise jump straight to microphone detection.
3771 */
3772 if (wm8994->jackdet) {
99af79df
MB		 3773 /* Disable debounce for the initial detect */
3774 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3775 WM1811_JACKDET_DB, 0);
3776
55a27786
MB		 3777 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3778 WM8958_MICB2_DISCH,
3779 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3780 snd_soc_update_bits(codec, WM8994_LDO_1,
3781 WM8994_LDO1_DISCH, 0);
3782 wm1811_jackdet_set_mode(codec,
3783 WM1811_JACKDET_MODE_JACK);
3784 } else {
3785 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3786 WM8958_MICD_ENA, WM8958_MICD_ENA);
3787 }
3788
821edd2f
MB		 3789 } else {
3790 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3791 WM8958_MICD_ENA, 0);
afaf1591 3792 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3793 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3794 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3795 }
3796
3797 return 0;
3798}
3799EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3800
3801static irqreturn_t wm8958_mic_irq(int irq, void *data)
3802{
3803 struct wm8994_priv *wm8994 = data;
8cb8e83b 3804 struct snd_soc_codec *codec = wm8994->hubs.codec;
8afd0ef2 3805 int reg, count, ret;
821edd2f 3806
af6b6fe4
MB		 3807 /*
3808 * Jack detection may have detected a removal simulataneously
3809 * with an update of the MICDET status; if so it will have
3810 * stopped detection and we can ignore this interrupt.
3811 */
c986564b 3812 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3813 return IRQ_HANDLED;
af6b6fe4 3814
b8176627
MB		 3815 pm_runtime_get_sync(codec->dev);
3816
19940b3d
MB		 3817 /* We may occasionally read a detection without an impedence
3818 * range being provided - if that happens loop again.
3819 */
3820 count = 10;
3821 do {
3822 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3823 if (reg < 0) {
3824 dev_err(codec->dev,
3825 "Failed to read mic detect status: %d\n",
3826 reg);
b8176627 3827 pm_runtime_put(codec->dev);
19940b3d
MB		 3828 return IRQ_NONE;
3829 }
821edd2f 3830
19940b3d
MB		 3831 if (!(reg & WM8958_MICD_VALID)) {
3832 dev_dbg(codec->dev, "Mic detect data not valid\n");
3833 goto out;
3834 }
3835
3836 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3837 break;
3838
3839 msleep(1);
3840 } while (count--);
3841
3842 if (count == 0)
ec8f53fb 3843 dev_warn(codec->dev, "No impedance range reported for jack\n");
821edd2f 3844
7116f452 3845#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3846 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3847#endif
2bbb5d66 3848
e874de43
MB		 3849 /* Avoid a transient report when the accessory is being removed */
3850 if (wm8994->jackdet) {
8afd0ef2
MB		 3851 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3852 if (ret < 0) {
e874de43 3853 dev_err(codec->dev, "Failed to read jack status: %d\n",
8afd0ef2
MB		 3854 ret);
3855 } else if (!(ret & WM1811_JACKDET_LVL)) {
e874de43
MB		 3856 dev_dbg(codec->dev, "Ignoring removed jack\n");
3857 return IRQ_HANDLED;
3858 }
3859 }
3860
78b76dbe 3861 if (wm8994->mic_detecting)
98869f68 3862 wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg);
821edd2f 3863 else
78b76dbe 3864 wm8958_button_det(codec, reg);
821edd2f
MB		 3865
3866out:
b8176627 3867 pm_runtime_put(codec->dev);
821edd2f
MB		 3868 return IRQ_HANDLED;
3869}
3870
3b1af3f8
MB		 3871static irqreturn_t wm8994_fifo_error(int irq, void *data)
3872{
3873 struct snd_soc_codec *codec = data;
3874
3875 dev_err(codec->dev, "FIFO error\n");
3876
3877 return IRQ_HANDLED;
3878}
3879
f0b182b0
MB		 3880static irqreturn_t wm8994_temp_warn(int irq, void *data)
3881{
3882 struct snd_soc_codec *codec = data;
3883
3884 dev_err(codec->dev, "Thermal warning\n");
3885
3886 return IRQ_HANDLED;
3887}
3888
3889static irqreturn_t wm8994_temp_shut(int irq, void *data)
3890{
3891 struct snd_soc_codec *codec = data;
3892
3893 dev_crit(codec->dev, "Thermal shutdown\n");
3894
3895 return IRQ_HANDLED;
3896}
3897
f0fba2ad 3898static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3899{
d9a7666f 3900 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3901 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3902 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3903 unsigned int reg;
ec62dbd7 3904 int ret, i;
9e6e96a1 3905
8cb8e83b 3906 wm8994->hubs.codec = codec;
d9a7666f 3907 codec->control_data = control->regmap;
9e6e96a1 3908
d9a7666f 3909 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3910
af6b6fe4 3911 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3912 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3913 wm1811_jackdet_bootstrap);
af6b6fe4 3914
c0cc3f16
MB		 3915 switch (control->type) {
3916 case WM8994:
3917 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3918 break;
3919 case WM1811:
3920 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3921 break;
3922 default:
3923 break;
3924 }
3925
c7ebf932
MB		 3926 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3927 init_completion(&wm8994->fll_locked[i]);
3928
d9dd4ada 3929 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 3930
39fb51a1 3931 pm_runtime_enable(codec->dev);
5fab5174 3932 pm_runtime_idle(codec->dev);
39fb51a1 3933
f959dee9
MB		 3934 /* By default use idle_bias_off, will override for WM8994 */
3935 codec->dapm.idle_bias_off = 1;
3936
9e6e96a1 3937 /* Set revision-specific configuration */
3a423157
MB		 3938 switch (control->type) {
3939 case WM8994:
f959dee9 3940 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 3941 if (!control->pdata.lineout1_diff ||
3942 !control->pdata.lineout2_diff)
f959dee9
MB		 3943 codec->dapm.idle_bias_off = 0;
3944
da445afe 3945 switch (control->revision) {
3a423157
MB		 3946 case 2:
3947 case 3:
4537c4e7
MB		 3948 wm8994->hubs.dcs_codes_l = -5;
3949 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3950 wm8994->hubs.hp_startup_mode = 1;
3951 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3952 wm8994->hubs.series_startup = 1;
3a423157
MB		 3953 break;
3954 default:
79ef0abc 3955 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3956 break;
3957 }
280ec8b7 3958 break;
3a423157
MB		 3959
3960 case WM8958:
8437f700 3961 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3962 wm8994->hubs.hp_startup_mode = 1;
20dc24a9 3963
da445afe 3964 switch (control->revision) {
20dc24a9
MB		 3965 case 0:
3966 break;
3967 default:
3968 wm8994->fll_byp = true;
3969 break;
3970 }
9e6e96a1 3971 break;
3a423157 3972
81204c84
MB		 3973 case WM1811:
3974 wm8994->hubs.dcs_readback_mode = 2;
3975 wm8994->hubs.no_series_update = 1;
29fdc360 3976 wm8994->hubs.hp_startup_mode = 1;
af31a227 3977 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 3978 wm8994->fll_byp = true;
81204c84 3979
72222be3
MB		 3980 wm8994->hubs.dcs_codes_l = -9;
3981 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3982
3983 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3984 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3985 break;
3986
9e6e96a1
MB		 3987 default:
3988 break;
3989 }
9e6e96a1 3990
2a8a856d 3991 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3992 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3993 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3994 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3995 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3996 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3997
2a8a856d 3998 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3999 wm_hubs_dcs_done, "DC servo done",
4000 &wm8994->hubs);
4001 if (ret == 0)
4002 wm8994->hubs.dcs_done_irq = true;
4003
3a423157
MB		 4004 switch (control->type) {
4005 case WM8994:
9b7c525d
MB		 4006 if (wm8994->micdet_irq) {
4007 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4008 wm8994_mic_irq,
4009 IRQF_TRIGGER_RISING,
4010 "Mic1 detect",
4011 wm8994);
4012 if (ret != 0)
4013 dev_warn(codec->dev,
4014 "Failed to request Mic1 detect IRQ: %d\n",
4015 ret);
4016 }
3a423157 4017
2a8a856d 4018 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4019 WM8994_IRQ_MIC1_SHRT,
4020 wm8994_mic_irq, "Mic 1 short",
4021 wm8994);
4022 if (ret != 0)
4023 dev_warn(codec->dev,
4024 "Failed to request Mic1 short IRQ: %d\n",
4025 ret);
4026
2a8a856d 4027 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4028 WM8994_IRQ_MIC2_DET,
4029 wm8994_mic_irq, "Mic 2 detect",
4030 wm8994);
4031 if (ret != 0)
4032 dev_warn(codec->dev,
4033 "Failed to request Mic2 detect IRQ: %d\n",
4034 ret);
4035
2a8a856d 4036 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4037 WM8994_IRQ_MIC2_SHRT,
4038 wm8994_mic_irq, "Mic 2 short",
4039 wm8994);
4040 if (ret != 0)
4041 dev_warn(codec->dev,
4042 "Failed to request Mic2 short IRQ: %d\n",
4043 ret);
4044 break;
821edd2f
MB		 4045
4046 case WM8958:
81204c84 4047 case WM1811:
9b7c525d
MB		 4048 if (wm8994->micdet_irq) {
4049 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4050 wm8958_mic_irq,
4051 IRQF_TRIGGER_RISING,
4052 "Mic detect",
4053 wm8994);
4054 if (ret != 0)
4055 dev_warn(codec->dev,
4056 "Failed to request Mic detect IRQ: %d\n",
4057 ret);
b4046d01
MB		 4058 } else {
4059 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4060 wm8958_mic_irq, "Mic detect",
4061 wm8994);
9b7c525d 4062 }
3a423157 4063 }
88766984 4064
af6b6fe4
MB		 4065 switch (control->type) {
4066 case WM1811:
da445afe 4067 if (control->cust_id > 1 || control->revision > 1) {
af6b6fe4
MB		 4068 ret = wm8994_request_irq(wm8994->wm8994,
4069 WM8994_IRQ_GPIO(6),
4070 wm1811_jackdet_irq, "JACKDET",
4071 wm8994);
4072 if (ret == 0)
4073 wm8994->jackdet = true;
4074 }
4075 break;
4076 default:
4077 break;
4078 }
4079
c7ebf932
MB		 4080 wm8994->fll_locked_irq = true;
4081 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 4082 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 4083 WM8994_IRQ_FLL1_LOCK + i,
4084 wm8994_fll_locked_irq, "FLL lock",
4085 &wm8994->fll_locked[i]);
4086 if (ret != 0)
4087 wm8994->fll_locked_irq = false;
4088 }
4089
27060b3c
MB		 4090 /* Make sure we can read from the GPIOs if they're inputs */
4091 pm_runtime_get_sync(codec->dev);
4092
9e6e96a1
MB		 4093 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4094 * configured on init - if a system wants to do this dynamically
4095 * at runtime we can deal with that then.
4096 */
d9a7666f 4097 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 4098 if (ret < 0) {
4099 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4100 goto err_irq;
9e6e96a1 4101 }
d9a7666f 4102 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4103 wm8994->lrclk_shared[0] = 1;
4104 wm8994_dai[0].symmetric_rates = 1;
4105 } else {
4106 wm8994->lrclk_shared[0] = 0;
4107 }
4108
d9a7666f 4109 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4110 if (ret < 0) {
4111 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4112 goto err_irq;
9e6e96a1 4113 }
d9a7666f 4114 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4115 wm8994->lrclk_shared[1] = 1;
4116 wm8994_dai[1].symmetric_rates = 1;
4117 } else {
4118 wm8994->lrclk_shared[1] = 0;
4119 }
4120
27060b3c
MB		 4121 pm_runtime_put(codec->dev);
4122
bfd37bb5
MB		 4123 /* Latch volume update bits */
4124 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4125 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4126 wm8994_vu_bits[i].mask,
4127 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4128
4129 /* Set the low bit of the 3D stereo depth so TLV matches */
4130 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4131 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4132 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4133 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4134 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4135 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4136 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4137 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4138 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4139
5b739670
MB		 4140 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4141 * use this; it only affects behaviour on idle TDM clock
4142 * cycles. */
4143 switch (control->type) {
4144 case WM8994:
4145 case WM8958:
4146 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4147 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4148 break;
4149 default:
4150 break;
4151 }
d1ce6b20 4152
500fa30e
MB		 4153 /* Put MICBIAS into bypass mode by default on newer devices */
4154 switch (control->type) {
4155 case WM8958:
4156 case WM1811:
4157 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4158 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4159 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4160 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4161 break;
4162 default:
4163 break;
4164 }
4165
c340304d
MB		 4166 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4167 wm_hubs_update_class_w(codec);
9e6e96a1 4168
f0fba2ad 4169 wm8994_handle_pdata(wm8994);
9e6e96a1 4170
f0fba2ad 4171 wm_hubs_add_analogue_controls(codec);
022658be 4172 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4173 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4174 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4175 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4176
4177 switch (control->type) {
4178 case WM8994:
4179 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4180 ARRAY_SIZE(wm8994_specific_dapm_widgets));
da445afe 4181 if (control->revision < 4) {
173efa09
DP		 4182 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4183 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4184 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4185 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4186 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4187 ARRAY_SIZE(wm8994_dac_revd_widgets));
4188 } else {
173efa09
DP		 4189 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4190 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4191 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4192 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4193 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4194 ARRAY_SIZE(wm8994_dac_widgets));
4195 }
c4431df0
MB		 4196 break;
4197 case WM8958:
022658be 4198 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4199 ARRAY_SIZE(wm8958_snd_controls));
4200 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4201 ARRAY_SIZE(wm8958_dapm_widgets));
da445afe 4202 if (control->revision < 1) {
780e2806
MB		 4203 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4204 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4205 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4206 ARRAY_SIZE(wm8994_adc_revd_widgets));
4207 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4208 ARRAY_SIZE(wm8994_dac_revd_widgets));
4209 } else {
4210 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4211 ARRAY_SIZE(wm8994_lateclk_widgets));
4212 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4213 ARRAY_SIZE(wm8994_adc_widgets));
4214 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4215 ARRAY_SIZE(wm8994_dac_widgets));
4216 }
c4431df0 4217 break;
81204c84
MB		 4218
4219 case WM1811:
022658be 4220 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4221 ARRAY_SIZE(wm8958_snd_controls));
4222 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4223 ARRAY_SIZE(wm8958_dapm_widgets));
4224 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4225 ARRAY_SIZE(wm8994_lateclk_widgets));
4226 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4227 ARRAY_SIZE(wm8994_adc_widgets));
4228 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4229 ARRAY_SIZE(wm8994_dac_widgets));
4230 break;
c4431df0 4231 }
c4431df0 4232
f0fba2ad 4233 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4234 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4235
c4431df0
MB		 4236 switch (control->type) {
4237 case WM8994:
4238 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4239 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4240
da445afe 4241 if (control->revision < 4) {
6ed8f148
MB		 4242 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4243 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4244 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4245 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4246 } else {
4247 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4248 ARRAY_SIZE(wm8994_lateclk_intercon));
4249 }
c4431df0
MB		 4250 break;
4251 case WM8958:
da445afe 4252 if (control->revision < 1) {
15676937
CR		 4253 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4254 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4255 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4256 ARRAY_SIZE(wm8994_revd_intercon));
4257 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4258 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4259 } else {
4260 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4261 ARRAY_SIZE(wm8994_lateclk_intercon));
4262 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4263 ARRAY_SIZE(wm8958_intercon));
4264 }
f701a2e5
MB		 4265
4266 wm8958_dsp2_init(codec);
c4431df0 4267 break;
81204c84
MB		 4268 case WM1811:
4269 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4270 ARRAY_SIZE(wm8994_lateclk_intercon));
4271 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4272 ARRAY_SIZE(wm8958_intercon));
4273 break;
c4431df0
MB		 4274 }
4275
9e6e96a1
MB		 4276 return 0;
4277
88766984 4278err_irq:
af6b6fe4
MB		 4279 if (wm8994->jackdet)
4280 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4281 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4282 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4283 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4284 if (wm8994->micdet_irq)
4285 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4286 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4287 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4288 &wm8994->fll_locked[i]);
2a8a856d 4289 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4290 &wm8994->hubs);
2a8a856d
MB		 4291 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4292 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4293 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4294
9e6e96a1
MB		 4295 return ret;
4296}
4297
34ff0f95 4298static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4299{
f0fba2ad 4300 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4301 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4302 int i;
9e6e96a1
MB		 4303
4304 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4305
39fb51a1
MB		 4306 pm_runtime_disable(codec->dev);
4307
c7ebf932 4308 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4309 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4310 &wm8994->fll_locked[i]);
4311
2a8a856d 4312 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4313 &wm8994->hubs);
2a8a856d
MB		 4314 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4315 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4316 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4317
af6b6fe4
MB		 4318 if (wm8994->jackdet)
4319 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4320
3a423157
MB		 4321 switch (control->type) {
4322 case WM8994:
9b7c525d
MB		 4323 if (wm8994->micdet_irq)
4324 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4325 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4326 wm8994);
2a8a856d 4327 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4328 wm8994);
2a8a856d 4329 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4330 wm8994);
4331 break;
821edd2f 4332
81204c84 4333 case WM1811:
821edd2f 4334 case WM8958:
9b7c525d
MB		 4335 if (wm8994->micdet_irq)
4336 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4337 break;
3a423157 4338 }
34ff0f95
JJ		 4339 release_firmware(wm8994->mbc);
4340 release_firmware(wm8994->mbc_vss);
4341 release_firmware(wm8994->enh_eq);
24fb2b11 4342 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4343 return 0;
4344}
4345
f0fba2ad
LG		 4346static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4347 .probe = wm8994_codec_probe,
4348 .remove = wm8994_codec_remove,
4752a887
MB		 4349 .suspend = wm8994_codec_suspend,
4350 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4351 .set_bias_level = wm8994_set_bias_level,
4352};
4353
7a79e94e 4354static int wm8994_probe(struct platform_device *pdev)
f0fba2ad 4355{
2bc16ed8
MB		 4356 struct wm8994_priv *wm8994;
4357
4358 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4359 GFP_KERNEL);
4360 if (wm8994 == NULL)
4361 return -ENOMEM;
4362 platform_set_drvdata(pdev, wm8994);
4363
4364 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4365
f0fba2ad
LG		 4366 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4367 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4368}
4369
7a79e94e 4370static int wm8994_remove(struct platform_device *pdev)
f0fba2ad
LG		 4371{
4372 snd_soc_unregister_codec(&pdev->dev);
4373 return 0;
4374}
4375
4752a887
MB		 4376#ifdef CONFIG_PM_SLEEP
4377static int wm8994_suspend(struct device *dev)
4378{
4379 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4380
4381 /* Drop down to power saving mode when system is suspended */
4382 if (wm8994->jackdet && !wm8994->active_refcount)
4383 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4384 WM1811_JACKDET_MODE_MASK,
4385 wm8994->jackdet_mode);
4386
4387 return 0;
4388}
4389
4390static int wm8994_resume(struct device *dev)
4391{
4392 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4393
78b76dbe 4394 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB		 4395 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4396 WM1811_JACKDET_MODE_MASK,
4397 WM1811_JACKDET_MODE_AUDIO);
4398
4399 return 0;
4400}
4401#endif
4402
4403static const struct dev_pm_ops wm8994_pm_ops = {
4404 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4405};
4406
9e6e96a1
MB		 4407static struct platform_driver wm8994_codec_driver = {
4408 .driver = {
4752a887
MB		 4409 .name = "wm8994-codec",
4410 .owner = THIS_MODULE,
4411 .pm = &wm8994_pm_ops,
4412 },
f0fba2ad 4413 .probe = wm8994_probe,
7a79e94e 4414 .remove = wm8994_remove,
9e6e96a1
MB		 4415};
4416
5bbcc3c0 4417module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4418
4419MODULE_DESCRIPTION("ASoC WM8994 driver");
4420MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4421MODULE_LICENSE("GPL");
4422MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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