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Merge remote-tracking branch 'regulator/topic/arizona' into regulator-next
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
bfd37bb5
MB		 49static struct {
50 unsigned int reg;
51 unsigned int mask;
52} wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80};
81
9e6e96a1
MB		 82static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86};
87
88static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92};
93
af6b6fe4 94static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 95 { 32768, true, 1, 4 },
96 { 32768, false, 1, 1 },
604533de
MB		 97 { 44100 * 256, true, 7, 10 },
98 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 99};
100
af6b6fe4
MB		 101static const struct wm8958_micd_rate jackdet_rates[] = {
102 { 32768, true, 0, 1 },
103 { 32768, false, 0, 1 },
e9d9a968
MB		 104 { 44100 * 256, true, 10, 10 },
105 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 106};
107
b00adf76
MB		 108static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
109{
110 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 111 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 112 int best, i, sysclk, val;
113 bool idle;
af6b6fe4
MB		 114 const struct wm8958_micd_rate *rates;
115 int num_rates;
b00adf76 116
b00adf76
MB		 117 idle = !wm8994->jack_mic;
118
119 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
120 if (sysclk & WM8994_SYSCLK_SRC)
121 sysclk = wm8994->aifclk[1];
122 else
123 sysclk = wm8994->aifclk[0];
124
d9dd4ada
MB		 125 if (control->pdata.micd_rates) {
126 rates = control->pdata.micd_rates;
127 num_rates = control->pdata.num_micd_rates;
cd1707a9 128 } else if (wm8994->jackdet) {
af6b6fe4
MB		 129 rates = jackdet_rates;
130 num_rates = ARRAY_SIZE(jackdet_rates);
131 } else {
132 rates = micdet_rates;
133 num_rates = ARRAY_SIZE(micdet_rates);
134 }
135
b00adf76 136 best = 0;
af6b6fe4
MB		 137 for (i = 0; i < num_rates; i++) {
138 if (rates[i].idle != idle)
b00adf76 139 continue;
af6b6fe4
MB		 140 if (abs(rates[i].sysclk - sysclk) <
141 abs(rates[best].sysclk - sysclk))
b00adf76 142 best = i;
af6b6fe4 143 else if (rates[best].idle != idle)
b00adf76
MB		 144 best = i;
145 }
146
af6b6fe4
MB		 147 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
148 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 149
3a334ada
MB		 150 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
151 rates[best].start, rates[best].rate, sysclk,
152 idle ? "idle" : "active");
153
b00adf76
MB		 154 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
155 WM8958_MICD_BIAS_STARTTIME_MASK |
156 WM8958_MICD_RATE_MASK, val);
157}
158
9e6e96a1
MB		 159static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
160{
b2c812e2 161 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 162 int rate;
163 int reg1 = 0;
164 int offset;
165
166 if (aif)
167 offset = 4;
168 else
169 offset = 0;
170
171 switch (wm8994->sysclk[aif]) {
172 case WM8994_SYSCLK_MCLK1:
173 rate = wm8994->mclk[0];
174 break;
175
176 case WM8994_SYSCLK_MCLK2:
177 reg1 |= 0x8;
178 rate = wm8994->mclk[1];
179 break;
180
181 case WM8994_SYSCLK_FLL1:
182 reg1 |= 0x10;
183 rate = wm8994->fll[0].out;
184 break;
185
186 case WM8994_SYSCLK_FLL2:
187 reg1 |= 0x18;
188 rate = wm8994->fll[1].out;
189 break;
190
191 default:
192 return -EINVAL;
193 }
194
195 if (rate >= 13500000) {
196 rate /= 2;
197 reg1 |= WM8994_AIF1CLK_DIV;
198
199 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
200 aif + 1, rate);
201 }
5e5e2bef 202
9e6e96a1
MB		 203 wm8994->aifclk[aif] = rate;
204
205 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
206 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
207 reg1);
208
209 return 0;
210}
211
212static int configure_clock(struct snd_soc_codec *codec)
213{
b2c812e2 214 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 215 int change, new;
9e6e96a1
MB		 216
217 /* Bring up the AIF clocks first */
218 configure_aif_clock(codec, 0);
219 configure_aif_clock(codec, 1);
220
221 /* Then switch CLK_SYS over to the higher of them; a change
222 * can only happen as a result of a clocking change which can
223 * only be made outside of DAPM so we can safely redo the
224 * clocking.
225 */
226
227 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 228 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
229 wm8958_micd_set_rate(codec);
9e6e96a1 230 return 0;
b00adf76 231 }
9e6e96a1
MB		 232
233 if (wm8994->aifclk[0] < wm8994->aifclk[1])
234 new = WM8994_SYSCLK_SRC;
235 else
236 new = 0;
237
04f45c49
AL		 238 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
239 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 240 if (change)
241 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 242
b00adf76
MB		 243 wm8958_micd_set_rate(codec);
244
9e6e96a1
MB		 245 return 0;
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
252 const char *clk;
253
254 /* Check what we're currently using for CLK_SYS */
255 if (reg & WM8994_SYSCLK_SRC)
256 clk = "AIF2CLK";
257 else
258 clk = "AIF1CLK";
259
260 return strcmp(source->name, clk) == 0;
261}
262
263static const char *sidetone_hpf_text[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
265};
266
267static const struct soc_enum sidetone_hpf =
268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
269
146fd574
UK		 270static const char *adc_hpf_text[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
272};
273
274static const struct soc_enum aif1adc1_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
276
277static const struct soc_enum aif1adc2_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
279
280static const struct soc_enum aif2adc_hpf =
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
282
9e6e96a1
MB		 283static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
284static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
285static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
286static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
287static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 288static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 289static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 290
291#define WM8994_DRC_SWITCH(xname, reg, shift) \
292{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
293 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
294 .put = wm8994_put_drc_sw, \
295 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
296
297static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
298 struct snd_ctl_elem_value *ucontrol)
299{
300 struct soc_mixer_control *mc =
301 (struct soc_mixer_control *)kcontrol->private_value;
302 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
303 int mask, ret;
304
305 /* Can't enable both ADC and DAC paths simultaneously */
306 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
307 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
308 WM8994_AIF1ADC1R_DRC_ENA_MASK;
309 else
310 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
311
312 ret = snd_soc_read(codec, mc->reg);
313 if (ret < 0)
314 return ret;
315 if (ret & mask)
316 return -EINVAL;
317
318 return snd_soc_put_volsw(kcontrol, ucontrol);
319}
320
9e6e96a1
MB		 321static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
322{
b2c812e2 323 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 324 struct wm8994 *control = wm8994->wm8994;
325 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 326 int base = wm8994_drc_base[drc];
327 int cfg = wm8994->drc_cfg[drc];
328 int save, i;
329
330 /* Save any enables; the configuration should clear them. */
331 save = snd_soc_read(codec, base);
332 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
333 WM8994_AIF1ADC1R_DRC_ENA;
334
335 for (i = 0; i < WM8994_DRC_REGS; i++)
336 snd_soc_update_bits(codec, base + i, 0xffff,
337 pdata->drc_cfgs[cfg].regs[i]);
338
339 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
340 WM8994_AIF1ADC1L_DRC_ENA |
341 WM8994_AIF1ADC1R_DRC_ENA, save);
342}
343
344/* Icky as hell but saves code duplication */
345static int wm8994_get_drc(const char *name)
346{
347 if (strcmp(name, "AIF1DRC1 Mode") == 0)
348 return 0;
349 if (strcmp(name, "AIF1DRC2 Mode") == 0)
350 return 1;
351 if (strcmp(name, "AIF2DRC Mode") == 0)
352 return 2;
353 return -EINVAL;
354}
355
356static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
357 struct snd_ctl_elem_value *ucontrol)
358{
359 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 360 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 361 struct wm8994 *control = wm8994->wm8994;
362 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 363 int drc = wm8994_get_drc(kcontrol->id.name);
364 int value = ucontrol->value.integer.value[0];
365
366 if (drc < 0)
367 return drc;
368
369 if (value >= pdata->num_drc_cfgs)
370 return -EINVAL;
371
372 wm8994->drc_cfg[drc] = value;
373
374 wm8994_set_drc(codec, drc);
375
376 return 0;
377}
378
379static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
382 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 384 int drc = wm8994_get_drc(kcontrol->id.name);
385
386 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
387
388 return 0;
389}
390
391static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
392{
b2c812e2 393 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 394 struct wm8994 *control = wm8994->wm8994;
395 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 396 int base = wm8994_retune_mobile_base[block];
397 int iface, best, best_val, save, i, cfg;
398
399 if (!pdata || !wm8994->num_retune_mobile_texts)
400 return;
401
402 switch (block) {
403 case 0:
404 case 1:
405 iface = 0;
406 break;
407 case 2:
408 iface = 1;
409 break;
410 default:
411 return;
412 }
413
414 /* Find the version of the currently selected configuration
415 * with the nearest sample rate. */
416 cfg = wm8994->retune_mobile_cfg[block];
417 best = 0;
418 best_val = INT_MAX;
419 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
420 if (strcmp(pdata->retune_mobile_cfgs[i].name,
421 wm8994->retune_mobile_texts[cfg]) == 0 &&
422 abs(pdata->retune_mobile_cfgs[i].rate
423 - wm8994->dac_rates[iface]) < best_val) {
424 best = i;
425 best_val = abs(pdata->retune_mobile_cfgs[i].rate
426 - wm8994->dac_rates[iface]);
427 }
428 }
429
430 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
431 block,
432 pdata->retune_mobile_cfgs[best].name,
433 pdata->retune_mobile_cfgs[best].rate,
434 wm8994->dac_rates[iface]);
435
436 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 437 * current configuration.
9e6e96a1
MB		 438 */
439 save = snd_soc_read(codec, base);
440 save &= WM8994_AIF1DAC1_EQ_ENA;
441
442 for (i = 0; i < WM8994_EQ_REGS; i++)
443 snd_soc_update_bits(codec, base + i, 0xffff,
444 pdata->retune_mobile_cfgs[best].regs[i]);
445
446 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
447}
448
449/* Icky as hell but saves code duplication */
450static int wm8994_get_retune_mobile_block(const char *name)
451{
452 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
453 return 0;
454 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
455 return 1;
456 if (strcmp(name, "AIF2 EQ Mode") == 0)
457 return 2;
458 return -EINVAL;
459}
460
461static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463{
464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 466 struct wm8994 *control = wm8994->wm8994;
467 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 468 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
469 int value = ucontrol->value.integer.value[0];
470
471 if (block < 0)
472 return block;
473
474 if (value >= pdata->num_retune_mobile_cfgs)
475 return -EINVAL;
476
477 wm8994->retune_mobile_cfg[block] = value;
478
479 wm8994_set_retune_mobile(codec, block);
480
481 return 0;
482}
483
484static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
485 struct snd_ctl_elem_value *ucontrol)
486{
487 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 488 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 489 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
490
491 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
492
493 return 0;
494}
495
96b101ef 496static const char *aif_chan_src_text[] = {
f554885f
MB		 497 "Left", "Right"
498};
499
96b101ef
MB		 500static const struct soc_enum aif1adcl_src =
501 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
502
503static const struct soc_enum aif1adcr_src =
504 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
505
506static const struct soc_enum aif2adcl_src =
507 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
508
509static const struct soc_enum aif2adcr_src =
510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
511
f554885f 512static const struct soc_enum aif1dacl_src =
96b101ef 513 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 514
515static const struct soc_enum aif1dacr_src =
96b101ef 516 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 517
518static const struct soc_enum aif2dacl_src =
96b101ef 519 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 520
521static const struct soc_enum aif2dacr_src =
96b101ef 522 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 523
154b26aa
MB		 524static const char *osr_text[] = {
525 "Low Power", "High Performance",
526};
527
528static const struct soc_enum dac_osr =
529 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
530
531static const struct soc_enum adc_osr =
532 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
533
9e6e96a1
MB		 534static const struct snd_kcontrol_new wm8994_snd_controls[] = {
535SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
536 WM8994_AIF1_ADC1_RIGHT_VOLUME,
537 1, 119, 0, digital_tlv),
538SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
539 WM8994_AIF1_ADC2_RIGHT_VOLUME,
540 1, 119, 0, digital_tlv),
541SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
542 WM8994_AIF2_ADC_RIGHT_VOLUME,
543 1, 119, 0, digital_tlv),
544
96b101ef
MB		 545SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
546SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 547SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
548SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 549
f554885f
MB		 550SOC_ENUM("AIF1DACL Source", aif1dacl_src),
551SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 552SOC_ENUM("AIF2DACL Source", aif2dacl_src),
553SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 554
9e6e96a1
MB		 555SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
556 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
557SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
558 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
559SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
560 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561
562SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
563SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
564
565SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
566SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
567SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
568
569WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
570WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
571WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
572
573WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
574WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
575WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
576
577WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
578WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
579WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
580
581SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
582 5, 12, 0, st_tlv),
583SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
584 0, 12, 0, st_tlv),
585SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
590SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
591
146fd574
UK		 592SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
593SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
594
595SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
596SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
597
598SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
599SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
600
154b26aa
MB		 601SOC_ENUM("ADC OSR", adc_osr),
602SOC_ENUM("DAC OSR", dac_osr),
603
9e6e96a1
MB		 604SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
605 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
606SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
607 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
608
609SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
610 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
611SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
612 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
613
614SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
615 6, 1, 1, wm_hubs_spkmix_tlv),
616SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
617 2, 1, 1, wm_hubs_spkmix_tlv),
618
619SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
620 6, 1, 1, wm_hubs_spkmix_tlv),
621SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
622 2, 1, 1, wm_hubs_spkmix_tlv),
623
624SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
625 10, 15, 0, wm8994_3d_tlv),
458350b3 626SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 627 8, 1, 0),
628SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
630SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
631 8, 1, 0),
458350b3 632SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 633 10, 15, 0, wm8994_3d_tlv),
458350b3 634SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 635 8, 1, 0),
636};
637
638static const struct snd_kcontrol_new wm8994_eq_controls[] = {
639SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
640 eq_tlv),
641SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
642 eq_tlv),
643SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
648 eq_tlv),
649
650SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
653 eq_tlv),
654SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
659 eq_tlv),
660
661SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
664 eq_tlv),
665SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
666 eq_tlv),
667SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
668 eq_tlv),
669SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
670 eq_tlv),
671};
672
45a690f6
MB		 673static const struct snd_kcontrol_new wm8994_drc_controls[] = {
674SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
675 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
676 WM8994_AIF1ADC1R_DRC_ENA),
677SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
678 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
679 WM8994_AIF1ADC2R_DRC_ENA),
680SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
681 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
682 WM8994_AIF2ADCR_DRC_ENA),
683};
684
1ddc07d0
MB		 685static const char *wm8958_ng_text[] = {
686 "30ms", "125ms", "250ms", "500ms",
687};
688
689static const struct soc_enum wm8958_aif1dac1_ng_hold =
690 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
691 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
692
693static const struct soc_enum wm8958_aif1dac2_ng_hold =
694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
695 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
696
697static const struct soc_enum wm8958_aif2dac_ng_hold =
698 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
699 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
700
c4431df0
MB		 701static const struct snd_kcontrol_new wm8958_snd_controls[] = {
702SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 703
704SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
705 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
706SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
707SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
708 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
709 7, 1, ng_tlv),
710
711SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
712 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
713SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
714SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
715 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
716 7, 1, ng_tlv),
717
718SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
719 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
720SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
721SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
722 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
723 7, 1, ng_tlv),
c4431df0
MB		 724};
725
81204c84
MB		 726static const struct snd_kcontrol_new wm1811_snd_controls[] = {
727SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
728 mixin_boost_tlv),
729SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
730 mixin_boost_tlv),
731};
732
af6b6fe4
MB		 733/* We run all mode setting through a function to enforce audio mode */
734static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
735{
736 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
737
78b76dbe 738 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
MB		 739 return;
740
af6b6fe4
MB		 741 if (wm8994->active_refcount)
742 mode = WM1811_JACKDET_MODE_AUDIO;
743
4752a887 744 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 745 return;
746
4752a887 747 wm8994->jackdet_mode = mode;
1defde2a 748
4752a887
MB		 749 /* Always use audio mode to detect while the system is active */
750 if (mode != WM1811_JACKDET_MODE_NONE)
751 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 752
4752a887
MB		 753 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
754 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 755}
756
757static void active_reference(struct snd_soc_codec *codec)
758{
759 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
760
761 mutex_lock(&wm8994->accdet_lock);
762
763 wm8994->active_refcount++;
764
765 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
766 wm8994->active_refcount);
767
1defde2a
MB		 768 /* If we're using jack detection go into audio mode */
769 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 770
771 mutex_unlock(&wm8994->accdet_lock);
772}
773
774static void active_dereference(struct snd_soc_codec *codec)
775{
776 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
777 u16 mode;
778
779 mutex_lock(&wm8994->accdet_lock);
780
781 wm8994->active_refcount--;
782
783 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
784 wm8994->active_refcount);
785
786 if (wm8994->active_refcount == 0) {
787 /* Go into appropriate detection only mode */
1defde2a
MB		 788 if (wm8994->jack_mic || wm8994->mic_detecting)
789 mode = WM1811_JACKDET_MODE_MIC;
790 else
791 mode = WM1811_JACKDET_MODE_JACK;
792
793 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 794 }
795
796 mutex_unlock(&wm8994->accdet_lock);
797}
798
9e6e96a1
MB		 799static int clk_sys_event(struct snd_soc_dapm_widget *w,
800 struct snd_kcontrol *kcontrol, int event)
801{
802 struct snd_soc_codec *codec = w->codec;
99af79df 803 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 804
805 switch (event) {
806 case SND_SOC_DAPM_PRE_PMU:
807 return configure_clock(codec);
808
99af79df
MB		 809 case SND_SOC_DAPM_POST_PMU:
810 /*
811 * JACKDET won't run until we start the clock and it
812 * only reports deltas, make sure we notify the state
813 * up the stack on startup. Use a *very* generous
814 * timeout for paranoia, there's no urgency and we
815 * don't want false reports.
816 */
817 if (wm8994->jackdet && !wm8994->clk_has_run) {
818 schedule_delayed_work(&wm8994->jackdet_bootstrap,
819 msecs_to_jiffies(1000));
820 wm8994->clk_has_run = true;
821 }
822 break;
823
9e6e96a1
MB		 824 case SND_SOC_DAPM_POST_PMD:
825 configure_clock(codec);
826 break;
827 }
828
829 return 0;
830}
831
4b7ed83a
MB		 832static void vmid_reference(struct snd_soc_codec *codec)
833{
834 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
835
db966f8a
MB		 836 pm_runtime_get_sync(codec->dev);
837
4b7ed83a
MB		 838 wm8994->vmid_refcount++;
839
840 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
841 wm8994->vmid_refcount);
842
843 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 844 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 845 WM8994_LINEOUT1_DISCH |
22f8d055 846 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 847
f7085641
MB		 848 wm_hubs_vmid_ena(codec);
849
22f8d055
MB		 850 switch (wm8994->vmid_mode) {
851 default:
cbd71f30 852 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 853 case WM8994_VMID_NORMAL:
854 /* Startup bias, VMID ramp & buffer */
855 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
856 WM8994_BIAS_SRC |
857 WM8994_VMID_DISCH |
858 WM8994_STARTUP_BIAS_ENA |
859 WM8994_VMID_BUF_ENA |
860 WM8994_VMID_RAMP_MASK,
861 WM8994_BIAS_SRC |
862 WM8994_STARTUP_BIAS_ENA |
863 WM8994_VMID_BUF_ENA |
a3a1d9d2 864 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 865
866 /* Main bias enable, VMID=2x40k */
867 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
868 WM8994_BIAS_ENA |
869 WM8994_VMID_SEL_MASK,
870 WM8994_BIAS_ENA | 0x2);
871
a3a1d9d2 872 msleep(300);
22f8d055
MB		 873
874 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
875 WM8994_VMID_RAMP_MASK |
876 WM8994_BIAS_SRC,
877 0);
878 break;
cc6d5a8c 879
22f8d055
MB		 880 case WM8994_VMID_FORCE:
881 /* Startup bias, slow VMID ramp & buffer */
882 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
883 WM8994_BIAS_SRC |
884 WM8994_VMID_DISCH |
885 WM8994_STARTUP_BIAS_ENA |
886 WM8994_VMID_BUF_ENA |
887 WM8994_VMID_RAMP_MASK,
888 WM8994_BIAS_SRC |
889 WM8994_STARTUP_BIAS_ENA |
890 WM8994_VMID_BUF_ENA |
891 (0x2 << WM8994_VMID_RAMP_SHIFT));
892
893 /* Main bias enable, VMID=2x40k */
894 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
895 WM8994_BIAS_ENA |
896 WM8994_VMID_SEL_MASK,
897 WM8994_BIAS_ENA | 0x2);
898
899 msleep(400);
900
901 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
902 WM8994_VMID_RAMP_MASK |
903 WM8994_BIAS_SRC,
904 0);
905 break;
906 }
4b7ed83a
MB		 907 }
908}
909
910static void vmid_dereference(struct snd_soc_codec *codec)
911{
912 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
913
914 wm8994->vmid_refcount--;
915
916 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
917 wm8994->vmid_refcount);
918
919 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 920 if (wm8994->hubs.lineout1_se)
921 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
922 WM8994_LINEOUT1N_ENA |
923 WM8994_LINEOUT1P_ENA,
924 WM8994_LINEOUT1N_ENA |
925 WM8994_LINEOUT1P_ENA);
926
927 if (wm8994->hubs.lineout2_se)
928 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
929 WM8994_LINEOUT2N_ENA |
930 WM8994_LINEOUT2P_ENA,
931 WM8994_LINEOUT2N_ENA |
932 WM8994_LINEOUT2P_ENA);
933
934 /* Start discharging VMID */
4b7ed83a
MB		 935 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
936 WM8994_BIAS_SRC |
22f8d055 937 WM8994_VMID_DISCH,
4b7ed83a 938 WM8994_BIAS_SRC |
22f8d055 939 WM8994_VMID_DISCH);
4b7ed83a 940
f95be9d6
MB		 941 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
942 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 943
f95be9d6 944 msleep(400);
e85b26ce 945
22f8d055 946 /* Active discharge */
4b7ed83a
MB		 947 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
948 WM8994_LINEOUT1_DISCH |
949 WM8994_LINEOUT2_DISCH,
950 WM8994_LINEOUT1_DISCH |
951 WM8994_LINEOUT2_DISCH);
952
22f8d055
MB		 953 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
954 WM8994_LINEOUT1N_ENA |
955 WM8994_LINEOUT1P_ENA |
956 WM8994_LINEOUT2N_ENA |
957 WM8994_LINEOUT2P_ENA, 0);
958
4b7ed83a
MB		 959 /* Switch off startup biases */
960 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
961 WM8994_BIAS_SRC |
962 WM8994_STARTUP_BIAS_ENA |
963 WM8994_VMID_BUF_ENA |
964 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 965
966 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 967 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 968 }
db966f8a
MB		 969
970 pm_runtime_put(codec->dev);
4b7ed83a
MB		 971}
972
973static int vmid_event(struct snd_soc_dapm_widget *w,
974 struct snd_kcontrol *kcontrol, int event)
975{
976 struct snd_soc_codec *codec = w->codec;
977
978 switch (event) {
979 case SND_SOC_DAPM_PRE_PMU:
980 vmid_reference(codec);
981 break;
982
983 case SND_SOC_DAPM_POST_PMD:
984 vmid_dereference(codec);
985 break;
986 }
987
988 return 0;
989}
990
c340304d 991static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 992{
9e6e96a1
MB		 993 int source = 0; /* GCC flow analysis can't track enable */
994 int reg, reg_r;
995
c340304d 996 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 997 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
998 switch (reg) {
999 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1000 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1001 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1002 break;
1003 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1004 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1005 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1006 break;
1007 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1008 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1009 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010 break;
1011 default:
ee839a21 1012 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1013 return false;
9e6e96a1
MB		 1014 }
1015
1016 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1017 if (reg_r != reg) {
ee839a21 1018 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1019 return false;
9e6e96a1
MB		 1020 }
1021
c340304d
MB		 1022 /* Set the source up */
1023 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1024 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1025
c340304d 1026 return true;
9e6e96a1
MB		 1027}
1028
1a38336b
MB		 1029static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1030 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1031{
1032 struct snd_soc_codec *codec = w->codec;
79748cdb 1033 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1a38336b
MB		 1034 struct wm8994 *control = codec->control_data;
1035 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1036 int i;
1a38336b
MB		 1037 int dac;
1038 int adc;
1039 int val;
1040
1041 switch (control->type) {
1042 case WM8994:
1043 case WM8958:
1044 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1045 break;
1046 default:
1047 break;
1048 }
173efa09
DP		 1049
1050 switch (event) {
1051 case SND_SOC_DAPM_PRE_PMU:
79748cdb
MB		 1052 /* Don't enable timeslot 2 if not in use */
1053 if (wm8994->channels[0] <= 2)
1054 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1055
1a38336b
MB		 1056 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1057 if ((val & WM8994_AIF1ADCL_SRC) &&
1058 (val & WM8994_AIF1ADCR_SRC))
1059 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1060 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1061 !(val & WM8994_AIF1ADCR_SRC))
1062 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1063 else
1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1065 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1066
1067 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1068 if ((val & WM8994_AIF1DACL_SRC) &&
1069 (val & WM8994_AIF1DACR_SRC))
1070 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1071 else if (!(val & WM8994_AIF1DACL_SRC) &&
1072 !(val & WM8994_AIF1DACR_SRC))
1073 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1074 else
1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1076 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1077
1078 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1079 mask, adc);
1080 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1081 mask, dac);
1082 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1083 WM8994_AIF1DSPCLK_ENA |
1084 WM8994_SYSDSPCLK_ENA,
1085 WM8994_AIF1DSPCLK_ENA |
1086 WM8994_SYSDSPCLK_ENA);
1087 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1088 WM8994_AIF1ADC1R_ENA |
1089 WM8994_AIF1ADC1L_ENA |
1090 WM8994_AIF1ADC2R_ENA |
1091 WM8994_AIF1ADC2L_ENA);
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1093 WM8994_AIF1DAC1R_ENA |
1094 WM8994_AIF1DAC1L_ENA |
1095 WM8994_AIF1DAC2R_ENA |
1096 WM8994_AIF1DAC2L_ENA);
173efa09 1097 break;
173efa09 1098
bfd37bb5
MB		 1099 case SND_SOC_DAPM_POST_PMU:
1100 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1101 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1102 snd_soc_read(codec,
1103 wm8994_vu_bits[i].reg));
1104 break;
1105
1a38336b
MB		 1106 case SND_SOC_DAPM_PRE_PMD:
1107 case SND_SOC_DAPM_POST_PMD:
1108 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1109 mask, 0);
1110 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1111 mask, 0);
1112
1113 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1114 if (val & WM8994_AIF2DSPCLK_ENA)
1115 val = WM8994_SYSDSPCLK_ENA;
1116 else
1117 val = 0;
1118 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1119 WM8994_SYSDSPCLK_ENA |
1120 WM8994_AIF1DSPCLK_ENA, val);
1121 break;
1122 }
c6b7b570 1123
173efa09
DP		 1124 return 0;
1125}
1126
1a38336b
MB		 1127static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1128 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1129{
1130 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1131 int i;
1a38336b
MB		 1132 int dac;
1133 int adc;
1134 int val;
173efa09
DP		 1135
1136 switch (event) {
1a38336b
MB		 1137 case SND_SOC_DAPM_PRE_PMU:
1138 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1139 if ((val & WM8994_AIF2ADCL_SRC) &&
1140 (val & WM8994_AIF2ADCR_SRC))
1141 adc = WM8994_AIF2ADCR_ENA;
1142 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1143 !(val & WM8994_AIF2ADCR_SRC))
1144 adc = WM8994_AIF2ADCL_ENA;
1145 else
1146 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1147
1148
1149 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1150 if ((val & WM8994_AIF2DACL_SRC) &&
1151 (val & WM8994_AIF2DACR_SRC))
1152 dac = WM8994_AIF2DACR_ENA;
1153 else if (!(val & WM8994_AIF2DACL_SRC) &&
1154 !(val & WM8994_AIF2DACR_SRC))
1155 dac = WM8994_AIF2DACL_ENA;
1156 else
1157 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1158
1159 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1160 WM8994_AIF2ADCL_ENA |
1161 WM8994_AIF2ADCR_ENA, adc);
1162 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1163 WM8994_AIF2DACL_ENA |
1164 WM8994_AIF2DACR_ENA, dac);
1165 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1166 WM8994_AIF2DSPCLK_ENA |
1167 WM8994_SYSDSPCLK_ENA,
1168 WM8994_AIF2DSPCLK_ENA |
1169 WM8994_SYSDSPCLK_ENA);
1170 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1171 WM8994_AIF2ADCL_ENA |
1172 WM8994_AIF2ADCR_ENA,
1173 WM8994_AIF2ADCL_ENA |
1174 WM8994_AIF2ADCR_ENA);
1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1176 WM8994_AIF2DACL_ENA |
1177 WM8994_AIF2DACR_ENA,
1178 WM8994_AIF2DACL_ENA |
1179 WM8994_AIF2DACR_ENA);
1180 break;
1181
bfd37bb5
MB		 1182 case SND_SOC_DAPM_POST_PMU:
1183 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1184 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1185 snd_soc_read(codec,
1186 wm8994_vu_bits[i].reg));
1187 break;
1188
1a38336b 1189 case SND_SOC_DAPM_PRE_PMD:
173efa09 1190 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1191 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1192 WM8994_AIF2DACL_ENA |
1193 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1194 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1195 WM8994_AIF2ADCL_ENA |
1196 WM8994_AIF2ADCR_ENA, 0);
1197
1198 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1199 if (val & WM8994_AIF1DSPCLK_ENA)
1200 val = WM8994_SYSDSPCLK_ENA;
1201 else
1202 val = 0;
1203 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1204 WM8994_SYSDSPCLK_ENA |
1205 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1206 break;
1207 }
1208
1209 return 0;
1210}
1211
1a38336b
MB		 1212static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1213 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1214{
1215 struct snd_soc_codec *codec = w->codec;
1216 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1217
1218 switch (event) {
1219 case SND_SOC_DAPM_PRE_PMU:
1220 wm8994->aif1clk_enable = 1;
1221 break;
a3cff81a
DP		 1222 case SND_SOC_DAPM_POST_PMD:
1223 wm8994->aif1clk_disable = 1;
1224 break;
173efa09
DP		 1225 }
1226
1227 return 0;
1228}
1229
1a38336b
MB		 1230static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1231 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1232{
1233 struct snd_soc_codec *codec = w->codec;
1234 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1235
1236 switch (event) {
1237 case SND_SOC_DAPM_PRE_PMU:
1238 wm8994->aif2clk_enable = 1;
1239 break;
a3cff81a
DP		 1240 case SND_SOC_DAPM_POST_PMD:
1241 wm8994->aif2clk_disable = 1;
1242 break;
173efa09
DP		 1243 }
1244
1245 return 0;
1246}
1247
1a38336b
MB		 1248static int late_enable_ev(struct snd_soc_dapm_widget *w,
1249 struct snd_kcontrol *kcontrol, int event)
1250{
1251 struct snd_soc_codec *codec = w->codec;
1252 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1253
1254 switch (event) {
1255 case SND_SOC_DAPM_PRE_PMU:
1256 if (wm8994->aif1clk_enable) {
c8fdc1b5 1257 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1258 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1259 WM8994_AIF1CLK_ENA_MASK,
1260 WM8994_AIF1CLK_ENA);
c8fdc1b5 1261 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1262 wm8994->aif1clk_enable = 0;
1263 }
1264 if (wm8994->aif2clk_enable) {
c8fdc1b5 1265 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1266 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1267 WM8994_AIF2CLK_ENA_MASK,
1268 WM8994_AIF2CLK_ENA);
c8fdc1b5 1269 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1270 wm8994->aif2clk_enable = 0;
1271 }
1272 break;
1273 }
1274
1275 /* We may also have postponed startup of DSP, handle that. */
1276 wm8958_aif_ev(w, kcontrol, event);
1277
1278 return 0;
1279}
1280
1281static int late_disable_ev(struct snd_soc_dapm_widget *w,
1282 struct snd_kcontrol *kcontrol, int event)
1283{
1284 struct snd_soc_codec *codec = w->codec;
1285 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1286
1287 switch (event) {
1288 case SND_SOC_DAPM_POST_PMD:
1289 if (wm8994->aif1clk_disable) {
c8fdc1b5 1290 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1291 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1292 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1293 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1294 wm8994->aif1clk_disable = 0;
1295 }
1296 if (wm8994->aif2clk_disable) {
c8fdc1b5 1297 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1298 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1299 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1300 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1301 wm8994->aif2clk_disable = 0;
1302 }
1303 break;
1304 }
1305
1306 return 0;
1307}
1308
04d28681
DP		 1309static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1310 struct snd_kcontrol *kcontrol, int event)
1311{
1312 late_enable_ev(w, kcontrol, event);
1313 return 0;
1314}
1315
b462c6e6
DP		 1316static int micbias_ev(struct snd_soc_dapm_widget *w,
1317 struct snd_kcontrol *kcontrol, int event)
1318{
1319 late_enable_ev(w, kcontrol, event);
1320 return 0;
1321}
1322
c52fd021
DP		 1323static int dac_ev(struct snd_soc_dapm_widget *w,
1324 struct snd_kcontrol *kcontrol, int event)
1325{
1326 struct snd_soc_codec *codec = w->codec;
1327 unsigned int mask = 1 << w->shift;
1328
1329 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1330 mask, mask);
1331 return 0;
1332}
1333
9e6e96a1
MB		 1334static const char *adc_mux_text[] = {
1335 "ADC",
1336 "DMIC",
1337};
1338
1339static const struct soc_enum adc_enum =
1340 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1341
1342static const struct snd_kcontrol_new adcl_mux =
1343 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1344
1345static const struct snd_kcontrol_new adcr_mux =
1346 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1347
1348static const struct snd_kcontrol_new left_speaker_mixer[] = {
1349SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1350SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1351SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1352SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1353SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1354};
1355
1356static const struct snd_kcontrol_new right_speaker_mixer[] = {
1357SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1358SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1359SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1360SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1361SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1362};
1363
1364/* Debugging; dump chip status after DAPM transitions */
1365static int post_ev(struct snd_soc_dapm_widget *w,
1366 struct snd_kcontrol *kcontrol, int event)
1367{
1368 struct snd_soc_codec *codec = w->codec;
1369 dev_dbg(codec->dev, "SRC status: %x\n",
1370 snd_soc_read(codec,
1371 WM8994_RATE_STATUS));
1372 return 0;
1373}
1374
1375static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1376SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1377 1, 1, 0),
1378SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1379 0, 1, 0),
1380};
1381
1382static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1383SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1384 1, 1, 0),
1385SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1386 0, 1, 0),
1387};
1388
a3257ba8
MB		 1389static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1390SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1391 1, 1, 0),
1392SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1393 0, 1, 0),
1394};
1395
1396static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1397SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1398 1, 1, 0),
1399SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1400 0, 1, 0),
1401};
1402
9e6e96a1
MB		 1403static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1404SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1405 5, 1, 0),
1406SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1407 4, 1, 0),
1408SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1409 2, 1, 0),
1410SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1411 1, 1, 0),
1412SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 0, 1, 0),
1414};
1415
1416static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1417SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1418 5, 1, 0),
1419SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1420 4, 1, 0),
1421SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1422 2, 1, 0),
1423SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1424 1, 1, 0),
1425SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 0, 1, 0),
1427};
1428
1429#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1430{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1431 .info = snd_soc_info_volsw, \
1432 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1433 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1434
1435static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1436 struct snd_ctl_elem_value *ucontrol)
1437{
9d03545d
JN		 1438 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1439 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1440 struct snd_soc_codec *codec = w->codec;
1441 int ret;
1442
1443 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1444
c340304d 1445 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1446
1447 return ret;
1448}
1449
1450static const struct snd_kcontrol_new dac1l_mix[] = {
1451WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1452 5, 1, 0),
1453WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1454 4, 1, 0),
1455WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 2, 1, 0),
1457WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 1, 1, 0),
1459WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 0, 1, 0),
1461};
1462
1463static const struct snd_kcontrol_new dac1r_mix[] = {
1464WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1465 5, 1, 0),
1466WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1467 4, 1, 0),
1468WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 2, 1, 0),
1470WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 1, 1, 0),
1472WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 0, 1, 0),
1474};
1475
1476static const char *sidetone_text[] = {
1477 "ADC/DMIC1", "DMIC2",
1478};
1479
1480static const struct soc_enum sidetone1_enum =
1481 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1482
1483static const struct snd_kcontrol_new sidetone1_mux =
1484 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1485
1486static const struct soc_enum sidetone2_enum =
1487 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1488
1489static const struct snd_kcontrol_new sidetone2_mux =
1490 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1491
1492static const char *aif1dac_text[] = {
1493 "AIF1DACDAT", "AIF3DACDAT",
1494};
1495
1496static const struct soc_enum aif1dac_enum =
1497 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1498
1499static const struct snd_kcontrol_new aif1dac_mux =
1500 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1501
1502static const char *aif2dac_text[] = {
1503 "AIF2DACDAT", "AIF3DACDAT",
1504};
1505
1506static const struct soc_enum aif2dac_enum =
1507 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1508
1509static const struct snd_kcontrol_new aif2dac_mux =
1510 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1511
1512static const char *aif2adc_text[] = {
1513 "AIF2ADCDAT", "AIF3DACDAT",
1514};
1515
1516static const struct soc_enum aif2adc_enum =
1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1518
1519static const struct snd_kcontrol_new aif2adc_mux =
1520 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1521
1522static const char *aif3adc_text[] = {
c4431df0 1523 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1524};
1525
c4431df0 1526static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1528
c4431df0
MB		 1529static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1530 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1531
1532static const struct soc_enum wm8958_aif3adc_enum =
1533 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1534
1535static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1536 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1537
1538static const char *mono_pcm_out_text[] = {
c1a4ecd9 1539 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1540};
1541
1542static const struct soc_enum mono_pcm_out_enum =
1543 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1544
1545static const struct snd_kcontrol_new mono_pcm_out_mux =
1546 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1547
1548static const char *aif2dac_src_text[] = {
1549 "AIF2", "AIF3",
1550};
1551
1552/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1553static const struct soc_enum aif2dacl_src_enum =
1554 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1555
1556static const struct snd_kcontrol_new aif2dacl_src_mux =
1557 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1558
1559static const struct soc_enum aif2dacr_src_enum =
1560 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1561
1562static const struct snd_kcontrol_new aif2dacr_src_mux =
1563 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1564
173efa09 1565static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1566SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1567 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1568SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1569 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1570
1571SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1572 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1573SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1574 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1575SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1576 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1577SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1578 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1579SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1580 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1581
1582SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1583 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1584 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1585SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1586 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1587 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1588SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1589 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1590SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1591 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1592
1593SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1594};
1595
1596static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1597SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1598 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1599 SND_SOC_DAPM_PRE_PMD),
1a38336b 1600SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1602 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1603SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1604SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1605 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1606SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1607 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1608SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1609SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1610};
1611
c52fd021
DP		 1612static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1613SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1614 dac_ev, SND_SOC_DAPM_PRE_PMU),
1615SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1616 dac_ev, SND_SOC_DAPM_PRE_PMU),
1617SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1618 dac_ev, SND_SOC_DAPM_PRE_PMU),
1619SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1620 dac_ev, SND_SOC_DAPM_PRE_PMU),
1621};
1622
1623static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1624SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1625SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1626SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1627SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1628};
1629
04d28681 1630static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1631SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1632 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1633SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1634 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1635};
1636
1637static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1638SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1639SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1640};
1641
9e6e96a1
MB		 1642static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1643SND_SOC_DAPM_INPUT("DMIC1DAT"),
1644SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1645SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1646
b462c6e6
DP		 1647SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1648 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1649SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1650 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1651
9e6e96a1 1652SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1653 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1654 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1655
1a38336b
MB		 1656SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1657SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1658SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1659
7f94de48 1660SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1661 0, SND_SOC_NOPM, 9, 0),
7f94de48 1662SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1663 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1664SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1665 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1666 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1667SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1668 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1669 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1670
7f94de48 1671SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1672 0, SND_SOC_NOPM, 11, 0),
7f94de48 1673SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1674 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1675SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1676 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1677 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1678SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1679 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1680 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1681
1682SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1683 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1684SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1685 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1686
a3257ba8
MB		 1687SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1688 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1689SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1690 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1691
9e6e96a1
MB		 1692SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1693 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1694SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1695 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1696
1697SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1698SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1699
1700SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1701 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1702SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1703 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1704
1705SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1706 SND_SOC_NOPM, 13, 0),
9e6e96a1 1707SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1708 SND_SOC_NOPM, 12, 0),
d6addcc9 1709SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1710 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1711 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1712SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1713 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1714 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1715
5567d8c6
MB		 1716SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1717SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1718SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1719SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1720
1721SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1722SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1723SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1724
5567d8c6
MB		 1725SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1726SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1727
1728SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1729
1730SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1731SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1732SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1733SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1734
1735/* Power is done with the muxes since the ADC power also controls the
1736 * downsampling chain, the chip will automatically manage the analogue
1737 * specific portions.
1738 */
1739SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1740SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1741
9e6e96a1
MB		 1742SND_SOC_DAPM_POST("Debug log", post_ev),
1743};
1744
c4431df0
MB		 1745static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1746SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1747};
9e6e96a1 1748
c4431df0 1749static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1750SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1751SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1752SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1753SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1754SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1755};
1756
1757static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1758 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1759 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1760
1761 { "DSP1CLK", NULL, "CLK_SYS" },
1762 { "DSP2CLK", NULL, "CLK_SYS" },
1763 { "DSPINTCLK", NULL, "CLK_SYS" },
1764
1765 { "AIF1ADC1L", NULL, "AIF1CLK" },
1766 { "AIF1ADC1L", NULL, "DSP1CLK" },
1767 { "AIF1ADC1R", NULL, "AIF1CLK" },
1768 { "AIF1ADC1R", NULL, "DSP1CLK" },
1769 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1770
1771 { "AIF1DAC1L", NULL, "AIF1CLK" },
1772 { "AIF1DAC1L", NULL, "DSP1CLK" },
1773 { "AIF1DAC1R", NULL, "AIF1CLK" },
1774 { "AIF1DAC1R", NULL, "DSP1CLK" },
1775 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1776
1777 { "AIF1ADC2L", NULL, "AIF1CLK" },
1778 { "AIF1ADC2L", NULL, "DSP1CLK" },
1779 { "AIF1ADC2R", NULL, "AIF1CLK" },
1780 { "AIF1ADC2R", NULL, "DSP1CLK" },
1781 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1782
1783 { "AIF1DAC2L", NULL, "AIF1CLK" },
1784 { "AIF1DAC2L", NULL, "DSP1CLK" },
1785 { "AIF1DAC2R", NULL, "AIF1CLK" },
1786 { "AIF1DAC2R", NULL, "DSP1CLK" },
1787 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1788
1789 { "AIF2ADCL", NULL, "AIF2CLK" },
1790 { "AIF2ADCL", NULL, "DSP2CLK" },
1791 { "AIF2ADCR", NULL, "AIF2CLK" },
1792 { "AIF2ADCR", NULL, "DSP2CLK" },
1793 { "AIF2ADCR", NULL, "DSPINTCLK" },
1794
1795 { "AIF2DACL", NULL, "AIF2CLK" },
1796 { "AIF2DACL", NULL, "DSP2CLK" },
1797 { "AIF2DACR", NULL, "AIF2CLK" },
1798 { "AIF2DACR", NULL, "DSP2CLK" },
1799 { "AIF2DACR", NULL, "DSPINTCLK" },
1800
1801 { "DMIC1L", NULL, "DMIC1DAT" },
1802 { "DMIC1L", NULL, "CLK_SYS" },
1803 { "DMIC1R", NULL, "DMIC1DAT" },
1804 { "DMIC1R", NULL, "CLK_SYS" },
1805 { "DMIC2L", NULL, "DMIC2DAT" },
1806 { "DMIC2L", NULL, "CLK_SYS" },
1807 { "DMIC2R", NULL, "DMIC2DAT" },
1808 { "DMIC2R", NULL, "CLK_SYS" },
1809
1810 { "ADCL", NULL, "AIF1CLK" },
1811 { "ADCL", NULL, "DSP1CLK" },
1812 { "ADCL", NULL, "DSPINTCLK" },
1813
1814 { "ADCR", NULL, "AIF1CLK" },
1815 { "ADCR", NULL, "DSP1CLK" },
1816 { "ADCR", NULL, "DSPINTCLK" },
1817
1818 { "ADCL Mux", "ADC", "ADCL" },
1819 { "ADCL Mux", "DMIC", "DMIC1L" },
1820 { "ADCR Mux", "ADC", "ADCR" },
1821 { "ADCR Mux", "DMIC", "DMIC1R" },
1822
1823 { "DAC1L", NULL, "AIF1CLK" },
1824 { "DAC1L", NULL, "DSP1CLK" },
1825 { "DAC1L", NULL, "DSPINTCLK" },
1826
1827 { "DAC1R", NULL, "AIF1CLK" },
1828 { "DAC1R", NULL, "DSP1CLK" },
1829 { "DAC1R", NULL, "DSPINTCLK" },
1830
1831 { "DAC2L", NULL, "AIF2CLK" },
1832 { "DAC2L", NULL, "DSP2CLK" },
1833 { "DAC2L", NULL, "DSPINTCLK" },
1834
1835 { "DAC2R", NULL, "AIF2DACR" },
1836 { "DAC2R", NULL, "AIF2CLK" },
1837 { "DAC2R", NULL, "DSP2CLK" },
1838 { "DAC2R", NULL, "DSPINTCLK" },
1839
1840 { "TOCLK", NULL, "CLK_SYS" },
1841
5567d8c6
MB		 1842 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1843 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1844 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1845
1846 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1847 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1848 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1849
9e6e96a1
MB		 1850 /* AIF1 outputs */
1851 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1852 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1853 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1854
1855 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1856 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1857 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1858
a3257ba8
MB		 1859 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1860 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1861 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1862
1863 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1864 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1865 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1866
9e6e96a1
MB		 1867 /* Pin level routing for AIF3 */
1868 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1869 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1870 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1871 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1872
9e6e96a1
MB		 1873 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1874 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1875 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1876 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1877 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1878 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1879 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1880
1881 /* DAC1 inputs */
9e6e96a1
MB		 1882 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1883 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1884 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1885 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1886 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1887
9e6e96a1
MB		 1888 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1889 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1890 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1891 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1892 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1893
1894 /* DAC2/AIF2 outputs */
1895 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1896 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1897 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1898 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1899 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1900 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1901
1902 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1903 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1904 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1905 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1906 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1907 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1908
7f94de48
MB		 1909 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1910 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1911 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1912 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1913
9e6e96a1
MB		 1914 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1915
1916 /* AIF3 output */
1917 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1918 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1919 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1920 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1921 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1922 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1923 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1924 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1925
1926 /* Sidetone */
1927 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1928 { "Left Sidetone", "DMIC2", "DMIC2L" },
1929 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1930 { "Right Sidetone", "DMIC2", "DMIC2R" },
1931
1932 /* Output stages */
1933 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1934 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1935
1936 { "SPKL", "DAC1 Switch", "DAC1L" },
1937 { "SPKL", "DAC2 Switch", "DAC2L" },
1938
1939 { "SPKR", "DAC1 Switch", "DAC1R" },
1940 { "SPKR", "DAC2 Switch", "DAC2R" },
1941
1942 { "Left Headphone Mux", "DAC", "DAC1L" },
1943 { "Right Headphone Mux", "DAC", "DAC1R" },
1944};
1945
173efa09
DP		 1946static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1947 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1948 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1949 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1950 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1951 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1952 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1953 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1954 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1955};
1956
1957static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1958 { "DAC1L", NULL, "DAC1L Mixer" },
1959 { "DAC1R", NULL, "DAC1R Mixer" },
1960 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1961 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1962};
1963
6ed8f148
MB		 1964static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1965 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1966 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1967 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1968 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1969 { "MICBIAS1", NULL, "CLK_SYS" },
1970 { "MICBIAS1", NULL, "MICBIAS Supply" },
1971 { "MICBIAS2", NULL, "CLK_SYS" },
1972 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1973};
1974
c4431df0
MB		 1975static const struct snd_soc_dapm_route wm8994_intercon[] = {
1976 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1977 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1978 { "MICBIAS1", NULL, "VMID" },
1979 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1980};
1981
1982static const struct snd_soc_dapm_route wm8958_intercon[] = {
1983 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1984 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1985
1986 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1987 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1988 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1989 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1990
8c5b842b
MB		 1991 { "AIF3DACDAT", NULL, "AIF3" },
1992 { "AIF3ADCDAT", NULL, "AIF3" },
1993
c4431df0
MB		 1994 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1995 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1996
1997 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1998};
1999
9e6e96a1
MB		 2000/* The size in bits of the FLL divide multiplied by 10
2001 * to allow rounding later */
2002#define FIXED_FLL_SIZE ((1 << 16) * 10)
2003
2004struct fll_div {
2005 u16 outdiv;
2006 u16 n;
2007 u16 k;
2008 u16 clk_ref_div;
2009 u16 fll_fratio;
2010};
2011
2012static int wm8994_get_fll_config(struct fll_div *fll,
2013 int freq_in, int freq_out)
2014{
2015 u64 Kpart;
2016 unsigned int K, Ndiv, Nmod;
2017
2018 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2019
2020 /* Scale the input frequency down to <= 13.5MHz */
2021 fll->clk_ref_div = 0;
2022 while (freq_in > 13500000) {
2023 fll->clk_ref_div++;
2024 freq_in /= 2;
2025
2026 if (fll->clk_ref_div > 3)
2027 return -EINVAL;
2028 }
2029 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2030
2031 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2032 fll->outdiv = 3;
2033 while (freq_out * (fll->outdiv + 1) < 90000000) {
2034 fll->outdiv++;
2035 if (fll->outdiv > 63)
2036 return -EINVAL;
2037 }
2038 freq_out *= fll->outdiv + 1;
2039 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2040
2041 if (freq_in > 1000000) {
2042 fll->fll_fratio = 0;
7d48a6ac
MB		 2043 } else if (freq_in > 256000) {
2044 fll->fll_fratio = 1;
2045 freq_in *= 2;
2046 } else if (freq_in > 128000) {
2047 fll->fll_fratio = 2;
2048 freq_in *= 4;
2049 } else if (freq_in > 64000) {
9e6e96a1
MB		 2050 fll->fll_fratio = 3;
2051 freq_in *= 8;
7d48a6ac
MB		 2052 } else {
2053 fll->fll_fratio = 4;
2054 freq_in *= 16;
9e6e96a1
MB		 2055 }
2056 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2057
2058 /* Now, calculate N.K */
2059 Ndiv = freq_out / freq_in;
2060
2061 fll->n = Ndiv;
2062 Nmod = freq_out % freq_in;
2063 pr_debug("Nmod=%d\n", Nmod);
2064
2065 /* Calculate fractional part - scale up so we can round. */
2066 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2067
2068 do_div(Kpart, freq_in);
2069
2070 K = Kpart & 0xFFFFFFFF;
2071
2072 if ((K % 10) >= 5)
2073 K += 5;
2074
2075 /* Move down to proper range now rounding is done */
2076 fll->k = K / 10;
2077
2078 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2079
2080 return 0;
2081}
2082
f0fba2ad 2083static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2084 unsigned int freq_in, unsigned int freq_out)
2085{
b2c812e2 2086 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2087 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2088 int reg_offset, ret;
2089 struct fll_div fll;
e413ba88 2090 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2091 unsigned long timeout;
4b7ed83a 2092 bool was_enabled;
9e6e96a1 2093
9e6e96a1
MB		 2094 switch (id) {
2095 case WM8994_FLL1:
2096 reg_offset = 0;
2097 id = 0;
e413ba88 2098 aif_src = 0x10;
9e6e96a1
MB		 2099 break;
2100 case WM8994_FLL2:
2101 reg_offset = 0x20;
2102 id = 1;
e413ba88 2103 aif_src = 0x18;
9e6e96a1
MB		 2104 break;
2105 default:
2106 return -EINVAL;
2107 }
2108
4b7ed83a
MB		 2109 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2110 was_enabled = reg & WM8994_FLL1_ENA;
2111
136ff2a2 2112 switch (src) {
7add84aa
MB		 2113 case 0:
2114 /* Allow no source specification when stopping */
2115 if (freq_out)
2116 return -EINVAL;
4514e899 2117 src = wm8994->fll[id].src;
7add84aa 2118 break;
136ff2a2
MB		 2119 case WM8994_FLL_SRC_MCLK1:
2120 case WM8994_FLL_SRC_MCLK2:
2121 case WM8994_FLL_SRC_LRCLK:
2122 case WM8994_FLL_SRC_BCLK:
2123 break;
fbfe6983
MB		 2124 case WM8994_FLL_SRC_INTERNAL:
2125 freq_in = 12000000;
2126 freq_out = 12000000;
2127 break;
136ff2a2
MB		 2128 default:
2129 return -EINVAL;
2130 }
2131
9e6e96a1
MB		 2132 /* Are we changing anything? */
2133 if (wm8994->fll[id].src == src &&
2134 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2135 return 0;
2136
2137 /* If we're stopping the FLL redo the old config - no
2138 * registers will actually be written but we avoid GCC flow
2139 * analysis bugs spewing warnings.
2140 */
2141 if (freq_out)
2142 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2143 else
2144 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2145 wm8994->fll[id].out);
2146 if (ret < 0)
2147 return ret;
2148
e413ba88
MB		 2149 /* Make sure that we're not providing SYSCLK right now */
2150 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2151 if (clk1 & WM8994_SYSCLK_SRC)
2152 aif_reg = WM8994_AIF2_CLOCKING_1;
2153 else
2154 aif_reg = WM8994_AIF1_CLOCKING_1;
2155 reg = snd_soc_read(codec, aif_reg);
2156
2157 if ((reg & WM8994_AIF1CLK_ENA) &&
2158 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2159 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2160 id + 1);
2161 return -EBUSY;
2162 }
9e6e96a1
MB		 2163
2164 /* We always need to disable the FLL while reconfiguring */
2165 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2166 WM8994_FLL1_ENA, 0);
2167
20dc24a9 2168 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2169 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2170 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2171 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2172 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2173 goto out;
2174 }
2175
9e6e96a1
MB		 2176 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2177 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2178 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2179 WM8994_FLL1_OUTDIV_MASK |
2180 WM8994_FLL1_FRATIO_MASK, reg);
2181
b16db745
MB		 2182 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2183 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2184
2185 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2186 WM8994_FLL1_N_MASK,
7435d4ee 2187 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1
MB		 2188
2189 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2190 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2191 WM8994_FLL1_REFCLK_DIV_MASK |
2192 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2193 ((src == WM8994_FLL_SRC_INTERNAL)
2194 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2195 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2196 (src - 1));
9e6e96a1 2197
f0f5039c
MB		 2198 /* Clear any pending completion from a previous failure */
2199 try_wait_for_completion(&wm8994->fll_locked[id]);
2200
9e6e96a1
MB		 2201 /* Enable (with fractional mode if required) */
2202 if (freq_out) {
4b7ed83a
MB		 2203 /* Enable VMID if we need it */
2204 if (!was_enabled) {
af6b6fe4
MB		 2205 active_reference(codec);
2206
4b7ed83a
MB		 2207 switch (control->type) {
2208 case WM8994:
2209 vmid_reference(codec);
2210 break;
2211 case WM8958:
2212 if (wm8994->revision < 1)
2213 vmid_reference(codec);
2214 break;
2215 default:
2216 break;
2217 }
2218 }
2219
fbfe6983
MB		 2220 reg = WM8994_FLL1_ENA;
2221
9e6e96a1 2222 if (fll.k)
fbfe6983
MB		 2223 reg |= WM8994_FLL1_FRAC;
2224 if (src == WM8994_FLL_SRC_INTERNAL)
2225 reg |= WM8994_FLL1_OSC_ENA;
2226
9e6e96a1 2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2228 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2229 WM8994_FLL1_FRAC, reg);
8e9ddf81 2230
c7ebf932
MB		 2231 if (wm8994->fll_locked_irq) {
2232 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2233 msecs_to_jiffies(10));
2234 if (timeout == 0)
2235 dev_warn(codec->dev,
2236 "Timed out waiting for FLL lock\n");
2237 } else {
2238 msleep(5);
2239 }
4b7ed83a
MB		 2240 } else {
2241 if (was_enabled) {
2242 switch (control->type) {
2243 case WM8994:
2244 vmid_dereference(codec);
2245 break;
2246 case WM8958:
2247 if (wm8994->revision < 1)
2248 vmid_dereference(codec);
2249 break;
2250 default:
2251 break;
2252 }
af6b6fe4
MB		 2253
2254 active_dereference(codec);
4b7ed83a 2255 }
9e6e96a1
MB		 2256 }
2257
20dc24a9 2258out:
9e6e96a1
MB		 2259 wm8994->fll[id].in = freq_in;
2260 wm8994->fll[id].out = freq_out;
136ff2a2 2261 wm8994->fll[id].src = src;
9e6e96a1 2262
9e6e96a1
MB		 2263 configure_clock(codec);
2264
cd22000a
MB		 2265 /*
2266 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2267 * for detection.
2268 */
2269 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2270 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2271 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2272 WM8994_AIF1CLK_RATE_MASK, 0x1);
2273 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2274 WM8994_AIF2CLK_RATE_MASK, 0x1);
2275 }
2276
9e6e96a1
MB		 2277 return 0;
2278}
2279
c7ebf932
MB		 2280static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2281{
2282 struct completion *completion = data;
2283
2284 complete(completion);
2285
2286 return IRQ_HANDLED;
2287}
f0fba2ad 2288
66b47fdb
MB		 2289static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2290
f0fba2ad
LG		 2291static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2292 unsigned int freq_in, unsigned int freq_out)
2293{
2294 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2295}
2296
9e6e96a1
MB		 2297static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2298 int clk_id, unsigned int freq, int dir)
2299{
2300 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2301 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2302 int i;
9e6e96a1
MB		 2303
2304 switch (dai->id) {
2305 case 1:
2306 case 2:
2307 break;
2308
2309 default:
2310 /* AIF3 shares clocking with AIF1/2 */
2311 return -EINVAL;
2312 }
2313
2314 switch (clk_id) {
2315 case WM8994_SYSCLK_MCLK1:
2316 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2317 wm8994->mclk[0] = freq;
2318 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2319 dai->id, freq);
2320 break;
2321
2322 case WM8994_SYSCLK_MCLK2:
2323 /* TODO: Set GPIO AF */
2324 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2325 wm8994->mclk[1] = freq;
2326 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2327 dai->id, freq);
2328 break;
2329
2330 case WM8994_SYSCLK_FLL1:
2331 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2332 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2333 break;
2334
2335 case WM8994_SYSCLK_FLL2:
2336 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2337 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2338 break;
2339
66b47fdb
MB		 2340 case WM8994_SYSCLK_OPCLK:
2341 /* Special case - a division (times 10) is given and
c1a4ecd9 2342 * no effect on main clocking.
66b47fdb
MB		 2343 */
2344 if (freq) {
2345 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2346 if (opclk_divs[i] == freq)
2347 break;
2348 if (i == ARRAY_SIZE(opclk_divs))
2349 return -EINVAL;
2350 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2351 WM8994_OPCLK_DIV_MASK, i);
2352 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2353 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2354 } else {
2355 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2356 WM8994_OPCLK_ENA, 0);
2357 }
2358
9e6e96a1
MB		 2359 default:
2360 return -EINVAL;
2361 }
2362
2363 configure_clock(codec);
2364
6730049a
MB		 2365 /*
2366 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2367 * for detection.
2368 */
2369 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2370 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2371 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2372 WM8994_AIF1CLK_RATE_MASK, 0x1);
2373 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2374 WM8994_AIF2CLK_RATE_MASK, 0x1);
2375 }
2376
9e6e96a1
MB		 2377 return 0;
2378}
2379
2380static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2381 enum snd_soc_bias_level level)
2382{
b6b05691 2383 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2384 struct wm8994 *control = wm8994->wm8994;
b6b05691 2385
5f2f3890
MB		 2386 wm_hubs_set_bias_level(codec, level);
2387
9e6e96a1
MB		 2388 switch (level) {
2389 case SND_SOC_BIAS_ON:
2390 break;
2391
2392 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2393 /* MICBIAS into regulating mode */
2394 switch (control->type) {
2395 case WM8958:
2396 case WM1811:
2397 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2398 WM8958_MICB1_MODE, 0);
2399 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2400 WM8958_MICB2_MODE, 0);
2401 break;
2402 default:
2403 break;
2404 }
af6b6fe4
MB		 2405
2406 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2407 active_reference(codec);
9e6e96a1
MB		 2408 break;
2409
2410 case SND_SOC_BIAS_STANDBY:
ce6120cc 2411 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2412 switch (control->type) {
8bc3c2c2
MB		 2413 case WM8958:
2414 if (wm8994->revision == 0) {
2415 /* Optimise performance for rev A */
8bc3c2c2
MB		 2416 snd_soc_update_bits(codec,
2417 WM8958_CHARGE_PUMP_2,
2418 WM8958_CP_DISCH,
2419 WM8958_CP_DISCH);
2420 }
2421 break;
81204c84 2422
462835e4 2423 default:
81204c84 2424 break;
b6b05691 2425 }
9e6e96a1
MB		 2426
2427 /* Discharge LINEOUT1 & 2 */
2428 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2429 WM8994_LINEOUT1_DISCH |
2430 WM8994_LINEOUT2_DISCH,
2431 WM8994_LINEOUT1_DISCH |
2432 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2433 }
2434
af6b6fe4
MB		 2435 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2436 active_dereference(codec);
2437
500fa30e
MB		 2438 /* MICBIAS into bypass mode on newer devices */
2439 switch (control->type) {
2440 case WM8958:
2441 case WM1811:
2442 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2443 WM8958_MICB1_MODE,
2444 WM8958_MICB1_MODE);
2445 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2446 WM8958_MICB2_MODE,
2447 WM8958_MICB2_MODE);
2448 break;
2449 default:
2450 break;
2451 }
9e6e96a1
MB		 2452 break;
2453
2454 case SND_SOC_BIAS_OFF:
4105ab84 2455 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2456 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2457 break;
2458 }
5f2f3890 2459
ce6120cc 2460 codec->dapm.bias_level = level;
af6b6fe4 2461
22f8d055
MB		 2462 return 0;
2463}
2464
2465int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2466{
2467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2468
2469 switch (mode) {
2470 case WM8994_VMID_NORMAL:
2471 if (wm8994->hubs.lineout1_se) {
2472 snd_soc_dapm_disable_pin(&codec->dapm,
2473 "LINEOUT1N Driver");
2474 snd_soc_dapm_disable_pin(&codec->dapm,
2475 "LINEOUT1P Driver");
2476 }
2477 if (wm8994->hubs.lineout2_se) {
2478 snd_soc_dapm_disable_pin(&codec->dapm,
2479 "LINEOUT2N Driver");
2480 snd_soc_dapm_disable_pin(&codec->dapm,
2481 "LINEOUT2P Driver");
2482 }
2483
2484 /* Do the sync with the old mode to allow it to clean up */
2485 snd_soc_dapm_sync(&codec->dapm);
2486 wm8994->vmid_mode = mode;
2487 break;
2488
2489 case WM8994_VMID_FORCE:
2490 if (wm8994->hubs.lineout1_se) {
2491 snd_soc_dapm_force_enable_pin(&codec->dapm,
2492 "LINEOUT1N Driver");
2493 snd_soc_dapm_force_enable_pin(&codec->dapm,
2494 "LINEOUT1P Driver");
2495 }
2496 if (wm8994->hubs.lineout2_se) {
2497 snd_soc_dapm_force_enable_pin(&codec->dapm,
2498 "LINEOUT2N Driver");
2499 snd_soc_dapm_force_enable_pin(&codec->dapm,
2500 "LINEOUT2P Driver");
2501 }
2502
2503 wm8994->vmid_mode = mode;
2504 snd_soc_dapm_sync(&codec->dapm);
2505 break;
2506
2507 default:
2508 return -EINVAL;
2509 }
2510
9e6e96a1
MB		 2511 return 0;
2512}
2513
2514static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2515{
2516 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2517 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2518 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2519 int ms_reg;
2520 int aif1_reg;
2521 int ms = 0;
2522 int aif1 = 0;
2523
2524 switch (dai->id) {
2525 case 1:
2526 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2527 aif1_reg = WM8994_AIF1_CONTROL_1;
2528 break;
2529 case 2:
2530 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2531 aif1_reg = WM8994_AIF2_CONTROL_1;
2532 break;
2533 default:
2534 return -EINVAL;
2535 }
2536
2537 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2538 case SND_SOC_DAIFMT_CBS_CFS:
2539 break;
2540 case SND_SOC_DAIFMT_CBM_CFM:
2541 ms = WM8994_AIF1_MSTR;
2542 break;
2543 default:
2544 return -EINVAL;
2545 }
2546
2547 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2548 case SND_SOC_DAIFMT_DSP_B:
2549 aif1 |= WM8994_AIF1_LRCLK_INV;
2550 case SND_SOC_DAIFMT_DSP_A:
2551 aif1 |= 0x18;
2552 break;
2553 case SND_SOC_DAIFMT_I2S:
2554 aif1 |= 0x10;
2555 break;
2556 case SND_SOC_DAIFMT_RIGHT_J:
2557 break;
2558 case SND_SOC_DAIFMT_LEFT_J:
2559 aif1 |= 0x8;
2560 break;
2561 default:
2562 return -EINVAL;
2563 }
2564
2565 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2566 case SND_SOC_DAIFMT_DSP_A:
2567 case SND_SOC_DAIFMT_DSP_B:
2568 /* frame inversion not valid for DSP modes */
2569 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2570 case SND_SOC_DAIFMT_NB_NF:
2571 break;
2572 case SND_SOC_DAIFMT_IB_NF:
2573 aif1 |= WM8994_AIF1_BCLK_INV;
2574 break;
2575 default:
2576 return -EINVAL;
2577 }
2578 break;
2579
2580 case SND_SOC_DAIFMT_I2S:
2581 case SND_SOC_DAIFMT_RIGHT_J:
2582 case SND_SOC_DAIFMT_LEFT_J:
2583 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2584 case SND_SOC_DAIFMT_NB_NF:
2585 break;
2586 case SND_SOC_DAIFMT_IB_IF:
2587 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2588 break;
2589 case SND_SOC_DAIFMT_IB_NF:
2590 aif1 |= WM8994_AIF1_BCLK_INV;
2591 break;
2592 case SND_SOC_DAIFMT_NB_IF:
2593 aif1 |= WM8994_AIF1_LRCLK_INV;
2594 break;
2595 default:
2596 return -EINVAL;
2597 }
2598 break;
2599 default:
2600 return -EINVAL;
2601 }
2602
c4431df0
MB		 2603 /* The AIF2 format configuration needs to be mirrored to AIF3
2604 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2605 switch (control->type) {
2606 case WM1811:
2607 case WM8958:
2608 if (dai->id == 2)
2609 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2610 WM8994_AIF1_LRCLK_INV |
2611 WM8958_AIF3_FMT_MASK, aif1);
2612 break;
2613
2614 default:
2615 break;
2616 }
c4431df0 2617
9e6e96a1
MB		 2618 snd_soc_update_bits(codec, aif1_reg,
2619 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2620 WM8994_AIF1_FMT_MASK,
2621 aif1);
2622 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2623 ms);
2624
2625 return 0;
2626}
2627
2628static struct {
2629 int val, rate;
2630} srs[] = {
2631 { 0, 8000 },
2632 { 1, 11025 },
2633 { 2, 12000 },
2634 { 3, 16000 },
2635 { 4, 22050 },
2636 { 5, 24000 },
2637 { 6, 32000 },
2638 { 7, 44100 },
2639 { 8, 48000 },
2640 { 9, 88200 },
2641 { 10, 96000 },
2642};
2643
2644static int fs_ratios[] = {
2645 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2646};
2647
2648static int bclk_divs[] = {
2649 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2650 640, 880, 960, 1280, 1760, 1920
2651};
2652
2653static int wm8994_hw_params(struct snd_pcm_substream *substream,
2654 struct snd_pcm_hw_params *params,
2655 struct snd_soc_dai *dai)
2656{
2657 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2658 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2659 int aif1_reg;
b1e43d93 2660 int aif2_reg;
9e6e96a1
MB		 2661 int bclk_reg;
2662 int lrclk_reg;
2663 int rate_reg;
2664 int aif1 = 0;
b1e43d93 2665 int aif2 = 0;
9e6e96a1
MB		 2666 int bclk = 0;
2667 int lrclk = 0;
2668 int rate_val = 0;
2669 int id = dai->id - 1;
2670
2671 int i, cur_val, best_val, bclk_rate, best;
2672
2673 switch (dai->id) {
2674 case 1:
2675 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2676 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2677 bclk_reg = WM8994_AIF1_BCLK;
2678 rate_reg = WM8994_AIF1_RATE;
2679 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2680 wm8994->lrclk_shared[0]) {
9e6e96a1 2681 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2682 } else {
9e6e96a1 2683 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2684 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2685 }
9e6e96a1
MB		 2686 break;
2687 case 2:
2688 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2689 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2690 bclk_reg = WM8994_AIF2_BCLK;
2691 rate_reg = WM8994_AIF2_RATE;
2692 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2693 wm8994->lrclk_shared[1]) {
9e6e96a1 2694 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2695 } else {
9e6e96a1 2696 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2697 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2698 }
9e6e96a1
MB		 2699 break;
2700 default:
2701 return -EINVAL;
2702 }
2703
79748cdb 2704 bclk_rate = params_rate(params);
9e6e96a1
MB		 2705 switch (params_format(params)) {
2706 case SNDRV_PCM_FORMAT_S16_LE:
2707 bclk_rate *= 16;
2708 break;
2709 case SNDRV_PCM_FORMAT_S20_3LE:
2710 bclk_rate *= 20;
2711 aif1 |= 0x20;
2712 break;
2713 case SNDRV_PCM_FORMAT_S24_LE:
2714 bclk_rate *= 24;
2715 aif1 |= 0x40;
2716 break;
2717 case SNDRV_PCM_FORMAT_S32_LE:
2718 bclk_rate *= 32;
2719 aif1 |= 0x60;
2720 break;
2721 default:
2722 return -EINVAL;
2723 }
2724
79748cdb
MB		 2725 wm8994->channels[id] = params_channels(params);
2726 switch (params_channels(params)) {
2727 case 1:
2728 case 2:
2729 bclk_rate *= 2;
2730 break;
2731 default:
2732 bclk_rate *= 4;
2733 break;
2734 }
2735
9e6e96a1
MB		 2736 /* Try to find an appropriate sample rate; look for an exact match. */
2737 for (i = 0; i < ARRAY_SIZE(srs); i++)
2738 if (srs[i].rate == params_rate(params))
2739 break;
2740 if (i == ARRAY_SIZE(srs))
2741 return -EINVAL;
2742 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2743
2744 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2745 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2746 dai->id, wm8994->aifclk[id], bclk_rate);
2747
b1e43d93
MB		 2748 if (params_channels(params) == 1 &&
2749 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2750 aif2 |= WM8994_AIF1_MONO;
2751
9e6e96a1
MB		 2752 if (wm8994->aifclk[id] == 0) {
2753 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2754 return -EINVAL;
2755 }
2756
2757 /* AIFCLK/fs ratio; look for a close match in either direction */
2758 best = 0;
2759 best_val = abs((fs_ratios[0] * params_rate(params))
2760 - wm8994->aifclk[id]);
2761 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2762 cur_val = abs((fs_ratios[i] * params_rate(params))
2763 - wm8994->aifclk[id]);
2764 if (cur_val >= best_val)
2765 continue;
2766 best = i;
2767 best_val = cur_val;
2768 }
2769 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2770 dai->id, fs_ratios[best]);
2771 rate_val |= best;
2772
2773 /* We may not get quite the right frequency if using
2774 * approximate clocks so look for the closest match that is
2775 * higher than the target (we need to ensure that there enough
2776 * BCLKs to clock out the samples).
2777 */
2778 best = 0;
2779 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2780 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2781 if (cur_val < 0) /* BCLK table is sorted */
2782 break;
2783 best = i;
2784 }
07cd8ada 2785 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2786 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2787 bclk_divs[best], bclk_rate);
2788 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2789
2790 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2791 if (!lrclk) {
2792 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2793 bclk_rate);
2794 return -EINVAL;
2795 }
9e6e96a1
MB		 2796 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2797 lrclk, bclk_rate / lrclk);
2798
2799 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2800 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2801 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2802 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2803 lrclk);
2804 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2805 WM8994_AIF1CLK_RATE_MASK, rate_val);
2806
2807 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2808 switch (dai->id) {
2809 case 1:
2810 wm8994->dac_rates[0] = params_rate(params);
2811 wm8994_set_retune_mobile(codec, 0);
2812 wm8994_set_retune_mobile(codec, 1);
2813 break;
2814 case 2:
2815 wm8994->dac_rates[1] = params_rate(params);
2816 wm8994_set_retune_mobile(codec, 2);
2817 break;
2818 }
2819 }
2820
2821 return 0;
2822}
2823
c4431df0
MB		 2824static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2825 struct snd_pcm_hw_params *params,
2826 struct snd_soc_dai *dai)
2827{
2828 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2829 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2830 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2831 int aif1_reg;
2832 int aif1 = 0;
2833
2834 switch (dai->id) {
2835 case 3:
2836 switch (control->type) {
81204c84 2837 case WM1811:
c4431df0
MB		 2838 case WM8958:
2839 aif1_reg = WM8958_AIF3_CONTROL_1;
2840 break;
2841 default:
2842 return 0;
2843 }
2844 default:
2845 return 0;
2846 }
2847
2848 switch (params_format(params)) {
2849 case SNDRV_PCM_FORMAT_S16_LE:
2850 break;
2851 case SNDRV_PCM_FORMAT_S20_3LE:
2852 aif1 |= 0x20;
2853 break;
2854 case SNDRV_PCM_FORMAT_S24_LE:
2855 aif1 |= 0x40;
2856 break;
2857 case SNDRV_PCM_FORMAT_S32_LE:
2858 aif1 |= 0x60;
2859 break;
2860 default:
2861 return -EINVAL;
2862 }
2863
2864 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2865}
2866
9e6e96a1
MB		 2867static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2868{
2869 struct snd_soc_codec *codec = codec_dai->codec;
2870 int mute_reg;
2871 int reg;
2872
2873 switch (codec_dai->id) {
2874 case 1:
2875 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2876 break;
2877 case 2:
2878 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2879 break;
2880 default:
2881 return -EINVAL;
2882 }
2883
2884 if (mute)
2885 reg = WM8994_AIF1DAC1_MUTE;
2886 else
2887 reg = 0;
2888
2889 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2890
2891 return 0;
2892}
2893
778a76e2
MB		 2894static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2895{
2896 struct snd_soc_codec *codec = codec_dai->codec;
2897 int reg, val, mask;
2898
2899 switch (codec_dai->id) {
2900 case 1:
2901 reg = WM8994_AIF1_MASTER_SLAVE;
2902 mask = WM8994_AIF1_TRI;
2903 break;
2904 case 2:
2905 reg = WM8994_AIF2_MASTER_SLAVE;
2906 mask = WM8994_AIF2_TRI;
2907 break;
778a76e2
MB		 2908 default:
2909 return -EINVAL;
2910 }
2911
2912 if (tristate)
2913 val = mask;
2914 else
2915 val = 0;
2916
78b3fb46 2917 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2918}
2919
d09f3ecf
MB		 2920static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2921{
2922 struct snd_soc_codec *codec = dai->codec;
2923
2924 /* Disable the pulls on the AIF if we're using it to save power. */
2925 snd_soc_update_bits(codec, WM8994_GPIO_3,
2926 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2927 snd_soc_update_bits(codec, WM8994_GPIO_4,
2928 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2929 snd_soc_update_bits(codec, WM8994_GPIO_5,
2930 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2931
2932 return 0;
2933}
2934
9e6e96a1
MB		 2935#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2936
2937#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2938 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2939
85e7652d 2940static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2941 .set_sysclk = wm8994_set_dai_sysclk,
2942 .set_fmt = wm8994_set_dai_fmt,
2943 .hw_params = wm8994_hw_params,
2944 .digital_mute = wm8994_aif_mute,
2945 .set_pll = wm8994_set_fll,
778a76e2 2946 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2947};
2948
85e7652d 2949static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2950 .set_sysclk = wm8994_set_dai_sysclk,
2951 .set_fmt = wm8994_set_dai_fmt,
2952 .hw_params = wm8994_hw_params,
2953 .digital_mute = wm8994_aif_mute,
2954 .set_pll = wm8994_set_fll,
778a76e2
MB		 2955 .set_tristate = wm8994_set_tristate,
2956};
2957
85e7652d 2958static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2959 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 2960};
2961
f0fba2ad 2962static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2963 {
f0fba2ad 2964 .name = "wm8994-aif1",
8c7f78b3 2965 .id = 1,
9e6e96a1
MB		 2966 .playback = {
2967 .stream_name = "AIF1 Playback",
b1e43d93 2968 .channels_min = 1,
9e6e96a1
MB		 2969 .channels_max = 2,
2970 .rates = WM8994_RATES,
2971 .formats = WM8994_FORMATS,
99b0292d 2972 .sig_bits = 24,
9e6e96a1
MB		 2973 },
2974 .capture = {
2975 .stream_name = "AIF1 Capture",
b1e43d93 2976 .channels_min = 1,
9e6e96a1
MB		 2977 .channels_max = 2,
2978 .rates = WM8994_RATES,
2979 .formats = WM8994_FORMATS,
99b0292d 2980 .sig_bits = 24,
9e6e96a1
MB		 2981 },
2982 .ops = &wm8994_aif1_dai_ops,
2983 },
2984 {
f0fba2ad 2985 .name = "wm8994-aif2",
8c7f78b3 2986 .id = 2,
9e6e96a1
MB		 2987 .playback = {
2988 .stream_name = "AIF2 Playback",
b1e43d93 2989 .channels_min = 1,
9e6e96a1
MB		 2990 .channels_max = 2,
2991 .rates = WM8994_RATES,
2992 .formats = WM8994_FORMATS,
99b0292d 2993 .sig_bits = 24,
9e6e96a1
MB		 2994 },
2995 .capture = {
2996 .stream_name = "AIF2 Capture",
b1e43d93 2997 .channels_min = 1,
9e6e96a1
MB		 2998 .channels_max = 2,
2999 .rates = WM8994_RATES,
3000 .formats = WM8994_FORMATS,
99b0292d 3001 .sig_bits = 24,
9e6e96a1 3002 },
d09f3ecf 3003 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 3004 .ops = &wm8994_aif2_dai_ops,
3005 },
3006 {
f0fba2ad 3007 .name = "wm8994-aif3",
8c7f78b3 3008 .id = 3,
9e6e96a1
MB		 3009 .playback = {
3010 .stream_name = "AIF3 Playback",
b1e43d93 3011 .channels_min = 1,
9e6e96a1
MB		 3012 .channels_max = 2,
3013 .rates = WM8994_RATES,
3014 .formats = WM8994_FORMATS,
99b0292d 3015 .sig_bits = 24,
9e6e96a1 3016 },
a8462bde 3017 .capture = {
9e6e96a1 3018 .stream_name = "AIF3 Capture",
b1e43d93 3019 .channels_min = 1,
9e6e96a1
MB		 3020 .channels_max = 2,
3021 .rates = WM8994_RATES,
3022 .formats = WM8994_FORMATS,
99b0292d
MB		 3023 .sig_bits = 24,
3024 },
778a76e2 3025 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3026 }
3027};
9e6e96a1
MB		 3028
3029#ifdef CONFIG_PM
4752a887 3030static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3031{
b2c812e2 3032 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3033 int i, ret;
3034
3035 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3036 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3037 sizeof(struct wm8994_fll_config));
f0fba2ad 3038 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3039 if (ret < 0)
3040 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3041 i + 1, ret);
3042 }
3043
3044 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3045
3046 return 0;
3047}
3048
4752a887 3049static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3050{
b2c812e2 3051 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3052 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 3053 int i, ret;
c52fd021
DP		 3054 unsigned int val, mask;
3055
3056 if (wm8994->revision < 4) {
3057 /* force a HW read */
d9a7666f
MB		 3058 ret = regmap_read(control->regmap,
3059 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 3060
3061 /* modify the cache only */
3062 codec->cache_only = 1;
3063 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3064 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3065 val &= mask;
3066 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3067 mask, val);
3068 codec->cache_only = 0;
3069 }
9e6e96a1 3070
9e6e96a1 3071 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3072 if (!wm8994->fll_suspend[i].out)
3073 continue;
3074
f0fba2ad 3075 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3076 wm8994->fll_suspend[i].src,
3077 wm8994->fll_suspend[i].in,
3078 wm8994->fll_suspend[i].out);
3079 if (ret < 0)
3080 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3081 i + 1, ret);
3082 }
3083
3084 return 0;
3085}
3086#else
4752a887
MB		 3087#define wm8994_codec_suspend NULL
3088#define wm8994_codec_resume NULL
9e6e96a1
MB		 3089#endif
3090
3091static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3092{
8cb8e83b 3093 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3094 struct wm8994 *control = wm8994->wm8994;
3095 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3096 struct snd_kcontrol_new controls[] = {
3097 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3098 wm8994->retune_mobile_enum,
3099 wm8994_get_retune_mobile_enum,
3100 wm8994_put_retune_mobile_enum),
3101 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3102 wm8994->retune_mobile_enum,
3103 wm8994_get_retune_mobile_enum,
3104 wm8994_put_retune_mobile_enum),
3105 SOC_ENUM_EXT("AIF2 EQ Mode",
3106 wm8994->retune_mobile_enum,
3107 wm8994_get_retune_mobile_enum,
3108 wm8994_put_retune_mobile_enum),
3109 };
3110 int ret, i, j;
3111 const char **t;
3112
3113 /* We need an array of texts for the enum API but the number
3114 * of texts is likely to be less than the number of
3115 * configurations due to the sample rate dependency of the
3116 * configurations. */
3117 wm8994->num_retune_mobile_texts = 0;
3118 wm8994->retune_mobile_texts = NULL;
3119 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3120 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3121 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3122 wm8994->retune_mobile_texts[j]) == 0)
3123 break;
3124 }
3125
3126 if (j != wm8994->num_retune_mobile_texts)
3127 continue;
3128
3129 /* Expand the array... */
3130 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3131 sizeof(char *) *
9e6e96a1
MB		 3132 (wm8994->num_retune_mobile_texts + 1),
3133 GFP_KERNEL);
3134 if (t == NULL)
3135 continue;
3136
3137 /* ...store the new entry... */
c1a4ecd9 3138 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3139 pdata->retune_mobile_cfgs[i].name;
3140
3141 /* ...and remember the new version. */
3142 wm8994->num_retune_mobile_texts++;
3143 wm8994->retune_mobile_texts = t;
3144 }
3145
3146 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3147 wm8994->num_retune_mobile_texts);
3148
3149 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3150 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3151
8cb8e83b 3152 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3153 ARRAY_SIZE(controls));
3154 if (ret != 0)
8cb8e83b 3155 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3156 "Failed to add ReTune Mobile controls: %d\n", ret);
3157}
3158
3159static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3160{
8cb8e83b 3161 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3162 struct wm8994 *control = wm8994->wm8994;
3163 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3164 int ret, i;
3165
3166 if (!pdata)
3167 return;
3168
3169 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3170 pdata->lineout2_diff,
3171 pdata->lineout1fb,
3172 pdata->lineout2fb,
3173 pdata->jd_scthr,
3174 pdata->jd_thr,
02e79476
MB		 3175 pdata->micb1_delay,
3176 pdata->micb2_delay,
9e6e96a1
MB		 3177 pdata->micbias1_lvl,
3178 pdata->micbias2_lvl);
3179
3180 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3181
3182 if (pdata->num_drc_cfgs) {
3183 struct snd_kcontrol_new controls[] = {
3184 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3185 wm8994_get_drc_enum, wm8994_put_drc_enum),
3186 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3187 wm8994_get_drc_enum, wm8994_put_drc_enum),
3188 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3189 wm8994_get_drc_enum, wm8994_put_drc_enum),
3190 };
3191
3192 /* We need an array of texts for the enum API */
8cb8e83b 3193 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3194 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3195 if (!wm8994->drc_texts) {
8cb8e83b 3196 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3197 "Failed to allocate %d DRC config texts\n",
3198 pdata->num_drc_cfgs);
3199 return;
3200 }
3201
3202 for (i = 0; i < pdata->num_drc_cfgs; i++)
3203 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3204
3205 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3206 wm8994->drc_enum.texts = wm8994->drc_texts;
3207
8cb8e83b 3208 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3209 ARRAY_SIZE(controls));
9e6e96a1
MB		 3210 for (i = 0; i < WM8994_NUM_DRC; i++)
3211 wm8994_set_drc(codec, i);
45a690f6
MB		 3212 } else {
3213 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3214 wm8994_drc_controls,
3215 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3216 }
3217
45a690f6
MB		 3218 if (ret != 0)
3219 dev_err(wm8994->hubs.codec->dev,
3220 "Failed to add DRC mode controls: %d\n", ret);
3221
3222
9e6e96a1
MB		 3223 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3224 pdata->num_retune_mobile_cfgs);
3225
3226 if (pdata->num_retune_mobile_cfgs)
3227 wm8994_handle_retune_mobile_pdata(wm8994);
3228 else
8cb8e83b 3229 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3230 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3231
3232 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3233 if (pdata->micbias[i]) {
3234 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3235 pdata->micbias[i] & 0xffff);
3236 }
3237 }
9e6e96a1
MB		 3238}
3239
88766984
MB		 3240/**
3241 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3242 *
3243 * @codec: WM8994 codec
3244 * @jack: jack to report detection events on
3245 * @micbias: microphone bias to detect on
88766984
MB		 3246 *
3247 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3248 * being used to bring out signals to the processor then only platform
5ab230a7 3249 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3250 * be configured using snd_soc_jack_add_gpios() instead.
3251 *
3252 * Configuration of detection levels is available via the micbias1_lvl
3253 * and micbias2_lvl platform data members.
3254 */
3255int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3256 int micbias)
88766984 3257{
b2c812e2 3258 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3259 struct wm8994_micdet *micdet;
2a8a856d 3260 struct wm8994 *control = wm8994->wm8994;
87092e3c 3261 int reg, ret;
88766984 3262
87092e3c
MB		 3263 if (control->type != WM8994) {
3264 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3265 return -EINVAL;
87092e3c 3266 }
3a423157 3267
88766984
MB		 3268 switch (micbias) {
3269 case 1:
3270 micdet = &wm8994->micdet[0];
87092e3c
MB		 3271 if (jack)
3272 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3273 "MICBIAS1");
3274 else
3275 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3276 "MICBIAS1");
88766984
MB		 3277 break;
3278 case 2:
3279 micdet = &wm8994->micdet[1];
87092e3c
MB		 3280 if (jack)
3281 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3282 "MICBIAS1");
3283 else
3284 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3285 "MICBIAS1");
88766984
MB		 3286 break;
3287 default:
87092e3c 3288 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3289 return -EINVAL;
87092e3c 3290 }
88766984 3291
87092e3c
MB		 3292 if (ret != 0)
3293 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3294 micbias, ret);
3295
3296 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3297 micbias, jack);
88766984
MB		 3298
3299 /* Store the configuration */
3300 micdet->jack = jack;
87092e3c 3301 micdet->detecting = true;
88766984
MB		 3302
3303 /* If either of the jacks is set up then enable detection */
3304 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3305 reg = WM8994_MICD_ENA;
87092e3c 3306 else
88766984
MB		 3307 reg = 0;
3308
3309 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3310
d9f34df7
CR		 3311 /* enable MICDET and MICSHRT deboune */
3312 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3313 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3314 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3315 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3316
87092e3c
MB		 3317 snd_soc_dapm_sync(&codec->dapm);
3318
88766984
MB		 3319 return 0;
3320}
3321EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3322
e9b54de4 3323static void wm8994_mic_work(struct work_struct *work)
88766984 3324{
e9b54de4
MB		 3325 struct wm8994_priv *priv = container_of(work,
3326 struct wm8994_priv,
3327 mic_work.work);
fdfc4f3e
MB		 3328 struct regmap *regmap = priv->wm8994->regmap;
3329 struct device *dev = priv->wm8994->dev;
3330 unsigned int reg;
3331 int ret;
88766984
MB		 3332 int report;
3333
b8176627
MB		 3334 pm_runtime_get_sync(dev);
3335
fdfc4f3e
MB		 3336 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3337 if (ret < 0) {
3338 dev_err(dev, "Failed to read microphone status: %d\n",
3339 ret);
b8176627 3340 pm_runtime_put(dev);
e9b54de4 3341 return;
88766984
MB		 3342 }
3343
fdfc4f3e 3344 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3345
3346 report = 0;
87092e3c
MB		 3347 if (reg & WM8994_MIC1_DET_STS) {
3348 if (priv->micdet[0].detecting)
3349 report = SND_JACK_HEADSET;
3350 }
3351 if (reg & WM8994_MIC1_SHRT_STS) {
3352 if (priv->micdet[0].detecting)
3353 report = SND_JACK_HEADPHONE;
3354 else
3355 report |= SND_JACK_BTN_0;
3356 }
3357 if (report)
3358 priv->micdet[0].detecting = false;
3359 else
3360 priv->micdet[0].detecting = true;
3361
88766984 3362 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3363 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3364
3365 report = 0;
87092e3c
MB		 3366 if (reg & WM8994_MIC2_DET_STS) {
3367 if (priv->micdet[1].detecting)
3368 report = SND_JACK_HEADSET;
3369 }
3370 if (reg & WM8994_MIC2_SHRT_STS) {
3371 if (priv->micdet[1].detecting)
3372 report = SND_JACK_HEADPHONE;
3373 else
3374 report |= SND_JACK_BTN_0;
3375 }
3376 if (report)
3377 priv->micdet[1].detecting = false;
3378 else
3379 priv->micdet[1].detecting = true;
3380
88766984 3381 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3382 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3383
3384 pm_runtime_put(dev);
e9b54de4
MB		 3385}
3386
3387static irqreturn_t wm8994_mic_irq(int irq, void *data)
3388{
3389 struct wm8994_priv *priv = data;
8cb8e83b 3390 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3391
3392#ifndef CONFIG_SND_SOC_WM8994_MODULE
3393 trace_snd_soc_jack_irq(dev_name(codec->dev));
3394#endif
3395
3396 pm_wakeup_event(codec->dev, 300);
3397
3398 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3399
3400 return IRQ_HANDLED;
3401}
3402
f02b0de0
MB		 3403static void wm1811_micd_stop(struct snd_soc_codec *codec)
3404{
3405 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3406
3407 if (!wm8994->jackdet)
3408 return;
3409
3410 mutex_lock(&wm8994->accdet_lock);
3411
3412 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3413
3414 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3415
3416 mutex_unlock(&wm8994->accdet_lock);
3417
3418 if (wm8994->wm8994->pdata.jd_ext_cap)
3419 snd_soc_dapm_disable_pin(&codec->dapm,
3420 "MICBIAS2");
3421}
3422
78b76dbe 3423static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3424{
821edd2f 3425 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3426 int report;
821edd2f 3427
78b76dbe
MB		 3428 report = 0;
3429 if (status & 0x4)
3430 report |= SND_JACK_BTN_0;
3431
3432 if (status & 0x8)
3433 report |= SND_JACK_BTN_1;
3434
3435 if (status & 0x10)
3436 report |= SND_JACK_BTN_2;
3437
3438 if (status & 0x20)
3439 report |= SND_JACK_BTN_3;
3440
3441 if (status & 0x40)
3442 report |= SND_JACK_BTN_4;
3443
3444 if (status & 0x80)
3445 report |= SND_JACK_BTN_5;
3446
3447 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3448 wm8994->btn_mask);
3449}
3450
98869f68 3451static void wm8958_mic_id(void *data, u16 status)
78b76dbe 3452{
98869f68 3453 struct snd_soc_codec *codec = data;
78b76dbe 3454 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3455
af6b6fe4 3456 /* Either nothing present or just starting detection */
b00adf76 3457 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB		 3458 /* If nothing present then clear our statuses */
3459 dev_dbg(codec->dev, "Detected open circuit\n");
3460 wm8994->jack_mic = false;
3461 wm8994->mic_detecting = true;
b00adf76 3462
f02b0de0 3463 wm1811_micd_stop(codec);
b00adf76 3464
f02b0de0
MB		 3465 wm8958_micd_set_rate(codec);
3466
3467 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3468 wm8994->btn_mask |
3469 SND_JACK_HEADSET);
b00adf76
MB		 3470 return;
3471 }
821edd2f 3472
b00adf76
MB		 3473 /* If the measurement is showing a high impedence we've got a
3474 * microphone.
3475 */
78b76dbe 3476 if (status & 0x600) {
b00adf76
MB		 3477 dev_dbg(codec->dev, "Detected microphone\n");
3478
157a75e6 3479 wm8994->mic_detecting = false;
b00adf76
MB		 3480 wm8994->jack_mic = true;
3481
3482 wm8958_micd_set_rate(codec);
3483
3484 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3485 SND_JACK_HEADSET);
3486 }
821edd2f 3487
b00adf76 3488
78b76dbe 3489 if (status & 0xfc) {
b00adf76 3490 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3491 wm8994->mic_detecting = false;
b00adf76
MB		 3492
3493 wm8958_micd_set_rate(codec);
3494
af6b6fe4 3495 /* If we have jackdet that will detect removal */
f02b0de0 3496 wm1811_micd_stop(codec);
ecd1732f
MB		 3497
3498 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3499 SND_JACK_HEADSET);
b00adf76 3500 }
821edd2f 3501}
b00adf76 3502
c0cc3f16
MB		 3503/* Deferred mic detection to allow for extra settling time */
3504static void wm1811_mic_work(struct work_struct *work)
3505{
3506 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3507 mic_work.work);
d9dd4ada 3508 struct wm8994 *control = wm8994->wm8994;
c0cc3f16 3509 struct snd_soc_codec *codec = wm8994->hubs.codec;
4585790d 3510
c0cc3f16 3511 pm_runtime_get_sync(codec->dev);
4585790d 3512
c0cc3f16 3513 /* If required for an external cap force MICBIAS on */
d9dd4ada 3514 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3515 snd_soc_dapm_force_enable_pin(&codec->dapm,
3516 "MICBIAS2");
3517 snd_soc_dapm_sync(&codec->dapm);
3518 }
4585790d 3519
c0cc3f16 3520 mutex_lock(&wm8994->accdet_lock);
4585790d 3521
c0cc3f16 3522 dev_dbg(codec->dev, "Starting mic detection\n");
4585790d 3523
63dd5452
MB		 3524 /* Use a user-supplied callback if we have one */
3525 if (wm8994->micd_cb) {
3526 wm8994->micd_cb(wm8994->micd_cb_data);
3527 } else {
3528 /*
3529 * Start off measument of microphone impedence to find out
3530 * what's actually there.
3531 */
3532 wm8994->mic_detecting = true;
3533 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
4585790d 3534
63dd5452
MB		 3535 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3536 WM8958_MICD_ENA, WM8958_MICD_ENA);
b00adf76 3537 }
c0cc3f16
MB		 3538
3539 mutex_unlock(&wm8994->accdet_lock);
3540
3541 pm_runtime_put(codec->dev);
821edd2f
MB		 3542}
3543
af6b6fe4
MB		 3544static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3545{
3546 struct wm8994_priv *wm8994 = data;
d9dd4ada 3547 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3548 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3549 int reg, delay;
c986564b 3550 bool present;
af6b6fe4 3551
b8176627
MB		 3552 pm_runtime_get_sync(codec->dev);
3553
af6b6fe4
MB		 3554 mutex_lock(&wm8994->accdet_lock);
3555
3556 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3557 if (reg < 0) {
3558 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3559 mutex_unlock(&wm8994->accdet_lock);
b8176627 3560 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3561 return IRQ_NONE;
3562 }
3563
3564 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3565
c986564b 3566 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3567
c986564b
MB		 3568 if (present) {
3569 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3570
e9d9a968
MB		 3571 wm8958_micd_set_rate(codec);
3572
55a27786
MB		 3573 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3574 WM8958_MICB2_DISCH, 0);
3575
378ec0ca
MB		 3576 /* Disable debounce while inserted */
3577 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3578 WM1811_JACKDET_DB, 0);
3579
d9dd4ada 3580 delay = control->pdata.micdet_delay;
c0cc3f16
MB		 3581 schedule_delayed_work(&wm8994->mic_work,
3582 msecs_to_jiffies(delay));
af6b6fe4
MB		 3583 } else {
3584 dev_dbg(codec->dev, "Jack not detected\n");
3585
c0cc3f16
MB		 3586 cancel_delayed_work_sync(&wm8994->mic_work);
3587
55a27786
MB		 3588 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3589 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3590
378ec0ca
MB		 3591 /* Enable debounce while removed */
3592 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3593 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3594
af6b6fe4
MB		 3595 wm8994->mic_detecting = false;
3596 wm8994->jack_mic = false;
3597 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3598 WM8958_MICD_ENA, 0);
3599 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3600 }
3601
3602 mutex_unlock(&wm8994->accdet_lock);
3603
c0cc3f16 3604 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3605 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3606 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3607
3608 if (present)
3609 snd_soc_jack_report(wm8994->micdet[0].jack,
3610 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3611 else
3612 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3613 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3614 wm8994->btn_mask);
3615
99af79df
MB		 3616 /* Since we only report deltas force an update, ensures we
3617 * avoid bootstrapping issues with the core. */
3618 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3619
b8176627 3620 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3621 return IRQ_HANDLED;
3622}
3623
99af79df
MB		 3624static void wm1811_jackdet_bootstrap(struct work_struct *work)
3625{
3626 struct wm8994_priv *wm8994 = container_of(work,
3627 struct wm8994_priv,
3628 jackdet_bootstrap.work);
3629 wm1811_jackdet_irq(0, wm8994);
3630}
3631
821edd2f
MB		 3632/**
3633 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3634 *
3635 * @codec: WM8958 codec
3636 * @jack: jack to report detection events on
3637 *
3638 * Enable microphone detection functionality for the WM8958. By
3639 * default simple detection which supports the detection of up to 6
3640 * buttons plus video and microphone functionality is supported.
3641 *
3642 * The WM8958 has an advanced jack detection facility which is able to
3643 * support complex accessory detection, especially when used in
3644 * conjunction with external circuitry. In order to provide maximum
3645 * flexiblity a callback is provided which allows a completely custom
3646 * detection algorithm.
3647 */
3648int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
98869f68
MB		 3649 wm1811_micdet_cb det_cb, void *det_cb_data,
3650 wm1811_mic_id_cb id_cb, void *id_cb_data)
821edd2f
MB		 3651{
3652 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3653 struct wm8994 *control = wm8994->wm8994;
4585790d 3654 u16 micd_lvl_sel;
821edd2f 3655
81204c84
MB		 3656 switch (control->type) {
3657 case WM1811:
3658 case WM8958:
3659 break;
3660 default:
821edd2f 3661 return -EINVAL;
81204c84 3662 }
821edd2f
MB		 3663
3664 if (jack) {
4cdf5e49 3665 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3666 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3667
821edd2f 3668 wm8994->micdet[0].jack = jack;
821edd2f 3669
98869f68
MB		 3670 if (det_cb) {
3671 wm8994->micd_cb = det_cb;
3672 wm8994->micd_cb_data = det_cb_data;
63dd5452
MB		 3673 } else {
3674 wm8994->mic_detecting = true;
3675 wm8994->jack_mic = false;
3676 }
b00adf76 3677
98869f68
MB		 3678 if (id_cb) {
3679 wm8994->mic_id_cb = id_cb;
3680 wm8994->mic_id_cb_data = id_cb_data;
3681 } else {
3682 wm8994->mic_id_cb = wm8958_mic_id;
3683 wm8994->mic_id_cb_data = codec;
3684 }
b00adf76
MB		 3685
3686 wm8958_micd_set_rate(codec);
3687
4585790d 3688 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3689 if (control->pdata.micd_lvl_sel)
3690 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3691 else
3692 micd_lvl_sel = 0x41;
3693
3694 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3695 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3696 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3697
b00adf76 3698 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3699 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3700
af6b6fe4
MB		 3701 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3702
3703 /*
3704 * If we can use jack detection start off with that,
3705 * otherwise jump straight to microphone detection.
3706 */
3707 if (wm8994->jackdet) {
99af79df
MB		 3708 /* Disable debounce for the initial detect */
3709 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3710 WM1811_JACKDET_DB, 0);
3711
55a27786
MB		 3712 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3713 WM8958_MICB2_DISCH,
3714 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3715 snd_soc_update_bits(codec, WM8994_LDO_1,
3716 WM8994_LDO1_DISCH, 0);
3717 wm1811_jackdet_set_mode(codec,
3718 WM1811_JACKDET_MODE_JACK);
3719 } else {
3720 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3721 WM8958_MICD_ENA, WM8958_MICD_ENA);
3722 }
3723
821edd2f
MB		 3724 } else {
3725 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3726 WM8958_MICD_ENA, 0);
afaf1591 3727 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3728 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3729 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3730 }
3731
3732 return 0;
3733}
3734EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3735
3736static irqreturn_t wm8958_mic_irq(int irq, void *data)
3737{
3738 struct wm8994_priv *wm8994 = data;
8cb8e83b 3739 struct snd_soc_codec *codec = wm8994->hubs.codec;
19940b3d 3740 int reg, count;
821edd2f 3741
af6b6fe4
MB		 3742 /*
3743 * Jack detection may have detected a removal simulataneously
3744 * with an update of the MICDET status; if so it will have
3745 * stopped detection and we can ignore this interrupt.
3746 */
c986564b 3747 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3748 return IRQ_HANDLED;
af6b6fe4 3749
b8176627
MB		 3750 pm_runtime_get_sync(codec->dev);
3751
19940b3d
MB		 3752 /* We may occasionally read a detection without an impedence
3753 * range being provided - if that happens loop again.
3754 */
3755 count = 10;
3756 do {
3757 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3758 if (reg < 0) {
3759 dev_err(codec->dev,
3760 "Failed to read mic detect status: %d\n",
3761 reg);
b8176627 3762 pm_runtime_put(codec->dev);
19940b3d
MB		 3763 return IRQ_NONE;
3764 }
821edd2f 3765
19940b3d
MB		 3766 if (!(reg & WM8958_MICD_VALID)) {
3767 dev_dbg(codec->dev, "Mic detect data not valid\n");
3768 goto out;
3769 }
3770
3771 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3772 break;
3773
3774 msleep(1);
3775 } while (count--);
3776
3777 if (count == 0)
ec8f53fb 3778 dev_warn(codec->dev, "No impedance range reported for jack\n");
821edd2f 3779
7116f452 3780#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3781 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3782#endif
2bbb5d66 3783
e874de43
MB		 3784 /* Avoid a transient report when the accessory is being removed */
3785 if (wm8994->jackdet) {
3786 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3787 if (reg < 0) {
3788 dev_err(codec->dev, "Failed to read jack status: %d\n",
3789 reg);
3790 } else if (!(reg & WM1811_JACKDET_LVL)) {
3791 dev_dbg(codec->dev, "Ignoring removed jack\n");
3792 return IRQ_HANDLED;
3793 }
3794 }
3795
78b76dbe 3796 if (wm8994->mic_detecting)
98869f68 3797 wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg);
821edd2f 3798 else
78b76dbe 3799 wm8958_button_det(codec, reg);
821edd2f
MB		 3800
3801out:
b8176627 3802 pm_runtime_put(codec->dev);
821edd2f
MB		 3803 return IRQ_HANDLED;
3804}
3805
3b1af3f8
MB		 3806static irqreturn_t wm8994_fifo_error(int irq, void *data)
3807{
3808 struct snd_soc_codec *codec = data;
3809
3810 dev_err(codec->dev, "FIFO error\n");
3811
3812 return IRQ_HANDLED;
3813}
3814
f0b182b0
MB		 3815static irqreturn_t wm8994_temp_warn(int irq, void *data)
3816{
3817 struct snd_soc_codec *codec = data;
3818
3819 dev_err(codec->dev, "Thermal warning\n");
3820
3821 return IRQ_HANDLED;
3822}
3823
3824static irqreturn_t wm8994_temp_shut(int irq, void *data)
3825{
3826 struct snd_soc_codec *codec = data;
3827
3828 dev_crit(codec->dev, "Thermal shutdown\n");
3829
3830 return IRQ_HANDLED;
3831}
3832
f0fba2ad 3833static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3834{
d9a7666f 3835 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3836 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3837 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3838 unsigned int reg;
ec62dbd7 3839 int ret, i;
9e6e96a1 3840
8cb8e83b 3841 wm8994->hubs.codec = codec;
d9a7666f 3842 codec->control_data = control->regmap;
9e6e96a1 3843
d9a7666f 3844 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3845
af6b6fe4 3846 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3847 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3848 wm1811_jackdet_bootstrap);
af6b6fe4 3849
c0cc3f16
MB		 3850 switch (control->type) {
3851 case WM8994:
3852 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3853 break;
3854 case WM1811:
3855 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3856 break;
3857 default:
3858 break;
3859 }
3860
c7ebf932
MB		 3861 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3862 init_completion(&wm8994->fll_locked[i]);
3863
d9dd4ada 3864 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 3865
39fb51a1 3866 pm_runtime_enable(codec->dev);
5fab5174 3867 pm_runtime_idle(codec->dev);
39fb51a1 3868
f959dee9
MB		 3869 /* By default use idle_bias_off, will override for WM8994 */
3870 codec->dapm.idle_bias_off = 1;
3871
9e6e96a1 3872 /* Set revision-specific configuration */
b6b05691 3873 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3874 switch (control->type) {
3875 case WM8994:
f959dee9 3876 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 3877 if (!control->pdata.lineout1_diff ||
3878 !control->pdata.lineout2_diff)
f959dee9
MB		 3879 codec->dapm.idle_bias_off = 0;
3880
3a423157
MB		 3881 switch (wm8994->revision) {
3882 case 2:
3883 case 3:
4537c4e7
MB		 3884 wm8994->hubs.dcs_codes_l = -5;
3885 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3886 wm8994->hubs.hp_startup_mode = 1;
3887 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3888 wm8994->hubs.series_startup = 1;
3a423157
MB		 3889 break;
3890 default:
79ef0abc 3891 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3892 break;
3893 }
280ec8b7 3894 break;
3a423157
MB		 3895
3896 case WM8958:
8437f700 3897 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3898 wm8994->hubs.hp_startup_mode = 1;
20dc24a9
MB		 3899
3900 switch (wm8994->revision) {
3901 case 0:
3902 break;
3903 default:
3904 wm8994->fll_byp = true;
3905 break;
3906 }
9e6e96a1 3907 break;
3a423157 3908
81204c84
MB		 3909 case WM1811:
3910 wm8994->hubs.dcs_readback_mode = 2;
3911 wm8994->hubs.no_series_update = 1;
29fdc360 3912 wm8994->hubs.hp_startup_mode = 1;
af31a227 3913 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 3914 wm8994->fll_byp = true;
81204c84 3915
72222be3
MB		 3916 wm8994->hubs.dcs_codes_l = -9;
3917 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3918
3919 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3920 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3921 break;
3922
9e6e96a1
MB		 3923 default:
3924 break;
3925 }
9e6e96a1 3926
2a8a856d 3927 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3928 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3929 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3930 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3931 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3932 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3933
2a8a856d 3934 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3935 wm_hubs_dcs_done, "DC servo done",
3936 &wm8994->hubs);
3937 if (ret == 0)
3938 wm8994->hubs.dcs_done_irq = true;
3939
3a423157
MB		 3940 switch (control->type) {
3941 case WM8994:
9b7c525d
MB		 3942 if (wm8994->micdet_irq) {
3943 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3944 wm8994_mic_irq,
3945 IRQF_TRIGGER_RISING,
3946 "Mic1 detect",
3947 wm8994);
3948 if (ret != 0)
3949 dev_warn(codec->dev,
3950 "Failed to request Mic1 detect IRQ: %d\n",
3951 ret);
3952 }
3a423157 3953
2a8a856d 3954 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3955 WM8994_IRQ_MIC1_SHRT,
3956 wm8994_mic_irq, "Mic 1 short",
3957 wm8994);
3958 if (ret != 0)
3959 dev_warn(codec->dev,
3960 "Failed to request Mic1 short IRQ: %d\n",
3961 ret);
3962
2a8a856d 3963 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3964 WM8994_IRQ_MIC2_DET,
3965 wm8994_mic_irq, "Mic 2 detect",
3966 wm8994);
3967 if (ret != 0)
3968 dev_warn(codec->dev,
3969 "Failed to request Mic2 detect IRQ: %d\n",
3970 ret);
3971
2a8a856d 3972 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3973 WM8994_IRQ_MIC2_SHRT,
3974 wm8994_mic_irq, "Mic 2 short",
3975 wm8994);
3976 if (ret != 0)
3977 dev_warn(codec->dev,
3978 "Failed to request Mic2 short IRQ: %d\n",
3979 ret);
3980 break;
821edd2f
MB		 3981
3982 case WM8958:
81204c84 3983 case WM1811:
9b7c525d
MB		 3984 if (wm8994->micdet_irq) {
3985 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3986 wm8958_mic_irq,
3987 IRQF_TRIGGER_RISING,
3988 "Mic detect",
3989 wm8994);
3990 if (ret != 0)
3991 dev_warn(codec->dev,
3992 "Failed to request Mic detect IRQ: %d\n",
3993 ret);
b4046d01
MB		 3994 } else {
3995 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3996 wm8958_mic_irq, "Mic detect",
3997 wm8994);
9b7c525d 3998 }
3a423157 3999 }
88766984 4000
af6b6fe4
MB		 4001 switch (control->type) {
4002 case WM1811:
52ca1138 4003 if (control->cust_id > 1 || wm8994->revision > 1) {
af6b6fe4
MB		 4004 ret = wm8994_request_irq(wm8994->wm8994,
4005 WM8994_IRQ_GPIO(6),
4006 wm1811_jackdet_irq, "JACKDET",
4007 wm8994);
4008 if (ret == 0)
4009 wm8994->jackdet = true;
4010 }
4011 break;
4012 default:
4013 break;
4014 }
4015
c7ebf932
MB		 4016 wm8994->fll_locked_irq = true;
4017 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 4018 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 4019 WM8994_IRQ_FLL1_LOCK + i,
4020 wm8994_fll_locked_irq, "FLL lock",
4021 &wm8994->fll_locked[i]);
4022 if (ret != 0)
4023 wm8994->fll_locked_irq = false;
4024 }
4025
27060b3c
MB		 4026 /* Make sure we can read from the GPIOs if they're inputs */
4027 pm_runtime_get_sync(codec->dev);
4028
9e6e96a1
MB		 4029 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4030 * configured on init - if a system wants to do this dynamically
4031 * at runtime we can deal with that then.
4032 */
d9a7666f 4033 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 4034 if (ret < 0) {
4035 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4036 goto err_irq;
9e6e96a1 4037 }
d9a7666f 4038 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4039 wm8994->lrclk_shared[0] = 1;
4040 wm8994_dai[0].symmetric_rates = 1;
4041 } else {
4042 wm8994->lrclk_shared[0] = 0;
4043 }
4044
d9a7666f 4045 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4046 if (ret < 0) {
4047 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4048 goto err_irq;
9e6e96a1 4049 }
d9a7666f 4050 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4051 wm8994->lrclk_shared[1] = 1;
4052 wm8994_dai[1].symmetric_rates = 1;
4053 } else {
4054 wm8994->lrclk_shared[1] = 0;
4055 }
4056
27060b3c
MB		 4057 pm_runtime_put(codec->dev);
4058
bfd37bb5
MB		 4059 /* Latch volume update bits */
4060 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4061 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4062 wm8994_vu_bits[i].mask,
4063 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4064
4065 /* Set the low bit of the 3D stereo depth so TLV matches */
4066 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4067 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4068 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4069 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4070 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4071 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4072 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4073 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4074 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4075
5b739670
MB		 4076 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4077 * use this; it only affects behaviour on idle TDM clock
4078 * cycles. */
4079 switch (control->type) {
4080 case WM8994:
4081 case WM8958:
4082 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4083 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4084 break;
4085 default:
4086 break;
4087 }
d1ce6b20 4088
500fa30e
MB		 4089 /* Put MICBIAS into bypass mode by default on newer devices */
4090 switch (control->type) {
4091 case WM8958:
4092 case WM1811:
4093 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4094 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4095 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4096 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4097 break;
4098 default:
4099 break;
4100 }
4101
c340304d
MB		 4102 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4103 wm_hubs_update_class_w(codec);
9e6e96a1 4104
f0fba2ad 4105 wm8994_handle_pdata(wm8994);
9e6e96a1 4106
f0fba2ad 4107 wm_hubs_add_analogue_controls(codec);
022658be 4108 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4109 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4110 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4111 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4112
4113 switch (control->type) {
4114 case WM8994:
4115 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4116 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 4117 if (wm8994->revision < 4) {
173efa09
DP		 4118 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4119 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4120 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4121 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4122 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4123 ARRAY_SIZE(wm8994_dac_revd_widgets));
4124 } else {
173efa09
DP		 4125 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4126 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4127 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4128 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4129 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4130 ARRAY_SIZE(wm8994_dac_widgets));
4131 }
c4431df0
MB		 4132 break;
4133 case WM8958:
022658be 4134 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4135 ARRAY_SIZE(wm8958_snd_controls));
4136 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4137 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 4138 if (wm8994->revision < 1) {
4139 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4140 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4141 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4142 ARRAY_SIZE(wm8994_adc_revd_widgets));
4143 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4144 ARRAY_SIZE(wm8994_dac_revd_widgets));
4145 } else {
4146 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4147 ARRAY_SIZE(wm8994_lateclk_widgets));
4148 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4149 ARRAY_SIZE(wm8994_adc_widgets));
4150 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4151 ARRAY_SIZE(wm8994_dac_widgets));
4152 }
c4431df0 4153 break;
81204c84
MB		 4154
4155 case WM1811:
022658be 4156 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4157 ARRAY_SIZE(wm8958_snd_controls));
4158 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4159 ARRAY_SIZE(wm8958_dapm_widgets));
4160 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4161 ARRAY_SIZE(wm8994_lateclk_widgets));
4162 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4163 ARRAY_SIZE(wm8994_adc_widgets));
4164 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4165 ARRAY_SIZE(wm8994_dac_widgets));
4166 break;
c4431df0 4167 }
c4431df0 4168
f0fba2ad 4169 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4170 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4171
c4431df0
MB		 4172 switch (control->type) {
4173 case WM8994:
4174 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4175 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4176
173efa09 4177 if (wm8994->revision < 4) {
6ed8f148
MB		 4178 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4179 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4180 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4181 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4182 } else {
4183 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4184 ARRAY_SIZE(wm8994_lateclk_intercon));
4185 }
c4431df0
MB		 4186 break;
4187 case WM8958:
780e2806 4188 if (wm8994->revision < 1) {
15676937
CR		 4189 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4190 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4191 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4192 ARRAY_SIZE(wm8994_revd_intercon));
4193 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4194 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4195 } else {
4196 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4197 ARRAY_SIZE(wm8994_lateclk_intercon));
4198 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4199 ARRAY_SIZE(wm8958_intercon));
4200 }
f701a2e5
MB		 4201
4202 wm8958_dsp2_init(codec);
c4431df0 4203 break;
81204c84
MB		 4204 case WM1811:
4205 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4206 ARRAY_SIZE(wm8994_lateclk_intercon));
4207 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4208 ARRAY_SIZE(wm8958_intercon));
4209 break;
c4431df0
MB		 4210 }
4211
9e6e96a1
MB		 4212 return 0;
4213
88766984 4214err_irq:
af6b6fe4
MB		 4215 if (wm8994->jackdet)
4216 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4217 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4218 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4219 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4220 if (wm8994->micdet_irq)
4221 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4222 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4223 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4224 &wm8994->fll_locked[i]);
2a8a856d 4225 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4226 &wm8994->hubs);
2a8a856d
MB		 4227 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4228 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4229 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4230
9e6e96a1
MB		 4231 return ret;
4232}
4233
34ff0f95 4234static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4235{
f0fba2ad 4236 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4237 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4238 int i;
9e6e96a1
MB		 4239
4240 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4241
39fb51a1
MB		 4242 pm_runtime_disable(codec->dev);
4243
c7ebf932 4244 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4245 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4246 &wm8994->fll_locked[i]);
4247
2a8a856d 4248 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4249 &wm8994->hubs);
2a8a856d
MB		 4250 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4251 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4252 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4253
af6b6fe4
MB		 4254 if (wm8994->jackdet)
4255 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4256
3a423157
MB		 4257 switch (control->type) {
4258 case WM8994:
9b7c525d
MB		 4259 if (wm8994->micdet_irq)
4260 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4261 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4262 wm8994);
2a8a856d 4263 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4264 wm8994);
2a8a856d 4265 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4266 wm8994);
4267 break;
821edd2f 4268
81204c84 4269 case WM1811:
821edd2f 4270 case WM8958:
9b7c525d
MB		 4271 if (wm8994->micdet_irq)
4272 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4273 break;
3a423157 4274 }
34ff0f95
JJ		 4275 release_firmware(wm8994->mbc);
4276 release_firmware(wm8994->mbc_vss);
4277 release_firmware(wm8994->enh_eq);
24fb2b11 4278 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4279 return 0;
4280}
4281
f0fba2ad
LG		 4282static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4283 .probe = wm8994_codec_probe,
4284 .remove = wm8994_codec_remove,
4752a887
MB		 4285 .suspend = wm8994_codec_suspend,
4286 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4287 .set_bias_level = wm8994_set_bias_level,
4288};
4289
7a79e94e 4290static int wm8994_probe(struct platform_device *pdev)
f0fba2ad 4291{
2bc16ed8
MB		 4292 struct wm8994_priv *wm8994;
4293
4294 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4295 GFP_KERNEL);
4296 if (wm8994 == NULL)
4297 return -ENOMEM;
4298 platform_set_drvdata(pdev, wm8994);
4299
4300 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4301
f0fba2ad
LG		 4302 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4303 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4304}
4305
7a79e94e 4306static int wm8994_remove(struct platform_device *pdev)
f0fba2ad
LG		 4307{
4308 snd_soc_unregister_codec(&pdev->dev);
4309 return 0;
4310}
4311
4752a887
MB		 4312#ifdef CONFIG_PM_SLEEP
4313static int wm8994_suspend(struct device *dev)
4314{
4315 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4316
4317 /* Drop down to power saving mode when system is suspended */
4318 if (wm8994->jackdet && !wm8994->active_refcount)
4319 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4320 WM1811_JACKDET_MODE_MASK,
4321 wm8994->jackdet_mode);
4322
4323 return 0;
4324}
4325
4326static int wm8994_resume(struct device *dev)
4327{
4328 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4329
78b76dbe 4330 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB		 4331 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4332 WM1811_JACKDET_MODE_MASK,
4333 WM1811_JACKDET_MODE_AUDIO);
4334
4335 return 0;
4336}
4337#endif
4338
4339static const struct dev_pm_ops wm8994_pm_ops = {
4340 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4341};
4342
9e6e96a1
MB		 4343static struct platform_driver wm8994_codec_driver = {
4344 .driver = {
4752a887
MB		 4345 .name = "wm8994-codec",
4346 .owner = THIS_MODULE,
4347 .pm = &wm8994_pm_ops,
4348 },
f0fba2ad 4349 .probe = wm8994_probe,
7a79e94e 4350 .remove = wm8994_remove,
9e6e96a1
MB		 4351};
4352
5bbcc3c0 4353module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4354
4355MODULE_DESCRIPTION("ASoC WM8994 driver");
4356MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4357MODULE_LICENSE("GPL");
4358MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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