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ASoC: Convert WM8962 register access map to modern style
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (wm8994->active_refcount)
690 mode = WM1811_JACKDET_MODE_AUDIO;
691
692 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
693 WM1811_JACKDET_MODE_MASK, mode);
694
695 if (mode == WM1811_JACKDET_MODE_MIC)
696 msleep(2);
697}
698
699static void active_reference(struct snd_soc_codec *codec)
700{
701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702
703 mutex_lock(&wm8994->accdet_lock);
704
705 wm8994->active_refcount++;
706
707 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
708 wm8994->active_refcount);
709
710 if (wm8994->active_refcount == 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994->jackdet && wm8994->jack_cb) {
713 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
714 WM1811_JACKDET_MODE_MASK,
715 WM1811_JACKDET_MODE_AUDIO);
716 msleep(2);
717 }
718 }
719
720 mutex_unlock(&wm8994->accdet_lock);
721}
722
723static void active_dereference(struct snd_soc_codec *codec)
724{
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726 u16 mode;
727
728 mutex_lock(&wm8994->accdet_lock);
729
730 wm8994->active_refcount--;
731
732 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
733 wm8994->active_refcount);
734
735 if (wm8994->active_refcount == 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994->jackdet && wm8994->jack_cb) {
738 if (wm8994->jack_mic || wm8994->mic_detecting)
739 mode = WM1811_JACKDET_MODE_MIC;
740 else
741 mode = WM1811_JACKDET_MODE_JACK;
742
743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
744 WM1811_JACKDET_MODE_MASK,
745 mode);
746 }
747 }
748
749 mutex_unlock(&wm8994->accdet_lock);
750}
751
9e6e96a1
MB		 752static int clk_sys_event(struct snd_soc_dapm_widget *w,
753 struct snd_kcontrol *kcontrol, int event)
754{
755 struct snd_soc_codec *codec = w->codec;
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 return configure_clock(codec);
760
761 case SND_SOC_DAPM_POST_PMD:
762 configure_clock(codec);
763 break;
764 }
765
766 return 0;
767}
768
4b7ed83a
MB		 769static void vmid_reference(struct snd_soc_codec *codec)
770{
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
773 wm8994->vmid_refcount++;
774
775 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
776 wm8994->vmid_refcount);
777
778 if (wm8994->vmid_refcount == 1) {
779 /* Startup bias, VMID ramp & buffer */
780 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
781 WM8994_STARTUP_BIAS_ENA |
782 WM8994_VMID_BUF_ENA |
783 WM8994_VMID_RAMP_MASK,
784 WM8994_STARTUP_BIAS_ENA |
785 WM8994_VMID_BUF_ENA |
786 (0x11 << WM8994_VMID_RAMP_SHIFT));
787
788 /* Main bias enable, VMID=2x40k */
789 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
790 WM8994_BIAS_ENA |
791 WM8994_VMID_SEL_MASK,
792 WM8994_BIAS_ENA | 0x2);
793
794 msleep(20);
795 }
796}
797
798static void vmid_dereference(struct snd_soc_codec *codec)
799{
800 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
801
802 wm8994->vmid_refcount--;
803
804 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
805 wm8994->vmid_refcount);
806
807 if (wm8994->vmid_refcount == 0) {
808 /* Switch over to startup biases */
809 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810 WM8994_BIAS_SRC |
811 WM8994_STARTUP_BIAS_ENA |
812 WM8994_VMID_BUF_ENA |
813 WM8994_VMID_RAMP_MASK,
814 WM8994_BIAS_SRC |
815 WM8994_STARTUP_BIAS_ENA |
816 WM8994_VMID_BUF_ENA |
817 (1 << WM8994_VMID_RAMP_SHIFT));
818
819 /* Disable main biases */
820 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
821 WM8994_BIAS_ENA |
822 WM8994_VMID_SEL_MASK, 0);
823
824 /* Discharge line */
825 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
826 WM8994_LINEOUT1_DISCH |
827 WM8994_LINEOUT2_DISCH,
828 WM8994_LINEOUT1_DISCH |
829 WM8994_LINEOUT2_DISCH);
830
831 msleep(5);
832
833 /* Switch off startup biases */
834 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
835 WM8994_BIAS_SRC |
836 WM8994_STARTUP_BIAS_ENA |
837 WM8994_VMID_BUF_ENA |
838 WM8994_VMID_RAMP_MASK, 0);
839 }
840}
841
842static int vmid_event(struct snd_soc_dapm_widget *w,
843 struct snd_kcontrol *kcontrol, int event)
844{
845 struct snd_soc_codec *codec = w->codec;
846
847 switch (event) {
848 case SND_SOC_DAPM_PRE_PMU:
849 vmid_reference(codec);
850 break;
851
852 case SND_SOC_DAPM_POST_PMD:
853 vmid_dereference(codec);
854 break;
855 }
856
857 return 0;
858}
859
9e6e96a1
MB		 860static void wm8994_update_class_w(struct snd_soc_codec *codec)
861{
fec6dd83 862 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 863 int enable = 1;
864 int source = 0; /* GCC flow analysis can't track enable */
865 int reg, reg_r;
866
867 /* Only support direct DAC->headphone paths */
868 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
869 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 870 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 871 enable = 0;
872 }
873
874 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
875 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 876 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 877 enable = 0;
878 }
879
880 /* We also need the same setting for L/R and only one path */
881 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
882 switch (reg) {
883 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 884 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 885 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
886 break;
887 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 888 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 889 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
890 break;
891 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 892 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 893 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
894 break;
895 default:
ee839a21 896 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 897 enable = 0;
898 break;
899 }
900
901 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
902 if (reg_r != reg) {
ee839a21 903 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 904 enable = 0;
905 }
906
907 if (enable) {
908 dev_dbg(codec->dev, "Class W enabled\n");
909 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
910 WM8994_CP_DYN_PWR |
911 WM8994_CP_DYN_SRC_SEL_MASK,
912 source | WM8994_CP_DYN_PWR);
fec6dd83 913 wm8994->hubs.class_w = true;
9e6e96a1
MB		 914
915 } else {
916 dev_dbg(codec->dev, "Class W disabled\n");
917 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
918 WM8994_CP_DYN_PWR, 0);
fec6dd83 919 wm8994->hubs.class_w = false;
9e6e96a1
MB		 920 }
921}
922
173efa09
DP		 923static int late_enable_ev(struct snd_soc_dapm_widget *w,
924 struct snd_kcontrol *kcontrol, int event)
925{
926 struct snd_soc_codec *codec = w->codec;
927 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
928
929 switch (event) {
930 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 931 if (wm8994->aif1clk_enable) {
173efa09
DP		 932 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
933 WM8994_AIF1CLK_ENA_MASK,
934 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 935 wm8994->aif1clk_enable = 0;
936 }
937 if (wm8994->aif2clk_enable) {
173efa09
DP		 938 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
939 WM8994_AIF2CLK_ENA_MASK,
940 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 941 wm8994->aif2clk_enable = 0;
942 }
173efa09
DP		 943 break;
944 }
945
c6b7b570
MB		 946 /* We may also have postponed startup of DSP, handle that. */
947 wm8958_aif_ev(w, kcontrol, event);
948
173efa09
DP		 949 return 0;
950}
951
952static int late_disable_ev(struct snd_soc_dapm_widget *w,
953 struct snd_kcontrol *kcontrol, int event)
954{
955 struct snd_soc_codec *codec = w->codec;
956 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
957
958 switch (event) {
959 case SND_SOC_DAPM_POST_PMD:
a3cff81a 960 if (wm8994->aif1clk_disable) {
173efa09
DP		 961 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
962 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 963 wm8994->aif1clk_disable = 0;
173efa09 964 }
a3cff81a 965 if (wm8994->aif2clk_disable) {
173efa09
DP		 966 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
967 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 968 wm8994->aif2clk_disable = 0;
173efa09
DP		 969 }
970 break;
971 }
972
973 return 0;
974}
975
976static int aif1clk_ev(struct snd_soc_dapm_widget *w,
977 struct snd_kcontrol *kcontrol, int event)
978{
979 struct snd_soc_codec *codec = w->codec;
980 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
981
982 switch (event) {
983 case SND_SOC_DAPM_PRE_PMU:
984 wm8994->aif1clk_enable = 1;
985 break;
a3cff81a
DP		 986 case SND_SOC_DAPM_POST_PMD:
987 wm8994->aif1clk_disable = 1;
988 break;
173efa09
DP		 989 }
990
991 return 0;
992}
993
994static int aif2clk_ev(struct snd_soc_dapm_widget *w,
995 struct snd_kcontrol *kcontrol, int event)
996{
997 struct snd_soc_codec *codec = w->codec;
998 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
999
1000 switch (event) {
1001 case SND_SOC_DAPM_PRE_PMU:
1002 wm8994->aif2clk_enable = 1;
1003 break;
a3cff81a
DP		 1004 case SND_SOC_DAPM_POST_PMD:
1005 wm8994->aif2clk_disable = 1;
1006 break;
173efa09
DP		 1007 }
1008
1009 return 0;
1010}
1011
04d28681
DP		 1012static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1013 struct snd_kcontrol *kcontrol, int event)
1014{
1015 late_enable_ev(w, kcontrol, event);
1016 return 0;
1017}
1018
b462c6e6
DP		 1019static int micbias_ev(struct snd_soc_dapm_widget *w,
1020 struct snd_kcontrol *kcontrol, int event)
1021{
1022 late_enable_ev(w, kcontrol, event);
1023 return 0;
1024}
1025
c52fd021
DP		 1026static int dac_ev(struct snd_soc_dapm_widget *w,
1027 struct snd_kcontrol *kcontrol, int event)
1028{
1029 struct snd_soc_codec *codec = w->codec;
1030 unsigned int mask = 1 << w->shift;
1031
1032 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1033 mask, mask);
1034 return 0;
1035}
1036
9e6e96a1
MB		 1037static const char *hp_mux_text[] = {
1038 "Mixer",
1039 "DAC",
1040};
1041
1042#define WM8994_HP_ENUM(xname, xenum) \
1043{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1044 .info = snd_soc_info_enum_double, \
1045 .get = snd_soc_dapm_get_enum_double, \
1046 .put = wm8994_put_hp_enum, \
1047 .private_value = (unsigned long)&xenum }
1048
1049static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1050 struct snd_ctl_elem_value *ucontrol)
1051{
9d03545d
JN		 1052 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1053 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1054 struct snd_soc_codec *codec = w->codec;
1055 int ret;
1056
1057 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1058
1059 wm8994_update_class_w(codec);
1060
1061 return ret;
1062}
1063
1064static const struct soc_enum hpl_enum =
1065 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1066
1067static const struct snd_kcontrol_new hpl_mux =
1068 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1069
1070static const struct soc_enum hpr_enum =
1071 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1072
1073static const struct snd_kcontrol_new hpr_mux =
1074 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1075
1076static const char *adc_mux_text[] = {
1077 "ADC",
1078 "DMIC",
1079};
1080
1081static const struct soc_enum adc_enum =
1082 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1083
1084static const struct snd_kcontrol_new adcl_mux =
1085 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1086
1087static const struct snd_kcontrol_new adcr_mux =
1088 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1089
1090static const struct snd_kcontrol_new left_speaker_mixer[] = {
1091SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1092SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1093SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1094SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1095SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1096};
1097
1098static const struct snd_kcontrol_new right_speaker_mixer[] = {
1099SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1100SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1101SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1102SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1103SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1104};
1105
1106/* Debugging; dump chip status after DAPM transitions */
1107static int post_ev(struct snd_soc_dapm_widget *w,
1108 struct snd_kcontrol *kcontrol, int event)
1109{
1110 struct snd_soc_codec *codec = w->codec;
1111 dev_dbg(codec->dev, "SRC status: %x\n",
1112 snd_soc_read(codec,
1113 WM8994_RATE_STATUS));
1114 return 0;
1115}
1116
1117static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1118SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1119 1, 1, 0),
1120SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1121 0, 1, 0),
1122};
1123
1124static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1125SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1126 1, 1, 0),
1127SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1128 0, 1, 0),
1129};
1130
a3257ba8
MB		 1131static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1132SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1133 1, 1, 0),
1134SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1135 0, 1, 0),
1136};
1137
1138static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1139SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1140 1, 1, 0),
1141SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1142 0, 1, 0),
1143};
1144
9e6e96a1
MB		 1145static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1146SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1147 5, 1, 0),
1148SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1149 4, 1, 0),
1150SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1151 2, 1, 0),
1152SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1153 1, 1, 0),
1154SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1155 0, 1, 0),
1156};
1157
1158static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1159SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1160 5, 1, 0),
1161SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1162 4, 1, 0),
1163SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1164 2, 1, 0),
1165SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1166 1, 1, 0),
1167SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1168 0, 1, 0),
1169};
1170
1171#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1172{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1173 .info = snd_soc_info_volsw, \
1174 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1175 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1176
1177static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1178 struct snd_ctl_elem_value *ucontrol)
1179{
9d03545d
JN		 1180 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1181 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1182 struct snd_soc_codec *codec = w->codec;
1183 int ret;
1184
1185 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1186
1187 wm8994_update_class_w(codec);
1188
1189 return ret;
1190}
1191
1192static const struct snd_kcontrol_new dac1l_mix[] = {
1193WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1194 5, 1, 0),
1195WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1196 4, 1, 0),
1197WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1198 2, 1, 0),
1199WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1200 1, 1, 0),
1201WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1202 0, 1, 0),
1203};
1204
1205static const struct snd_kcontrol_new dac1r_mix[] = {
1206WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1207 5, 1, 0),
1208WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1209 4, 1, 0),
1210WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1211 2, 1, 0),
1212WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1213 1, 1, 0),
1214WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1215 0, 1, 0),
1216};
1217
1218static const char *sidetone_text[] = {
1219 "ADC/DMIC1", "DMIC2",
1220};
1221
1222static const struct soc_enum sidetone1_enum =
1223 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1224
1225static const struct snd_kcontrol_new sidetone1_mux =
1226 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1227
1228static const struct soc_enum sidetone2_enum =
1229 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1230
1231static const struct snd_kcontrol_new sidetone2_mux =
1232 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1233
1234static const char *aif1dac_text[] = {
1235 "AIF1DACDAT", "AIF3DACDAT",
1236};
1237
1238static const struct soc_enum aif1dac_enum =
1239 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1240
1241static const struct snd_kcontrol_new aif1dac_mux =
1242 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1243
1244static const char *aif2dac_text[] = {
1245 "AIF2DACDAT", "AIF3DACDAT",
1246};
1247
1248static const struct soc_enum aif2dac_enum =
1249 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1250
1251static const struct snd_kcontrol_new aif2dac_mux =
1252 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1253
1254static const char *aif2adc_text[] = {
1255 "AIF2ADCDAT", "AIF3DACDAT",
1256};
1257
1258static const struct soc_enum aif2adc_enum =
1259 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1260
1261static const struct snd_kcontrol_new aif2adc_mux =
1262 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1263
1264static const char *aif3adc_text[] = {
c4431df0 1265 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1266};
1267
c4431df0 1268static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1269 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1270
c4431df0
MB		 1271static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1272 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1273
1274static const struct soc_enum wm8958_aif3adc_enum =
1275 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1276
1277static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1278 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1279
1280static const char *mono_pcm_out_text[] = {
1281 "None", "AIF2ADCL", "AIF2ADCR",
1282};
1283
1284static const struct soc_enum mono_pcm_out_enum =
1285 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1286
1287static const struct snd_kcontrol_new mono_pcm_out_mux =
1288 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1289
1290static const char *aif2dac_src_text[] = {
1291 "AIF2", "AIF3",
1292};
1293
1294/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1295static const struct soc_enum aif2dacl_src_enum =
1296 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1297
1298static const struct snd_kcontrol_new aif2dacl_src_mux =
1299 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1300
1301static const struct soc_enum aif2dacr_src_enum =
1302 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1303
1304static const struct snd_kcontrol_new aif2dacr_src_mux =
1305 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1306
173efa09
DP		 1307static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1308SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1309 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1310SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1311 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1312
1313SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1314 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1315SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1316 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1317SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1318 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1319SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1320 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1321SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1322 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1323
1324SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1325 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1326 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1327SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1328 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1329 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1330SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1331 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1332SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1333 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1334
1335SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1336};
1337
1338static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1339SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1340SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1341SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1342SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1343 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1344SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1345 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1346SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1347SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1348};
1349
c52fd021
DP		 1350static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1351SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1352 dac_ev, SND_SOC_DAPM_PRE_PMU),
1353SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1354 dac_ev, SND_SOC_DAPM_PRE_PMU),
1355SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1356 dac_ev, SND_SOC_DAPM_PRE_PMU),
1357SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1358 dac_ev, SND_SOC_DAPM_PRE_PMU),
1359};
1360
1361static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1362SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1363SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1364SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1365SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1366};
1367
04d28681 1368static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1369SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1370 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1371SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1372 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1373};
1374
1375static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1376SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1377SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1378};
1379
9e6e96a1
MB		 1380static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1381SND_SOC_DAPM_INPUT("DMIC1DAT"),
1382SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1383SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1384
b462c6e6
DP		 1385SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1386 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1387SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1388 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1389
9e6e96a1
MB		 1390SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1391 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1392
1393SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1394SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1395SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1396
7f94de48 1397SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1398 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1399SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1400 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1401SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1402 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1403 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1404SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1405 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1406 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1407
7f94de48 1408SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1409 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1410SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1411 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1412SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1413 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1414 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1415SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1416 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1417 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1418
1419SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1420 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1421SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1422 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1423
a3257ba8
MB		 1424SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1425 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1426SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1427 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1428
9e6e96a1
MB		 1429SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1430 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1431SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1432 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1433
1434SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1435SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1436
1437SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1438 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1439SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1440 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1441
1442SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1443 WM8994_POWER_MANAGEMENT_4, 13, 0),
1444SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1445 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1446SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1447 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1448 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1449SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1450 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1451 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1452
1453SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1454SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1455SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1456SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1457
1458SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1459SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1460SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1461
1462SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
35024f49 1463SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1464
1465SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1466
1467SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1468SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1469SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1470SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1471
1472/* Power is done with the muxes since the ADC power also controls the
1473 * downsampling chain, the chip will automatically manage the analogue
1474 * specific portions.
1475 */
1476SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1477SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1478
9e6e96a1
MB		 1479SND_SOC_DAPM_POST("Debug log", post_ev),
1480};
1481
c4431df0
MB		 1482static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1483SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1484};
9e6e96a1 1485
c4431df0
MB		 1486static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1487SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1488SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1489SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1490SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1491};
1492
1493static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1494 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1495 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1496
1497 { "DSP1CLK", NULL, "CLK_SYS" },
1498 { "DSP2CLK", NULL, "CLK_SYS" },
1499 { "DSPINTCLK", NULL, "CLK_SYS" },
1500
1501 { "AIF1ADC1L", NULL, "AIF1CLK" },
1502 { "AIF1ADC1L", NULL, "DSP1CLK" },
1503 { "AIF1ADC1R", NULL, "AIF1CLK" },
1504 { "AIF1ADC1R", NULL, "DSP1CLK" },
1505 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1506
1507 { "AIF1DAC1L", NULL, "AIF1CLK" },
1508 { "AIF1DAC1L", NULL, "DSP1CLK" },
1509 { "AIF1DAC1R", NULL, "AIF1CLK" },
1510 { "AIF1DAC1R", NULL, "DSP1CLK" },
1511 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1512
1513 { "AIF1ADC2L", NULL, "AIF1CLK" },
1514 { "AIF1ADC2L", NULL, "DSP1CLK" },
1515 { "AIF1ADC2R", NULL, "AIF1CLK" },
1516 { "AIF1ADC2R", NULL, "DSP1CLK" },
1517 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1518
1519 { "AIF1DAC2L", NULL, "AIF1CLK" },
1520 { "AIF1DAC2L", NULL, "DSP1CLK" },
1521 { "AIF1DAC2R", NULL, "AIF1CLK" },
1522 { "AIF1DAC2R", NULL, "DSP1CLK" },
1523 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1524
1525 { "AIF2ADCL", NULL, "AIF2CLK" },
1526 { "AIF2ADCL", NULL, "DSP2CLK" },
1527 { "AIF2ADCR", NULL, "AIF2CLK" },
1528 { "AIF2ADCR", NULL, "DSP2CLK" },
1529 { "AIF2ADCR", NULL, "DSPINTCLK" },
1530
1531 { "AIF2DACL", NULL, "AIF2CLK" },
1532 { "AIF2DACL", NULL, "DSP2CLK" },
1533 { "AIF2DACR", NULL, "AIF2CLK" },
1534 { "AIF2DACR", NULL, "DSP2CLK" },
1535 { "AIF2DACR", NULL, "DSPINTCLK" },
1536
1537 { "DMIC1L", NULL, "DMIC1DAT" },
1538 { "DMIC1L", NULL, "CLK_SYS" },
1539 { "DMIC1R", NULL, "DMIC1DAT" },
1540 { "DMIC1R", NULL, "CLK_SYS" },
1541 { "DMIC2L", NULL, "DMIC2DAT" },
1542 { "DMIC2L", NULL, "CLK_SYS" },
1543 { "DMIC2R", NULL, "DMIC2DAT" },
1544 { "DMIC2R", NULL, "CLK_SYS" },
1545
1546 { "ADCL", NULL, "AIF1CLK" },
1547 { "ADCL", NULL, "DSP1CLK" },
1548 { "ADCL", NULL, "DSPINTCLK" },
1549
1550 { "ADCR", NULL, "AIF1CLK" },
1551 { "ADCR", NULL, "DSP1CLK" },
1552 { "ADCR", NULL, "DSPINTCLK" },
1553
1554 { "ADCL Mux", "ADC", "ADCL" },
1555 { "ADCL Mux", "DMIC", "DMIC1L" },
1556 { "ADCR Mux", "ADC", "ADCR" },
1557 { "ADCR Mux", "DMIC", "DMIC1R" },
1558
1559 { "DAC1L", NULL, "AIF1CLK" },
1560 { "DAC1L", NULL, "DSP1CLK" },
1561 { "DAC1L", NULL, "DSPINTCLK" },
1562
1563 { "DAC1R", NULL, "AIF1CLK" },
1564 { "DAC1R", NULL, "DSP1CLK" },
1565 { "DAC1R", NULL, "DSPINTCLK" },
1566
1567 { "DAC2L", NULL, "AIF2CLK" },
1568 { "DAC2L", NULL, "DSP2CLK" },
1569 { "DAC2L", NULL, "DSPINTCLK" },
1570
1571 { "DAC2R", NULL, "AIF2DACR" },
1572 { "DAC2R", NULL, "AIF2CLK" },
1573 { "DAC2R", NULL, "DSP2CLK" },
1574 { "DAC2R", NULL, "DSPINTCLK" },
1575
1576 { "TOCLK", NULL, "CLK_SYS" },
1577
1578 /* AIF1 outputs */
1579 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1580 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1581 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1582
1583 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1584 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1585 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1586
a3257ba8
MB		 1587 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1588 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1589 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1590
1591 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1592 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1593 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1594
9e6e96a1
MB		 1595 /* Pin level routing for AIF3 */
1596 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1597 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1598 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1599 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1600
9e6e96a1
MB		 1601 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1602 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1603 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1604 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1605 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1606 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1607 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1608
1609 /* DAC1 inputs */
9e6e96a1
MB		 1610 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1611 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1612 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1613 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1614 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1615
9e6e96a1
MB		 1616 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1617 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1618 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1619 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1620 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1621
1622 /* DAC2/AIF2 outputs */
1623 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1624 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1625 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1626 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1627 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1628 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1629
1630 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1631 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1632 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1633 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1634 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1635 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1636
7f94de48
MB		 1637 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1638 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1639 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1640 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1641
9e6e96a1
MB		 1642 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1643
1644 /* AIF3 output */
1645 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1646 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1647 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1648 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1649 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1650 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1651 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1652 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1653
1654 /* Sidetone */
1655 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1656 { "Left Sidetone", "DMIC2", "DMIC2L" },
1657 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1658 { "Right Sidetone", "DMIC2", "DMIC2R" },
1659
1660 /* Output stages */
1661 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1662 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1663
1664 { "SPKL", "DAC1 Switch", "DAC1L" },
1665 { "SPKL", "DAC2 Switch", "DAC2L" },
1666
1667 { "SPKR", "DAC1 Switch", "DAC1R" },
1668 { "SPKR", "DAC2 Switch", "DAC2R" },
1669
1670 { "Left Headphone Mux", "DAC", "DAC1L" },
1671 { "Right Headphone Mux", "DAC", "DAC1R" },
1672};
1673
173efa09
DP		 1674static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1675 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1676 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1677 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1678 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1679 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1680 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1681 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1682 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1683};
1684
1685static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1686 { "DAC1L", NULL, "DAC1L Mixer" },
1687 { "DAC1R", NULL, "DAC1R Mixer" },
1688 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1689 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1690};
1691
6ed8f148
MB		 1692static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1693 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1694 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1695 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1696 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1697 { "MICBIAS1", NULL, "CLK_SYS" },
1698 { "MICBIAS1", NULL, "MICBIAS Supply" },
1699 { "MICBIAS2", NULL, "CLK_SYS" },
1700 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1701};
1702
c4431df0
MB		 1703static const struct snd_soc_dapm_route wm8994_intercon[] = {
1704 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1705 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1706 { "MICBIAS1", NULL, "VMID" },
1707 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1708};
1709
1710static const struct snd_soc_dapm_route wm8958_intercon[] = {
1711 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1712 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1713
1714 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1715 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1716 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1717 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1718
1719 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1720 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1721
1722 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1723};
1724
9e6e96a1
MB		 1725/* The size in bits of the FLL divide multiplied by 10
1726 * to allow rounding later */
1727#define FIXED_FLL_SIZE ((1 << 16) * 10)
1728
1729struct fll_div {
1730 u16 outdiv;
1731 u16 n;
1732 u16 k;
1733 u16 clk_ref_div;
1734 u16 fll_fratio;
1735};
1736
1737static int wm8994_get_fll_config(struct fll_div *fll,
1738 int freq_in, int freq_out)
1739{
1740 u64 Kpart;
1741 unsigned int K, Ndiv, Nmod;
1742
1743 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1744
1745 /* Scale the input frequency down to <= 13.5MHz */
1746 fll->clk_ref_div = 0;
1747 while (freq_in > 13500000) {
1748 fll->clk_ref_div++;
1749 freq_in /= 2;
1750
1751 if (fll->clk_ref_div > 3)
1752 return -EINVAL;
1753 }
1754 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1755
1756 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1757 fll->outdiv = 3;
1758 while (freq_out * (fll->outdiv + 1) < 90000000) {
1759 fll->outdiv++;
1760 if (fll->outdiv > 63)
1761 return -EINVAL;
1762 }
1763 freq_out *= fll->outdiv + 1;
1764 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1765
1766 if (freq_in > 1000000) {
1767 fll->fll_fratio = 0;
7d48a6ac
MB		 1768 } else if (freq_in > 256000) {
1769 fll->fll_fratio = 1;
1770 freq_in *= 2;
1771 } else if (freq_in > 128000) {
1772 fll->fll_fratio = 2;
1773 freq_in *= 4;
1774 } else if (freq_in > 64000) {
9e6e96a1
MB		 1775 fll->fll_fratio = 3;
1776 freq_in *= 8;
7d48a6ac
MB		 1777 } else {
1778 fll->fll_fratio = 4;
1779 freq_in *= 16;
9e6e96a1
MB		 1780 }
1781 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1782
1783 /* Now, calculate N.K */
1784 Ndiv = freq_out / freq_in;
1785
1786 fll->n = Ndiv;
1787 Nmod = freq_out % freq_in;
1788 pr_debug("Nmod=%d\n", Nmod);
1789
1790 /* Calculate fractional part - scale up so we can round. */
1791 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1792
1793 do_div(Kpart, freq_in);
1794
1795 K = Kpart & 0xFFFFFFFF;
1796
1797 if ((K % 10) >= 5)
1798 K += 5;
1799
1800 /* Move down to proper range now rounding is done */
1801 fll->k = K / 10;
1802
1803 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1804
1805 return 0;
1806}
1807
f0fba2ad 1808static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1809 unsigned int freq_in, unsigned int freq_out)
1810{
b2c812e2 1811 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1812 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1813 int reg_offset, ret;
1814 struct fll_div fll;
1815 u16 reg, aif1, aif2;
c7ebf932 1816 unsigned long timeout;
4b7ed83a 1817 bool was_enabled;
9e6e96a1
MB		 1818
1819 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1820 & WM8994_AIF1CLK_ENA;
1821
1822 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1823 & WM8994_AIF2CLK_ENA;
1824
1825 switch (id) {
1826 case WM8994_FLL1:
1827 reg_offset = 0;
1828 id = 0;
1829 break;
1830 case WM8994_FLL2:
1831 reg_offset = 0x20;
1832 id = 1;
1833 break;
1834 default:
1835 return -EINVAL;
1836 }
1837
4b7ed83a
MB		 1838 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1839 was_enabled = reg & WM8994_FLL1_ENA;
1840
136ff2a2 1841 switch (src) {
7add84aa
MB		 1842 case 0:
1843 /* Allow no source specification when stopping */
1844 if (freq_out)
1845 return -EINVAL;
4514e899 1846 src = wm8994->fll[id].src;
7add84aa 1847 break;
136ff2a2
MB		 1848 case WM8994_FLL_SRC_MCLK1:
1849 case WM8994_FLL_SRC_MCLK2:
1850 case WM8994_FLL_SRC_LRCLK:
1851 case WM8994_FLL_SRC_BCLK:
1852 break;
1853 default:
1854 return -EINVAL;
1855 }
1856
9e6e96a1
MB		 1857 /* Are we changing anything? */
1858 if (wm8994->fll[id].src == src &&
1859 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1860 return 0;
1861
1862 /* If we're stopping the FLL redo the old config - no
1863 * registers will actually be written but we avoid GCC flow
1864 * analysis bugs spewing warnings.
1865 */
1866 if (freq_out)
1867 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1868 else
1869 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1870 wm8994->fll[id].out);
1871 if (ret < 0)
1872 return ret;
1873
1874 /* Gate the AIF clocks while we reclock */
1875 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1876 WM8994_AIF1CLK_ENA, 0);
1877 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1878 WM8994_AIF2CLK_ENA, 0);
1879
1880 /* We always need to disable the FLL while reconfiguring */
1881 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1882 WM8994_FLL1_ENA, 0);
1883
1884 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1885 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1886 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1887 WM8994_FLL1_OUTDIV_MASK |
1888 WM8994_FLL1_FRATIO_MASK, reg);
1889
1890 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1891
1892 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1893 WM8994_FLL1_N_MASK,
1894 fll.n << WM8994_FLL1_N_SHIFT);
1895
1896 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1897 WM8994_FLL1_REFCLK_DIV_MASK |
1898 WM8994_FLL1_REFCLK_SRC_MASK,
1899 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1900 (src - 1));
9e6e96a1 1901
f0f5039c
MB		 1902 /* Clear any pending completion from a previous failure */
1903 try_wait_for_completion(&wm8994->fll_locked[id]);
1904
9e6e96a1
MB		 1905 /* Enable (with fractional mode if required) */
1906 if (freq_out) {
4b7ed83a
MB		 1907 /* Enable VMID if we need it */
1908 if (!was_enabled) {
af6b6fe4
MB		 1909 active_reference(codec);
1910
4b7ed83a
MB		 1911 switch (control->type) {
1912 case WM8994:
1913 vmid_reference(codec);
1914 break;
1915 case WM8958:
1916 if (wm8994->revision < 1)
1917 vmid_reference(codec);
1918 break;
1919 default:
1920 break;
1921 }
1922 }
1923
9e6e96a1
MB		 1924 if (fll.k)
1925 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1926 else
1927 reg = WM8994_FLL1_ENA;
1928 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1929 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1930 reg);
8e9ddf81 1931
c7ebf932
MB		 1932 if (wm8994->fll_locked_irq) {
1933 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1934 msecs_to_jiffies(10));
1935 if (timeout == 0)
1936 dev_warn(codec->dev,
1937 "Timed out waiting for FLL lock\n");
1938 } else {
1939 msleep(5);
1940 }
4b7ed83a
MB		 1941 } else {
1942 if (was_enabled) {
1943 switch (control->type) {
1944 case WM8994:
1945 vmid_dereference(codec);
1946 break;
1947 case WM8958:
1948 if (wm8994->revision < 1)
1949 vmid_dereference(codec);
1950 break;
1951 default:
1952 break;
1953 }
af6b6fe4
MB		 1954
1955 active_dereference(codec);
4b7ed83a 1956 }
9e6e96a1
MB		 1957 }
1958
1959 wm8994->fll[id].in = freq_in;
1960 wm8994->fll[id].out = freq_out;
136ff2a2 1961 wm8994->fll[id].src = src;
9e6e96a1
MB		 1962
1963 /* Enable any gated AIF clocks */
1964 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1965 WM8994_AIF1CLK_ENA, aif1);
1966 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1967 WM8994_AIF2CLK_ENA, aif2);
1968
1969 configure_clock(codec);
1970
1971 return 0;
1972}
1973
c7ebf932
MB		 1974static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1975{
1976 struct completion *completion = data;
1977
1978 complete(completion);
1979
1980 return IRQ_HANDLED;
1981}
f0fba2ad 1982
66b47fdb
MB		 1983static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1984
f0fba2ad
LG		 1985static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1986 unsigned int freq_in, unsigned int freq_out)
1987{
1988 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1989}
1990
9e6e96a1
MB		 1991static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1992 int clk_id, unsigned int freq, int dir)
1993{
1994 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1995 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1996 int i;
9e6e96a1
MB		 1997
1998 switch (dai->id) {
1999 case 1:
2000 case 2:
2001 break;
2002
2003 default:
2004 /* AIF3 shares clocking with AIF1/2 */
2005 return -EINVAL;
2006 }
2007
2008 switch (clk_id) {
2009 case WM8994_SYSCLK_MCLK1:
2010 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2011 wm8994->mclk[0] = freq;
2012 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2013 dai->id, freq);
2014 break;
2015
2016 case WM8994_SYSCLK_MCLK2:
2017 /* TODO: Set GPIO AF */
2018 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2019 wm8994->mclk[1] = freq;
2020 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2021 dai->id, freq);
2022 break;
2023
2024 case WM8994_SYSCLK_FLL1:
2025 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2026 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2027 break;
2028
2029 case WM8994_SYSCLK_FLL2:
2030 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2031 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2032 break;
2033
66b47fdb
MB		 2034 case WM8994_SYSCLK_OPCLK:
2035 /* Special case - a division (times 10) is given and
2036 * no effect on main clocking.
2037 */
2038 if (freq) {
2039 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2040 if (opclk_divs[i] == freq)
2041 break;
2042 if (i == ARRAY_SIZE(opclk_divs))
2043 return -EINVAL;
2044 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2045 WM8994_OPCLK_DIV_MASK, i);
2046 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2047 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2048 } else {
2049 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2050 WM8994_OPCLK_ENA, 0);
2051 }
2052
9e6e96a1
MB		 2053 default:
2054 return -EINVAL;
2055 }
2056
2057 configure_clock(codec);
2058
2059 return 0;
2060}
2061
2062static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2063 enum snd_soc_bias_level level)
2064{
b6b05691 2065 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2066 struct wm8994 *control = wm8994->wm8994;
b6b05691 2067
9e6e96a1
MB		 2068 switch (level) {
2069 case SND_SOC_BIAS_ON:
2070 break;
2071
2072 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2073 /* MICBIAS into regulating mode */
2074 switch (control->type) {
2075 case WM8958:
2076 case WM1811:
2077 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2078 WM8958_MICB1_MODE, 0);
2079 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2080 WM8958_MICB2_MODE, 0);
2081 break;
2082 default:
2083 break;
2084 }
af6b6fe4
MB		 2085
2086 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2087 active_reference(codec);
9e6e96a1
MB		 2088 break;
2089
2090 case SND_SOC_BIAS_STANDBY:
ce6120cc 2091 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2
MB		 2092 switch (control->type) {
2093 case WM8994:
2094 if (wm8994->revision < 4) {
2095 /* Tweak DC servo and DSP
2096 * configuration for improved
2097 * performance. */
2098 snd_soc_write(codec, 0x102, 0x3);
2099 snd_soc_write(codec, 0x56, 0x3);
2100 snd_soc_write(codec, 0x817, 0);
2101 snd_soc_write(codec, 0x102, 0);
2102 }
2103 break;
2104
2105 case WM8958:
2106 if (wm8994->revision == 0) {
2107 /* Optimise performance for rev A */
2108 snd_soc_write(codec, 0x102, 0x3);
2109 snd_soc_write(codec, 0xcb, 0x81);
2110 snd_soc_write(codec, 0x817, 0);
2111 snd_soc_write(codec, 0x102, 0);
2112
2113 snd_soc_update_bits(codec,
2114 WM8958_CHARGE_PUMP_2,
2115 WM8958_CP_DISCH,
2116 WM8958_CP_DISCH);
2117 }
2118 break;
81204c84
MB		 2119
2120 case WM1811:
2121 if (wm8994->revision < 2) {
2122 snd_soc_write(codec, 0x102, 0x3);
2123 snd_soc_write(codec, 0x5d, 0x7e);
2124 snd_soc_write(codec, 0x5e, 0x0);
2125 snd_soc_write(codec, 0x102, 0x0);
2126 }
2127 break;
b6b05691 2128 }
9e6e96a1
MB		 2129
2130 /* Discharge LINEOUT1 & 2 */
2131 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2132 WM8994_LINEOUT1_DISCH |
2133 WM8994_LINEOUT2_DISCH,
2134 WM8994_LINEOUT1_DISCH |
2135 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2136 }
2137
af6b6fe4
MB		 2138 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2139 active_dereference(codec);
2140
500fa30e
MB		 2141 /* MICBIAS into bypass mode on newer devices */
2142 switch (control->type) {
2143 case WM8958:
2144 case WM1811:
2145 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2146 WM8958_MICB1_MODE,
2147 WM8958_MICB1_MODE);
2148 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2149 WM8958_MICB2_MODE,
2150 WM8958_MICB2_MODE);
2151 break;
2152 default:
2153 break;
2154 }
9e6e96a1
MB		 2155 break;
2156
2157 case SND_SOC_BIAS_OFF:
4105ab84 2158 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2159 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2160 break;
2161 }
ce6120cc 2162 codec->dapm.bias_level = level;
af6b6fe4 2163
9e6e96a1
MB		 2164 return 0;
2165}
2166
2167static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2168{
2169 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2170 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2171 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2172 int ms_reg;
2173 int aif1_reg;
2174 int ms = 0;
2175 int aif1 = 0;
2176
2177 switch (dai->id) {
2178 case 1:
2179 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2180 aif1_reg = WM8994_AIF1_CONTROL_1;
2181 break;
2182 case 2:
2183 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2184 aif1_reg = WM8994_AIF2_CONTROL_1;
2185 break;
2186 default:
2187 return -EINVAL;
2188 }
2189
2190 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2191 case SND_SOC_DAIFMT_CBS_CFS:
2192 break;
2193 case SND_SOC_DAIFMT_CBM_CFM:
2194 ms = WM8994_AIF1_MSTR;
2195 break;
2196 default:
2197 return -EINVAL;
2198 }
2199
2200 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2201 case SND_SOC_DAIFMT_DSP_B:
2202 aif1 |= WM8994_AIF1_LRCLK_INV;
2203 case SND_SOC_DAIFMT_DSP_A:
2204 aif1 |= 0x18;
2205 break;
2206 case SND_SOC_DAIFMT_I2S:
2207 aif1 |= 0x10;
2208 break;
2209 case SND_SOC_DAIFMT_RIGHT_J:
2210 break;
2211 case SND_SOC_DAIFMT_LEFT_J:
2212 aif1 |= 0x8;
2213 break;
2214 default:
2215 return -EINVAL;
2216 }
2217
2218 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2219 case SND_SOC_DAIFMT_DSP_A:
2220 case SND_SOC_DAIFMT_DSP_B:
2221 /* frame inversion not valid for DSP modes */
2222 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2223 case SND_SOC_DAIFMT_NB_NF:
2224 break;
2225 case SND_SOC_DAIFMT_IB_NF:
2226 aif1 |= WM8994_AIF1_BCLK_INV;
2227 break;
2228 default:
2229 return -EINVAL;
2230 }
2231 break;
2232
2233 case SND_SOC_DAIFMT_I2S:
2234 case SND_SOC_DAIFMT_RIGHT_J:
2235 case SND_SOC_DAIFMT_LEFT_J:
2236 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2237 case SND_SOC_DAIFMT_NB_NF:
2238 break;
2239 case SND_SOC_DAIFMT_IB_IF:
2240 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2241 break;
2242 case SND_SOC_DAIFMT_IB_NF:
2243 aif1 |= WM8994_AIF1_BCLK_INV;
2244 break;
2245 case SND_SOC_DAIFMT_NB_IF:
2246 aif1 |= WM8994_AIF1_LRCLK_INV;
2247 break;
2248 default:
2249 return -EINVAL;
2250 }
2251 break;
2252 default:
2253 return -EINVAL;
2254 }
2255
c4431df0
MB		 2256 /* The AIF2 format configuration needs to be mirrored to AIF3
2257 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2258 switch (control->type) {
2259 case WM1811:
2260 case WM8958:
2261 if (dai->id == 2)
2262 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2263 WM8994_AIF1_LRCLK_INV |
2264 WM8958_AIF3_FMT_MASK, aif1);
2265 break;
2266
2267 default:
2268 break;
2269 }
c4431df0 2270
9e6e96a1
MB		 2271 snd_soc_update_bits(codec, aif1_reg,
2272 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2273 WM8994_AIF1_FMT_MASK,
2274 aif1);
2275 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2276 ms);
2277
2278 return 0;
2279}
2280
2281static struct {
2282 int val, rate;
2283} srs[] = {
2284 { 0, 8000 },
2285 { 1, 11025 },
2286 { 2, 12000 },
2287 { 3, 16000 },
2288 { 4, 22050 },
2289 { 5, 24000 },
2290 { 6, 32000 },
2291 { 7, 44100 },
2292 { 8, 48000 },
2293 { 9, 88200 },
2294 { 10, 96000 },
2295};
2296
2297static int fs_ratios[] = {
2298 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2299};
2300
2301static int bclk_divs[] = {
2302 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2303 640, 880, 960, 1280, 1760, 1920
2304};
2305
2306static int wm8994_hw_params(struct snd_pcm_substream *substream,
2307 struct snd_pcm_hw_params *params,
2308 struct snd_soc_dai *dai)
2309{
2310 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2311 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2312 int aif1_reg;
b1e43d93 2313 int aif2_reg;
9e6e96a1
MB		 2314 int bclk_reg;
2315 int lrclk_reg;
2316 int rate_reg;
2317 int aif1 = 0;
b1e43d93 2318 int aif2 = 0;
9e6e96a1
MB		 2319 int bclk = 0;
2320 int lrclk = 0;
2321 int rate_val = 0;
2322 int id = dai->id - 1;
2323
2324 int i, cur_val, best_val, bclk_rate, best;
2325
2326 switch (dai->id) {
2327 case 1:
2328 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2329 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2330 bclk_reg = WM8994_AIF1_BCLK;
2331 rate_reg = WM8994_AIF1_RATE;
2332 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2333 wm8994->lrclk_shared[0]) {
9e6e96a1 2334 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2335 } else {
9e6e96a1 2336 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2337 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2338 }
9e6e96a1
MB		 2339 break;
2340 case 2:
2341 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2342 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2343 bclk_reg = WM8994_AIF2_BCLK;
2344 rate_reg = WM8994_AIF2_RATE;
2345 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2346 wm8994->lrclk_shared[1]) {
9e6e96a1 2347 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2348 } else {
9e6e96a1 2349 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2350 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2351 }
9e6e96a1
MB		 2352 break;
2353 default:
2354 return -EINVAL;
2355 }
2356
2357 bclk_rate = params_rate(params) * 2;
2358 switch (params_format(params)) {
2359 case SNDRV_PCM_FORMAT_S16_LE:
2360 bclk_rate *= 16;
2361 break;
2362 case SNDRV_PCM_FORMAT_S20_3LE:
2363 bclk_rate *= 20;
2364 aif1 |= 0x20;
2365 break;
2366 case SNDRV_PCM_FORMAT_S24_LE:
2367 bclk_rate *= 24;
2368 aif1 |= 0x40;
2369 break;
2370 case SNDRV_PCM_FORMAT_S32_LE:
2371 bclk_rate *= 32;
2372 aif1 |= 0x60;
2373 break;
2374 default:
2375 return -EINVAL;
2376 }
2377
2378 /* Try to find an appropriate sample rate; look for an exact match. */
2379 for (i = 0; i < ARRAY_SIZE(srs); i++)
2380 if (srs[i].rate == params_rate(params))
2381 break;
2382 if (i == ARRAY_SIZE(srs))
2383 return -EINVAL;
2384 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2385
2386 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2387 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2388 dai->id, wm8994->aifclk[id], bclk_rate);
2389
b1e43d93
MB		 2390 if (params_channels(params) == 1 &&
2391 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2392 aif2 |= WM8994_AIF1_MONO;
2393
9e6e96a1
MB		 2394 if (wm8994->aifclk[id] == 0) {
2395 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2396 return -EINVAL;
2397 }
2398
2399 /* AIFCLK/fs ratio; look for a close match in either direction */
2400 best = 0;
2401 best_val = abs((fs_ratios[0] * params_rate(params))
2402 - wm8994->aifclk[id]);
2403 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2404 cur_val = abs((fs_ratios[i] * params_rate(params))
2405 - wm8994->aifclk[id]);
2406 if (cur_val >= best_val)
2407 continue;
2408 best = i;
2409 best_val = cur_val;
2410 }
2411 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2412 dai->id, fs_ratios[best]);
2413 rate_val |= best;
2414
2415 /* We may not get quite the right frequency if using
2416 * approximate clocks so look for the closest match that is
2417 * higher than the target (we need to ensure that there enough
2418 * BCLKs to clock out the samples).
2419 */
2420 best = 0;
2421 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2422 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2423 if (cur_val < 0) /* BCLK table is sorted */
2424 break;
2425 best = i;
2426 }
07cd8ada 2427 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2428 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2429 bclk_divs[best], bclk_rate);
2430 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2431
2432 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2433 if (!lrclk) {
2434 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2435 bclk_rate);
2436 return -EINVAL;
2437 }
9e6e96a1
MB		 2438 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2439 lrclk, bclk_rate / lrclk);
2440
2441 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2442 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2443 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2444 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2445 lrclk);
2446 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2447 WM8994_AIF1CLK_RATE_MASK, rate_val);
2448
2449 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2450 switch (dai->id) {
2451 case 1:
2452 wm8994->dac_rates[0] = params_rate(params);
2453 wm8994_set_retune_mobile(codec, 0);
2454 wm8994_set_retune_mobile(codec, 1);
2455 break;
2456 case 2:
2457 wm8994->dac_rates[1] = params_rate(params);
2458 wm8994_set_retune_mobile(codec, 2);
2459 break;
2460 }
2461 }
2462
2463 return 0;
2464}
2465
c4431df0
MB		 2466static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2467 struct snd_pcm_hw_params *params,
2468 struct snd_soc_dai *dai)
2469{
2470 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2471 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2472 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2473 int aif1_reg;
2474 int aif1 = 0;
2475
2476 switch (dai->id) {
2477 case 3:
2478 switch (control->type) {
81204c84 2479 case WM1811:
c4431df0
MB		 2480 case WM8958:
2481 aif1_reg = WM8958_AIF3_CONTROL_1;
2482 break;
2483 default:
2484 return 0;
2485 }
2486 default:
2487 return 0;
2488 }
2489
2490 switch (params_format(params)) {
2491 case SNDRV_PCM_FORMAT_S16_LE:
2492 break;
2493 case SNDRV_PCM_FORMAT_S20_3LE:
2494 aif1 |= 0x20;
2495 break;
2496 case SNDRV_PCM_FORMAT_S24_LE:
2497 aif1 |= 0x40;
2498 break;
2499 case SNDRV_PCM_FORMAT_S32_LE:
2500 aif1 |= 0x60;
2501 break;
2502 default:
2503 return -EINVAL;
2504 }
2505
2506 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2507}
2508
7d02173c
MB		 2509static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2510 struct snd_soc_dai *dai)
2511{
2512 struct snd_soc_codec *codec = dai->codec;
2513 int rate_reg = 0;
2514
2515 switch (dai->id) {
2516 case 1:
2517 rate_reg = WM8994_AIF1_RATE;
2518 break;
2519 case 2:
c527e6aa 2520 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2521 break;
2522 default:
2523 break;
2524 }
2525
2526 /* If the DAI is idle then configure the divider tree for the
2527 * lowest output rate to save a little power if the clock is
2528 * still active (eg, because it is system clock).
2529 */
2530 if (rate_reg && !dai->playback_active && !dai->capture_active)
2531 snd_soc_update_bits(codec, rate_reg,
2532 WM8994_AIF1_SR_MASK |
2533 WM8994_AIF1CLK_RATE_MASK, 0x9);
2534}
2535
9e6e96a1
MB		 2536static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2537{
2538 struct snd_soc_codec *codec = codec_dai->codec;
2539 int mute_reg;
2540 int reg;
2541
2542 switch (codec_dai->id) {
2543 case 1:
2544 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2545 break;
2546 case 2:
2547 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2548 break;
2549 default:
2550 return -EINVAL;
2551 }
2552
2553 if (mute)
2554 reg = WM8994_AIF1DAC1_MUTE;
2555 else
2556 reg = 0;
2557
2558 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2559
2560 return 0;
2561}
2562
778a76e2
MB		 2563static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2564{
2565 struct snd_soc_codec *codec = codec_dai->codec;
2566 int reg, val, mask;
2567
2568 switch (codec_dai->id) {
2569 case 1:
2570 reg = WM8994_AIF1_MASTER_SLAVE;
2571 mask = WM8994_AIF1_TRI;
2572 break;
2573 case 2:
2574 reg = WM8994_AIF2_MASTER_SLAVE;
2575 mask = WM8994_AIF2_TRI;
2576 break;
2577 case 3:
2578 reg = WM8994_POWER_MANAGEMENT_6;
2579 mask = WM8994_AIF3_TRI;
2580 break;
2581 default:
2582 return -EINVAL;
2583 }
2584
2585 if (tristate)
2586 val = mask;
2587 else
2588 val = 0;
2589
78b3fb46 2590 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2591}
2592
d09f3ecf
MB		 2593static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2594{
2595 struct snd_soc_codec *codec = dai->codec;
2596
2597 /* Disable the pulls on the AIF if we're using it to save power. */
2598 snd_soc_update_bits(codec, WM8994_GPIO_3,
2599 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2600 snd_soc_update_bits(codec, WM8994_GPIO_4,
2601 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2602 snd_soc_update_bits(codec, WM8994_GPIO_5,
2603 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2604
2605 return 0;
2606}
2607
9e6e96a1
MB		 2608#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2609
2610#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2611 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2612
85e7652d 2613static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2614 .set_sysclk = wm8994_set_dai_sysclk,
2615 .set_fmt = wm8994_set_dai_fmt,
2616 .hw_params = wm8994_hw_params,
7d02173c 2617 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2618 .digital_mute = wm8994_aif_mute,
2619 .set_pll = wm8994_set_fll,
778a76e2 2620 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2621};
2622
85e7652d 2623static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2624 .set_sysclk = wm8994_set_dai_sysclk,
2625 .set_fmt = wm8994_set_dai_fmt,
2626 .hw_params = wm8994_hw_params,
7d02173c 2627 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2628 .digital_mute = wm8994_aif_mute,
2629 .set_pll = wm8994_set_fll,
778a76e2
MB		 2630 .set_tristate = wm8994_set_tristate,
2631};
2632
85e7652d 2633static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2634 .hw_params = wm8994_aif3_hw_params,
778a76e2 2635 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2636};
2637
f0fba2ad 2638static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2639 {
f0fba2ad 2640 .name = "wm8994-aif1",
8c7f78b3 2641 .id = 1,
9e6e96a1
MB		 2642 .playback = {
2643 .stream_name = "AIF1 Playback",
b1e43d93 2644 .channels_min = 1,
9e6e96a1
MB		 2645 .channels_max = 2,
2646 .rates = WM8994_RATES,
2647 .formats = WM8994_FORMATS,
2648 },
2649 .capture = {
2650 .stream_name = "AIF1 Capture",
b1e43d93 2651 .channels_min = 1,
9e6e96a1
MB		 2652 .channels_max = 2,
2653 .rates = WM8994_RATES,
2654 .formats = WM8994_FORMATS,
2655 },
2656 .ops = &wm8994_aif1_dai_ops,
2657 },
2658 {
f0fba2ad 2659 .name = "wm8994-aif2",
8c7f78b3 2660 .id = 2,
9e6e96a1
MB		 2661 .playback = {
2662 .stream_name = "AIF2 Playback",
b1e43d93 2663 .channels_min = 1,
9e6e96a1
MB		 2664 .channels_max = 2,
2665 .rates = WM8994_RATES,
2666 .formats = WM8994_FORMATS,
2667 },
2668 .capture = {
2669 .stream_name = "AIF2 Capture",
b1e43d93 2670 .channels_min = 1,
9e6e96a1
MB		 2671 .channels_max = 2,
2672 .rates = WM8994_RATES,
2673 .formats = WM8994_FORMATS,
2674 },
d09f3ecf 2675 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2676 .ops = &wm8994_aif2_dai_ops,
2677 },
2678 {
f0fba2ad 2679 .name = "wm8994-aif3",
8c7f78b3 2680 .id = 3,
9e6e96a1
MB		 2681 .playback = {
2682 .stream_name = "AIF3 Playback",
b1e43d93 2683 .channels_min = 1,
9e6e96a1
MB		 2684 .channels_max = 2,
2685 .rates = WM8994_RATES,
2686 .formats = WM8994_FORMATS,
2687 },
a8462bde 2688 .capture = {
9e6e96a1 2689 .stream_name = "AIF3 Capture",
b1e43d93 2690 .channels_min = 1,
9e6e96a1
MB		 2691 .channels_max = 2,
2692 .rates = WM8994_RATES,
2693 .formats = WM8994_FORMATS,
2694 },
778a76e2 2695 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2696 }
2697};
9e6e96a1
MB		 2698
2699#ifdef CONFIG_PM
84b315ee 2700static int wm8994_suspend(struct snd_soc_codec *codec)
9e6e96a1 2701{
b2c812e2 2702 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2703 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2704 int i, ret;
2705
ca629928
MB		 2706 switch (control->type) {
2707 case WM8994:
2708 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2709 break;
81204c84 2710 case WM1811:
af6b6fe4
MB		 2711 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2712 WM1811_JACKDET_MODE_MASK, 0);
2713 /* Fall through */
ca629928
MB		 2714 case WM8958:
2715 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2716 WM8958_MICD_ENA, 0);
2717 break;
2718 }
2719
9e6e96a1
MB		 2720 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2721 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2722 sizeof(struct wm8994_fll_config));
f0fba2ad 2723 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2724 if (ret < 0)
2725 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2726 i + 1, ret);
2727 }
2728
2729 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2730
2731 return 0;
2732}
2733
f0fba2ad 2734static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2735{
b2c812e2 2736 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2737 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2738 int i, ret;
c52fd021
DP		 2739 unsigned int val, mask;
2740
2741 if (wm8994->revision < 4) {
2742 /* force a HW read */
d9a7666f
MB		 2743 ret = regmap_read(control->regmap,
2744 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2745
2746 /* modify the cache only */
2747 codec->cache_only = 1;
2748 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2749 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2750 val &= mask;
2751 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2752 mask, val);
2753 codec->cache_only = 0;
2754 }
9e6e96a1
MB		 2755
2756 /* Restore the registers */
ca9aef50
MB		 2757 ret = snd_soc_cache_sync(codec);
2758 if (ret != 0)
2759 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2760
2761 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2762
2763 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2764 if (!wm8994->fll_suspend[i].out)
2765 continue;
2766
f0fba2ad 2767 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2768 wm8994->fll_suspend[i].src,
2769 wm8994->fll_suspend[i].in,
2770 wm8994->fll_suspend[i].out);
2771 if (ret < 0)
2772 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2773 i + 1, ret);
2774 }
2775
ca629928
MB		 2776 switch (control->type) {
2777 case WM8994:
2778 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2779 snd_soc_update_bits(codec, WM8994_MICBIAS,
2780 WM8994_MICD_ENA, WM8994_MICD_ENA);
2781 break;
81204c84 2782 case WM1811:
af6b6fe4
MB		 2783 if (wm8994->jackdet && wm8994->jack_cb) {
2784 /* Restart from idle */
2785 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2786 WM1811_JACKDET_MODE_MASK,
2787 WM1811_JACKDET_MODE_JACK);
2788 break;
2789 }
ca629928
MB		 2790 case WM8958:
2791 if (wm8994->jack_cb)
2792 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2793 WM8958_MICD_ENA, WM8958_MICD_ENA);
2794 break;
2795 }
2796
9e6e96a1
MB		 2797 return 0;
2798}
2799#else
2800#define wm8994_suspend NULL
2801#define wm8994_resume NULL
2802#endif
2803
2804static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2805{
f0fba2ad 2806 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2807 struct wm8994_pdata *pdata = wm8994->pdata;
2808 struct snd_kcontrol_new controls[] = {
2809 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2810 wm8994->retune_mobile_enum,
2811 wm8994_get_retune_mobile_enum,
2812 wm8994_put_retune_mobile_enum),
2813 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2814 wm8994->retune_mobile_enum,
2815 wm8994_get_retune_mobile_enum,
2816 wm8994_put_retune_mobile_enum),
2817 SOC_ENUM_EXT("AIF2 EQ Mode",
2818 wm8994->retune_mobile_enum,
2819 wm8994_get_retune_mobile_enum,
2820 wm8994_put_retune_mobile_enum),
2821 };
2822 int ret, i, j;
2823 const char **t;
2824
2825 /* We need an array of texts for the enum API but the number
2826 * of texts is likely to be less than the number of
2827 * configurations due to the sample rate dependency of the
2828 * configurations. */
2829 wm8994->num_retune_mobile_texts = 0;
2830 wm8994->retune_mobile_texts = NULL;
2831 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2832 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2833 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2834 wm8994->retune_mobile_texts[j]) == 0)
2835 break;
2836 }
2837
2838 if (j != wm8994->num_retune_mobile_texts)
2839 continue;
2840
2841 /* Expand the array... */
2842 t = krealloc(wm8994->retune_mobile_texts,
2843 sizeof(char *) *
2844 (wm8994->num_retune_mobile_texts + 1),
2845 GFP_KERNEL);
2846 if (t == NULL)
2847 continue;
2848
2849 /* ...store the new entry... */
2850 t[wm8994->num_retune_mobile_texts] =
2851 pdata->retune_mobile_cfgs[i].name;
2852
2853 /* ...and remember the new version. */
2854 wm8994->num_retune_mobile_texts++;
2855 wm8994->retune_mobile_texts = t;
2856 }
2857
2858 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2859 wm8994->num_retune_mobile_texts);
2860
2861 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2862 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2863
f0fba2ad 2864 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2865 ARRAY_SIZE(controls));
2866 if (ret != 0)
f0fba2ad 2867 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2868 "Failed to add ReTune Mobile controls: %d\n", ret);
2869}
2870
2871static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2872{
f0fba2ad 2873 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2874 struct wm8994_pdata *pdata = wm8994->pdata;
2875 int ret, i;
2876
2877 if (!pdata)
2878 return;
2879
2880 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2881 pdata->lineout2_diff,
2882 pdata->lineout1fb,
2883 pdata->lineout2fb,
2884 pdata->jd_scthr,
2885 pdata->jd_thr,
2886 pdata->micbias1_lvl,
2887 pdata->micbias2_lvl);
2888
2889 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2890
2891 if (pdata->num_drc_cfgs) {
2892 struct snd_kcontrol_new controls[] = {
2893 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2894 wm8994_get_drc_enum, wm8994_put_drc_enum),
2895 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2896 wm8994_get_drc_enum, wm8994_put_drc_enum),
2897 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2898 wm8994_get_drc_enum, wm8994_put_drc_enum),
2899 };
2900
2901 /* We need an array of texts for the enum API */
7270cebe
MB		 2902 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2903 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2904 if (!wm8994->drc_texts) {
f0fba2ad 2905 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2906 "Failed to allocate %d DRC config texts\n",
2907 pdata->num_drc_cfgs);
2908 return;
2909 }
2910
2911 for (i = 0; i < pdata->num_drc_cfgs; i++)
2912 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2913
2914 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2915 wm8994->drc_enum.texts = wm8994->drc_texts;
2916
f0fba2ad 2917 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2918 ARRAY_SIZE(controls));
2919 if (ret != 0)
f0fba2ad 2920 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2921 "Failed to add DRC mode controls: %d\n", ret);
2922
2923 for (i = 0; i < WM8994_NUM_DRC; i++)
2924 wm8994_set_drc(codec, i);
2925 }
2926
2927 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2928 pdata->num_retune_mobile_cfgs);
2929
2930 if (pdata->num_retune_mobile_cfgs)
2931 wm8994_handle_retune_mobile_pdata(wm8994);
2932 else
f0fba2ad 2933 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2934 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2935
2936 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2937 if (pdata->micbias[i]) {
2938 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2939 pdata->micbias[i] & 0xffff);
2940 }
2941 }
9e6e96a1
MB		 2942}
2943
88766984
MB		 2944/**
2945 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2946 *
2947 * @codec: WM8994 codec
2948 * @jack: jack to report detection events on
2949 * @micbias: microphone bias to detect on
2950 * @det: value to report for presence detection
2951 * @shrt: value to report for short detection
2952 *
2953 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2954 * being used to bring out signals to the processor then only platform
5ab230a7 2955 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2956 * be configured using snd_soc_jack_add_gpios() instead.
2957 *
2958 * Configuration of detection levels is available via the micbias1_lvl
2959 * and micbias2_lvl platform data members.
2960 */
2961int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2962 int micbias, int det, int shrt)
2963{
b2c812e2 2964 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2965 struct wm8994_micdet *micdet;
2a8a856d 2966 struct wm8994 *control = wm8994->wm8994;
88766984
MB		 2967 int reg;
2968
3a423157
MB		 2969 if (control->type != WM8994)
2970 return -EINVAL;
2971
88766984
MB		 2972 switch (micbias) {
2973 case 1:
2974 micdet = &wm8994->micdet[0];
2975 break;
2976 case 2:
2977 micdet = &wm8994->micdet[1];
2978 break;
2979 default:
2980 return -EINVAL;
2981 }
2982
2983 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2984 micbias, det, shrt);
2985
2986 /* Store the configuration */
2987 micdet->jack = jack;
2988 micdet->det = det;
2989 micdet->shrt = shrt;
2990
2991 /* If either of the jacks is set up then enable detection */
2992 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2993 reg = WM8994_MICD_ENA;
2994 else
2995 reg = 0;
2996
2997 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2998
2999 return 0;
3000}
3001EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3002
3003static irqreturn_t wm8994_mic_irq(int irq, void *data)
3004{
3005 struct wm8994_priv *priv = data;
f0fba2ad 3006 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3007 int reg;
3008 int report;
3009
7116f452 3010#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3011 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3012#endif
2bbb5d66 3013
88766984
MB		 3014 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3015 if (reg < 0) {
3016 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3017 reg);
3018 return IRQ_HANDLED;
3019 }
3020
3021 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3022
3023 report = 0;
3024 if (reg & WM8994_MIC1_DET_STS)
3025 report |= priv->micdet[0].det;
3026 if (reg & WM8994_MIC1_SHRT_STS)
3027 report |= priv->micdet[0].shrt;
3028 snd_soc_jack_report(priv->micdet[0].jack, report,
3029 priv->micdet[0].det | priv->micdet[0].shrt);
3030
3031 report = 0;
3032 if (reg & WM8994_MIC2_DET_STS)
3033 report |= priv->micdet[1].det;
3034 if (reg & WM8994_MIC2_SHRT_STS)
3035 report |= priv->micdet[1].shrt;
3036 snd_soc_jack_report(priv->micdet[1].jack, report,
3037 priv->micdet[1].det | priv->micdet[1].shrt);
3038
3039 return IRQ_HANDLED;
3040}
3041
821edd2f
MB		 3042/* Default microphone detection handler for WM8958 - the user can
3043 * override this if they wish.
3044 */
3045static void wm8958_default_micdet(u16 status, void *data)
3046{
3047 struct snd_soc_codec *codec = data;
3048 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3049 int report;
821edd2f 3050
a1691343
MB		 3051 dev_dbg(codec->dev, "MICDET %x\n", status);
3052
af6b6fe4 3053 /* Either nothing present or just starting detection */
b00adf76 3054 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3055 if (!wm8994->jackdet) {
3056 /* If nothing present then clear our statuses */
3057 dev_dbg(codec->dev, "Detected open circuit\n");
3058 wm8994->jack_mic = false;
3059 wm8994->mic_detecting = true;
b00adf76 3060
af6b6fe4 3061 wm8958_micd_set_rate(codec);
b00adf76 3062
af6b6fe4
MB		 3063 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3064 wm8994->btn_mask |
3065 SND_JACK_HEADSET);
3066 }
b00adf76
MB		 3067 return;
3068 }
821edd2f 3069
b00adf76
MB		 3070 /* If the measurement is showing a high impedence we've got a
3071 * microphone.
3072 */
157a75e6 3073 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3074 dev_dbg(codec->dev, "Detected microphone\n");
3075
157a75e6 3076 wm8994->mic_detecting = false;
b00adf76
MB		 3077 wm8994->jack_mic = true;
3078
3079 wm8958_micd_set_rate(codec);
3080
3081 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3082 SND_JACK_HEADSET);
3083 }
821edd2f 3084
b00adf76 3085
157a75e6 3086 if (wm8994->mic_detecting && status & 0x4) {
b00adf76 3087 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3088 wm8994->mic_detecting = false;
b00adf76
MB		 3089
3090 wm8958_micd_set_rate(codec);
3091
3092 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3093 SND_JACK_HEADSET);
af6b6fe4
MB		 3094
3095 /* If we have jackdet that will detect removal */
3096 if (wm8994->jackdet) {
3097 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3098 WM8958_MICD_ENA, 0);
3099
3100 wm1811_jackdet_set_mode(codec,
3101 WM1811_JACKDET_MODE_JACK);
3102 }
b00adf76
MB		 3103 }
3104
3105 /* Report short circuit as a button */
3106 if (wm8994->jack_mic) {
4585790d 3107 report = 0;
b00adf76 3108 if (status & 0x4)
4585790d
MB		 3109 report |= SND_JACK_BTN_0;
3110
3111 if (status & 0x8)
3112 report |= SND_JACK_BTN_1;
3113
3114 if (status & 0x10)
3115 report |= SND_JACK_BTN_2;
3116
3117 if (status & 0x20)
3118 report |= SND_JACK_BTN_3;
3119
3120 if (status & 0x40)
3121 report |= SND_JACK_BTN_4;
3122
3123 if (status & 0x80)
3124 report |= SND_JACK_BTN_5;
3125
3126 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3127 wm8994->btn_mask);
b00adf76 3128 }
821edd2f
MB		 3129}
3130
af6b6fe4
MB		 3131static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3132{
3133 struct wm8994_priv *wm8994 = data;
3134 struct snd_soc_codec *codec = wm8994->codec;
3135 int reg;
3136
3137 mutex_lock(&wm8994->accdet_lock);
3138
3139 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3140 if (reg < 0) {
3141 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3142 mutex_unlock(&wm8994->accdet_lock);
3143 return IRQ_NONE;
3144 }
3145
3146 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3147
3148 if (reg & WM1811_JACKDET_LVL) {
3149 dev_dbg(codec->dev, "Jack detected\n");
3150
3151 snd_soc_jack_report(wm8994->micdet[0].jack,
3152 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3153
3154 /*
3155 * Start off measument of microphone impedence to find
3156 * out what's actually there.
3157 */
3158 wm8994->mic_detecting = true;
3159 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3160 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3161 WM8958_MICD_ENA, WM8958_MICD_ENA);
3162 } else {
3163 dev_dbg(codec->dev, "Jack not detected\n");
3164
3165 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3166 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3167 wm8994->btn_mask);
3168
3169 wm8994->mic_detecting = false;
3170 wm8994->jack_mic = false;
3171 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3172 WM8958_MICD_ENA, 0);
3173 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3174 }
3175
3176 mutex_unlock(&wm8994->accdet_lock);
3177
3178 return IRQ_HANDLED;
3179}
3180
821edd2f
MB		 3181/**
3182 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3183 *
3184 * @codec: WM8958 codec
3185 * @jack: jack to report detection events on
3186 *
3187 * Enable microphone detection functionality for the WM8958. By
3188 * default simple detection which supports the detection of up to 6
3189 * buttons plus video and microphone functionality is supported.
3190 *
3191 * The WM8958 has an advanced jack detection facility which is able to
3192 * support complex accessory detection, especially when used in
3193 * conjunction with external circuitry. In order to provide maximum
3194 * flexiblity a callback is provided which allows a completely custom
3195 * detection algorithm.
3196 */
3197int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3198 wm8958_micdet_cb cb, void *cb_data)
3199{
3200 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3201 struct wm8994 *control = wm8994->wm8994;
4585790d 3202 u16 micd_lvl_sel;
821edd2f 3203
81204c84
MB		 3204 switch (control->type) {
3205 case WM1811:
3206 case WM8958:
3207 break;
3208 default:
821edd2f 3209 return -EINVAL;
81204c84 3210 }
821edd2f
MB		 3211
3212 if (jack) {
3213 if (!cb) {
3214 dev_dbg(codec->dev, "Using default micdet callback\n");
3215 cb = wm8958_default_micdet;
3216 cb_data = codec;
3217 }
3218
4cdf5e49
MB		 3219 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3220
821edd2f
MB		 3221 wm8994->micdet[0].jack = jack;
3222 wm8994->jack_cb = cb;
3223 wm8994->jack_cb_data = cb_data;
3224
157a75e6 3225 wm8994->mic_detecting = true;
b00adf76
MB		 3226 wm8994->jack_mic = false;
3227
3228 wm8958_micd_set_rate(codec);
3229
4585790d
MB		 3230 /* Detect microphones and short circuits by default */
3231 if (wm8994->pdata->micd_lvl_sel)
3232 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3233 else
3234 micd_lvl_sel = 0x41;
3235
3236 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3237 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3238 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3239
b00adf76 3240 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3241 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3242
af6b6fe4
MB		 3243 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3244
3245 /*
3246 * If we can use jack detection start off with that,
3247 * otherwise jump straight to microphone detection.
3248 */
3249 if (wm8994->jackdet) {
3250 snd_soc_update_bits(codec, WM8994_LDO_1,
3251 WM8994_LDO1_DISCH, 0);
3252 wm1811_jackdet_set_mode(codec,
3253 WM1811_JACKDET_MODE_JACK);
3254 } else {
3255 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3256 WM8958_MICD_ENA, WM8958_MICD_ENA);
3257 }
3258
821edd2f
MB		 3259 } else {
3260 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3261 WM8958_MICD_ENA, 0);
4cdf5e49 3262 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
821edd2f
MB		 3263 }
3264
3265 return 0;
3266}
3267EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3268
3269static irqreturn_t wm8958_mic_irq(int irq, void *data)
3270{
3271 struct wm8994_priv *wm8994 = data;
3272 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3273 int reg, count;
821edd2f 3274
af6b6fe4
MB		 3275 mutex_lock(&wm8994->accdet_lock);
3276
3277 /*
3278 * Jack detection may have detected a removal simulataneously
3279 * with an update of the MICDET status; if so it will have
3280 * stopped detection and we can ignore this interrupt.
3281 */
3282 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3283 mutex_unlock(&wm8994->accdet_lock);
3284 return IRQ_HANDLED;
3285 }
3286
19940b3d
MB		 3287 /* We may occasionally read a detection without an impedence
3288 * range being provided - if that happens loop again.
3289 */
3290 count = 10;
3291 do {
3292 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3293 if (reg < 0) {
af6b6fe4 3294 mutex_unlock(&wm8994->accdet_lock);
19940b3d
MB		 3295 dev_err(codec->dev,
3296 "Failed to read mic detect status: %d\n",
3297 reg);
3298 return IRQ_NONE;
3299 }
821edd2f 3300
19940b3d
MB		 3301 if (!(reg & WM8958_MICD_VALID)) {
3302 dev_dbg(codec->dev, "Mic detect data not valid\n");
3303 goto out;
3304 }
3305
3306 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3307 break;
3308
3309 msleep(1);
3310 } while (count--);
3311
3312 if (count == 0)
3313 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3314
7116f452 3315#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3316 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3317#endif
2bbb5d66 3318
821edd2f
MB		 3319 if (wm8994->jack_cb)
3320 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3321 else
3322 dev_warn(codec->dev, "Accessory detection with no callback\n");
3323
3324out:
af6b6fe4
MB		 3325 mutex_unlock(&wm8994->accdet_lock);
3326
821edd2f
MB		 3327 return IRQ_HANDLED;
3328}
3329
3b1af3f8
MB		 3330static irqreturn_t wm8994_fifo_error(int irq, void *data)
3331{
3332 struct snd_soc_codec *codec = data;
3333
3334 dev_err(codec->dev, "FIFO error\n");
3335
3336 return IRQ_HANDLED;
3337}
3338
f0b182b0
MB		 3339static irqreturn_t wm8994_temp_warn(int irq, void *data)
3340{
3341 struct snd_soc_codec *codec = data;
3342
3343 dev_err(codec->dev, "Thermal warning\n");
3344
3345 return IRQ_HANDLED;
3346}
3347
3348static irqreturn_t wm8994_temp_shut(int irq, void *data)
3349{
3350 struct snd_soc_codec *codec = data;
3351
3352 dev_crit(codec->dev, "Thermal shutdown\n");
3353
3354 return IRQ_HANDLED;
3355}
3356
f0fba2ad 3357static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3358{
d9a7666f 3359 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
9e6e96a1 3360 struct wm8994_priv *wm8994;
ce6120cc 3361 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3362 unsigned int reg;
ec62dbd7 3363 int ret, i;
9e6e96a1 3364
d9a7666f 3365 codec->control_data = control->regmap;
9e6e96a1 3366
7270cebe
MB		 3367 wm8994 = devm_kzalloc(codec->dev, sizeof(struct wm8994_priv),
3368 GFP_KERNEL);
f0fba2ad 3369 if (wm8994 == NULL)
9e6e96a1 3370 return -ENOMEM;
b2c812e2 3371 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 3372
d9a7666f 3373 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d
MB		 3374
3375 wm8994->wm8994 = dev_get_drvdata(codec->dev->parent);
f0fba2ad
LG		 3376 wm8994->pdata = dev_get_platdata(codec->dev->parent);
3377 wm8994->codec = codec;
9e6e96a1 3378
af6b6fe4
MB		 3379 mutex_init(&wm8994->accdet_lock);
3380
c7ebf932
MB		 3381 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3382 init_completion(&wm8994->fll_locked[i]);
3383
9b7c525d
MB		 3384 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3385 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3386 else if (wm8994->pdata && wm8994->pdata->irq_base)
3387 wm8994->micdet_irq = wm8994->pdata->irq_base +
3388 WM8994_IRQ_MIC1_DET;
3389
39fb51a1
MB		 3390 pm_runtime_enable(codec->dev);
3391 pm_runtime_resume(codec->dev);
3392
9e6e96a1 3393 /* Set revision-specific configuration */
b6b05691 3394 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3395 switch (control->type) {
3396 case WM8994:
3397 switch (wm8994->revision) {
3398 case 2:
3399 case 3:
4537c4e7
MB		 3400 wm8994->hubs.dcs_codes_l = -5;
3401 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3402 wm8994->hubs.hp_startup_mode = 1;
3403 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3404 wm8994->hubs.series_startup = 1;
3a423157
MB		 3405 break;
3406 default:
79ef0abc 3407 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3408 break;
3409 }
280ec8b7 3410 break;
3a423157
MB		 3411
3412 case WM8958:
8437f700 3413 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 3414 break;
3a423157 3415
81204c84
MB		 3416 case WM1811:
3417 wm8994->hubs.dcs_readback_mode = 2;
3418 wm8994->hubs.no_series_update = 1;
3419
3420 switch (wm8994->revision) {
3421 case 0:
3422 case 1:
fc8e6e86
MB		 3423 case 2:
3424 case 3:
6473a148
MB		 3425 wm8994->hubs.dcs_codes_l = -9;
3426 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3427 break;
3428 default:
3429 break;
3430 }
3431
3432 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3433 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3434 break;
3435
9e6e96a1
MB		 3436 default:
3437 break;
3438 }
9e6e96a1 3439
2a8a856d 3440 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3441 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3442 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3443 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3444 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3445 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3446
2a8a856d 3447 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3448 wm_hubs_dcs_done, "DC servo done",
3449 &wm8994->hubs);
3450 if (ret == 0)
3451 wm8994->hubs.dcs_done_irq = true;
3452
3a423157
MB		 3453 switch (control->type) {
3454 case WM8994:
9b7c525d
MB		 3455 if (wm8994->micdet_irq) {
3456 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3457 wm8994_mic_irq,
3458 IRQF_TRIGGER_RISING,
3459 "Mic1 detect",
3460 wm8994);
3461 if (ret != 0)
3462 dev_warn(codec->dev,
3463 "Failed to request Mic1 detect IRQ: %d\n",
3464 ret);
3465 }
3a423157 3466
2a8a856d 3467 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3468 WM8994_IRQ_MIC1_SHRT,
3469 wm8994_mic_irq, "Mic 1 short",
3470 wm8994);
3471 if (ret != 0)
3472 dev_warn(codec->dev,
3473 "Failed to request Mic1 short IRQ: %d\n",
3474 ret);
3475
2a8a856d 3476 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3477 WM8994_IRQ_MIC2_DET,
3478 wm8994_mic_irq, "Mic 2 detect",
3479 wm8994);
3480 if (ret != 0)
3481 dev_warn(codec->dev,
3482 "Failed to request Mic2 detect IRQ: %d\n",
3483 ret);
3484
2a8a856d 3485 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3486 WM8994_IRQ_MIC2_SHRT,
3487 wm8994_mic_irq, "Mic 2 short",
3488 wm8994);
3489 if (ret != 0)
3490 dev_warn(codec->dev,
3491 "Failed to request Mic2 short IRQ: %d\n",
3492 ret);
3493 break;
821edd2f
MB		 3494
3495 case WM8958:
81204c84 3496 case WM1811:
9b7c525d
MB		 3497 if (wm8994->micdet_irq) {
3498 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3499 wm8958_mic_irq,
3500 IRQF_TRIGGER_RISING,
3501 "Mic detect",
3502 wm8994);
3503 if (ret != 0)
3504 dev_warn(codec->dev,
3505 "Failed to request Mic detect IRQ: %d\n",
3506 ret);
3507 }
3a423157 3508 }
88766984 3509
af6b6fe4
MB		 3510 switch (control->type) {
3511 case WM1811:
3512 if (wm8994->revision > 1) {
3513 ret = wm8994_request_irq(wm8994->wm8994,
3514 WM8994_IRQ_GPIO(6),
3515 wm1811_jackdet_irq, "JACKDET",
3516 wm8994);
3517 if (ret == 0)
3518 wm8994->jackdet = true;
3519 }
3520 break;
3521 default:
3522 break;
3523 }
3524
c7ebf932
MB		 3525 wm8994->fll_locked_irq = true;
3526 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3527 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3528 WM8994_IRQ_FLL1_LOCK + i,
3529 wm8994_fll_locked_irq, "FLL lock",
3530 &wm8994->fll_locked[i]);
3531 if (ret != 0)
3532 wm8994->fll_locked_irq = false;
3533 }
3534
9e6e96a1
MB		 3535 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3536 * configured on init - if a system wants to do this dynamically
3537 * at runtime we can deal with that then.
3538 */
d9a7666f 3539 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3540 if (ret < 0) {
3541 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3542 goto err_irq;
9e6e96a1 3543 }
d9a7666f 3544 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3545 wm8994->lrclk_shared[0] = 1;
3546 wm8994_dai[0].symmetric_rates = 1;
3547 } else {
3548 wm8994->lrclk_shared[0] = 0;
3549 }
3550
d9a7666f 3551 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3552 if (ret < 0) {
3553 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3554 goto err_irq;
9e6e96a1 3555 }
d9a7666f 3556 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3557 wm8994->lrclk_shared[1] = 1;
3558 wm8994_dai[1].symmetric_rates = 1;
3559 } else {
3560 wm8994->lrclk_shared[1] = 0;
3561 }
3562
9e6e96a1
MB		 3563 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3564
9e6e96a1 3565 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3566 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3567 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3568 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3569 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3570 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3571 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3572 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3573 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3574 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3575 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3576 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3577 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3578 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3579 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3580 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3581 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3582 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3583 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3584 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3585 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3586 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3587 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3588 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3589 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3590 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3591 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3592 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3593 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3594 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3595 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3596 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3597 WM8994_DAC2_VU, WM8994_DAC2_VU);
3598
3599 /* Set the low bit of the 3D stereo depth so TLV matches */
3600 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3601 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3602 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3603 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3604 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3605 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3606 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3607 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3608 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3609
5b739670
MB		 3610 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3611 * use this; it only affects behaviour on idle TDM clock
3612 * cycles. */
3613 switch (control->type) {
3614 case WM8994:
3615 case WM8958:
3616 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3617 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3618 break;
3619 default:
3620 break;
3621 }
d1ce6b20 3622
500fa30e
MB		 3623 /* Put MICBIAS into bypass mode by default on newer devices */
3624 switch (control->type) {
3625 case WM8958:
3626 case WM1811:
3627 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3628 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3629 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3630 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3631 break;
3632 default:
3633 break;
3634 }
3635
9e6e96a1
MB		 3636 wm8994_update_class_w(codec);
3637
f0fba2ad 3638 wm8994_handle_pdata(wm8994);
9e6e96a1 3639
f0fba2ad
LG		 3640 wm_hubs_add_analogue_controls(codec);
3641 snd_soc_add_controls(codec, wm8994_snd_controls,
3642 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3643 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3644 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3645
3646 switch (control->type) {
3647 case WM8994:
3648 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3649 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3650 if (wm8994->revision < 4) {
173efa09
DP		 3651 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3652 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3653 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3654 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3655 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3656 ARRAY_SIZE(wm8994_dac_revd_widgets));
3657 } else {
173efa09
DP		 3658 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3659 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3660 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3661 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3662 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3663 ARRAY_SIZE(wm8994_dac_widgets));
3664 }
c4431df0
MB		 3665 break;
3666 case WM8958:
3667 snd_soc_add_controls(codec, wm8958_snd_controls,
3668 ARRAY_SIZE(wm8958_snd_controls));
3669 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3670 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3671 if (wm8994->revision < 1) {
3672 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3673 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3674 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3675 ARRAY_SIZE(wm8994_adc_revd_widgets));
3676 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3677 ARRAY_SIZE(wm8994_dac_revd_widgets));
3678 } else {
3679 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3680 ARRAY_SIZE(wm8994_lateclk_widgets));
3681 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3682 ARRAY_SIZE(wm8994_adc_widgets));
3683 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3684 ARRAY_SIZE(wm8994_dac_widgets));
3685 }
c4431df0 3686 break;
81204c84
MB		 3687
3688 case WM1811:
3689 snd_soc_add_controls(codec, wm8958_snd_controls,
3690 ARRAY_SIZE(wm8958_snd_controls));
3691 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3692 ARRAY_SIZE(wm8958_dapm_widgets));
3693 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3694 ARRAY_SIZE(wm8994_lateclk_widgets));
3695 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3696 ARRAY_SIZE(wm8994_adc_widgets));
3697 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3698 ARRAY_SIZE(wm8994_dac_widgets));
3699 break;
c4431df0
MB		 3700 }
3701
3702
f0fba2ad 3703 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3704 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3705
c4431df0
MB		 3706 switch (control->type) {
3707 case WM8994:
3708 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3709 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3710
173efa09 3711 if (wm8994->revision < 4) {
6ed8f148
MB		 3712 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3713 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3714 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3715 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3716 } else {
3717 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3718 ARRAY_SIZE(wm8994_lateclk_intercon));
3719 }
c4431df0
MB		 3720 break;
3721 case WM8958:
780e2806
MB		 3722 if (wm8994->revision < 1) {
3723 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3724 ARRAY_SIZE(wm8994_revd_intercon));
3725 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3726 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3727 } else {
3728 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3729 ARRAY_SIZE(wm8994_lateclk_intercon));
3730 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3731 ARRAY_SIZE(wm8958_intercon));
3732 }
f701a2e5
MB		 3733
3734 wm8958_dsp2_init(codec);
c4431df0 3735 break;
81204c84
MB		 3736 case WM1811:
3737 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3738 ARRAY_SIZE(wm8994_lateclk_intercon));
3739 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3740 ARRAY_SIZE(wm8958_intercon));
3741 break;
c4431df0
MB		 3742 }
3743
9e6e96a1
MB		 3744 return 0;
3745
88766984 3746err_irq:
af6b6fe4
MB		 3747 if (wm8994->jackdet)
3748 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3749 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3750 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3751 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3752 if (wm8994->micdet_irq)
3753 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3754 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3755 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3756 &wm8994->fll_locked[i]);
2a8a856d 3757 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3758 &wm8994->hubs);
2a8a856d
MB		 3759 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3760 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3761 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3762
9e6e96a1
MB		 3763 return ret;
3764}
3765
f0fba2ad 3766static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3767{
f0fba2ad 3768 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3769 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3770 int i;
9e6e96a1
MB		 3771
3772 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3773
39fb51a1
MB		 3774 pm_runtime_disable(codec->dev);
3775
c7ebf932 3776 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3777 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3778 &wm8994->fll_locked[i]);
3779
2a8a856d 3780 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3781 &wm8994->hubs);
2a8a856d
MB		 3782 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3783 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3784 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3785
af6b6fe4
MB		 3786 if (wm8994->jackdet)
3787 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3788
3a423157
MB		 3789 switch (control->type) {
3790 case WM8994:
9b7c525d
MB		 3791 if (wm8994->micdet_irq)
3792 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3793 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3794 wm8994);
2a8a856d 3795 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3796 wm8994);
2a8a856d 3797 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3798 wm8994);
3799 break;
821edd2f 3800
81204c84 3801 case WM1811:
821edd2f 3802 case WM8958:
9b7c525d
MB		 3803 if (wm8994->micdet_irq)
3804 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3805 break;
3a423157 3806 }
fbbf5920
MB		 3807 if (wm8994->mbc)
3808 release_firmware(wm8994->mbc);
09e10d7f
MB		 3809 if (wm8994->mbc_vss)
3810 release_firmware(wm8994->mbc_vss);
31215871
MB		 3811 if (wm8994->enh_eq)
3812 release_firmware(wm8994->enh_eq);
24fb2b11 3813 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3814
3815 return 0;
3816}
3817
1b39bf34
MB		 3818static int wm8994_soc_volatile(struct snd_soc_codec *codec,
3819 unsigned int reg)
3820{
3821 return true;
3822}
3823
f0fba2ad
LG		 3824static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3825 .probe = wm8994_codec_probe,
3826 .remove = wm8994_codec_remove,
3827 .suspend = wm8994_suspend,
3828 .resume = wm8994_resume,
f0fba2ad 3829 .set_bias_level = wm8994_set_bias_level,
1b39bf34
MB		 3830 .reg_cache_size = WM8994_MAX_REGISTER,
3831 .volatile_register = wm8994_soc_volatile,
f0fba2ad
LG		 3832};
3833
3834static int __devinit wm8994_probe(struct platform_device *pdev)
3835{
3836 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3837 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3838}
3839
3840static int __devexit wm8994_remove(struct platform_device *pdev)
3841{
3842 snd_soc_unregister_codec(&pdev->dev);
3843 return 0;
3844}
3845
9e6e96a1
MB		 3846static struct platform_driver wm8994_codec_driver = {
3847 .driver = {
3848 .name = "wm8994-codec",
3849 .owner = THIS_MODULE,
3850 },
f0fba2ad
LG		 3851 .probe = wm8994_probe,
3852 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3853};
3854
5bbcc3c0 3855module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 3856
3857MODULE_DESCRIPTION("ASoC WM8994 driver");
3858MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3859MODULE_LICENSE("GPL");
3860MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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