Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney...
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
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1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
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5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
d1a0a299 19#include <linux/gcd.h>
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20#include <linux/i2c.h>
21#include <linux/platform_device.h>
39fb51a1 22#include <linux/pm_runtime.h>
9e6e96a1 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
9e6e96a1 25#include <sound/core.h>
821edd2f 26#include <sound/jack.h>
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27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
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30#include <sound/initval.h>
31#include <sound/tlv.h>
2bbb5d66 32#include <trace/events/asoc.h>
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33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
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42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
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47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
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50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
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83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
af6b6fe4 95static const struct wm8958_micd_rate micdet_rates[] = {
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96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
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98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
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100};
101
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102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
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105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
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107};
108
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109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 112 struct wm8994 *control = wm8994->wm8994;
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113 int best, i, sysclk, val;
114 bool idle;
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115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
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118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
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126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
cd1707a9 129 } else if (wm8994->jackdet) {
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130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
b00adf76 137 best = 0;
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138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
b00adf76 140 continue;
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141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
b00adf76 143 best = i;
af6b6fe4 144 else if (rates[best].idle != idle)
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145 best = i;
146 }
147
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148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 150
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151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
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155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
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160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
b2c812e2 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
5e5e2bef 203
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204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
b2c812e2 215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 216 int change, new;
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217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
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229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
9e6e96a1 231 return 0;
b00adf76 232 }
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233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
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239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
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241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 243
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244 wm8958_micd_set_rate(codec);
245
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246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262}
263
264static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266};
267
268static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270
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271static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273};
274
275static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277
278static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280
281static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283
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284static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 289static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 290static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
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291
292#define WM8994_DRC_SWITCH(xname, reg, shift) \
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293 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294 snd_soc_get_volsw, wm8994_put_drc_sw)
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295
296static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298{
299 struct soc_mixer_control *mc =
300 (struct soc_mixer_control *)kcontrol->private_value;
301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
302 int mask, ret;
303
304 /* Can't enable both ADC and DAC paths simultaneously */
305 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307 WM8994_AIF1ADC1R_DRC_ENA_MASK;
308 else
309 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310
311 ret = snd_soc_read(codec, mc->reg);
312 if (ret < 0)
313 return ret;
314 if (ret & mask)
315 return -EINVAL;
316
317 return snd_soc_put_volsw(kcontrol, ucontrol);
318}
319
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320static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321{
b2c812e2 322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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323 struct wm8994 *control = wm8994->wm8994;
324 struct wm8994_pdata *pdata = &control->pdata;
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325 int base = wm8994_drc_base[drc];
326 int cfg = wm8994->drc_cfg[drc];
327 int save, i;
328
329 /* Save any enables; the configuration should clear them. */
330 save = snd_soc_read(codec, base);
331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332 WM8994_AIF1ADC1R_DRC_ENA;
333
334 for (i = 0; i < WM8994_DRC_REGS; i++)
335 snd_soc_update_bits(codec, base + i, 0xffff,
336 pdata->drc_cfgs[cfg].regs[i]);
337
338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339 WM8994_AIF1ADC1L_DRC_ENA |
340 WM8994_AIF1ADC1R_DRC_ENA, save);
341}
342
343/* Icky as hell but saves code duplication */
344static int wm8994_get_drc(const char *name)
345{
346 if (strcmp(name, "AIF1DRC1 Mode") == 0)
347 return 0;
348 if (strcmp(name, "AIF1DRC2 Mode") == 0)
349 return 1;
350 if (strcmp(name, "AIF2DRC Mode") == 0)
351 return 2;
352 return -EINVAL;
353}
354
355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357{
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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360 struct wm8994 *control = wm8994->wm8994;
361 struct wm8994_pdata *pdata = &control->pdata;
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362 int drc = wm8994_get_drc(kcontrol->id.name);
363 int value = ucontrol->value.integer.value[0];
364
365 if (drc < 0)
366 return drc;
367
368 if (value >= pdata->num_drc_cfgs)
369 return -EINVAL;
370
371 wm8994->drc_cfg[drc] = value;
372
373 wm8994_set_drc(codec, drc);
374
375 return 0;
376}
377
378static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380{
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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383 int drc = wm8994_get_drc(kcontrol->id.name);
384
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385 if (drc < 0)
386 return drc;
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387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
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397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 438 * current configuration.
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439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448}
449
450/* Icky as hell but saves code duplication */
451static int wm8994_get_retune_mobile_block(const char *name)
452{
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460}
461
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
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469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
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492 if (block < 0)
493 return block;
494
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495 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496
497 return 0;
498}
499
96b101ef 500static const char *aif_chan_src_text[] = {
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501 "Left", "Right"
502};
503
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504static const struct soc_enum aif1adcl_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
506
507static const struct soc_enum aif1adcr_src =
508 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
509
510static const struct soc_enum aif2adcl_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
512
513static const struct soc_enum aif2adcr_src =
514 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
515
f554885f 516static const struct soc_enum aif1dacl_src =
96b101ef 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
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518
519static const struct soc_enum aif1dacr_src =
96b101ef 520 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
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521
522static const struct soc_enum aif2dacl_src =
96b101ef 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
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524
525static const struct soc_enum aif2dacr_src =
96b101ef 526 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 527
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528static const char *osr_text[] = {
529 "Low Power", "High Performance",
530};
531
532static const struct soc_enum dac_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
534
535static const struct soc_enum adc_osr =
536 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
537
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538static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540 WM8994_AIF1_ADC1_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543 WM8994_AIF1_ADC2_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546 WM8994_AIF2_ADC_RIGHT_VOLUME,
547 1, 119, 0, digital_tlv),
548
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549SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
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551SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 553
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554SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555SOC_ENUM("AIF1DACR Source", aif1dacr_src),
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556SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 558
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559SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565
566SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568
569SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572
573WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576
577WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580
581WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584
585SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590 5, 12, 0, st_tlv),
591SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592 0, 12, 0, st_tlv),
593SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595
146fd574
UK
596SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601
602SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604
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605SOC_ENUM("ADC OSR", adc_osr),
606SOC_ENUM("DAC OSR", dac_osr),
607
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608SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612
613SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617
618SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619 6, 1, 1, wm_hubs_spkmix_tlv),
620SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621 2, 1, 1, wm_hubs_spkmix_tlv),
622
623SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624 6, 1, 1, wm_hubs_spkmix_tlv),
625SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626 2, 1, 1, wm_hubs_spkmix_tlv),
627
628SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
458350b3 630SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
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631 8, 1, 0),
632SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633 10, 15, 0, wm8994_3d_tlv),
634SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635 8, 1, 0),
458350b3 636SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 637 10, 15, 0, wm8994_3d_tlv),
458350b3 638SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
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639 8, 1, 0),
640};
641
642static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648 eq_tlv),
649SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652 eq_tlv),
653
654SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659 eq_tlv),
660SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661 eq_tlv),
662SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663 eq_tlv),
664
665SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666 eq_tlv),
667SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668 eq_tlv),
669SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670 eq_tlv),
671SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672 eq_tlv),
673SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674 eq_tlv),
675};
676
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677static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680 WM8994_AIF1ADC1R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683 WM8994_AIF1ADC2R_DRC_ENA),
684SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686 WM8994_AIF2ADCR_DRC_ENA),
687};
688
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689static const char *wm8958_ng_text[] = {
690 "30ms", "125ms", "250ms", "500ms",
691};
692
693static const struct soc_enum wm8958_aif1dac1_ng_hold =
694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
695 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
696
697static const struct soc_enum wm8958_aif1dac2_ng_hold =
698 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
699 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
700
701static const struct soc_enum wm8958_aif2dac_ng_hold =
702 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
703 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
704
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705static const struct snd_kcontrol_new wm8958_snd_controls[] = {
706SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
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707
708SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
709 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
710SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
711SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
712 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
713 7, 1, ng_tlv),
714
715SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
716 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
717SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
718SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
719 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
720 7, 1, ng_tlv),
721
722SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
723 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
724SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
725SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
726 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
727 7, 1, ng_tlv),
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728};
729
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730static const struct snd_kcontrol_new wm1811_snd_controls[] = {
731SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
732 mixin_boost_tlv),
733SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
734 mixin_boost_tlv),
735};
736
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737/* We run all mode setting through a function to enforce audio mode */
738static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
739{
740 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
741
78b76dbe 742 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
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743 return;
744
af6b6fe4
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745 if (wm8994->active_refcount)
746 mode = WM1811_JACKDET_MODE_AUDIO;
747
4752a887 748 if (mode == wm8994->jackdet_mode)
1defde2a
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749 return;
750
4752a887 751 wm8994->jackdet_mode = mode;
1defde2a 752
4752a887
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753 /* Always use audio mode to detect while the system is active */
754 if (mode != WM1811_JACKDET_MODE_NONE)
755 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 756
4752a887
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757 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
758 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
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759}
760
761static void active_reference(struct snd_soc_codec *codec)
762{
763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
764
765 mutex_lock(&wm8994->accdet_lock);
766
767 wm8994->active_refcount++;
768
769 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
770 wm8994->active_refcount);
771
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772 /* If we're using jack detection go into audio mode */
773 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
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774
775 mutex_unlock(&wm8994->accdet_lock);
776}
777
778static void active_dereference(struct snd_soc_codec *codec)
779{
780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
781 u16 mode;
782
783 mutex_lock(&wm8994->accdet_lock);
784
785 wm8994->active_refcount--;
786
787 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
788 wm8994->active_refcount);
789
790 if (wm8994->active_refcount == 0) {
791 /* Go into appropriate detection only mode */
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792 if (wm8994->jack_mic || wm8994->mic_detecting)
793 mode = WM1811_JACKDET_MODE_MIC;
794 else
795 mode = WM1811_JACKDET_MODE_JACK;
796
797 wm1811_jackdet_set_mode(codec, mode);
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798 }
799
800 mutex_unlock(&wm8994->accdet_lock);
801}
802
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803static int clk_sys_event(struct snd_soc_dapm_widget *w,
804 struct snd_kcontrol *kcontrol, int event)
805{
806 struct snd_soc_codec *codec = w->codec;
99af79df 807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
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808
809 switch (event) {
810 case SND_SOC_DAPM_PRE_PMU:
811 return configure_clock(codec);
812
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813 case SND_SOC_DAPM_POST_PMU:
814 /*
815 * JACKDET won't run until we start the clock and it
816 * only reports deltas, make sure we notify the state
817 * up the stack on startup. Use a *very* generous
818 * timeout for paranoia, there's no urgency and we
819 * don't want false reports.
820 */
821 if (wm8994->jackdet && !wm8994->clk_has_run) {
68defe58
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822 queue_delayed_work(system_power_efficient_wq,
823 &wm8994->jackdet_bootstrap,
824 msecs_to_jiffies(1000));
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825 wm8994->clk_has_run = true;
826 }
827 break;
828
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829 case SND_SOC_DAPM_POST_PMD:
830 configure_clock(codec);
831 break;
832 }
833
834 return 0;
835}
836
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837static void vmid_reference(struct snd_soc_codec *codec)
838{
839 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
840
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841 pm_runtime_get_sync(codec->dev);
842
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843 wm8994->vmid_refcount++;
844
845 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
846 wm8994->vmid_refcount);
847
848 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 849 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 850 WM8994_LINEOUT1_DISCH |
22f8d055 851 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 852
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853 wm_hubs_vmid_ena(codec);
854
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855 switch (wm8994->vmid_mode) {
856 default:
cbd71f30 857 WARN_ON(NULL == "Invalid VMID mode");
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858 case WM8994_VMID_NORMAL:
859 /* Startup bias, VMID ramp & buffer */
860 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
861 WM8994_BIAS_SRC |
862 WM8994_VMID_DISCH |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
865 WM8994_VMID_RAMP_MASK,
866 WM8994_BIAS_SRC |
867 WM8994_STARTUP_BIAS_ENA |
868 WM8994_VMID_BUF_ENA |
a3a1d9d2 869 (0x2 << WM8994_VMID_RAMP_SHIFT));
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870
871 /* Main bias enable, VMID=2x40k */
872 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
873 WM8994_BIAS_ENA |
874 WM8994_VMID_SEL_MASK,
875 WM8994_BIAS_ENA | 0x2);
876
a3a1d9d2 877 msleep(300);
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878
879 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
880 WM8994_VMID_RAMP_MASK |
881 WM8994_BIAS_SRC,
882 0);
883 break;
cc6d5a8c 884
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885 case WM8994_VMID_FORCE:
886 /* Startup bias, slow VMID ramp & buffer */
887 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
888 WM8994_BIAS_SRC |
889 WM8994_VMID_DISCH |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 WM8994_VMID_RAMP_MASK,
893 WM8994_BIAS_SRC |
894 WM8994_STARTUP_BIAS_ENA |
895 WM8994_VMID_BUF_ENA |
896 (0x2 << WM8994_VMID_RAMP_SHIFT));
897
898 /* Main bias enable, VMID=2x40k */
899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
900 WM8994_BIAS_ENA |
901 WM8994_VMID_SEL_MASK,
902 WM8994_BIAS_ENA | 0x2);
903
904 msleep(400);
905
906 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907 WM8994_VMID_RAMP_MASK |
908 WM8994_BIAS_SRC,
909 0);
910 break;
911 }
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912 }
913}
914
915static void vmid_dereference(struct snd_soc_codec *codec)
916{
917 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
918
919 wm8994->vmid_refcount--;
920
921 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
922 wm8994->vmid_refcount);
923
924 if (wm8994->vmid_refcount == 0) {
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925 if (wm8994->hubs.lineout1_se)
926 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
927 WM8994_LINEOUT1N_ENA |
928 WM8994_LINEOUT1P_ENA,
929 WM8994_LINEOUT1N_ENA |
930 WM8994_LINEOUT1P_ENA);
931
932 if (wm8994->hubs.lineout2_se)
933 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
934 WM8994_LINEOUT2N_ENA |
935 WM8994_LINEOUT2P_ENA,
936 WM8994_LINEOUT2N_ENA |
937 WM8994_LINEOUT2P_ENA);
938
939 /* Start discharging VMID */
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940 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
941 WM8994_BIAS_SRC |
22f8d055 942 WM8994_VMID_DISCH,
4b7ed83a 943 WM8994_BIAS_SRC |
22f8d055 944 WM8994_VMID_DISCH);
4b7ed83a 945
f95be9d6
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946 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
947 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 948
f95be9d6 949 msleep(400);
e85b26ce 950
22f8d055 951 /* Active discharge */
4b7ed83a
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952 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
953 WM8994_LINEOUT1_DISCH |
954 WM8994_LINEOUT2_DISCH,
955 WM8994_LINEOUT1_DISCH |
956 WM8994_LINEOUT2_DISCH);
957
22f8d055
MB
958 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
959 WM8994_LINEOUT1N_ENA |
960 WM8994_LINEOUT1P_ENA |
961 WM8994_LINEOUT2N_ENA |
962 WM8994_LINEOUT2P_ENA, 0);
963
4b7ed83a
MB
964 /* Switch off startup biases */
965 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
966 WM8994_BIAS_SRC |
967 WM8994_STARTUP_BIAS_ENA |
968 WM8994_VMID_BUF_ENA |
969 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB
970
971 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 972 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 973 }
db966f8a
MB
974
975 pm_runtime_put(codec->dev);
4b7ed83a
MB
976}
977
978static int vmid_event(struct snd_soc_dapm_widget *w,
979 struct snd_kcontrol *kcontrol, int event)
980{
981 struct snd_soc_codec *codec = w->codec;
982
983 switch (event) {
984 case SND_SOC_DAPM_PRE_PMU:
985 vmid_reference(codec);
986 break;
987
988 case SND_SOC_DAPM_POST_PMD:
989 vmid_dereference(codec);
990 break;
991 }
992
993 return 0;
994}
995
c340304d 996static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 997{
9e6e96a1
MB
998 int source = 0; /* GCC flow analysis can't track enable */
999 int reg, reg_r;
1000
c340304d 1001 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB
1002 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1003 switch (reg) {
1004 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1005 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB
1006 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1009 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB
1010 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1013 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB
1014 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1015 break;
1016 default:
ee839a21 1017 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1018 return false;
9e6e96a1
MB
1019 }
1020
1021 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1022 if (reg_r != reg) {
ee839a21 1023 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1024 return false;
9e6e96a1
MB
1025 }
1026
c340304d
MB
1027 /* Set the source up */
1028 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1029 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1030
c340304d 1031 return true;
9e6e96a1
MB
1032}
1033
1a38336b
MB
1034static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1035 struct snd_kcontrol *kcontrol, int event)
173efa09
DP
1036{
1037 struct snd_soc_codec *codec = w->codec;
79748cdb 1038 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d3134e21 1039 struct wm8994 *control = wm8994->wm8994;
1a38336b 1040 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1041 int i;
1a38336b
MB
1042 int dac;
1043 int adc;
1044 int val;
1045
1046 switch (control->type) {
1047 case WM8994:
1048 case WM8958:
1049 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1050 break;
1051 default:
1052 break;
1053 }
173efa09
DP
1054
1055 switch (event) {
1056 case SND_SOC_DAPM_PRE_PMU:
79748cdb
MB
1057 /* Don't enable timeslot 2 if not in use */
1058 if (wm8994->channels[0] <= 2)
1059 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1060
1a38336b
MB
1061 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1062 if ((val & WM8994_AIF1ADCL_SRC) &&
1063 (val & WM8994_AIF1ADCR_SRC))
1064 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1065 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1066 !(val & WM8994_AIF1ADCR_SRC))
1067 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1068 else
1069 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1070 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1071
1072 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1073 if ((val & WM8994_AIF1DACL_SRC) &&
1074 (val & WM8994_AIF1DACR_SRC))
1075 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1076 else if (!(val & WM8994_AIF1DACL_SRC) &&
1077 !(val & WM8994_AIF1DACR_SRC))
1078 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1079 else
1080 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1081 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1082
1083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1084 mask, adc);
1085 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1086 mask, dac);
1087 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1088 WM8994_AIF1DSPCLK_ENA |
1089 WM8994_SYSDSPCLK_ENA,
1090 WM8994_AIF1DSPCLK_ENA |
1091 WM8994_SYSDSPCLK_ENA);
1092 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1093 WM8994_AIF1ADC1R_ENA |
1094 WM8994_AIF1ADC1L_ENA |
1095 WM8994_AIF1ADC2R_ENA |
1096 WM8994_AIF1ADC2L_ENA);
1097 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1098 WM8994_AIF1DAC1R_ENA |
1099 WM8994_AIF1DAC1L_ENA |
1100 WM8994_AIF1DAC2R_ENA |
1101 WM8994_AIF1DAC2L_ENA);
173efa09 1102 break;
173efa09 1103
bfd37bb5
MB
1104 case SND_SOC_DAPM_POST_PMU:
1105 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1106 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1107 snd_soc_read(codec,
1108 wm8994_vu_bits[i].reg));
1109 break;
1110
1a38336b
MB
1111 case SND_SOC_DAPM_PRE_PMD:
1112 case SND_SOC_DAPM_POST_PMD:
1113 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1114 mask, 0);
1115 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1116 mask, 0);
1117
1118 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1119 if (val & WM8994_AIF2DSPCLK_ENA)
1120 val = WM8994_SYSDSPCLK_ENA;
1121 else
1122 val = 0;
1123 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1124 WM8994_SYSDSPCLK_ENA |
1125 WM8994_AIF1DSPCLK_ENA, val);
1126 break;
1127 }
c6b7b570 1128
173efa09
DP
1129 return 0;
1130}
1131
1a38336b
MB
1132static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1133 struct snd_kcontrol *kcontrol, int event)
173efa09
DP
1134{
1135 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1136 int i;
1a38336b
MB
1137 int dac;
1138 int adc;
1139 int val;
173efa09
DP
1140
1141 switch (event) {
1a38336b
MB
1142 case SND_SOC_DAPM_PRE_PMU:
1143 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1144 if ((val & WM8994_AIF2ADCL_SRC) &&
1145 (val & WM8994_AIF2ADCR_SRC))
1146 adc = WM8994_AIF2ADCR_ENA;
1147 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1148 !(val & WM8994_AIF2ADCR_SRC))
1149 adc = WM8994_AIF2ADCL_ENA;
1150 else
1151 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1152
1153
1154 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1155 if ((val & WM8994_AIF2DACL_SRC) &&
1156 (val & WM8994_AIF2DACR_SRC))
1157 dac = WM8994_AIF2DACR_ENA;
1158 else if (!(val & WM8994_AIF2DACL_SRC) &&
1159 !(val & WM8994_AIF2DACR_SRC))
1160 dac = WM8994_AIF2DACL_ENA;
1161 else
1162 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1163
1164 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1165 WM8994_AIF2ADCL_ENA |
1166 WM8994_AIF2ADCR_ENA, adc);
1167 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1168 WM8994_AIF2DACL_ENA |
1169 WM8994_AIF2DACR_ENA, dac);
1170 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1171 WM8994_AIF2DSPCLK_ENA |
1172 WM8994_SYSDSPCLK_ENA,
1173 WM8994_AIF2DSPCLK_ENA |
1174 WM8994_SYSDSPCLK_ENA);
1175 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1176 WM8994_AIF2ADCL_ENA |
1177 WM8994_AIF2ADCR_ENA,
1178 WM8994_AIF2ADCL_ENA |
1179 WM8994_AIF2ADCR_ENA);
1180 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1181 WM8994_AIF2DACL_ENA |
1182 WM8994_AIF2DACR_ENA,
1183 WM8994_AIF2DACL_ENA |
1184 WM8994_AIF2DACR_ENA);
1185 break;
1186
bfd37bb5
MB
1187 case SND_SOC_DAPM_POST_PMU:
1188 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1189 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1190 snd_soc_read(codec,
1191 wm8994_vu_bits[i].reg));
1192 break;
1193
1a38336b 1194 case SND_SOC_DAPM_PRE_PMD:
173efa09 1195 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB
1196 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1197 WM8994_AIF2DACL_ENA |
1198 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1199 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB
1200 WM8994_AIF2ADCL_ENA |
1201 WM8994_AIF2ADCR_ENA, 0);
1202
1203 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1204 if (val & WM8994_AIF1DSPCLK_ENA)
1205 val = WM8994_SYSDSPCLK_ENA;
1206 else
1207 val = 0;
1208 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1209 WM8994_SYSDSPCLK_ENA |
1210 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP
1211 break;
1212 }
1213
1214 return 0;
1215}
1216
1a38336b
MB
1217static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1218 struct snd_kcontrol *kcontrol, int event)
173efa09
DP
1219{
1220 struct snd_soc_codec *codec = w->codec;
1221 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1222
1223 switch (event) {
1224 case SND_SOC_DAPM_PRE_PMU:
1225 wm8994->aif1clk_enable = 1;
1226 break;
a3cff81a
DP
1227 case SND_SOC_DAPM_POST_PMD:
1228 wm8994->aif1clk_disable = 1;
1229 break;
173efa09
DP
1230 }
1231
1232 return 0;
1233}
1234
1a38336b
MB
1235static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1236 struct snd_kcontrol *kcontrol, int event)
173efa09
DP
1237{
1238 struct snd_soc_codec *codec = w->codec;
1239 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1240
1241 switch (event) {
1242 case SND_SOC_DAPM_PRE_PMU:
1243 wm8994->aif2clk_enable = 1;
1244 break;
a3cff81a
DP
1245 case SND_SOC_DAPM_POST_PMD:
1246 wm8994->aif2clk_disable = 1;
1247 break;
173efa09
DP
1248 }
1249
1250 return 0;
1251}
1252
1a38336b
MB
1253static int late_enable_ev(struct snd_soc_dapm_widget *w,
1254 struct snd_kcontrol *kcontrol, int event)
1255{
1256 struct snd_soc_codec *codec = w->codec;
1257 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1258
1259 switch (event) {
1260 case SND_SOC_DAPM_PRE_PMU:
1261 if (wm8994->aif1clk_enable) {
c8fdc1b5 1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB
1263 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1264 WM8994_AIF1CLK_ENA_MASK,
1265 WM8994_AIF1CLK_ENA);
c8fdc1b5 1266 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB
1267 wm8994->aif1clk_enable = 0;
1268 }
1269 if (wm8994->aif2clk_enable) {
c8fdc1b5 1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB
1271 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1272 WM8994_AIF2CLK_ENA_MASK,
1273 WM8994_AIF2CLK_ENA);
c8fdc1b5 1274 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB
1275 wm8994->aif2clk_enable = 0;
1276 }
1277 break;
1278 }
1279
1280 /* We may also have postponed startup of DSP, handle that. */
1281 wm8958_aif_ev(w, kcontrol, event);
1282
1283 return 0;
1284}
1285
1286static int late_disable_ev(struct snd_soc_dapm_widget *w,
1287 struct snd_kcontrol *kcontrol, int event)
1288{
1289 struct snd_soc_codec *codec = w->codec;
1290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1291
1292 switch (event) {
1293 case SND_SOC_DAPM_POST_PMD:
1294 if (wm8994->aif1clk_disable) {
c8fdc1b5 1295 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB
1296 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1297 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1298 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB
1299 wm8994->aif1clk_disable = 0;
1300 }
1301 if (wm8994->aif2clk_disable) {
c8fdc1b5 1302 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB
1303 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1304 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1305 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB
1306 wm8994->aif2clk_disable = 0;
1307 }
1308 break;
1309 }
1310
1311 return 0;
1312}
1313
04d28681
DP
1314static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1315 struct snd_kcontrol *kcontrol, int event)
1316{
1317 late_enable_ev(w, kcontrol, event);
1318 return 0;
1319}
1320
b462c6e6
DP
1321static int micbias_ev(struct snd_soc_dapm_widget *w,
1322 struct snd_kcontrol *kcontrol, int event)
1323{
1324 late_enable_ev(w, kcontrol, event);
1325 return 0;
1326}
1327
c52fd021
DP
1328static int dac_ev(struct snd_soc_dapm_widget *w,
1329 struct snd_kcontrol *kcontrol, int event)
1330{
1331 struct snd_soc_codec *codec = w->codec;
1332 unsigned int mask = 1 << w->shift;
1333
1334 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1335 mask, mask);
1336 return 0;
1337}
1338
9e6e96a1
MB
1339static const char *adc_mux_text[] = {
1340 "ADC",
1341 "DMIC",
1342};
1343
1344static const struct soc_enum adc_enum =
1345 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1346
1347static const struct snd_kcontrol_new adcl_mux =
1348 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1349
1350static const struct snd_kcontrol_new adcr_mux =
1351 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1352
1353static const struct snd_kcontrol_new left_speaker_mixer[] = {
1354SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1355SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1356SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1357SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1358SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1359};
1360
1361static const struct snd_kcontrol_new right_speaker_mixer[] = {
1362SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1363SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1364SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1365SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1366SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1367};
1368
1369/* Debugging; dump chip status after DAPM transitions */
1370static int post_ev(struct snd_soc_dapm_widget *w,
1371 struct snd_kcontrol *kcontrol, int event)
1372{
1373 struct snd_soc_codec *codec = w->codec;
1374 dev_dbg(codec->dev, "SRC status: %x\n",
1375 snd_soc_read(codec,
1376 WM8994_RATE_STATUS));
1377 return 0;
1378}
1379
1380static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1381SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1382 1, 1, 0),
1383SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1384 0, 1, 0),
1385};
1386
1387static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1388SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1389 1, 1, 0),
1390SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1391 0, 1, 0),
1392};
1393
a3257ba8
MB
1394static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1395SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1396 1, 1, 0),
1397SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1398 0, 1, 0),
1399};
1400
1401static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1402SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1403 1, 1, 0),
1404SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1405 0, 1, 0),
1406};
1407
9e6e96a1
MB
1408static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1409SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410 5, 1, 0),
1411SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 4, 1, 0),
1413SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 2, 1, 0),
1415SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416 1, 1, 0),
1417SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418 0, 1, 0),
1419};
1420
1421static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1422SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423 5, 1, 0),
1424SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 4, 1, 0),
1426SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 2, 1, 0),
1428SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429 1, 1, 0),
1430SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431 0, 1, 0),
1432};
1433
1434#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
6e06509c 1435 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
ed6a2772 1436 snd_soc_dapm_get_volsw, wm8994_put_class_w)
9e6e96a1
MB
1437
1438static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1439 struct snd_ctl_elem_value *ucontrol)
1440{
eee5d7f9 1441 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
9e6e96a1
MB
1442 int ret;
1443
1444 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1445
c340304d 1446 wm_hubs_update_class_w(codec);
9e6e96a1
MB
1447
1448 return ret;
1449}
1450
1451static const struct snd_kcontrol_new dac1l_mix[] = {
1452WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453 5, 1, 0),
1454WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 4, 1, 0),
1456WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457 2, 1, 0),
1458WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 1, 1, 0),
1460WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 0, 1, 0),
1462};
1463
1464static const struct snd_kcontrol_new dac1r_mix[] = {
1465WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466 5, 1, 0),
1467WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 4, 1, 0),
1469WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470 2, 1, 0),
1471WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 1, 1, 0),
1473WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 0, 1, 0),
1475};
1476
1477static const char *sidetone_text[] = {
1478 "ADC/DMIC1", "DMIC2",
1479};
1480
1481static const struct soc_enum sidetone1_enum =
1482 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1483
1484static const struct snd_kcontrol_new sidetone1_mux =
1485 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1486
1487static const struct soc_enum sidetone2_enum =
1488 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1489
1490static const struct snd_kcontrol_new sidetone2_mux =
1491 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1492
1493static const char *aif1dac_text[] = {
1494 "AIF1DACDAT", "AIF3DACDAT",
1495};
1496
50941968
MB
1497static const char *loopback_text[] = {
1498 "None", "ADCDAT",
1499};
1500
1501static const struct soc_enum aif1_loopback_enum =
1502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, WM8994_AIF1_LOOPBACK_SHIFT, 2,
1503 loopback_text);
1504
1505static const struct snd_kcontrol_new aif1_loopback =
1506 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1507
1508static const struct soc_enum aif2_loopback_enum =
1509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, WM8994_AIF2_LOOPBACK_SHIFT, 2,
1510 loopback_text);
1511
1512static const struct snd_kcontrol_new aif2_loopback =
1513 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1514
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MB
1515static const struct soc_enum aif1dac_enum =
1516 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1517
1518static const struct snd_kcontrol_new aif1dac_mux =
1519 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1520
1521static const char *aif2dac_text[] = {
1522 "AIF2DACDAT", "AIF3DACDAT",
1523};
1524
1525static const struct soc_enum aif2dac_enum =
1526 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1527
1528static const struct snd_kcontrol_new aif2dac_mux =
1529 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1530
1531static const char *aif2adc_text[] = {
1532 "AIF2ADCDAT", "AIF3DACDAT",
1533};
1534
1535static const struct soc_enum aif2adc_enum =
1536 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1537
1538static const struct snd_kcontrol_new aif2adc_mux =
1539 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1540
1541static const char *aif3adc_text[] = {
c4431df0 1542 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB
1543};
1544
c4431df0 1545static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
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1546 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1547
c4431df0
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1548static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1549 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1550
1551static const struct soc_enum wm8958_aif3adc_enum =
1552 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1553
1554static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1555 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1556
1557static const char *mono_pcm_out_text[] = {
c1a4ecd9 1558 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB
1559};
1560
1561static const struct soc_enum mono_pcm_out_enum =
1562 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1563
1564static const struct snd_kcontrol_new mono_pcm_out_mux =
1565 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1566
1567static const char *aif2dac_src_text[] = {
1568 "AIF2", "AIF3",
1569};
1570
1571/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1572static const struct soc_enum aif2dacl_src_enum =
1573 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1574
1575static const struct snd_kcontrol_new aif2dacl_src_mux =
1576 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1577
1578static const struct soc_enum aif2dacr_src_enum =
1579 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1580
1581static const struct snd_kcontrol_new aif2dacr_src_mux =
1582 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1583
173efa09 1584static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1585SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1586 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1587SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP
1588 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1589
1590SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1591 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1592SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1593 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1594SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1595 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1597 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB
1598SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1599 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600
1601SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1602 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1603 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1605 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1606 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1607SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1609SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1610 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP
1611
1612SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1613};
1614
1615static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1616SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB
1617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1618 SND_SOC_DAPM_PRE_PMD),
1a38336b 1619SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB
1620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1621 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB
1622SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1623SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1624 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1625SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1626 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB
1627SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1628SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP
1629};
1630
c52fd021
DP
1631static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1632SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1633 dac_ev, SND_SOC_DAPM_PRE_PMU),
1634SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1635 dac_ev, SND_SOC_DAPM_PRE_PMU),
1636SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1637 dac_ev, SND_SOC_DAPM_PRE_PMU),
1638SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1639 dac_ev, SND_SOC_DAPM_PRE_PMU),
1640};
1641
1642static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1643SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1644SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP
1645SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1646SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1647};
1648
04d28681 1649static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
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1650SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1651 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1652SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1653 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP
1654};
1655
1656static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB
1657SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1658SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP
1659};
1660
9e6e96a1
MB
1661static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1662SND_SOC_DAPM_INPUT("DMIC1DAT"),
1663SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1664SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1665
b462c6e6
DP
1666SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1667 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB
1668SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1669 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1670
9e6e96a1 1671SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB
1672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1673 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1674
1a38336b
MB
1675SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1676SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1677SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1678
7f94de48 1679SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1680 0, SND_SOC_NOPM, 9, 0),
7f94de48 1681SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1682 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1683SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1684 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1685 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1686SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1687 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1688 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1689
7f94de48 1690SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1691 0, SND_SOC_NOPM, 11, 0),
7f94de48 1692SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1693 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1694SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1695 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1696 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1697SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1698 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1699 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB
1700
1701SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1702 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1703SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1704 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1705
a3257ba8
MB
1706SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1707 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1708SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1710
9e6e96a1
MB
1711SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1712 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1713SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1714 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1715
1716SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1717SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1718
1719SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1720 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1721SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1722 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1723
1724SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1725 SND_SOC_NOPM, 13, 0),
9e6e96a1 1726SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1727 SND_SOC_NOPM, 12, 0),
d6addcc9 1728SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1729 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB
1730 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1731SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1732 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1733 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1734
5567d8c6
MB
1735SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1736SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1737SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1738SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB
1739
1740SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1741SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1742SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1743
5567d8c6
MB
1744SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1745SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB
1746
1747SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1748
1749SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1750SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1751SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1752SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1753
1754/* Power is done with the muxes since the ADC power also controls the
1755 * downsampling chain, the chip will automatically manage the analogue
1756 * specific portions.
1757 */
1758SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1759SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1760
50941968
MB
1761SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1762SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1763
9e6e96a1
MB
1764SND_SOC_DAPM_POST("Debug log", post_ev),
1765};
1766
c4431df0
MB
1767static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1768SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1769};
9e6e96a1 1770
c4431df0 1771static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1772SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
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1773SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1774SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1775SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1776SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1777};
1778
1779static const struct snd_soc_dapm_route intercon[] = {
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1780 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1781 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1782
1783 { "DSP1CLK", NULL, "CLK_SYS" },
1784 { "DSP2CLK", NULL, "CLK_SYS" },
1785 { "DSPINTCLK", NULL, "CLK_SYS" },
1786
1787 { "AIF1ADC1L", NULL, "AIF1CLK" },
1788 { "AIF1ADC1L", NULL, "DSP1CLK" },
1789 { "AIF1ADC1R", NULL, "AIF1CLK" },
1790 { "AIF1ADC1R", NULL, "DSP1CLK" },
1791 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1792
1793 { "AIF1DAC1L", NULL, "AIF1CLK" },
1794 { "AIF1DAC1L", NULL, "DSP1CLK" },
1795 { "AIF1DAC1R", NULL, "AIF1CLK" },
1796 { "AIF1DAC1R", NULL, "DSP1CLK" },
1797 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1798
1799 { "AIF1ADC2L", NULL, "AIF1CLK" },
1800 { "AIF1ADC2L", NULL, "DSP1CLK" },
1801 { "AIF1ADC2R", NULL, "AIF1CLK" },
1802 { "AIF1ADC2R", NULL, "DSP1CLK" },
1803 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1804
1805 { "AIF1DAC2L", NULL, "AIF1CLK" },
1806 { "AIF1DAC2L", NULL, "DSP1CLK" },
1807 { "AIF1DAC2R", NULL, "AIF1CLK" },
1808 { "AIF1DAC2R", NULL, "DSP1CLK" },
1809 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1810
1811 { "AIF2ADCL", NULL, "AIF2CLK" },
1812 { "AIF2ADCL", NULL, "DSP2CLK" },
1813 { "AIF2ADCR", NULL, "AIF2CLK" },
1814 { "AIF2ADCR", NULL, "DSP2CLK" },
1815 { "AIF2ADCR", NULL, "DSPINTCLK" },
1816
1817 { "AIF2DACL", NULL, "AIF2CLK" },
1818 { "AIF2DACL", NULL, "DSP2CLK" },
1819 { "AIF2DACR", NULL, "AIF2CLK" },
1820 { "AIF2DACR", NULL, "DSP2CLK" },
1821 { "AIF2DACR", NULL, "DSPINTCLK" },
1822
1823 { "DMIC1L", NULL, "DMIC1DAT" },
1824 { "DMIC1L", NULL, "CLK_SYS" },
1825 { "DMIC1R", NULL, "DMIC1DAT" },
1826 { "DMIC1R", NULL, "CLK_SYS" },
1827 { "DMIC2L", NULL, "DMIC2DAT" },
1828 { "DMIC2L", NULL, "CLK_SYS" },
1829 { "DMIC2R", NULL, "DMIC2DAT" },
1830 { "DMIC2R", NULL, "CLK_SYS" },
1831
1832 { "ADCL", NULL, "AIF1CLK" },
1833 { "ADCL", NULL, "DSP1CLK" },
1834 { "ADCL", NULL, "DSPINTCLK" },
1835
1836 { "ADCR", NULL, "AIF1CLK" },
1837 { "ADCR", NULL, "DSP1CLK" },
1838 { "ADCR", NULL, "DSPINTCLK" },
1839
1840 { "ADCL Mux", "ADC", "ADCL" },
1841 { "ADCL Mux", "DMIC", "DMIC1L" },
1842 { "ADCR Mux", "ADC", "ADCR" },
1843 { "ADCR Mux", "DMIC", "DMIC1R" },
1844
1845 { "DAC1L", NULL, "AIF1CLK" },
1846 { "DAC1L", NULL, "DSP1CLK" },
1847 { "DAC1L", NULL, "DSPINTCLK" },
1848
1849 { "DAC1R", NULL, "AIF1CLK" },
1850 { "DAC1R", NULL, "DSP1CLK" },
1851 { "DAC1R", NULL, "DSPINTCLK" },
1852
1853 { "DAC2L", NULL, "AIF2CLK" },
1854 { "DAC2L", NULL, "DSP2CLK" },
1855 { "DAC2L", NULL, "DSPINTCLK" },
1856
1857 { "DAC2R", NULL, "AIF2DACR" },
1858 { "DAC2R", NULL, "AIF2CLK" },
1859 { "DAC2R", NULL, "DSP2CLK" },
1860 { "DAC2R", NULL, "DSPINTCLK" },
1861
1862 { "TOCLK", NULL, "CLK_SYS" },
1863
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1864 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1865 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1866 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1867
1868 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1869 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1870 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1871
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1872 /* AIF1 outputs */
1873 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1874 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1875 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1876
1877 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1878 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1879 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1880
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1881 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1882 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1883 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1884
1885 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1886 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1887 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1888
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1889 /* Pin level routing for AIF3 */
1890 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1891 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1892 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1893 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1894
50941968 1895 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
9e6e96a1 1896 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
50941968 1897 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
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1898 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1899 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1900 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1901 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1902
1903 /* DAC1 inputs */
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1904 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1905 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1906 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1907 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909
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1910 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1911 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1912 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1913 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1914 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1915
1916 /* DAC2/AIF2 outputs */
1917 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
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1918 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1919 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1920 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1921 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1922 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1923
1924 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
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1925 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1926 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1927 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1928 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1929 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1930
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1931 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1932 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1933 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1934 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1935
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1936 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1937
1938 /* AIF3 output */
1939 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1940 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1941 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1942 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1943 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1944 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1945 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1946 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1947
50941968
MB
1948 /* Loopback */
1949 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1950 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1951 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1952 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1953
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1954 /* Sidetone */
1955 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1956 { "Left Sidetone", "DMIC2", "DMIC2L" },
1957 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1958 { "Right Sidetone", "DMIC2", "DMIC2R" },
1959
1960 /* Output stages */
1961 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1962 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1963
1964 { "SPKL", "DAC1 Switch", "DAC1L" },
1965 { "SPKL", "DAC2 Switch", "DAC2L" },
1966
1967 { "SPKR", "DAC1 Switch", "DAC1R" },
1968 { "SPKR", "DAC2 Switch", "DAC2R" },
1969
1970 { "Left Headphone Mux", "DAC", "DAC1L" },
1971 { "Right Headphone Mux", "DAC", "DAC1R" },
1972};
1973
173efa09
DP
1974static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1975 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1976 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1977 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1978 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1979 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1980 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1981 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1982 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1983};
1984
1985static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1986 { "DAC1L", NULL, "DAC1L Mixer" },
1987 { "DAC1R", NULL, "DAC1R Mixer" },
1988 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1989 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1990};
1991
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1992static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1993 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1994 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1995 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1996 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
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1997 { "MICBIAS1", NULL, "CLK_SYS" },
1998 { "MICBIAS1", NULL, "MICBIAS Supply" },
1999 { "MICBIAS2", NULL, "CLK_SYS" },
2000 { "MICBIAS2", NULL, "MICBIAS Supply" },
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2001};
2002
c4431df0
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2003static const struct snd_soc_dapm_route wm8994_intercon[] = {
2004 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2005 { "AIF2DACR", NULL, "AIF2DAC Mux" },
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2006 { "MICBIAS1", NULL, "VMID" },
2007 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB
2008};
2009
2010static const struct snd_soc_dapm_route wm8958_intercon[] = {
2011 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2012 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2013
2014 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2015 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2016 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2017 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2018
8c5b842b
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2019 { "AIF3DACDAT", NULL, "AIF3" },
2020 { "AIF3ADCDAT", NULL, "AIF3" },
2021
c4431df0
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2022 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2023 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2024
2025 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2026};
2027
9e6e96a1
MB
2028/* The size in bits of the FLL divide multiplied by 10
2029 * to allow rounding later */
2030#define FIXED_FLL_SIZE ((1 << 16) * 10)
2031
2032struct fll_div {
2033 u16 outdiv;
2034 u16 n;
2035 u16 k;
d1a0a299 2036 u16 lambda;
9e6e96a1
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2037 u16 clk_ref_div;
2038 u16 fll_fratio;
2039};
2040
d1a0a299 2041static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
9e6e96a1
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2042 int freq_in, int freq_out)
2043{
2044 u64 Kpart;
d1a0a299 2045 unsigned int K, Ndiv, Nmod, gcd_fll;
9e6e96a1
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2046
2047 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2048
2049 /* Scale the input frequency down to <= 13.5MHz */
2050 fll->clk_ref_div = 0;
2051 while (freq_in > 13500000) {
2052 fll->clk_ref_div++;
2053 freq_in /= 2;
2054
2055 if (fll->clk_ref_div > 3)
2056 return -EINVAL;
2057 }
2058 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2059
2060 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2061 fll->outdiv = 3;
2062 while (freq_out * (fll->outdiv + 1) < 90000000) {
2063 fll->outdiv++;
2064 if (fll->outdiv > 63)
2065 return -EINVAL;
2066 }
2067 freq_out *= fll->outdiv + 1;
2068 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2069
2070 if (freq_in > 1000000) {
2071 fll->fll_fratio = 0;
7d48a6ac
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2072 } else if (freq_in > 256000) {
2073 fll->fll_fratio = 1;
2074 freq_in *= 2;
2075 } else if (freq_in > 128000) {
2076 fll->fll_fratio = 2;
2077 freq_in *= 4;
2078 } else if (freq_in > 64000) {
9e6e96a1
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2079 fll->fll_fratio = 3;
2080 freq_in *= 8;
7d48a6ac
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2081 } else {
2082 fll->fll_fratio = 4;
2083 freq_in *= 16;
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2084 }
2085 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2086
2087 /* Now, calculate N.K */
2088 Ndiv = freq_out / freq_in;
2089
2090 fll->n = Ndiv;
2091 Nmod = freq_out % freq_in;
2092 pr_debug("Nmod=%d\n", Nmod);
2093
d1a0a299
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2094 switch (control->type) {
2095 case WM8994:
2096 /* Calculate fractional part - scale up so we can round. */
2097 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
9e6e96a1 2098
d1a0a299 2099 do_div(Kpart, freq_in);
9e6e96a1 2100
d1a0a299 2101 K = Kpart & 0xFFFFFFFF;
9e6e96a1 2102
d1a0a299
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2103 if ((K % 10) >= 5)
2104 K += 5;
9e6e96a1 2105
d1a0a299
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2106 /* Move down to proper range now rounding is done */
2107 fll->k = K / 10;
f7dbd399 2108 fll->lambda = 0;
9e6e96a1 2109
d1a0a299 2110 pr_debug("N=%x K=%x\n", fll->n, fll->k);
571ab6c6 2111 break;
9e6e96a1 2112
d1a0a299
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2113 default:
2114 gcd_fll = gcd(freq_out, freq_in);
9e6e96a1 2115
d1a0a299
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2116 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2117 fll->lambda = freq_in / gcd_fll;
2118
2119 }
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2120
2121 return 0;
2122}
2123
f0fba2ad 2124static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
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2125 unsigned int freq_in, unsigned int freq_out)
2126{
b2c812e2 2127 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2128 struct wm8994 *control = wm8994->wm8994;
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2129 int reg_offset, ret;
2130 struct fll_div fll;
e413ba88 2131 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2132 unsigned long timeout;
4b7ed83a 2133 bool was_enabled;
9e6e96a1 2134
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2135 switch (id) {
2136 case WM8994_FLL1:
2137 reg_offset = 0;
2138 id = 0;
e413ba88 2139 aif_src = 0x10;
9e6e96a1
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2140 break;
2141 case WM8994_FLL2:
2142 reg_offset = 0x20;
2143 id = 1;
e413ba88 2144 aif_src = 0x18;
9e6e96a1
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2145 break;
2146 default:
2147 return -EINVAL;
2148 }
2149
4b7ed83a
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2150 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2151 was_enabled = reg & WM8994_FLL1_ENA;
2152
136ff2a2 2153 switch (src) {
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2154 case 0:
2155 /* Allow no source specification when stopping */
2156 if (freq_out)
2157 return -EINVAL;
4514e899 2158 src = wm8994->fll[id].src;
7add84aa 2159 break;
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2160 case WM8994_FLL_SRC_MCLK1:
2161 case WM8994_FLL_SRC_MCLK2:
2162 case WM8994_FLL_SRC_LRCLK:
2163 case WM8994_FLL_SRC_BCLK:
2164 break;
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2165 case WM8994_FLL_SRC_INTERNAL:
2166 freq_in = 12000000;
2167 freq_out = 12000000;
2168 break;
136ff2a2
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2169 default:
2170 return -EINVAL;
2171 }
2172
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2173 /* Are we changing anything? */
2174 if (wm8994->fll[id].src == src &&
2175 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2176 return 0;
2177
2178 /* If we're stopping the FLL redo the old config - no
2179 * registers will actually be written but we avoid GCC flow
2180 * analysis bugs spewing warnings.
2181 */
2182 if (freq_out)
d1a0a299 2183 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
9e6e96a1 2184 else
d1a0a299 2185 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
9e6e96a1
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2186 wm8994->fll[id].out);
2187 if (ret < 0)
2188 return ret;
2189
e413ba88
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2190 /* Make sure that we're not providing SYSCLK right now */
2191 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2192 if (clk1 & WM8994_SYSCLK_SRC)
2193 aif_reg = WM8994_AIF2_CLOCKING_1;
2194 else
2195 aif_reg = WM8994_AIF1_CLOCKING_1;
2196 reg = snd_soc_read(codec, aif_reg);
2197
2198 if ((reg & WM8994_AIF1CLK_ENA) &&
2199 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2200 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2201 id + 1);
2202 return -EBUSY;
2203 }
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2204
2205 /* We always need to disable the FLL while reconfiguring */
2206 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2207 WM8994_FLL1_ENA, 0);
2208
20dc24a9 2209 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2210 freq_in == freq_out && freq_out) {
20dc24a9
MB
2211 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2212 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2213 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2214 goto out;
2215 }
2216
9e6e96a1
MB
2217 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2218 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2219 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2220 WM8994_FLL1_OUTDIV_MASK |
2221 WM8994_FLL1_FRATIO_MASK, reg);
2222
b16db745
MB
2223 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2224 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB
2225
2226 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2227 WM8994_FLL1_N_MASK,
7435d4ee 2228 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1 2229
d1a0a299
MB
2230 if (fll.lambda) {
2231 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2232 WM8958_FLL1_LAMBDA_MASK,
2233 fll.lambda);
2234 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2235 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2236 } else {
2237 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2238 WM8958_FLL1_EFS_ENA, 0);
2239 }
2240
9e6e96a1 2241 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2242 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB
2243 WM8994_FLL1_REFCLK_DIV_MASK |
2244 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB
2245 ((src == WM8994_FLL_SRC_INTERNAL)
2246 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB
2247 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2248 (src - 1));
9e6e96a1 2249
f0f5039c
MB
2250 /* Clear any pending completion from a previous failure */
2251 try_wait_for_completion(&wm8994->fll_locked[id]);
2252
9e6e96a1
MB
2253 /* Enable (with fractional mode if required) */
2254 if (freq_out) {
4b7ed83a
MB
2255 /* Enable VMID if we need it */
2256 if (!was_enabled) {
af6b6fe4
MB
2257 active_reference(codec);
2258
4b7ed83a
MB
2259 switch (control->type) {
2260 case WM8994:
2261 vmid_reference(codec);
2262 break;
2263 case WM8958:
da445afe 2264 if (control->revision < 1)
4b7ed83a
MB
2265 vmid_reference(codec);
2266 break;
2267 default:
2268 break;
2269 }
2270 }
2271
fbfe6983
MB
2272 reg = WM8994_FLL1_ENA;
2273
9e6e96a1 2274 if (fll.k)
fbfe6983
MB
2275 reg |= WM8994_FLL1_FRAC;
2276 if (src == WM8994_FLL_SRC_INTERNAL)
2277 reg |= WM8994_FLL1_OSC_ENA;
2278
9e6e96a1 2279 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB
2280 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2281 WM8994_FLL1_FRAC, reg);
8e9ddf81 2282
c7ebf932
MB
2283 if (wm8994->fll_locked_irq) {
2284 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2285 msecs_to_jiffies(10));
2286 if (timeout == 0)
2287 dev_warn(codec->dev,
2288 "Timed out waiting for FLL lock\n");
2289 } else {
2290 msleep(5);
2291 }
4b7ed83a
MB
2292 } else {
2293 if (was_enabled) {
2294 switch (control->type) {
2295 case WM8994:
2296 vmid_dereference(codec);
2297 break;
2298 case WM8958:
da445afe 2299 if (control->revision < 1)
4b7ed83a
MB
2300 vmid_dereference(codec);
2301 break;
2302 default:
2303 break;
2304 }
af6b6fe4
MB
2305
2306 active_dereference(codec);
4b7ed83a 2307 }
9e6e96a1
MB
2308 }
2309
20dc24a9 2310out:
9e6e96a1
MB
2311 wm8994->fll[id].in = freq_in;
2312 wm8994->fll[id].out = freq_out;
136ff2a2 2313 wm8994->fll[id].src = src;
9e6e96a1 2314
9e6e96a1
MB
2315 configure_clock(codec);
2316
cd22000a
MB
2317 /*
2318 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2319 * for detection.
2320 */
2321 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2322 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB
2323
2324 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2325 & WM8994_AIF1CLK_RATE_MASK;
2326 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2327 & WM8994_AIF1CLK_RATE_MASK;
2328
cd22000a
MB
2329 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2330 WM8994_AIF1CLK_RATE_MASK, 0x1);
2331 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2332 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB
2333 } else if (wm8994->aifdiv[0]) {
2334 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2335 WM8994_AIF1CLK_RATE_MASK,
2336 wm8994->aifdiv[0]);
2337 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2338 WM8994_AIF2CLK_RATE_MASK,
2339 wm8994->aifdiv[1]);
2340
2341 wm8994->aifdiv[0] = 0;
2342 wm8994->aifdiv[1] = 0;
cd22000a
MB
2343 }
2344
9e6e96a1
MB
2345 return 0;
2346}
2347
c7ebf932
MB
2348static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2349{
2350 struct completion *completion = data;
2351
2352 complete(completion);
2353
2354 return IRQ_HANDLED;
2355}
f0fba2ad 2356
66b47fdb
MB
2357static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2358
f0fba2ad
LG
2359static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2360 unsigned int freq_in, unsigned int freq_out)
2361{
2362 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2363}
2364
9e6e96a1
MB
2365static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2366 int clk_id, unsigned int freq, int dir)
2367{
2368 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2369 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2370 int i;
9e6e96a1
MB
2371
2372 switch (dai->id) {
2373 case 1:
2374 case 2:
2375 break;
2376
2377 default:
2378 /* AIF3 shares clocking with AIF1/2 */
2379 return -EINVAL;
2380 }
2381
2382 switch (clk_id) {
2383 case WM8994_SYSCLK_MCLK1:
2384 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2385 wm8994->mclk[0] = freq;
2386 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2387 dai->id, freq);
2388 break;
2389
2390 case WM8994_SYSCLK_MCLK2:
2391 /* TODO: Set GPIO AF */
2392 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2393 wm8994->mclk[1] = freq;
2394 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2395 dai->id, freq);
2396 break;
2397
2398 case WM8994_SYSCLK_FLL1:
2399 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2400 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2401 break;
2402
2403 case WM8994_SYSCLK_FLL2:
2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2405 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2406 break;
2407
66b47fdb
MB
2408 case WM8994_SYSCLK_OPCLK:
2409 /* Special case - a division (times 10) is given and
c1a4ecd9 2410 * no effect on main clocking.
66b47fdb
MB
2411 */
2412 if (freq) {
2413 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2414 if (opclk_divs[i] == freq)
2415 break;
2416 if (i == ARRAY_SIZE(opclk_divs))
2417 return -EINVAL;
2418 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2419 WM8994_OPCLK_DIV_MASK, i);
2420 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2421 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2422 } else {
2423 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2424 WM8994_OPCLK_ENA, 0);
2425 }
2426
9e6e96a1
MB
2427 default:
2428 return -EINVAL;
2429 }
2430
2431 configure_clock(codec);
2432
6730049a
MB
2433 /*
2434 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2435 * for detection.
2436 */
2437 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2438 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB
2439
2440 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2441 & WM8994_AIF1CLK_RATE_MASK;
2442 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2443 & WM8994_AIF1CLK_RATE_MASK;
2444
6730049a
MB
2445 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2446 WM8994_AIF1CLK_RATE_MASK, 0x1);
2447 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2448 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB
2449 } else if (wm8994->aifdiv[0]) {
2450 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451 WM8994_AIF1CLK_RATE_MASK,
2452 wm8994->aifdiv[0]);
2453 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2454 WM8994_AIF2CLK_RATE_MASK,
2455 wm8994->aifdiv[1]);
2456
2457 wm8994->aifdiv[0] = 0;
2458 wm8994->aifdiv[1] = 0;
6730049a
MB
2459 }
2460
9e6e96a1
MB
2461 return 0;
2462}
2463
2464static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2465 enum snd_soc_bias_level level)
2466{
b6b05691 2467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2468 struct wm8994 *control = wm8994->wm8994;
b6b05691 2469
5f2f3890
MB
2470 wm_hubs_set_bias_level(codec, level);
2471
9e6e96a1
MB
2472 switch (level) {
2473 case SND_SOC_BIAS_ON:
2474 break;
2475
2476 case SND_SOC_BIAS_PREPARE:
500fa30e
MB
2477 /* MICBIAS into regulating mode */
2478 switch (control->type) {
2479 case WM8958:
2480 case WM1811:
2481 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2482 WM8958_MICB1_MODE, 0);
2483 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2484 WM8958_MICB2_MODE, 0);
2485 break;
2486 default:
2487 break;
2488 }
af6b6fe4
MB
2489
2490 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2491 active_reference(codec);
9e6e96a1
MB
2492 break;
2493
2494 case SND_SOC_BIAS_STANDBY:
ce6120cc 2495 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2496 switch (control->type) {
8bc3c2c2 2497 case WM8958:
da445afe 2498 if (control->revision == 0) {
8bc3c2c2 2499 /* Optimise performance for rev A */
8bc3c2c2
MB
2500 snd_soc_update_bits(codec,
2501 WM8958_CHARGE_PUMP_2,
2502 WM8958_CP_DISCH,
2503 WM8958_CP_DISCH);
2504 }
2505 break;
81204c84 2506
462835e4 2507 default:
81204c84 2508 break;
b6b05691 2509 }
9e6e96a1
MB
2510
2511 /* Discharge LINEOUT1 & 2 */
2512 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2513 WM8994_LINEOUT1_DISCH |
2514 WM8994_LINEOUT2_DISCH,
2515 WM8994_LINEOUT1_DISCH |
2516 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB
2517 }
2518
af6b6fe4
MB
2519 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2520 active_dereference(codec);
2521
500fa30e
MB
2522 /* MICBIAS into bypass mode on newer devices */
2523 switch (control->type) {
2524 case WM8958:
2525 case WM1811:
2526 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2527 WM8958_MICB1_MODE,
2528 WM8958_MICB1_MODE);
2529 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2530 WM8958_MICB2_MODE,
2531 WM8958_MICB2_MODE);
2532 break;
2533 default:
2534 break;
2535 }
9e6e96a1
MB
2536 break;
2537
2538 case SND_SOC_BIAS_OFF:
4105ab84 2539 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2540 wm8994->cur_fw = NULL;
9e6e96a1
MB
2541 break;
2542 }
5f2f3890 2543
ce6120cc 2544 codec->dapm.bias_level = level;
af6b6fe4 2545
22f8d055
MB
2546 return 0;
2547}
2548
2549int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2550{
2551 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2552
2553 switch (mode) {
2554 case WM8994_VMID_NORMAL:
2555 if (wm8994->hubs.lineout1_se) {
2556 snd_soc_dapm_disable_pin(&codec->dapm,
2557 "LINEOUT1N Driver");
2558 snd_soc_dapm_disable_pin(&codec->dapm,
2559 "LINEOUT1P Driver");
2560 }
2561 if (wm8994->hubs.lineout2_se) {
2562 snd_soc_dapm_disable_pin(&codec->dapm,
2563 "LINEOUT2N Driver");
2564 snd_soc_dapm_disable_pin(&codec->dapm,
2565 "LINEOUT2P Driver");
2566 }
2567
2568 /* Do the sync with the old mode to allow it to clean up */
2569 snd_soc_dapm_sync(&codec->dapm);
2570 wm8994->vmid_mode = mode;
2571 break;
2572
2573 case WM8994_VMID_FORCE:
2574 if (wm8994->hubs.lineout1_se) {
2575 snd_soc_dapm_force_enable_pin(&codec->dapm,
2576 "LINEOUT1N Driver");
2577 snd_soc_dapm_force_enable_pin(&codec->dapm,
2578 "LINEOUT1P Driver");
2579 }
2580 if (wm8994->hubs.lineout2_se) {
2581 snd_soc_dapm_force_enable_pin(&codec->dapm,
2582 "LINEOUT2N Driver");
2583 snd_soc_dapm_force_enable_pin(&codec->dapm,
2584 "LINEOUT2P Driver");
2585 }
2586
2587 wm8994->vmid_mode = mode;
2588 snd_soc_dapm_sync(&codec->dapm);
2589 break;
2590
2591 default:
2592 return -EINVAL;
2593 }
2594
9e6e96a1
MB
2595 return 0;
2596}
2597
2598static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2599{
2600 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB
2601 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2602 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB
2603 int ms_reg;
2604 int aif1_reg;
435705e8
MB
2605 int dac_reg;
2606 int adc_reg;
9e6e96a1
MB
2607 int ms = 0;
2608 int aif1 = 0;
435705e8 2609 int lrclk = 0;
9e6e96a1
MB
2610
2611 switch (dai->id) {
2612 case 1:
2613 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2614 aif1_reg = WM8994_AIF1_CONTROL_1;
435705e8
MB
2615 dac_reg = WM8994_AIF1DAC_LRCLK;
2616 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB
2617 break;
2618 case 2:
2619 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2620 aif1_reg = WM8994_AIF2_CONTROL_1;
435705e8
MB
2621 dac_reg = WM8994_AIF1DAC_LRCLK;
2622 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB
2623 break;
2624 default:
2625 return -EINVAL;
2626 }
2627
2628 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2629 case SND_SOC_DAIFMT_CBS_CFS:
2630 break;
2631 case SND_SOC_DAIFMT_CBM_CFM:
2632 ms = WM8994_AIF1_MSTR;
2633 break;
2634 default:
2635 return -EINVAL;
2636 }
2637
2638 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2639 case SND_SOC_DAIFMT_DSP_B:
2640 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2641 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB
2642 case SND_SOC_DAIFMT_DSP_A:
2643 aif1 |= 0x18;
2644 break;
2645 case SND_SOC_DAIFMT_I2S:
2646 aif1 |= 0x10;
2647 break;
2648 case SND_SOC_DAIFMT_RIGHT_J:
2649 break;
2650 case SND_SOC_DAIFMT_LEFT_J:
2651 aif1 |= 0x8;
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2658 case SND_SOC_DAIFMT_DSP_A:
2659 case SND_SOC_DAIFMT_DSP_B:
2660 /* frame inversion not valid for DSP modes */
2661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2662 case SND_SOC_DAIFMT_NB_NF:
2663 break;
2664 case SND_SOC_DAIFMT_IB_NF:
2665 aif1 |= WM8994_AIF1_BCLK_INV;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
2670 break;
2671
2672 case SND_SOC_DAIFMT_I2S:
2673 case SND_SOC_DAIFMT_RIGHT_J:
2674 case SND_SOC_DAIFMT_LEFT_J:
2675 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2676 case SND_SOC_DAIFMT_NB_NF:
2677 break;
2678 case SND_SOC_DAIFMT_IB_IF:
2679 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
435705e8 2680 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB
2681 break;
2682 case SND_SOC_DAIFMT_IB_NF:
2683 aif1 |= WM8994_AIF1_BCLK_INV;
2684 break;
2685 case SND_SOC_DAIFMT_NB_IF:
2686 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2687 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB
2688 break;
2689 default:
2690 return -EINVAL;
2691 }
2692 break;
2693 default:
2694 return -EINVAL;
2695 }
2696
c4431df0
MB
2697 /* The AIF2 format configuration needs to be mirrored to AIF3
2698 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB
2699 switch (control->type) {
2700 case WM1811:
2701 case WM8958:
2702 if (dai->id == 2)
2703 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2704 WM8994_AIF1_LRCLK_INV |
2705 WM8958_AIF3_FMT_MASK, aif1);
2706 break;
2707
2708 default:
2709 break;
2710 }
c4431df0 2711
9e6e96a1
MB
2712 snd_soc_update_bits(codec, aif1_reg,
2713 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2714 WM8994_AIF1_FMT_MASK,
2715 aif1);
2716 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2717 ms);
435705e8
MB
2718 snd_soc_update_bits(codec, dac_reg,
2719 WM8958_AIF1_LRCLK_INV, lrclk);
2720 snd_soc_update_bits(codec, adc_reg,
2721 WM8958_AIF1_LRCLK_INV, lrclk);
9e6e96a1
MB
2722
2723 return 0;
2724}
2725
2726static struct {
2727 int val, rate;
2728} srs[] = {
2729 { 0, 8000 },
2730 { 1, 11025 },
2731 { 2, 12000 },
2732 { 3, 16000 },
2733 { 4, 22050 },
2734 { 5, 24000 },
2735 { 6, 32000 },
2736 { 7, 44100 },
2737 { 8, 48000 },
2738 { 9, 88200 },
2739 { 10, 96000 },
2740};
2741
2742static int fs_ratios[] = {
2743 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2744};
2745
2746static int bclk_divs[] = {
2747 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2748 640, 880, 960, 1280, 1760, 1920
2749};
2750
2751static int wm8994_hw_params(struct snd_pcm_substream *substream,
2752 struct snd_pcm_hw_params *params,
2753 struct snd_soc_dai *dai)
2754{
2755 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2756 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3cf956ee
MB
2757 struct wm8994 *control = wm8994->wm8994;
2758 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1 2759 int aif1_reg;
b1e43d93 2760 int aif2_reg;
9e6e96a1
MB
2761 int bclk_reg;
2762 int lrclk_reg;
2763 int rate_reg;
2764 int aif1 = 0;
b1e43d93 2765 int aif2 = 0;
9e6e96a1
MB
2766 int bclk = 0;
2767 int lrclk = 0;
2768 int rate_val = 0;
2769 int id = dai->id - 1;
2770
2771 int i, cur_val, best_val, bclk_rate, best;
2772
2773 switch (dai->id) {
2774 case 1:
2775 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2776 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB
2777 bclk_reg = WM8994_AIF1_BCLK;
2778 rate_reg = WM8994_AIF1_RATE;
2779 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2780 wm8994->lrclk_shared[0]) {
9e6e96a1 2781 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2782 } else {
9e6e96a1 2783 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB
2784 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2785 }
9e6e96a1
MB
2786 break;
2787 case 2:
2788 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2789 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB
2790 bclk_reg = WM8994_AIF2_BCLK;
2791 rate_reg = WM8994_AIF2_RATE;
2792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2793 wm8994->lrclk_shared[1]) {
9e6e96a1 2794 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2795 } else {
9e6e96a1 2796 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB
2797 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2798 }
9e6e96a1
MB
2799 break;
2800 default:
2801 return -EINVAL;
2802 }
2803
79748cdb 2804 bclk_rate = params_rate(params);
9e6e96a1
MB
2805 switch (params_format(params)) {
2806 case SNDRV_PCM_FORMAT_S16_LE:
2807 bclk_rate *= 16;
2808 break;
2809 case SNDRV_PCM_FORMAT_S20_3LE:
2810 bclk_rate *= 20;
2811 aif1 |= 0x20;
2812 break;
2813 case SNDRV_PCM_FORMAT_S24_LE:
2814 bclk_rate *= 24;
2815 aif1 |= 0x40;
2816 break;
2817 case SNDRV_PCM_FORMAT_S32_LE:
2818 bclk_rate *= 32;
2819 aif1 |= 0x60;
2820 break;
2821 default:
2822 return -EINVAL;
2823 }
2824
79748cdb 2825 wm8994->channels[id] = params_channels(params);
3cf956ee
MB
2826 if (pdata->max_channels_clocked[id] &&
2827 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2828 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2829 pdata->max_channels_clocked[id], wm8994->channels[id]);
2830 wm8994->channels[id] = pdata->max_channels_clocked[id];
2831 }
2832
2833 switch (wm8994->channels[id]) {
79748cdb
MB
2834 case 1:
2835 case 2:
2836 bclk_rate *= 2;
2837 break;
2838 default:
2839 bclk_rate *= 4;
2840 break;
2841 }
2842
9e6e96a1
MB
2843 /* Try to find an appropriate sample rate; look for an exact match. */
2844 for (i = 0; i < ARRAY_SIZE(srs); i++)
2845 if (srs[i].rate == params_rate(params))
2846 break;
2847 if (i == ARRAY_SIZE(srs))
2848 return -EINVAL;
2849 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2850
2851 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2852 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2853 dai->id, wm8994->aifclk[id], bclk_rate);
2854
3cf956ee 2855 if (wm8994->channels[id] == 1 &&
b1e43d93
MB
2856 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2857 aif2 |= WM8994_AIF1_MONO;
2858
9e6e96a1
MB
2859 if (wm8994->aifclk[id] == 0) {
2860 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2861 return -EINVAL;
2862 }
2863
2864 /* AIFCLK/fs ratio; look for a close match in either direction */
2865 best = 0;
2866 best_val = abs((fs_ratios[0] * params_rate(params))
2867 - wm8994->aifclk[id]);
2868 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2869 cur_val = abs((fs_ratios[i] * params_rate(params))
2870 - wm8994->aifclk[id]);
2871 if (cur_val >= best_val)
2872 continue;
2873 best = i;
2874 best_val = cur_val;
2875 }
2876 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2877 dai->id, fs_ratios[best]);
2878 rate_val |= best;
2879
2880 /* We may not get quite the right frequency if using
2881 * approximate clocks so look for the closest match that is
2882 * higher than the target (we need to ensure that there enough
2883 * BCLKs to clock out the samples).
2884 */
2885 best = 0;
2886 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2887 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB
2888 if (cur_val < 0) /* BCLK table is sorted */
2889 break;
2890 best = i;
2891 }
07cd8ada 2892 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB
2893 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2894 bclk_divs[best], bclk_rate);
2895 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2896
2897 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB
2898 if (!lrclk) {
2899 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2900 bclk_rate);
2901 return -EINVAL;
2902 }
9e6e96a1
MB
2903 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2904 lrclk, bclk_rate / lrclk);
2905
2906 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2907 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB
2908 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2909 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2910 lrclk);
2911 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2912 WM8994_AIF1CLK_RATE_MASK, rate_val);
2913
2914 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2915 switch (dai->id) {
2916 case 1:
2917 wm8994->dac_rates[0] = params_rate(params);
2918 wm8994_set_retune_mobile(codec, 0);
2919 wm8994_set_retune_mobile(codec, 1);
2920 break;
2921 case 2:
2922 wm8994->dac_rates[1] = params_rate(params);
2923 wm8994_set_retune_mobile(codec, 2);
2924 break;
2925 }
2926 }
2927
2928 return 0;
2929}
2930
c4431df0
MB
2931static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2932 struct snd_pcm_hw_params *params,
2933 struct snd_soc_dai *dai)
2934{
2935 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB
2936 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2937 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB
2938 int aif1_reg;
2939 int aif1 = 0;
2940
2941 switch (dai->id) {
2942 case 3:
2943 switch (control->type) {
81204c84 2944 case WM1811:
c4431df0
MB
2945 case WM8958:
2946 aif1_reg = WM8958_AIF3_CONTROL_1;
2947 break;
2948 default:
2949 return 0;
2950 }
4495e46f 2951 break;
c4431df0
MB
2952 default:
2953 return 0;
2954 }
2955
2956 switch (params_format(params)) {
2957 case SNDRV_PCM_FORMAT_S16_LE:
2958 break;
2959 case SNDRV_PCM_FORMAT_S20_3LE:
2960 aif1 |= 0x20;
2961 break;
2962 case SNDRV_PCM_FORMAT_S24_LE:
2963 aif1 |= 0x40;
2964 break;
2965 case SNDRV_PCM_FORMAT_S32_LE:
2966 aif1 |= 0x60;
2967 break;
2968 default:
2969 return -EINVAL;
2970 }
2971
2972 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2973}
2974
9e6e96a1
MB
2975static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2976{
2977 struct snd_soc_codec *codec = codec_dai->codec;
2978 int mute_reg;
2979 int reg;
2980
2981 switch (codec_dai->id) {
2982 case 1:
2983 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2984 break;
2985 case 2:
2986 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2987 break;
2988 default:
2989 return -EINVAL;
2990 }
2991
2992 if (mute)
2993 reg = WM8994_AIF1DAC1_MUTE;
2994 else
2995 reg = 0;
2996
2997 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2998
2999 return 0;
3000}
3001
778a76e2
MB
3002static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3003{
3004 struct snd_soc_codec *codec = codec_dai->codec;
3005 int reg, val, mask;
3006
3007 switch (codec_dai->id) {
3008 case 1:
3009 reg = WM8994_AIF1_MASTER_SLAVE;
3010 mask = WM8994_AIF1_TRI;
3011 break;
3012 case 2:
3013 reg = WM8994_AIF2_MASTER_SLAVE;
3014 mask = WM8994_AIF2_TRI;
3015 break;
778a76e2
MB
3016 default:
3017 return -EINVAL;
3018 }
3019
3020 if (tristate)
3021 val = mask;
3022 else
3023 val = 0;
3024
78b3fb46 3025 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB
3026}
3027
d09f3ecf
MB
3028static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3029{
3030 struct snd_soc_codec *codec = dai->codec;
3031
3032 /* Disable the pulls on the AIF if we're using it to save power. */
3033 snd_soc_update_bits(codec, WM8994_GPIO_3,
3034 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3035 snd_soc_update_bits(codec, WM8994_GPIO_4,
3036 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3037 snd_soc_update_bits(codec, WM8994_GPIO_5,
3038 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3039
3040 return 0;
3041}
3042
9e6e96a1
MB
3043#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3044
3045#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 3046 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 3047
85e7652d 3048static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB
3049 .set_sysclk = wm8994_set_dai_sysclk,
3050 .set_fmt = wm8994_set_dai_fmt,
3051 .hw_params = wm8994_hw_params,
3052 .digital_mute = wm8994_aif_mute,
3053 .set_pll = wm8994_set_fll,
778a76e2 3054 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB
3055};
3056
85e7652d 3057static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB
3058 .set_sysclk = wm8994_set_dai_sysclk,
3059 .set_fmt = wm8994_set_dai_fmt,
3060 .hw_params = wm8994_hw_params,
3061 .digital_mute = wm8994_aif_mute,
3062 .set_pll = wm8994_set_fll,
778a76e2
MB
3063 .set_tristate = wm8994_set_tristate,
3064};
3065
85e7652d 3066static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 3067 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB
3068};
3069
f0fba2ad 3070static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 3071 {
f0fba2ad 3072 .name = "wm8994-aif1",
8c7f78b3 3073 .id = 1,
9e6e96a1
MB
3074 .playback = {
3075 .stream_name = "AIF1 Playback",
b1e43d93 3076 .channels_min = 1,
9e6e96a1
MB
3077 .channels_max = 2,
3078 .rates = WM8994_RATES,
3079 .formats = WM8994_FORMATS,
99b0292d 3080 .sig_bits = 24,
9e6e96a1
MB
3081 },
3082 .capture = {
3083 .stream_name = "AIF1 Capture",
b1e43d93 3084 .channels_min = 1,
9e6e96a1
MB
3085 .channels_max = 2,
3086 .rates = WM8994_RATES,
3087 .formats = WM8994_FORMATS,
99b0292d 3088 .sig_bits = 24,
9e6e96a1
MB
3089 },
3090 .ops = &wm8994_aif1_dai_ops,
3091 },
3092 {
f0fba2ad 3093 .name = "wm8994-aif2",
8c7f78b3 3094 .id = 2,
9e6e96a1
MB
3095 .playback = {
3096 .stream_name = "AIF2 Playback",
b1e43d93 3097 .channels_min = 1,
9e6e96a1
MB
3098 .channels_max = 2,
3099 .rates = WM8994_RATES,
3100 .formats = WM8994_FORMATS,
99b0292d 3101 .sig_bits = 24,
9e6e96a1
MB
3102 },
3103 .capture = {
3104 .stream_name = "AIF2 Capture",
b1e43d93 3105 .channels_min = 1,
9e6e96a1
MB
3106 .channels_max = 2,
3107 .rates = WM8994_RATES,
3108 .formats = WM8994_FORMATS,
99b0292d 3109 .sig_bits = 24,
9e6e96a1 3110 },
d09f3ecf 3111 .probe = wm8994_aif2_probe,
9e6e96a1
MB
3112 .ops = &wm8994_aif2_dai_ops,
3113 },
3114 {
f0fba2ad 3115 .name = "wm8994-aif3",
8c7f78b3 3116 .id = 3,
9e6e96a1
MB
3117 .playback = {
3118 .stream_name = "AIF3 Playback",
b1e43d93 3119 .channels_min = 1,
9e6e96a1
MB
3120 .channels_max = 2,
3121 .rates = WM8994_RATES,
3122 .formats = WM8994_FORMATS,
99b0292d 3123 .sig_bits = 24,
9e6e96a1 3124 },
a8462bde 3125 .capture = {
9e6e96a1 3126 .stream_name = "AIF3 Capture",
b1e43d93 3127 .channels_min = 1,
9e6e96a1
MB
3128 .channels_max = 2,
3129 .rates = WM8994_RATES,
3130 .formats = WM8994_FORMATS,
99b0292d
MB
3131 .sig_bits = 24,
3132 },
778a76e2 3133 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB
3134 }
3135};
9e6e96a1
MB
3136
3137#ifdef CONFIG_PM
4752a887 3138static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3139{
b2c812e2 3140 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB
3141 int i, ret;
3142
3143 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3144 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3145 sizeof(struct wm8994_fll_config));
f0fba2ad 3146 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB
3147 if (ret < 0)
3148 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3149 i + 1, ret);
3150 }
3151
3152 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3153
3154 return 0;
3155}
3156
4752a887 3157static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3158{
b2c812e2 3159 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB
3160 int i, ret;
3161
9e6e96a1 3162 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB
3163 if (!wm8994->fll_suspend[i].out)
3164 continue;
3165
f0fba2ad 3166 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB
3167 wm8994->fll_suspend[i].src,
3168 wm8994->fll_suspend[i].in,
3169 wm8994->fll_suspend[i].out);
3170 if (ret < 0)
3171 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3172 i + 1, ret);
3173 }
3174
3175 return 0;
3176}
3177#else
4752a887
MB
3178#define wm8994_codec_suspend NULL
3179#define wm8994_codec_resume NULL
9e6e96a1
MB
3180#endif
3181
3182static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3183{
8cb8e83b 3184 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB
3185 struct wm8994 *control = wm8994->wm8994;
3186 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB
3187 struct snd_kcontrol_new controls[] = {
3188 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3189 wm8994->retune_mobile_enum,
3190 wm8994_get_retune_mobile_enum,
3191 wm8994_put_retune_mobile_enum),
3192 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3193 wm8994->retune_mobile_enum,
3194 wm8994_get_retune_mobile_enum,
3195 wm8994_put_retune_mobile_enum),
3196 SOC_ENUM_EXT("AIF2 EQ Mode",
3197 wm8994->retune_mobile_enum,
3198 wm8994_get_retune_mobile_enum,
3199 wm8994_put_retune_mobile_enum),
3200 };
3201 int ret, i, j;
3202 const char **t;
3203
3204 /* We need an array of texts for the enum API but the number
3205 * of texts is likely to be less than the number of
3206 * configurations due to the sample rate dependency of the
3207 * configurations. */
3208 wm8994->num_retune_mobile_texts = 0;
3209 wm8994->retune_mobile_texts = NULL;
3210 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3211 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3212 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3213 wm8994->retune_mobile_texts[j]) == 0)
3214 break;
3215 }
3216
3217 if (j != wm8994->num_retune_mobile_texts)
3218 continue;
3219
3220 /* Expand the array... */
3221 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3222 sizeof(char *) *
9e6e96a1
MB
3223 (wm8994->num_retune_mobile_texts + 1),
3224 GFP_KERNEL);
3225 if (t == NULL)
3226 continue;
3227
3228 /* ...store the new entry... */
c1a4ecd9 3229 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB
3230 pdata->retune_mobile_cfgs[i].name;
3231
3232 /* ...and remember the new version. */
3233 wm8994->num_retune_mobile_texts++;
3234 wm8994->retune_mobile_texts = t;
3235 }
3236
3237 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3238 wm8994->num_retune_mobile_texts);
3239
3240 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3241 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3242
8cb8e83b 3243 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB
3244 ARRAY_SIZE(controls));
3245 if (ret != 0)
8cb8e83b 3246 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB
3247 "Failed to add ReTune Mobile controls: %d\n", ret);
3248}
3249
3250static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3251{
8cb8e83b 3252 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB
3253 struct wm8994 *control = wm8994->wm8994;
3254 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB
3255 int ret, i;
3256
3257 if (!pdata)
3258 return;
3259
3260 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3261 pdata->lineout2_diff,
3262 pdata->lineout1fb,
3263 pdata->lineout2fb,
3264 pdata->jd_scthr,
3265 pdata->jd_thr,
02e79476
MB
3266 pdata->micb1_delay,
3267 pdata->micb2_delay,
9e6e96a1
MB
3268 pdata->micbias1_lvl,
3269 pdata->micbias2_lvl);
3270
3271 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3272
3273 if (pdata->num_drc_cfgs) {
3274 struct snd_kcontrol_new controls[] = {
3275 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3276 wm8994_get_drc_enum, wm8994_put_drc_enum),
3277 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3278 wm8994_get_drc_enum, wm8994_put_drc_enum),
3279 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3280 wm8994_get_drc_enum, wm8994_put_drc_enum),
3281 };
3282
3283 /* We need an array of texts for the enum API */
8cb8e83b 3284 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3285 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3286 if (!wm8994->drc_texts) {
8cb8e83b 3287 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB
3288 "Failed to allocate %d DRC config texts\n",
3289 pdata->num_drc_cfgs);
3290 return;
3291 }
3292
3293 for (i = 0; i < pdata->num_drc_cfgs; i++)
3294 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3295
3296 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3297 wm8994->drc_enum.texts = wm8994->drc_texts;
3298
8cb8e83b 3299 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3300 ARRAY_SIZE(controls));
9e6e96a1
MB
3301 for (i = 0; i < WM8994_NUM_DRC; i++)
3302 wm8994_set_drc(codec, i);
45a690f6
MB
3303 } else {
3304 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3305 wm8994_drc_controls,
3306 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB
3307 }
3308
45a690f6
MB
3309 if (ret != 0)
3310 dev_err(wm8994->hubs.codec->dev,
3311 "Failed to add DRC mode controls: %d\n", ret);
3312
3313
9e6e96a1
MB
3314 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3315 pdata->num_retune_mobile_cfgs);
3316
3317 if (pdata->num_retune_mobile_cfgs)
3318 wm8994_handle_retune_mobile_pdata(wm8994);
3319 else
8cb8e83b 3320 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3321 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB
3322
3323 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3324 if (pdata->micbias[i]) {
3325 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3326 pdata->micbias[i] & 0xffff);
3327 }
3328 }
9e6e96a1
MB
3329}
3330
88766984
MB
3331/**
3332 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3333 *
3334 * @codec: WM8994 codec
3335 * @jack: jack to report detection events on
3336 * @micbias: microphone bias to detect on
88766984
MB
3337 *
3338 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3339 * being used to bring out signals to the processor then only platform
5ab230a7 3340 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB
3341 * be configured using snd_soc_jack_add_gpios() instead.
3342 *
3343 * Configuration of detection levels is available via the micbias1_lvl
3344 * and micbias2_lvl platform data members.
3345 */
3346int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3347 int micbias)
88766984 3348{
b2c812e2 3349 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3350 struct wm8994_micdet *micdet;
2a8a856d 3351 struct wm8994 *control = wm8994->wm8994;
87092e3c 3352 int reg, ret;
88766984 3353
87092e3c
MB
3354 if (control->type != WM8994) {
3355 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3356 return -EINVAL;
87092e3c 3357 }
3a423157 3358
88766984
MB
3359 switch (micbias) {
3360 case 1:
3361 micdet = &wm8994->micdet[0];
87092e3c
MB
3362 if (jack)
3363 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3364 "MICBIAS1");
3365 else
3366 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3367 "MICBIAS1");
88766984
MB
3368 break;
3369 case 2:
3370 micdet = &wm8994->micdet[1];
87092e3c
MB
3371 if (jack)
3372 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3373 "MICBIAS1");
3374 else
3375 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3376 "MICBIAS1");
88766984
MB
3377 break;
3378 default:
87092e3c 3379 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3380 return -EINVAL;
87092e3c 3381 }
88766984 3382
87092e3c
MB
3383 if (ret != 0)
3384 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3385 micbias, ret);
3386
3387 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3388 micbias, jack);
88766984
MB
3389
3390 /* Store the configuration */
3391 micdet->jack = jack;
87092e3c 3392 micdet->detecting = true;
88766984
MB
3393
3394 /* If either of the jacks is set up then enable detection */
3395 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3396 reg = WM8994_MICD_ENA;
87092e3c 3397 else
88766984
MB
3398 reg = 0;
3399
3400 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3401
d9f34df7
CR
3402 /* enable MICDET and MICSHRT deboune */
3403 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3404 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3405 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3406 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3407
87092e3c
MB
3408 snd_soc_dapm_sync(&codec->dapm);
3409
88766984
MB
3410 return 0;
3411}
3412EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3413
e9b54de4 3414static void wm8994_mic_work(struct work_struct *work)
88766984 3415{
e9b54de4
MB
3416 struct wm8994_priv *priv = container_of(work,
3417 struct wm8994_priv,
3418 mic_work.work);
fdfc4f3e
MB
3419 struct regmap *regmap = priv->wm8994->regmap;
3420 struct device *dev = priv->wm8994->dev;
3421 unsigned int reg;
3422 int ret;
88766984
MB
3423 int report;
3424
b8176627
MB
3425 pm_runtime_get_sync(dev);
3426
fdfc4f3e
MB
3427 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3428 if (ret < 0) {
3429 dev_err(dev, "Failed to read microphone status: %d\n",
3430 ret);
b8176627 3431 pm_runtime_put(dev);
e9b54de4 3432 return;
88766984
MB
3433 }
3434
fdfc4f3e 3435 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB
3436
3437 report = 0;
87092e3c
MB
3438 if (reg & WM8994_MIC1_DET_STS) {
3439 if (priv->micdet[0].detecting)
3440 report = SND_JACK_HEADSET;
3441 }
3442 if (reg & WM8994_MIC1_SHRT_STS) {
3443 if (priv->micdet[0].detecting)
3444 report = SND_JACK_HEADPHONE;
3445 else
3446 report |= SND_JACK_BTN_0;
3447 }
3448 if (report)
3449 priv->micdet[0].detecting = false;
3450 else
3451 priv->micdet[0].detecting = true;
3452
88766984 3453 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3454 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB
3455
3456 report = 0;
87092e3c
MB
3457 if (reg & WM8994_MIC2_DET_STS) {
3458 if (priv->micdet[1].detecting)
3459 report = SND_JACK_HEADSET;
3460 }
3461 if (reg & WM8994_MIC2_SHRT_STS) {
3462 if (priv->micdet[1].detecting)
3463 report = SND_JACK_HEADPHONE;
3464 else
3465 report |= SND_JACK_BTN_0;
3466 }
3467 if (report)
3468 priv->micdet[1].detecting = false;
3469 else
3470 priv->micdet[1].detecting = true;
3471
88766984 3472 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3473 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB
3474
3475 pm_runtime_put(dev);
e9b54de4
MB
3476}
3477
3478static irqreturn_t wm8994_mic_irq(int irq, void *data)
3479{
3480 struct wm8994_priv *priv = data;
8cb8e83b 3481 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB
3482
3483#ifndef CONFIG_SND_SOC_WM8994_MODULE
3484 trace_snd_soc_jack_irq(dev_name(codec->dev));
3485#endif
3486
3487 pm_wakeup_event(codec->dev, 300);
3488
68defe58
MB
3489 queue_delayed_work(system_power_efficient_wq,
3490 &priv->mic_work, msecs_to_jiffies(250));
88766984
MB
3491
3492 return IRQ_HANDLED;
3493}
3494
f02b0de0
MB
3495static void wm1811_micd_stop(struct snd_soc_codec *codec)
3496{
3497 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3498
3499 if (!wm8994->jackdet)
3500 return;
3501
3502 mutex_lock(&wm8994->accdet_lock);
3503
3504 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3505
3506 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3507
3508 mutex_unlock(&wm8994->accdet_lock);
3509
3510 if (wm8994->wm8994->pdata.jd_ext_cap)
3511 snd_soc_dapm_disable_pin(&codec->dapm,
3512 "MICBIAS2");
3513}
3514
78b76dbe 3515static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3516{
821edd2f 3517 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3518 int report;
821edd2f 3519
78b76dbe
MB
3520 report = 0;
3521 if (status & 0x4)
3522 report |= SND_JACK_BTN_0;
3523
3524 if (status & 0x8)
3525 report |= SND_JACK_BTN_1;
3526
3527 if (status & 0x10)
3528 report |= SND_JACK_BTN_2;
3529
3530 if (status & 0x20)
3531 report |= SND_JACK_BTN_3;
3532
3533 if (status & 0x40)
3534 report |= SND_JACK_BTN_4;
3535
3536 if (status & 0x80)
3537 report |= SND_JACK_BTN_5;
3538
3539 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3540 wm8994->btn_mask);
3541}
3542
70bd3b29
MB
3543static void wm8958_open_circuit_work(struct work_struct *work)
3544{
3545 struct wm8994_priv *wm8994 = container_of(work,
3546 struct wm8994_priv,
3547 open_circuit_work.work);
3548 struct device *dev = wm8994->wm8994->dev;
3549
3550 wm1811_micd_stop(wm8994->hubs.codec);
3551
3552 mutex_lock(&wm8994->accdet_lock);
3553
3554 dev_dbg(dev, "Reporting open circuit\n");
3555
3556 wm8994->jack_mic = false;
3557 wm8994->mic_detecting = true;
3558
3559 wm8958_micd_set_rate(wm8994->hubs.codec);
3560
3561 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3562 wm8994->btn_mask |
3563 SND_JACK_HEADSET);
3564
3565 mutex_unlock(&wm8994->accdet_lock);
3566}
3567
98869f68 3568static void wm8958_mic_id(void *data, u16 status)
78b76dbe 3569{
98869f68 3570 struct snd_soc_codec *codec = data;
78b76dbe 3571 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3572
af6b6fe4 3573 /* Either nothing present or just starting detection */
b00adf76 3574 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB
3575 /* If nothing present then clear our statuses */
3576 dev_dbg(codec->dev, "Detected open circuit\n");
f02b0de0 3577
68defe58
MB
3578 queue_delayed_work(system_power_efficient_wq,
3579 &wm8994->open_circuit_work,
3580 msecs_to_jiffies(2500));
b00adf76
MB
3581 return;
3582 }
821edd2f 3583
b00adf76
MB
3584 /* If the measurement is showing a high impedence we've got a
3585 * microphone.
3586 */
78b76dbe 3587 if (status & 0x600) {
b00adf76
MB
3588 dev_dbg(codec->dev, "Detected microphone\n");
3589
157a75e6 3590 wm8994->mic_detecting = false;
b00adf76
MB
3591 wm8994->jack_mic = true;
3592
3593 wm8958_micd_set_rate(codec);
3594
3595 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3596 SND_JACK_HEADSET);
3597 }
821edd2f 3598
b00adf76 3599
78b76dbe 3600 if (status & 0xfc) {
b00adf76 3601 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3602 wm8994->mic_detecting = false;
b00adf76
MB
3603
3604 wm8958_micd_set_rate(codec);
3605
af6b6fe4 3606 /* If we have jackdet that will detect removal */
f02b0de0 3607 wm1811_micd_stop(codec);
ecd1732f
MB
3608
3609 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3610 SND_JACK_HEADSET);
b00adf76 3611 }
821edd2f 3612}
b00adf76 3613
c0cc3f16
MB
3614/* Deferred mic detection to allow for extra settling time */
3615static void wm1811_mic_work(struct work_struct *work)
3616{
3617 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3618 mic_work.work);
d9dd4ada 3619 struct wm8994 *control = wm8994->wm8994;
c0cc3f16 3620 struct snd_soc_codec *codec = wm8994->hubs.codec;
4585790d 3621
c0cc3f16 3622 pm_runtime_get_sync(codec->dev);
4585790d 3623
c0cc3f16 3624 /* If required for an external cap force MICBIAS on */
d9dd4ada 3625 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB
3626 snd_soc_dapm_force_enable_pin(&codec->dapm,
3627 "MICBIAS2");
3628 snd_soc_dapm_sync(&codec->dapm);
3629 }
4585790d 3630
c0cc3f16 3631 mutex_lock(&wm8994->accdet_lock);
4585790d 3632
c0cc3f16 3633 dev_dbg(codec->dev, "Starting mic detection\n");
4585790d 3634
63dd5452
MB
3635 /* Use a user-supplied callback if we have one */
3636 if (wm8994->micd_cb) {
3637 wm8994->micd_cb(wm8994->micd_cb_data);
3638 } else {
3639 /*
3640 * Start off measument of microphone impedence to find out
3641 * what's actually there.
3642 */
3643 wm8994->mic_detecting = true;
3644 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
4585790d 3645
63dd5452
MB
3646 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3647 WM8958_MICD_ENA, WM8958_MICD_ENA);
b00adf76 3648 }
c0cc3f16
MB
3649
3650 mutex_unlock(&wm8994->accdet_lock);
3651
3652 pm_runtime_put(codec->dev);
821edd2f
MB
3653}
3654
af6b6fe4
MB
3655static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3656{
3657 struct wm8994_priv *wm8994 = data;
d9dd4ada 3658 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3659 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3660 int reg, delay;
c986564b 3661 bool present;
af6b6fe4 3662
b8176627
MB
3663 pm_runtime_get_sync(codec->dev);
3664
2da1c4bf
MB
3665 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3666
af6b6fe4
MB
3667 mutex_lock(&wm8994->accdet_lock);
3668
3669 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3670 if (reg < 0) {
3671 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3672 mutex_unlock(&wm8994->accdet_lock);
b8176627 3673 pm_runtime_put(codec->dev);
af6b6fe4
MB
3674 return IRQ_NONE;
3675 }
3676
3677 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3678
c986564b 3679 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3680
c986564b
MB
3681 if (present) {
3682 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3683
e9d9a968
MB
3684 wm8958_micd_set_rate(codec);
3685
55a27786
MB
3686 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3687 WM8958_MICB2_DISCH, 0);
3688
378ec0ca
MB
3689 /* Disable debounce while inserted */
3690 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3691 WM1811_JACKDET_DB, 0);
3692
d9dd4ada 3693 delay = control->pdata.micdet_delay;
68defe58
MB
3694 queue_delayed_work(system_power_efficient_wq,
3695 &wm8994->mic_work,
3696 msecs_to_jiffies(delay));
af6b6fe4
MB
3697 } else {
3698 dev_dbg(codec->dev, "Jack not detected\n");
3699
c0cc3f16
MB
3700 cancel_delayed_work_sync(&wm8994->mic_work);
3701
55a27786
MB
3702 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3703 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3704
378ec0ca
MB
3705 /* Enable debounce while removed */
3706 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3707 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3708
af6b6fe4
MB
3709 wm8994->mic_detecting = false;
3710 wm8994->jack_mic = false;
3711 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3712 WM8958_MICD_ENA, 0);
3713 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3714 }
3715
3716 mutex_unlock(&wm8994->accdet_lock);
3717
c0cc3f16 3718 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3719 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3720 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB
3721
3722 if (present)
3723 snd_soc_jack_report(wm8994->micdet[0].jack,
3724 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3725 else
3726 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3727 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3728 wm8994->btn_mask);
3729
99af79df
MB
3730 /* Since we only report deltas force an update, ensures we
3731 * avoid bootstrapping issues with the core. */
3732 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3733
b8176627 3734 pm_runtime_put(codec->dev);
af6b6fe4
MB
3735 return IRQ_HANDLED;
3736}
3737
99af79df
MB
3738static void wm1811_jackdet_bootstrap(struct work_struct *work)
3739{
3740 struct wm8994_priv *wm8994 = container_of(work,
3741 struct wm8994_priv,
3742 jackdet_bootstrap.work);
3743 wm1811_jackdet_irq(0, wm8994);
3744}
3745
821edd2f
MB
3746/**
3747 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3748 *
3749 * @codec: WM8958 codec
3750 * @jack: jack to report detection events on
3751 *
3752 * Enable microphone detection functionality for the WM8958. By
3753 * default simple detection which supports the detection of up to 6
3754 * buttons plus video and microphone functionality is supported.
3755 *
3756 * The WM8958 has an advanced jack detection facility which is able to
3757 * support complex accessory detection, especially when used in
3758 * conjunction with external circuitry. In order to provide maximum
3759 * flexiblity a callback is provided which allows a completely custom
3760 * detection algorithm.
3761 */
3762int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
98869f68
MB
3763 wm1811_micdet_cb det_cb, void *det_cb_data,
3764 wm1811_mic_id_cb id_cb, void *id_cb_data)
821edd2f
MB
3765{
3766 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3767 struct wm8994 *control = wm8994->wm8994;
4585790d 3768 u16 micd_lvl_sel;
821edd2f 3769
81204c84
MB
3770 switch (control->type) {
3771 case WM1811:
3772 case WM8958:
3773 break;
3774 default:
821edd2f 3775 return -EINVAL;
81204c84 3776 }
821edd2f
MB
3777
3778 if (jack) {
4cdf5e49 3779 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3780 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3781
821edd2f 3782 wm8994->micdet[0].jack = jack;
821edd2f 3783
98869f68
MB
3784 if (det_cb) {
3785 wm8994->micd_cb = det_cb;
3786 wm8994->micd_cb_data = det_cb_data;
63dd5452
MB
3787 } else {
3788 wm8994->mic_detecting = true;
3789 wm8994->jack_mic = false;
3790 }
b00adf76 3791
98869f68
MB
3792 if (id_cb) {
3793 wm8994->mic_id_cb = id_cb;
3794 wm8994->mic_id_cb_data = id_cb_data;
3795 } else {
3796 wm8994->mic_id_cb = wm8958_mic_id;
3797 wm8994->mic_id_cb_data = codec;
3798 }
b00adf76
MB
3799
3800 wm8958_micd_set_rate(codec);
3801
4585790d 3802 /* Detect microphones and short circuits by default */
d9dd4ada
MB
3803 if (control->pdata.micd_lvl_sel)
3804 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB
3805 else
3806 micd_lvl_sel = 0x41;
3807
3808 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3809 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3810 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3811
b00adf76 3812 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3813 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3814
af6b6fe4
MB
3815 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3816
3817 /*
3818 * If we can use jack detection start off with that,
3819 * otherwise jump straight to microphone detection.
3820 */
3821 if (wm8994->jackdet) {
99af79df
MB
3822 /* Disable debounce for the initial detect */
3823 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3824 WM1811_JACKDET_DB, 0);
3825
55a27786
MB
3826 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3827 WM8958_MICB2_DISCH,
3828 WM8958_MICB2_DISCH);
af6b6fe4
MB
3829 snd_soc_update_bits(codec, WM8994_LDO_1,
3830 WM8994_LDO1_DISCH, 0);
3831 wm1811_jackdet_set_mode(codec,
3832 WM1811_JACKDET_MODE_JACK);
3833 } else {
3834 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3835 WM8958_MICD_ENA, WM8958_MICD_ENA);
3836 }
3837
821edd2f
MB
3838 } else {
3839 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3840 WM8958_MICD_ENA, 0);
afaf1591 3841 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3842 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3843 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB
3844 }
3845
3846 return 0;
3847}
3848EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3849
2da1c4bf
MB
3850static void wm8958_mic_work(struct work_struct *work)
3851{
3852 struct wm8994_priv *wm8994 = container_of(work,
3853 struct wm8994_priv,
3854 mic_complete_work.work);
3855 struct snd_soc_codec *codec = wm8994->hubs.codec;
3856
2da1c4bf
MB
3857 pm_runtime_get_sync(codec->dev);
3858
3859 mutex_lock(&wm8994->accdet_lock);
3860
3861 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3862
3863 mutex_unlock(&wm8994->accdet_lock);
3864
3865 pm_runtime_put(codec->dev);
2da1c4bf
MB
3866}
3867
821edd2f
MB
3868static irqreturn_t wm8958_mic_irq(int irq, void *data)
3869{
3870 struct wm8994_priv *wm8994 = data;
8cb8e83b 3871 struct snd_soc_codec *codec = wm8994->hubs.codec;
2da1c4bf 3872 int reg, count, ret, id_delay;
821edd2f 3873
af6b6fe4
MB
3874 /*
3875 * Jack detection may have detected a removal simulataneously
3876 * with an update of the MICDET status; if so it will have
3877 * stopped detection and we can ignore this interrupt.
3878 */
c986564b 3879 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3880 return IRQ_HANDLED;
af6b6fe4 3881
2da1c4bf 3882 cancel_delayed_work_sync(&wm8994->mic_complete_work);
70bd3b29
MB
3883 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3884
b8176627
MB
3885 pm_runtime_get_sync(codec->dev);
3886
19940b3d
MB
3887 /* We may occasionally read a detection without an impedence
3888 * range being provided - if that happens loop again.
3889 */
3890 count = 10;
3891 do {
3892 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3893 if (reg < 0) {
3894 dev_err(codec->dev,
3895 "Failed to read mic detect status: %d\n",
3896 reg);
b8176627 3897 pm_runtime_put(codec->dev);
19940b3d
MB
3898 return IRQ_NONE;
3899 }
821edd2f 3900
19940b3d
MB
3901 if (!(reg & WM8958_MICD_VALID)) {
3902 dev_dbg(codec->dev, "Mic detect data not valid\n");
3903 goto out;
3904 }
3905
3906 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3907 break;
3908
3909 msleep(1);
3910 } while (count--);
3911
3912 if (count == 0)
ec8f53fb 3913 dev_warn(codec->dev, "No impedance range reported for jack\n");
821edd2f 3914
7116f452 3915#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3916 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3917#endif
2bbb5d66 3918
e874de43
MB
3919 /* Avoid a transient report when the accessory is being removed */
3920 if (wm8994->jackdet) {
8afd0ef2
MB
3921 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3922 if (ret < 0) {
e874de43 3923 dev_err(codec->dev, "Failed to read jack status: %d\n",
8afd0ef2
MB
3924 ret);
3925 } else if (!(ret & WM1811_JACKDET_LVL)) {
e874de43 3926 dev_dbg(codec->dev, "Ignoring removed jack\n");
9e43088b 3927 goto out;
e874de43 3928 }
9767a58b
MB
3929 } else if (!(reg & WM8958_MICD_STS)) {
3930 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3931 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3932 wm8994->btn_mask);
7afce3f5 3933 wm8994->mic_detecting = true;
9767a58b 3934 goto out;
e874de43
MB
3935 }
3936
2da1c4bf
MB
3937 wm8994->mic_status = reg;
3938 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3939
78b76dbe 3940 if (wm8994->mic_detecting)
68defe58
MB
3941 queue_delayed_work(system_power_efficient_wq,
3942 &wm8994->mic_complete_work,
3943 msecs_to_jiffies(id_delay));
821edd2f 3944 else
78b76dbe 3945 wm8958_button_det(codec, reg);
821edd2f
MB
3946
3947out:
b8176627 3948 pm_runtime_put(codec->dev);
821edd2f
MB
3949 return IRQ_HANDLED;
3950}
3951
3b1af3f8
MB
3952static irqreturn_t wm8994_fifo_error(int irq, void *data)
3953{
3954 struct snd_soc_codec *codec = data;
3955
3956 dev_err(codec->dev, "FIFO error\n");
3957
3958 return IRQ_HANDLED;
3959}
3960
f0b182b0
MB
3961static irqreturn_t wm8994_temp_warn(int irq, void *data)
3962{
3963 struct snd_soc_codec *codec = data;
3964
3965 dev_err(codec->dev, "Thermal warning\n");
3966
3967 return IRQ_HANDLED;
3968}
3969
3970static irqreturn_t wm8994_temp_shut(int irq, void *data)
3971{
3972 struct snd_soc_codec *codec = data;
3973
3974 dev_crit(codec->dev, "Thermal shutdown\n");
3975
3976 return IRQ_HANDLED;
3977}
3978
f0fba2ad 3979static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3980{
d9a7666f 3981 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3982 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3983 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3984 unsigned int reg;
ec62dbd7 3985 int ret, i;
9e6e96a1 3986
8cb8e83b 3987 wm8994->hubs.codec = codec;
d9a7666f 3988 codec->control_data = control->regmap;
9e6e96a1 3989
d9a7666f 3990 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3991
af6b6fe4 3992 mutex_init(&wm8994->accdet_lock);
99af79df
MB
3993 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3994 wm1811_jackdet_bootstrap);
70bd3b29
MB
3995 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
3996 wm8958_open_circuit_work);
af6b6fe4 3997
c0cc3f16
MB
3998 switch (control->type) {
3999 case WM8994:
4000 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4001 break;
4002 case WM1811:
4003 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4004 break;
4005 default:
4006 break;
4007 }
4008
2da1c4bf
MB
4009 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4010
c7ebf932
MB
4011 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4012 init_completion(&wm8994->fll_locked[i]);
4013
d9dd4ada 4014 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 4015
f959dee9
MB
4016 /* By default use idle_bias_off, will override for WM8994 */
4017 codec->dapm.idle_bias_off = 1;
4018
9e6e96a1 4019 /* Set revision-specific configuration */
3a423157
MB
4020 switch (control->type) {
4021 case WM8994:
f959dee9 4022 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB
4023 if (!control->pdata.lineout1_diff ||
4024 !control->pdata.lineout2_diff)
f959dee9
MB
4025 codec->dapm.idle_bias_off = 0;
4026
da445afe 4027 switch (control->revision) {
3a423157
MB
4028 case 2:
4029 case 3:
4537c4e7
MB
4030 wm8994->hubs.dcs_codes_l = -5;
4031 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB
4032 wm8994->hubs.hp_startup_mode = 1;
4033 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 4034 wm8994->hubs.series_startup = 1;
3a423157
MB
4035 break;
4036 default:
79ef0abc 4037 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB
4038 break;
4039 }
280ec8b7 4040 break;
3a423157
MB
4041
4042 case WM8958:
8437f700 4043 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 4044 wm8994->hubs.hp_startup_mode = 1;
20dc24a9 4045
da445afe 4046 switch (control->revision) {
20dc24a9
MB
4047 case 0:
4048 break;
4049 default:
4050 wm8994->fll_byp = true;
4051 break;
4052 }
9e6e96a1 4053 break;
3a423157 4054
81204c84
MB
4055 case WM1811:
4056 wm8994->hubs.dcs_readback_mode = 2;
4057 wm8994->hubs.no_series_update = 1;
29fdc360 4058 wm8994->hubs.hp_startup_mode = 1;
af31a227 4059 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 4060 wm8994->fll_byp = true;
81204c84 4061
72222be3
MB
4062 wm8994->hubs.dcs_codes_l = -9;
4063 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB
4064
4065 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4066 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4067 break;
4068
9e6e96a1
MB
4069 default:
4070 break;
4071 }
9e6e96a1 4072
2a8a856d 4073 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 4074 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 4075 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 4076 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 4077 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 4078 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 4079
3a423157
MB
4080 switch (control->type) {
4081 case WM8994:
9b7c525d
MB
4082 if (wm8994->micdet_irq) {
4083 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4084 wm8994_mic_irq,
4085 IRQF_TRIGGER_RISING,
4086 "Mic1 detect",
4087 wm8994);
4088 if (ret != 0)
4089 dev_warn(codec->dev,
4090 "Failed to request Mic1 detect IRQ: %d\n",
4091 ret);
4092 }
3a423157 4093
2a8a856d 4094 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB
4095 WM8994_IRQ_MIC1_SHRT,
4096 wm8994_mic_irq, "Mic 1 short",
4097 wm8994);
4098 if (ret != 0)
4099 dev_warn(codec->dev,
4100 "Failed to request Mic1 short IRQ: %d\n",
4101 ret);
4102
2a8a856d 4103 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB
4104 WM8994_IRQ_MIC2_DET,
4105 wm8994_mic_irq, "Mic 2 detect",
4106 wm8994);
4107 if (ret != 0)
4108 dev_warn(codec->dev,
4109 "Failed to request Mic2 detect IRQ: %d\n",
4110 ret);
4111
2a8a856d 4112 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB
4113 WM8994_IRQ_MIC2_SHRT,
4114 wm8994_mic_irq, "Mic 2 short",
4115 wm8994);
4116 if (ret != 0)
4117 dev_warn(codec->dev,
4118 "Failed to request Mic2 short IRQ: %d\n",
4119 ret);
4120 break;
821edd2f
MB
4121
4122 case WM8958:
81204c84 4123 case WM1811:
9b7c525d
MB
4124 if (wm8994->micdet_irq) {
4125 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4126 wm8958_mic_irq,
4127 IRQF_TRIGGER_RISING,
4128 "Mic detect",
4129 wm8994);
4130 if (ret != 0)
4131 dev_warn(codec->dev,
4132 "Failed to request Mic detect IRQ: %d\n",
4133 ret);
b4046d01
MB
4134 } else {
4135 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4136 wm8958_mic_irq, "Mic detect",
4137 wm8994);
9b7c525d 4138 }
3a423157 4139 }
88766984 4140
af6b6fe4
MB
4141 switch (control->type) {
4142 case WM1811:
da445afe 4143 if (control->cust_id > 1 || control->revision > 1) {
af6b6fe4
MB
4144 ret = wm8994_request_irq(wm8994->wm8994,
4145 WM8994_IRQ_GPIO(6),
4146 wm1811_jackdet_irq, "JACKDET",
4147 wm8994);
4148 if (ret == 0)
4149 wm8994->jackdet = true;
4150 }
4151 break;
4152 default:
4153 break;
4154 }
4155
c7ebf932
MB
4156 wm8994->fll_locked_irq = true;
4157 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 4158 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB
4159 WM8994_IRQ_FLL1_LOCK + i,
4160 wm8994_fll_locked_irq, "FLL lock",
4161 &wm8994->fll_locked[i]);
4162 if (ret != 0)
4163 wm8994->fll_locked_irq = false;
4164 }
4165
27060b3c
MB
4166 /* Make sure we can read from the GPIOs if they're inputs */
4167 pm_runtime_get_sync(codec->dev);
4168
9e6e96a1
MB
4169 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4170 * configured on init - if a system wants to do this dynamically
4171 * at runtime we can deal with that then.
4172 */
d9a7666f 4173 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB
4174 if (ret < 0) {
4175 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4176 goto err_irq;
9e6e96a1 4177 }
d9a7666f 4178 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB
4179 wm8994->lrclk_shared[0] = 1;
4180 wm8994_dai[0].symmetric_rates = 1;
4181 } else {
4182 wm8994->lrclk_shared[0] = 0;
4183 }
4184
d9a7666f 4185 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB
4186 if (ret < 0) {
4187 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4188 goto err_irq;
9e6e96a1 4189 }
d9a7666f 4190 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB
4191 wm8994->lrclk_shared[1] = 1;
4192 wm8994_dai[1].symmetric_rates = 1;
4193 } else {
4194 wm8994->lrclk_shared[1] = 0;
4195 }
4196
27060b3c
MB
4197 pm_runtime_put(codec->dev);
4198
bfd37bb5
MB
4199 /* Latch volume update bits */
4200 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4201 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4202 wm8994_vu_bits[i].mask,
4203 wm8994_vu_bits[i].mask);
9e6e96a1
MB
4204
4205 /* Set the low bit of the 3D stereo depth so TLV matches */
4206 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4207 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4208 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4209 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4210 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4211 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4212 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4213 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4214 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4215
5b739670
MB
4216 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4217 * use this; it only affects behaviour on idle TDM clock
4218 * cycles. */
4219 switch (control->type) {
4220 case WM8994:
4221 case WM8958:
4222 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4223 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4224 break;
4225 default:
4226 break;
4227 }
d1ce6b20 4228
500fa30e
MB
4229 /* Put MICBIAS into bypass mode by default on newer devices */
4230 switch (control->type) {
4231 case WM8958:
4232 case WM1811:
4233 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4234 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4235 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4236 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4237 break;
4238 default:
4239 break;
4240 }
4241
c340304d
MB
4242 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4243 wm_hubs_update_class_w(codec);
9e6e96a1 4244
f0fba2ad 4245 wm8994_handle_pdata(wm8994);
9e6e96a1 4246
f0fba2ad 4247 wm_hubs_add_analogue_controls(codec);
022658be 4248 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4249 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4250 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4251 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB
4252
4253 switch (control->type) {
4254 case WM8994:
4255 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4256 ARRAY_SIZE(wm8994_specific_dapm_widgets));
da445afe 4257 if (control->revision < 4) {
173efa09
DP
4258 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4259 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP
4260 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4261 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP
4262 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4263 ARRAY_SIZE(wm8994_dac_revd_widgets));
4264 } else {
173efa09
DP
4265 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4266 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP
4267 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4268 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP
4269 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4270 ARRAY_SIZE(wm8994_dac_widgets));
4271 }
c4431df0
MB
4272 break;
4273 case WM8958:
022658be 4274 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB
4275 ARRAY_SIZE(wm8958_snd_controls));
4276 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4277 ARRAY_SIZE(wm8958_dapm_widgets));
da445afe 4278 if (control->revision < 1) {
780e2806
MB
4279 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4280 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4281 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4282 ARRAY_SIZE(wm8994_adc_revd_widgets));
4283 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4284 ARRAY_SIZE(wm8994_dac_revd_widgets));
4285 } else {
4286 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4287 ARRAY_SIZE(wm8994_lateclk_widgets));
4288 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4289 ARRAY_SIZE(wm8994_adc_widgets));
4290 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4291 ARRAY_SIZE(wm8994_dac_widgets));
4292 }
c4431df0 4293 break;
81204c84
MB
4294
4295 case WM1811:
022658be 4296 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB
4297 ARRAY_SIZE(wm8958_snd_controls));
4298 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4299 ARRAY_SIZE(wm8958_dapm_widgets));
4300 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4301 ARRAY_SIZE(wm8994_lateclk_widgets));
4302 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4303 ARRAY_SIZE(wm8994_adc_widgets));
4304 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4305 ARRAY_SIZE(wm8994_dac_widgets));
4306 break;
c4431df0 4307 }
c4431df0 4308
f0fba2ad 4309 wm_hubs_add_analogue_routes(codec, 0, 0);
b888edbc 4310 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4311 wm_hubs_dcs_done, "DC servo done",
4312 &wm8994->hubs);
4313 if (ret == 0)
4314 wm8994->hubs.dcs_done_irq = true;
ce6120cc 4315 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4316
c4431df0
MB
4317 switch (control->type) {
4318 case WM8994:
4319 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4320 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4321
da445afe 4322 if (control->revision < 4) {
6ed8f148
MB
4323 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4324 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP
4325 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4326 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4327 } else {
4328 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4329 ARRAY_SIZE(wm8994_lateclk_intercon));
4330 }
c4431df0
MB
4331 break;
4332 case WM8958:
da445afe 4333 if (control->revision < 1) {
15676937
CR
4334 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4335 ARRAY_SIZE(wm8994_intercon));
780e2806
MB
4336 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4337 ARRAY_SIZE(wm8994_revd_intercon));
4338 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4339 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4340 } else {
4341 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4342 ARRAY_SIZE(wm8994_lateclk_intercon));
4343 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4344 ARRAY_SIZE(wm8958_intercon));
4345 }
f701a2e5
MB
4346
4347 wm8958_dsp2_init(codec);
c4431df0 4348 break;
81204c84
MB
4349 case WM1811:
4350 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4351 ARRAY_SIZE(wm8994_lateclk_intercon));
4352 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4353 ARRAY_SIZE(wm8958_intercon));
4354 break;
c4431df0
MB
4355 }
4356
9e6e96a1
MB
4357 return 0;
4358
88766984 4359err_irq:
af6b6fe4
MB
4360 if (wm8994->jackdet)
4361 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB
4362 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4363 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4364 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB
4365 if (wm8994->micdet_irq)
4366 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4367 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4368 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4369 &wm8994->fll_locked[i]);
2a8a856d 4370 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4371 &wm8994->hubs);
2a8a856d
MB
4372 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4374 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4375
9e6e96a1
MB
4376 return ret;
4377}
4378
34ff0f95 4379static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4380{
f0fba2ad 4381 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4382 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4383 int i;
9e6e96a1
MB
4384
4385 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4386
c7ebf932 4387 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4388 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB
4389 &wm8994->fll_locked[i]);
4390
2a8a856d 4391 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4392 &wm8994->hubs);
2a8a856d
MB
4393 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4394 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4395 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4396
af6b6fe4
MB
4397 if (wm8994->jackdet)
4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4399
3a423157
MB
4400 switch (control->type) {
4401 case WM8994:
9b7c525d
MB
4402 if (wm8994->micdet_irq)
4403 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4405 wm8994);
2a8a856d 4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4407 wm8994);
2a8a856d 4408 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB
4409 wm8994);
4410 break;
821edd2f 4411
81204c84 4412 case WM1811:
821edd2f 4413 case WM8958:
9b7c525d
MB
4414 if (wm8994->micdet_irq)
4415 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4416 break;
3a423157 4417 }
34ff0f95
JJ
4418 release_firmware(wm8994->mbc);
4419 release_firmware(wm8994->mbc_vss);
4420 release_firmware(wm8994->enh_eq);
24fb2b11 4421 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB
4422 return 0;
4423}
4424
f0fba2ad
LG
4425static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4426 .probe = wm8994_codec_probe,
4427 .remove = wm8994_codec_remove,
4752a887
MB
4428 .suspend = wm8994_codec_suspend,
4429 .resume = wm8994_codec_resume,
f0fba2ad
LG
4430 .set_bias_level = wm8994_set_bias_level,
4431};
4432
7a79e94e 4433static int wm8994_probe(struct platform_device *pdev)
f0fba2ad 4434{
2bc16ed8
MB
4435 struct wm8994_priv *wm8994;
4436
4437 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4438 GFP_KERNEL);
4439 if (wm8994 == NULL)
4440 return -ENOMEM;
4441 platform_set_drvdata(pdev, wm8994);
4442
4443 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4444
57e265c8
MB
4445 pm_runtime_enable(&pdev->dev);
4446 pm_runtime_idle(&pdev->dev);
4447
f0fba2ad
LG
4448 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4449 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4450}
4451
7a79e94e 4452static int wm8994_remove(struct platform_device *pdev)
f0fba2ad
LG
4453{
4454 snd_soc_unregister_codec(&pdev->dev);
57e265c8
MB
4455 pm_runtime_disable(&pdev->dev);
4456
f0fba2ad
LG
4457 return 0;
4458}
4459
4752a887
MB
4460#ifdef CONFIG_PM_SLEEP
4461static int wm8994_suspend(struct device *dev)
4462{
4463 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4464
4465 /* Drop down to power saving mode when system is suspended */
4466 if (wm8994->jackdet && !wm8994->active_refcount)
4467 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4468 WM1811_JACKDET_MODE_MASK,
4469 wm8994->jackdet_mode);
4470
4471 return 0;
4472}
4473
4474static int wm8994_resume(struct device *dev)
4475{
4476 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4477
78b76dbe 4478 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB
4479 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4480 WM1811_JACKDET_MODE_MASK,
4481 WM1811_JACKDET_MODE_AUDIO);
4482
4483 return 0;
4484}
4485#endif
4486
4487static const struct dev_pm_ops wm8994_pm_ops = {
4488 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4489};
4490
9e6e96a1
MB
4491static struct platform_driver wm8994_codec_driver = {
4492 .driver = {
4752a887
MB
4493 .name = "wm8994-codec",
4494 .owner = THIS_MODULE,
4495 .pm = &wm8994_pm_ops,
4496 },
f0fba2ad 4497 .probe = wm8994_probe,
7a79e94e 4498 .remove = wm8994_remove,
9e6e96a1
MB
4499};
4500
5bbcc3c0 4501module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB
4502
4503MODULE_DESCRIPTION("ASoC WM8994 driver");
4504MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4505MODULE_LICENSE("GPL");
4506MODULE_ALIAS("platform:wm8994-codec");
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