projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: wm8994: Allow debounce before MICDET identification
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
d1a0a299 19#include <linux/gcd.h>
9e6e96a1
MB		 20#include <linux/i2c.h>
21#include <linux/platform_device.h>
39fb51a1 22#include <linux/pm_runtime.h>
9e6e96a1 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
9e6e96a1 25#include <sound/core.h>
821edd2f 26#include <sound/jack.h>
9e6e96a1
MB		 27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
9e6e96a1
MB		 30#include <sound/initval.h>
31#include <sound/tlv.h>
2bbb5d66 32#include <trace/events/asoc.h>
9e6e96a1
MB		 33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
af6b6fe4
MB		 42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
9e6e96a1
MB		 47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
bfd37bb5
MB		 50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
9e6e96a1
MB		 83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
af6b6fe4 95static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
604533de
MB		 98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 100};
101
af6b6fe4
MB		 102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
e9d9a968
MB		 105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 107};
108
b00adf76
MB		 109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 112 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 113 int best, i, sysclk, val;
114 bool idle;
af6b6fe4
MB		 115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
b00adf76
MB		 118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
d9dd4ada
MB		 126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
cd1707a9 129 } else if (wm8994->jackdet) {
af6b6fe4
MB		 130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
b00adf76 137 best = 0;
af6b6fe4
MB		 138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
b00adf76 140 continue;
af6b6fe4
MB		 141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
b00adf76 143 best = i;
af6b6fe4 144 else if (rates[best].idle != idle)
b00adf76
MB		 145 best = i;
146 }
147
af6b6fe4
MB		 148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 150
3a334ada
MB		 151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
b00adf76
MB		 155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
9e6e96a1
MB		 160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
b2c812e2 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
5e5e2bef 203
9e6e96a1
MB		 204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
b2c812e2 215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 216 int change, new;
9e6e96a1
MB		 217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
9e6e96a1 231 return 0;
b00adf76 232 }
9e6e96a1
MB		 233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
04f45c49
AL		 239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 243
b00adf76
MB		 244 wm8958_micd_set_rate(codec);
245
9e6e96a1
MB		 246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262}
263
264static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266};
267
268static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270
146fd574
UK		 271static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273};
274
275static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277
278static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280
281static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283
9e6e96a1
MB		 284static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 289static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 290static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 291
292#define WM8994_DRC_SWITCH(xname, reg, shift) \
293{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
294 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
295 .put = wm8994_put_drc_sw, \
296 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
297
298static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
299 struct snd_ctl_elem_value *ucontrol)
300{
301 struct soc_mixer_control *mc =
302 (struct soc_mixer_control *)kcontrol->private_value;
303 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
304 int mask, ret;
305
306 /* Can't enable both ADC and DAC paths simultaneously */
307 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
308 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
309 WM8994_AIF1ADC1R_DRC_ENA_MASK;
310 else
311 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
312
313 ret = snd_soc_read(codec, mc->reg);
314 if (ret < 0)
315 return ret;
316 if (ret & mask)
317 return -EINVAL;
318
319 return snd_soc_put_volsw(kcontrol, ucontrol);
320}
321
9e6e96a1
MB		 322static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
323{
b2c812e2 324 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 325 struct wm8994 *control = wm8994->wm8994;
326 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 327 int base = wm8994_drc_base[drc];
328 int cfg = wm8994->drc_cfg[drc];
329 int save, i;
330
331 /* Save any enables; the configuration should clear them. */
332 save = snd_soc_read(codec, base);
333 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA;
335
336 for (i = 0; i < WM8994_DRC_REGS; i++)
337 snd_soc_update_bits(codec, base + i, 0xffff,
338 pdata->drc_cfgs[cfg].regs[i]);
339
340 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
341 WM8994_AIF1ADC1L_DRC_ENA |
342 WM8994_AIF1ADC1R_DRC_ENA, save);
343}
344
345/* Icky as hell but saves code duplication */
346static int wm8994_get_drc(const char *name)
347{
348 if (strcmp(name, "AIF1DRC1 Mode") == 0)
349 return 0;
350 if (strcmp(name, "AIF1DRC2 Mode") == 0)
351 return 1;
352 if (strcmp(name, "AIF2DRC Mode") == 0)
353 return 2;
354 return -EINVAL;
355}
356
357static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
358 struct snd_ctl_elem_value *ucontrol)
359{
360 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 361 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 362 struct wm8994 *control = wm8994->wm8994;
363 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.integer.value[0];
366
367 if (drc < 0)
368 return drc;
369
370 if (value >= pdata->num_drc_cfgs)
371 return -EINVAL;
372
373 wm8994->drc_cfg[drc] = value;
374
375 wm8994_set_drc(codec, drc);
376
377 return 0;
378}
379
380static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382{
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 385 int drc = wm8994_get_drc(kcontrol->id.name);
386
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 438 * current configuration.
9e6e96a1
MB		 439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448}
449
450/* Icky as hell but saves code duplication */
451static int wm8994_get_retune_mobile_block(const char *name)
452{
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460}
461
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495}
496
96b101ef 497static const char *aif_chan_src_text[] = {
f554885f
MB		 498 "Left", "Right"
499};
500
96b101ef
MB		 501static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
f554885f 513static const struct soc_enum aif1dacl_src =
96b101ef 514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 515
516static const struct soc_enum aif1dacr_src =
96b101ef 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 518
519static const struct soc_enum aif2dacl_src =
96b101ef 520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 521
522static const struct soc_enum aif2dacr_src =
96b101ef 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 524
154b26aa
MB		 525static const char *osr_text[] = {
526 "Low Power", "High Performance",
527};
528
529static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
9e6e96a1
MB		 535static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
96b101ef
MB		 546SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 548SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 550
f554885f
MB		 551SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 553SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 555
9e6e96a1
MB		 556SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
146fd574
UK		 593SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
154b26aa
MB		 602SOC_ENUM("ADC OSR", adc_osr),
603SOC_ENUM("DAC OSR", dac_osr),
604
9e6e96a1
MB		 605SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
458350b3 627SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 628 8, 1, 0),
629SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
458350b3 633SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 634 10, 15, 0, wm8994_3d_tlv),
458350b3 635SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 636 8, 1, 0),
637};
638
639static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672};
673
45a690f6
MB		 674static const struct snd_kcontrol_new wm8994_drc_controls[] = {
675SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
676 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
677 WM8994_AIF1ADC1R_DRC_ENA),
678SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
679 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
680 WM8994_AIF1ADC2R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
682 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
683 WM8994_AIF2ADCR_DRC_ENA),
684};
685
1ddc07d0
MB		 686static const char *wm8958_ng_text[] = {
687 "30ms", "125ms", "250ms", "500ms",
688};
689
690static const struct soc_enum wm8958_aif1dac1_ng_hold =
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
692 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
693
694static const struct soc_enum wm8958_aif1dac2_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
696 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698static const struct soc_enum wm8958_aif2dac_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
700 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
701
c4431df0
MB		 702static const struct snd_kcontrol_new wm8958_snd_controls[] = {
703SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 704
705SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
707SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
708SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
710 7, 1, ng_tlv),
711
712SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
714SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
715SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
720 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
721SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
722SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
724 7, 1, ng_tlv),
c4431df0
MB		 725};
726
81204c84
MB		 727static const struct snd_kcontrol_new wm1811_snd_controls[] = {
728SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
729 mixin_boost_tlv),
730SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
731 mixin_boost_tlv),
732};
733
af6b6fe4
MB		 734/* We run all mode setting through a function to enforce audio mode */
735static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
736{
737 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
738
78b76dbe 739 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
MB		 740 return;
741
af6b6fe4
MB		 742 if (wm8994->active_refcount)
743 mode = WM1811_JACKDET_MODE_AUDIO;
744
4752a887 745 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 746 return;
747
4752a887 748 wm8994->jackdet_mode = mode;
1defde2a 749
4752a887
MB		 750 /* Always use audio mode to detect while the system is active */
751 if (mode != WM1811_JACKDET_MODE_NONE)
752 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 753
4752a887
MB		 754 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
755 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 756}
757
758static void active_reference(struct snd_soc_codec *codec)
759{
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762 mutex_lock(&wm8994->accdet_lock);
763
764 wm8994->active_refcount++;
765
766 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
767 wm8994->active_refcount);
768
1defde2a
MB		 769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 771
772 mutex_unlock(&wm8994->accdet_lock);
773}
774
775static void active_dereference(struct snd_soc_codec *codec)
776{
777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778 u16 mode;
779
780 mutex_lock(&wm8994->accdet_lock);
781
782 wm8994->active_refcount--;
783
784 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
785 wm8994->active_refcount);
786
787 if (wm8994->active_refcount == 0) {
788 /* Go into appropriate detection only mode */
1defde2a
MB		 789 if (wm8994->jack_mic || wm8994->mic_detecting)
790 mode = WM1811_JACKDET_MODE_MIC;
791 else
792 mode = WM1811_JACKDET_MODE_JACK;
793
794 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 795 }
796
797 mutex_unlock(&wm8994->accdet_lock);
798}
799
9e6e96a1
MB		 800static int clk_sys_event(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802{
803 struct snd_soc_codec *codec = w->codec;
99af79df 804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 return configure_clock(codec);
809
99af79df
MB		 810 case SND_SOC_DAPM_POST_PMU:
811 /*
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
817 */
818 if (wm8994->jackdet && !wm8994->clk_has_run) {
819 schedule_delayed_work(&wm8994->jackdet_bootstrap,
820 msecs_to_jiffies(1000));
821 wm8994->clk_has_run = true;
822 }
823 break;
824
9e6e96a1
MB		 825 case SND_SOC_DAPM_POST_PMD:
826 configure_clock(codec);
827 break;
828 }
829
830 return 0;
831}
832
4b7ed83a
MB		 833static void vmid_reference(struct snd_soc_codec *codec)
834{
835 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
836
db966f8a
MB		 837 pm_runtime_get_sync(codec->dev);
838
4b7ed83a
MB		 839 wm8994->vmid_refcount++;
840
841 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
842 wm8994->vmid_refcount);
843
844 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 845 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 846 WM8994_LINEOUT1_DISCH |
22f8d055 847 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 848
f7085641
MB		 849 wm_hubs_vmid_ena(codec);
850
22f8d055
MB		 851 switch (wm8994->vmid_mode) {
852 default:
cbd71f30 853 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 854 case WM8994_VMID_NORMAL:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
857 WM8994_BIAS_SRC |
858 WM8994_VMID_DISCH |
859 WM8994_STARTUP_BIAS_ENA |
860 WM8994_VMID_BUF_ENA |
861 WM8994_VMID_RAMP_MASK,
862 WM8994_BIAS_SRC |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
a3a1d9d2 865 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 866
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
869 WM8994_BIAS_ENA |
870 WM8994_VMID_SEL_MASK,
871 WM8994_BIAS_ENA | 0x2);
872
a3a1d9d2 873 msleep(300);
22f8d055
MB		 874
875 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
876 WM8994_VMID_RAMP_MASK |
877 WM8994_BIAS_SRC,
878 0);
879 break;
cc6d5a8c 880
22f8d055
MB		 881 case WM8994_VMID_FORCE:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_BIAS_SRC |
885 WM8994_VMID_DISCH |
886 WM8994_STARTUP_BIAS_ENA |
887 WM8994_VMID_BUF_ENA |
888 WM8994_VMID_RAMP_MASK,
889 WM8994_BIAS_SRC |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 (0x2 << WM8994_VMID_RAMP_SHIFT));
893
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
896 WM8994_BIAS_ENA |
897 WM8994_VMID_SEL_MASK,
898 WM8994_BIAS_ENA | 0x2);
899
900 msleep(400);
901
902 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
903 WM8994_VMID_RAMP_MASK |
904 WM8994_BIAS_SRC,
905 0);
906 break;
907 }
4b7ed83a
MB		 908 }
909}
910
911static void vmid_dereference(struct snd_soc_codec *codec)
912{
913 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
914
915 wm8994->vmid_refcount--;
916
917 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
918 wm8994->vmid_refcount);
919
920 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 921 if (wm8994->hubs.lineout1_se)
922 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
923 WM8994_LINEOUT1N_ENA |
924 WM8994_LINEOUT1P_ENA,
925 WM8994_LINEOUT1N_ENA |
926 WM8994_LINEOUT1P_ENA);
927
928 if (wm8994->hubs.lineout2_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT2N_ENA |
931 WM8994_LINEOUT2P_ENA,
932 WM8994_LINEOUT2N_ENA |
933 WM8994_LINEOUT2P_ENA);
934
935 /* Start discharging VMID */
4b7ed83a
MB		 936 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
937 WM8994_BIAS_SRC |
22f8d055 938 WM8994_VMID_DISCH,
4b7ed83a 939 WM8994_BIAS_SRC |
22f8d055 940 WM8994_VMID_DISCH);
4b7ed83a 941
f95be9d6
MB		 942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
943 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 944
f95be9d6 945 msleep(400);
e85b26ce 946
22f8d055 947 /* Active discharge */
4b7ed83a
MB		 948 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
949 WM8994_LINEOUT1_DISCH |
950 WM8994_LINEOUT2_DISCH,
951 WM8994_LINEOUT1_DISCH |
952 WM8994_LINEOUT2_DISCH);
953
22f8d055
MB		 954 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
955 WM8994_LINEOUT1N_ENA |
956 WM8994_LINEOUT1P_ENA |
957 WM8994_LINEOUT2N_ENA |
958 WM8994_LINEOUT2P_ENA, 0);
959
4b7ed83a
MB		 960 /* Switch off startup biases */
961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
962 WM8994_BIAS_SRC |
963 WM8994_STARTUP_BIAS_ENA |
964 WM8994_VMID_BUF_ENA |
965 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 966
967 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 968 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 969 }
db966f8a
MB		 970
971 pm_runtime_put(codec->dev);
4b7ed83a
MB		 972}
973
974static int vmid_event(struct snd_soc_dapm_widget *w,
975 struct snd_kcontrol *kcontrol, int event)
976{
977 struct snd_soc_codec *codec = w->codec;
978
979 switch (event) {
980 case SND_SOC_DAPM_PRE_PMU:
981 vmid_reference(codec);
982 break;
983
984 case SND_SOC_DAPM_POST_PMD:
985 vmid_dereference(codec);
986 break;
987 }
988
989 return 0;
990}
991
c340304d 992static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 993{
9e6e96a1
MB		 994 int source = 0; /* GCC flow analysis can't track enable */
995 int reg, reg_r;
996
c340304d 997 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 998 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
999 switch (reg) {
1000 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1001 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1002 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003 break;
1004 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1005 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1006 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1009 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1010 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 default:
ee839a21 1013 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1014 return false;
9e6e96a1
MB		 1015 }
1016
1017 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1018 if (reg_r != reg) {
ee839a21 1019 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1020 return false;
9e6e96a1
MB		 1021 }
1022
c340304d
MB		 1023 /* Set the source up */
1024 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1025 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1026
c340304d 1027 return true;
9e6e96a1
MB		 1028}
1029
1a38336b
MB		 1030static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1031 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1032{
1033 struct snd_soc_codec *codec = w->codec;
79748cdb 1034 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1a38336b
MB		 1035 struct wm8994 *control = codec->control_data;
1036 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1037 int i;
1a38336b
MB		 1038 int dac;
1039 int adc;
1040 int val;
1041
1042 switch (control->type) {
1043 case WM8994:
1044 case WM8958:
1045 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1046 break;
1047 default:
1048 break;
1049 }
173efa09
DP		 1050
1051 switch (event) {
1052 case SND_SOC_DAPM_PRE_PMU:
79748cdb
MB		 1053 /* Don't enable timeslot 2 if not in use */
1054 if (wm8994->channels[0] <= 2)
1055 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1056
1a38336b
MB		 1057 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1058 if ((val & WM8994_AIF1ADCL_SRC) &&
1059 (val & WM8994_AIF1ADCR_SRC))
1060 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1061 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1062 !(val & WM8994_AIF1ADCR_SRC))
1063 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1064 else
1065 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1066 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1067
1068 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1069 if ((val & WM8994_AIF1DACL_SRC) &&
1070 (val & WM8994_AIF1DACR_SRC))
1071 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1072 else if (!(val & WM8994_AIF1DACL_SRC) &&
1073 !(val & WM8994_AIF1DACR_SRC))
1074 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1075 else
1076 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1077 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1078
1079 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1080 mask, adc);
1081 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1082 mask, dac);
1083 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1084 WM8994_AIF1DSPCLK_ENA |
1085 WM8994_SYSDSPCLK_ENA,
1086 WM8994_AIF1DSPCLK_ENA |
1087 WM8994_SYSDSPCLK_ENA);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1089 WM8994_AIF1ADC1R_ENA |
1090 WM8994_AIF1ADC1L_ENA |
1091 WM8994_AIF1ADC2R_ENA |
1092 WM8994_AIF1ADC2L_ENA);
1093 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1094 WM8994_AIF1DAC1R_ENA |
1095 WM8994_AIF1DAC1L_ENA |
1096 WM8994_AIF1DAC2R_ENA |
1097 WM8994_AIF1DAC2L_ENA);
173efa09 1098 break;
173efa09 1099
bfd37bb5
MB		 1100 case SND_SOC_DAPM_POST_PMU:
1101 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1102 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1103 snd_soc_read(codec,
1104 wm8994_vu_bits[i].reg));
1105 break;
1106
1a38336b
MB		 1107 case SND_SOC_DAPM_PRE_PMD:
1108 case SND_SOC_DAPM_POST_PMD:
1109 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1110 mask, 0);
1111 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1112 mask, 0);
1113
1114 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1115 if (val & WM8994_AIF2DSPCLK_ENA)
1116 val = WM8994_SYSDSPCLK_ENA;
1117 else
1118 val = 0;
1119 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1120 WM8994_SYSDSPCLK_ENA |
1121 WM8994_AIF1DSPCLK_ENA, val);
1122 break;
1123 }
c6b7b570 1124
173efa09
DP		 1125 return 0;
1126}
1127
1a38336b
MB		 1128static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1129 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1130{
1131 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1132 int i;
1a38336b
MB		 1133 int dac;
1134 int adc;
1135 int val;
173efa09
DP		 1136
1137 switch (event) {
1a38336b
MB		 1138 case SND_SOC_DAPM_PRE_PMU:
1139 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1140 if ((val & WM8994_AIF2ADCL_SRC) &&
1141 (val & WM8994_AIF2ADCR_SRC))
1142 adc = WM8994_AIF2ADCR_ENA;
1143 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1144 !(val & WM8994_AIF2ADCR_SRC))
1145 adc = WM8994_AIF2ADCL_ENA;
1146 else
1147 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1148
1149
1150 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1151 if ((val & WM8994_AIF2DACL_SRC) &&
1152 (val & WM8994_AIF2DACR_SRC))
1153 dac = WM8994_AIF2DACR_ENA;
1154 else if (!(val & WM8994_AIF2DACL_SRC) &&
1155 !(val & WM8994_AIF2DACR_SRC))
1156 dac = WM8994_AIF2DACL_ENA;
1157 else
1158 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1159
1160 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1161 WM8994_AIF2ADCL_ENA |
1162 WM8994_AIF2ADCR_ENA, adc);
1163 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1164 WM8994_AIF2DACL_ENA |
1165 WM8994_AIF2DACR_ENA, dac);
1166 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1167 WM8994_AIF2DSPCLK_ENA |
1168 WM8994_SYSDSPCLK_ENA,
1169 WM8994_AIF2DSPCLK_ENA |
1170 WM8994_SYSDSPCLK_ENA);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1172 WM8994_AIF2ADCL_ENA |
1173 WM8994_AIF2ADCR_ENA,
1174 WM8994_AIF2ADCL_ENA |
1175 WM8994_AIF2ADCR_ENA);
1176 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1177 WM8994_AIF2DACL_ENA |
1178 WM8994_AIF2DACR_ENA,
1179 WM8994_AIF2DACL_ENA |
1180 WM8994_AIF2DACR_ENA);
1181 break;
1182
bfd37bb5
MB		 1183 case SND_SOC_DAPM_POST_PMU:
1184 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1185 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1186 snd_soc_read(codec,
1187 wm8994_vu_bits[i].reg));
1188 break;
1189
1a38336b 1190 case SND_SOC_DAPM_PRE_PMD:
173efa09 1191 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1192 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1193 WM8994_AIF2DACL_ENA |
1194 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1195 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1196 WM8994_AIF2ADCL_ENA |
1197 WM8994_AIF2ADCR_ENA, 0);
1198
1199 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1200 if (val & WM8994_AIF1DSPCLK_ENA)
1201 val = WM8994_SYSDSPCLK_ENA;
1202 else
1203 val = 0;
1204 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1205 WM8994_SYSDSPCLK_ENA |
1206 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1207 break;
1208 }
1209
1210 return 0;
1211}
1212
1a38336b
MB		 1213static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1214 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1215{
1216 struct snd_soc_codec *codec = w->codec;
1217 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1218
1219 switch (event) {
1220 case SND_SOC_DAPM_PRE_PMU:
1221 wm8994->aif1clk_enable = 1;
1222 break;
a3cff81a
DP		 1223 case SND_SOC_DAPM_POST_PMD:
1224 wm8994->aif1clk_disable = 1;
1225 break;
173efa09
DP		 1226 }
1227
1228 return 0;
1229}
1230
1a38336b
MB		 1231static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1232 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1233{
1234 struct snd_soc_codec *codec = w->codec;
1235 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1236
1237 switch (event) {
1238 case SND_SOC_DAPM_PRE_PMU:
1239 wm8994->aif2clk_enable = 1;
1240 break;
a3cff81a
DP		 1241 case SND_SOC_DAPM_POST_PMD:
1242 wm8994->aif2clk_disable = 1;
1243 break;
173efa09
DP		 1244 }
1245
1246 return 0;
1247}
1248
1a38336b
MB		 1249static int late_enable_ev(struct snd_soc_dapm_widget *w,
1250 struct snd_kcontrol *kcontrol, int event)
1251{
1252 struct snd_soc_codec *codec = w->codec;
1253 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1254
1255 switch (event) {
1256 case SND_SOC_DAPM_PRE_PMU:
1257 if (wm8994->aif1clk_enable) {
c8fdc1b5 1258 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1259 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1260 WM8994_AIF1CLK_ENA_MASK,
1261 WM8994_AIF1CLK_ENA);
c8fdc1b5 1262 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1263 wm8994->aif1clk_enable = 0;
1264 }
1265 if (wm8994->aif2clk_enable) {
c8fdc1b5 1266 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1267 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1268 WM8994_AIF2CLK_ENA_MASK,
1269 WM8994_AIF2CLK_ENA);
c8fdc1b5 1270 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1271 wm8994->aif2clk_enable = 0;
1272 }
1273 break;
1274 }
1275
1276 /* We may also have postponed startup of DSP, handle that. */
1277 wm8958_aif_ev(w, kcontrol, event);
1278
1279 return 0;
1280}
1281
1282static int late_disable_ev(struct snd_soc_dapm_widget *w,
1283 struct snd_kcontrol *kcontrol, int event)
1284{
1285 struct snd_soc_codec *codec = w->codec;
1286 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1287
1288 switch (event) {
1289 case SND_SOC_DAPM_POST_PMD:
1290 if (wm8994->aif1clk_disable) {
c8fdc1b5 1291 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1292 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1293 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1294 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1295 wm8994->aif1clk_disable = 0;
1296 }
1297 if (wm8994->aif2clk_disable) {
c8fdc1b5 1298 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1299 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1300 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1301 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1302 wm8994->aif2clk_disable = 0;
1303 }
1304 break;
1305 }
1306
1307 return 0;
1308}
1309
04d28681
DP		 1310static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1311 struct snd_kcontrol *kcontrol, int event)
1312{
1313 late_enable_ev(w, kcontrol, event);
1314 return 0;
1315}
1316
b462c6e6
DP		 1317static int micbias_ev(struct snd_soc_dapm_widget *w,
1318 struct snd_kcontrol *kcontrol, int event)
1319{
1320 late_enable_ev(w, kcontrol, event);
1321 return 0;
1322}
1323
c52fd021
DP		 1324static int dac_ev(struct snd_soc_dapm_widget *w,
1325 struct snd_kcontrol *kcontrol, int event)
1326{
1327 struct snd_soc_codec *codec = w->codec;
1328 unsigned int mask = 1 << w->shift;
1329
1330 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1331 mask, mask);
1332 return 0;
1333}
1334
9e6e96a1
MB		 1335static const char *adc_mux_text[] = {
1336 "ADC",
1337 "DMIC",
1338};
1339
1340static const struct soc_enum adc_enum =
1341 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1342
1343static const struct snd_kcontrol_new adcl_mux =
1344 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1345
1346static const struct snd_kcontrol_new adcr_mux =
1347 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1348
1349static const struct snd_kcontrol_new left_speaker_mixer[] = {
1350SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1351SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1352SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1353SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1354SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1355};
1356
1357static const struct snd_kcontrol_new right_speaker_mixer[] = {
1358SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1359SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1360SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1361SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1362SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1363};
1364
1365/* Debugging; dump chip status after DAPM transitions */
1366static int post_ev(struct snd_soc_dapm_widget *w,
1367 struct snd_kcontrol *kcontrol, int event)
1368{
1369 struct snd_soc_codec *codec = w->codec;
1370 dev_dbg(codec->dev, "SRC status: %x\n",
1371 snd_soc_read(codec,
1372 WM8994_RATE_STATUS));
1373 return 0;
1374}
1375
1376static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1377SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1378 1, 1, 0),
1379SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1380 0, 1, 0),
1381};
1382
1383static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1384SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1385 1, 1, 0),
1386SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1387 0, 1, 0),
1388};
1389
a3257ba8
MB		 1390static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1391SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1392 1, 1, 0),
1393SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1394 0, 1, 0),
1395};
1396
1397static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1398SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1399 1, 1, 0),
1400SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1401 0, 1, 0),
1402};
1403
9e6e96a1
MB		 1404static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1405SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1406 5, 1, 0),
1407SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1408 4, 1, 0),
1409SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1410 2, 1, 0),
1411SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 1, 1, 0),
1413SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 0, 1, 0),
1415};
1416
1417static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1418SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1419 5, 1, 0),
1420SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1421 4, 1, 0),
1422SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1423 2, 1, 0),
1424SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 1, 1, 0),
1426SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 0, 1, 0),
1428};
1429
1430#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1431{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1432 .info = snd_soc_info_volsw, \
1433 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1434 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1435
1436static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1437 struct snd_ctl_elem_value *ucontrol)
1438{
9d03545d
JN		 1439 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1440 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1441 struct snd_soc_codec *codec = w->codec;
1442 int ret;
1443
1444 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1445
c340304d 1446 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1447
1448 return ret;
1449}
1450
1451static const struct snd_kcontrol_new dac1l_mix[] = {
1452WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1453 5, 1, 0),
1454WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 4, 1, 0),
1456WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457 2, 1, 0),
1458WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 1, 1, 0),
1460WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 0, 1, 0),
1462};
1463
1464static const struct snd_kcontrol_new dac1r_mix[] = {
1465WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1466 5, 1, 0),
1467WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 4, 1, 0),
1469WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470 2, 1, 0),
1471WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 1, 1, 0),
1473WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 0, 1, 0),
1475};
1476
1477static const char *sidetone_text[] = {
1478 "ADC/DMIC1", "DMIC2",
1479};
1480
1481static const struct soc_enum sidetone1_enum =
1482 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1483
1484static const struct snd_kcontrol_new sidetone1_mux =
1485 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1486
1487static const struct soc_enum sidetone2_enum =
1488 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1489
1490static const struct snd_kcontrol_new sidetone2_mux =
1491 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1492
1493static const char *aif1dac_text[] = {
1494 "AIF1DACDAT", "AIF3DACDAT",
1495};
1496
50941968
MB		 1497static const char *loopback_text[] = {
1498 "None", "ADCDAT",
1499};
1500
1501static const struct soc_enum aif1_loopback_enum =
1502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, WM8994_AIF1_LOOPBACK_SHIFT, 2,
1503 loopback_text);
1504
1505static const struct snd_kcontrol_new aif1_loopback =
1506 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1507
1508static const struct soc_enum aif2_loopback_enum =
1509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, WM8994_AIF2_LOOPBACK_SHIFT, 2,
1510 loopback_text);
1511
1512static const struct snd_kcontrol_new aif2_loopback =
1513 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1514
9e6e96a1
MB		 1515static const struct soc_enum aif1dac_enum =
1516 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1517
1518static const struct snd_kcontrol_new aif1dac_mux =
1519 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1520
1521static const char *aif2dac_text[] = {
1522 "AIF2DACDAT", "AIF3DACDAT",
1523};
1524
1525static const struct soc_enum aif2dac_enum =
1526 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1527
1528static const struct snd_kcontrol_new aif2dac_mux =
1529 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1530
1531static const char *aif2adc_text[] = {
1532 "AIF2ADCDAT", "AIF3DACDAT",
1533};
1534
1535static const struct soc_enum aif2adc_enum =
1536 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1537
1538static const struct snd_kcontrol_new aif2adc_mux =
1539 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1540
1541static const char *aif3adc_text[] = {
c4431df0 1542 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1543};
1544
c4431df0 1545static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1546 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1547
c4431df0
MB		 1548static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1549 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1550
1551static const struct soc_enum wm8958_aif3adc_enum =
1552 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1553
1554static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1555 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1556
1557static const char *mono_pcm_out_text[] = {
c1a4ecd9 1558 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1559};
1560
1561static const struct soc_enum mono_pcm_out_enum =
1562 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1563
1564static const struct snd_kcontrol_new mono_pcm_out_mux =
1565 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1566
1567static const char *aif2dac_src_text[] = {
1568 "AIF2", "AIF3",
1569};
1570
1571/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1572static const struct soc_enum aif2dacl_src_enum =
1573 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1574
1575static const struct snd_kcontrol_new aif2dacl_src_mux =
1576 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1577
1578static const struct soc_enum aif2dacr_src_enum =
1579 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1580
1581static const struct snd_kcontrol_new aif2dacr_src_mux =
1582 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1583
173efa09 1584static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1585SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1586 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1587SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1588 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1589
1590SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1591 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1592SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1593 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1594SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1595 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1597 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1598SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1599 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600
1601SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1602 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1603 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1605 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1606 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1607SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1609SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1610 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1611
1612SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1613};
1614
1615static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1616SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1618 SND_SOC_DAPM_PRE_PMD),
1a38336b 1619SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1620 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1621 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1622SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1623SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1624 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1625SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1626 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1627SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1628SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1629};
1630
c52fd021
DP		 1631static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1632SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1633 dac_ev, SND_SOC_DAPM_PRE_PMU),
1634SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1635 dac_ev, SND_SOC_DAPM_PRE_PMU),
1636SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1637 dac_ev, SND_SOC_DAPM_PRE_PMU),
1638SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1639 dac_ev, SND_SOC_DAPM_PRE_PMU),
1640};
1641
1642static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1643SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1644SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1645SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1646SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1647};
1648
04d28681 1649static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1650SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1651 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1652SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1653 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1654};
1655
1656static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1657SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1658SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1659};
1660
9e6e96a1
MB		 1661static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1662SND_SOC_DAPM_INPUT("DMIC1DAT"),
1663SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1664SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1665
b462c6e6
DP		 1666SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1667 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1668SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1669 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1670
9e6e96a1 1671SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1672 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1673 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1674
1a38336b
MB		 1675SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1676SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1677SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1678
7f94de48 1679SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1680 0, SND_SOC_NOPM, 9, 0),
7f94de48 1681SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1682 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1683SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1684 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1685 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1686SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1687 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1688 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1689
7f94de48 1690SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1691 0, SND_SOC_NOPM, 11, 0),
7f94de48 1692SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1693 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1694SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1695 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1696 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1697SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1698 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1699 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1700
1701SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1702 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1703SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1704 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1705
a3257ba8
MB		 1706SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1707 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1708SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1710
9e6e96a1
MB		 1711SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1712 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1713SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1714 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1715
1716SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1717SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1718
1719SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1720 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1721SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1722 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1723
1724SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1725 SND_SOC_NOPM, 13, 0),
9e6e96a1 1726SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1727 SND_SOC_NOPM, 12, 0),
d6addcc9 1728SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1729 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1730 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1731SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1732 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1733 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1734
5567d8c6
MB		 1735SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1736SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1737SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1738SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1739
1740SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1741SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1742SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1743
5567d8c6
MB		 1744SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1745SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1746
1747SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1748
1749SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1750SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1751SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1752SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1753
1754/* Power is done with the muxes since the ADC power also controls the
1755 * downsampling chain, the chip will automatically manage the analogue
1756 * specific portions.
1757 */
1758SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1759SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1760
50941968
MB		 1761SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1762SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1763
9e6e96a1
MB		 1764SND_SOC_DAPM_POST("Debug log", post_ev),
1765};
1766
c4431df0
MB		 1767static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1768SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1769};
9e6e96a1 1770
c4431df0 1771static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1772SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1773SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1774SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1775SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1776SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1777};
1778
1779static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1780 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1781 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1782
1783 { "DSP1CLK", NULL, "CLK_SYS" },
1784 { "DSP2CLK", NULL, "CLK_SYS" },
1785 { "DSPINTCLK", NULL, "CLK_SYS" },
1786
1787 { "AIF1ADC1L", NULL, "AIF1CLK" },
1788 { "AIF1ADC1L", NULL, "DSP1CLK" },
1789 { "AIF1ADC1R", NULL, "AIF1CLK" },
1790 { "AIF1ADC1R", NULL, "DSP1CLK" },
1791 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1792
1793 { "AIF1DAC1L", NULL, "AIF1CLK" },
1794 { "AIF1DAC1L", NULL, "DSP1CLK" },
1795 { "AIF1DAC1R", NULL, "AIF1CLK" },
1796 { "AIF1DAC1R", NULL, "DSP1CLK" },
1797 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1798
1799 { "AIF1ADC2L", NULL, "AIF1CLK" },
1800 { "AIF1ADC2L", NULL, "DSP1CLK" },
1801 { "AIF1ADC2R", NULL, "AIF1CLK" },
1802 { "AIF1ADC2R", NULL, "DSP1CLK" },
1803 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1804
1805 { "AIF1DAC2L", NULL, "AIF1CLK" },
1806 { "AIF1DAC2L", NULL, "DSP1CLK" },
1807 { "AIF1DAC2R", NULL, "AIF1CLK" },
1808 { "AIF1DAC2R", NULL, "DSP1CLK" },
1809 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1810
1811 { "AIF2ADCL", NULL, "AIF2CLK" },
1812 { "AIF2ADCL", NULL, "DSP2CLK" },
1813 { "AIF2ADCR", NULL, "AIF2CLK" },
1814 { "AIF2ADCR", NULL, "DSP2CLK" },
1815 { "AIF2ADCR", NULL, "DSPINTCLK" },
1816
1817 { "AIF2DACL", NULL, "AIF2CLK" },
1818 { "AIF2DACL", NULL, "DSP2CLK" },
1819 { "AIF2DACR", NULL, "AIF2CLK" },
1820 { "AIF2DACR", NULL, "DSP2CLK" },
1821 { "AIF2DACR", NULL, "DSPINTCLK" },
1822
1823 { "DMIC1L", NULL, "DMIC1DAT" },
1824 { "DMIC1L", NULL, "CLK_SYS" },
1825 { "DMIC1R", NULL, "DMIC1DAT" },
1826 { "DMIC1R", NULL, "CLK_SYS" },
1827 { "DMIC2L", NULL, "DMIC2DAT" },
1828 { "DMIC2L", NULL, "CLK_SYS" },
1829 { "DMIC2R", NULL, "DMIC2DAT" },
1830 { "DMIC2R", NULL, "CLK_SYS" },
1831
1832 { "ADCL", NULL, "AIF1CLK" },
1833 { "ADCL", NULL, "DSP1CLK" },
1834 { "ADCL", NULL, "DSPINTCLK" },
1835
1836 { "ADCR", NULL, "AIF1CLK" },
1837 { "ADCR", NULL, "DSP1CLK" },
1838 { "ADCR", NULL, "DSPINTCLK" },
1839
1840 { "ADCL Mux", "ADC", "ADCL" },
1841 { "ADCL Mux", "DMIC", "DMIC1L" },
1842 { "ADCR Mux", "ADC", "ADCR" },
1843 { "ADCR Mux", "DMIC", "DMIC1R" },
1844
1845 { "DAC1L", NULL, "AIF1CLK" },
1846 { "DAC1L", NULL, "DSP1CLK" },
1847 { "DAC1L", NULL, "DSPINTCLK" },
1848
1849 { "DAC1R", NULL, "AIF1CLK" },
1850 { "DAC1R", NULL, "DSP1CLK" },
1851 { "DAC1R", NULL, "DSPINTCLK" },
1852
1853 { "DAC2L", NULL, "AIF2CLK" },
1854 { "DAC2L", NULL, "DSP2CLK" },
1855 { "DAC2L", NULL, "DSPINTCLK" },
1856
1857 { "DAC2R", NULL, "AIF2DACR" },
1858 { "DAC2R", NULL, "AIF2CLK" },
1859 { "DAC2R", NULL, "DSP2CLK" },
1860 { "DAC2R", NULL, "DSPINTCLK" },
1861
1862 { "TOCLK", NULL, "CLK_SYS" },
1863
5567d8c6
MB		 1864 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1865 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1866 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1867
1868 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1869 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1870 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1871
9e6e96a1
MB		 1872 /* AIF1 outputs */
1873 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1874 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1875 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1876
1877 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1878 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1879 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1880
a3257ba8
MB		 1881 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1882 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1883 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1884
1885 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1886 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1887 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1888
9e6e96a1
MB		 1889 /* Pin level routing for AIF3 */
1890 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1891 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1892 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1893 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1894
50941968 1895 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
9e6e96a1 1896 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
50941968 1897 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
9e6e96a1
MB		 1898 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1899 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1900 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1901 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1902
1903 /* DAC1 inputs */
9e6e96a1
MB		 1904 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1905 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1906 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1907 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1908 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1909
9e6e96a1
MB		 1910 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1911 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1912 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1913 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1914 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1915
1916 /* DAC2/AIF2 outputs */
1917 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1918 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1919 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1920 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1921 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1922 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1923
1924 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1925 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1926 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1927 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1928 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1929 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1930
7f94de48
MB		 1931 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1932 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1933 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1934 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1935
9e6e96a1
MB		 1936 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1937
1938 /* AIF3 output */
1939 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1940 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1941 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1942 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1943 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1944 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1945 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1946 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1947
50941968
MB		 1948 /* Loopback */
1949 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1950 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1951 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1952 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1953
9e6e96a1
MB		 1954 /* Sidetone */
1955 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1956 { "Left Sidetone", "DMIC2", "DMIC2L" },
1957 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1958 { "Right Sidetone", "DMIC2", "DMIC2R" },
1959
1960 /* Output stages */
1961 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1962 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1963
1964 { "SPKL", "DAC1 Switch", "DAC1L" },
1965 { "SPKL", "DAC2 Switch", "DAC2L" },
1966
1967 { "SPKR", "DAC1 Switch", "DAC1R" },
1968 { "SPKR", "DAC2 Switch", "DAC2R" },
1969
1970 { "Left Headphone Mux", "DAC", "DAC1L" },
1971 { "Right Headphone Mux", "DAC", "DAC1R" },
1972};
1973
173efa09
DP		 1974static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1975 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1976 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1977 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1978 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1979 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1980 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1981 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1982 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1983};
1984
1985static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1986 { "DAC1L", NULL, "DAC1L Mixer" },
1987 { "DAC1R", NULL, "DAC1R Mixer" },
1988 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1989 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1990};
1991
6ed8f148
MB		 1992static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1993 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1994 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1995 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1996 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1997 { "MICBIAS1", NULL, "CLK_SYS" },
1998 { "MICBIAS1", NULL, "MICBIAS Supply" },
1999 { "MICBIAS2", NULL, "CLK_SYS" },
2000 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 2001};
2002
c4431df0
MB		 2003static const struct snd_soc_dapm_route wm8994_intercon[] = {
2004 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2005 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 2006 { "MICBIAS1", NULL, "VMID" },
2007 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 2008};
2009
2010static const struct snd_soc_dapm_route wm8958_intercon[] = {
2011 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2012 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2013
2014 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2015 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2016 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2017 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2018
8c5b842b
MB		 2019 { "AIF3DACDAT", NULL, "AIF3" },
2020 { "AIF3ADCDAT", NULL, "AIF3" },
2021
c4431df0
MB		 2022 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2023 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2024
2025 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2026};
2027
9e6e96a1
MB		 2028/* The size in bits of the FLL divide multiplied by 10
2029 * to allow rounding later */
2030#define FIXED_FLL_SIZE ((1 << 16) * 10)
2031
2032struct fll_div {
2033 u16 outdiv;
2034 u16 n;
2035 u16 k;
d1a0a299 2036 u16 lambda;
9e6e96a1
MB		 2037 u16 clk_ref_div;
2038 u16 fll_fratio;
2039};
2040
d1a0a299 2041static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
9e6e96a1
MB		 2042 int freq_in, int freq_out)
2043{
2044 u64 Kpart;
d1a0a299 2045 unsigned int K, Ndiv, Nmod, gcd_fll;
9e6e96a1
MB		 2046
2047 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2048
2049 /* Scale the input frequency down to <= 13.5MHz */
2050 fll->clk_ref_div = 0;
2051 while (freq_in > 13500000) {
2052 fll->clk_ref_div++;
2053 freq_in /= 2;
2054
2055 if (fll->clk_ref_div > 3)
2056 return -EINVAL;
2057 }
2058 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2059
2060 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2061 fll->outdiv = 3;
2062 while (freq_out * (fll->outdiv + 1) < 90000000) {
2063 fll->outdiv++;
2064 if (fll->outdiv > 63)
2065 return -EINVAL;
2066 }
2067 freq_out *= fll->outdiv + 1;
2068 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2069
2070 if (freq_in > 1000000) {
2071 fll->fll_fratio = 0;
7d48a6ac
MB		 2072 } else if (freq_in > 256000) {
2073 fll->fll_fratio = 1;
2074 freq_in *= 2;
2075 } else if (freq_in > 128000) {
2076 fll->fll_fratio = 2;
2077 freq_in *= 4;
2078 } else if (freq_in > 64000) {
9e6e96a1
MB		 2079 fll->fll_fratio = 3;
2080 freq_in *= 8;
7d48a6ac
MB		 2081 } else {
2082 fll->fll_fratio = 4;
2083 freq_in *= 16;
9e6e96a1
MB		 2084 }
2085 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2086
2087 /* Now, calculate N.K */
2088 Ndiv = freq_out / freq_in;
2089
2090 fll->n = Ndiv;
2091 Nmod = freq_out % freq_in;
2092 pr_debug("Nmod=%d\n", Nmod);
2093
d1a0a299
MB		 2094 switch (control->type) {
2095 case WM8994:
2096 /* Calculate fractional part - scale up so we can round. */
2097 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
9e6e96a1 2098
d1a0a299 2099 do_div(Kpart, freq_in);
9e6e96a1 2100
d1a0a299 2101 K = Kpart & 0xFFFFFFFF;
9e6e96a1 2102
d1a0a299
MB		 2103 if ((K % 10) >= 5)
2104 K += 5;
9e6e96a1 2105
d1a0a299
MB		 2106 /* Move down to proper range now rounding is done */
2107 fll->k = K / 10;
f7dbd399 2108 fll->lambda = 0;
9e6e96a1 2109
d1a0a299 2110 pr_debug("N=%x K=%x\n", fll->n, fll->k);
571ab6c6 2111 break;
d1a0a299
MB		 2112
2113 default:
2114 gcd_fll = gcd(freq_out, freq_in);
2115
2116 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2117 fll->lambda = freq_in / gcd_fll;
2118
2119 }
9e6e96a1
MB		 2120
2121 return 0;
2122}
2123
f0fba2ad 2124static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2125 unsigned int freq_in, unsigned int freq_out)
2126{
b2c812e2 2127 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2128 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2129 int reg_offset, ret;
2130 struct fll_div fll;
e413ba88 2131 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2132 unsigned long timeout;
4b7ed83a 2133 bool was_enabled;
9e6e96a1 2134
9e6e96a1
MB		 2135 switch (id) {
2136 case WM8994_FLL1:
2137 reg_offset = 0;
2138 id = 0;
e413ba88 2139 aif_src = 0x10;
9e6e96a1
MB		 2140 break;
2141 case WM8994_FLL2:
2142 reg_offset = 0x20;
2143 id = 1;
e413ba88 2144 aif_src = 0x18;
9e6e96a1
MB		 2145 break;
2146 default:
2147 return -EINVAL;
2148 }
2149
4b7ed83a
MB		 2150 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2151 was_enabled = reg & WM8994_FLL1_ENA;
2152
136ff2a2 2153 switch (src) {
7add84aa
MB		 2154 case 0:
2155 /* Allow no source specification when stopping */
2156 if (freq_out)
2157 return -EINVAL;
4514e899 2158 src = wm8994->fll[id].src;
7add84aa 2159 break;
136ff2a2
MB		 2160 case WM8994_FLL_SRC_MCLK1:
2161 case WM8994_FLL_SRC_MCLK2:
2162 case WM8994_FLL_SRC_LRCLK:
2163 case WM8994_FLL_SRC_BCLK:
2164 break;
fbfe6983
MB		 2165 case WM8994_FLL_SRC_INTERNAL:
2166 freq_in = 12000000;
2167 freq_out = 12000000;
2168 break;
136ff2a2
MB		 2169 default:
2170 return -EINVAL;
2171 }
2172
9e6e96a1
MB		 2173 /* Are we changing anything? */
2174 if (wm8994->fll[id].src == src &&
2175 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2176 return 0;
2177
2178 /* If we're stopping the FLL redo the old config - no
2179 * registers will actually be written but we avoid GCC flow
2180 * analysis bugs spewing warnings.
2181 */
2182 if (freq_out)
d1a0a299 2183 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
9e6e96a1 2184 else
d1a0a299 2185 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
9e6e96a1
MB		 2186 wm8994->fll[id].out);
2187 if (ret < 0)
2188 return ret;
2189
e413ba88
MB		 2190 /* Make sure that we're not providing SYSCLK right now */
2191 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2192 if (clk1 & WM8994_SYSCLK_SRC)
2193 aif_reg = WM8994_AIF2_CLOCKING_1;
2194 else
2195 aif_reg = WM8994_AIF1_CLOCKING_1;
2196 reg = snd_soc_read(codec, aif_reg);
2197
2198 if ((reg & WM8994_AIF1CLK_ENA) &&
2199 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2200 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2201 id + 1);
2202 return -EBUSY;
2203 }
9e6e96a1
MB		 2204
2205 /* We always need to disable the FLL while reconfiguring */
2206 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2207 WM8994_FLL1_ENA, 0);
2208
20dc24a9 2209 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2210 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2211 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2212 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2213 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2214 goto out;
2215 }
2216
9e6e96a1
MB		 2217 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2218 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2219 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2220 WM8994_FLL1_OUTDIV_MASK |
2221 WM8994_FLL1_FRATIO_MASK, reg);
2222
b16db745
MB		 2223 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2224 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2225
2226 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2227 WM8994_FLL1_N_MASK,
7435d4ee 2228 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1 2229
d1a0a299
MB		 2230 if (fll.lambda) {
2231 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2232 WM8958_FLL1_LAMBDA_MASK,
2233 fll.lambda);
2234 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2235 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2236 } else {
2237 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2238 WM8958_FLL1_EFS_ENA, 0);
2239 }
2240
9e6e96a1 2241 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2242 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2243 WM8994_FLL1_REFCLK_DIV_MASK |
2244 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2245 ((src == WM8994_FLL_SRC_INTERNAL)
2246 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2247 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2248 (src - 1));
9e6e96a1 2249
f0f5039c
MB		 2250 /* Clear any pending completion from a previous failure */
2251 try_wait_for_completion(&wm8994->fll_locked[id]);
2252
9e6e96a1
MB		 2253 /* Enable (with fractional mode if required) */
2254 if (freq_out) {
4b7ed83a
MB		 2255 /* Enable VMID if we need it */
2256 if (!was_enabled) {
af6b6fe4
MB		 2257 active_reference(codec);
2258
4b7ed83a
MB		 2259 switch (control->type) {
2260 case WM8994:
2261 vmid_reference(codec);
2262 break;
2263 case WM8958:
da445afe 2264 if (control->revision < 1)
4b7ed83a
MB		 2265 vmid_reference(codec);
2266 break;
2267 default:
2268 break;
2269 }
2270 }
2271
fbfe6983
MB		 2272 reg = WM8994_FLL1_ENA;
2273
9e6e96a1 2274 if (fll.k)
fbfe6983
MB		 2275 reg |= WM8994_FLL1_FRAC;
2276 if (src == WM8994_FLL_SRC_INTERNAL)
2277 reg |= WM8994_FLL1_OSC_ENA;
2278
9e6e96a1 2279 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2280 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2281 WM8994_FLL1_FRAC, reg);
8e9ddf81 2282
c7ebf932
MB		 2283 if (wm8994->fll_locked_irq) {
2284 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2285 msecs_to_jiffies(10));
2286 if (timeout == 0)
2287 dev_warn(codec->dev,
2288 "Timed out waiting for FLL lock\n");
2289 } else {
2290 msleep(5);
2291 }
4b7ed83a
MB		 2292 } else {
2293 if (was_enabled) {
2294 switch (control->type) {
2295 case WM8994:
2296 vmid_dereference(codec);
2297 break;
2298 case WM8958:
da445afe 2299 if (control->revision < 1)
4b7ed83a
MB		 2300 vmid_dereference(codec);
2301 break;
2302 default:
2303 break;
2304 }
af6b6fe4
MB		 2305
2306 active_dereference(codec);
4b7ed83a 2307 }
9e6e96a1
MB		 2308 }
2309
20dc24a9 2310out:
9e6e96a1
MB		 2311 wm8994->fll[id].in = freq_in;
2312 wm8994->fll[id].out = freq_out;
136ff2a2 2313 wm8994->fll[id].src = src;
9e6e96a1 2314
9e6e96a1
MB		 2315 configure_clock(codec);
2316
cd22000a
MB		 2317 /*
2318 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2319 * for detection.
2320 */
2321 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2322 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2323
2324 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2325 & WM8994_AIF1CLK_RATE_MASK;
2326 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2327 & WM8994_AIF1CLK_RATE_MASK;
2328
cd22000a
MB		 2329 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2330 WM8994_AIF1CLK_RATE_MASK, 0x1);
2331 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2332 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2333 } else if (wm8994->aifdiv[0]) {
2334 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2335 WM8994_AIF1CLK_RATE_MASK,
2336 wm8994->aifdiv[0]);
2337 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2338 WM8994_AIF2CLK_RATE_MASK,
2339 wm8994->aifdiv[1]);
2340
2341 wm8994->aifdiv[0] = 0;
2342 wm8994->aifdiv[1] = 0;
cd22000a
MB		 2343 }
2344
9e6e96a1
MB		 2345 return 0;
2346}
2347
c7ebf932
MB		 2348static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2349{
2350 struct completion *completion = data;
2351
2352 complete(completion);
2353
2354 return IRQ_HANDLED;
2355}
f0fba2ad 2356
66b47fdb
MB		 2357static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2358
f0fba2ad
LG		 2359static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2360 unsigned int freq_in, unsigned int freq_out)
2361{
2362 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2363}
2364
9e6e96a1
MB		 2365static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2366 int clk_id, unsigned int freq, int dir)
2367{
2368 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2369 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2370 int i;
9e6e96a1
MB		 2371
2372 switch (dai->id) {
2373 case 1:
2374 case 2:
2375 break;
2376
2377 default:
2378 /* AIF3 shares clocking with AIF1/2 */
2379 return -EINVAL;
2380 }
2381
2382 switch (clk_id) {
2383 case WM8994_SYSCLK_MCLK1:
2384 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2385 wm8994->mclk[0] = freq;
2386 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2387 dai->id, freq);
2388 break;
2389
2390 case WM8994_SYSCLK_MCLK2:
2391 /* TODO: Set GPIO AF */
2392 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2393 wm8994->mclk[1] = freq;
2394 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2395 dai->id, freq);
2396 break;
2397
2398 case WM8994_SYSCLK_FLL1:
2399 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2400 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2401 break;
2402
2403 case WM8994_SYSCLK_FLL2:
2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2405 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2406 break;
2407
66b47fdb
MB		 2408 case WM8994_SYSCLK_OPCLK:
2409 /* Special case - a division (times 10) is given and
c1a4ecd9 2410 * no effect on main clocking.
66b47fdb
MB		 2411 */
2412 if (freq) {
2413 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2414 if (opclk_divs[i] == freq)
2415 break;
2416 if (i == ARRAY_SIZE(opclk_divs))
2417 return -EINVAL;
2418 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2419 WM8994_OPCLK_DIV_MASK, i);
2420 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2421 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2422 } else {
2423 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2424 WM8994_OPCLK_ENA, 0);
2425 }
2426
9e6e96a1
MB		 2427 default:
2428 return -EINVAL;
2429 }
2430
2431 configure_clock(codec);
2432
6730049a
MB		 2433 /*
2434 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2435 * for detection.
2436 */
2437 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2438 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2439
2440 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2441 & WM8994_AIF1CLK_RATE_MASK;
2442 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2443 & WM8994_AIF1CLK_RATE_MASK;
2444
6730049a
MB		 2445 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2446 WM8994_AIF1CLK_RATE_MASK, 0x1);
2447 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2448 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2449 } else if (wm8994->aifdiv[0]) {
2450 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451 WM8994_AIF1CLK_RATE_MASK,
2452 wm8994->aifdiv[0]);
2453 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2454 WM8994_AIF2CLK_RATE_MASK,
2455 wm8994->aifdiv[1]);
2456
2457 wm8994->aifdiv[0] = 0;
2458 wm8994->aifdiv[1] = 0;
6730049a
MB		 2459 }
2460
9e6e96a1
MB		 2461 return 0;
2462}
2463
2464static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2465 enum snd_soc_bias_level level)
2466{
b6b05691 2467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2468 struct wm8994 *control = wm8994->wm8994;
b6b05691 2469
5f2f3890
MB		 2470 wm_hubs_set_bias_level(codec, level);
2471
9e6e96a1
MB		 2472 switch (level) {
2473 case SND_SOC_BIAS_ON:
2474 break;
2475
2476 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2477 /* MICBIAS into regulating mode */
2478 switch (control->type) {
2479 case WM8958:
2480 case WM1811:
2481 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2482 WM8958_MICB1_MODE, 0);
2483 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2484 WM8958_MICB2_MODE, 0);
2485 break;
2486 default:
2487 break;
2488 }
af6b6fe4
MB		 2489
2490 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2491 active_reference(codec);
9e6e96a1
MB		 2492 break;
2493
2494 case SND_SOC_BIAS_STANDBY:
ce6120cc 2495 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2496 switch (control->type) {
8bc3c2c2 2497 case WM8958:
da445afe 2498 if (control->revision == 0) {
8bc3c2c2 2499 /* Optimise performance for rev A */
8bc3c2c2
MB		 2500 snd_soc_update_bits(codec,
2501 WM8958_CHARGE_PUMP_2,
2502 WM8958_CP_DISCH,
2503 WM8958_CP_DISCH);
2504 }
2505 break;
81204c84 2506
462835e4 2507 default:
81204c84 2508 break;
b6b05691 2509 }
9e6e96a1
MB		 2510
2511 /* Discharge LINEOUT1 & 2 */
2512 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2513 WM8994_LINEOUT1_DISCH |
2514 WM8994_LINEOUT2_DISCH,
2515 WM8994_LINEOUT1_DISCH |
2516 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2517 }
2518
af6b6fe4
MB		 2519 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2520 active_dereference(codec);
2521
500fa30e
MB		 2522 /* MICBIAS into bypass mode on newer devices */
2523 switch (control->type) {
2524 case WM8958:
2525 case WM1811:
2526 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2527 WM8958_MICB1_MODE,
2528 WM8958_MICB1_MODE);
2529 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2530 WM8958_MICB2_MODE,
2531 WM8958_MICB2_MODE);
2532 break;
2533 default:
2534 break;
2535 }
9e6e96a1
MB		 2536 break;
2537
2538 case SND_SOC_BIAS_OFF:
4105ab84 2539 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2540 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2541 break;
2542 }
5f2f3890 2543
ce6120cc 2544 codec->dapm.bias_level = level;
af6b6fe4 2545
22f8d055
MB		 2546 return 0;
2547}
2548
2549int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2550{
2551 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2552
2553 switch (mode) {
2554 case WM8994_VMID_NORMAL:
2555 if (wm8994->hubs.lineout1_se) {
2556 snd_soc_dapm_disable_pin(&codec->dapm,
2557 "LINEOUT1N Driver");
2558 snd_soc_dapm_disable_pin(&codec->dapm,
2559 "LINEOUT1P Driver");
2560 }
2561 if (wm8994->hubs.lineout2_se) {
2562 snd_soc_dapm_disable_pin(&codec->dapm,
2563 "LINEOUT2N Driver");
2564 snd_soc_dapm_disable_pin(&codec->dapm,
2565 "LINEOUT2P Driver");
2566 }
2567
2568 /* Do the sync with the old mode to allow it to clean up */
2569 snd_soc_dapm_sync(&codec->dapm);
2570 wm8994->vmid_mode = mode;
2571 break;
2572
2573 case WM8994_VMID_FORCE:
2574 if (wm8994->hubs.lineout1_se) {
2575 snd_soc_dapm_force_enable_pin(&codec->dapm,
2576 "LINEOUT1N Driver");
2577 snd_soc_dapm_force_enable_pin(&codec->dapm,
2578 "LINEOUT1P Driver");
2579 }
2580 if (wm8994->hubs.lineout2_se) {
2581 snd_soc_dapm_force_enable_pin(&codec->dapm,
2582 "LINEOUT2N Driver");
2583 snd_soc_dapm_force_enable_pin(&codec->dapm,
2584 "LINEOUT2P Driver");
2585 }
2586
2587 wm8994->vmid_mode = mode;
2588 snd_soc_dapm_sync(&codec->dapm);
2589 break;
2590
2591 default:
2592 return -EINVAL;
2593 }
2594
9e6e96a1
MB		 2595 return 0;
2596}
2597
2598static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2599{
2600 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2601 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2602 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2603 int ms_reg;
2604 int aif1_reg;
435705e8
MB		 2605 int dac_reg;
2606 int adc_reg;
9e6e96a1
MB		 2607 int ms = 0;
2608 int aif1 = 0;
435705e8 2609 int lrclk = 0;
9e6e96a1
MB		 2610
2611 switch (dai->id) {
2612 case 1:
2613 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2614 aif1_reg = WM8994_AIF1_CONTROL_1;
435705e8
MB		 2615 dac_reg = WM8994_AIF1DAC_LRCLK;
2616 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2617 break;
2618 case 2:
2619 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2620 aif1_reg = WM8994_AIF2_CONTROL_1;
435705e8
MB		 2621 dac_reg = WM8994_AIF1DAC_LRCLK;
2622 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2623 break;
2624 default:
2625 return -EINVAL;
2626 }
2627
2628 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2629 case SND_SOC_DAIFMT_CBS_CFS:
2630 break;
2631 case SND_SOC_DAIFMT_CBM_CFM:
2632 ms = WM8994_AIF1_MSTR;
2633 break;
2634 default:
2635 return -EINVAL;
2636 }
2637
2638 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2639 case SND_SOC_DAIFMT_DSP_B:
2640 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2641 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2642 case SND_SOC_DAIFMT_DSP_A:
2643 aif1 |= 0x18;
2644 break;
2645 case SND_SOC_DAIFMT_I2S:
2646 aif1 |= 0x10;
2647 break;
2648 case SND_SOC_DAIFMT_RIGHT_J:
2649 break;
2650 case SND_SOC_DAIFMT_LEFT_J:
2651 aif1 |= 0x8;
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2658 case SND_SOC_DAIFMT_DSP_A:
2659 case SND_SOC_DAIFMT_DSP_B:
2660 /* frame inversion not valid for DSP modes */
2661 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2662 case SND_SOC_DAIFMT_NB_NF:
2663 break;
2664 case SND_SOC_DAIFMT_IB_NF:
2665 aif1 |= WM8994_AIF1_BCLK_INV;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
2670 break;
2671
2672 case SND_SOC_DAIFMT_I2S:
2673 case SND_SOC_DAIFMT_RIGHT_J:
2674 case SND_SOC_DAIFMT_LEFT_J:
2675 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2676 case SND_SOC_DAIFMT_NB_NF:
2677 break;
2678 case SND_SOC_DAIFMT_IB_IF:
2679 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
435705e8 2680 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2681 break;
2682 case SND_SOC_DAIFMT_IB_NF:
2683 aif1 |= WM8994_AIF1_BCLK_INV;
2684 break;
2685 case SND_SOC_DAIFMT_NB_IF:
2686 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2687 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2688 break;
2689 default:
2690 return -EINVAL;
2691 }
2692 break;
2693 default:
2694 return -EINVAL;
2695 }
2696
c4431df0
MB		 2697 /* The AIF2 format configuration needs to be mirrored to AIF3
2698 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2699 switch (control->type) {
2700 case WM1811:
2701 case WM8958:
2702 if (dai->id == 2)
2703 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2704 WM8994_AIF1_LRCLK_INV |
2705 WM8958_AIF3_FMT_MASK, aif1);
2706 break;
2707
2708 default:
2709 break;
2710 }
c4431df0 2711
9e6e96a1
MB		 2712 snd_soc_update_bits(codec, aif1_reg,
2713 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2714 WM8994_AIF1_FMT_MASK,
2715 aif1);
2716 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2717 ms);
435705e8
MB		 2718 snd_soc_update_bits(codec, dac_reg,
2719 WM8958_AIF1_LRCLK_INV, lrclk);
2720 snd_soc_update_bits(codec, adc_reg,
2721 WM8958_AIF1_LRCLK_INV, lrclk);
9e6e96a1
MB		 2722
2723 return 0;
2724}
2725
2726static struct {
2727 int val, rate;
2728} srs[] = {
2729 { 0, 8000 },
2730 { 1, 11025 },
2731 { 2, 12000 },
2732 { 3, 16000 },
2733 { 4, 22050 },
2734 { 5, 24000 },
2735 { 6, 32000 },
2736 { 7, 44100 },
2737 { 8, 48000 },
2738 { 9, 88200 },
2739 { 10, 96000 },
2740};
2741
2742static int fs_ratios[] = {
2743 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2744};
2745
2746static int bclk_divs[] = {
2747 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2748 640, 880, 960, 1280, 1760, 1920
2749};
2750
2751static int wm8994_hw_params(struct snd_pcm_substream *substream,
2752 struct snd_pcm_hw_params *params,
2753 struct snd_soc_dai *dai)
2754{
2755 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2756 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3cf956ee
MB		 2757 struct wm8994 *control = wm8994->wm8994;
2758 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1 2759 int aif1_reg;
b1e43d93 2760 int aif2_reg;
9e6e96a1
MB		 2761 int bclk_reg;
2762 int lrclk_reg;
2763 int rate_reg;
2764 int aif1 = 0;
b1e43d93 2765 int aif2 = 0;
9e6e96a1
MB		 2766 int bclk = 0;
2767 int lrclk = 0;
2768 int rate_val = 0;
2769 int id = dai->id - 1;
2770
2771 int i, cur_val, best_val, bclk_rate, best;
2772
2773 switch (dai->id) {
2774 case 1:
2775 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2776 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2777 bclk_reg = WM8994_AIF1_BCLK;
2778 rate_reg = WM8994_AIF1_RATE;
2779 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2780 wm8994->lrclk_shared[0]) {
9e6e96a1 2781 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2782 } else {
9e6e96a1 2783 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2784 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2785 }
9e6e96a1
MB		 2786 break;
2787 case 2:
2788 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2789 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2790 bclk_reg = WM8994_AIF2_BCLK;
2791 rate_reg = WM8994_AIF2_RATE;
2792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2793 wm8994->lrclk_shared[1]) {
9e6e96a1 2794 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2795 } else {
9e6e96a1 2796 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2797 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2798 }
9e6e96a1
MB		 2799 break;
2800 default:
2801 return -EINVAL;
2802 }
2803
79748cdb 2804 bclk_rate = params_rate(params);
9e6e96a1
MB		 2805 switch (params_format(params)) {
2806 case SNDRV_PCM_FORMAT_S16_LE:
2807 bclk_rate *= 16;
2808 break;
2809 case SNDRV_PCM_FORMAT_S20_3LE:
2810 bclk_rate *= 20;
2811 aif1 |= 0x20;
2812 break;
2813 case SNDRV_PCM_FORMAT_S24_LE:
2814 bclk_rate *= 24;
2815 aif1 |= 0x40;
2816 break;
2817 case SNDRV_PCM_FORMAT_S32_LE:
2818 bclk_rate *= 32;
2819 aif1 |= 0x60;
2820 break;
2821 default:
2822 return -EINVAL;
2823 }
2824
79748cdb 2825 wm8994->channels[id] = params_channels(params);
3cf956ee
MB		 2826 if (pdata->max_channels_clocked[id] &&
2827 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2828 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2829 pdata->max_channels_clocked[id], wm8994->channels[id]);
2830 wm8994->channels[id] = pdata->max_channels_clocked[id];
2831 }
2832
2833 switch (wm8994->channels[id]) {
79748cdb
MB		 2834 case 1:
2835 case 2:
2836 bclk_rate *= 2;
2837 break;
2838 default:
2839 bclk_rate *= 4;
2840 break;
2841 }
2842
9e6e96a1
MB		 2843 /* Try to find an appropriate sample rate; look for an exact match. */
2844 for (i = 0; i < ARRAY_SIZE(srs); i++)
2845 if (srs[i].rate == params_rate(params))
2846 break;
2847 if (i == ARRAY_SIZE(srs))
2848 return -EINVAL;
2849 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2850
2851 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2852 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2853 dai->id, wm8994->aifclk[id], bclk_rate);
2854
3cf956ee 2855 if (wm8994->channels[id] == 1 &&
b1e43d93
MB		 2856 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2857 aif2 |= WM8994_AIF1_MONO;
2858
9e6e96a1
MB		 2859 if (wm8994->aifclk[id] == 0) {
2860 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2861 return -EINVAL;
2862 }
2863
2864 /* AIFCLK/fs ratio; look for a close match in either direction */
2865 best = 0;
2866 best_val = abs((fs_ratios[0] * params_rate(params))
2867 - wm8994->aifclk[id]);
2868 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2869 cur_val = abs((fs_ratios[i] * params_rate(params))
2870 - wm8994->aifclk[id]);
2871 if (cur_val >= best_val)
2872 continue;
2873 best = i;
2874 best_val = cur_val;
2875 }
2876 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2877 dai->id, fs_ratios[best]);
2878 rate_val |= best;
2879
2880 /* We may not get quite the right frequency if using
2881 * approximate clocks so look for the closest match that is
2882 * higher than the target (we need to ensure that there enough
2883 * BCLKs to clock out the samples).
2884 */
2885 best = 0;
2886 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2887 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2888 if (cur_val < 0) /* BCLK table is sorted */
2889 break;
2890 best = i;
2891 }
07cd8ada 2892 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2893 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2894 bclk_divs[best], bclk_rate);
2895 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2896
2897 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2898 if (!lrclk) {
2899 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2900 bclk_rate);
2901 return -EINVAL;
2902 }
9e6e96a1
MB		 2903 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2904 lrclk, bclk_rate / lrclk);
2905
2906 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2907 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2908 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2909 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2910 lrclk);
2911 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2912 WM8994_AIF1CLK_RATE_MASK, rate_val);
2913
2914 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2915 switch (dai->id) {
2916 case 1:
2917 wm8994->dac_rates[0] = params_rate(params);
2918 wm8994_set_retune_mobile(codec, 0);
2919 wm8994_set_retune_mobile(codec, 1);
2920 break;
2921 case 2:
2922 wm8994->dac_rates[1] = params_rate(params);
2923 wm8994_set_retune_mobile(codec, 2);
2924 break;
2925 }
2926 }
2927
2928 return 0;
2929}
2930
c4431df0
MB		 2931static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2932 struct snd_pcm_hw_params *params,
2933 struct snd_soc_dai *dai)
2934{
2935 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2936 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2937 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2938 int aif1_reg;
2939 int aif1 = 0;
2940
2941 switch (dai->id) {
2942 case 3:
2943 switch (control->type) {
81204c84 2944 case WM1811:
c4431df0
MB		 2945 case WM8958:
2946 aif1_reg = WM8958_AIF3_CONTROL_1;
2947 break;
2948 default:
2949 return 0;
2950 }
4495e46f 2951 break;
c4431df0
MB		 2952 default:
2953 return 0;
2954 }
2955
2956 switch (params_format(params)) {
2957 case SNDRV_PCM_FORMAT_S16_LE:
2958 break;
2959 case SNDRV_PCM_FORMAT_S20_3LE:
2960 aif1 |= 0x20;
2961 break;
2962 case SNDRV_PCM_FORMAT_S24_LE:
2963 aif1 |= 0x40;
2964 break;
2965 case SNDRV_PCM_FORMAT_S32_LE:
2966 aif1 |= 0x60;
2967 break;
2968 default:
2969 return -EINVAL;
2970 }
2971
2972 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2973}
2974
9e6e96a1
MB		 2975static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2976{
2977 struct snd_soc_codec *codec = codec_dai->codec;
2978 int mute_reg;
2979 int reg;
2980
2981 switch (codec_dai->id) {
2982 case 1:
2983 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2984 break;
2985 case 2:
2986 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2987 break;
2988 default:
2989 return -EINVAL;
2990 }
2991
2992 if (mute)
2993 reg = WM8994_AIF1DAC1_MUTE;
2994 else
2995 reg = 0;
2996
2997 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2998
2999 return 0;
3000}
3001
778a76e2
MB		 3002static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3003{
3004 struct snd_soc_codec *codec = codec_dai->codec;
3005 int reg, val, mask;
3006
3007 switch (codec_dai->id) {
3008 case 1:
3009 reg = WM8994_AIF1_MASTER_SLAVE;
3010 mask = WM8994_AIF1_TRI;
3011 break;
3012 case 2:
3013 reg = WM8994_AIF2_MASTER_SLAVE;
3014 mask = WM8994_AIF2_TRI;
3015 break;
778a76e2
MB		 3016 default:
3017 return -EINVAL;
3018 }
3019
3020 if (tristate)
3021 val = mask;
3022 else
3023 val = 0;
3024
78b3fb46 3025 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 3026}
3027
d09f3ecf
MB		 3028static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3029{
3030 struct snd_soc_codec *codec = dai->codec;
3031
3032 /* Disable the pulls on the AIF if we're using it to save power. */
3033 snd_soc_update_bits(codec, WM8994_GPIO_3,
3034 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3035 snd_soc_update_bits(codec, WM8994_GPIO_4,
3036 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3037 snd_soc_update_bits(codec, WM8994_GPIO_5,
3038 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3039
3040 return 0;
3041}
3042
9e6e96a1
MB		 3043#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3044
3045#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 3046 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 3047
85e7652d 3048static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 3049 .set_sysclk = wm8994_set_dai_sysclk,
3050 .set_fmt = wm8994_set_dai_fmt,
3051 .hw_params = wm8994_hw_params,
3052 .digital_mute = wm8994_aif_mute,
3053 .set_pll = wm8994_set_fll,
778a76e2 3054 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 3055};
3056
85e7652d 3057static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 3058 .set_sysclk = wm8994_set_dai_sysclk,
3059 .set_fmt = wm8994_set_dai_fmt,
3060 .hw_params = wm8994_hw_params,
3061 .digital_mute = wm8994_aif_mute,
3062 .set_pll = wm8994_set_fll,
778a76e2
MB		 3063 .set_tristate = wm8994_set_tristate,
3064};
3065
85e7652d 3066static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 3067 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 3068};
3069
f0fba2ad 3070static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 3071 {
f0fba2ad 3072 .name = "wm8994-aif1",
8c7f78b3 3073 .id = 1,
9e6e96a1
MB		 3074 .playback = {
3075 .stream_name = "AIF1 Playback",
b1e43d93 3076 .channels_min = 1,
9e6e96a1
MB		 3077 .channels_max = 2,
3078 .rates = WM8994_RATES,
3079 .formats = WM8994_FORMATS,
99b0292d 3080 .sig_bits = 24,
9e6e96a1
MB		 3081 },
3082 .capture = {
3083 .stream_name = "AIF1 Capture",
b1e43d93 3084 .channels_min = 1,
9e6e96a1
MB		 3085 .channels_max = 2,
3086 .rates = WM8994_RATES,
3087 .formats = WM8994_FORMATS,
99b0292d 3088 .sig_bits = 24,
9e6e96a1
MB		 3089 },
3090 .ops = &wm8994_aif1_dai_ops,
3091 },
3092 {
f0fba2ad 3093 .name = "wm8994-aif2",
8c7f78b3 3094 .id = 2,
9e6e96a1
MB		 3095 .playback = {
3096 .stream_name = "AIF2 Playback",
b1e43d93 3097 .channels_min = 1,
9e6e96a1
MB		 3098 .channels_max = 2,
3099 .rates = WM8994_RATES,
3100 .formats = WM8994_FORMATS,
99b0292d 3101 .sig_bits = 24,
9e6e96a1
MB		 3102 },
3103 .capture = {
3104 .stream_name = "AIF2 Capture",
b1e43d93 3105 .channels_min = 1,
9e6e96a1
MB		 3106 .channels_max = 2,
3107 .rates = WM8994_RATES,
3108 .formats = WM8994_FORMATS,
99b0292d 3109 .sig_bits = 24,
9e6e96a1 3110 },
d09f3ecf 3111 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 3112 .ops = &wm8994_aif2_dai_ops,
3113 },
3114 {
f0fba2ad 3115 .name = "wm8994-aif3",
8c7f78b3 3116 .id = 3,
9e6e96a1
MB		 3117 .playback = {
3118 .stream_name = "AIF3 Playback",
b1e43d93 3119 .channels_min = 1,
9e6e96a1
MB		 3120 .channels_max = 2,
3121 .rates = WM8994_RATES,
3122 .formats = WM8994_FORMATS,
99b0292d 3123 .sig_bits = 24,
9e6e96a1 3124 },
a8462bde 3125 .capture = {
9e6e96a1 3126 .stream_name = "AIF3 Capture",
b1e43d93 3127 .channels_min = 1,
9e6e96a1
MB		 3128 .channels_max = 2,
3129 .rates = WM8994_RATES,
3130 .formats = WM8994_FORMATS,
99b0292d
MB		 3131 .sig_bits = 24,
3132 },
778a76e2 3133 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3134 }
3135};
9e6e96a1
MB		 3136
3137#ifdef CONFIG_PM
4752a887 3138static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3139{
b2c812e2 3140 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3141 int i, ret;
3142
3143 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3144 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3145 sizeof(struct wm8994_fll_config));
f0fba2ad 3146 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3147 if (ret < 0)
3148 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3149 i + 1, ret);
3150 }
3151
3152 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3153
3154 return 0;
3155}
3156
4752a887 3157static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3158{
b2c812e2 3159 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3160 int i, ret;
3161
9e6e96a1 3162 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3163 if (!wm8994->fll_suspend[i].out)
3164 continue;
3165
f0fba2ad 3166 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3167 wm8994->fll_suspend[i].src,
3168 wm8994->fll_suspend[i].in,
3169 wm8994->fll_suspend[i].out);
3170 if (ret < 0)
3171 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3172 i + 1, ret);
3173 }
3174
3175 return 0;
3176}
3177#else
4752a887
MB		 3178#define wm8994_codec_suspend NULL
3179#define wm8994_codec_resume NULL
9e6e96a1
MB		 3180#endif
3181
3182static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3183{
8cb8e83b 3184 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3185 struct wm8994 *control = wm8994->wm8994;
3186 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3187 struct snd_kcontrol_new controls[] = {
3188 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3189 wm8994->retune_mobile_enum,
3190 wm8994_get_retune_mobile_enum,
3191 wm8994_put_retune_mobile_enum),
3192 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3193 wm8994->retune_mobile_enum,
3194 wm8994_get_retune_mobile_enum,
3195 wm8994_put_retune_mobile_enum),
3196 SOC_ENUM_EXT("AIF2 EQ Mode",
3197 wm8994->retune_mobile_enum,
3198 wm8994_get_retune_mobile_enum,
3199 wm8994_put_retune_mobile_enum),
3200 };
3201 int ret, i, j;
3202 const char **t;
3203
3204 /* We need an array of texts for the enum API but the number
3205 * of texts is likely to be less than the number of
3206 * configurations due to the sample rate dependency of the
3207 * configurations. */
3208 wm8994->num_retune_mobile_texts = 0;
3209 wm8994->retune_mobile_texts = NULL;
3210 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3211 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3212 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3213 wm8994->retune_mobile_texts[j]) == 0)
3214 break;
3215 }
3216
3217 if (j != wm8994->num_retune_mobile_texts)
3218 continue;
3219
3220 /* Expand the array... */
3221 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3222 sizeof(char *) *
9e6e96a1
MB		 3223 (wm8994->num_retune_mobile_texts + 1),
3224 GFP_KERNEL);
3225 if (t == NULL)
3226 continue;
3227
3228 /* ...store the new entry... */
c1a4ecd9 3229 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3230 pdata->retune_mobile_cfgs[i].name;
3231
3232 /* ...and remember the new version. */
3233 wm8994->num_retune_mobile_texts++;
3234 wm8994->retune_mobile_texts = t;
3235 }
3236
3237 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3238 wm8994->num_retune_mobile_texts);
3239
3240 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3241 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3242
8cb8e83b 3243 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3244 ARRAY_SIZE(controls));
3245 if (ret != 0)
8cb8e83b 3246 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3247 "Failed to add ReTune Mobile controls: %d\n", ret);
3248}
3249
3250static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3251{
8cb8e83b 3252 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3253 struct wm8994 *control = wm8994->wm8994;
3254 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3255 int ret, i;
3256
3257 if (!pdata)
3258 return;
3259
3260 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3261 pdata->lineout2_diff,
3262 pdata->lineout1fb,
3263 pdata->lineout2fb,
3264 pdata->jd_scthr,
3265 pdata->jd_thr,
02e79476
MB		 3266 pdata->micb1_delay,
3267 pdata->micb2_delay,
9e6e96a1
MB		 3268 pdata->micbias1_lvl,
3269 pdata->micbias2_lvl);
3270
3271 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3272
3273 if (pdata->num_drc_cfgs) {
3274 struct snd_kcontrol_new controls[] = {
3275 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3276 wm8994_get_drc_enum, wm8994_put_drc_enum),
3277 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3278 wm8994_get_drc_enum, wm8994_put_drc_enum),
3279 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3280 wm8994_get_drc_enum, wm8994_put_drc_enum),
3281 };
3282
3283 /* We need an array of texts for the enum API */
8cb8e83b 3284 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3285 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3286 if (!wm8994->drc_texts) {
8cb8e83b 3287 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3288 "Failed to allocate %d DRC config texts\n",
3289 pdata->num_drc_cfgs);
3290 return;
3291 }
3292
3293 for (i = 0; i < pdata->num_drc_cfgs; i++)
3294 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3295
3296 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3297 wm8994->drc_enum.texts = wm8994->drc_texts;
3298
8cb8e83b 3299 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3300 ARRAY_SIZE(controls));
9e6e96a1
MB		 3301 for (i = 0; i < WM8994_NUM_DRC; i++)
3302 wm8994_set_drc(codec, i);
45a690f6
MB		 3303 } else {
3304 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3305 wm8994_drc_controls,
3306 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3307 }
3308
45a690f6
MB		 3309 if (ret != 0)
3310 dev_err(wm8994->hubs.codec->dev,
3311 "Failed to add DRC mode controls: %d\n", ret);
3312
3313
9e6e96a1
MB		 3314 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3315 pdata->num_retune_mobile_cfgs);
3316
3317 if (pdata->num_retune_mobile_cfgs)
3318 wm8994_handle_retune_mobile_pdata(wm8994);
3319 else
8cb8e83b 3320 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3321 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3322
3323 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3324 if (pdata->micbias[i]) {
3325 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3326 pdata->micbias[i] & 0xffff);
3327 }
3328 }
9e6e96a1
MB		 3329}
3330
88766984
MB		 3331/**
3332 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3333 *
3334 * @codec: WM8994 codec
3335 * @jack: jack to report detection events on
3336 * @micbias: microphone bias to detect on
88766984
MB		 3337 *
3338 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3339 * being used to bring out signals to the processor then only platform
5ab230a7 3340 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3341 * be configured using snd_soc_jack_add_gpios() instead.
3342 *
3343 * Configuration of detection levels is available via the micbias1_lvl
3344 * and micbias2_lvl platform data members.
3345 */
3346int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3347 int micbias)
88766984 3348{
b2c812e2 3349 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3350 struct wm8994_micdet *micdet;
2a8a856d 3351 struct wm8994 *control = wm8994->wm8994;
87092e3c 3352 int reg, ret;
88766984 3353
87092e3c
MB		 3354 if (control->type != WM8994) {
3355 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3356 return -EINVAL;
87092e3c 3357 }
3a423157 3358
88766984
MB		 3359 switch (micbias) {
3360 case 1:
3361 micdet = &wm8994->micdet[0];
87092e3c
MB		 3362 if (jack)
3363 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3364 "MICBIAS1");
3365 else
3366 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3367 "MICBIAS1");
88766984
MB		 3368 break;
3369 case 2:
3370 micdet = &wm8994->micdet[1];
87092e3c
MB		 3371 if (jack)
3372 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3373 "MICBIAS1");
3374 else
3375 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3376 "MICBIAS1");
88766984
MB		 3377 break;
3378 default:
87092e3c 3379 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3380 return -EINVAL;
87092e3c 3381 }
88766984 3382
87092e3c
MB		 3383 if (ret != 0)
3384 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3385 micbias, ret);
3386
3387 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3388 micbias, jack);
88766984
MB		 3389
3390 /* Store the configuration */
3391 micdet->jack = jack;
87092e3c 3392 micdet->detecting = true;
88766984
MB		 3393
3394 /* If either of the jacks is set up then enable detection */
3395 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3396 reg = WM8994_MICD_ENA;
87092e3c 3397 else
88766984
MB		 3398 reg = 0;
3399
3400 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3401
d9f34df7
CR		 3402 /* enable MICDET and MICSHRT deboune */
3403 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3404 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3405 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3406 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3407
87092e3c
MB		 3408 snd_soc_dapm_sync(&codec->dapm);
3409
88766984
MB		 3410 return 0;
3411}
3412EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3413
e9b54de4 3414static void wm8994_mic_work(struct work_struct *work)
88766984 3415{
e9b54de4
MB		 3416 struct wm8994_priv *priv = container_of(work,
3417 struct wm8994_priv,
3418 mic_work.work);
fdfc4f3e
MB		 3419 struct regmap *regmap = priv->wm8994->regmap;
3420 struct device *dev = priv->wm8994->dev;
3421 unsigned int reg;
3422 int ret;
88766984
MB		 3423 int report;
3424
b8176627
MB		 3425 pm_runtime_get_sync(dev);
3426
fdfc4f3e
MB		 3427 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3428 if (ret < 0) {
3429 dev_err(dev, "Failed to read microphone status: %d\n",
3430 ret);
b8176627 3431 pm_runtime_put(dev);
e9b54de4 3432 return;
88766984
MB		 3433 }
3434
fdfc4f3e 3435 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3436
3437 report = 0;
87092e3c
MB		 3438 if (reg & WM8994_MIC1_DET_STS) {
3439 if (priv->micdet[0].detecting)
3440 report = SND_JACK_HEADSET;
3441 }
3442 if (reg & WM8994_MIC1_SHRT_STS) {
3443 if (priv->micdet[0].detecting)
3444 report = SND_JACK_HEADPHONE;
3445 else
3446 report |= SND_JACK_BTN_0;
3447 }
3448 if (report)
3449 priv->micdet[0].detecting = false;
3450 else
3451 priv->micdet[0].detecting = true;
3452
88766984 3453 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3454 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3455
3456 report = 0;
87092e3c
MB		 3457 if (reg & WM8994_MIC2_DET_STS) {
3458 if (priv->micdet[1].detecting)
3459 report = SND_JACK_HEADSET;
3460 }
3461 if (reg & WM8994_MIC2_SHRT_STS) {
3462 if (priv->micdet[1].detecting)
3463 report = SND_JACK_HEADPHONE;
3464 else
3465 report |= SND_JACK_BTN_0;
3466 }
3467 if (report)
3468 priv->micdet[1].detecting = false;
3469 else
3470 priv->micdet[1].detecting = true;
3471
88766984 3472 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3473 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3474
3475 pm_runtime_put(dev);
e9b54de4
MB		 3476}
3477
3478static irqreturn_t wm8994_mic_irq(int irq, void *data)
3479{
3480 struct wm8994_priv *priv = data;
8cb8e83b 3481 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3482
3483#ifndef CONFIG_SND_SOC_WM8994_MODULE
3484 trace_snd_soc_jack_irq(dev_name(codec->dev));
3485#endif
3486
3487 pm_wakeup_event(codec->dev, 300);
3488
3489 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3490
3491 return IRQ_HANDLED;
3492}
3493
f02b0de0
MB		 3494static void wm1811_micd_stop(struct snd_soc_codec *codec)
3495{
3496 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3497
3498 if (!wm8994->jackdet)
3499 return;
3500
3501 mutex_lock(&wm8994->accdet_lock);
3502
3503 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3504
3505 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3506
3507 mutex_unlock(&wm8994->accdet_lock);
3508
3509 if (wm8994->wm8994->pdata.jd_ext_cap)
3510 snd_soc_dapm_disable_pin(&codec->dapm,
3511 "MICBIAS2");
3512}
3513
78b76dbe 3514static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3515{
821edd2f 3516 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3517 int report;
821edd2f 3518
78b76dbe
MB		 3519 report = 0;
3520 if (status & 0x4)
3521 report |= SND_JACK_BTN_0;
3522
3523 if (status & 0x8)
3524 report |= SND_JACK_BTN_1;
3525
3526 if (status & 0x10)
3527 report |= SND_JACK_BTN_2;
3528
3529 if (status & 0x20)
3530 report |= SND_JACK_BTN_3;
3531
3532 if (status & 0x40)
3533 report |= SND_JACK_BTN_4;
3534
3535 if (status & 0x80)
3536 report |= SND_JACK_BTN_5;
3537
3538 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3539 wm8994->btn_mask);
3540}
3541
70bd3b29
MB		 3542static void wm8958_open_circuit_work(struct work_struct *work)
3543{
3544 struct wm8994_priv *wm8994 = container_of(work,
3545 struct wm8994_priv,
3546 open_circuit_work.work);
3547 struct device *dev = wm8994->wm8994->dev;
3548
3549 wm1811_micd_stop(wm8994->hubs.codec);
3550
3551 mutex_lock(&wm8994->accdet_lock);
3552
3553 dev_dbg(dev, "Reporting open circuit\n");
3554
3555 wm8994->jack_mic = false;
3556 wm8994->mic_detecting = true;
3557
3558 wm8958_micd_set_rate(wm8994->hubs.codec);
3559
3560 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3561 wm8994->btn_mask |
3562 SND_JACK_HEADSET);
3563
3564 mutex_unlock(&wm8994->accdet_lock);
3565}
3566
98869f68 3567static void wm8958_mic_id(void *data, u16 status)
78b76dbe 3568{
98869f68 3569 struct snd_soc_codec *codec = data;
78b76dbe 3570 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3571
af6b6fe4 3572 /* Either nothing present or just starting detection */
b00adf76 3573 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB		 3574 /* If nothing present then clear our statuses */
3575 dev_dbg(codec->dev, "Detected open circuit\n");
b00adf76 3576
70bd3b29
MB		 3577 schedule_delayed_work(&wm8994->open_circuit_work,
3578 msecs_to_jiffies(2500));
b00adf76
MB		 3579 return;
3580 }
821edd2f 3581
b00adf76
MB		 3582 /* If the measurement is showing a high impedence we've got a
3583 * microphone.
3584 */
78b76dbe 3585 if (status & 0x600) {
b00adf76
MB		 3586 dev_dbg(codec->dev, "Detected microphone\n");
3587
157a75e6 3588 wm8994->mic_detecting = false;
b00adf76
MB		 3589 wm8994->jack_mic = true;
3590
3591 wm8958_micd_set_rate(codec);
3592
3593 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3594 SND_JACK_HEADSET);
3595 }
821edd2f 3596
b00adf76 3597
78b76dbe 3598 if (status & 0xfc) {
b00adf76 3599 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3600 wm8994->mic_detecting = false;
b00adf76
MB		 3601
3602 wm8958_micd_set_rate(codec);
3603
af6b6fe4 3604 /* If we have jackdet that will detect removal */
f02b0de0 3605 wm1811_micd_stop(codec);
ecd1732f
MB		 3606
3607 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3608 SND_JACK_HEADSET);
b00adf76 3609 }
821edd2f 3610}
b00adf76 3611
c0cc3f16
MB		 3612/* Deferred mic detection to allow for extra settling time */
3613static void wm1811_mic_work(struct work_struct *work)
3614{
3615 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3616 mic_work.work);
d9dd4ada 3617 struct wm8994 *control = wm8994->wm8994;
c0cc3f16 3618 struct snd_soc_codec *codec = wm8994->hubs.codec;
4585790d 3619
c0cc3f16 3620 pm_runtime_get_sync(codec->dev);
4585790d 3621
c0cc3f16 3622 /* If required for an external cap force MICBIAS on */
d9dd4ada 3623 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3624 snd_soc_dapm_force_enable_pin(&codec->dapm,
3625 "MICBIAS2");
3626 snd_soc_dapm_sync(&codec->dapm);
3627 }
4585790d 3628
c0cc3f16 3629 mutex_lock(&wm8994->accdet_lock);
4585790d 3630
c0cc3f16 3631 dev_dbg(codec->dev, "Starting mic detection\n");
4585790d 3632
63dd5452
MB		 3633 /* Use a user-supplied callback if we have one */
3634 if (wm8994->micd_cb) {
3635 wm8994->micd_cb(wm8994->micd_cb_data);
3636 } else {
3637 /*
3638 * Start off measument of microphone impedence to find out
3639 * what's actually there.
3640 */
3641 wm8994->mic_detecting = true;
3642 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
4585790d 3643
63dd5452
MB		 3644 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3645 WM8958_MICD_ENA, WM8958_MICD_ENA);
b00adf76 3646 }
c0cc3f16
MB		 3647
3648 mutex_unlock(&wm8994->accdet_lock);
3649
3650 pm_runtime_put(codec->dev);
821edd2f
MB		 3651}
3652
af6b6fe4
MB		 3653static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3654{
3655 struct wm8994_priv *wm8994 = data;
d9dd4ada 3656 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3657 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3658 int reg, delay;
c986564b 3659 bool present;
af6b6fe4 3660
b8176627
MB		 3661 pm_runtime_get_sync(codec->dev);
3662
2da1c4bf
MB		 3663 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3664
af6b6fe4
MB		 3665 mutex_lock(&wm8994->accdet_lock);
3666
3667 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3668 if (reg < 0) {
3669 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3670 mutex_unlock(&wm8994->accdet_lock);
b8176627 3671 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3672 return IRQ_NONE;
3673 }
3674
3675 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3676
c986564b 3677 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3678
c986564b
MB		 3679 if (present) {
3680 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3681
e9d9a968
MB		 3682 wm8958_micd_set_rate(codec);
3683
55a27786
MB		 3684 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3685 WM8958_MICB2_DISCH, 0);
3686
378ec0ca
MB		 3687 /* Disable debounce while inserted */
3688 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3689 WM1811_JACKDET_DB, 0);
3690
d9dd4ada 3691 delay = control->pdata.micdet_delay;
c0cc3f16
MB		 3692 schedule_delayed_work(&wm8994->mic_work,
3693 msecs_to_jiffies(delay));
af6b6fe4
MB		 3694 } else {
3695 dev_dbg(codec->dev, "Jack not detected\n");
3696
c0cc3f16
MB		 3697 cancel_delayed_work_sync(&wm8994->mic_work);
3698
55a27786
MB		 3699 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3700 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3701
378ec0ca
MB		 3702 /* Enable debounce while removed */
3703 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3704 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3705
af6b6fe4
MB		 3706 wm8994->mic_detecting = false;
3707 wm8994->jack_mic = false;
3708 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3709 WM8958_MICD_ENA, 0);
3710 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3711 }
3712
3713 mutex_unlock(&wm8994->accdet_lock);
3714
c0cc3f16 3715 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3716 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3717 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3718
3719 if (present)
3720 snd_soc_jack_report(wm8994->micdet[0].jack,
3721 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3722 else
3723 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3724 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3725 wm8994->btn_mask);
3726
99af79df
MB		 3727 /* Since we only report deltas force an update, ensures we
3728 * avoid bootstrapping issues with the core. */
3729 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3730
b8176627 3731 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3732 return IRQ_HANDLED;
3733}
3734
99af79df
MB		 3735static void wm1811_jackdet_bootstrap(struct work_struct *work)
3736{
3737 struct wm8994_priv *wm8994 = container_of(work,
3738 struct wm8994_priv,
3739 jackdet_bootstrap.work);
3740 wm1811_jackdet_irq(0, wm8994);
3741}
3742
821edd2f
MB		 3743/**
3744 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3745 *
3746 * @codec: WM8958 codec
3747 * @jack: jack to report detection events on
3748 *
3749 * Enable microphone detection functionality for the WM8958. By
3750 * default simple detection which supports the detection of up to 6
3751 * buttons plus video and microphone functionality is supported.
3752 *
3753 * The WM8958 has an advanced jack detection facility which is able to
3754 * support complex accessory detection, especially when used in
3755 * conjunction with external circuitry. In order to provide maximum
3756 * flexiblity a callback is provided which allows a completely custom
3757 * detection algorithm.
3758 */
3759int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
98869f68
MB		 3760 wm1811_micdet_cb det_cb, void *det_cb_data,
3761 wm1811_mic_id_cb id_cb, void *id_cb_data)
821edd2f
MB		 3762{
3763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3764 struct wm8994 *control = wm8994->wm8994;
4585790d 3765 u16 micd_lvl_sel;
821edd2f 3766
81204c84
MB		 3767 switch (control->type) {
3768 case WM1811:
3769 case WM8958:
3770 break;
3771 default:
821edd2f 3772 return -EINVAL;
81204c84 3773 }
821edd2f
MB		 3774
3775 if (jack) {
4cdf5e49 3776 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3777 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3778
821edd2f 3779 wm8994->micdet[0].jack = jack;
821edd2f 3780
98869f68
MB		 3781 if (det_cb) {
3782 wm8994->micd_cb = det_cb;
3783 wm8994->micd_cb_data = det_cb_data;
63dd5452
MB		 3784 } else {
3785 wm8994->mic_detecting = true;
3786 wm8994->jack_mic = false;
3787 }
b00adf76 3788
98869f68
MB		 3789 if (id_cb) {
3790 wm8994->mic_id_cb = id_cb;
3791 wm8994->mic_id_cb_data = id_cb_data;
3792 } else {
3793 wm8994->mic_id_cb = wm8958_mic_id;
3794 wm8994->mic_id_cb_data = codec;
3795 }
b00adf76
MB		 3796
3797 wm8958_micd_set_rate(codec);
3798
4585790d 3799 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3800 if (control->pdata.micd_lvl_sel)
3801 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3802 else
3803 micd_lvl_sel = 0x41;
3804
3805 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3806 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3807 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3808
b00adf76 3809 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3810 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3811
af6b6fe4
MB		 3812 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3813
3814 /*
3815 * If we can use jack detection start off with that,
3816 * otherwise jump straight to microphone detection.
3817 */
3818 if (wm8994->jackdet) {
99af79df
MB		 3819 /* Disable debounce for the initial detect */
3820 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3821 WM1811_JACKDET_DB, 0);
3822
55a27786
MB		 3823 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3824 WM8958_MICB2_DISCH,
3825 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3826 snd_soc_update_bits(codec, WM8994_LDO_1,
3827 WM8994_LDO1_DISCH, 0);
3828 wm1811_jackdet_set_mode(codec,
3829 WM1811_JACKDET_MODE_JACK);
3830 } else {
3831 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3832 WM8958_MICD_ENA, WM8958_MICD_ENA);
3833 }
3834
821edd2f
MB		 3835 } else {
3836 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3837 WM8958_MICD_ENA, 0);
afaf1591 3838 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3839 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3840 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3841 }
3842
3843 return 0;
3844}
3845EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3846
2da1c4bf
MB		 3847static void wm8958_mic_work(struct work_struct *work)
3848{
3849 struct wm8994_priv *wm8994 = container_of(work,
3850 struct wm8994_priv,
3851 mic_complete_work.work);
3852 struct snd_soc_codec *codec = wm8994->hubs.codec;
3853
3854 dev_crit(codec->dev, "MIC WORK %x\n", wm8994->mic_status);
3855
3856 pm_runtime_get_sync(codec->dev);
3857
3858 mutex_lock(&wm8994->accdet_lock);
3859
3860 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3861
3862 mutex_unlock(&wm8994->accdet_lock);
3863
3864 pm_runtime_put(codec->dev);
3865
3866 dev_crit(codec->dev, "MIC WORK %x DONE\n", wm8994->mic_status);
3867}
3868
821edd2f
MB		 3869static irqreturn_t wm8958_mic_irq(int irq, void *data)
3870{
3871 struct wm8994_priv *wm8994 = data;
8cb8e83b 3872 struct snd_soc_codec *codec = wm8994->hubs.codec;
2da1c4bf 3873 int reg, count, ret, id_delay;
821edd2f 3874
af6b6fe4
MB		 3875 /*
3876 * Jack detection may have detected a removal simulataneously
3877 * with an update of the MICDET status; if so it will have
3878 * stopped detection and we can ignore this interrupt.
3879 */
c986564b 3880 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3881 return IRQ_HANDLED;
af6b6fe4 3882
2da1c4bf 3883 cancel_delayed_work_sync(&wm8994->mic_complete_work);
70bd3b29
MB		 3884 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3885
b8176627
MB		 3886 pm_runtime_get_sync(codec->dev);
3887
19940b3d
MB		 3888 /* We may occasionally read a detection without an impedence
3889 * range being provided - if that happens loop again.
3890 */
3891 count = 10;
3892 do {
3893 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3894 if (reg < 0) {
3895 dev_err(codec->dev,
3896 "Failed to read mic detect status: %d\n",
3897 reg);
b8176627 3898 pm_runtime_put(codec->dev);
19940b3d
MB		 3899 return IRQ_NONE;
3900 }
821edd2f 3901
19940b3d
MB		 3902 if (!(reg & WM8958_MICD_VALID)) {
3903 dev_dbg(codec->dev, "Mic detect data not valid\n");
3904 goto out;
3905 }
3906
3907 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3908 break;
3909
3910 msleep(1);
3911 } while (count--);
3912
3913 if (count == 0)
ec8f53fb 3914 dev_warn(codec->dev, "No impedance range reported for jack\n");
821edd2f 3915
7116f452 3916#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3917 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3918#endif
2bbb5d66 3919
e874de43
MB		 3920 /* Avoid a transient report when the accessory is being removed */
3921 if (wm8994->jackdet) {
8afd0ef2
MB		 3922 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3923 if (ret < 0) {
e874de43 3924 dev_err(codec->dev, "Failed to read jack status: %d\n",
8afd0ef2
MB		 3925 ret);
3926 } else if (!(ret & WM1811_JACKDET_LVL)) {
e874de43
MB		 3927 dev_dbg(codec->dev, "Ignoring removed jack\n");
3928 return IRQ_HANDLED;
3929 }
3930 }
3931
2da1c4bf
MB		 3932 wm8994->mic_status = reg;
3933 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3934
78b76dbe 3935 if (wm8994->mic_detecting)
2da1c4bf
MB		 3936 schedule_delayed_work(&wm8994->mic_complete_work,
3937 msecs_to_jiffies(id_delay));
821edd2f 3938 else
78b76dbe 3939 wm8958_button_det(codec, reg);
821edd2f
MB		 3940
3941out:
b8176627 3942 pm_runtime_put(codec->dev);
821edd2f
MB		 3943 return IRQ_HANDLED;
3944}
3945
3b1af3f8
MB		 3946static irqreturn_t wm8994_fifo_error(int irq, void *data)
3947{
3948 struct snd_soc_codec *codec = data;
3949
3950 dev_err(codec->dev, "FIFO error\n");
3951
3952 return IRQ_HANDLED;
3953}
3954
f0b182b0
MB		 3955static irqreturn_t wm8994_temp_warn(int irq, void *data)
3956{
3957 struct snd_soc_codec *codec = data;
3958
3959 dev_err(codec->dev, "Thermal warning\n");
3960
3961 return IRQ_HANDLED;
3962}
3963
3964static irqreturn_t wm8994_temp_shut(int irq, void *data)
3965{
3966 struct snd_soc_codec *codec = data;
3967
3968 dev_crit(codec->dev, "Thermal shutdown\n");
3969
3970 return IRQ_HANDLED;
3971}
3972
f0fba2ad 3973static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3974{
d9a7666f 3975 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3976 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3977 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3978 unsigned int reg;
ec62dbd7 3979 int ret, i;
9e6e96a1 3980
8cb8e83b 3981 wm8994->hubs.codec = codec;
d9a7666f 3982 codec->control_data = control->regmap;
9e6e96a1 3983
d9a7666f 3984 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3985
af6b6fe4 3986 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3987 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3988 wm1811_jackdet_bootstrap);
70bd3b29
MB		 3989 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
3990 wm8958_open_circuit_work);
af6b6fe4 3991
c0cc3f16
MB		 3992 switch (control->type) {
3993 case WM8994:
3994 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3995 break;
3996 case WM1811:
3997 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3998 break;
3999 default:
4000 break;
4001 }
4002
2da1c4bf
MB		 4003 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4004
c7ebf932
MB		 4005 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4006 init_completion(&wm8994->fll_locked[i]);
4007
d9dd4ada 4008 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 4009
39fb51a1 4010 pm_runtime_enable(codec->dev);
5fab5174 4011 pm_runtime_idle(codec->dev);
39fb51a1 4012
f959dee9
MB		 4013 /* By default use idle_bias_off, will override for WM8994 */
4014 codec->dapm.idle_bias_off = 1;
4015
9e6e96a1 4016 /* Set revision-specific configuration */
3a423157
MB		 4017 switch (control->type) {
4018 case WM8994:
f959dee9 4019 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 4020 if (!control->pdata.lineout1_diff ||
4021 !control->pdata.lineout2_diff)
f959dee9
MB		 4022 codec->dapm.idle_bias_off = 0;
4023
da445afe 4024 switch (control->revision) {
3a423157
MB		 4025 case 2:
4026 case 3:
4537c4e7
MB		 4027 wm8994->hubs.dcs_codes_l = -5;
4028 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 4029 wm8994->hubs.hp_startup_mode = 1;
4030 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 4031 wm8994->hubs.series_startup = 1;
3a423157
MB		 4032 break;
4033 default:
79ef0abc 4034 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 4035 break;
4036 }
280ec8b7 4037 break;
3a423157
MB		 4038
4039 case WM8958:
8437f700 4040 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 4041 wm8994->hubs.hp_startup_mode = 1;
20dc24a9 4042
da445afe 4043 switch (control->revision) {
20dc24a9
MB		 4044 case 0:
4045 break;
4046 default:
4047 wm8994->fll_byp = true;
4048 break;
4049 }
9e6e96a1 4050 break;
3a423157 4051
81204c84
MB		 4052 case WM1811:
4053 wm8994->hubs.dcs_readback_mode = 2;
4054 wm8994->hubs.no_series_update = 1;
29fdc360 4055 wm8994->hubs.hp_startup_mode = 1;
af31a227 4056 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 4057 wm8994->fll_byp = true;
81204c84 4058
72222be3
MB		 4059 wm8994->hubs.dcs_codes_l = -9;
4060 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 4061
4062 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4063 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4064 break;
4065
9e6e96a1
MB		 4066 default:
4067 break;
4068 }
9e6e96a1 4069
2a8a856d 4070 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 4071 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 4072 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 4073 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 4074 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 4075 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 4076
2a8a856d 4077 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 4078 wm_hubs_dcs_done, "DC servo done",
4079 &wm8994->hubs);
4080 if (ret == 0)
4081 wm8994->hubs.dcs_done_irq = true;
4082
3a423157
MB		 4083 switch (control->type) {
4084 case WM8994:
9b7c525d
MB		 4085 if (wm8994->micdet_irq) {
4086 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4087 wm8994_mic_irq,
4088 IRQF_TRIGGER_RISING,
4089 "Mic1 detect",
4090 wm8994);
4091 if (ret != 0)
4092 dev_warn(codec->dev,
4093 "Failed to request Mic1 detect IRQ: %d\n",
4094 ret);
4095 }
3a423157 4096
2a8a856d 4097 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4098 WM8994_IRQ_MIC1_SHRT,
4099 wm8994_mic_irq, "Mic 1 short",
4100 wm8994);
4101 if (ret != 0)
4102 dev_warn(codec->dev,
4103 "Failed to request Mic1 short IRQ: %d\n",
4104 ret);
4105
2a8a856d 4106 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4107 WM8994_IRQ_MIC2_DET,
4108 wm8994_mic_irq, "Mic 2 detect",
4109 wm8994);
4110 if (ret != 0)
4111 dev_warn(codec->dev,
4112 "Failed to request Mic2 detect IRQ: %d\n",
4113 ret);
4114
2a8a856d 4115 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4116 WM8994_IRQ_MIC2_SHRT,
4117 wm8994_mic_irq, "Mic 2 short",
4118 wm8994);
4119 if (ret != 0)
4120 dev_warn(codec->dev,
4121 "Failed to request Mic2 short IRQ: %d\n",
4122 ret);
4123 break;
821edd2f
MB		 4124
4125 case WM8958:
81204c84 4126 case WM1811:
9b7c525d
MB		 4127 if (wm8994->micdet_irq) {
4128 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4129 wm8958_mic_irq,
4130 IRQF_TRIGGER_RISING,
4131 "Mic detect",
4132 wm8994);
4133 if (ret != 0)
4134 dev_warn(codec->dev,
4135 "Failed to request Mic detect IRQ: %d\n",
4136 ret);
b4046d01
MB		 4137 } else {
4138 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4139 wm8958_mic_irq, "Mic detect",
4140 wm8994);
9b7c525d 4141 }
3a423157 4142 }
88766984 4143
af6b6fe4
MB		 4144 switch (control->type) {
4145 case WM1811:
da445afe 4146 if (control->cust_id > 1 || control->revision > 1) {
af6b6fe4
MB		 4147 ret = wm8994_request_irq(wm8994->wm8994,
4148 WM8994_IRQ_GPIO(6),
4149 wm1811_jackdet_irq, "JACKDET",
4150 wm8994);
4151 if (ret == 0)
4152 wm8994->jackdet = true;
4153 }
4154 break;
4155 default:
4156 break;
4157 }
4158
c7ebf932
MB		 4159 wm8994->fll_locked_irq = true;
4160 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 4161 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 4162 WM8994_IRQ_FLL1_LOCK + i,
4163 wm8994_fll_locked_irq, "FLL lock",
4164 &wm8994->fll_locked[i]);
4165 if (ret != 0)
4166 wm8994->fll_locked_irq = false;
4167 }
4168
27060b3c
MB		 4169 /* Make sure we can read from the GPIOs if they're inputs */
4170 pm_runtime_get_sync(codec->dev);
4171
9e6e96a1
MB		 4172 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4173 * configured on init - if a system wants to do this dynamically
4174 * at runtime we can deal with that then.
4175 */
d9a7666f 4176 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 4177 if (ret < 0) {
4178 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4179 goto err_irq;
9e6e96a1 4180 }
d9a7666f 4181 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4182 wm8994->lrclk_shared[0] = 1;
4183 wm8994_dai[0].symmetric_rates = 1;
4184 } else {
4185 wm8994->lrclk_shared[0] = 0;
4186 }
4187
d9a7666f 4188 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4189 if (ret < 0) {
4190 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4191 goto err_irq;
9e6e96a1 4192 }
d9a7666f 4193 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4194 wm8994->lrclk_shared[1] = 1;
4195 wm8994_dai[1].symmetric_rates = 1;
4196 } else {
4197 wm8994->lrclk_shared[1] = 0;
4198 }
4199
27060b3c
MB		 4200 pm_runtime_put(codec->dev);
4201
bfd37bb5
MB		 4202 /* Latch volume update bits */
4203 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4204 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4205 wm8994_vu_bits[i].mask,
4206 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4207
4208 /* Set the low bit of the 3D stereo depth so TLV matches */
4209 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4210 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4211 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4212 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4213 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4214 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4215 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4216 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4217 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4218
5b739670
MB		 4219 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4220 * use this; it only affects behaviour on idle TDM clock
4221 * cycles. */
4222 switch (control->type) {
4223 case WM8994:
4224 case WM8958:
4225 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4226 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4227 break;
4228 default:
4229 break;
4230 }
d1ce6b20 4231
500fa30e
MB		 4232 /* Put MICBIAS into bypass mode by default on newer devices */
4233 switch (control->type) {
4234 case WM8958:
4235 case WM1811:
4236 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4237 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4238 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4239 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4240 break;
4241 default:
4242 break;
4243 }
4244
c340304d
MB		 4245 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4246 wm_hubs_update_class_w(codec);
9e6e96a1 4247
f0fba2ad 4248 wm8994_handle_pdata(wm8994);
9e6e96a1 4249
f0fba2ad 4250 wm_hubs_add_analogue_controls(codec);
022658be 4251 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4252 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4253 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4254 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4255
4256 switch (control->type) {
4257 case WM8994:
4258 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4259 ARRAY_SIZE(wm8994_specific_dapm_widgets));
da445afe 4260 if (control->revision < 4) {
173efa09
DP		 4261 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4262 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4263 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4264 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4265 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4266 ARRAY_SIZE(wm8994_dac_revd_widgets));
4267 } else {
173efa09
DP		 4268 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4269 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4270 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4271 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4272 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4273 ARRAY_SIZE(wm8994_dac_widgets));
4274 }
c4431df0
MB		 4275 break;
4276 case WM8958:
022658be 4277 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4278 ARRAY_SIZE(wm8958_snd_controls));
4279 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4280 ARRAY_SIZE(wm8958_dapm_widgets));
da445afe 4281 if (control->revision < 1) {
780e2806
MB		 4282 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4283 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4284 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4285 ARRAY_SIZE(wm8994_adc_revd_widgets));
4286 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4287 ARRAY_SIZE(wm8994_dac_revd_widgets));
4288 } else {
4289 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4290 ARRAY_SIZE(wm8994_lateclk_widgets));
4291 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4292 ARRAY_SIZE(wm8994_adc_widgets));
4293 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4294 ARRAY_SIZE(wm8994_dac_widgets));
4295 }
c4431df0 4296 break;
81204c84
MB		 4297
4298 case WM1811:
022658be 4299 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4300 ARRAY_SIZE(wm8958_snd_controls));
4301 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4302 ARRAY_SIZE(wm8958_dapm_widgets));
4303 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4304 ARRAY_SIZE(wm8994_lateclk_widgets));
4305 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4306 ARRAY_SIZE(wm8994_adc_widgets));
4307 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4308 ARRAY_SIZE(wm8994_dac_widgets));
4309 break;
c4431df0 4310 }
c4431df0 4311
f0fba2ad 4312 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4313 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4314
c4431df0
MB		 4315 switch (control->type) {
4316 case WM8994:
4317 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4318 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4319
da445afe 4320 if (control->revision < 4) {
6ed8f148
MB		 4321 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4322 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4323 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4324 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4325 } else {
4326 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4327 ARRAY_SIZE(wm8994_lateclk_intercon));
4328 }
c4431df0
MB		 4329 break;
4330 case WM8958:
da445afe 4331 if (control->revision < 1) {
15676937
CR		 4332 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4333 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4334 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4335 ARRAY_SIZE(wm8994_revd_intercon));
4336 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4337 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4338 } else {
4339 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4340 ARRAY_SIZE(wm8994_lateclk_intercon));
4341 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4342 ARRAY_SIZE(wm8958_intercon));
4343 }
f701a2e5
MB		 4344
4345 wm8958_dsp2_init(codec);
c4431df0 4346 break;
81204c84
MB		 4347 case WM1811:
4348 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4349 ARRAY_SIZE(wm8994_lateclk_intercon));
4350 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4351 ARRAY_SIZE(wm8958_intercon));
4352 break;
c4431df0
MB		 4353 }
4354
9e6e96a1
MB		 4355 return 0;
4356
88766984 4357err_irq:
af6b6fe4
MB		 4358 if (wm8994->jackdet)
4359 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4360 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4361 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4362 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4363 if (wm8994->micdet_irq)
4364 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4365 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4366 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4367 &wm8994->fll_locked[i]);
2a8a856d 4368 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4369 &wm8994->hubs);
2a8a856d
MB		 4370 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4371 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4372 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4373
9e6e96a1
MB		 4374 return ret;
4375}
4376
34ff0f95 4377static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4378{
f0fba2ad 4379 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4380 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4381 int i;
9e6e96a1
MB		 4382
4383 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4384
39fb51a1
MB		 4385 pm_runtime_disable(codec->dev);
4386
c7ebf932 4387 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4388 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4389 &wm8994->fll_locked[i]);
4390
2a8a856d 4391 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4392 &wm8994->hubs);
2a8a856d
MB		 4393 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4394 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4395 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4396
af6b6fe4
MB		 4397 if (wm8994->jackdet)
4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4399
3a423157
MB		 4400 switch (control->type) {
4401 case WM8994:
9b7c525d
MB		 4402 if (wm8994->micdet_irq)
4403 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4404 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4405 wm8994);
2a8a856d 4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4407 wm8994);
2a8a856d 4408 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4409 wm8994);
4410 break;
821edd2f 4411
81204c84 4412 case WM1811:
821edd2f 4413 case WM8958:
9b7c525d
MB		 4414 if (wm8994->micdet_irq)
4415 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4416 break;
3a423157 4417 }
34ff0f95
JJ		 4418 release_firmware(wm8994->mbc);
4419 release_firmware(wm8994->mbc_vss);
4420 release_firmware(wm8994->enh_eq);
24fb2b11 4421 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4422 return 0;
4423}
4424
f0fba2ad
LG		 4425static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4426 .probe = wm8994_codec_probe,
4427 .remove = wm8994_codec_remove,
4752a887
MB		 4428 .suspend = wm8994_codec_suspend,
4429 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4430 .set_bias_level = wm8994_set_bias_level,
4431};
4432
7a79e94e 4433static int wm8994_probe(struct platform_device *pdev)
f0fba2ad 4434{
2bc16ed8
MB		 4435 struct wm8994_priv *wm8994;
4436
4437 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4438 GFP_KERNEL);
4439 if (wm8994 == NULL)
4440 return -ENOMEM;
4441 platform_set_drvdata(pdev, wm8994);
4442
4443 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4444
f0fba2ad
LG		 4445 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4446 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4447}
4448
7a79e94e 4449static int wm8994_remove(struct platform_device *pdev)
f0fba2ad
LG		 4450{
4451 snd_soc_unregister_codec(&pdev->dev);
4452 return 0;
4453}
4454
4752a887
MB		 4455#ifdef CONFIG_PM_SLEEP
4456static int wm8994_suspend(struct device *dev)
4457{
4458 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4459
4460 /* Drop down to power saving mode when system is suspended */
4461 if (wm8994->jackdet && !wm8994->active_refcount)
4462 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4463 WM1811_JACKDET_MODE_MASK,
4464 wm8994->jackdet_mode);
4465
4466 return 0;
4467}
4468
4469static int wm8994_resume(struct device *dev)
4470{
4471 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4472
78b76dbe 4473 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB		 4474 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4475 WM1811_JACKDET_MODE_MASK,
4476 WM1811_JACKDET_MODE_AUDIO);
4477
4478 return 0;
4479}
4480#endif
4481
4482static const struct dev_pm_ops wm8994_pm_ops = {
4483 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4484};
4485
9e6e96a1
MB		 4486static struct platform_driver wm8994_codec_driver = {
4487 .driver = {
4752a887
MB		 4488 .name = "wm8994-codec",
4489 .owner = THIS_MODULE,
4490 .pm = &wm8994_pm_ops,
4491 },
f0fba2ad 4492 .probe = wm8994_probe,
7a79e94e 4493 .remove = wm8994_remove,
9e6e96a1
MB		 4494};
4495
5bbcc3c0 4496module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4497
4498MODULE_DESCRIPTION("ASoC WM8994 driver");
4499MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4500MODULE_LICENSE("GPL");
4501MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
This page took 0.469179 seconds and 5 git commands to generate.