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ASoC: WM8903: Fix mic detection enable logic
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
9e6e96a1
MB		 41struct fll_config {
42 int src;
43 int in;
44 int out;
45};
46
47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
50static int wm8994_drc_base[] = {
51 WM8994_AIF1_DRC1_1,
52 WM8994_AIF1_DRC2_1,
53 WM8994_AIF2_DRC_1,
54};
55
56static int wm8994_retune_mobile_base[] = {
57 WM8994_AIF1_DAC1_EQ_GAINS_1,
58 WM8994_AIF1_DAC2_EQ_GAINS_1,
59 WM8994_AIF2_EQ_GAINS_1,
60};
61
88766984
MB		 62struct wm8994_micdet {
63 struct snd_soc_jack *jack;
64 int det;
65 int shrt;
66};
67
9e6e96a1
MB		 68/* codec private data */
69struct wm8994_priv {
70 struct wm_hubs_data hubs;
f0fba2ad
LG		 71 enum snd_soc_control_type control_type;
72 void *control_data;
73 struct snd_soc_codec *codec;
9e6e96a1
MB		 74 int sysclk[2];
75 int sysclk_rate[2];
76 int mclk[2];
77 int aifclk[2];
78 struct fll_config fll[2], fll_suspend[2];
79
80 int dac_rates[2];
81 int lrclk_shared[2];
82
d6addcc9
MB		 83 int mbc_ena[3];
84
9e6e96a1
MB		 85 /* Platform dependant DRC configuration */
86 const char **drc_texts;
87 int drc_cfg[WM8994_NUM_DRC];
88 struct soc_enum drc_enum;
89
90 /* Platform dependant ReTune mobile configuration */
91 int num_retune_mobile_texts;
92 const char **retune_mobile_texts;
93 int retune_mobile_cfg[WM8994_NUM_EQ];
94 struct soc_enum retune_mobile_enum;
95
131d8106
MB		 96 /* Platform dependant MBC configuration */
97 int mbc_cfg;
98 const char **mbc_texts;
99 struct soc_enum mbc_enum;
100
88766984
MB		 101 struct wm8994_micdet micdet[2];
102
821edd2f
MB		 103 wm8958_micdet_cb jack_cb;
104 void *jack_cb_data;
105 bool jack_is_mic;
106 bool jack_is_video;
107
b6b05691 108 int revision;
9e6e96a1
MB		 109 struct wm8994_pdata *pdata;
110};
111
9e6e96a1
MB		 112static int wm8994_readable(unsigned int reg)
113{
e88ff1e6
MB		 114 switch (reg) {
115 case WM8994_GPIO_1:
116 case WM8994_GPIO_2:
117 case WM8994_GPIO_3:
118 case WM8994_GPIO_4:
119 case WM8994_GPIO_5:
120 case WM8994_GPIO_6:
121 case WM8994_GPIO_7:
122 case WM8994_GPIO_8:
123 case WM8994_GPIO_9:
124 case WM8994_GPIO_10:
125 case WM8994_GPIO_11:
126 case WM8994_INTERRUPT_STATUS_1:
127 case WM8994_INTERRUPT_STATUS_2:
128 case WM8994_INTERRUPT_RAW_STATUS_2:
129 return 1;
130 default:
131 break;
132 }
133
7b306dae 134 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 135 return 0;
7b306dae 136 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 137}
138
139static int wm8994_volatile(unsigned int reg)
140{
ca9aef50 141 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 142 return 1;
143
144 switch (reg) {
145 case WM8994_SOFTWARE_RESET:
146 case WM8994_CHIP_REVISION:
147 case WM8994_DC_SERVO_1:
148 case WM8994_DC_SERVO_READBACK:
149 case WM8994_RATE_STATUS:
150 case WM8994_LDO_1:
151 case WM8994_LDO_2:
d6addcc9 152 case WM8958_DSP2_EXECCONTROL:
821edd2f 153 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 154 return 1;
155 default:
156 return 0;
157 }
158}
159
160static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
161 unsigned int value)
162{
ca9aef50 163 int ret;
9e6e96a1
MB		 164
165 BUG_ON(reg > WM8994_MAX_REGISTER);
166
ca9aef50
MB		 167 if (!wm8994_volatile(reg)) {
168 ret = snd_soc_cache_write(codec, reg, value);
169 if (ret != 0)
170 dev_err(codec->dev, "Cache write to %x failed: %d\n",
171 reg, ret);
172 }
9e6e96a1
MB		 173
174 return wm8994_reg_write(codec->control_data, reg, value);
175}
176
177static unsigned int wm8994_read(struct snd_soc_codec *codec,
178 unsigned int reg)
179{
ca9aef50
MB		 180 unsigned int val;
181 int ret;
9e6e96a1
MB		 182
183 BUG_ON(reg > WM8994_MAX_REGISTER);
184
ca9aef50
MB		 185 if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
186 reg < codec->driver->reg_cache_size) {
187 ret = snd_soc_cache_read(codec, reg, &val);
188 if (ret >= 0)
189 return val;
190 else
191 dev_err(codec->dev, "Cache read from %x failed: %d\n",
192 reg, ret);
193 }
194
195 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 196}
197
198static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
199{
b2c812e2 200 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 201 int rate;
202 int reg1 = 0;
203 int offset;
204
205 if (aif)
206 offset = 4;
207 else
208 offset = 0;
209
210 switch (wm8994->sysclk[aif]) {
211 case WM8994_SYSCLK_MCLK1:
212 rate = wm8994->mclk[0];
213 break;
214
215 case WM8994_SYSCLK_MCLK2:
216 reg1 |= 0x8;
217 rate = wm8994->mclk[1];
218 break;
219
220 case WM8994_SYSCLK_FLL1:
221 reg1 |= 0x10;
222 rate = wm8994->fll[0].out;
223 break;
224
225 case WM8994_SYSCLK_FLL2:
226 reg1 |= 0x18;
227 rate = wm8994->fll[1].out;
228 break;
229
230 default:
231 return -EINVAL;
232 }
233
234 if (rate >= 13500000) {
235 rate /= 2;
236 reg1 |= WM8994_AIF1CLK_DIV;
237
238 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
239 aif + 1, rate);
240 }
5e5e2bef
MB		 241
242 if (rate && rate < 3000000)
243 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
244 aif + 1, rate);
245
9e6e96a1
MB		 246 wm8994->aifclk[aif] = rate;
247
248 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
249 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
250 reg1);
251
252 return 0;
253}
254
255static int configure_clock(struct snd_soc_codec *codec)
256{
b2c812e2 257 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 258 int old, new;
259
260 /* Bring up the AIF clocks first */
261 configure_aif_clock(codec, 0);
262 configure_aif_clock(codec, 1);
263
264 /* Then switch CLK_SYS over to the higher of them; a change
265 * can only happen as a result of a clocking change which can
266 * only be made outside of DAPM so we can safely redo the
267 * clocking.
268 */
269
270 /* If they're equal it doesn't matter which is used */
271 if (wm8994->aifclk[0] == wm8994->aifclk[1])
272 return 0;
273
274 if (wm8994->aifclk[0] < wm8994->aifclk[1])
275 new = WM8994_SYSCLK_SRC;
276 else
277 new = 0;
278
279 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
280
281 /* If there's no change then we're done. */
282 if (old == new)
283 return 0;
284
285 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
286
ce6120cc 287 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 288
289 return 0;
290}
291
292static int check_clk_sys(struct snd_soc_dapm_widget *source,
293 struct snd_soc_dapm_widget *sink)
294{
295 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
296 const char *clk;
297
298 /* Check what we're currently using for CLK_SYS */
299 if (reg & WM8994_SYSCLK_SRC)
300 clk = "AIF2CLK";
301 else
302 clk = "AIF1CLK";
303
304 return strcmp(source->name, clk) == 0;
305}
306
307static const char *sidetone_hpf_text[] = {
308 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
309};
310
311static const struct soc_enum sidetone_hpf =
312 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
313
146fd574
UK		 314static const char *adc_hpf_text[] = {
315 "HiFi", "Voice 1", "Voice 2", "Voice 3"
316};
317
318static const struct soc_enum aif1adc1_hpf =
319 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
320
321static const struct soc_enum aif1adc2_hpf =
322 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
323
324static const struct soc_enum aif2adc_hpf =
325 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
326
9e6e96a1
MB		 327static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
328static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
329static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
330static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
331static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
332
333#define WM8994_DRC_SWITCH(xname, reg, shift) \
334{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
335 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
336 .put = wm8994_put_drc_sw, \
337 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
338
339static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
340 struct snd_ctl_elem_value *ucontrol)
341{
342 struct soc_mixer_control *mc =
343 (struct soc_mixer_control *)kcontrol->private_value;
344 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
345 int mask, ret;
346
347 /* Can't enable both ADC and DAC paths simultaneously */
348 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
349 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
350 WM8994_AIF1ADC1R_DRC_ENA_MASK;
351 else
352 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
353
354 ret = snd_soc_read(codec, mc->reg);
355 if (ret < 0)
356 return ret;
357 if (ret & mask)
358 return -EINVAL;
359
360 return snd_soc_put_volsw(kcontrol, ucontrol);
361}
362
9e6e96a1
MB		 363static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
364{
b2c812e2 365 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 366 struct wm8994_pdata *pdata = wm8994->pdata;
367 int base = wm8994_drc_base[drc];
368 int cfg = wm8994->drc_cfg[drc];
369 int save, i;
370
371 /* Save any enables; the configuration should clear them. */
372 save = snd_soc_read(codec, base);
373 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
374 WM8994_AIF1ADC1R_DRC_ENA;
375
376 for (i = 0; i < WM8994_DRC_REGS; i++)
377 snd_soc_update_bits(codec, base + i, 0xffff,
378 pdata->drc_cfgs[cfg].regs[i]);
379
380 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
381 WM8994_AIF1ADC1L_DRC_ENA |
382 WM8994_AIF1ADC1R_DRC_ENA, save);
383}
384
385/* Icky as hell but saves code duplication */
386static int wm8994_get_drc(const char *name)
387{
388 if (strcmp(name, "AIF1DRC1 Mode") == 0)
389 return 0;
390 if (strcmp(name, "AIF1DRC2 Mode") == 0)
391 return 1;
392 if (strcmp(name, "AIF2DRC Mode") == 0)
393 return 2;
394 return -EINVAL;
395}
396
397static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
398 struct snd_ctl_elem_value *ucontrol)
399{
400 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 401 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 402 struct wm8994_pdata *pdata = wm8994->pdata;
403 int drc = wm8994_get_drc(kcontrol->id.name);
404 int value = ucontrol->value.integer.value[0];
405
406 if (drc < 0)
407 return drc;
408
409 if (value >= pdata->num_drc_cfgs)
410 return -EINVAL;
411
412 wm8994->drc_cfg[drc] = value;
413
414 wm8994_set_drc(codec, drc);
415
416 return 0;
417}
418
419static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
420 struct snd_ctl_elem_value *ucontrol)
421{
422 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 423 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 424 int drc = wm8994_get_drc(kcontrol->id.name);
425
426 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
427
428 return 0;
429}
430
431static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
432{
b2c812e2 433 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 434 struct wm8994_pdata *pdata = wm8994->pdata;
435 int base = wm8994_retune_mobile_base[block];
436 int iface, best, best_val, save, i, cfg;
437
438 if (!pdata || !wm8994->num_retune_mobile_texts)
439 return;
440
441 switch (block) {
442 case 0:
443 case 1:
444 iface = 0;
445 break;
446 case 2:
447 iface = 1;
448 break;
449 default:
450 return;
451 }
452
453 /* Find the version of the currently selected configuration
454 * with the nearest sample rate. */
455 cfg = wm8994->retune_mobile_cfg[block];
456 best = 0;
457 best_val = INT_MAX;
458 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
459 if (strcmp(pdata->retune_mobile_cfgs[i].name,
460 wm8994->retune_mobile_texts[cfg]) == 0 &&
461 abs(pdata->retune_mobile_cfgs[i].rate
462 - wm8994->dac_rates[iface]) < best_val) {
463 best = i;
464 best_val = abs(pdata->retune_mobile_cfgs[i].rate
465 - wm8994->dac_rates[iface]);
466 }
467 }
468
469 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
470 block,
471 pdata->retune_mobile_cfgs[best].name,
472 pdata->retune_mobile_cfgs[best].rate,
473 wm8994->dac_rates[iface]);
474
475 /* The EQ will be disabled while reconfiguring it, remember the
476 * current configuration.
477 */
478 save = snd_soc_read(codec, base);
479 save &= WM8994_AIF1DAC1_EQ_ENA;
480
481 for (i = 0; i < WM8994_EQ_REGS; i++)
482 snd_soc_update_bits(codec, base + i, 0xffff,
483 pdata->retune_mobile_cfgs[best].regs[i]);
484
485 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
486}
487
488/* Icky as hell but saves code duplication */
489static int wm8994_get_retune_mobile_block(const char *name)
490{
491 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
492 return 0;
493 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
494 return 1;
495 if (strcmp(name, "AIF2 EQ Mode") == 0)
496 return 2;
497 return -EINVAL;
498}
499
500static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
501 struct snd_ctl_elem_value *ucontrol)
502{
503 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 504 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 505 struct wm8994_pdata *pdata = wm8994->pdata;
506 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
507 int value = ucontrol->value.integer.value[0];
508
509 if (block < 0)
510 return block;
511
512 if (value >= pdata->num_retune_mobile_cfgs)
513 return -EINVAL;
514
515 wm8994->retune_mobile_cfg[block] = value;
516
517 wm8994_set_retune_mobile(codec, block);
518
519 return 0;
520}
521
522static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
523 struct snd_ctl_elem_value *ucontrol)
524{
525 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 526 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 527 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
528
529 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
530
531 return 0;
532}
533
96b101ef 534static const char *aif_chan_src_text[] = {
f554885f
MB		 535 "Left", "Right"
536};
537
96b101ef
MB		 538static const struct soc_enum aif1adcl_src =
539 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
540
541static const struct soc_enum aif1adcr_src =
542 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
543
544static const struct soc_enum aif2adcl_src =
545 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
546
547static const struct soc_enum aif2adcr_src =
548 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
549
f554885f 550static const struct soc_enum aif1dacl_src =
96b101ef 551 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 552
553static const struct soc_enum aif1dacr_src =
96b101ef 554 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 555
556static const struct soc_enum aif2dacl_src =
96b101ef 557 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 558
559static const struct soc_enum aif2dacr_src =
96b101ef 560 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 561
154b26aa
MB		 562static const char *osr_text[] = {
563 "Low Power", "High Performance",
564};
565
566static const struct soc_enum dac_osr =
567 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
568
569static const struct soc_enum adc_osr =
570 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
571
d6addcc9
MB		 572static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
573{
574 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
131d8106 575 struct wm8994_pdata *pdata = wm8994->pdata;
d6addcc9 576 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
131d8106 577 int ena, reg, aif, i;
d6addcc9
MB		 578
579 switch (mbc) {
580 case 0:
581 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
582 aif = 0;
583 break;
584 case 1:
585 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
586 aif = 0;
587 break;
588 case 2:
589 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
590 aif = 1;
591 break;
592 default:
593 BUG();
594 return;
595 }
596
597 /* We can only enable the MBC if the AIF is enabled and we
598 * want it to be enabled. */
599 ena = pwr_reg && wm8994->mbc_ena[mbc];
600
601 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
602
603 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
604 mbc, start, pwr_reg, reg);
605
606 if (start && ena) {
607 /* If the DSP is already running then noop */
608 if (reg & WM8958_DSP2_ENA)
609 return;
610
611 /* Switch the clock over to the appropriate AIF */
612 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
613 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
614 aif << WM8958_DSP2CLK_SRC_SHIFT |
615 WM8958_DSP2CLK_ENA);
616
617 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
618 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
619
131d8106
MB		 620 /* If we've got user supplied MBC settings use them */
621 if (pdata && pdata->num_mbc_cfgs) {
622 struct wm8958_mbc_cfg *cfg
623 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
624
625 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
626 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
627 cfg->coeff_regs[i]);
628
629 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
630 snd_soc_write(codec,
631 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
632 cfg->cutoff_regs[i]);
633 }
d6addcc9
MB		 634
635 /* Run the DSP */
636 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
637 WM8958_DSP2_RUNR);
638
639 /* And we're off! */
640 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
641 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
642 mbc << WM8958_MBC_SEL_SHIFT |
643 WM8958_MBC_ENA);
644 } else {
645 /* If the DSP is already stopped then noop */
646 if (!(reg & WM8958_DSP2_ENA))
647 return;
648
649 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
650 WM8958_MBC_ENA, 0);
651 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
652 WM8958_DSP2_ENA, 0);
653 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
654 WM8958_DSP2CLK_ENA, 0);
655 }
656}
657
658static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
659 struct snd_kcontrol *kcontrol, int event)
660{
661 struct snd_soc_codec *codec = w->codec;
662 int mbc;
663
664 switch (w->shift) {
665 case 13:
666 case 12:
667 mbc = 2;
668 break;
669 case 11:
670 case 10:
671 mbc = 1;
672 break;
673 case 9:
674 case 8:
675 mbc = 0;
676 break;
677 default:
678 BUG();
679 return -EINVAL;
680 }
681
682 switch (event) {
683 case SND_SOC_DAPM_POST_PMU:
684 wm8958_mbc_apply(codec, mbc, 1);
685 break;
686 case SND_SOC_DAPM_POST_PMD:
687 wm8958_mbc_apply(codec, mbc, 0);
688 break;
689 }
690
691 return 0;
692}
693
131d8106
MB		 694static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
695 struct snd_ctl_elem_value *ucontrol)
696{
697 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
698 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
699 struct wm8994_pdata *pdata = wm8994->pdata;
700 int value = ucontrol->value.integer.value[0];
701 int reg;
702
703 /* Don't allow on the fly reconfiguration */
704 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
705 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
706 return -EBUSY;
707
708 if (value >= pdata->num_mbc_cfgs)
709 return -EINVAL;
710
711 wm8994->mbc_cfg = value;
712
713 return 0;
714}
715
716static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
717 struct snd_ctl_elem_value *ucontrol)
718{
719 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
720 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
721
722 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
723
724 return 0;
725}
726
d6addcc9
MB		 727static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
728 struct snd_ctl_elem_info *uinfo)
729{
730 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
731 uinfo->count = 1;
732 uinfo->value.integer.min = 0;
733 uinfo->value.integer.max = 1;
734 return 0;
735}
736
737static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
738 struct snd_ctl_elem_value *ucontrol)
739{
740 int mbc = kcontrol->private_value;
741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
742 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
743
744 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
745
746 return 0;
747}
748
749static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
750 struct snd_ctl_elem_value *ucontrol)
751{
752 int mbc = kcontrol->private_value;
753 int i;
754 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
755 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
756
757 if (ucontrol->value.integer.value[0] > 1)
758 return -EINVAL;
759
760 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
761 if (mbc != i && wm8994->mbc_ena[i]) {
762 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
763 return -EBUSY;
764 }
765 }
766
767 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
768
769 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
770
771 return 0;
772}
773
774#define WM8958_MBC_SWITCH(xname, xval) {\
775 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
776 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
777 .info = wm8958_mbc_info, \
778 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
779 .private_value = xval }
780
9e6e96a1
MB		 781static const struct snd_kcontrol_new wm8994_snd_controls[] = {
782SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
783 WM8994_AIF1_ADC1_RIGHT_VOLUME,
784 1, 119, 0, digital_tlv),
785SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
786 WM8994_AIF1_ADC2_RIGHT_VOLUME,
787 1, 119, 0, digital_tlv),
788SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
789 WM8994_AIF2_ADC_RIGHT_VOLUME,
790 1, 119, 0, digital_tlv),
791
96b101ef
MB		 792SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
793SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 794SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
795SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 796
f554885f
MB		 797SOC_ENUM("AIF1DACL Source", aif1dacl_src),
798SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 799SOC_ENUM("AIF2DACL Source", aif2dacl_src),
800SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 801
9e6e96a1
MB		 802SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
803 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
804SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
805 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
806SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
807 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
808
809SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
810SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
811
812SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
813SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
814SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
815
816WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
817WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
818WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
819
820WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
821WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
822WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
823
824WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
825WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
826WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
827
828SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
829 5, 12, 0, st_tlv),
830SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
831 0, 12, 0, st_tlv),
832SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
833 5, 12, 0, st_tlv),
834SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
835 0, 12, 0, st_tlv),
836SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
837SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
838
146fd574
UK		 839SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
840SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
841
842SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
843SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
844
845SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
846SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
847
154b26aa
MB		 848SOC_ENUM("ADC OSR", adc_osr),
849SOC_ENUM("DAC OSR", dac_osr),
850
9e6e96a1
MB		 851SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
852 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
853SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
854 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
855
856SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
857 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
858SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
859 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
860
861SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
862 6, 1, 1, wm_hubs_spkmix_tlv),
863SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
864 2, 1, 1, wm_hubs_spkmix_tlv),
865
866SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
867 6, 1, 1, wm_hubs_spkmix_tlv),
868SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
869 2, 1, 1, wm_hubs_spkmix_tlv),
870
871SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
872 10, 15, 0, wm8994_3d_tlv),
458350b3 873SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 874 8, 1, 0),
875SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
876 10, 15, 0, wm8994_3d_tlv),
877SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
878 8, 1, 0),
458350b3 879SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 880 10, 15, 0, wm8994_3d_tlv),
458350b3 881SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 882 8, 1, 0),
883};
884
885static const struct snd_kcontrol_new wm8994_eq_controls[] = {
886SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
887 eq_tlv),
888SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
889 eq_tlv),
890SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
891 eq_tlv),
892SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
893 eq_tlv),
894SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
895 eq_tlv),
896
897SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
898 eq_tlv),
899SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
900 eq_tlv),
901SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
902 eq_tlv),
903SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
904 eq_tlv),
905SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
906 eq_tlv),
907
908SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
909 eq_tlv),
910SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
911 eq_tlv),
912SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
913 eq_tlv),
914SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
915 eq_tlv),
916SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
917 eq_tlv),
918};
919
c4431df0
MB		 920static const struct snd_kcontrol_new wm8958_snd_controls[] = {
921SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
d6addcc9
MB		 922WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
923WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
924WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
c4431df0
MB		 925};
926
9e6e96a1
MB		 927static int clk_sys_event(struct snd_soc_dapm_widget *w,
928 struct snd_kcontrol *kcontrol, int event)
929{
930 struct snd_soc_codec *codec = w->codec;
931
932 switch (event) {
933 case SND_SOC_DAPM_PRE_PMU:
934 return configure_clock(codec);
935
936 case SND_SOC_DAPM_POST_PMD:
937 configure_clock(codec);
938 break;
939 }
940
941 return 0;
942}
943
944static void wm8994_update_class_w(struct snd_soc_codec *codec)
945{
fec6dd83 946 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 947 int enable = 1;
948 int source = 0; /* GCC flow analysis can't track enable */
949 int reg, reg_r;
950
951 /* Only support direct DAC->headphone paths */
952 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
953 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 954 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 955 enable = 0;
956 }
957
958 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
959 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 960 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 961 enable = 0;
962 }
963
964 /* We also need the same setting for L/R and only one path */
965 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
966 switch (reg) {
967 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 968 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 969 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
970 break;
971 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 972 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 973 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
974 break;
975 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 976 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 977 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
978 break;
979 default:
ee839a21 980 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 981 enable = 0;
982 break;
983 }
984
985 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
986 if (reg_r != reg) {
ee839a21 987 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 988 enable = 0;
989 }
990
991 if (enable) {
992 dev_dbg(codec->dev, "Class W enabled\n");
993 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
994 WM8994_CP_DYN_PWR |
995 WM8994_CP_DYN_SRC_SEL_MASK,
996 source | WM8994_CP_DYN_PWR);
fec6dd83 997 wm8994->hubs.class_w = true;
9e6e96a1
MB		 998
999 } else {
1000 dev_dbg(codec->dev, "Class W disabled\n");
1001 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1002 WM8994_CP_DYN_PWR, 0);
fec6dd83 1003 wm8994->hubs.class_w = false;
9e6e96a1
MB		 1004 }
1005}
1006
1007static const char *hp_mux_text[] = {
1008 "Mixer",
1009 "DAC",
1010};
1011
1012#define WM8994_HP_ENUM(xname, xenum) \
1013{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1014 .info = snd_soc_info_enum_double, \
1015 .get = snd_soc_dapm_get_enum_double, \
1016 .put = wm8994_put_hp_enum, \
1017 .private_value = (unsigned long)&xenum }
1018
1019static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1020 struct snd_ctl_elem_value *ucontrol)
1021{
1022 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1023 struct snd_soc_codec *codec = w->codec;
1024 int ret;
1025
1026 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1027
1028 wm8994_update_class_w(codec);
1029
1030 return ret;
1031}
1032
1033static const struct soc_enum hpl_enum =
1034 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1035
1036static const struct snd_kcontrol_new hpl_mux =
1037 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1038
1039static const struct soc_enum hpr_enum =
1040 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1041
1042static const struct snd_kcontrol_new hpr_mux =
1043 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1044
1045static const char *adc_mux_text[] = {
1046 "ADC",
1047 "DMIC",
1048};
1049
1050static const struct soc_enum adc_enum =
1051 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1052
1053static const struct snd_kcontrol_new adcl_mux =
1054 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1055
1056static const struct snd_kcontrol_new adcr_mux =
1057 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1058
1059static const struct snd_kcontrol_new left_speaker_mixer[] = {
1060SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1061SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1062SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1063SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1064SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1065};
1066
1067static const struct snd_kcontrol_new right_speaker_mixer[] = {
1068SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1069SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1070SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1071SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1072SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1073};
1074
1075/* Debugging; dump chip status after DAPM transitions */
1076static int post_ev(struct snd_soc_dapm_widget *w,
1077 struct snd_kcontrol *kcontrol, int event)
1078{
1079 struct snd_soc_codec *codec = w->codec;
1080 dev_dbg(codec->dev, "SRC status: %x\n",
1081 snd_soc_read(codec,
1082 WM8994_RATE_STATUS));
1083 return 0;
1084}
1085
1086static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1087SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1088 1, 1, 0),
1089SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1090 0, 1, 0),
1091};
1092
1093static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1094SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1095 1, 1, 0),
1096SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1097 0, 1, 0),
1098};
1099
a3257ba8
MB		 1100static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1101SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1102 1, 1, 0),
1103SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1104 0, 1, 0),
1105};
1106
1107static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1108SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1109 1, 1, 0),
1110SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1111 0, 1, 0),
1112};
1113
9e6e96a1
MB		 1114static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1115SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1116 5, 1, 0),
1117SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1118 4, 1, 0),
1119SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1120 2, 1, 0),
1121SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1122 1, 1, 0),
1123SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1124 0, 1, 0),
1125};
1126
1127static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1128SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1129 5, 1, 0),
1130SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1131 4, 1, 0),
1132SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1133 2, 1, 0),
1134SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1135 1, 1, 0),
1136SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1137 0, 1, 0),
1138};
1139
1140#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1141{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1142 .info = snd_soc_info_volsw, \
1143 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1144 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1145
1146static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1147 struct snd_ctl_elem_value *ucontrol)
1148{
1149 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1150 struct snd_soc_codec *codec = w->codec;
1151 int ret;
1152
1153 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1154
1155 wm8994_update_class_w(codec);
1156
1157 return ret;
1158}
1159
1160static const struct snd_kcontrol_new dac1l_mix[] = {
1161WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1162 5, 1, 0),
1163WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1164 4, 1, 0),
1165WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1166 2, 1, 0),
1167WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1168 1, 1, 0),
1169WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1170 0, 1, 0),
1171};
1172
1173static const struct snd_kcontrol_new dac1r_mix[] = {
1174WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1175 5, 1, 0),
1176WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1177 4, 1, 0),
1178WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1179 2, 1, 0),
1180WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1181 1, 1, 0),
1182WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1183 0, 1, 0),
1184};
1185
1186static const char *sidetone_text[] = {
1187 "ADC/DMIC1", "DMIC2",
1188};
1189
1190static const struct soc_enum sidetone1_enum =
1191 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1192
1193static const struct snd_kcontrol_new sidetone1_mux =
1194 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1195
1196static const struct soc_enum sidetone2_enum =
1197 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1198
1199static const struct snd_kcontrol_new sidetone2_mux =
1200 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1201
1202static const char *aif1dac_text[] = {
1203 "AIF1DACDAT", "AIF3DACDAT",
1204};
1205
1206static const struct soc_enum aif1dac_enum =
1207 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1208
1209static const struct snd_kcontrol_new aif1dac_mux =
1210 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1211
1212static const char *aif2dac_text[] = {
1213 "AIF2DACDAT", "AIF3DACDAT",
1214};
1215
1216static const struct soc_enum aif2dac_enum =
1217 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1218
1219static const struct snd_kcontrol_new aif2dac_mux =
1220 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1221
1222static const char *aif2adc_text[] = {
1223 "AIF2ADCDAT", "AIF3DACDAT",
1224};
1225
1226static const struct soc_enum aif2adc_enum =
1227 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1228
1229static const struct snd_kcontrol_new aif2adc_mux =
1230 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1231
1232static const char *aif3adc_text[] = {
c4431df0 1233 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1234};
1235
c4431df0 1236static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1237 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1238
c4431df0
MB		 1239static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1240 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1241
1242static const struct soc_enum wm8958_aif3adc_enum =
1243 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1244
1245static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1246 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1247
1248static const char *mono_pcm_out_text[] = {
1249 "None", "AIF2ADCL", "AIF2ADCR",
1250};
1251
1252static const struct soc_enum mono_pcm_out_enum =
1253 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1254
1255static const struct snd_kcontrol_new mono_pcm_out_mux =
1256 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1257
1258static const char *aif2dac_src_text[] = {
1259 "AIF2", "AIF3",
1260};
1261
1262/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1263static const struct soc_enum aif2dacl_src_enum =
1264 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1265
1266static const struct snd_kcontrol_new aif2dacl_src_mux =
1267 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1268
1269static const struct soc_enum aif2dacr_src_enum =
1270 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1271
1272static const struct snd_kcontrol_new aif2dacr_src_mux =
1273 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1
MB		 1274
1275static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1276SND_SOC_DAPM_INPUT("DMIC1DAT"),
1277SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1278SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 1279
1280SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1281 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1282
1283SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1284SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1285SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1286
1287SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1288SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1289
7f94de48 1290SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1291 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1292SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1293 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1294SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1295 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1296 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1297SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1298 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1299 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1300
7f94de48 1301SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1302 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1303SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1304 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1305SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1306 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1307 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1308SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1309 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1310 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1311
1312SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1313 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1314SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1315 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1316
a3257ba8
MB		 1317SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1318 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1319SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1320 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1321
9e6e96a1
MB		 1322SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1323 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1324SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1325 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1326
1327SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1328SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1329
1330SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1331 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1332SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1333 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1334
1335SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1336 WM8994_POWER_MANAGEMENT_4, 13, 0),
1337SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1338 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1339SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1340 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1341 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1342SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1343 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1344 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1345
1346SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1347SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1348SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1349SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1350
1351SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1352SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1353SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1354
1355SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1356SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1357
1358SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1359
1360SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1361SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1362SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1363SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1364
1365/* Power is done with the muxes since the ADC power also controls the
1366 * downsampling chain, the chip will automatically manage the analogue
1367 * specific portions.
1368 */
1369SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1370SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1371
1372SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1373SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1374
1375SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1376SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1377SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1378SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1379
1380SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1381SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1382
1383SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1384 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1385SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1386 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1387
1388SND_SOC_DAPM_POST("Debug log", post_ev),
1389};
1390
c4431df0
MB		 1391static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1392SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1393};
9e6e96a1 1394
c4431df0
MB		 1395static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1396SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1397SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1398SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1399SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1400};
1401
1402static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1403 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1404 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1405
1406 { "DSP1CLK", NULL, "CLK_SYS" },
1407 { "DSP2CLK", NULL, "CLK_SYS" },
1408 { "DSPINTCLK", NULL, "CLK_SYS" },
1409
1410 { "AIF1ADC1L", NULL, "AIF1CLK" },
1411 { "AIF1ADC1L", NULL, "DSP1CLK" },
1412 { "AIF1ADC1R", NULL, "AIF1CLK" },
1413 { "AIF1ADC1R", NULL, "DSP1CLK" },
1414 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1415
1416 { "AIF1DAC1L", NULL, "AIF1CLK" },
1417 { "AIF1DAC1L", NULL, "DSP1CLK" },
1418 { "AIF1DAC1R", NULL, "AIF1CLK" },
1419 { "AIF1DAC1R", NULL, "DSP1CLK" },
1420 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1421
1422 { "AIF1ADC2L", NULL, "AIF1CLK" },
1423 { "AIF1ADC2L", NULL, "DSP1CLK" },
1424 { "AIF1ADC2R", NULL, "AIF1CLK" },
1425 { "AIF1ADC2R", NULL, "DSP1CLK" },
1426 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1427
1428 { "AIF1DAC2L", NULL, "AIF1CLK" },
1429 { "AIF1DAC2L", NULL, "DSP1CLK" },
1430 { "AIF1DAC2R", NULL, "AIF1CLK" },
1431 { "AIF1DAC2R", NULL, "DSP1CLK" },
1432 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1433
1434 { "AIF2ADCL", NULL, "AIF2CLK" },
1435 { "AIF2ADCL", NULL, "DSP2CLK" },
1436 { "AIF2ADCR", NULL, "AIF2CLK" },
1437 { "AIF2ADCR", NULL, "DSP2CLK" },
1438 { "AIF2ADCR", NULL, "DSPINTCLK" },
1439
1440 { "AIF2DACL", NULL, "AIF2CLK" },
1441 { "AIF2DACL", NULL, "DSP2CLK" },
1442 { "AIF2DACR", NULL, "AIF2CLK" },
1443 { "AIF2DACR", NULL, "DSP2CLK" },
1444 { "AIF2DACR", NULL, "DSPINTCLK" },
1445
1446 { "DMIC1L", NULL, "DMIC1DAT" },
1447 { "DMIC1L", NULL, "CLK_SYS" },
1448 { "DMIC1R", NULL, "DMIC1DAT" },
1449 { "DMIC1R", NULL, "CLK_SYS" },
1450 { "DMIC2L", NULL, "DMIC2DAT" },
1451 { "DMIC2L", NULL, "CLK_SYS" },
1452 { "DMIC2R", NULL, "DMIC2DAT" },
1453 { "DMIC2R", NULL, "CLK_SYS" },
1454
1455 { "ADCL", NULL, "AIF1CLK" },
1456 { "ADCL", NULL, "DSP1CLK" },
1457 { "ADCL", NULL, "DSPINTCLK" },
1458
1459 { "ADCR", NULL, "AIF1CLK" },
1460 { "ADCR", NULL, "DSP1CLK" },
1461 { "ADCR", NULL, "DSPINTCLK" },
1462
1463 { "ADCL Mux", "ADC", "ADCL" },
1464 { "ADCL Mux", "DMIC", "DMIC1L" },
1465 { "ADCR Mux", "ADC", "ADCR" },
1466 { "ADCR Mux", "DMIC", "DMIC1R" },
1467
1468 { "DAC1L", NULL, "AIF1CLK" },
1469 { "DAC1L", NULL, "DSP1CLK" },
1470 { "DAC1L", NULL, "DSPINTCLK" },
1471
1472 { "DAC1R", NULL, "AIF1CLK" },
1473 { "DAC1R", NULL, "DSP1CLK" },
1474 { "DAC1R", NULL, "DSPINTCLK" },
1475
1476 { "DAC2L", NULL, "AIF2CLK" },
1477 { "DAC2L", NULL, "DSP2CLK" },
1478 { "DAC2L", NULL, "DSPINTCLK" },
1479
1480 { "DAC2R", NULL, "AIF2DACR" },
1481 { "DAC2R", NULL, "AIF2CLK" },
1482 { "DAC2R", NULL, "DSP2CLK" },
1483 { "DAC2R", NULL, "DSPINTCLK" },
1484
1485 { "TOCLK", NULL, "CLK_SYS" },
1486
1487 /* AIF1 outputs */
1488 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1489 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1490 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1491
1492 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1493 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1494 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1495
a3257ba8
MB		 1496 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1497 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1498 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1499
1500 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1501 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1502 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1503
9e6e96a1
MB		 1504 /* Pin level routing for AIF3 */
1505 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1506 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1507 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1508 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1509
9e6e96a1
MB		 1510 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1511 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1512 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1513 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1514 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1515 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1516 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1517
1518 /* DAC1 inputs */
1519 { "DAC1L", NULL, "DAC1L Mixer" },
1520 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1521 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1522 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1523 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1524 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1525
1526 { "DAC1R", NULL, "DAC1R Mixer" },
1527 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1528 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1529 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1530 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1531 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1532
1533 /* DAC2/AIF2 outputs */
1534 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1535 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1536 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1537 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1538 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1539 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1540 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1541
1542 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1543 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1544 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1545 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1546 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1547 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1548 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1549
7f94de48
MB		 1550 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1551 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1552 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1553 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1554
9e6e96a1
MB		 1555 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1556
1557 /* AIF3 output */
1558 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1559 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1560 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1561 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1562 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1563 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1564 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1565 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1566
1567 /* Sidetone */
1568 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1569 { "Left Sidetone", "DMIC2", "DMIC2L" },
1570 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1571 { "Right Sidetone", "DMIC2", "DMIC2R" },
1572
1573 /* Output stages */
1574 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1575 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1576
1577 { "SPKL", "DAC1 Switch", "DAC1L" },
1578 { "SPKL", "DAC2 Switch", "DAC2L" },
1579
1580 { "SPKR", "DAC1 Switch", "DAC1R" },
1581 { "SPKR", "DAC2 Switch", "DAC2R" },
1582
1583 { "Left Headphone Mux", "DAC", "DAC1L" },
1584 { "Right Headphone Mux", "DAC", "DAC1R" },
1585};
1586
6ed8f148
MB		 1587static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1588 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1589 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1590 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1591 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1592};
1593
c4431df0
MB		 1594static const struct snd_soc_dapm_route wm8994_intercon[] = {
1595 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1596 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1597};
1598
1599static const struct snd_soc_dapm_route wm8958_intercon[] = {
1600 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1601 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1602
1603 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1604 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1605 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1606 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1607
1608 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1609 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1610
1611 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1612};
1613
9e6e96a1
MB		 1614/* The size in bits of the FLL divide multiplied by 10
1615 * to allow rounding later */
1616#define FIXED_FLL_SIZE ((1 << 16) * 10)
1617
1618struct fll_div {
1619 u16 outdiv;
1620 u16 n;
1621 u16 k;
1622 u16 clk_ref_div;
1623 u16 fll_fratio;
1624};
1625
1626static int wm8994_get_fll_config(struct fll_div *fll,
1627 int freq_in, int freq_out)
1628{
1629 u64 Kpart;
1630 unsigned int K, Ndiv, Nmod;
1631
1632 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1633
1634 /* Scale the input frequency down to <= 13.5MHz */
1635 fll->clk_ref_div = 0;
1636 while (freq_in > 13500000) {
1637 fll->clk_ref_div++;
1638 freq_in /= 2;
1639
1640 if (fll->clk_ref_div > 3)
1641 return -EINVAL;
1642 }
1643 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1644
1645 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1646 fll->outdiv = 3;
1647 while (freq_out * (fll->outdiv + 1) < 90000000) {
1648 fll->outdiv++;
1649 if (fll->outdiv > 63)
1650 return -EINVAL;
1651 }
1652 freq_out *= fll->outdiv + 1;
1653 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1654
1655 if (freq_in > 1000000) {
1656 fll->fll_fratio = 0;
7d48a6ac
MB		 1657 } else if (freq_in > 256000) {
1658 fll->fll_fratio = 1;
1659 freq_in *= 2;
1660 } else if (freq_in > 128000) {
1661 fll->fll_fratio = 2;
1662 freq_in *= 4;
1663 } else if (freq_in > 64000) {
9e6e96a1
MB		 1664 fll->fll_fratio = 3;
1665 freq_in *= 8;
7d48a6ac
MB		 1666 } else {
1667 fll->fll_fratio = 4;
1668 freq_in *= 16;
9e6e96a1
MB		 1669 }
1670 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1671
1672 /* Now, calculate N.K */
1673 Ndiv = freq_out / freq_in;
1674
1675 fll->n = Ndiv;
1676 Nmod = freq_out % freq_in;
1677 pr_debug("Nmod=%d\n", Nmod);
1678
1679 /* Calculate fractional part - scale up so we can round. */
1680 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1681
1682 do_div(Kpart, freq_in);
1683
1684 K = Kpart & 0xFFFFFFFF;
1685
1686 if ((K % 10) >= 5)
1687 K += 5;
1688
1689 /* Move down to proper range now rounding is done */
1690 fll->k = K / 10;
1691
1692 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1693
1694 return 0;
1695}
1696
f0fba2ad 1697static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1698 unsigned int freq_in, unsigned int freq_out)
1699{
b2c812e2 1700 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1701 int reg_offset, ret;
1702 struct fll_div fll;
1703 u16 reg, aif1, aif2;
1704
1705 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1706 & WM8994_AIF1CLK_ENA;
1707
1708 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1709 & WM8994_AIF2CLK_ENA;
1710
1711 switch (id) {
1712 case WM8994_FLL1:
1713 reg_offset = 0;
1714 id = 0;
1715 break;
1716 case WM8994_FLL2:
1717 reg_offset = 0x20;
1718 id = 1;
1719 break;
1720 default:
1721 return -EINVAL;
1722 }
1723
136ff2a2 1724 switch (src) {
7add84aa
MB		 1725 case 0:
1726 /* Allow no source specification when stopping */
1727 if (freq_out)
1728 return -EINVAL;
4514e899 1729 src = wm8994->fll[id].src;
7add84aa 1730 break;
136ff2a2
MB		 1731 case WM8994_FLL_SRC_MCLK1:
1732 case WM8994_FLL_SRC_MCLK2:
1733 case WM8994_FLL_SRC_LRCLK:
1734 case WM8994_FLL_SRC_BCLK:
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
9e6e96a1
MB		 1740 /* Are we changing anything? */
1741 if (wm8994->fll[id].src == src &&
1742 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1743 return 0;
1744
1745 /* If we're stopping the FLL redo the old config - no
1746 * registers will actually be written but we avoid GCC flow
1747 * analysis bugs spewing warnings.
1748 */
1749 if (freq_out)
1750 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1751 else
1752 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1753 wm8994->fll[id].out);
1754 if (ret < 0)
1755 return ret;
1756
1757 /* Gate the AIF clocks while we reclock */
1758 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1759 WM8994_AIF1CLK_ENA, 0);
1760 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1761 WM8994_AIF2CLK_ENA, 0);
1762
1763 /* We always need to disable the FLL while reconfiguring */
1764 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1765 WM8994_FLL1_ENA, 0);
1766
1767 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1768 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1769 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1770 WM8994_FLL1_OUTDIV_MASK |
1771 WM8994_FLL1_FRATIO_MASK, reg);
1772
1773 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1774
1775 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1776 WM8994_FLL1_N_MASK,
1777 fll.n << WM8994_FLL1_N_SHIFT);
1778
1779 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1780 WM8994_FLL1_REFCLK_DIV_MASK |
1781 WM8994_FLL1_REFCLK_SRC_MASK,
1782 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1783 (src - 1));
9e6e96a1
MB		 1784
1785 /* Enable (with fractional mode if required) */
1786 if (freq_out) {
1787 if (fll.k)
1788 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1789 else
1790 reg = WM8994_FLL1_ENA;
1791 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1792 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1793 reg);
1794 }
1795
1796 wm8994->fll[id].in = freq_in;
1797 wm8994->fll[id].out = freq_out;
136ff2a2 1798 wm8994->fll[id].src = src;
9e6e96a1
MB		 1799
1800 /* Enable any gated AIF clocks */
1801 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1802 WM8994_AIF1CLK_ENA, aif1);
1803 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1804 WM8994_AIF2CLK_ENA, aif2);
1805
1806 configure_clock(codec);
1807
1808 return 0;
1809}
1810
f0fba2ad 1811
66b47fdb
MB		 1812static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1813
f0fba2ad
LG		 1814static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1815 unsigned int freq_in, unsigned int freq_out)
1816{
1817 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1818}
1819
9e6e96a1
MB		 1820static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1821 int clk_id, unsigned int freq, int dir)
1822{
1823 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1824 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1825 int i;
9e6e96a1
MB		 1826
1827 switch (dai->id) {
1828 case 1:
1829 case 2:
1830 break;
1831
1832 default:
1833 /* AIF3 shares clocking with AIF1/2 */
1834 return -EINVAL;
1835 }
1836
1837 switch (clk_id) {
1838 case WM8994_SYSCLK_MCLK1:
1839 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1840 wm8994->mclk[0] = freq;
1841 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1842 dai->id, freq);
1843 break;
1844
1845 case WM8994_SYSCLK_MCLK2:
1846 /* TODO: Set GPIO AF */
1847 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1848 wm8994->mclk[1] = freq;
1849 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1850 dai->id, freq);
1851 break;
1852
1853 case WM8994_SYSCLK_FLL1:
1854 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1855 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1856 break;
1857
1858 case WM8994_SYSCLK_FLL2:
1859 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1860 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1861 break;
1862
66b47fdb
MB		 1863 case WM8994_SYSCLK_OPCLK:
1864 /* Special case - a division (times 10) is given and
1865 * no effect on main clocking.
1866 */
1867 if (freq) {
1868 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1869 if (opclk_divs[i] == freq)
1870 break;
1871 if (i == ARRAY_SIZE(opclk_divs))
1872 return -EINVAL;
1873 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1874 WM8994_OPCLK_DIV_MASK, i);
1875 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1876 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1877 } else {
1878 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1879 WM8994_OPCLK_ENA, 0);
1880 }
1881
9e6e96a1
MB		 1882 default:
1883 return -EINVAL;
1884 }
1885
1886 configure_clock(codec);
1887
1888 return 0;
1889}
1890
1891static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1892 enum snd_soc_bias_level level)
1893{
3a423157 1894 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1895 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1896
9e6e96a1
MB		 1897 switch (level) {
1898 case SND_SOC_BIAS_ON:
1899 break;
1900
1901 case SND_SOC_BIAS_PREPARE:
1902 /* VMID=2x40k */
1903 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1904 WM8994_VMID_SEL_MASK, 0x2);
1905 break;
1906
1907 case SND_SOC_BIAS_STANDBY:
ce6120cc 1908 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 1909 pm_runtime_get_sync(codec->dev);
1910
8bc3c2c2
MB		 1911 switch (control->type) {
1912 case WM8994:
1913 if (wm8994->revision < 4) {
1914 /* Tweak DC servo and DSP
1915 * configuration for improved
1916 * performance. */
1917 snd_soc_write(codec, 0x102, 0x3);
1918 snd_soc_write(codec, 0x56, 0x3);
1919 snd_soc_write(codec, 0x817, 0);
1920 snd_soc_write(codec, 0x102, 0);
1921 }
1922 break;
1923
1924 case WM8958:
1925 if (wm8994->revision == 0) {
1926 /* Optimise performance for rev A */
1927 snd_soc_write(codec, 0x102, 0x3);
1928 snd_soc_write(codec, 0xcb, 0x81);
1929 snd_soc_write(codec, 0x817, 0);
1930 snd_soc_write(codec, 0x102, 0);
1931
1932 snd_soc_update_bits(codec,
1933 WM8958_CHARGE_PUMP_2,
1934 WM8958_CP_DISCH,
1935 WM8958_CP_DISCH);
1936 }
1937 break;
b6b05691 1938 }
9e6e96a1
MB		 1939
1940 /* Discharge LINEOUT1 & 2 */
1941 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1942 WM8994_LINEOUT1_DISCH |
1943 WM8994_LINEOUT2_DISCH,
1944 WM8994_LINEOUT1_DISCH |
1945 WM8994_LINEOUT2_DISCH);
1946
1947 /* Startup bias, VMID ramp & buffer */
1948 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1949 WM8994_STARTUP_BIAS_ENA |
1950 WM8994_VMID_BUF_ENA |
1951 WM8994_VMID_RAMP_MASK,
1952 WM8994_STARTUP_BIAS_ENA |
1953 WM8994_VMID_BUF_ENA |
1954 (0x11 << WM8994_VMID_RAMP_SHIFT));
1955
1956 /* Main bias enable, VMID=2x40k */
1957 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1958 WM8994_BIAS_ENA |
1959 WM8994_VMID_SEL_MASK,
1960 WM8994_BIAS_ENA | 0x2);
1961
1962 msleep(20);
1963 }
1964
1965 /* VMID=2x500k */
1966 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1967 WM8994_VMID_SEL_MASK, 0x4);
1968
1969 break;
1970
1971 case SND_SOC_BIAS_OFF:
ce6120cc 1972 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1973 /* Switch over to startup biases */
1974 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1975 WM8994_BIAS_SRC |
1976 WM8994_STARTUP_BIAS_ENA |
1977 WM8994_VMID_BUF_ENA |
1978 WM8994_VMID_RAMP_MASK,
1979 WM8994_BIAS_SRC |
1980 WM8994_STARTUP_BIAS_ENA |
1981 WM8994_VMID_BUF_ENA |
1982 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1983
d522ffbf
MB		 1984 /* Disable main biases */
1985 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1986 WM8994_BIAS_ENA |
1987 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1988
d522ffbf
MB		 1989 /* Discharge line */
1990 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1991 WM8994_LINEOUT1_DISCH |
1992 WM8994_LINEOUT2_DISCH,
1993 WM8994_LINEOUT1_DISCH |
1994 WM8994_LINEOUT2_DISCH);
9e6e96a1 1995
d522ffbf 1996 msleep(5);
9e6e96a1 1997
d522ffbf
MB		 1998 /* Switch off startup biases */
1999 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2000 WM8994_BIAS_SRC |
2001 WM8994_STARTUP_BIAS_ENA |
2002 WM8994_VMID_BUF_ENA |
2003 WM8994_VMID_RAMP_MASK, 0);
39fb51a1
MB		 2004
2005 pm_runtime_put(codec->dev);
d522ffbf 2006 }
9e6e96a1
MB		 2007 break;
2008 }
ce6120cc 2009 codec->dapm.bias_level = level;
9e6e96a1
MB		 2010 return 0;
2011}
2012
2013static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2014{
2015 struct snd_soc_codec *codec = dai->codec;
c4431df0 2016 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2017 int ms_reg;
2018 int aif1_reg;
2019 int ms = 0;
2020 int aif1 = 0;
2021
2022 switch (dai->id) {
2023 case 1:
2024 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2025 aif1_reg = WM8994_AIF1_CONTROL_1;
2026 break;
2027 case 2:
2028 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2029 aif1_reg = WM8994_AIF2_CONTROL_1;
2030 break;
2031 default:
2032 return -EINVAL;
2033 }
2034
2035 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2036 case SND_SOC_DAIFMT_CBS_CFS:
2037 break;
2038 case SND_SOC_DAIFMT_CBM_CFM:
2039 ms = WM8994_AIF1_MSTR;
2040 break;
2041 default:
2042 return -EINVAL;
2043 }
2044
2045 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2046 case SND_SOC_DAIFMT_DSP_B:
2047 aif1 |= WM8994_AIF1_LRCLK_INV;
2048 case SND_SOC_DAIFMT_DSP_A:
2049 aif1 |= 0x18;
2050 break;
2051 case SND_SOC_DAIFMT_I2S:
2052 aif1 |= 0x10;
2053 break;
2054 case SND_SOC_DAIFMT_RIGHT_J:
2055 break;
2056 case SND_SOC_DAIFMT_LEFT_J:
2057 aif1 |= 0x8;
2058 break;
2059 default:
2060 return -EINVAL;
2061 }
2062
2063 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2064 case SND_SOC_DAIFMT_DSP_A:
2065 case SND_SOC_DAIFMT_DSP_B:
2066 /* frame inversion not valid for DSP modes */
2067 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2068 case SND_SOC_DAIFMT_NB_NF:
2069 break;
2070 case SND_SOC_DAIFMT_IB_NF:
2071 aif1 |= WM8994_AIF1_BCLK_INV;
2072 break;
2073 default:
2074 return -EINVAL;
2075 }
2076 break;
2077
2078 case SND_SOC_DAIFMT_I2S:
2079 case SND_SOC_DAIFMT_RIGHT_J:
2080 case SND_SOC_DAIFMT_LEFT_J:
2081 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2082 case SND_SOC_DAIFMT_NB_NF:
2083 break;
2084 case SND_SOC_DAIFMT_IB_IF:
2085 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2086 break;
2087 case SND_SOC_DAIFMT_IB_NF:
2088 aif1 |= WM8994_AIF1_BCLK_INV;
2089 break;
2090 case SND_SOC_DAIFMT_NB_IF:
2091 aif1 |= WM8994_AIF1_LRCLK_INV;
2092 break;
2093 default:
2094 return -EINVAL;
2095 }
2096 break;
2097 default:
2098 return -EINVAL;
2099 }
2100
c4431df0
MB		 2101 /* The AIF2 format configuration needs to be mirrored to AIF3
2102 * on WM8958 if it's in use so just do it all the time. */
2103 if (control->type == WM8958 && dai->id == 2)
2104 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2105 WM8994_AIF1_LRCLK_INV |
2106 WM8958_AIF3_FMT_MASK, aif1);
2107
9e6e96a1
MB		 2108 snd_soc_update_bits(codec, aif1_reg,
2109 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2110 WM8994_AIF1_FMT_MASK,
2111 aif1);
2112 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2113 ms);
2114
2115 return 0;
2116}
2117
2118static struct {
2119 int val, rate;
2120} srs[] = {
2121 { 0, 8000 },
2122 { 1, 11025 },
2123 { 2, 12000 },
2124 { 3, 16000 },
2125 { 4, 22050 },
2126 { 5, 24000 },
2127 { 6, 32000 },
2128 { 7, 44100 },
2129 { 8, 48000 },
2130 { 9, 88200 },
2131 { 10, 96000 },
2132};
2133
2134static int fs_ratios[] = {
2135 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2136};
2137
2138static int bclk_divs[] = {
2139 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2140 640, 880, 960, 1280, 1760, 1920
2141};
2142
2143static int wm8994_hw_params(struct snd_pcm_substream *substream,
2144 struct snd_pcm_hw_params *params,
2145 struct snd_soc_dai *dai)
2146{
2147 struct snd_soc_codec *codec = dai->codec;
c4431df0 2148 struct wm8994 *control = codec->control_data;
b2c812e2 2149 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2150 int aif1_reg;
b1e43d93 2151 int aif2_reg;
9e6e96a1
MB		 2152 int bclk_reg;
2153 int lrclk_reg;
2154 int rate_reg;
2155 int aif1 = 0;
b1e43d93 2156 int aif2 = 0;
9e6e96a1
MB		 2157 int bclk = 0;
2158 int lrclk = 0;
2159 int rate_val = 0;
2160 int id = dai->id - 1;
2161
2162 int i, cur_val, best_val, bclk_rate, best;
2163
2164 switch (dai->id) {
2165 case 1:
2166 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2167 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2168 bclk_reg = WM8994_AIF1_BCLK;
2169 rate_reg = WM8994_AIF1_RATE;
2170 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2171 wm8994->lrclk_shared[0]) {
9e6e96a1 2172 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2173 } else {
9e6e96a1 2174 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2175 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2176 }
9e6e96a1
MB		 2177 break;
2178 case 2:
2179 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2180 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2181 bclk_reg = WM8994_AIF2_BCLK;
2182 rate_reg = WM8994_AIF2_RATE;
2183 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2184 wm8994->lrclk_shared[1]) {
9e6e96a1 2185 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2186 } else {
9e6e96a1 2187 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2188 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2189 }
9e6e96a1 2190 break;
c4431df0
MB		 2191 case 3:
2192 switch (control->type) {
2193 case WM8958:
2194 aif1_reg = WM8958_AIF3_CONTROL_1;
2195 break;
2196 default:
2197 return 0;
2198 }
9e6e96a1
MB		 2199 default:
2200 return -EINVAL;
2201 }
2202
2203 bclk_rate = params_rate(params) * 2;
2204 switch (params_format(params)) {
2205 case SNDRV_PCM_FORMAT_S16_LE:
2206 bclk_rate *= 16;
2207 break;
2208 case SNDRV_PCM_FORMAT_S20_3LE:
2209 bclk_rate *= 20;
2210 aif1 |= 0x20;
2211 break;
2212 case SNDRV_PCM_FORMAT_S24_LE:
2213 bclk_rate *= 24;
2214 aif1 |= 0x40;
2215 break;
2216 case SNDRV_PCM_FORMAT_S32_LE:
2217 bclk_rate *= 32;
2218 aif1 |= 0x60;
2219 break;
2220 default:
2221 return -EINVAL;
2222 }
2223
2224 /* Try to find an appropriate sample rate; look for an exact match. */
2225 for (i = 0; i < ARRAY_SIZE(srs); i++)
2226 if (srs[i].rate == params_rate(params))
2227 break;
2228 if (i == ARRAY_SIZE(srs))
2229 return -EINVAL;
2230 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2231
2232 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2233 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2234 dai->id, wm8994->aifclk[id], bclk_rate);
2235
b1e43d93
MB		 2236 if (params_channels(params) == 1 &&
2237 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2238 aif2 |= WM8994_AIF1_MONO;
2239
9e6e96a1
MB		 2240 if (wm8994->aifclk[id] == 0) {
2241 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2242 return -EINVAL;
2243 }
2244
2245 /* AIFCLK/fs ratio; look for a close match in either direction */
2246 best = 0;
2247 best_val = abs((fs_ratios[0] * params_rate(params))
2248 - wm8994->aifclk[id]);
2249 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2250 cur_val = abs((fs_ratios[i] * params_rate(params))
2251 - wm8994->aifclk[id]);
2252 if (cur_val >= best_val)
2253 continue;
2254 best = i;
2255 best_val = cur_val;
2256 }
2257 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2258 dai->id, fs_ratios[best]);
2259 rate_val |= best;
2260
2261 /* We may not get quite the right frequency if using
2262 * approximate clocks so look for the closest match that is
2263 * higher than the target (we need to ensure that there enough
2264 * BCLKs to clock out the samples).
2265 */
2266 best = 0;
2267 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2268 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2269 if (cur_val < 0) /* BCLK table is sorted */
2270 break;
2271 best = i;
2272 }
07cd8ada 2273 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2274 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2275 bclk_divs[best], bclk_rate);
2276 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2277
2278 lrclk = bclk_rate / params_rate(params);
2279 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2280 lrclk, bclk_rate / lrclk);
2281
2282 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2283 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2284 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2285 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2286 lrclk);
2287 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2288 WM8994_AIF1CLK_RATE_MASK, rate_val);
2289
2290 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2291 switch (dai->id) {
2292 case 1:
2293 wm8994->dac_rates[0] = params_rate(params);
2294 wm8994_set_retune_mobile(codec, 0);
2295 wm8994_set_retune_mobile(codec, 1);
2296 break;
2297 case 2:
2298 wm8994->dac_rates[1] = params_rate(params);
2299 wm8994_set_retune_mobile(codec, 2);
2300 break;
2301 }
2302 }
2303
2304 return 0;
2305}
2306
c4431df0
MB		 2307static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2308 struct snd_pcm_hw_params *params,
2309 struct snd_soc_dai *dai)
2310{
2311 struct snd_soc_codec *codec = dai->codec;
2312 struct wm8994 *control = codec->control_data;
2313 int aif1_reg;
2314 int aif1 = 0;
2315
2316 switch (dai->id) {
2317 case 3:
2318 switch (control->type) {
2319 case WM8958:
2320 aif1_reg = WM8958_AIF3_CONTROL_1;
2321 break;
2322 default:
2323 return 0;
2324 }
2325 default:
2326 return 0;
2327 }
2328
2329 switch (params_format(params)) {
2330 case SNDRV_PCM_FORMAT_S16_LE:
2331 break;
2332 case SNDRV_PCM_FORMAT_S20_3LE:
2333 aif1 |= 0x20;
2334 break;
2335 case SNDRV_PCM_FORMAT_S24_LE:
2336 aif1 |= 0x40;
2337 break;
2338 case SNDRV_PCM_FORMAT_S32_LE:
2339 aif1 |= 0x60;
2340 break;
2341 default:
2342 return -EINVAL;
2343 }
2344
2345 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2346}
2347
9e6e96a1
MB		 2348static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2349{
2350 struct snd_soc_codec *codec = codec_dai->codec;
2351 int mute_reg;
2352 int reg;
2353
2354 switch (codec_dai->id) {
2355 case 1:
2356 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2357 break;
2358 case 2:
2359 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2360 break;
2361 default:
2362 return -EINVAL;
2363 }
2364
2365 if (mute)
2366 reg = WM8994_AIF1DAC1_MUTE;
2367 else
2368 reg = 0;
2369
2370 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2371
2372 return 0;
2373}
2374
778a76e2
MB		 2375static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2376{
2377 struct snd_soc_codec *codec = codec_dai->codec;
2378 int reg, val, mask;
2379
2380 switch (codec_dai->id) {
2381 case 1:
2382 reg = WM8994_AIF1_MASTER_SLAVE;
2383 mask = WM8994_AIF1_TRI;
2384 break;
2385 case 2:
2386 reg = WM8994_AIF2_MASTER_SLAVE;
2387 mask = WM8994_AIF2_TRI;
2388 break;
2389 case 3:
2390 reg = WM8994_POWER_MANAGEMENT_6;
2391 mask = WM8994_AIF3_TRI;
2392 break;
2393 default:
2394 return -EINVAL;
2395 }
2396
2397 if (tristate)
2398 val = mask;
2399 else
2400 val = 0;
2401
78b3fb46 2402 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2403}
2404
9e6e96a1
MB		 2405#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2406
2407#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2408 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2409
2410static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2411 .set_sysclk = wm8994_set_dai_sysclk,
2412 .set_fmt = wm8994_set_dai_fmt,
2413 .hw_params = wm8994_hw_params,
2414 .digital_mute = wm8994_aif_mute,
2415 .set_pll = wm8994_set_fll,
778a76e2 2416 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2417};
2418
2419static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2420 .set_sysclk = wm8994_set_dai_sysclk,
2421 .set_fmt = wm8994_set_dai_fmt,
2422 .hw_params = wm8994_hw_params,
2423 .digital_mute = wm8994_aif_mute,
2424 .set_pll = wm8994_set_fll,
778a76e2
MB		 2425 .set_tristate = wm8994_set_tristate,
2426};
2427
2428static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2429 .hw_params = wm8994_aif3_hw_params,
778a76e2 2430 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2431};
2432
f0fba2ad 2433static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2434 {
f0fba2ad 2435 .name = "wm8994-aif1",
8c7f78b3 2436 .id = 1,
9e6e96a1
MB		 2437 .playback = {
2438 .stream_name = "AIF1 Playback",
b1e43d93 2439 .channels_min = 1,
9e6e96a1
MB		 2440 .channels_max = 2,
2441 .rates = WM8994_RATES,
2442 .formats = WM8994_FORMATS,
2443 },
2444 .capture = {
2445 .stream_name = "AIF1 Capture",
b1e43d93 2446 .channels_min = 1,
9e6e96a1
MB		 2447 .channels_max = 2,
2448 .rates = WM8994_RATES,
2449 .formats = WM8994_FORMATS,
2450 },
2451 .ops = &wm8994_aif1_dai_ops,
2452 },
2453 {
f0fba2ad 2454 .name = "wm8994-aif2",
8c7f78b3 2455 .id = 2,
9e6e96a1
MB		 2456 .playback = {
2457 .stream_name = "AIF2 Playback",
b1e43d93 2458 .channels_min = 1,
9e6e96a1
MB		 2459 .channels_max = 2,
2460 .rates = WM8994_RATES,
2461 .formats = WM8994_FORMATS,
2462 },
2463 .capture = {
2464 .stream_name = "AIF2 Capture",
b1e43d93 2465 .channels_min = 1,
9e6e96a1
MB		 2466 .channels_max = 2,
2467 .rates = WM8994_RATES,
2468 .formats = WM8994_FORMATS,
2469 },
2470 .ops = &wm8994_aif2_dai_ops,
2471 },
2472 {
f0fba2ad 2473 .name = "wm8994-aif3",
8c7f78b3 2474 .id = 3,
9e6e96a1
MB		 2475 .playback = {
2476 .stream_name = "AIF3 Playback",
b1e43d93 2477 .channels_min = 1,
9e6e96a1
MB		 2478 .channels_max = 2,
2479 .rates = WM8994_RATES,
2480 .formats = WM8994_FORMATS,
2481 },
a8462bde 2482 .capture = {
9e6e96a1 2483 .stream_name = "AIF3 Capture",
b1e43d93 2484 .channels_min = 1,
9e6e96a1
MB		 2485 .channels_max = 2,
2486 .rates = WM8994_RATES,
2487 .formats = WM8994_FORMATS,
2488 },
778a76e2 2489 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2490 }
2491};
9e6e96a1
MB		 2492
2493#ifdef CONFIG_PM
f0fba2ad 2494static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2495{
b2c812e2 2496 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2497 int i, ret;
2498
2499 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2500 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2501 sizeof(struct fll_config));
f0fba2ad 2502 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2503 if (ret < 0)
2504 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2505 i + 1, ret);
2506 }
2507
2508 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2509
2510 return 0;
2511}
2512
f0fba2ad 2513static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2514{
b2c812e2 2515 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2516 int i, ret;
2517
2518 /* Restore the registers */
ca9aef50
MB		 2519 ret = snd_soc_cache_sync(codec);
2520 if (ret != 0)
2521 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2522
2523 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2524
2525 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2526 if (!wm8994->fll_suspend[i].out)
2527 continue;
2528
f0fba2ad 2529 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2530 wm8994->fll_suspend[i].src,
2531 wm8994->fll_suspend[i].in,
2532 wm8994->fll_suspend[i].out);
2533 if (ret < 0)
2534 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2535 i + 1, ret);
2536 }
2537
2538 return 0;
2539}
2540#else
2541#define wm8994_suspend NULL
2542#define wm8994_resume NULL
2543#endif
2544
2545static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2546{
f0fba2ad 2547 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2548 struct wm8994_pdata *pdata = wm8994->pdata;
2549 struct snd_kcontrol_new controls[] = {
2550 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2551 wm8994->retune_mobile_enum,
2552 wm8994_get_retune_mobile_enum,
2553 wm8994_put_retune_mobile_enum),
2554 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2555 wm8994->retune_mobile_enum,
2556 wm8994_get_retune_mobile_enum,
2557 wm8994_put_retune_mobile_enum),
2558 SOC_ENUM_EXT("AIF2 EQ Mode",
2559 wm8994->retune_mobile_enum,
2560 wm8994_get_retune_mobile_enum,
2561 wm8994_put_retune_mobile_enum),
2562 };
2563 int ret, i, j;
2564 const char **t;
2565
2566 /* We need an array of texts for the enum API but the number
2567 * of texts is likely to be less than the number of
2568 * configurations due to the sample rate dependency of the
2569 * configurations. */
2570 wm8994->num_retune_mobile_texts = 0;
2571 wm8994->retune_mobile_texts = NULL;
2572 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2573 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2574 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2575 wm8994->retune_mobile_texts[j]) == 0)
2576 break;
2577 }
2578
2579 if (j != wm8994->num_retune_mobile_texts)
2580 continue;
2581
2582 /* Expand the array... */
2583 t = krealloc(wm8994->retune_mobile_texts,
2584 sizeof(char *) *
2585 (wm8994->num_retune_mobile_texts + 1),
2586 GFP_KERNEL);
2587 if (t == NULL)
2588 continue;
2589
2590 /* ...store the new entry... */
2591 t[wm8994->num_retune_mobile_texts] =
2592 pdata->retune_mobile_cfgs[i].name;
2593
2594 /* ...and remember the new version. */
2595 wm8994->num_retune_mobile_texts++;
2596 wm8994->retune_mobile_texts = t;
2597 }
2598
2599 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2600 wm8994->num_retune_mobile_texts);
2601
2602 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2603 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2604
f0fba2ad 2605 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2606 ARRAY_SIZE(controls));
2607 if (ret != 0)
f0fba2ad 2608 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2609 "Failed to add ReTune Mobile controls: %d\n", ret);
2610}
2611
2612static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2613{
f0fba2ad 2614 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2615 struct wm8994_pdata *pdata = wm8994->pdata;
2616 int ret, i;
2617
2618 if (!pdata)
2619 return;
2620
2621 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2622 pdata->lineout2_diff,
2623 pdata->lineout1fb,
2624 pdata->lineout2fb,
2625 pdata->jd_scthr,
2626 pdata->jd_thr,
2627 pdata->micbias1_lvl,
2628 pdata->micbias2_lvl);
2629
2630 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2631
2632 if (pdata->num_drc_cfgs) {
2633 struct snd_kcontrol_new controls[] = {
2634 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2635 wm8994_get_drc_enum, wm8994_put_drc_enum),
2636 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2637 wm8994_get_drc_enum, wm8994_put_drc_enum),
2638 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2639 wm8994_get_drc_enum, wm8994_put_drc_enum),
2640 };
2641
2642 /* We need an array of texts for the enum API */
2643 wm8994->drc_texts = kmalloc(sizeof(char *)
2644 * pdata->num_drc_cfgs, GFP_KERNEL);
2645 if (!wm8994->drc_texts) {
f0fba2ad 2646 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2647 "Failed to allocate %d DRC config texts\n",
2648 pdata->num_drc_cfgs);
2649 return;
2650 }
2651
2652 for (i = 0; i < pdata->num_drc_cfgs; i++)
2653 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2654
2655 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2656 wm8994->drc_enum.texts = wm8994->drc_texts;
2657
f0fba2ad 2658 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2659 ARRAY_SIZE(controls));
2660 if (ret != 0)
f0fba2ad 2661 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2662 "Failed to add DRC mode controls: %d\n", ret);
2663
2664 for (i = 0; i < WM8994_NUM_DRC; i++)
2665 wm8994_set_drc(codec, i);
2666 }
2667
2668 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2669 pdata->num_retune_mobile_cfgs);
2670
131d8106
MB		 2671 if (pdata->num_mbc_cfgs) {
2672 struct snd_kcontrol_new control[] = {
2673 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2674 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2675 };
2676
2677 /* We need an array of texts for the enum API */
2678 wm8994->mbc_texts = kmalloc(sizeof(char *)
2679 * pdata->num_mbc_cfgs, GFP_KERNEL);
2680 if (!wm8994->mbc_texts) {
2681 dev_err(wm8994->codec->dev,
2682 "Failed to allocate %d MBC config texts\n",
2683 pdata->num_mbc_cfgs);
2684 return;
2685 }
2686
2687 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2688 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2689
2690 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2691 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2692
2693 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2694 if (ret != 0)
2695 dev_err(wm8994->codec->dev,
2696 "Failed to add MBC mode controls: %d\n", ret);
2697 }
2698
9e6e96a1
MB		 2699 if (pdata->num_retune_mobile_cfgs)
2700 wm8994_handle_retune_mobile_pdata(wm8994);
2701 else
f0fba2ad 2702 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2703 ARRAY_SIZE(wm8994_eq_controls));
2704}
2705
88766984
MB		 2706/**
2707 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2708 *
2709 * @codec: WM8994 codec
2710 * @jack: jack to report detection events on
2711 * @micbias: microphone bias to detect on
2712 * @det: value to report for presence detection
2713 * @shrt: value to report for short detection
2714 *
2715 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2716 * being used to bring out signals to the processor then only platform
5ab230a7 2717 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2718 * be configured using snd_soc_jack_add_gpios() instead.
2719 *
2720 * Configuration of detection levels is available via the micbias1_lvl
2721 * and micbias2_lvl platform data members.
2722 */
2723int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2724 int micbias, int det, int shrt)
2725{
b2c812e2 2726 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2727 struct wm8994_micdet *micdet;
3a423157 2728 struct wm8994 *control = codec->control_data;
88766984
MB		 2729 int reg;
2730
3a423157
MB		 2731 if (control->type != WM8994)
2732 return -EINVAL;
2733
88766984
MB		 2734 switch (micbias) {
2735 case 1:
2736 micdet = &wm8994->micdet[0];
2737 break;
2738 case 2:
2739 micdet = &wm8994->micdet[1];
2740 break;
2741 default:
2742 return -EINVAL;
2743 }
2744
2745 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2746 micbias, det, shrt);
2747
2748 /* Store the configuration */
2749 micdet->jack = jack;
2750 micdet->det = det;
2751 micdet->shrt = shrt;
2752
2753 /* If either of the jacks is set up then enable detection */
2754 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2755 reg = WM8994_MICD_ENA;
2756 else
2757 reg = 0;
2758
2759 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2760
2761 return 0;
2762}
2763EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2764
2765static irqreturn_t wm8994_mic_irq(int irq, void *data)
2766{
2767 struct wm8994_priv *priv = data;
f0fba2ad 2768 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2769 int reg;
2770 int report;
2771
7116f452 2772#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2773 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2774#endif
2bbb5d66 2775
88766984
MB		 2776 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2777 if (reg < 0) {
2778 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2779 reg);
2780 return IRQ_HANDLED;
2781 }
2782
2783 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2784
2785 report = 0;
2786 if (reg & WM8994_MIC1_DET_STS)
2787 report |= priv->micdet[0].det;
2788 if (reg & WM8994_MIC1_SHRT_STS)
2789 report |= priv->micdet[0].shrt;
2790 snd_soc_jack_report(priv->micdet[0].jack, report,
2791 priv->micdet[0].det | priv->micdet[0].shrt);
2792
2793 report = 0;
2794 if (reg & WM8994_MIC2_DET_STS)
2795 report |= priv->micdet[1].det;
2796 if (reg & WM8994_MIC2_SHRT_STS)
2797 report |= priv->micdet[1].shrt;
2798 snd_soc_jack_report(priv->micdet[1].jack, report,
2799 priv->micdet[1].det | priv->micdet[1].shrt);
2800
2801 return IRQ_HANDLED;
2802}
2803
821edd2f
MB		 2804/* Default microphone detection handler for WM8958 - the user can
2805 * override this if they wish.
2806 */
2807static void wm8958_default_micdet(u16 status, void *data)
2808{
2809 struct snd_soc_codec *codec = data;
2810 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2811 int report = 0;
2812
2813 /* If nothing present then clear our statuses */
2814 if (!(status & WM8958_MICD_STS)) {
2815 wm8994->jack_is_video = false;
2816 wm8994->jack_is_mic = false;
2817 goto done;
2818 }
2819
2820 /* Assume anything over 475 ohms is a microphone and remember
2821 * that we've seen one (since buttons override it) */
2822 if (status & 0x600)
2823 wm8994->jack_is_mic = true;
2824 if (wm8994->jack_is_mic)
2825 report |= SND_JACK_MICROPHONE;
2826
2827 /* Video has an impedence of approximately 75 ohms; assume
2828 * this isn't used as a button and remember it since buttons
2829 * override it. */
2830 if (status & 0x40)
2831 wm8994->jack_is_video = true;
2832 if (wm8994->jack_is_video)
2833 report |= SND_JACK_VIDEOOUT;
2834
2835 /* Everything else is buttons; just assign slots */
2836 if (status & 0x4)
2837 report |= SND_JACK_BTN_0;
2838 if (status & 0x8)
2839 report |= SND_JACK_BTN_1;
2840 if (status & 0x10)
2841 report |= SND_JACK_BTN_2;
2842 if (status & 0x20)
2843 report |= SND_JACK_BTN_3;
2844 if (status & 0x80)
2845 report |= SND_JACK_BTN_4;
2846 if (status & 0x100)
2847 report |= SND_JACK_BTN_5;
2848
2849done:
2850 snd_soc_jack_report(wm8994->micdet[0].jack,
2851 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2852 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2853 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2854 report);
2855}
2856
2857/**
2858 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2859 *
2860 * @codec: WM8958 codec
2861 * @jack: jack to report detection events on
2862 *
2863 * Enable microphone detection functionality for the WM8958. By
2864 * default simple detection which supports the detection of up to 6
2865 * buttons plus video and microphone functionality is supported.
2866 *
2867 * The WM8958 has an advanced jack detection facility which is able to
2868 * support complex accessory detection, especially when used in
2869 * conjunction with external circuitry. In order to provide maximum
2870 * flexiblity a callback is provided which allows a completely custom
2871 * detection algorithm.
2872 */
2873int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2874 wm8958_micdet_cb cb, void *cb_data)
2875{
2876 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2877 struct wm8994 *control = codec->control_data;
2878
2879 if (control->type != WM8958)
2880 return -EINVAL;
2881
2882 if (jack) {
2883 if (!cb) {
2884 dev_dbg(codec->dev, "Using default micdet callback\n");
2885 cb = wm8958_default_micdet;
2886 cb_data = codec;
2887 }
2888
2889 wm8994->micdet[0].jack = jack;
2890 wm8994->jack_cb = cb;
2891 wm8994->jack_cb_data = cb_data;
2892
2893 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2894 WM8958_MICD_ENA, WM8958_MICD_ENA);
2895 } else {
2896 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2897 WM8958_MICD_ENA, 0);
2898 }
2899
2900 return 0;
2901}
2902EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2903
2904static irqreturn_t wm8958_mic_irq(int irq, void *data)
2905{
2906 struct wm8994_priv *wm8994 = data;
2907 struct snd_soc_codec *codec = wm8994->codec;
2908 int reg;
2909
2910 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2911 if (reg < 0) {
2912 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2913 reg);
2914 return IRQ_NONE;
2915 }
2916
2917 if (!(reg & WM8958_MICD_VALID)) {
2918 dev_dbg(codec->dev, "Mic detect data not valid\n");
2919 goto out;
2920 }
2921
7116f452 2922#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2923 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2924#endif
2bbb5d66 2925
821edd2f
MB		 2926 if (wm8994->jack_cb)
2927 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2928 else
2929 dev_warn(codec->dev, "Accessory detection with no callback\n");
2930
2931out:
2932 return IRQ_HANDLED;
2933}
2934
f0fba2ad 2935static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2936{
3a423157 2937 struct wm8994 *control;
9e6e96a1 2938 struct wm8994_priv *wm8994;
ce6120cc 2939 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2940 int ret, i;
9e6e96a1 2941
f0fba2ad 2942 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2943 control = codec->control_data;
9e6e96a1
MB		 2944
2945 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2946 if (wm8994 == NULL)
9e6e96a1 2947 return -ENOMEM;
b2c812e2 2948 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 2949
2950 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2951 wm8994->codec = codec;
9e6e96a1 2952
39fb51a1
MB		 2953 pm_runtime_enable(codec->dev);
2954 pm_runtime_resume(codec->dev);
2955
ca9aef50
MB		 2956 /* Read our current status back from the chip - we don't want to
2957 * reset as this may interfere with the GPIO or LDO operation. */
2958 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2959 if (!wm8994_readable(i) || wm8994_volatile(i))
2960 continue;
9e6e96a1 2961
ca9aef50
MB		 2962 ret = wm8994_reg_read(codec->control_data, i);
2963 if (ret <= 0)
2964 continue;
2965
2966 ret = snd_soc_cache_write(codec, i, ret);
2967 if (ret != 0) {
2968 dev_err(codec->dev,
2969 "Failed to initialise cache for 0x%x: %d\n",
2970 i, ret);
2971 goto err;
2972 }
2973 }
9e6e96a1
MB		 2974
2975 /* Set revision-specific configuration */
b6b05691 2976 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2977 switch (control->type) {
2978 case WM8994:
2979 switch (wm8994->revision) {
2980 case 2:
2981 case 3:
2982 wm8994->hubs.dcs_codes = -5;
2983 wm8994->hubs.hp_startup_mode = 1;
2984 wm8994->hubs.dcs_readback_mode = 1;
2985 break;
2986 default:
2987 wm8994->hubs.dcs_readback_mode = 1;
2988 break;
2989 }
2990
2991 case WM8958:
8437f700 2992 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2993 break;
3a423157 2994
9e6e96a1
MB		 2995 default:
2996 break;
2997 }
9e6e96a1 2998
3a423157
MB		 2999 switch (control->type) {
3000 case WM8994:
3001 ret = wm8994_request_irq(codec->control_data,
3002 WM8994_IRQ_MIC1_DET,
3003 wm8994_mic_irq, "Mic 1 detect",
3004 wm8994);
3005 if (ret != 0)
3006 dev_warn(codec->dev,
3007 "Failed to request Mic1 detect IRQ: %d\n",
3008 ret);
3009
3010 ret = wm8994_request_irq(codec->control_data,
3011 WM8994_IRQ_MIC1_SHRT,
3012 wm8994_mic_irq, "Mic 1 short",
3013 wm8994);
3014 if (ret != 0)
3015 dev_warn(codec->dev,
3016 "Failed to request Mic1 short IRQ: %d\n",
3017 ret);
3018
3019 ret = wm8994_request_irq(codec->control_data,
3020 WM8994_IRQ_MIC2_DET,
3021 wm8994_mic_irq, "Mic 2 detect",
3022 wm8994);
3023 if (ret != 0)
3024 dev_warn(codec->dev,
3025 "Failed to request Mic2 detect IRQ: %d\n",
3026 ret);
3027
3028 ret = wm8994_request_irq(codec->control_data,
3029 WM8994_IRQ_MIC2_SHRT,
3030 wm8994_mic_irq, "Mic 2 short",
3031 wm8994);
3032 if (ret != 0)
3033 dev_warn(codec->dev,
3034 "Failed to request Mic2 short IRQ: %d\n",
3035 ret);
3036 break;
821edd2f
MB		 3037
3038 case WM8958:
3039 ret = wm8994_request_irq(codec->control_data,
3040 WM8994_IRQ_MIC1_DET,
3041 wm8958_mic_irq, "Mic detect",
3042 wm8994);
3043 if (ret != 0)
3044 dev_warn(codec->dev,
3045 "Failed to request Mic detect IRQ: %d\n",
3046 ret);
3047 break;
3a423157 3048 }
88766984 3049
9e6e96a1
MB		 3050 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3051 * configured on init - if a system wants to do this dynamically
3052 * at runtime we can deal with that then.
3053 */
3054 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3055 if (ret < 0) {
3056 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3057 goto err_irq;
9e6e96a1
MB		 3058 }
3059 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3060 wm8994->lrclk_shared[0] = 1;
3061 wm8994_dai[0].symmetric_rates = 1;
3062 } else {
3063 wm8994->lrclk_shared[0] = 0;
3064 }
3065
3066 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3067 if (ret < 0) {
3068 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3069 goto err_irq;
9e6e96a1
MB		 3070 }
3071 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3072 wm8994->lrclk_shared[1] = 1;
3073 wm8994_dai[1].symmetric_rates = 1;
3074 } else {
3075 wm8994->lrclk_shared[1] = 0;
3076 }
3077
9e6e96a1
MB		 3078 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3079
9e6e96a1
MB		 3080 /* Latch volume updates (right only; we always do left then right). */
3081 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3082 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3083 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3084 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3085 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3086 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3087 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3088 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3089 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3090 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3091 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3092 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3093 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3094 WM8994_DAC1_VU, WM8994_DAC1_VU);
3095 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3096 WM8994_DAC2_VU, WM8994_DAC2_VU);
3097
3098 /* Set the low bit of the 3D stereo depth so TLV matches */
3099 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3100 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3101 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3102 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3103 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3104 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3105 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3106 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3107 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3108
d1ce6b20
MB		 3109 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3110 * behaviour on idle TDM clock cycles. */
3111 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3112 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3113
9e6e96a1
MB		 3114 wm8994_update_class_w(codec);
3115
f0fba2ad 3116 wm8994_handle_pdata(wm8994);
9e6e96a1 3117
f0fba2ad
LG		 3118 wm_hubs_add_analogue_controls(codec);
3119 snd_soc_add_controls(codec, wm8994_snd_controls,
3120 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3121 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3122 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3123
3124 switch (control->type) {
3125 case WM8994:
3126 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3127 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3128 break;
3129 case WM8958:
3130 snd_soc_add_controls(codec, wm8958_snd_controls,
3131 ARRAY_SIZE(wm8958_snd_controls));
3132 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3133 ARRAY_SIZE(wm8958_dapm_widgets));
3134 break;
3135 }
3136
3137
f0fba2ad 3138 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3139 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3140
c4431df0
MB		 3141 switch (control->type) {
3142 case WM8994:
3143 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3144 ARRAY_SIZE(wm8994_intercon));
6ed8f148
MB		 3145
3146 if (wm8994->revision < 4)
3147 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3148 ARRAY_SIZE(wm8994_revd_intercon));
3149
c4431df0
MB		 3150 break;
3151 case WM8958:
3152 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3153 ARRAY_SIZE(wm8958_intercon));
3154 break;
3155 }
3156
9e6e96a1
MB		 3157 return 0;
3158
88766984
MB		 3159err_irq:
3160 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3161 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3162 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3163 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
9e6e96a1
MB		 3164err:
3165 kfree(wm8994);
3166 return ret;
3167}
3168
f0fba2ad 3169static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3170{
f0fba2ad 3171 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3172 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 3173
3174 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3175
39fb51a1
MB		 3176 pm_runtime_disable(codec->dev);
3177
3a423157
MB		 3178 switch (control->type) {
3179 case WM8994:
3180 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3181 wm8994);
3182 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3183 wm8994);
3184 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3185 wm8994);
3186 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3187 wm8994);
3188 break;
821edd2f
MB		 3189
3190 case WM8958:
3191 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3192 wm8994);
3193 break;
3a423157 3194 }
24fb2b11
AL		 3195 kfree(wm8994->retune_mobile_texts);
3196 kfree(wm8994->drc_texts);
9e6e96a1 3197 kfree(wm8994);
9e6e96a1
MB		 3198
3199 return 0;
3200}
3201
f0fba2ad
LG		 3202static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3203 .probe = wm8994_codec_probe,
3204 .remove = wm8994_codec_remove,
3205 .suspend = wm8994_suspend,
3206 .resume = wm8994_resume,
ca9aef50
MB		 3207 .read = wm8994_read,
3208 .write = wm8994_write,
eba19fdd
MB		 3209 .readable_register = wm8994_readable,
3210 .volatile_register = wm8994_volatile,
f0fba2ad 3211 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3212
3213 .reg_cache_size = WM8994_CACHE_SIZE,
3214 .reg_cache_default = wm8994_reg_defaults,
3215 .reg_word_size = 2,
2e19b0c8 3216 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3217};
3218
3219static int __devinit wm8994_probe(struct platform_device *pdev)
3220{
3221 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3222 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3223}
3224
3225static int __devexit wm8994_remove(struct platform_device *pdev)
3226{
3227 snd_soc_unregister_codec(&pdev->dev);
3228 return 0;
3229}
3230
9e6e96a1
MB		 3231static struct platform_driver wm8994_codec_driver = {
3232 .driver = {
3233 .name = "wm8994-codec",
3234 .owner = THIS_MODULE,
3235 },
f0fba2ad
LG		 3236 .probe = wm8994_probe,
3237 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3238};
3239
3240static __init int wm8994_init(void)
3241{
3242 return platform_driver_register(&wm8994_codec_driver);
3243}
3244module_init(wm8994_init);
3245
3246static __exit void wm8994_exit(void)
3247{
3248 platform_driver_unregister(&wm8994_codec_driver);
3249}
3250module_exit(wm8994_exit);
3251
3252
3253MODULE_DESCRIPTION("ASoC WM8994 driver");
3254MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3255MODULE_LICENSE("GPL");
3256MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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