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ASoC: wm8994: Don't test for NULL before release_firmware()
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
149c53b5
MB		 689 if (!wm8994->jackdet || !wm8994->jack_cb)
690 return;
691
28e33269
MB		 692 if (!wm8994->jackdet || !wm8994->jack_cb)
693 return;
694
af6b6fe4
MB		 695 if (wm8994->active_refcount)
696 mode = WM1811_JACKDET_MODE_AUDIO;
697
4752a887 698 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 699 return;
700
4752a887 701 wm8994->jackdet_mode = mode;
1defde2a 702
4752a887
MB		 703 /* Always use audio mode to detect while the system is active */
704 if (mode != WM1811_JACKDET_MODE_NONE)
705 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 706
4752a887
MB		 707 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
708 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 709}
710
711static void active_reference(struct snd_soc_codec *codec)
712{
713 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
714
715 mutex_lock(&wm8994->accdet_lock);
716
717 wm8994->active_refcount++;
718
719 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
720 wm8994->active_refcount);
721
1defde2a
MB		 722 /* If we're using jack detection go into audio mode */
723 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 724
725 mutex_unlock(&wm8994->accdet_lock);
726}
727
728static void active_dereference(struct snd_soc_codec *codec)
729{
730 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
731 u16 mode;
732
733 mutex_lock(&wm8994->accdet_lock);
734
735 wm8994->active_refcount--;
736
737 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
738 wm8994->active_refcount);
739
740 if (wm8994->active_refcount == 0) {
741 /* Go into appropriate detection only mode */
1defde2a
MB		 742 if (wm8994->jack_mic || wm8994->mic_detecting)
743 mode = WM1811_JACKDET_MODE_MIC;
744 else
745 mode = WM1811_JACKDET_MODE_JACK;
746
747 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 748 }
749
750 mutex_unlock(&wm8994->accdet_lock);
751}
752
9e6e96a1
MB		 753static int clk_sys_event(struct snd_soc_dapm_widget *w,
754 struct snd_kcontrol *kcontrol, int event)
755{
756 struct snd_soc_codec *codec = w->codec;
757
758 switch (event) {
759 case SND_SOC_DAPM_PRE_PMU:
760 return configure_clock(codec);
761
762 case SND_SOC_DAPM_POST_PMD:
763 configure_clock(codec);
764 break;
765 }
766
767 return 0;
768}
769
4b7ed83a
MB		 770static void vmid_reference(struct snd_soc_codec *codec)
771{
772 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
773
db966f8a
MB		 774 pm_runtime_get_sync(codec->dev);
775
4b7ed83a
MB		 776 wm8994->vmid_refcount++;
777
778 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
779 wm8994->vmid_refcount);
780
781 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 782 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 783 WM8994_LINEOUT1_DISCH |
22f8d055 784 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 785
f7085641
MB		 786 wm_hubs_vmid_ena(codec);
787
22f8d055
MB		 788 switch (wm8994->vmid_mode) {
789 default:
790 WARN_ON(0 == "Invalid VMID mode");
791 case WM8994_VMID_NORMAL:
792 /* Startup bias, VMID ramp & buffer */
793 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
794 WM8994_BIAS_SRC |
795 WM8994_VMID_DISCH |
796 WM8994_STARTUP_BIAS_ENA |
797 WM8994_VMID_BUF_ENA |
798 WM8994_VMID_RAMP_MASK,
799 WM8994_BIAS_SRC |
800 WM8994_STARTUP_BIAS_ENA |
801 WM8994_VMID_BUF_ENA |
802 (0x3 << WM8994_VMID_RAMP_SHIFT));
803
804 /* Main bias enable, VMID=2x40k */
805 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
806 WM8994_BIAS_ENA |
807 WM8994_VMID_SEL_MASK,
808 WM8994_BIAS_ENA | 0x2);
809
810 msleep(50);
811
812 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
813 WM8994_VMID_RAMP_MASK |
814 WM8994_BIAS_SRC,
815 0);
816 break;
cc6d5a8c 817
22f8d055
MB		 818 case WM8994_VMID_FORCE:
819 /* Startup bias, slow VMID ramp & buffer */
820 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
821 WM8994_BIAS_SRC |
822 WM8994_VMID_DISCH |
823 WM8994_STARTUP_BIAS_ENA |
824 WM8994_VMID_BUF_ENA |
825 WM8994_VMID_RAMP_MASK,
826 WM8994_BIAS_SRC |
827 WM8994_STARTUP_BIAS_ENA |
828 WM8994_VMID_BUF_ENA |
829 (0x2 << WM8994_VMID_RAMP_SHIFT));
830
831 /* Main bias enable, VMID=2x40k */
832 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
833 WM8994_BIAS_ENA |
834 WM8994_VMID_SEL_MASK,
835 WM8994_BIAS_ENA | 0x2);
836
837 msleep(400);
838
839 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
840 WM8994_VMID_RAMP_MASK |
841 WM8994_BIAS_SRC,
842 0);
843 break;
844 }
4b7ed83a
MB		 845 }
846}
847
848static void vmid_dereference(struct snd_soc_codec *codec)
849{
850 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
851
852 wm8994->vmid_refcount--;
853
854 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
855 wm8994->vmid_refcount);
856
857 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 858 if (wm8994->hubs.lineout1_se)
859 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
860 WM8994_LINEOUT1N_ENA |
861 WM8994_LINEOUT1P_ENA,
862 WM8994_LINEOUT1N_ENA |
863 WM8994_LINEOUT1P_ENA);
864
865 if (wm8994->hubs.lineout2_se)
866 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
867 WM8994_LINEOUT2N_ENA |
868 WM8994_LINEOUT2P_ENA,
869 WM8994_LINEOUT2N_ENA |
870 WM8994_LINEOUT2P_ENA);
871
872 /* Start discharging VMID */
4b7ed83a
MB		 873 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
874 WM8994_BIAS_SRC |
22f8d055 875 WM8994_VMID_DISCH,
4b7ed83a 876 WM8994_BIAS_SRC |
22f8d055 877 WM8994_VMID_DISCH);
4b7ed83a 878
22f8d055
MB		 879 switch (wm8994->vmid_mode) {
880 case WM8994_VMID_FORCE:
881 msleep(350);
882 break;
883 default:
884 break;
885 }
4b7ed83a 886
22f8d055
MB		 887 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
888 WM8994_VROI, WM8994_VROI);
e85b26ce 889
22f8d055 890 /* Active discharge */
4b7ed83a
MB		 891 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
892 WM8994_LINEOUT1_DISCH |
893 WM8994_LINEOUT2_DISCH,
894 WM8994_LINEOUT1_DISCH |
895 WM8994_LINEOUT2_DISCH);
896
22f8d055
MB		 897 msleep(150);
898
899 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
900 WM8994_LINEOUT1N_ENA |
901 WM8994_LINEOUT1P_ENA |
902 WM8994_LINEOUT2N_ENA |
903 WM8994_LINEOUT2P_ENA, 0);
904
905 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
906 WM8994_VROI, 0);
4b7ed83a
MB		 907
908 /* Switch off startup biases */
909 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
910 WM8994_BIAS_SRC |
911 WM8994_STARTUP_BIAS_ENA |
912 WM8994_VMID_BUF_ENA |
913 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 914
915 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
916 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
917
918 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
919 WM8994_VMID_RAMP_MASK, 0);
4b7ed83a 920 }
db966f8a
MB		 921
922 pm_runtime_put(codec->dev);
4b7ed83a
MB		 923}
924
925static int vmid_event(struct snd_soc_dapm_widget *w,
926 struct snd_kcontrol *kcontrol, int event)
927{
928 struct snd_soc_codec *codec = w->codec;
929
930 switch (event) {
931 case SND_SOC_DAPM_PRE_PMU:
932 vmid_reference(codec);
933 break;
934
935 case SND_SOC_DAPM_POST_PMD:
936 vmid_dereference(codec);
937 break;
938 }
939
940 return 0;
941}
942
9e6e96a1
MB		 943static void wm8994_update_class_w(struct snd_soc_codec *codec)
944{
fec6dd83 945 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 946 int enable = 1;
947 int source = 0; /* GCC flow analysis can't track enable */
948 int reg, reg_r;
949
950 /* Only support direct DAC->headphone paths */
951 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
952 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 953 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 954 enable = 0;
955 }
956
957 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
958 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 959 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 960 enable = 0;
961 }
962
963 /* We also need the same setting for L/R and only one path */
964 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
965 switch (reg) {
966 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 967 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 968 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
969 break;
970 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 971 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 972 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
973 break;
974 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 975 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 976 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
977 break;
978 default:
ee839a21 979 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 980 enable = 0;
981 break;
982 }
983
984 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
985 if (reg_r != reg) {
ee839a21 986 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 987 enable = 0;
988 }
989
990 if (enable) {
991 dev_dbg(codec->dev, "Class W enabled\n");
992 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
993 WM8994_CP_DYN_PWR |
994 WM8994_CP_DYN_SRC_SEL_MASK,
995 source | WM8994_CP_DYN_PWR);
fec6dd83 996 wm8994->hubs.class_w = true;
9e6e96a1
MB		 997
998 } else {
999 dev_dbg(codec->dev, "Class W disabled\n");
1000 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1001 WM8994_CP_DYN_PWR, 0);
fec6dd83 1002 wm8994->hubs.class_w = false;
9e6e96a1
MB		 1003 }
1004}
1005
173efa09
DP		 1006static int late_enable_ev(struct snd_soc_dapm_widget *w,
1007 struct snd_kcontrol *kcontrol, int event)
1008{
1009 struct snd_soc_codec *codec = w->codec;
1010 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1011
1012 switch (event) {
1013 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 1014 if (wm8994->aif1clk_enable) {
173efa09
DP		 1015 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1016 WM8994_AIF1CLK_ENA_MASK,
1017 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 1018 wm8994->aif1clk_enable = 0;
1019 }
1020 if (wm8994->aif2clk_enable) {
173efa09
DP		 1021 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1022 WM8994_AIF2CLK_ENA_MASK,
1023 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 1024 wm8994->aif2clk_enable = 0;
1025 }
173efa09
DP		 1026 break;
1027 }
1028
c6b7b570
MB		 1029 /* We may also have postponed startup of DSP, handle that. */
1030 wm8958_aif_ev(w, kcontrol, event);
1031
173efa09
DP		 1032 return 0;
1033}
1034
1035static int late_disable_ev(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *kcontrol, int event)
1037{
1038 struct snd_soc_codec *codec = w->codec;
1039 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1040
1041 switch (event) {
1042 case SND_SOC_DAPM_POST_PMD:
a3cff81a 1043 if (wm8994->aif1clk_disable) {
173efa09
DP		 1044 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1045 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 1046 wm8994->aif1clk_disable = 0;
173efa09 1047 }
a3cff81a 1048 if (wm8994->aif2clk_disable) {
173efa09
DP		 1049 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1050 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 1051 wm8994->aif2clk_disable = 0;
173efa09
DP		 1052 }
1053 break;
1054 }
1055
1056 return 0;
1057}
1058
1059static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1060 struct snd_kcontrol *kcontrol, int event)
1061{
1062 struct snd_soc_codec *codec = w->codec;
1063 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1064
1065 switch (event) {
1066 case SND_SOC_DAPM_PRE_PMU:
1067 wm8994->aif1clk_enable = 1;
1068 break;
a3cff81a
DP		 1069 case SND_SOC_DAPM_POST_PMD:
1070 wm8994->aif1clk_disable = 1;
1071 break;
173efa09
DP		 1072 }
1073
1074 return 0;
1075}
1076
1077static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1078 struct snd_kcontrol *kcontrol, int event)
1079{
1080 struct snd_soc_codec *codec = w->codec;
1081 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1082
1083 switch (event) {
1084 case SND_SOC_DAPM_PRE_PMU:
1085 wm8994->aif2clk_enable = 1;
1086 break;
a3cff81a
DP		 1087 case SND_SOC_DAPM_POST_PMD:
1088 wm8994->aif2clk_disable = 1;
1089 break;
173efa09
DP		 1090 }
1091
1092 return 0;
1093}
1094
04d28681
DP		 1095static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1096 struct snd_kcontrol *kcontrol, int event)
1097{
1098 late_enable_ev(w, kcontrol, event);
1099 return 0;
1100}
1101
b462c6e6
DP		 1102static int micbias_ev(struct snd_soc_dapm_widget *w,
1103 struct snd_kcontrol *kcontrol, int event)
1104{
1105 late_enable_ev(w, kcontrol, event);
1106 return 0;
1107}
1108
c52fd021
DP		 1109static int dac_ev(struct snd_soc_dapm_widget *w,
1110 struct snd_kcontrol *kcontrol, int event)
1111{
1112 struct snd_soc_codec *codec = w->codec;
1113 unsigned int mask = 1 << w->shift;
1114
1115 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1116 mask, mask);
1117 return 0;
1118}
1119
9e6e96a1
MB		 1120static const char *hp_mux_text[] = {
1121 "Mixer",
1122 "DAC",
1123};
1124
1125#define WM8994_HP_ENUM(xname, xenum) \
1126{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1127 .info = snd_soc_info_enum_double, \
1128 .get = snd_soc_dapm_get_enum_double, \
1129 .put = wm8994_put_hp_enum, \
1130 .private_value = (unsigned long)&xenum }
1131
1132static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1133 struct snd_ctl_elem_value *ucontrol)
1134{
9d03545d
JN		 1135 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1136 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1137 struct snd_soc_codec *codec = w->codec;
1138 int ret;
1139
1140 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1141
1142 wm8994_update_class_w(codec);
1143
1144 return ret;
1145}
1146
1147static const struct soc_enum hpl_enum =
1148 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1149
1150static const struct snd_kcontrol_new hpl_mux =
1151 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1152
1153static const struct soc_enum hpr_enum =
1154 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1155
1156static const struct snd_kcontrol_new hpr_mux =
1157 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1158
1159static const char *adc_mux_text[] = {
1160 "ADC",
1161 "DMIC",
1162};
1163
1164static const struct soc_enum adc_enum =
1165 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1166
1167static const struct snd_kcontrol_new adcl_mux =
1168 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1169
1170static const struct snd_kcontrol_new adcr_mux =
1171 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1172
1173static const struct snd_kcontrol_new left_speaker_mixer[] = {
1174SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1175SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1176SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1177SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1178SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1179};
1180
1181static const struct snd_kcontrol_new right_speaker_mixer[] = {
1182SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1183SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1184SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1185SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1186SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1187};
1188
1189/* Debugging; dump chip status after DAPM transitions */
1190static int post_ev(struct snd_soc_dapm_widget *w,
1191 struct snd_kcontrol *kcontrol, int event)
1192{
1193 struct snd_soc_codec *codec = w->codec;
1194 dev_dbg(codec->dev, "SRC status: %x\n",
1195 snd_soc_read(codec,
1196 WM8994_RATE_STATUS));
1197 return 0;
1198}
1199
1200static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1201SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1202 1, 1, 0),
1203SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1204 0, 1, 0),
1205};
1206
1207static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1208SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1209 1, 1, 0),
1210SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1211 0, 1, 0),
1212};
1213
a3257ba8
MB		 1214static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1215SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1216 1, 1, 0),
1217SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1218 0, 1, 0),
1219};
1220
1221static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1222SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1223 1, 1, 0),
1224SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1225 0, 1, 0),
1226};
1227
9e6e96a1
MB		 1228static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1229SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1230 5, 1, 0),
1231SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1232 4, 1, 0),
1233SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1234 2, 1, 0),
1235SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1236 1, 1, 0),
1237SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1238 0, 1, 0),
1239};
1240
1241static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1242SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1243 5, 1, 0),
1244SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1245 4, 1, 0),
1246SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1247 2, 1, 0),
1248SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1249 1, 1, 0),
1250SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1251 0, 1, 0),
1252};
1253
1254#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1255{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1256 .info = snd_soc_info_volsw, \
1257 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1258 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1259
1260static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1261 struct snd_ctl_elem_value *ucontrol)
1262{
9d03545d
JN		 1263 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1264 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1265 struct snd_soc_codec *codec = w->codec;
1266 int ret;
1267
1268 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1269
1270 wm8994_update_class_w(codec);
1271
1272 return ret;
1273}
1274
1275static const struct snd_kcontrol_new dac1l_mix[] = {
1276WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1277 5, 1, 0),
1278WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1279 4, 1, 0),
1280WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1281 2, 1, 0),
1282WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1283 1, 1, 0),
1284WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1285 0, 1, 0),
1286};
1287
1288static const struct snd_kcontrol_new dac1r_mix[] = {
1289WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1290 5, 1, 0),
1291WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1292 4, 1, 0),
1293WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1294 2, 1, 0),
1295WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1296 1, 1, 0),
1297WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1298 0, 1, 0),
1299};
1300
1301static const char *sidetone_text[] = {
1302 "ADC/DMIC1", "DMIC2",
1303};
1304
1305static const struct soc_enum sidetone1_enum =
1306 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1307
1308static const struct snd_kcontrol_new sidetone1_mux =
1309 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1310
1311static const struct soc_enum sidetone2_enum =
1312 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1313
1314static const struct snd_kcontrol_new sidetone2_mux =
1315 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1316
1317static const char *aif1dac_text[] = {
1318 "AIF1DACDAT", "AIF3DACDAT",
1319};
1320
1321static const struct soc_enum aif1dac_enum =
1322 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1323
1324static const struct snd_kcontrol_new aif1dac_mux =
1325 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1326
1327static const char *aif2dac_text[] = {
1328 "AIF2DACDAT", "AIF3DACDAT",
1329};
1330
1331static const struct soc_enum aif2dac_enum =
1332 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1333
1334static const struct snd_kcontrol_new aif2dac_mux =
1335 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1336
1337static const char *aif2adc_text[] = {
1338 "AIF2ADCDAT", "AIF3DACDAT",
1339};
1340
1341static const struct soc_enum aif2adc_enum =
1342 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1343
1344static const struct snd_kcontrol_new aif2adc_mux =
1345 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1346
1347static const char *aif3adc_text[] = {
c4431df0 1348 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1349};
1350
c4431df0 1351static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1352 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1353
c4431df0
MB		 1354static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1355 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1356
1357static const struct soc_enum wm8958_aif3adc_enum =
1358 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1359
1360static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1361 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1362
1363static const char *mono_pcm_out_text[] = {
1364 "None", "AIF2ADCL", "AIF2ADCR",
1365};
1366
1367static const struct soc_enum mono_pcm_out_enum =
1368 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1369
1370static const struct snd_kcontrol_new mono_pcm_out_mux =
1371 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1372
1373static const char *aif2dac_src_text[] = {
1374 "AIF2", "AIF3",
1375};
1376
1377/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1378static const struct soc_enum aif2dacl_src_enum =
1379 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1380
1381static const struct snd_kcontrol_new aif2dacl_src_mux =
1382 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1383
1384static const struct soc_enum aif2dacr_src_enum =
1385 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1386
1387static const struct snd_kcontrol_new aif2dacr_src_mux =
1388 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1389
173efa09
DP		 1390static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1391SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1392 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1393SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1394 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1395
1396SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1397 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1398SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1399 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1400SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1401 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1402SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1403 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1404SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1405 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1406
1407SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1408 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1409 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1410SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1411 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1412 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1413SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1414 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1415SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1416 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1417
1418SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1419};
1420
1421static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1422SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1423SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1424SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1425SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1426 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1427SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1428 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1429SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1430SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1431};
1432
c52fd021
DP		 1433static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1434SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1435 dac_ev, SND_SOC_DAPM_PRE_PMU),
1436SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1437 dac_ev, SND_SOC_DAPM_PRE_PMU),
1438SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1439 dac_ev, SND_SOC_DAPM_PRE_PMU),
1440SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1441 dac_ev, SND_SOC_DAPM_PRE_PMU),
1442};
1443
1444static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1445SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1446SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1447SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1448SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1449};
1450
04d28681 1451static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1452SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1453 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1454SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1455 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1456};
1457
1458static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1459SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1460SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1461};
1462
9e6e96a1
MB		 1463static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1464SND_SOC_DAPM_INPUT("DMIC1DAT"),
1465SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1466SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1467
b462c6e6
DP		 1468SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1469 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1470SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1471 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1472
9e6e96a1
MB		 1473SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1475
1476SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1477SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1478SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1479
7f94de48 1480SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1481 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1482SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1483 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1484SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1485 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1486 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1487SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1488 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1489 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1490
7f94de48 1491SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1492 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1493SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1494 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1495SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1496 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1497 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1498SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1499 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1500 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1501
1502SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1503 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1504SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1505 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1506
a3257ba8
MB		 1507SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1508 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1509SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1510 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1511
9e6e96a1
MB		 1512SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1513 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1514SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1515 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1516
1517SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1518SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1519
1520SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1521 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1522SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1523 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1524
1525SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1526 WM8994_POWER_MANAGEMENT_4, 13, 0),
1527SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1528 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1529SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1530 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1531 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1532SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1533 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1534 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1535
5567d8c6
MB		 1536SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1537SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1538SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1539SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1540
1541SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1542SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1543SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1544
5567d8c6
MB		 1545SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1546SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1547
1548SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1549
1550SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1551SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1552SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1553SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1554
1555/* Power is done with the muxes since the ADC power also controls the
1556 * downsampling chain, the chip will automatically manage the analogue
1557 * specific portions.
1558 */
1559SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1560SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1561
9e6e96a1
MB		 1562SND_SOC_DAPM_POST("Debug log", post_ev),
1563};
1564
c4431df0
MB		 1565static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1566SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1567};
9e6e96a1 1568
c4431df0
MB		 1569static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1570SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1571SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1572SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1573SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1574};
1575
1576static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1577 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1578 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1579
1580 { "DSP1CLK", NULL, "CLK_SYS" },
1581 { "DSP2CLK", NULL, "CLK_SYS" },
1582 { "DSPINTCLK", NULL, "CLK_SYS" },
1583
1584 { "AIF1ADC1L", NULL, "AIF1CLK" },
1585 { "AIF1ADC1L", NULL, "DSP1CLK" },
1586 { "AIF1ADC1R", NULL, "AIF1CLK" },
1587 { "AIF1ADC1R", NULL, "DSP1CLK" },
1588 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1589
1590 { "AIF1DAC1L", NULL, "AIF1CLK" },
1591 { "AIF1DAC1L", NULL, "DSP1CLK" },
1592 { "AIF1DAC1R", NULL, "AIF1CLK" },
1593 { "AIF1DAC1R", NULL, "DSP1CLK" },
1594 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1595
1596 { "AIF1ADC2L", NULL, "AIF1CLK" },
1597 { "AIF1ADC2L", NULL, "DSP1CLK" },
1598 { "AIF1ADC2R", NULL, "AIF1CLK" },
1599 { "AIF1ADC2R", NULL, "DSP1CLK" },
1600 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1601
1602 { "AIF1DAC2L", NULL, "AIF1CLK" },
1603 { "AIF1DAC2L", NULL, "DSP1CLK" },
1604 { "AIF1DAC2R", NULL, "AIF1CLK" },
1605 { "AIF1DAC2R", NULL, "DSP1CLK" },
1606 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1607
1608 { "AIF2ADCL", NULL, "AIF2CLK" },
1609 { "AIF2ADCL", NULL, "DSP2CLK" },
1610 { "AIF2ADCR", NULL, "AIF2CLK" },
1611 { "AIF2ADCR", NULL, "DSP2CLK" },
1612 { "AIF2ADCR", NULL, "DSPINTCLK" },
1613
1614 { "AIF2DACL", NULL, "AIF2CLK" },
1615 { "AIF2DACL", NULL, "DSP2CLK" },
1616 { "AIF2DACR", NULL, "AIF2CLK" },
1617 { "AIF2DACR", NULL, "DSP2CLK" },
1618 { "AIF2DACR", NULL, "DSPINTCLK" },
1619
1620 { "DMIC1L", NULL, "DMIC1DAT" },
1621 { "DMIC1L", NULL, "CLK_SYS" },
1622 { "DMIC1R", NULL, "DMIC1DAT" },
1623 { "DMIC1R", NULL, "CLK_SYS" },
1624 { "DMIC2L", NULL, "DMIC2DAT" },
1625 { "DMIC2L", NULL, "CLK_SYS" },
1626 { "DMIC2R", NULL, "DMIC2DAT" },
1627 { "DMIC2R", NULL, "CLK_SYS" },
1628
1629 { "ADCL", NULL, "AIF1CLK" },
1630 { "ADCL", NULL, "DSP1CLK" },
1631 { "ADCL", NULL, "DSPINTCLK" },
1632
1633 { "ADCR", NULL, "AIF1CLK" },
1634 { "ADCR", NULL, "DSP1CLK" },
1635 { "ADCR", NULL, "DSPINTCLK" },
1636
1637 { "ADCL Mux", "ADC", "ADCL" },
1638 { "ADCL Mux", "DMIC", "DMIC1L" },
1639 { "ADCR Mux", "ADC", "ADCR" },
1640 { "ADCR Mux", "DMIC", "DMIC1R" },
1641
1642 { "DAC1L", NULL, "AIF1CLK" },
1643 { "DAC1L", NULL, "DSP1CLK" },
1644 { "DAC1L", NULL, "DSPINTCLK" },
1645
1646 { "DAC1R", NULL, "AIF1CLK" },
1647 { "DAC1R", NULL, "DSP1CLK" },
1648 { "DAC1R", NULL, "DSPINTCLK" },
1649
1650 { "DAC2L", NULL, "AIF2CLK" },
1651 { "DAC2L", NULL, "DSP2CLK" },
1652 { "DAC2L", NULL, "DSPINTCLK" },
1653
1654 { "DAC2R", NULL, "AIF2DACR" },
1655 { "DAC2R", NULL, "AIF2CLK" },
1656 { "DAC2R", NULL, "DSP2CLK" },
1657 { "DAC2R", NULL, "DSPINTCLK" },
1658
1659 { "TOCLK", NULL, "CLK_SYS" },
1660
5567d8c6
MB		 1661 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1662 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1663 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1664
1665 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1666 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1667 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1668
9e6e96a1
MB		 1669 /* AIF1 outputs */
1670 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1671 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1672 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1673
1674 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1675 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1676 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1677
a3257ba8
MB		 1678 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1679 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1680 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1681
1682 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1683 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1684 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1685
9e6e96a1
MB		 1686 /* Pin level routing for AIF3 */
1687 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1688 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1689 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1690 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1691
9e6e96a1
MB		 1692 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1693 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1694 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1695 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1696 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1697 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1698 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1699
1700 /* DAC1 inputs */
9e6e96a1
MB		 1701 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1702 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1703 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1704 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1705 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1706
9e6e96a1
MB		 1707 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1708 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1709 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1710 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1711 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1712
1713 /* DAC2/AIF2 outputs */
1714 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1715 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1716 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1717 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1718 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1719 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1720
1721 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1722 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1723 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1724 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1725 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1726 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1727
7f94de48
MB		 1728 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1729 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1730 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1731 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1732
9e6e96a1
MB		 1733 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1734
1735 /* AIF3 output */
1736 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1737 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1738 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1739 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1740 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1741 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1742 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1743 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1744
1745 /* Sidetone */
1746 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1747 { "Left Sidetone", "DMIC2", "DMIC2L" },
1748 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1749 { "Right Sidetone", "DMIC2", "DMIC2R" },
1750
1751 /* Output stages */
1752 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1753 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1754
1755 { "SPKL", "DAC1 Switch", "DAC1L" },
1756 { "SPKL", "DAC2 Switch", "DAC2L" },
1757
1758 { "SPKR", "DAC1 Switch", "DAC1R" },
1759 { "SPKR", "DAC2 Switch", "DAC2R" },
1760
1761 { "Left Headphone Mux", "DAC", "DAC1L" },
1762 { "Right Headphone Mux", "DAC", "DAC1R" },
1763};
1764
173efa09
DP		 1765static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1766 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1767 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1768 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1769 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1770 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1771 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1772 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1773 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1774};
1775
1776static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1777 { "DAC1L", NULL, "DAC1L Mixer" },
1778 { "DAC1R", NULL, "DAC1R Mixer" },
1779 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1780 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1781};
1782
6ed8f148
MB		 1783static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1784 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1785 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1786 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1787 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1788 { "MICBIAS1", NULL, "CLK_SYS" },
1789 { "MICBIAS1", NULL, "MICBIAS Supply" },
1790 { "MICBIAS2", NULL, "CLK_SYS" },
1791 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1792};
1793
c4431df0
MB		 1794static const struct snd_soc_dapm_route wm8994_intercon[] = {
1795 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1796 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1797 { "MICBIAS1", NULL, "VMID" },
1798 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1799};
1800
1801static const struct snd_soc_dapm_route wm8958_intercon[] = {
1802 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1803 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1804
1805 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1806 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1807 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1808 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1809
1810 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1811 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1812
1813 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1814};
1815
9e6e96a1
MB		 1816/* The size in bits of the FLL divide multiplied by 10
1817 * to allow rounding later */
1818#define FIXED_FLL_SIZE ((1 << 16) * 10)
1819
1820struct fll_div {
1821 u16 outdiv;
1822 u16 n;
1823 u16 k;
1824 u16 clk_ref_div;
1825 u16 fll_fratio;
1826};
1827
1828static int wm8994_get_fll_config(struct fll_div *fll,
1829 int freq_in, int freq_out)
1830{
1831 u64 Kpart;
1832 unsigned int K, Ndiv, Nmod;
1833
1834 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1835
1836 /* Scale the input frequency down to <= 13.5MHz */
1837 fll->clk_ref_div = 0;
1838 while (freq_in > 13500000) {
1839 fll->clk_ref_div++;
1840 freq_in /= 2;
1841
1842 if (fll->clk_ref_div > 3)
1843 return -EINVAL;
1844 }
1845 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1846
1847 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1848 fll->outdiv = 3;
1849 while (freq_out * (fll->outdiv + 1) < 90000000) {
1850 fll->outdiv++;
1851 if (fll->outdiv > 63)
1852 return -EINVAL;
1853 }
1854 freq_out *= fll->outdiv + 1;
1855 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1856
1857 if (freq_in > 1000000) {
1858 fll->fll_fratio = 0;
7d48a6ac
MB		 1859 } else if (freq_in > 256000) {
1860 fll->fll_fratio = 1;
1861 freq_in *= 2;
1862 } else if (freq_in > 128000) {
1863 fll->fll_fratio = 2;
1864 freq_in *= 4;
1865 } else if (freq_in > 64000) {
9e6e96a1
MB		 1866 fll->fll_fratio = 3;
1867 freq_in *= 8;
7d48a6ac
MB		 1868 } else {
1869 fll->fll_fratio = 4;
1870 freq_in *= 16;
9e6e96a1
MB		 1871 }
1872 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1873
1874 /* Now, calculate N.K */
1875 Ndiv = freq_out / freq_in;
1876
1877 fll->n = Ndiv;
1878 Nmod = freq_out % freq_in;
1879 pr_debug("Nmod=%d\n", Nmod);
1880
1881 /* Calculate fractional part - scale up so we can round. */
1882 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1883
1884 do_div(Kpart, freq_in);
1885
1886 K = Kpart & 0xFFFFFFFF;
1887
1888 if ((K % 10) >= 5)
1889 K += 5;
1890
1891 /* Move down to proper range now rounding is done */
1892 fll->k = K / 10;
1893
1894 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1895
1896 return 0;
1897}
1898
f0fba2ad 1899static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1900 unsigned int freq_in, unsigned int freq_out)
1901{
b2c812e2 1902 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1903 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1904 int reg_offset, ret;
1905 struct fll_div fll;
e413ba88 1906 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 1907 unsigned long timeout;
4b7ed83a 1908 bool was_enabled;
9e6e96a1 1909
9e6e96a1
MB		 1910 switch (id) {
1911 case WM8994_FLL1:
1912 reg_offset = 0;
1913 id = 0;
e413ba88 1914 aif_src = 0x10;
9e6e96a1
MB		 1915 break;
1916 case WM8994_FLL2:
1917 reg_offset = 0x20;
1918 id = 1;
e413ba88 1919 aif_src = 0x18;
9e6e96a1
MB		 1920 break;
1921 default:
1922 return -EINVAL;
1923 }
1924
4b7ed83a
MB		 1925 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1926 was_enabled = reg & WM8994_FLL1_ENA;
1927
136ff2a2 1928 switch (src) {
7add84aa
MB		 1929 case 0:
1930 /* Allow no source specification when stopping */
1931 if (freq_out)
1932 return -EINVAL;
4514e899 1933 src = wm8994->fll[id].src;
7add84aa 1934 break;
136ff2a2
MB		 1935 case WM8994_FLL_SRC_MCLK1:
1936 case WM8994_FLL_SRC_MCLK2:
1937 case WM8994_FLL_SRC_LRCLK:
1938 case WM8994_FLL_SRC_BCLK:
1939 break;
1940 default:
1941 return -EINVAL;
1942 }
1943
9e6e96a1
MB		 1944 /* Are we changing anything? */
1945 if (wm8994->fll[id].src == src &&
1946 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1947 return 0;
1948
1949 /* If we're stopping the FLL redo the old config - no
1950 * registers will actually be written but we avoid GCC flow
1951 * analysis bugs spewing warnings.
1952 */
1953 if (freq_out)
1954 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1955 else
1956 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1957 wm8994->fll[id].out);
1958 if (ret < 0)
1959 return ret;
1960
e413ba88
MB		 1961 /* Make sure that we're not providing SYSCLK right now */
1962 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
1963 if (clk1 & WM8994_SYSCLK_SRC)
1964 aif_reg = WM8994_AIF2_CLOCKING_1;
1965 else
1966 aif_reg = WM8994_AIF1_CLOCKING_1;
1967 reg = snd_soc_read(codec, aif_reg);
1968
1969 if ((reg & WM8994_AIF1CLK_ENA) &&
1970 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
1971 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
1972 id + 1);
1973 return -EBUSY;
1974 }
9e6e96a1
MB		 1975
1976 /* We always need to disable the FLL while reconfiguring */
1977 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1978 WM8994_FLL1_ENA, 0);
1979
1980 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1981 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1982 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1983 WM8994_FLL1_OUTDIV_MASK |
1984 WM8994_FLL1_FRATIO_MASK, reg);
1985
b16db745
MB		 1986 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1987 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 1988
1989 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1990 WM8994_FLL1_N_MASK,
1991 fll.n << WM8994_FLL1_N_SHIFT);
1992
1993 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1994 WM8994_FLL1_REFCLK_DIV_MASK |
1995 WM8994_FLL1_REFCLK_SRC_MASK,
1996 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1997 (src - 1));
9e6e96a1 1998
f0f5039c
MB		 1999 /* Clear any pending completion from a previous failure */
2000 try_wait_for_completion(&wm8994->fll_locked[id]);
2001
9e6e96a1
MB		 2002 /* Enable (with fractional mode if required) */
2003 if (freq_out) {
4b7ed83a
MB		 2004 /* Enable VMID if we need it */
2005 if (!was_enabled) {
af6b6fe4
MB		 2006 active_reference(codec);
2007
4b7ed83a
MB		 2008 switch (control->type) {
2009 case WM8994:
2010 vmid_reference(codec);
2011 break;
2012 case WM8958:
2013 if (wm8994->revision < 1)
2014 vmid_reference(codec);
2015 break;
2016 default:
2017 break;
2018 }
2019 }
2020
9e6e96a1
MB		 2021 if (fll.k)
2022 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2023 else
2024 reg = WM8994_FLL1_ENA;
2025 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2026 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2027 reg);
8e9ddf81 2028
c7ebf932
MB		 2029 if (wm8994->fll_locked_irq) {
2030 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2031 msecs_to_jiffies(10));
2032 if (timeout == 0)
2033 dev_warn(codec->dev,
2034 "Timed out waiting for FLL lock\n");
2035 } else {
2036 msleep(5);
2037 }
4b7ed83a
MB		 2038 } else {
2039 if (was_enabled) {
2040 switch (control->type) {
2041 case WM8994:
2042 vmid_dereference(codec);
2043 break;
2044 case WM8958:
2045 if (wm8994->revision < 1)
2046 vmid_dereference(codec);
2047 break;
2048 default:
2049 break;
2050 }
af6b6fe4
MB		 2051
2052 active_dereference(codec);
4b7ed83a 2053 }
9e6e96a1
MB		 2054 }
2055
2056 wm8994->fll[id].in = freq_in;
2057 wm8994->fll[id].out = freq_out;
136ff2a2 2058 wm8994->fll[id].src = src;
9e6e96a1 2059
9e6e96a1
MB		 2060 configure_clock(codec);
2061
2062 return 0;
2063}
2064
c7ebf932
MB		 2065static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2066{
2067 struct completion *completion = data;
2068
2069 complete(completion);
2070
2071 return IRQ_HANDLED;
2072}
f0fba2ad 2073
66b47fdb
MB		 2074static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2075
f0fba2ad
LG		 2076static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2077 unsigned int freq_in, unsigned int freq_out)
2078{
2079 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2080}
2081
9e6e96a1
MB		 2082static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2083 int clk_id, unsigned int freq, int dir)
2084{
2085 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2086 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2087 int i;
9e6e96a1
MB		 2088
2089 switch (dai->id) {
2090 case 1:
2091 case 2:
2092 break;
2093
2094 default:
2095 /* AIF3 shares clocking with AIF1/2 */
2096 return -EINVAL;
2097 }
2098
2099 switch (clk_id) {
2100 case WM8994_SYSCLK_MCLK1:
2101 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2102 wm8994->mclk[0] = freq;
2103 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2104 dai->id, freq);
2105 break;
2106
2107 case WM8994_SYSCLK_MCLK2:
2108 /* TODO: Set GPIO AF */
2109 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2110 wm8994->mclk[1] = freq;
2111 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2112 dai->id, freq);
2113 break;
2114
2115 case WM8994_SYSCLK_FLL1:
2116 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2117 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2118 break;
2119
2120 case WM8994_SYSCLK_FLL2:
2121 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2122 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2123 break;
2124
66b47fdb
MB		 2125 case WM8994_SYSCLK_OPCLK:
2126 /* Special case - a division (times 10) is given and
2127 * no effect on main clocking.
2128 */
2129 if (freq) {
2130 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2131 if (opclk_divs[i] == freq)
2132 break;
2133 if (i == ARRAY_SIZE(opclk_divs))
2134 return -EINVAL;
2135 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2136 WM8994_OPCLK_DIV_MASK, i);
2137 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2138 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2139 } else {
2140 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2141 WM8994_OPCLK_ENA, 0);
2142 }
2143
9e6e96a1
MB		 2144 default:
2145 return -EINVAL;
2146 }
2147
2148 configure_clock(codec);
2149
2150 return 0;
2151}
2152
2153static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2154 enum snd_soc_bias_level level)
2155{
b6b05691 2156 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2157 struct wm8994 *control = wm8994->wm8994;
b6b05691 2158
5f2f3890
MB		 2159 wm_hubs_set_bias_level(codec, level);
2160
9e6e96a1
MB		 2161 switch (level) {
2162 case SND_SOC_BIAS_ON:
2163 break;
2164
2165 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2166 /* MICBIAS into regulating mode */
2167 switch (control->type) {
2168 case WM8958:
2169 case WM1811:
2170 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2171 WM8958_MICB1_MODE, 0);
2172 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2173 WM8958_MICB2_MODE, 0);
2174 break;
2175 default:
2176 break;
2177 }
af6b6fe4
MB		 2178
2179 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2180 active_reference(codec);
9e6e96a1
MB		 2181 break;
2182
2183 case SND_SOC_BIAS_STANDBY:
ce6120cc 2184 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2185 switch (control->type) {
8bc3c2c2
MB		 2186 case WM8958:
2187 if (wm8994->revision == 0) {
2188 /* Optimise performance for rev A */
8bc3c2c2
MB		 2189 snd_soc_update_bits(codec,
2190 WM8958_CHARGE_PUMP_2,
2191 WM8958_CP_DISCH,
2192 WM8958_CP_DISCH);
2193 }
2194 break;
81204c84 2195
462835e4 2196 default:
81204c84 2197 break;
b6b05691 2198 }
9e6e96a1
MB		 2199
2200 /* Discharge LINEOUT1 & 2 */
2201 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2202 WM8994_LINEOUT1_DISCH |
2203 WM8994_LINEOUT2_DISCH,
2204 WM8994_LINEOUT1_DISCH |
2205 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2206 }
2207
af6b6fe4
MB		 2208 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2209 active_dereference(codec);
2210
500fa30e
MB		 2211 /* MICBIAS into bypass mode on newer devices */
2212 switch (control->type) {
2213 case WM8958:
2214 case WM1811:
2215 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2216 WM8958_MICB1_MODE,
2217 WM8958_MICB1_MODE);
2218 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2219 WM8958_MICB2_MODE,
2220 WM8958_MICB2_MODE);
2221 break;
2222 default:
2223 break;
2224 }
9e6e96a1
MB		 2225 break;
2226
2227 case SND_SOC_BIAS_OFF:
4105ab84 2228 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2229 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2230 break;
2231 }
5f2f3890 2232
ce6120cc 2233 codec->dapm.bias_level = level;
af6b6fe4 2234
22f8d055
MB		 2235 return 0;
2236}
2237
2238int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2239{
2240 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2241
2242 switch (mode) {
2243 case WM8994_VMID_NORMAL:
2244 if (wm8994->hubs.lineout1_se) {
2245 snd_soc_dapm_disable_pin(&codec->dapm,
2246 "LINEOUT1N Driver");
2247 snd_soc_dapm_disable_pin(&codec->dapm,
2248 "LINEOUT1P Driver");
2249 }
2250 if (wm8994->hubs.lineout2_se) {
2251 snd_soc_dapm_disable_pin(&codec->dapm,
2252 "LINEOUT2N Driver");
2253 snd_soc_dapm_disable_pin(&codec->dapm,
2254 "LINEOUT2P Driver");
2255 }
2256
2257 /* Do the sync with the old mode to allow it to clean up */
2258 snd_soc_dapm_sync(&codec->dapm);
2259 wm8994->vmid_mode = mode;
2260 break;
2261
2262 case WM8994_VMID_FORCE:
2263 if (wm8994->hubs.lineout1_se) {
2264 snd_soc_dapm_force_enable_pin(&codec->dapm,
2265 "LINEOUT1N Driver");
2266 snd_soc_dapm_force_enable_pin(&codec->dapm,
2267 "LINEOUT1P Driver");
2268 }
2269 if (wm8994->hubs.lineout2_se) {
2270 snd_soc_dapm_force_enable_pin(&codec->dapm,
2271 "LINEOUT2N Driver");
2272 snd_soc_dapm_force_enable_pin(&codec->dapm,
2273 "LINEOUT2P Driver");
2274 }
2275
2276 wm8994->vmid_mode = mode;
2277 snd_soc_dapm_sync(&codec->dapm);
2278 break;
2279
2280 default:
2281 return -EINVAL;
2282 }
2283
9e6e96a1
MB		 2284 return 0;
2285}
2286
2287static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2288{
2289 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2291 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2292 int ms_reg;
2293 int aif1_reg;
2294 int ms = 0;
2295 int aif1 = 0;
2296
2297 switch (dai->id) {
2298 case 1:
2299 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2300 aif1_reg = WM8994_AIF1_CONTROL_1;
2301 break;
2302 case 2:
2303 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2304 aif1_reg = WM8994_AIF2_CONTROL_1;
2305 break;
2306 default:
2307 return -EINVAL;
2308 }
2309
2310 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2311 case SND_SOC_DAIFMT_CBS_CFS:
2312 break;
2313 case SND_SOC_DAIFMT_CBM_CFM:
2314 ms = WM8994_AIF1_MSTR;
2315 break;
2316 default:
2317 return -EINVAL;
2318 }
2319
2320 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2321 case SND_SOC_DAIFMT_DSP_B:
2322 aif1 |= WM8994_AIF1_LRCLK_INV;
2323 case SND_SOC_DAIFMT_DSP_A:
2324 aif1 |= 0x18;
2325 break;
2326 case SND_SOC_DAIFMT_I2S:
2327 aif1 |= 0x10;
2328 break;
2329 case SND_SOC_DAIFMT_RIGHT_J:
2330 break;
2331 case SND_SOC_DAIFMT_LEFT_J:
2332 aif1 |= 0x8;
2333 break;
2334 default:
2335 return -EINVAL;
2336 }
2337
2338 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2339 case SND_SOC_DAIFMT_DSP_A:
2340 case SND_SOC_DAIFMT_DSP_B:
2341 /* frame inversion not valid for DSP modes */
2342 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2343 case SND_SOC_DAIFMT_NB_NF:
2344 break;
2345 case SND_SOC_DAIFMT_IB_NF:
2346 aif1 |= WM8994_AIF1_BCLK_INV;
2347 break;
2348 default:
2349 return -EINVAL;
2350 }
2351 break;
2352
2353 case SND_SOC_DAIFMT_I2S:
2354 case SND_SOC_DAIFMT_RIGHT_J:
2355 case SND_SOC_DAIFMT_LEFT_J:
2356 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2357 case SND_SOC_DAIFMT_NB_NF:
2358 break;
2359 case SND_SOC_DAIFMT_IB_IF:
2360 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2361 break;
2362 case SND_SOC_DAIFMT_IB_NF:
2363 aif1 |= WM8994_AIF1_BCLK_INV;
2364 break;
2365 case SND_SOC_DAIFMT_NB_IF:
2366 aif1 |= WM8994_AIF1_LRCLK_INV;
2367 break;
2368 default:
2369 return -EINVAL;
2370 }
2371 break;
2372 default:
2373 return -EINVAL;
2374 }
2375
c4431df0
MB		 2376 /* The AIF2 format configuration needs to be mirrored to AIF3
2377 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2378 switch (control->type) {
2379 case WM1811:
2380 case WM8958:
2381 if (dai->id == 2)
2382 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2383 WM8994_AIF1_LRCLK_INV |
2384 WM8958_AIF3_FMT_MASK, aif1);
2385 break;
2386
2387 default:
2388 break;
2389 }
c4431df0 2390
9e6e96a1
MB		 2391 snd_soc_update_bits(codec, aif1_reg,
2392 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2393 WM8994_AIF1_FMT_MASK,
2394 aif1);
2395 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2396 ms);
2397
2398 return 0;
2399}
2400
2401static struct {
2402 int val, rate;
2403} srs[] = {
2404 { 0, 8000 },
2405 { 1, 11025 },
2406 { 2, 12000 },
2407 { 3, 16000 },
2408 { 4, 22050 },
2409 { 5, 24000 },
2410 { 6, 32000 },
2411 { 7, 44100 },
2412 { 8, 48000 },
2413 { 9, 88200 },
2414 { 10, 96000 },
2415};
2416
2417static int fs_ratios[] = {
2418 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2419};
2420
2421static int bclk_divs[] = {
2422 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2423 640, 880, 960, 1280, 1760, 1920
2424};
2425
2426static int wm8994_hw_params(struct snd_pcm_substream *substream,
2427 struct snd_pcm_hw_params *params,
2428 struct snd_soc_dai *dai)
2429{
2430 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2431 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2432 int aif1_reg;
b1e43d93 2433 int aif2_reg;
9e6e96a1
MB		 2434 int bclk_reg;
2435 int lrclk_reg;
2436 int rate_reg;
2437 int aif1 = 0;
b1e43d93 2438 int aif2 = 0;
9e6e96a1
MB		 2439 int bclk = 0;
2440 int lrclk = 0;
2441 int rate_val = 0;
2442 int id = dai->id - 1;
2443
2444 int i, cur_val, best_val, bclk_rate, best;
2445
2446 switch (dai->id) {
2447 case 1:
2448 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2449 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2450 bclk_reg = WM8994_AIF1_BCLK;
2451 rate_reg = WM8994_AIF1_RATE;
2452 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2453 wm8994->lrclk_shared[0]) {
9e6e96a1 2454 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2455 } else {
9e6e96a1 2456 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2457 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2458 }
9e6e96a1
MB		 2459 break;
2460 case 2:
2461 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2462 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2463 bclk_reg = WM8994_AIF2_BCLK;
2464 rate_reg = WM8994_AIF2_RATE;
2465 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2466 wm8994->lrclk_shared[1]) {
9e6e96a1 2467 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2468 } else {
9e6e96a1 2469 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2470 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2471 }
9e6e96a1
MB		 2472 break;
2473 default:
2474 return -EINVAL;
2475 }
2476
2477 bclk_rate = params_rate(params) * 2;
2478 switch (params_format(params)) {
2479 case SNDRV_PCM_FORMAT_S16_LE:
2480 bclk_rate *= 16;
2481 break;
2482 case SNDRV_PCM_FORMAT_S20_3LE:
2483 bclk_rate *= 20;
2484 aif1 |= 0x20;
2485 break;
2486 case SNDRV_PCM_FORMAT_S24_LE:
2487 bclk_rate *= 24;
2488 aif1 |= 0x40;
2489 break;
2490 case SNDRV_PCM_FORMAT_S32_LE:
2491 bclk_rate *= 32;
2492 aif1 |= 0x60;
2493 break;
2494 default:
2495 return -EINVAL;
2496 }
2497
2498 /* Try to find an appropriate sample rate; look for an exact match. */
2499 for (i = 0; i < ARRAY_SIZE(srs); i++)
2500 if (srs[i].rate == params_rate(params))
2501 break;
2502 if (i == ARRAY_SIZE(srs))
2503 return -EINVAL;
2504 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2505
2506 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2507 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2508 dai->id, wm8994->aifclk[id], bclk_rate);
2509
b1e43d93
MB		 2510 if (params_channels(params) == 1 &&
2511 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2512 aif2 |= WM8994_AIF1_MONO;
2513
9e6e96a1
MB		 2514 if (wm8994->aifclk[id] == 0) {
2515 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2516 return -EINVAL;
2517 }
2518
2519 /* AIFCLK/fs ratio; look for a close match in either direction */
2520 best = 0;
2521 best_val = abs((fs_ratios[0] * params_rate(params))
2522 - wm8994->aifclk[id]);
2523 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2524 cur_val = abs((fs_ratios[i] * params_rate(params))
2525 - wm8994->aifclk[id]);
2526 if (cur_val >= best_val)
2527 continue;
2528 best = i;
2529 best_val = cur_val;
2530 }
2531 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2532 dai->id, fs_ratios[best]);
2533 rate_val |= best;
2534
2535 /* We may not get quite the right frequency if using
2536 * approximate clocks so look for the closest match that is
2537 * higher than the target (we need to ensure that there enough
2538 * BCLKs to clock out the samples).
2539 */
2540 best = 0;
2541 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2542 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2543 if (cur_val < 0) /* BCLK table is sorted */
2544 break;
2545 best = i;
2546 }
07cd8ada 2547 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2548 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2549 bclk_divs[best], bclk_rate);
2550 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2551
2552 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2553 if (!lrclk) {
2554 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2555 bclk_rate);
2556 return -EINVAL;
2557 }
9e6e96a1
MB		 2558 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2559 lrclk, bclk_rate / lrclk);
2560
2561 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2562 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2563 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2564 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2565 lrclk);
2566 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2567 WM8994_AIF1CLK_RATE_MASK, rate_val);
2568
2569 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2570 switch (dai->id) {
2571 case 1:
2572 wm8994->dac_rates[0] = params_rate(params);
2573 wm8994_set_retune_mobile(codec, 0);
2574 wm8994_set_retune_mobile(codec, 1);
2575 break;
2576 case 2:
2577 wm8994->dac_rates[1] = params_rate(params);
2578 wm8994_set_retune_mobile(codec, 2);
2579 break;
2580 }
2581 }
2582
2583 return 0;
2584}
2585
c4431df0
MB		 2586static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2587 struct snd_pcm_hw_params *params,
2588 struct snd_soc_dai *dai)
2589{
2590 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2591 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2592 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2593 int aif1_reg;
2594 int aif1 = 0;
2595
2596 switch (dai->id) {
2597 case 3:
2598 switch (control->type) {
81204c84 2599 case WM1811:
c4431df0
MB		 2600 case WM8958:
2601 aif1_reg = WM8958_AIF3_CONTROL_1;
2602 break;
2603 default:
2604 return 0;
2605 }
2606 default:
2607 return 0;
2608 }
2609
2610 switch (params_format(params)) {
2611 case SNDRV_PCM_FORMAT_S16_LE:
2612 break;
2613 case SNDRV_PCM_FORMAT_S20_3LE:
2614 aif1 |= 0x20;
2615 break;
2616 case SNDRV_PCM_FORMAT_S24_LE:
2617 aif1 |= 0x40;
2618 break;
2619 case SNDRV_PCM_FORMAT_S32_LE:
2620 aif1 |= 0x60;
2621 break;
2622 default:
2623 return -EINVAL;
2624 }
2625
2626 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2627}
2628
9e6e96a1
MB		 2629static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2630{
2631 struct snd_soc_codec *codec = codec_dai->codec;
2632 int mute_reg;
2633 int reg;
2634
2635 switch (codec_dai->id) {
2636 case 1:
2637 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2638 break;
2639 case 2:
2640 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2641 break;
2642 default:
2643 return -EINVAL;
2644 }
2645
2646 if (mute)
2647 reg = WM8994_AIF1DAC1_MUTE;
2648 else
2649 reg = 0;
2650
2651 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2652
2653 return 0;
2654}
2655
778a76e2
MB		 2656static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2657{
2658 struct snd_soc_codec *codec = codec_dai->codec;
2659 int reg, val, mask;
2660
2661 switch (codec_dai->id) {
2662 case 1:
2663 reg = WM8994_AIF1_MASTER_SLAVE;
2664 mask = WM8994_AIF1_TRI;
2665 break;
2666 case 2:
2667 reg = WM8994_AIF2_MASTER_SLAVE;
2668 mask = WM8994_AIF2_TRI;
2669 break;
2670 case 3:
2671 reg = WM8994_POWER_MANAGEMENT_6;
2672 mask = WM8994_AIF3_TRI;
2673 break;
2674 default:
2675 return -EINVAL;
2676 }
2677
2678 if (tristate)
2679 val = mask;
2680 else
2681 val = 0;
2682
78b3fb46 2683 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2684}
2685
d09f3ecf
MB		 2686static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2687{
2688 struct snd_soc_codec *codec = dai->codec;
2689
2690 /* Disable the pulls on the AIF if we're using it to save power. */
2691 snd_soc_update_bits(codec, WM8994_GPIO_3,
2692 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2693 snd_soc_update_bits(codec, WM8994_GPIO_4,
2694 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2695 snd_soc_update_bits(codec, WM8994_GPIO_5,
2696 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2697
2698 return 0;
2699}
2700
9e6e96a1
MB		 2701#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2702
2703#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2704 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2705
85e7652d 2706static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2707 .set_sysclk = wm8994_set_dai_sysclk,
2708 .set_fmt = wm8994_set_dai_fmt,
2709 .hw_params = wm8994_hw_params,
2710 .digital_mute = wm8994_aif_mute,
2711 .set_pll = wm8994_set_fll,
778a76e2 2712 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2713};
2714
85e7652d 2715static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2716 .set_sysclk = wm8994_set_dai_sysclk,
2717 .set_fmt = wm8994_set_dai_fmt,
2718 .hw_params = wm8994_hw_params,
2719 .digital_mute = wm8994_aif_mute,
2720 .set_pll = wm8994_set_fll,
778a76e2
MB		 2721 .set_tristate = wm8994_set_tristate,
2722};
2723
85e7652d 2724static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2725 .hw_params = wm8994_aif3_hw_params,
778a76e2 2726 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2727};
2728
f0fba2ad 2729static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2730 {
f0fba2ad 2731 .name = "wm8994-aif1",
8c7f78b3 2732 .id = 1,
9e6e96a1
MB		 2733 .playback = {
2734 .stream_name = "AIF1 Playback",
b1e43d93 2735 .channels_min = 1,
9e6e96a1
MB		 2736 .channels_max = 2,
2737 .rates = WM8994_RATES,
2738 .formats = WM8994_FORMATS,
99b0292d 2739 .sig_bits = 24,
9e6e96a1
MB		 2740 },
2741 .capture = {
2742 .stream_name = "AIF1 Capture",
b1e43d93 2743 .channels_min = 1,
9e6e96a1
MB		 2744 .channels_max = 2,
2745 .rates = WM8994_RATES,
2746 .formats = WM8994_FORMATS,
99b0292d 2747 .sig_bits = 24,
9e6e96a1
MB		 2748 },
2749 .ops = &wm8994_aif1_dai_ops,
2750 },
2751 {
f0fba2ad 2752 .name = "wm8994-aif2",
8c7f78b3 2753 .id = 2,
9e6e96a1
MB		 2754 .playback = {
2755 .stream_name = "AIF2 Playback",
b1e43d93 2756 .channels_min = 1,
9e6e96a1
MB		 2757 .channels_max = 2,
2758 .rates = WM8994_RATES,
2759 .formats = WM8994_FORMATS,
99b0292d 2760 .sig_bits = 24,
9e6e96a1
MB		 2761 },
2762 .capture = {
2763 .stream_name = "AIF2 Capture",
b1e43d93 2764 .channels_min = 1,
9e6e96a1
MB		 2765 .channels_max = 2,
2766 .rates = WM8994_RATES,
2767 .formats = WM8994_FORMATS,
99b0292d 2768 .sig_bits = 24,
9e6e96a1 2769 },
d09f3ecf 2770 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2771 .ops = &wm8994_aif2_dai_ops,
2772 },
2773 {
f0fba2ad 2774 .name = "wm8994-aif3",
8c7f78b3 2775 .id = 3,
9e6e96a1
MB		 2776 .playback = {
2777 .stream_name = "AIF3 Playback",
b1e43d93 2778 .channels_min = 1,
9e6e96a1
MB		 2779 .channels_max = 2,
2780 .rates = WM8994_RATES,
2781 .formats = WM8994_FORMATS,
99b0292d 2782 .sig_bits = 24,
9e6e96a1 2783 },
a8462bde 2784 .capture = {
9e6e96a1 2785 .stream_name = "AIF3 Capture",
b1e43d93 2786 .channels_min = 1,
9e6e96a1
MB		 2787 .channels_max = 2,
2788 .rates = WM8994_RATES,
2789 .formats = WM8994_FORMATS,
99b0292d
MB		 2790 .sig_bits = 24,
2791 },
778a76e2 2792 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2793 }
2794};
9e6e96a1
MB		 2795
2796#ifdef CONFIG_PM
4752a887 2797static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 2798{
b2c812e2 2799 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2800 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2801 int i, ret;
2802
ca629928
MB		 2803 switch (control->type) {
2804 case WM8994:
2805 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2806 break;
81204c84 2807 case WM1811:
af6b6fe4
MB		 2808 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2809 WM1811_JACKDET_MODE_MASK, 0);
2810 /* Fall through */
ca629928
MB		 2811 case WM8958:
2812 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2813 WM8958_MICD_ENA, 0);
2814 break;
2815 }
2816
9e6e96a1
MB		 2817 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2818 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2819 sizeof(struct wm8994_fll_config));
f0fba2ad 2820 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2821 if (ret < 0)
2822 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2823 i + 1, ret);
2824 }
2825
2826 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2827
2828 return 0;
2829}
2830
4752a887 2831static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 2832{
b2c812e2 2833 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2834 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2835 int i, ret;
c52fd021
DP		 2836 unsigned int val, mask;
2837
2838 if (wm8994->revision < 4) {
2839 /* force a HW read */
d9a7666f
MB		 2840 ret = regmap_read(control->regmap,
2841 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2842
2843 /* modify the cache only */
2844 codec->cache_only = 1;
2845 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2846 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2847 val &= mask;
2848 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2849 mask, val);
2850 codec->cache_only = 0;
2851 }
9e6e96a1 2852
9e6e96a1 2853 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2854 if (!wm8994->fll_suspend[i].out)
2855 continue;
2856
f0fba2ad 2857 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2858 wm8994->fll_suspend[i].src,
2859 wm8994->fll_suspend[i].in,
2860 wm8994->fll_suspend[i].out);
2861 if (ret < 0)
2862 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2863 i + 1, ret);
2864 }
2865
ca629928
MB		 2866 switch (control->type) {
2867 case WM8994:
2868 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2869 snd_soc_update_bits(codec, WM8994_MICBIAS,
2870 WM8994_MICD_ENA, WM8994_MICD_ENA);
2871 break;
81204c84 2872 case WM1811:
af6b6fe4
MB		 2873 if (wm8994->jackdet && wm8994->jack_cb) {
2874 /* Restart from idle */
2875 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2876 WM1811_JACKDET_MODE_MASK,
2877 WM1811_JACKDET_MODE_JACK);
2878 break;
2879 }
6f8270cc 2880 break;
ca629928
MB		 2881 case WM8958:
2882 if (wm8994->jack_cb)
2883 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2884 WM8958_MICD_ENA, WM8958_MICD_ENA);
2885 break;
2886 }
2887
9e6e96a1
MB		 2888 return 0;
2889}
2890#else
4752a887
MB		 2891#define wm8994_codec_suspend NULL
2892#define wm8994_codec_resume NULL
9e6e96a1
MB		 2893#endif
2894
2895static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2896{
f0fba2ad 2897 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2898 struct wm8994_pdata *pdata = wm8994->pdata;
2899 struct snd_kcontrol_new controls[] = {
2900 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2901 wm8994->retune_mobile_enum,
2902 wm8994_get_retune_mobile_enum,
2903 wm8994_put_retune_mobile_enum),
2904 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2905 wm8994->retune_mobile_enum,
2906 wm8994_get_retune_mobile_enum,
2907 wm8994_put_retune_mobile_enum),
2908 SOC_ENUM_EXT("AIF2 EQ Mode",
2909 wm8994->retune_mobile_enum,
2910 wm8994_get_retune_mobile_enum,
2911 wm8994_put_retune_mobile_enum),
2912 };
2913 int ret, i, j;
2914 const char **t;
2915
2916 /* We need an array of texts for the enum API but the number
2917 * of texts is likely to be less than the number of
2918 * configurations due to the sample rate dependency of the
2919 * configurations. */
2920 wm8994->num_retune_mobile_texts = 0;
2921 wm8994->retune_mobile_texts = NULL;
2922 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2923 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2924 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2925 wm8994->retune_mobile_texts[j]) == 0)
2926 break;
2927 }
2928
2929 if (j != wm8994->num_retune_mobile_texts)
2930 continue;
2931
2932 /* Expand the array... */
2933 t = krealloc(wm8994->retune_mobile_texts,
2934 sizeof(char *) *
2935 (wm8994->num_retune_mobile_texts + 1),
2936 GFP_KERNEL);
2937 if (t == NULL)
2938 continue;
2939
2940 /* ...store the new entry... */
2941 t[wm8994->num_retune_mobile_texts] =
2942 pdata->retune_mobile_cfgs[i].name;
2943
2944 /* ...and remember the new version. */
2945 wm8994->num_retune_mobile_texts++;
2946 wm8994->retune_mobile_texts = t;
2947 }
2948
2949 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2950 wm8994->num_retune_mobile_texts);
2951
2952 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2953 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2954
022658be 2955 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2956 ARRAY_SIZE(controls));
2957 if (ret != 0)
f0fba2ad 2958 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2959 "Failed to add ReTune Mobile controls: %d\n", ret);
2960}
2961
2962static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2963{
f0fba2ad 2964 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2965 struct wm8994_pdata *pdata = wm8994->pdata;
2966 int ret, i;
2967
2968 if (!pdata)
2969 return;
2970
2971 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2972 pdata->lineout2_diff,
2973 pdata->lineout1fb,
2974 pdata->lineout2fb,
2975 pdata->jd_scthr,
2976 pdata->jd_thr,
2977 pdata->micbias1_lvl,
2978 pdata->micbias2_lvl);
2979
2980 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2981
2982 if (pdata->num_drc_cfgs) {
2983 struct snd_kcontrol_new controls[] = {
2984 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2985 wm8994_get_drc_enum, wm8994_put_drc_enum),
2986 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2987 wm8994_get_drc_enum, wm8994_put_drc_enum),
2988 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2989 wm8994_get_drc_enum, wm8994_put_drc_enum),
2990 };
2991
2992 /* We need an array of texts for the enum API */
7270cebe
MB		 2993 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2994 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2995 if (!wm8994->drc_texts) {
f0fba2ad 2996 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2997 "Failed to allocate %d DRC config texts\n",
2998 pdata->num_drc_cfgs);
2999 return;
3000 }
3001
3002 for (i = 0; i < pdata->num_drc_cfgs; i++)
3003 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3004
3005 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3006 wm8994->drc_enum.texts = wm8994->drc_texts;
3007
022658be 3008 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 3009 ARRAY_SIZE(controls));
3010 if (ret != 0)
f0fba2ad 3011 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3012 "Failed to add DRC mode controls: %d\n", ret);
3013
3014 for (i = 0; i < WM8994_NUM_DRC; i++)
3015 wm8994_set_drc(codec, i);
3016 }
3017
3018 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3019 pdata->num_retune_mobile_cfgs);
3020
3021 if (pdata->num_retune_mobile_cfgs)
3022 wm8994_handle_retune_mobile_pdata(wm8994);
3023 else
022658be 3024 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 3025 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3026
3027 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3028 if (pdata->micbias[i]) {
3029 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3030 pdata->micbias[i] & 0xffff);
3031 }
3032 }
9e6e96a1
MB		 3033}
3034
88766984
MB		 3035/**
3036 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3037 *
3038 * @codec: WM8994 codec
3039 * @jack: jack to report detection events on
3040 * @micbias: microphone bias to detect on
88766984
MB		 3041 *
3042 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3043 * being used to bring out signals to the processor then only platform
5ab230a7 3044 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3045 * be configured using snd_soc_jack_add_gpios() instead.
3046 *
3047 * Configuration of detection levels is available via the micbias1_lvl
3048 * and micbias2_lvl platform data members.
3049 */
3050int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3051 int micbias)
88766984 3052{
b2c812e2 3053 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3054 struct wm8994_micdet *micdet;
2a8a856d 3055 struct wm8994 *control = wm8994->wm8994;
87092e3c 3056 int reg, ret;
88766984 3057
87092e3c
MB		 3058 if (control->type != WM8994) {
3059 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3060 return -EINVAL;
87092e3c 3061 }
3a423157 3062
88766984
MB		 3063 switch (micbias) {
3064 case 1:
3065 micdet = &wm8994->micdet[0];
87092e3c
MB		 3066 if (jack)
3067 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3068 "MICBIAS1");
3069 else
3070 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3071 "MICBIAS1");
88766984
MB		 3072 break;
3073 case 2:
3074 micdet = &wm8994->micdet[1];
87092e3c
MB		 3075 if (jack)
3076 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3077 "MICBIAS1");
3078 else
3079 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3080 "MICBIAS1");
88766984
MB		 3081 break;
3082 default:
87092e3c 3083 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3084 return -EINVAL;
87092e3c 3085 }
88766984 3086
87092e3c
MB		 3087 if (ret != 0)
3088 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3089 micbias, ret);
3090
3091 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3092 micbias, jack);
88766984
MB		 3093
3094 /* Store the configuration */
3095 micdet->jack = jack;
87092e3c 3096 micdet->detecting = true;
88766984
MB		 3097
3098 /* If either of the jacks is set up then enable detection */
3099 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3100 reg = WM8994_MICD_ENA;
87092e3c 3101 else
88766984
MB		 3102 reg = 0;
3103
3104 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3105
87092e3c
MB		 3106 snd_soc_dapm_sync(&codec->dapm);
3107
88766984
MB		 3108 return 0;
3109}
3110EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3111
3112static irqreturn_t wm8994_mic_irq(int irq, void *data)
3113{
3114 struct wm8994_priv *priv = data;
f0fba2ad 3115 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3116 int reg;
3117 int report;
3118
7116f452 3119#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3120 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3121#endif
2bbb5d66 3122
88766984
MB		 3123 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3124 if (reg < 0) {
3125 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3126 reg);
3127 return IRQ_HANDLED;
3128 }
3129
3130 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3131
3132 report = 0;
87092e3c
MB		 3133 if (reg & WM8994_MIC1_DET_STS) {
3134 if (priv->micdet[0].detecting)
3135 report = SND_JACK_HEADSET;
3136 }
3137 if (reg & WM8994_MIC1_SHRT_STS) {
3138 if (priv->micdet[0].detecting)
3139 report = SND_JACK_HEADPHONE;
3140 else
3141 report |= SND_JACK_BTN_0;
3142 }
3143 if (report)
3144 priv->micdet[0].detecting = false;
3145 else
3146 priv->micdet[0].detecting = true;
3147
88766984 3148 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3149 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3150
3151 report = 0;
87092e3c
MB		 3152 if (reg & WM8994_MIC2_DET_STS) {
3153 if (priv->micdet[1].detecting)
3154 report = SND_JACK_HEADSET;
3155 }
3156 if (reg & WM8994_MIC2_SHRT_STS) {
3157 if (priv->micdet[1].detecting)
3158 report = SND_JACK_HEADPHONE;
3159 else
3160 report |= SND_JACK_BTN_0;
3161 }
3162 if (report)
3163 priv->micdet[1].detecting = false;
3164 else
3165 priv->micdet[1].detecting = true;
3166
88766984 3167 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3168 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3169
3170 return IRQ_HANDLED;
3171}
3172
821edd2f
MB		 3173/* Default microphone detection handler for WM8958 - the user can
3174 * override this if they wish.
3175 */
3176static void wm8958_default_micdet(u16 status, void *data)
3177{
3178 struct snd_soc_codec *codec = data;
3179 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3180 int report;
821edd2f 3181
a1691343
MB		 3182 dev_dbg(codec->dev, "MICDET %x\n", status);
3183
af6b6fe4 3184 /* Either nothing present or just starting detection */
b00adf76 3185 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3186 if (!wm8994->jackdet) {
3187 /* If nothing present then clear our statuses */
3188 dev_dbg(codec->dev, "Detected open circuit\n");
3189 wm8994->jack_mic = false;
3190 wm8994->mic_detecting = true;
b00adf76 3191
af6b6fe4 3192 wm8958_micd_set_rate(codec);
b00adf76 3193
af6b6fe4
MB		 3194 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3195 wm8994->btn_mask |
3196 SND_JACK_HEADSET);
3197 }
b00adf76
MB		 3198 return;
3199 }
821edd2f 3200
b00adf76
MB		 3201 /* If the measurement is showing a high impedence we've got a
3202 * microphone.
3203 */
157a75e6 3204 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3205 dev_dbg(codec->dev, "Detected microphone\n");
3206
157a75e6 3207 wm8994->mic_detecting = false;
b00adf76
MB		 3208 wm8994->jack_mic = true;
3209
3210 wm8958_micd_set_rate(codec);
3211
3212 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3213 SND_JACK_HEADSET);
3214 }
821edd2f 3215
b00adf76 3216
7c08b51f 3217 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3218 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3219 wm8994->mic_detecting = false;
b00adf76
MB		 3220
3221 wm8958_micd_set_rate(codec);
3222
af6b6fe4
MB		 3223 /* If we have jackdet that will detect removal */
3224 if (wm8994->jackdet) {
c986564b
MB		 3225 mutex_lock(&wm8994->accdet_lock);
3226
af6b6fe4
MB		 3227 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3228 WM8958_MICD_ENA, 0);
3229
c986564b
MB		 3230 wm1811_jackdet_set_mode(codec,
3231 WM1811_JACKDET_MODE_JACK);
3232
3233 mutex_unlock(&wm8994->accdet_lock);
3234
ecd1732f 3235 if (wm8994->pdata->jd_ext_cap)
07fb9d9e
MB		 3236 snd_soc_dapm_disable_pin(&codec->dapm,
3237 "MICBIAS2");
af6b6fe4 3238 }
ecd1732f
MB		 3239
3240 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3241 SND_JACK_HEADSET);
b00adf76
MB		 3242 }
3243
3244 /* Report short circuit as a button */
3245 if (wm8994->jack_mic) {
4585790d 3246 report = 0;
b00adf76 3247 if (status & 0x4)
4585790d
MB		 3248 report |= SND_JACK_BTN_0;
3249
3250 if (status & 0x8)
3251 report |= SND_JACK_BTN_1;
3252
3253 if (status & 0x10)
3254 report |= SND_JACK_BTN_2;
3255
3256 if (status & 0x20)
3257 report |= SND_JACK_BTN_3;
3258
3259 if (status & 0x40)
3260 report |= SND_JACK_BTN_4;
3261
3262 if (status & 0x80)
3263 report |= SND_JACK_BTN_5;
3264
3265 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3266 wm8994->btn_mask);
b00adf76 3267 }
821edd2f
MB		 3268}
3269
af6b6fe4
MB		 3270static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3271{
3272 struct wm8994_priv *wm8994 = data;
3273 struct snd_soc_codec *codec = wm8994->codec;
3274 int reg;
c986564b 3275 bool present;
af6b6fe4
MB		 3276
3277 mutex_lock(&wm8994->accdet_lock);
3278
3279 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3280 if (reg < 0) {
3281 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3282 mutex_unlock(&wm8994->accdet_lock);
3283 return IRQ_NONE;
3284 }
3285
3286 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3287
c986564b 3288 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3289
c986564b
MB		 3290 if (present) {
3291 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3292
55a27786
MB		 3293 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3294 WM8958_MICB2_DISCH, 0);
3295
378ec0ca
MB		 3296 /* Disable debounce while inserted */
3297 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3298 WM1811_JACKDET_DB, 0);
3299
af6b6fe4
MB		 3300 /*
3301 * Start off measument of microphone impedence to find
3302 * out what's actually there.
3303 */
3304 wm8994->mic_detecting = true;
3305 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
b9e67e5e 3306
af6b6fe4
MB		 3307 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3308 WM8958_MICD_ENA, WM8958_MICD_ENA);
3309 } else {
3310 dev_dbg(codec->dev, "Jack not detected\n");
3311
55a27786
MB		 3312 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3313 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3314
378ec0ca
MB		 3315 /* Enable debounce while removed */
3316 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3317 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3318
af6b6fe4
MB		 3319 wm8994->mic_detecting = false;
3320 wm8994->jack_mic = false;
3321 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3322 WM8958_MICD_ENA, 0);
3323 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3324 }
3325
3326 mutex_unlock(&wm8994->accdet_lock);
3327
c986564b
MB		 3328 /* If required for an external cap force MICBIAS on */
3329 if (wm8994->pdata->jd_ext_cap) {
c986564b
MB		 3330 if (present)
3331 snd_soc_dapm_force_enable_pin(&codec->dapm,
3332 "MICBIAS2");
3333 else
3334 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3335 }
3336
3337 if (present)
3338 snd_soc_jack_report(wm8994->micdet[0].jack,
3339 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3340 else
3341 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3342 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3343 wm8994->btn_mask);
3344
af6b6fe4
MB		 3345 return IRQ_HANDLED;
3346}
3347
821edd2f
MB		 3348/**
3349 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3350 *
3351 * @codec: WM8958 codec
3352 * @jack: jack to report detection events on
3353 *
3354 * Enable microphone detection functionality for the WM8958. By
3355 * default simple detection which supports the detection of up to 6
3356 * buttons plus video and microphone functionality is supported.
3357 *
3358 * The WM8958 has an advanced jack detection facility which is able to
3359 * support complex accessory detection, especially when used in
3360 * conjunction with external circuitry. In order to provide maximum
3361 * flexiblity a callback is provided which allows a completely custom
3362 * detection algorithm.
3363 */
3364int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3365 wm8958_micdet_cb cb, void *cb_data)
3366{
3367 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3368 struct wm8994 *control = wm8994->wm8994;
4585790d 3369 u16 micd_lvl_sel;
821edd2f 3370
81204c84
MB		 3371 switch (control->type) {
3372 case WM1811:
3373 case WM8958:
3374 break;
3375 default:
821edd2f 3376 return -EINVAL;
81204c84 3377 }
821edd2f
MB		 3378
3379 if (jack) {
3380 if (!cb) {
3381 dev_dbg(codec->dev, "Using default micdet callback\n");
3382 cb = wm8958_default_micdet;
3383 cb_data = codec;
3384 }
3385
4cdf5e49 3386 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3387 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3388
821edd2f
MB		 3389 wm8994->micdet[0].jack = jack;
3390 wm8994->jack_cb = cb;
3391 wm8994->jack_cb_data = cb_data;
3392
157a75e6 3393 wm8994->mic_detecting = true;
b00adf76
MB		 3394 wm8994->jack_mic = false;
3395
3396 wm8958_micd_set_rate(codec);
3397
4585790d
MB		 3398 /* Detect microphones and short circuits by default */
3399 if (wm8994->pdata->micd_lvl_sel)
3400 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3401 else
3402 micd_lvl_sel = 0x41;
3403
3404 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3405 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3406 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3407
b00adf76 3408 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3409 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3410
af6b6fe4
MB		 3411 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3412
3413 /*
3414 * If we can use jack detection start off with that,
3415 * otherwise jump straight to microphone detection.
3416 */
3417 if (wm8994->jackdet) {
55a27786
MB		 3418 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3419 WM8958_MICB2_DISCH,
3420 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3421 snd_soc_update_bits(codec, WM8994_LDO_1,
3422 WM8994_LDO1_DISCH, 0);
3423 wm1811_jackdet_set_mode(codec,
3424 WM1811_JACKDET_MODE_JACK);
3425 } else {
3426 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3427 WM8958_MICD_ENA, WM8958_MICD_ENA);
3428 }
3429
821edd2f
MB		 3430 } else {
3431 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3432 WM8958_MICD_ENA, 0);
afaf1591 3433 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3434 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3435 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3436 }
3437
3438 return 0;
3439}
3440EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3441
3442static irqreturn_t wm8958_mic_irq(int irq, void *data)
3443{
3444 struct wm8994_priv *wm8994 = data;
3445 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3446 int reg, count;
821edd2f 3447
af6b6fe4
MB		 3448 /*
3449 * Jack detection may have detected a removal simulataneously
3450 * with an update of the MICDET status; if so it will have
3451 * stopped detection and we can ignore this interrupt.
3452 */
c986564b 3453 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3454 return IRQ_HANDLED;
af6b6fe4 3455
19940b3d
MB		 3456 /* We may occasionally read a detection without an impedence
3457 * range being provided - if that happens loop again.
3458 */
3459 count = 10;
3460 do {
3461 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3462 if (reg < 0) {
3463 dev_err(codec->dev,
3464 "Failed to read mic detect status: %d\n",
3465 reg);
3466 return IRQ_NONE;
3467 }
821edd2f 3468
19940b3d
MB		 3469 if (!(reg & WM8958_MICD_VALID)) {
3470 dev_dbg(codec->dev, "Mic detect data not valid\n");
3471 goto out;
3472 }
3473
3474 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3475 break;
3476
3477 msleep(1);
3478 } while (count--);
3479
3480 if (count == 0)
3481 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3482
7116f452 3483#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3484 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3485#endif
2bbb5d66 3486
821edd2f
MB		 3487 if (wm8994->jack_cb)
3488 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3489 else
3490 dev_warn(codec->dev, "Accessory detection with no callback\n");
3491
3492out:
3493 return IRQ_HANDLED;
3494}
3495
3b1af3f8
MB		 3496static irqreturn_t wm8994_fifo_error(int irq, void *data)
3497{
3498 struct snd_soc_codec *codec = data;
3499
3500 dev_err(codec->dev, "FIFO error\n");
3501
3502 return IRQ_HANDLED;
3503}
3504
f0b182b0
MB		 3505static irqreturn_t wm8994_temp_warn(int irq, void *data)
3506{
3507 struct snd_soc_codec *codec = data;
3508
3509 dev_err(codec->dev, "Thermal warning\n");
3510
3511 return IRQ_HANDLED;
3512}
3513
3514static irqreturn_t wm8994_temp_shut(int irq, void *data)
3515{
3516 struct snd_soc_codec *codec = data;
3517
3518 dev_crit(codec->dev, "Thermal shutdown\n");
3519
3520 return IRQ_HANDLED;
3521}
3522
f0fba2ad 3523static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3524{
d9a7666f 3525 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3526 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3527 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3528 unsigned int reg;
ec62dbd7 3529 int ret, i;
9e6e96a1 3530
2bc16ed8 3531 wm8994->codec = codec;
d9a7666f 3532 codec->control_data = control->regmap;
9e6e96a1 3533
d9a7666f 3534 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3535
f0fba2ad 3536 wm8994->codec = codec;
9e6e96a1 3537
af6b6fe4
MB		 3538 mutex_init(&wm8994->accdet_lock);
3539
c7ebf932
MB		 3540 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3541 init_completion(&wm8994->fll_locked[i]);
3542
9b7c525d
MB		 3543 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3544 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3545 else if (wm8994->pdata && wm8994->pdata->irq_base)
3546 wm8994->micdet_irq = wm8994->pdata->irq_base +
3547 WM8994_IRQ_MIC1_DET;
3548
39fb51a1 3549 pm_runtime_enable(codec->dev);
5fab5174 3550 pm_runtime_idle(codec->dev);
39fb51a1 3551
f959dee9
MB		 3552 /* By default use idle_bias_off, will override for WM8994 */
3553 codec->dapm.idle_bias_off = 1;
3554
9e6e96a1 3555 /* Set revision-specific configuration */
b6b05691 3556 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3557 switch (control->type) {
3558 case WM8994:
f959dee9
MB		 3559 /* Single ended line outputs should have VMID on. */
3560 if (!wm8994->pdata->lineout1_diff ||
3561 !wm8994->pdata->lineout2_diff)
3562 codec->dapm.idle_bias_off = 0;
3563
3a423157
MB		 3564 switch (wm8994->revision) {
3565 case 2:
3566 case 3:
4537c4e7
MB		 3567 wm8994->hubs.dcs_codes_l = -5;
3568 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3569 wm8994->hubs.hp_startup_mode = 1;
3570 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3571 wm8994->hubs.series_startup = 1;
3a423157
MB		 3572 break;
3573 default:
79ef0abc 3574 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3575 break;
3576 }
280ec8b7 3577 break;
3a423157
MB		 3578
3579 case WM8958:
8437f700 3580 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3581 wm8994->hubs.hp_startup_mode = 1;
9e6e96a1 3582 break;
3a423157 3583
81204c84
MB		 3584 case WM1811:
3585 wm8994->hubs.dcs_readback_mode = 2;
3586 wm8994->hubs.no_series_update = 1;
29fdc360 3587 wm8994->hubs.hp_startup_mode = 1;
67109cbe 3588 wm8994->hubs.no_cache_class_w = true;
81204c84
MB		 3589
3590 switch (wm8994->revision) {
3591 case 0:
3592 case 1:
fc8e6e86
MB		 3593 case 2:
3594 case 3:
6473a148 3595 wm8994->hubs.dcs_codes_l = -9;
e1660585 3596 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3597 break;
3598 default:
3599 break;
3600 }
3601
3602 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3603 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3604 break;
3605
9e6e96a1
MB		 3606 default:
3607 break;
3608 }
9e6e96a1 3609
2a8a856d 3610 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3611 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3612 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3613 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3614 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3615 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3616
2a8a856d 3617 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3618 wm_hubs_dcs_done, "DC servo done",
3619 &wm8994->hubs);
3620 if (ret == 0)
3621 wm8994->hubs.dcs_done_irq = true;
3622
3a423157
MB		 3623 switch (control->type) {
3624 case WM8994:
9b7c525d
MB		 3625 if (wm8994->micdet_irq) {
3626 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3627 wm8994_mic_irq,
3628 IRQF_TRIGGER_RISING,
3629 "Mic1 detect",
3630 wm8994);
3631 if (ret != 0)
3632 dev_warn(codec->dev,
3633 "Failed to request Mic1 detect IRQ: %d\n",
3634 ret);
3635 }
3a423157 3636
2a8a856d 3637 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3638 WM8994_IRQ_MIC1_SHRT,
3639 wm8994_mic_irq, "Mic 1 short",
3640 wm8994);
3641 if (ret != 0)
3642 dev_warn(codec->dev,
3643 "Failed to request Mic1 short IRQ: %d\n",
3644 ret);
3645
2a8a856d 3646 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3647 WM8994_IRQ_MIC2_DET,
3648 wm8994_mic_irq, "Mic 2 detect",
3649 wm8994);
3650 if (ret != 0)
3651 dev_warn(codec->dev,
3652 "Failed to request Mic2 detect IRQ: %d\n",
3653 ret);
3654
2a8a856d 3655 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3656 WM8994_IRQ_MIC2_SHRT,
3657 wm8994_mic_irq, "Mic 2 short",
3658 wm8994);
3659 if (ret != 0)
3660 dev_warn(codec->dev,
3661 "Failed to request Mic2 short IRQ: %d\n",
3662 ret);
3663 break;
821edd2f
MB		 3664
3665 case WM8958:
81204c84 3666 case WM1811:
9b7c525d
MB		 3667 if (wm8994->micdet_irq) {
3668 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3669 wm8958_mic_irq,
3670 IRQF_TRIGGER_RISING,
3671 "Mic detect",
3672 wm8994);
3673 if (ret != 0)
3674 dev_warn(codec->dev,
3675 "Failed to request Mic detect IRQ: %d\n",
3676 ret);
3677 }
3a423157 3678 }
88766984 3679
af6b6fe4
MB		 3680 switch (control->type) {
3681 case WM1811:
3682 if (wm8994->revision > 1) {
3683 ret = wm8994_request_irq(wm8994->wm8994,
3684 WM8994_IRQ_GPIO(6),
3685 wm1811_jackdet_irq, "JACKDET",
3686 wm8994);
3687 if (ret == 0)
3688 wm8994->jackdet = true;
3689 }
3690 break;
3691 default:
3692 break;
3693 }
3694
c7ebf932
MB		 3695 wm8994->fll_locked_irq = true;
3696 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3697 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3698 WM8994_IRQ_FLL1_LOCK + i,
3699 wm8994_fll_locked_irq, "FLL lock",
3700 &wm8994->fll_locked[i]);
3701 if (ret != 0)
3702 wm8994->fll_locked_irq = false;
3703 }
3704
27060b3c
MB		 3705 /* Make sure we can read from the GPIOs if they're inputs */
3706 pm_runtime_get_sync(codec->dev);
3707
9e6e96a1
MB		 3708 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3709 * configured on init - if a system wants to do this dynamically
3710 * at runtime we can deal with that then.
3711 */
d9a7666f 3712 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3713 if (ret < 0) {
3714 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3715 goto err_irq;
9e6e96a1 3716 }
d9a7666f 3717 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3718 wm8994->lrclk_shared[0] = 1;
3719 wm8994_dai[0].symmetric_rates = 1;
3720 } else {
3721 wm8994->lrclk_shared[0] = 0;
3722 }
3723
d9a7666f 3724 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3725 if (ret < 0) {
3726 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3727 goto err_irq;
9e6e96a1 3728 }
d9a7666f 3729 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3730 wm8994->lrclk_shared[1] = 1;
3731 wm8994_dai[1].symmetric_rates = 1;
3732 } else {
3733 wm8994->lrclk_shared[1] = 0;
3734 }
3735
27060b3c
MB		 3736 pm_runtime_put(codec->dev);
3737
9e6e96a1 3738 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3739 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3740 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3741 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3742 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3743 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3744 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3745 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3746 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3747 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3748 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3749 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3750 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3751 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3752 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3753 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3754 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3755 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3756 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3757 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3758 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3759 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3760 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3761 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3762 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3763 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3764 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3765 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3766 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3767 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3768 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3769 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3770 WM8994_DAC2_VU, WM8994_DAC2_VU);
3771
3772 /* Set the low bit of the 3D stereo depth so TLV matches */
3773 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3774 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3775 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3776 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3777 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3778 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3779 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3780 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3781 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3782
5b739670
MB		 3783 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3784 * use this; it only affects behaviour on idle TDM clock
3785 * cycles. */
3786 switch (control->type) {
3787 case WM8994:
3788 case WM8958:
3789 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3790 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3791 break;
3792 default:
3793 break;
3794 }
d1ce6b20 3795
500fa30e
MB		 3796 /* Put MICBIAS into bypass mode by default on newer devices */
3797 switch (control->type) {
3798 case WM8958:
3799 case WM1811:
3800 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3801 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3802 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3803 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3804 break;
3805 default:
3806 break;
3807 }
3808
9e6e96a1
MB		 3809 wm8994_update_class_w(codec);
3810
f0fba2ad 3811 wm8994_handle_pdata(wm8994);
9e6e96a1 3812
f0fba2ad 3813 wm_hubs_add_analogue_controls(codec);
022658be 3814 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3815 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3816 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3817 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3818
3819 switch (control->type) {
3820 case WM8994:
3821 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3822 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3823 if (wm8994->revision < 4) {
173efa09
DP		 3824 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3825 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3826 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3827 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3828 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3829 ARRAY_SIZE(wm8994_dac_revd_widgets));
3830 } else {
173efa09
DP		 3831 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3832 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3833 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3834 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3835 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3836 ARRAY_SIZE(wm8994_dac_widgets));
3837 }
c4431df0
MB		 3838 break;
3839 case WM8958:
022658be 3840 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3841 ARRAY_SIZE(wm8958_snd_controls));
3842 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3843 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3844 if (wm8994->revision < 1) {
3845 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3846 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3847 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3848 ARRAY_SIZE(wm8994_adc_revd_widgets));
3849 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3850 ARRAY_SIZE(wm8994_dac_revd_widgets));
3851 } else {
3852 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3853 ARRAY_SIZE(wm8994_lateclk_widgets));
3854 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3855 ARRAY_SIZE(wm8994_adc_widgets));
3856 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3857 ARRAY_SIZE(wm8994_dac_widgets));
3858 }
c4431df0 3859 break;
81204c84
MB		 3860
3861 case WM1811:
022658be 3862 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3863 ARRAY_SIZE(wm8958_snd_controls));
3864 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3865 ARRAY_SIZE(wm8958_dapm_widgets));
3866 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3867 ARRAY_SIZE(wm8994_lateclk_widgets));
3868 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3869 ARRAY_SIZE(wm8994_adc_widgets));
3870 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3871 ARRAY_SIZE(wm8994_dac_widgets));
3872 break;
c4431df0
MB		 3873 }
3874
3875
f0fba2ad 3876 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3877 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3878
c4431df0
MB		 3879 switch (control->type) {
3880 case WM8994:
3881 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3882 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3883
173efa09 3884 if (wm8994->revision < 4) {
6ed8f148
MB		 3885 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3886 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3887 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3888 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3889 } else {
3890 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3891 ARRAY_SIZE(wm8994_lateclk_intercon));
3892 }
c4431df0
MB		 3893 break;
3894 case WM8958:
780e2806
MB		 3895 if (wm8994->revision < 1) {
3896 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3897 ARRAY_SIZE(wm8994_revd_intercon));
3898 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3899 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3900 } else {
3901 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3902 ARRAY_SIZE(wm8994_lateclk_intercon));
3903 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3904 ARRAY_SIZE(wm8958_intercon));
3905 }
f701a2e5
MB		 3906
3907 wm8958_dsp2_init(codec);
c4431df0 3908 break;
81204c84
MB		 3909 case WM1811:
3910 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3911 ARRAY_SIZE(wm8994_lateclk_intercon));
3912 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3913 ARRAY_SIZE(wm8958_intercon));
3914 break;
c4431df0
MB		 3915 }
3916
9e6e96a1
MB		 3917 return 0;
3918
88766984 3919err_irq:
af6b6fe4
MB		 3920 if (wm8994->jackdet)
3921 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3922 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3923 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3924 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3925 if (wm8994->micdet_irq)
3926 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3927 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3928 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3929 &wm8994->fll_locked[i]);
2a8a856d 3930 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3931 &wm8994->hubs);
2a8a856d
MB		 3932 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3933 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3934 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3935
9e6e96a1
MB		 3936 return ret;
3937}
3938
34ff0f95 3939static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3940{
f0fba2ad 3941 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3942 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3943 int i;
9e6e96a1
MB		 3944
3945 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3946
39fb51a1
MB		 3947 pm_runtime_disable(codec->dev);
3948
c7ebf932 3949 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3950 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3951 &wm8994->fll_locked[i]);
3952
2a8a856d 3953 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3954 &wm8994->hubs);
2a8a856d
MB		 3955 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3956 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3957 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3958
af6b6fe4
MB		 3959 if (wm8994->jackdet)
3960 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3961
3a423157
MB		 3962 switch (control->type) {
3963 case WM8994:
9b7c525d
MB		 3964 if (wm8994->micdet_irq)
3965 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3966 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3967 wm8994);
2a8a856d 3968 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3969 wm8994);
2a8a856d 3970 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3971 wm8994);
3972 break;
821edd2f 3973
81204c84 3974 case WM1811:
821edd2f 3975 case WM8958:
9b7c525d
MB		 3976 if (wm8994->micdet_irq)
3977 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3978 break;
3a423157 3979 }
34ff0f95
JJ		 3980 release_firmware(wm8994->mbc);
3981 release_firmware(wm8994->mbc_vss);
3982 release_firmware(wm8994->enh_eq);
24fb2b11 3983 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3984 return 0;
3985}
3986
f0fba2ad
LG		 3987static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3988 .probe = wm8994_codec_probe,
3989 .remove = wm8994_codec_remove,
4752a887
MB		 3990 .suspend = wm8994_codec_suspend,
3991 .resume = wm8994_codec_resume,
f0fba2ad
LG		 3992 .set_bias_level = wm8994_set_bias_level,
3993};
3994
3995static int __devinit wm8994_probe(struct platform_device *pdev)
3996{
2bc16ed8
MB		 3997 struct wm8994_priv *wm8994;
3998
3999 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4000 GFP_KERNEL);
4001 if (wm8994 == NULL)
4002 return -ENOMEM;
4003 platform_set_drvdata(pdev, wm8994);
4004
4005 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4006 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4007
f0fba2ad
LG		 4008 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4009 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4010}
4011
4012static int __devexit wm8994_remove(struct platform_device *pdev)
4013{
4014 snd_soc_unregister_codec(&pdev->dev);
4015 return 0;
4016}
4017
4752a887
MB		 4018#ifdef CONFIG_PM_SLEEP
4019static int wm8994_suspend(struct device *dev)
4020{
4021 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4022
4023 /* Drop down to power saving mode when system is suspended */
4024 if (wm8994->jackdet && !wm8994->active_refcount)
4025 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4026 WM1811_JACKDET_MODE_MASK,
4027 wm8994->jackdet_mode);
4028
4029 return 0;
4030}
4031
4032static int wm8994_resume(struct device *dev)
4033{
4034 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4035
4036 if (wm8994->jackdet && wm8994->jack_cb)
4037 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4038 WM1811_JACKDET_MODE_MASK,
4039 WM1811_JACKDET_MODE_AUDIO);
4040
4041 return 0;
4042}
4043#endif
4044
4045static const struct dev_pm_ops wm8994_pm_ops = {
4046 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4047};
4048
9e6e96a1
MB		 4049static struct platform_driver wm8994_codec_driver = {
4050 .driver = {
4752a887
MB		 4051 .name = "wm8994-codec",
4052 .owner = THIS_MODULE,
4053 .pm = &wm8994_pm_ops,
4054 },
f0fba2ad
LG		 4055 .probe = wm8994_probe,
4056 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 4057};
4058
5bbcc3c0 4059module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4060
4061MODULE_DESCRIPTION("ASoC WM8994 driver");
4062MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4063MODULE_LICENSE("GPL");
4064MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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