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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
d1a0a299 19#include <linux/gcd.h>
9e6e96a1
MB		 20#include <linux/i2c.h>
21#include <linux/platform_device.h>
39fb51a1 22#include <linux/pm_runtime.h>
9e6e96a1 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
9e6e96a1 25#include <sound/core.h>
821edd2f 26#include <sound/jack.h>
9e6e96a1
MB		 27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
9e6e96a1
MB		 30#include <sound/initval.h>
31#include <sound/tlv.h>
2bbb5d66 32#include <trace/events/asoc.h>
9e6e96a1
MB		 33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
af6b6fe4
MB		 42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
9e6e96a1
MB		 47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
bfd37bb5
MB		 50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
9e6e96a1
MB		 83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
af6b6fe4 95static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
604533de
MB		 98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 100};
101
af6b6fe4
MB		 102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
e9d9a968
MB		 105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 107};
108
b00adf76
MB		 109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 112 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 113 int best, i, sysclk, val;
114 bool idle;
af6b6fe4
MB		 115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
b00adf76
MB		 118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
d9dd4ada
MB		 126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
cd1707a9 129 } else if (wm8994->jackdet) {
af6b6fe4
MB		 130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
b00adf76 137 best = 0;
af6b6fe4
MB		 138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
b00adf76 140 continue;
af6b6fe4
MB		 141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
b00adf76 143 best = i;
af6b6fe4 144 else if (rates[best].idle != idle)
b00adf76
MB		 145 best = i;
146 }
147
af6b6fe4
MB		 148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 150
3a334ada
MB		 151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
b00adf76
MB		 155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
9e6e96a1
MB		 160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
b2c812e2 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
5e5e2bef 203
9e6e96a1
MB		 204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
b2c812e2 215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 216 int change, new;
9e6e96a1
MB		 217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
9e6e96a1 231 return 0;
b00adf76 232 }
9e6e96a1
MB		 233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
04f45c49
AL		 239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 243
b00adf76
MB		 244 wm8958_micd_set_rate(codec);
245
9e6e96a1
MB		 246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262}
263
264static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266};
267
e61a35b7
TI		 268static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
269 WM8994_SIDETONE, 7, sidetone_hpf_text);
9e6e96a1 270
146fd574
UK		 271static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273};
274
e61a35b7
TI		 275static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
276 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
146fd574 277
e61a35b7
TI		 278static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
279 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
146fd574 280
e61a35b7
TI		 281static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
282 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
146fd574 283
9e6e96a1
MB		 284static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 289static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 290static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 291
292#define WM8994_DRC_SWITCH(xname, reg, shift) \
6e06509c
LPC		 293 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294 snd_soc_get_volsw, wm8994_put_drc_sw)
9e6e96a1
MB		 295
296static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298{
299 struct soc_mixer_control *mc =
300 (struct soc_mixer_control *)kcontrol->private_value;
301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
302 int mask, ret;
303
304 /* Can't enable both ADC and DAC paths simultaneously */
305 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307 WM8994_AIF1ADC1R_DRC_ENA_MASK;
308 else
309 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310
311 ret = snd_soc_read(codec, mc->reg);
312 if (ret < 0)
313 return ret;
314 if (ret & mask)
315 return -EINVAL;
316
317 return snd_soc_put_volsw(kcontrol, ucontrol);
318}
319
9e6e96a1
MB		 320static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321{
b2c812e2 322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 323 struct wm8994 *control = wm8994->wm8994;
324 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 325 int base = wm8994_drc_base[drc];
326 int cfg = wm8994->drc_cfg[drc];
327 int save, i;
328
329 /* Save any enables; the configuration should clear them. */
330 save = snd_soc_read(codec, base);
331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332 WM8994_AIF1ADC1R_DRC_ENA;
333
334 for (i = 0; i < WM8994_DRC_REGS; i++)
335 snd_soc_update_bits(codec, base + i, 0xffff,
336 pdata->drc_cfgs[cfg].regs[i]);
337
338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339 WM8994_AIF1ADC1L_DRC_ENA |
340 WM8994_AIF1ADC1R_DRC_ENA, save);
341}
342
343/* Icky as hell but saves code duplication */
344static int wm8994_get_drc(const char *name)
345{
346 if (strcmp(name, "AIF1DRC1 Mode") == 0)
347 return 0;
348 if (strcmp(name, "AIF1DRC2 Mode") == 0)
349 return 1;
350 if (strcmp(name, "AIF2DRC Mode") == 0)
351 return 2;
352 return -EINVAL;
353}
354
355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357{
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 360 struct wm8994 *control = wm8994->wm8994;
361 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 362 int drc = wm8994_get_drc(kcontrol->id.name);
363 int value = ucontrol->value.integer.value[0];
364
365 if (drc < 0)
366 return drc;
367
368 if (value >= pdata->num_drc_cfgs)
369 return -EINVAL;
370
371 wm8994->drc_cfg[drc] = value;
372
373 wm8994_set_drc(codec, drc);
374
375 return 0;
376}
377
378static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380{
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 383 int drc = wm8994_get_drc(kcontrol->id.name);
384
7d6898be
VK		 385 if (drc < 0)
386 return drc;
9e6e96a1
MB		 387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 438 * current configuration.
9e6e96a1
MB		 439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448}
449
450/* Icky as hell but saves code duplication */
451static int wm8994_get_retune_mobile_block(const char *name)
452{
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460}
461
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
7d6898be
VK		 492 if (block < 0)
493 return block;
494
9e6e96a1
MB		 495 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496
497 return 0;
498}
499
96b101ef 500static const char *aif_chan_src_text[] = {
f554885f
MB		 501 "Left", "Right"
502};
503
e61a35b7
TI		 504static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
505 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
96b101ef 506
e61a35b7
TI		 507static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
508 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
96b101ef 509
e61a35b7
TI		 510static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
511 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
96b101ef 512
e61a35b7
TI		 513static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
514 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
96b101ef 515
e61a35b7
TI		 516static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
517 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
f554885f 518
e61a35b7
TI		 519static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
520 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
f554885f 521
e61a35b7
TI		 522static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
523 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
f554885f 524
e61a35b7
TI		 525static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
526 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
f554885f 527
154b26aa
MB		 528static const char *osr_text[] = {
529 "Low Power", "High Performance",
530};
531
e61a35b7
TI		 532static SOC_ENUM_SINGLE_DECL(dac_osr,
533 WM8994_OVERSAMPLING, 0, osr_text);
154b26aa 534
e61a35b7
TI		 535static SOC_ENUM_SINGLE_DECL(adc_osr,
536 WM8994_OVERSAMPLING, 1, osr_text);
154b26aa 537
9e6e96a1
MB		 538static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540 WM8994_AIF1_ADC1_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543 WM8994_AIF1_ADC2_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546 WM8994_AIF2_ADC_RIGHT_VOLUME,
547 1, 119, 0, digital_tlv),
548
96b101ef
MB		 549SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 551SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 553
f554885f
MB		 554SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 556SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 558
9e6e96a1
MB		 559SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565
566SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568
569SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572
573WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576
577WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580
581WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584
585SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590 5, 12, 0, st_tlv),
591SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592 0, 12, 0, st_tlv),
593SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595
146fd574
UK		 596SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601
602SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604
154b26aa
MB		 605SOC_ENUM("ADC OSR", adc_osr),
606SOC_ENUM("DAC OSR", dac_osr),
607
9e6e96a1
MB		 608SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612
613SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617
618SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619 6, 1, 1, wm_hubs_spkmix_tlv),
620SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621 2, 1, 1, wm_hubs_spkmix_tlv),
622
623SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624 6, 1, 1, wm_hubs_spkmix_tlv),
625SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626 2, 1, 1, wm_hubs_spkmix_tlv),
627
628SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
458350b3 630SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 631 8, 1, 0),
632SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633 10, 15, 0, wm8994_3d_tlv),
634SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635 8, 1, 0),
458350b3 636SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 637 10, 15, 0, wm8994_3d_tlv),
458350b3 638SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 639 8, 1, 0),
640};
641
642static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648 eq_tlv),
649SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652 eq_tlv),
653
654SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659 eq_tlv),
660SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661 eq_tlv),
662SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663 eq_tlv),
664
665SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666 eq_tlv),
667SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668 eq_tlv),
669SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670 eq_tlv),
671SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672 eq_tlv),
673SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674 eq_tlv),
675};
676
45a690f6
MB		 677static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680 WM8994_AIF1ADC1R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683 WM8994_AIF1ADC2R_DRC_ENA),
684SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686 WM8994_AIF2ADCR_DRC_ENA),
687};
688
1ddc07d0
MB		 689static const char *wm8958_ng_text[] = {
690 "30ms", "125ms", "250ms", "500ms",
691};
692
e61a35b7
TI		 693static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
694 WM8958_AIF1_DAC1_NOISE_GATE,
695 WM8958_AIF1DAC1_NG_THR_SHIFT,
696 wm8958_ng_text);
1ddc07d0 697
e61a35b7
TI		 698static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
699 WM8958_AIF1_DAC2_NOISE_GATE,
700 WM8958_AIF1DAC2_NG_THR_SHIFT,
701 wm8958_ng_text);
1ddc07d0 702
e61a35b7
TI		 703static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
704 WM8958_AIF2_DAC_NOISE_GATE,
705 WM8958_AIF2DAC_NG_THR_SHIFT,
706 wm8958_ng_text);
1ddc07d0 707
c4431df0
MB		 708static const struct snd_kcontrol_new wm8958_snd_controls[] = {
709SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 710
711SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
712 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
713SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
714SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
715 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
716 7, 1, ng_tlv),
717
718SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
719 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
720SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
721SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
722 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
723 7, 1, ng_tlv),
724
725SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
726 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
727SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
728SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
729 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
730 7, 1, ng_tlv),
c4431df0
MB		 731};
732
81204c84
MB		 733static const struct snd_kcontrol_new wm1811_snd_controls[] = {
734SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
735 mixin_boost_tlv),
736SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
737 mixin_boost_tlv),
738};
739
af6b6fe4
MB		 740/* We run all mode setting through a function to enforce audio mode */
741static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
742{
743 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
744
78b76dbe 745 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
MB		 746 return;
747
af6b6fe4
MB		 748 if (wm8994->active_refcount)
749 mode = WM1811_JACKDET_MODE_AUDIO;
750
4752a887 751 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 752 return;
753
4752a887 754 wm8994->jackdet_mode = mode;
1defde2a 755
4752a887
MB		 756 /* Always use audio mode to detect while the system is active */
757 if (mode != WM1811_JACKDET_MODE_NONE)
758 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 759
4752a887
MB		 760 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
761 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 762}
763
764static void active_reference(struct snd_soc_codec *codec)
765{
766 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
767
768 mutex_lock(&wm8994->accdet_lock);
769
770 wm8994->active_refcount++;
771
772 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
773 wm8994->active_refcount);
774
1defde2a
MB		 775 /* If we're using jack detection go into audio mode */
776 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 777
778 mutex_unlock(&wm8994->accdet_lock);
779}
780
781static void active_dereference(struct snd_soc_codec *codec)
782{
783 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784 u16 mode;
785
786 mutex_lock(&wm8994->accdet_lock);
787
788 wm8994->active_refcount--;
789
790 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
791 wm8994->active_refcount);
792
793 if (wm8994->active_refcount == 0) {
794 /* Go into appropriate detection only mode */
1defde2a
MB		 795 if (wm8994->jack_mic || wm8994->mic_detecting)
796 mode = WM1811_JACKDET_MODE_MIC;
797 else
798 mode = WM1811_JACKDET_MODE_JACK;
799
800 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 801 }
802
803 mutex_unlock(&wm8994->accdet_lock);
804}
805
9e6e96a1
MB		 806static int clk_sys_event(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808{
809 struct snd_soc_codec *codec = w->codec;
99af79df 810 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 811
812 switch (event) {
813 case SND_SOC_DAPM_PRE_PMU:
814 return configure_clock(codec);
815
99af79df
MB		 816 case SND_SOC_DAPM_POST_PMU:
817 /*
818 * JACKDET won't run until we start the clock and it
819 * only reports deltas, make sure we notify the state
820 * up the stack on startup. Use a *very* generous
821 * timeout for paranoia, there's no urgency and we
822 * don't want false reports.
823 */
824 if (wm8994->jackdet && !wm8994->clk_has_run) {
68defe58
MB		 825 queue_delayed_work(system_power_efficient_wq,
826 &wm8994->jackdet_bootstrap,
827 msecs_to_jiffies(1000));
99af79df
MB		 828 wm8994->clk_has_run = true;
829 }
830 break;
831
9e6e96a1
MB		 832 case SND_SOC_DAPM_POST_PMD:
833 configure_clock(codec);
834 break;
835 }
836
837 return 0;
838}
839
4b7ed83a
MB		 840static void vmid_reference(struct snd_soc_codec *codec)
841{
842 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
843
db966f8a
MB		 844 pm_runtime_get_sync(codec->dev);
845
4b7ed83a
MB		 846 wm8994->vmid_refcount++;
847
848 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
849 wm8994->vmid_refcount);
850
851 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 852 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 853 WM8994_LINEOUT1_DISCH |
22f8d055 854 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 855
f7085641
MB		 856 wm_hubs_vmid_ena(codec);
857
22f8d055
MB		 858 switch (wm8994->vmid_mode) {
859 default:
cbd71f30 860 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 861 case WM8994_VMID_NORMAL:
862 /* Startup bias, VMID ramp & buffer */
863 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
864 WM8994_BIAS_SRC |
865 WM8994_VMID_DISCH |
866 WM8994_STARTUP_BIAS_ENA |
867 WM8994_VMID_BUF_ENA |
868 WM8994_VMID_RAMP_MASK,
869 WM8994_BIAS_SRC |
870 WM8994_STARTUP_BIAS_ENA |
871 WM8994_VMID_BUF_ENA |
a3a1d9d2 872 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 873
874 /* Main bias enable, VMID=2x40k */
875 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
876 WM8994_BIAS_ENA |
877 WM8994_VMID_SEL_MASK,
878 WM8994_BIAS_ENA | 0x2);
879
a3a1d9d2 880 msleep(300);
22f8d055
MB		 881
882 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
883 WM8994_VMID_RAMP_MASK |
884 WM8994_BIAS_SRC,
885 0);
886 break;
cc6d5a8c 887
22f8d055
MB		 888 case WM8994_VMID_FORCE:
889 /* Startup bias, slow VMID ramp & buffer */
890 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
891 WM8994_BIAS_SRC |
892 WM8994_VMID_DISCH |
893 WM8994_STARTUP_BIAS_ENA |
894 WM8994_VMID_BUF_ENA |
895 WM8994_VMID_RAMP_MASK,
896 WM8994_BIAS_SRC |
897 WM8994_STARTUP_BIAS_ENA |
898 WM8994_VMID_BUF_ENA |
899 (0x2 << WM8994_VMID_RAMP_SHIFT));
900
901 /* Main bias enable, VMID=2x40k */
902 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
903 WM8994_BIAS_ENA |
904 WM8994_VMID_SEL_MASK,
905 WM8994_BIAS_ENA | 0x2);
906
907 msleep(400);
908
909 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
910 WM8994_VMID_RAMP_MASK |
911 WM8994_BIAS_SRC,
912 0);
913 break;
914 }
4b7ed83a
MB		 915 }
916}
917
918static void vmid_dereference(struct snd_soc_codec *codec)
919{
920 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
921
922 wm8994->vmid_refcount--;
923
924 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
925 wm8994->vmid_refcount);
926
927 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 928 if (wm8994->hubs.lineout1_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT1N_ENA |
931 WM8994_LINEOUT1P_ENA,
932 WM8994_LINEOUT1N_ENA |
933 WM8994_LINEOUT1P_ENA);
934
935 if (wm8994->hubs.lineout2_se)
936 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
937 WM8994_LINEOUT2N_ENA |
938 WM8994_LINEOUT2P_ENA,
939 WM8994_LINEOUT2N_ENA |
940 WM8994_LINEOUT2P_ENA);
941
942 /* Start discharging VMID */
4b7ed83a
MB		 943 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
944 WM8994_BIAS_SRC |
22f8d055 945 WM8994_VMID_DISCH,
4b7ed83a 946 WM8994_BIAS_SRC |
22f8d055 947 WM8994_VMID_DISCH);
4b7ed83a 948
f95be9d6
MB		 949 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
950 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 951
f95be9d6 952 msleep(400);
e85b26ce 953
22f8d055 954 /* Active discharge */
4b7ed83a
MB		 955 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
956 WM8994_LINEOUT1_DISCH |
957 WM8994_LINEOUT2_DISCH,
958 WM8994_LINEOUT1_DISCH |
959 WM8994_LINEOUT2_DISCH);
960
22f8d055
MB		 961 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
962 WM8994_LINEOUT1N_ENA |
963 WM8994_LINEOUT1P_ENA |
964 WM8994_LINEOUT2N_ENA |
965 WM8994_LINEOUT2P_ENA, 0);
966
4b7ed83a
MB		 967 /* Switch off startup biases */
968 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
969 WM8994_BIAS_SRC |
970 WM8994_STARTUP_BIAS_ENA |
971 WM8994_VMID_BUF_ENA |
972 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 973
974 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 975 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 976 }
db966f8a
MB		 977
978 pm_runtime_put(codec->dev);
4b7ed83a
MB		 979}
980
981static int vmid_event(struct snd_soc_dapm_widget *w,
982 struct snd_kcontrol *kcontrol, int event)
983{
984 struct snd_soc_codec *codec = w->codec;
985
986 switch (event) {
987 case SND_SOC_DAPM_PRE_PMU:
988 vmid_reference(codec);
989 break;
990
991 case SND_SOC_DAPM_POST_PMD:
992 vmid_dereference(codec);
993 break;
994 }
995
996 return 0;
997}
998
c340304d 999static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 1000{
9e6e96a1
MB		 1001 int source = 0; /* GCC flow analysis can't track enable */
1002 int reg, reg_r;
1003
c340304d 1004 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 1005 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1006 switch (reg) {
1007 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1008 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1009 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010 break;
1011 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1012 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1013 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014 break;
1015 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1016 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1017 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018 break;
1019 default:
ee839a21 1020 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1021 return false;
9e6e96a1
MB		 1022 }
1023
1024 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1025 if (reg_r != reg) {
ee839a21 1026 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1027 return false;
9e6e96a1
MB		 1028 }
1029
c340304d
MB		 1030 /* Set the source up */
1031 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1032 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1033
c340304d 1034 return true;
9e6e96a1
MB		 1035}
1036
1a38336b
MB		 1037static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1038 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1039{
1040 struct snd_soc_codec *codec = w->codec;
79748cdb 1041 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d3134e21 1042 struct wm8994 *control = wm8994->wm8994;
1a38336b 1043 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1044 int i;
1a38336b
MB		 1045 int dac;
1046 int adc;
1047 int val;
1048
1049 switch (control->type) {
1050 case WM8994:
1051 case WM8958:
1052 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1053 break;
1054 default:
1055 break;
1056 }
173efa09
DP		 1057
1058 switch (event) {
1059 case SND_SOC_DAPM_PRE_PMU:
79748cdb
MB		 1060 /* Don't enable timeslot 2 if not in use */
1061 if (wm8994->channels[0] <= 2)
1062 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1063
1a38336b
MB		 1064 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1065 if ((val & WM8994_AIF1ADCL_SRC) &&
1066 (val & WM8994_AIF1ADCR_SRC))
1067 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1068 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1069 !(val & WM8994_AIF1ADCR_SRC))
1070 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1071 else
1072 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1073 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1074
1075 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1076 if ((val & WM8994_AIF1DACL_SRC) &&
1077 (val & WM8994_AIF1DACR_SRC))
1078 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1079 else if (!(val & WM8994_AIF1DACL_SRC) &&
1080 !(val & WM8994_AIF1DACR_SRC))
1081 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1082 else
1083 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1084 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1085
1086 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1087 mask, adc);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1089 mask, dac);
1090 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1091 WM8994_AIF1DSPCLK_ENA |
1092 WM8994_SYSDSPCLK_ENA,
1093 WM8994_AIF1DSPCLK_ENA |
1094 WM8994_SYSDSPCLK_ENA);
1095 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1096 WM8994_AIF1ADC1R_ENA |
1097 WM8994_AIF1ADC1L_ENA |
1098 WM8994_AIF1ADC2R_ENA |
1099 WM8994_AIF1ADC2L_ENA);
1100 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1101 WM8994_AIF1DAC1R_ENA |
1102 WM8994_AIF1DAC1L_ENA |
1103 WM8994_AIF1DAC2R_ENA |
1104 WM8994_AIF1DAC2L_ENA);
173efa09 1105 break;
173efa09 1106
bfd37bb5
MB		 1107 case SND_SOC_DAPM_POST_PMU:
1108 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1109 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1110 snd_soc_read(codec,
1111 wm8994_vu_bits[i].reg));
1112 break;
1113
1a38336b
MB		 1114 case SND_SOC_DAPM_PRE_PMD:
1115 case SND_SOC_DAPM_POST_PMD:
1116 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1117 mask, 0);
1118 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1119 mask, 0);
1120
1121 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1122 if (val & WM8994_AIF2DSPCLK_ENA)
1123 val = WM8994_SYSDSPCLK_ENA;
1124 else
1125 val = 0;
1126 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1127 WM8994_SYSDSPCLK_ENA |
1128 WM8994_AIF1DSPCLK_ENA, val);
1129 break;
1130 }
c6b7b570 1131
173efa09
DP		 1132 return 0;
1133}
1134
1a38336b
MB		 1135static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1136 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1137{
1138 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1139 int i;
1a38336b
MB		 1140 int dac;
1141 int adc;
1142 int val;
173efa09
DP		 1143
1144 switch (event) {
1a38336b
MB		 1145 case SND_SOC_DAPM_PRE_PMU:
1146 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1147 if ((val & WM8994_AIF2ADCL_SRC) &&
1148 (val & WM8994_AIF2ADCR_SRC))
1149 adc = WM8994_AIF2ADCR_ENA;
1150 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1151 !(val & WM8994_AIF2ADCR_SRC))
1152 adc = WM8994_AIF2ADCL_ENA;
1153 else
1154 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1155
1156
1157 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1158 if ((val & WM8994_AIF2DACL_SRC) &&
1159 (val & WM8994_AIF2DACR_SRC))
1160 dac = WM8994_AIF2DACR_ENA;
1161 else if (!(val & WM8994_AIF2DACL_SRC) &&
1162 !(val & WM8994_AIF2DACR_SRC))
1163 dac = WM8994_AIF2DACL_ENA;
1164 else
1165 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1166
1167 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1168 WM8994_AIF2ADCL_ENA |
1169 WM8994_AIF2ADCR_ENA, adc);
1170 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1171 WM8994_AIF2DACL_ENA |
1172 WM8994_AIF2DACR_ENA, dac);
1173 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1174 WM8994_AIF2DSPCLK_ENA |
1175 WM8994_SYSDSPCLK_ENA,
1176 WM8994_AIF2DSPCLK_ENA |
1177 WM8994_SYSDSPCLK_ENA);
1178 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1179 WM8994_AIF2ADCL_ENA |
1180 WM8994_AIF2ADCR_ENA,
1181 WM8994_AIF2ADCL_ENA |
1182 WM8994_AIF2ADCR_ENA);
1183 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1184 WM8994_AIF2DACL_ENA |
1185 WM8994_AIF2DACR_ENA,
1186 WM8994_AIF2DACL_ENA |
1187 WM8994_AIF2DACR_ENA);
1188 break;
1189
bfd37bb5
MB		 1190 case SND_SOC_DAPM_POST_PMU:
1191 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1192 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1193 snd_soc_read(codec,
1194 wm8994_vu_bits[i].reg));
1195 break;
1196
1a38336b 1197 case SND_SOC_DAPM_PRE_PMD:
173efa09 1198 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1199 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1200 WM8994_AIF2DACL_ENA |
1201 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1202 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1203 WM8994_AIF2ADCL_ENA |
1204 WM8994_AIF2ADCR_ENA, 0);
1205
1206 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1207 if (val & WM8994_AIF1DSPCLK_ENA)
1208 val = WM8994_SYSDSPCLK_ENA;
1209 else
1210 val = 0;
1211 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1212 WM8994_SYSDSPCLK_ENA |
1213 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1214 break;
1215 }
1216
1217 return 0;
1218}
1219
1a38336b
MB		 1220static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1221 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1222{
1223 struct snd_soc_codec *codec = w->codec;
1224 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1225
1226 switch (event) {
1227 case SND_SOC_DAPM_PRE_PMU:
1228 wm8994->aif1clk_enable = 1;
1229 break;
a3cff81a
DP		 1230 case SND_SOC_DAPM_POST_PMD:
1231 wm8994->aif1clk_disable = 1;
1232 break;
173efa09
DP		 1233 }
1234
1235 return 0;
1236}
1237
1a38336b
MB		 1238static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1239 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1240{
1241 struct snd_soc_codec *codec = w->codec;
1242 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1243
1244 switch (event) {
1245 case SND_SOC_DAPM_PRE_PMU:
1246 wm8994->aif2clk_enable = 1;
1247 break;
a3cff81a
DP		 1248 case SND_SOC_DAPM_POST_PMD:
1249 wm8994->aif2clk_disable = 1;
1250 break;
173efa09
DP		 1251 }
1252
1253 return 0;
1254}
1255
1a38336b
MB		 1256static int late_enable_ev(struct snd_soc_dapm_widget *w,
1257 struct snd_kcontrol *kcontrol, int event)
1258{
1259 struct snd_soc_codec *codec = w->codec;
1260 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1261
1262 switch (event) {
1263 case SND_SOC_DAPM_PRE_PMU:
1264 if (wm8994->aif1clk_enable) {
c8fdc1b5 1265 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1266 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1267 WM8994_AIF1CLK_ENA_MASK,
1268 WM8994_AIF1CLK_ENA);
c8fdc1b5 1269 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1270 wm8994->aif1clk_enable = 0;
1271 }
1272 if (wm8994->aif2clk_enable) {
c8fdc1b5 1273 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1274 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1275 WM8994_AIF2CLK_ENA_MASK,
1276 WM8994_AIF2CLK_ENA);
c8fdc1b5 1277 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1278 wm8994->aif2clk_enable = 0;
1279 }
1280 break;
1281 }
1282
1283 /* We may also have postponed startup of DSP, handle that. */
1284 wm8958_aif_ev(w, kcontrol, event);
1285
1286 return 0;
1287}
1288
1289static int late_disable_ev(struct snd_soc_dapm_widget *w,
1290 struct snd_kcontrol *kcontrol, int event)
1291{
1292 struct snd_soc_codec *codec = w->codec;
1293 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1294
1295 switch (event) {
1296 case SND_SOC_DAPM_POST_PMD:
1297 if (wm8994->aif1clk_disable) {
c8fdc1b5 1298 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1299 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1300 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1301 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1302 wm8994->aif1clk_disable = 0;
1303 }
1304 if (wm8994->aif2clk_disable) {
c8fdc1b5 1305 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1306 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1307 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1308 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1309 wm8994->aif2clk_disable = 0;
1310 }
1311 break;
1312 }
1313
1314 return 0;
1315}
1316
04d28681
DP		 1317static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1318 struct snd_kcontrol *kcontrol, int event)
1319{
1320 late_enable_ev(w, kcontrol, event);
1321 return 0;
1322}
1323
b462c6e6
DP		 1324static int micbias_ev(struct snd_soc_dapm_widget *w,
1325 struct snd_kcontrol *kcontrol, int event)
1326{
1327 late_enable_ev(w, kcontrol, event);
1328 return 0;
1329}
1330
c52fd021
DP		 1331static int dac_ev(struct snd_soc_dapm_widget *w,
1332 struct snd_kcontrol *kcontrol, int event)
1333{
1334 struct snd_soc_codec *codec = w->codec;
1335 unsigned int mask = 1 << w->shift;
1336
1337 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1338 mask, mask);
1339 return 0;
1340}
1341
9e6e96a1
MB		 1342static const char *adc_mux_text[] = {
1343 "ADC",
1344 "DMIC",
1345};
1346
e61a35b7
TI		 1347static SOC_ENUM_SINGLE_DECL(adc_enum,
1348 0, 0, adc_mux_text);
9e6e96a1
MB		 1349
1350static const struct snd_kcontrol_new adcl_mux =
1351 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1352
1353static const struct snd_kcontrol_new adcr_mux =
1354 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1355
1356static const struct snd_kcontrol_new left_speaker_mixer[] = {
1357SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1358SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1359SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1360SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1361SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1362};
1363
1364static const struct snd_kcontrol_new right_speaker_mixer[] = {
1365SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1366SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1367SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1368SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1369SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1370};
1371
1372/* Debugging; dump chip status after DAPM transitions */
1373static int post_ev(struct snd_soc_dapm_widget *w,
1374 struct snd_kcontrol *kcontrol, int event)
1375{
1376 struct snd_soc_codec *codec = w->codec;
1377 dev_dbg(codec->dev, "SRC status: %x\n",
1378 snd_soc_read(codec,
1379 WM8994_RATE_STATUS));
1380 return 0;
1381}
1382
1383static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1384SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1385 1, 1, 0),
1386SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1387 0, 1, 0),
1388};
1389
1390static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1391SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1392 1, 1, 0),
1393SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1394 0, 1, 0),
1395};
1396
a3257ba8
MB		 1397static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1398SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1399 1, 1, 0),
1400SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1401 0, 1, 0),
1402};
1403
1404static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1405SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1406 1, 1, 0),
1407SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1408 0, 1, 0),
1409};
1410
9e6e96a1
MB		 1411static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1412SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 5, 1, 0),
1414SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1415 4, 1, 0),
1416SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1417 2, 1, 0),
1418SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1419 1, 1, 0),
1420SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1421 0, 1, 0),
1422};
1423
1424static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1425SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 5, 1, 0),
1427SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1428 4, 1, 0),
1429SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1430 2, 1, 0),
1431SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1432 1, 1, 0),
1433SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1434 0, 1, 0),
1435};
1436
1437#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
6e06509c 1438 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
ed6a2772 1439 snd_soc_dapm_get_volsw, wm8994_put_class_w)
9e6e96a1
MB		 1440
1441static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1442 struct snd_ctl_elem_value *ucontrol)
1443{
eee5d7f9 1444 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
9e6e96a1
MB		 1445 int ret;
1446
1447 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1448
c340304d 1449 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1450
1451 return ret;
1452}
1453
1454static const struct snd_kcontrol_new dac1l_mix[] = {
1455WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 5, 1, 0),
1457WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 4, 1, 0),
1459WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 2, 1, 0),
1461WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1462 1, 1, 0),
1463WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1464 0, 1, 0),
1465};
1466
1467static const struct snd_kcontrol_new dac1r_mix[] = {
1468WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 5, 1, 0),
1470WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 4, 1, 0),
1472WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 2, 1, 0),
1474WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1475 1, 1, 0),
1476WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1477 0, 1, 0),
1478};
1479
1480static const char *sidetone_text[] = {
1481 "ADC/DMIC1", "DMIC2",
1482};
1483
e61a35b7
TI		 1484static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1485 WM8994_SIDETONE, 0, sidetone_text);
9e6e96a1
MB		 1486
1487static const struct snd_kcontrol_new sidetone1_mux =
1488 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1489
e61a35b7
TI		 1490static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1491 WM8994_SIDETONE, 1, sidetone_text);
9e6e96a1
MB		 1492
1493static const struct snd_kcontrol_new sidetone2_mux =
1494 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1495
1496static const char *aif1dac_text[] = {
1497 "AIF1DACDAT", "AIF3DACDAT",
1498};
1499
50941968
MB		 1500static const char *loopback_text[] = {
1501 "None", "ADCDAT",
1502};
1503
e61a35b7
TI		 1504static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1505 WM8994_AIF1_CONTROL_2,
1506 WM8994_AIF1_LOOPBACK_SHIFT,
1507 loopback_text);
50941968
MB		 1508
1509static const struct snd_kcontrol_new aif1_loopback =
1510 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1511
e61a35b7
TI		 1512static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1513 WM8994_AIF2_CONTROL_2,
1514 WM8994_AIF2_LOOPBACK_SHIFT,
1515 loopback_text);
50941968
MB		 1516
1517static const struct snd_kcontrol_new aif2_loopback =
1518 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1519
e61a35b7
TI		 1520static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1521 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
9e6e96a1
MB		 1522
1523static const struct snd_kcontrol_new aif1dac_mux =
1524 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1525
1526static const char *aif2dac_text[] = {
1527 "AIF2DACDAT", "AIF3DACDAT",
1528};
1529
e61a35b7
TI		 1530static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1531 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
9e6e96a1
MB		 1532
1533static const struct snd_kcontrol_new aif2dac_mux =
1534 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1535
1536static const char *aif2adc_text[] = {
1537 "AIF2ADCDAT", "AIF3DACDAT",
1538};
1539
e61a35b7
TI		 1540static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1541 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
9e6e96a1
MB		 1542
1543static const struct snd_kcontrol_new aif2adc_mux =
1544 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1545
1546static const char *aif3adc_text[] = {
c4431df0 1547 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1548};
1549
e61a35b7
TI		 1550static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1551 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
9e6e96a1 1552
c4431df0
MB		 1553static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1554 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1555
e61a35b7
TI		 1556static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1557 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
c4431df0
MB		 1558
1559static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1560 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1561
1562static const char *mono_pcm_out_text[] = {
c1a4ecd9 1563 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1564};
1565
e61a35b7
TI		 1566static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1567 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
c4431df0
MB		 1568
1569static const struct snd_kcontrol_new mono_pcm_out_mux =
1570 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1571
1572static const char *aif2dac_src_text[] = {
1573 "AIF2", "AIF3",
1574};
1575
1576/* Note that these two control shouldn't be simultaneously switched to AIF3 */
e61a35b7
TI		 1577static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1578 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
c4431df0
MB		 1579
1580static const struct snd_kcontrol_new aif2dacl_src_mux =
1581 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1582
e61a35b7
TI		 1583static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1584 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
c4431df0
MB		 1585
1586static const struct snd_kcontrol_new aif2dacr_src_mux =
1587 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1588
173efa09 1589static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1590SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1591 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1592SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1594
1595SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1597SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1599SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1601SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1602 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1603SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1604 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1605
1606SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1607 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1608 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1609SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1610 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1612SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1613 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1614SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1615 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1616
1617SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1618};
1619
1620static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1621SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1623 SND_SOC_DAPM_PRE_PMD),
1a38336b 1624SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1625 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1626 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1627SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1628SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1629 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1630SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1631 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1632SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1633SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1634};
1635
c52fd021
DP		 1636static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1637SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1638 dac_ev, SND_SOC_DAPM_PRE_PMU),
1639SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1640 dac_ev, SND_SOC_DAPM_PRE_PMU),
1641SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1642 dac_ev, SND_SOC_DAPM_PRE_PMU),
1643SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1644 dac_ev, SND_SOC_DAPM_PRE_PMU),
1645};
1646
1647static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1648SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1649SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1650SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1651SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1652};
1653
04d28681 1654static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1655SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1656 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1657SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1658 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1659};
1660
1661static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1662SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1663SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1664};
1665
9e6e96a1
MB		 1666static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1667SND_SOC_DAPM_INPUT("DMIC1DAT"),
1668SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1669SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1670
b462c6e6
DP		 1671SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1672 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1673SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1674 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1675
9e6e96a1 1676SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1677 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1678 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1679
1a38336b
MB		 1680SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1681SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1682SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1683
7f94de48 1684SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1685 0, SND_SOC_NOPM, 9, 0),
7f94de48 1686SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1687 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1688SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1689 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1690 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1691SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1692 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1694
7f94de48 1695SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1696 0, SND_SOC_NOPM, 11, 0),
7f94de48 1697SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1698 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1699SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1700 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1701 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1702SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1703 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1704 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1705
1706SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1707 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1708SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1709 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1710
a3257ba8
MB		 1711SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1712 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1713SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1714 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1715
9e6e96a1
MB		 1716SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1717 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1718SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1719 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1720
1721SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1722SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1723
1724SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1725 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1726SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1727 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1728
1729SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1730 SND_SOC_NOPM, 13, 0),
9e6e96a1 1731SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1732 SND_SOC_NOPM, 12, 0),
d6addcc9 1733SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1734 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1735 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1736SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1737 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1738 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1739
5567d8c6
MB		 1740SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1743SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1744
1745SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1746SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1747SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1748
5567d8c6
MB		 1749SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1751
1752SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1753
1754SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1755SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1756SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1757SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1758
1759/* Power is done with the muxes since the ADC power also controls the
1760 * downsampling chain, the chip will automatically manage the analogue
1761 * specific portions.
1762 */
1763SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1764SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1765
50941968
MB		 1766SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1767SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1768
9e6e96a1
MB		 1769SND_SOC_DAPM_POST("Debug log", post_ev),
1770};
1771
c4431df0
MB		 1772static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1773SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1774};
9e6e96a1 1775
c4431df0 1776static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1777SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1778SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1779SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1780SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1781SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1782};
1783
1784static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1785 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1786 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1787
1788 { "DSP1CLK", NULL, "CLK_SYS" },
1789 { "DSP2CLK", NULL, "CLK_SYS" },
1790 { "DSPINTCLK", NULL, "CLK_SYS" },
1791
1792 { "AIF1ADC1L", NULL, "AIF1CLK" },
1793 { "AIF1ADC1L", NULL, "DSP1CLK" },
1794 { "AIF1ADC1R", NULL, "AIF1CLK" },
1795 { "AIF1ADC1R", NULL, "DSP1CLK" },
1796 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1797
1798 { "AIF1DAC1L", NULL, "AIF1CLK" },
1799 { "AIF1DAC1L", NULL, "DSP1CLK" },
1800 { "AIF1DAC1R", NULL, "AIF1CLK" },
1801 { "AIF1DAC1R", NULL, "DSP1CLK" },
1802 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1803
1804 { "AIF1ADC2L", NULL, "AIF1CLK" },
1805 { "AIF1ADC2L", NULL, "DSP1CLK" },
1806 { "AIF1ADC2R", NULL, "AIF1CLK" },
1807 { "AIF1ADC2R", NULL, "DSP1CLK" },
1808 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1809
1810 { "AIF1DAC2L", NULL, "AIF1CLK" },
1811 { "AIF1DAC2L", NULL, "DSP1CLK" },
1812 { "AIF1DAC2R", NULL, "AIF1CLK" },
1813 { "AIF1DAC2R", NULL, "DSP1CLK" },
1814 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1815
1816 { "AIF2ADCL", NULL, "AIF2CLK" },
1817 { "AIF2ADCL", NULL, "DSP2CLK" },
1818 { "AIF2ADCR", NULL, "AIF2CLK" },
1819 { "AIF2ADCR", NULL, "DSP2CLK" },
1820 { "AIF2ADCR", NULL, "DSPINTCLK" },
1821
1822 { "AIF2DACL", NULL, "AIF2CLK" },
1823 { "AIF2DACL", NULL, "DSP2CLK" },
1824 { "AIF2DACR", NULL, "AIF2CLK" },
1825 { "AIF2DACR", NULL, "DSP2CLK" },
1826 { "AIF2DACR", NULL, "DSPINTCLK" },
1827
1828 { "DMIC1L", NULL, "DMIC1DAT" },
1829 { "DMIC1L", NULL, "CLK_SYS" },
1830 { "DMIC1R", NULL, "DMIC1DAT" },
1831 { "DMIC1R", NULL, "CLK_SYS" },
1832 { "DMIC2L", NULL, "DMIC2DAT" },
1833 { "DMIC2L", NULL, "CLK_SYS" },
1834 { "DMIC2R", NULL, "DMIC2DAT" },
1835 { "DMIC2R", NULL, "CLK_SYS" },
1836
1837 { "ADCL", NULL, "AIF1CLK" },
1838 { "ADCL", NULL, "DSP1CLK" },
1839 { "ADCL", NULL, "DSPINTCLK" },
1840
1841 { "ADCR", NULL, "AIF1CLK" },
1842 { "ADCR", NULL, "DSP1CLK" },
1843 { "ADCR", NULL, "DSPINTCLK" },
1844
1845 { "ADCL Mux", "ADC", "ADCL" },
1846 { "ADCL Mux", "DMIC", "DMIC1L" },
1847 { "ADCR Mux", "ADC", "ADCR" },
1848 { "ADCR Mux", "DMIC", "DMIC1R" },
1849
1850 { "DAC1L", NULL, "AIF1CLK" },
1851 { "DAC1L", NULL, "DSP1CLK" },
1852 { "DAC1L", NULL, "DSPINTCLK" },
1853
1854 { "DAC1R", NULL, "AIF1CLK" },
1855 { "DAC1R", NULL, "DSP1CLK" },
1856 { "DAC1R", NULL, "DSPINTCLK" },
1857
1858 { "DAC2L", NULL, "AIF2CLK" },
1859 { "DAC2L", NULL, "DSP2CLK" },
1860 { "DAC2L", NULL, "DSPINTCLK" },
1861
1862 { "DAC2R", NULL, "AIF2DACR" },
1863 { "DAC2R", NULL, "AIF2CLK" },
1864 { "DAC2R", NULL, "DSP2CLK" },
1865 { "DAC2R", NULL, "DSPINTCLK" },
1866
1867 { "TOCLK", NULL, "CLK_SYS" },
1868
5567d8c6
MB		 1869 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1870 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1871 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1872
1873 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1874 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1875 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1876
9e6e96a1
MB		 1877 /* AIF1 outputs */
1878 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1879 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1880 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1881
1882 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1883 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1884 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1885
a3257ba8
MB		 1886 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1887 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1888 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1889
1890 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1891 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1892 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1893
9e6e96a1
MB		 1894 /* Pin level routing for AIF3 */
1895 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1896 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1897 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1898 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1899
50941968 1900 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
9e6e96a1 1901 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
50941968 1902 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
9e6e96a1
MB		 1903 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1904 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1905 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1906 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1907
1908 /* DAC1 inputs */
9e6e96a1
MB		 1909 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1910 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1911 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1912 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1913 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1914
9e6e96a1
MB		 1915 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1916 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1917 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1918 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1919 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1920
1921 /* DAC2/AIF2 outputs */
1922 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1923 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1924 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1925 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1926 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1927 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1928
1929 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1930 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1931 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1932 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1933 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1934 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1935
7f94de48
MB		 1936 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1937 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1938 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1939 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1940
9e6e96a1
MB		 1941 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1942
1943 /* AIF3 output */
1944 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1945 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1946 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1947 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1948 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1949 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1950 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1951 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1952
50941968
MB		 1953 /* Loopback */
1954 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1955 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1956 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1957 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1958
9e6e96a1
MB		 1959 /* Sidetone */
1960 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1961 { "Left Sidetone", "DMIC2", "DMIC2L" },
1962 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1963 { "Right Sidetone", "DMIC2", "DMIC2R" },
1964
1965 /* Output stages */
1966 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1967 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1968
1969 { "SPKL", "DAC1 Switch", "DAC1L" },
1970 { "SPKL", "DAC2 Switch", "DAC2L" },
1971
1972 { "SPKR", "DAC1 Switch", "DAC1R" },
1973 { "SPKR", "DAC2 Switch", "DAC2R" },
1974
1975 { "Left Headphone Mux", "DAC", "DAC1L" },
1976 { "Right Headphone Mux", "DAC", "DAC1R" },
1977};
1978
173efa09
DP		 1979static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1980 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1981 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1982 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1983 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1984 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1985 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1986 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1987 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1988};
1989
1990static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1991 { "DAC1L", NULL, "DAC1L Mixer" },
1992 { "DAC1R", NULL, "DAC1R Mixer" },
1993 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1994 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1995};
1996
6ed8f148
MB		 1997static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1998 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1999 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
2000 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2001 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 2002 { "MICBIAS1", NULL, "CLK_SYS" },
2003 { "MICBIAS1", NULL, "MICBIAS Supply" },
2004 { "MICBIAS2", NULL, "CLK_SYS" },
2005 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 2006};
2007
c4431df0
MB		 2008static const struct snd_soc_dapm_route wm8994_intercon[] = {
2009 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2010 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 2011 { "MICBIAS1", NULL, "VMID" },
2012 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 2013};
2014
2015static const struct snd_soc_dapm_route wm8958_intercon[] = {
2016 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2017 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2018
2019 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2020 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2021 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2022 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2023
8c5b842b
MB		 2024 { "AIF3DACDAT", NULL, "AIF3" },
2025 { "AIF3ADCDAT", NULL, "AIF3" },
2026
c4431df0
MB		 2027 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2028 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2029
2030 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2031};
2032
9e6e96a1
MB		 2033/* The size in bits of the FLL divide multiplied by 10
2034 * to allow rounding later */
2035#define FIXED_FLL_SIZE ((1 << 16) * 10)
2036
2037struct fll_div {
2038 u16 outdiv;
2039 u16 n;
2040 u16 k;
d1a0a299 2041 u16 lambda;
9e6e96a1
MB		 2042 u16 clk_ref_div;
2043 u16 fll_fratio;
2044};
2045
d1a0a299 2046static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
9e6e96a1
MB		 2047 int freq_in, int freq_out)
2048{
2049 u64 Kpart;
d1a0a299 2050 unsigned int K, Ndiv, Nmod, gcd_fll;
9e6e96a1
MB		 2051
2052 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2053
2054 /* Scale the input frequency down to <= 13.5MHz */
2055 fll->clk_ref_div = 0;
2056 while (freq_in > 13500000) {
2057 fll->clk_ref_div++;
2058 freq_in /= 2;
2059
2060 if (fll->clk_ref_div > 3)
2061 return -EINVAL;
2062 }
2063 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2064
2065 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2066 fll->outdiv = 3;
2067 while (freq_out * (fll->outdiv + 1) < 90000000) {
2068 fll->outdiv++;
2069 if (fll->outdiv > 63)
2070 return -EINVAL;
2071 }
2072 freq_out *= fll->outdiv + 1;
2073 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2074
2075 if (freq_in > 1000000) {
2076 fll->fll_fratio = 0;
7d48a6ac
MB		 2077 } else if (freq_in > 256000) {
2078 fll->fll_fratio = 1;
2079 freq_in *= 2;
2080 } else if (freq_in > 128000) {
2081 fll->fll_fratio = 2;
2082 freq_in *= 4;
2083 } else if (freq_in > 64000) {
9e6e96a1
MB		 2084 fll->fll_fratio = 3;
2085 freq_in *= 8;
7d48a6ac
MB		 2086 } else {
2087 fll->fll_fratio = 4;
2088 freq_in *= 16;
9e6e96a1
MB		 2089 }
2090 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2091
2092 /* Now, calculate N.K */
2093 Ndiv = freq_out / freq_in;
2094
2095 fll->n = Ndiv;
2096 Nmod = freq_out % freq_in;
2097 pr_debug("Nmod=%d\n", Nmod);
2098
d1a0a299
MB		 2099 switch (control->type) {
2100 case WM8994:
2101 /* Calculate fractional part - scale up so we can round. */
2102 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
9e6e96a1 2103
d1a0a299 2104 do_div(Kpart, freq_in);
9e6e96a1 2105
d1a0a299 2106 K = Kpart & 0xFFFFFFFF;
9e6e96a1 2107
d1a0a299
MB		 2108 if ((K % 10) >= 5)
2109 K += 5;
9e6e96a1 2110
d1a0a299
MB		 2111 /* Move down to proper range now rounding is done */
2112 fll->k = K / 10;
f7dbd399 2113 fll->lambda = 0;
9e6e96a1 2114
d1a0a299 2115 pr_debug("N=%x K=%x\n", fll->n, fll->k);
571ab6c6 2116 break;
9e6e96a1 2117
d1a0a299
MB		 2118 default:
2119 gcd_fll = gcd(freq_out, freq_in);
9e6e96a1 2120
d1a0a299
MB		 2121 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2122 fll->lambda = freq_in / gcd_fll;
2123
2124 }
9e6e96a1
MB		 2125
2126 return 0;
2127}
2128
f0fba2ad 2129static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2130 unsigned int freq_in, unsigned int freq_out)
2131{
b2c812e2 2132 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2133 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2134 int reg_offset, ret;
2135 struct fll_div fll;
e413ba88 2136 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2137 unsigned long timeout;
4b7ed83a 2138 bool was_enabled;
9e6e96a1 2139
9e6e96a1
MB		 2140 switch (id) {
2141 case WM8994_FLL1:
2142 reg_offset = 0;
2143 id = 0;
e413ba88 2144 aif_src = 0x10;
9e6e96a1
MB		 2145 break;
2146 case WM8994_FLL2:
2147 reg_offset = 0x20;
2148 id = 1;
e413ba88 2149 aif_src = 0x18;
9e6e96a1
MB		 2150 break;
2151 default:
2152 return -EINVAL;
2153 }
2154
4b7ed83a
MB		 2155 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2156 was_enabled = reg & WM8994_FLL1_ENA;
2157
136ff2a2 2158 switch (src) {
7add84aa
MB		 2159 case 0:
2160 /* Allow no source specification when stopping */
2161 if (freq_out)
2162 return -EINVAL;
4514e899 2163 src = wm8994->fll[id].src;
7add84aa 2164 break;
136ff2a2
MB		 2165 case WM8994_FLL_SRC_MCLK1:
2166 case WM8994_FLL_SRC_MCLK2:
2167 case WM8994_FLL_SRC_LRCLK:
2168 case WM8994_FLL_SRC_BCLK:
2169 break;
fbfe6983
MB		 2170 case WM8994_FLL_SRC_INTERNAL:
2171 freq_in = 12000000;
2172 freq_out = 12000000;
2173 break;
136ff2a2
MB		 2174 default:
2175 return -EINVAL;
2176 }
2177
9e6e96a1
MB		 2178 /* Are we changing anything? */
2179 if (wm8994->fll[id].src == src &&
2180 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2181 return 0;
2182
2183 /* If we're stopping the FLL redo the old config - no
2184 * registers will actually be written but we avoid GCC flow
2185 * analysis bugs spewing warnings.
2186 */
2187 if (freq_out)
d1a0a299 2188 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
9e6e96a1 2189 else
d1a0a299 2190 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
9e6e96a1
MB		 2191 wm8994->fll[id].out);
2192 if (ret < 0)
2193 return ret;
2194
e413ba88
MB		 2195 /* Make sure that we're not providing SYSCLK right now */
2196 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2197 if (clk1 & WM8994_SYSCLK_SRC)
2198 aif_reg = WM8994_AIF2_CLOCKING_1;
2199 else
2200 aif_reg = WM8994_AIF1_CLOCKING_1;
2201 reg = snd_soc_read(codec, aif_reg);
2202
2203 if ((reg & WM8994_AIF1CLK_ENA) &&
2204 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2205 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2206 id + 1);
2207 return -EBUSY;
2208 }
9e6e96a1
MB		 2209
2210 /* We always need to disable the FLL while reconfiguring */
2211 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2212 WM8994_FLL1_ENA, 0);
2213
20dc24a9 2214 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2215 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2216 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2217 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2218 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2219 goto out;
2220 }
2221
9e6e96a1
MB		 2222 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2223 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2225 WM8994_FLL1_OUTDIV_MASK |
2226 WM8994_FLL1_FRATIO_MASK, reg);
2227
b16db745
MB		 2228 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2229 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2230
2231 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2232 WM8994_FLL1_N_MASK,
7435d4ee 2233 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1 2234
d1a0a299
MB		 2235 if (fll.lambda) {
2236 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2237 WM8958_FLL1_LAMBDA_MASK,
2238 fll.lambda);
2239 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2240 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2241 } else {
2242 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2243 WM8958_FLL1_EFS_ENA, 0);
2244 }
2245
9e6e96a1 2246 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2247 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2248 WM8994_FLL1_REFCLK_DIV_MASK |
2249 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2250 ((src == WM8994_FLL_SRC_INTERNAL)
2251 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2252 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2253 (src - 1));
9e6e96a1 2254
f0f5039c
MB		 2255 /* Clear any pending completion from a previous failure */
2256 try_wait_for_completion(&wm8994->fll_locked[id]);
2257
9e6e96a1
MB		 2258 /* Enable (with fractional mode if required) */
2259 if (freq_out) {
4b7ed83a
MB		 2260 /* Enable VMID if we need it */
2261 if (!was_enabled) {
af6b6fe4
MB		 2262 active_reference(codec);
2263
4b7ed83a
MB		 2264 switch (control->type) {
2265 case WM8994:
2266 vmid_reference(codec);
2267 break;
2268 case WM8958:
da445afe 2269 if (control->revision < 1)
4b7ed83a
MB		 2270 vmid_reference(codec);
2271 break;
2272 default:
2273 break;
2274 }
2275 }
2276
fbfe6983
MB		 2277 reg = WM8994_FLL1_ENA;
2278
9e6e96a1 2279 if (fll.k)
fbfe6983
MB		 2280 reg |= WM8994_FLL1_FRAC;
2281 if (src == WM8994_FLL_SRC_INTERNAL)
2282 reg |= WM8994_FLL1_OSC_ENA;
2283
9e6e96a1 2284 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2285 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2286 WM8994_FLL1_FRAC, reg);
8e9ddf81 2287
c7ebf932
MB		 2288 if (wm8994->fll_locked_irq) {
2289 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2290 msecs_to_jiffies(10));
2291 if (timeout == 0)
2292 dev_warn(codec->dev,
2293 "Timed out waiting for FLL lock\n");
2294 } else {
2295 msleep(5);
2296 }
4b7ed83a
MB		 2297 } else {
2298 if (was_enabled) {
2299 switch (control->type) {
2300 case WM8994:
2301 vmid_dereference(codec);
2302 break;
2303 case WM8958:
da445afe 2304 if (control->revision < 1)
4b7ed83a
MB		 2305 vmid_dereference(codec);
2306 break;
2307 default:
2308 break;
2309 }
af6b6fe4
MB		 2310
2311 active_dereference(codec);
4b7ed83a 2312 }
9e6e96a1
MB		 2313 }
2314
20dc24a9 2315out:
9e6e96a1
MB		 2316 wm8994->fll[id].in = freq_in;
2317 wm8994->fll[id].out = freq_out;
136ff2a2 2318 wm8994->fll[id].src = src;
9e6e96a1 2319
9e6e96a1
MB		 2320 configure_clock(codec);
2321
cd22000a
MB		 2322 /*
2323 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2324 * for detection.
2325 */
2326 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2327 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2328
2329 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2330 & WM8994_AIF1CLK_RATE_MASK;
2331 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2332 & WM8994_AIF1CLK_RATE_MASK;
2333
cd22000a
MB		 2334 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2335 WM8994_AIF1CLK_RATE_MASK, 0x1);
2336 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2337 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2338 } else if (wm8994->aifdiv[0]) {
2339 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2340 WM8994_AIF1CLK_RATE_MASK,
2341 wm8994->aifdiv[0]);
2342 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2343 WM8994_AIF2CLK_RATE_MASK,
2344 wm8994->aifdiv[1]);
2345
2346 wm8994->aifdiv[0] = 0;
2347 wm8994->aifdiv[1] = 0;
cd22000a
MB		 2348 }
2349
9e6e96a1
MB		 2350 return 0;
2351}
2352
c7ebf932
MB		 2353static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2354{
2355 struct completion *completion = data;
2356
2357 complete(completion);
2358
2359 return IRQ_HANDLED;
2360}
f0fba2ad 2361
66b47fdb
MB		 2362static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2363
f0fba2ad
LG		 2364static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2365 unsigned int freq_in, unsigned int freq_out)
2366{
2367 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2368}
2369
9e6e96a1
MB		 2370static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2371 int clk_id, unsigned int freq, int dir)
2372{
2373 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2374 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2375 int i;
9e6e96a1
MB		 2376
2377 switch (dai->id) {
2378 case 1:
2379 case 2:
2380 break;
2381
2382 default:
2383 /* AIF3 shares clocking with AIF1/2 */
2384 return -EINVAL;
2385 }
2386
2387 switch (clk_id) {
2388 case WM8994_SYSCLK_MCLK1:
2389 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2390 wm8994->mclk[0] = freq;
2391 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2392 dai->id, freq);
2393 break;
2394
2395 case WM8994_SYSCLK_MCLK2:
2396 /* TODO: Set GPIO AF */
2397 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2398 wm8994->mclk[1] = freq;
2399 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2400 dai->id, freq);
2401 break;
2402
2403 case WM8994_SYSCLK_FLL1:
2404 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2405 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2406 break;
2407
2408 case WM8994_SYSCLK_FLL2:
2409 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2410 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2411 break;
2412
66b47fdb
MB		 2413 case WM8994_SYSCLK_OPCLK:
2414 /* Special case - a division (times 10) is given and
c1a4ecd9 2415 * no effect on main clocking.
66b47fdb
MB		 2416 */
2417 if (freq) {
2418 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2419 if (opclk_divs[i] == freq)
2420 break;
2421 if (i == ARRAY_SIZE(opclk_divs))
2422 return -EINVAL;
2423 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2424 WM8994_OPCLK_DIV_MASK, i);
2425 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2426 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2427 } else {
2428 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2429 WM8994_OPCLK_ENA, 0);
2430 }
2431
9e6e96a1
MB		 2432 default:
2433 return -EINVAL;
2434 }
2435
2436 configure_clock(codec);
2437
6730049a
MB		 2438 /*
2439 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2440 * for detection.
2441 */
2442 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2443 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2444
2445 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2446 & WM8994_AIF1CLK_RATE_MASK;
2447 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2448 & WM8994_AIF1CLK_RATE_MASK;
2449
6730049a
MB		 2450 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2451 WM8994_AIF1CLK_RATE_MASK, 0x1);
2452 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2453 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2454 } else if (wm8994->aifdiv[0]) {
2455 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2456 WM8994_AIF1CLK_RATE_MASK,
2457 wm8994->aifdiv[0]);
2458 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2459 WM8994_AIF2CLK_RATE_MASK,
2460 wm8994->aifdiv[1]);
2461
2462 wm8994->aifdiv[0] = 0;
2463 wm8994->aifdiv[1] = 0;
6730049a
MB		 2464 }
2465
9e6e96a1
MB		 2466 return 0;
2467}
2468
2469static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2470 enum snd_soc_bias_level level)
2471{
b6b05691 2472 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2473 struct wm8994 *control = wm8994->wm8994;
b6b05691 2474
5f2f3890
MB		 2475 wm_hubs_set_bias_level(codec, level);
2476
9e6e96a1
MB		 2477 switch (level) {
2478 case SND_SOC_BIAS_ON:
2479 break;
2480
2481 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2482 /* MICBIAS into regulating mode */
2483 switch (control->type) {
2484 case WM8958:
2485 case WM1811:
2486 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2487 WM8958_MICB1_MODE, 0);
2488 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2489 WM8958_MICB2_MODE, 0);
2490 break;
2491 default:
2492 break;
2493 }
af6b6fe4
MB		 2494
2495 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2496 active_reference(codec);
9e6e96a1
MB		 2497 break;
2498
2499 case SND_SOC_BIAS_STANDBY:
ce6120cc 2500 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2501 switch (control->type) {
8bc3c2c2 2502 case WM8958:
da445afe 2503 if (control->revision == 0) {
8bc3c2c2 2504 /* Optimise performance for rev A */
8bc3c2c2
MB		 2505 snd_soc_update_bits(codec,
2506 WM8958_CHARGE_PUMP_2,
2507 WM8958_CP_DISCH,
2508 WM8958_CP_DISCH);
2509 }
2510 break;
81204c84 2511
462835e4 2512 default:
81204c84 2513 break;
b6b05691 2514 }
9e6e96a1
MB		 2515
2516 /* Discharge LINEOUT1 & 2 */
2517 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2518 WM8994_LINEOUT1_DISCH |
2519 WM8994_LINEOUT2_DISCH,
2520 WM8994_LINEOUT1_DISCH |
2521 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2522 }
2523
af6b6fe4
MB		 2524 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2525 active_dereference(codec);
2526
500fa30e
MB		 2527 /* MICBIAS into bypass mode on newer devices */
2528 switch (control->type) {
2529 case WM8958:
2530 case WM1811:
2531 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2532 WM8958_MICB1_MODE,
2533 WM8958_MICB1_MODE);
2534 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2535 WM8958_MICB2_MODE,
2536 WM8958_MICB2_MODE);
2537 break;
2538 default:
2539 break;
2540 }
9e6e96a1
MB		 2541 break;
2542
2543 case SND_SOC_BIAS_OFF:
4105ab84 2544 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2545 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2546 break;
2547 }
5f2f3890 2548
ce6120cc 2549 codec->dapm.bias_level = level;
af6b6fe4 2550
22f8d055
MB		 2551 return 0;
2552}
2553
2554int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2555{
2556 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2557
2558 switch (mode) {
2559 case WM8994_VMID_NORMAL:
2560 if (wm8994->hubs.lineout1_se) {
2561 snd_soc_dapm_disable_pin(&codec->dapm,
2562 "LINEOUT1N Driver");
2563 snd_soc_dapm_disable_pin(&codec->dapm,
2564 "LINEOUT1P Driver");
2565 }
2566 if (wm8994->hubs.lineout2_se) {
2567 snd_soc_dapm_disable_pin(&codec->dapm,
2568 "LINEOUT2N Driver");
2569 snd_soc_dapm_disable_pin(&codec->dapm,
2570 "LINEOUT2P Driver");
2571 }
2572
2573 /* Do the sync with the old mode to allow it to clean up */
2574 snd_soc_dapm_sync(&codec->dapm);
2575 wm8994->vmid_mode = mode;
2576 break;
2577
2578 case WM8994_VMID_FORCE:
2579 if (wm8994->hubs.lineout1_se) {
2580 snd_soc_dapm_force_enable_pin(&codec->dapm,
2581 "LINEOUT1N Driver");
2582 snd_soc_dapm_force_enable_pin(&codec->dapm,
2583 "LINEOUT1P Driver");
2584 }
2585 if (wm8994->hubs.lineout2_se) {
2586 snd_soc_dapm_force_enable_pin(&codec->dapm,
2587 "LINEOUT2N Driver");
2588 snd_soc_dapm_force_enable_pin(&codec->dapm,
2589 "LINEOUT2P Driver");
2590 }
2591
2592 wm8994->vmid_mode = mode;
2593 snd_soc_dapm_sync(&codec->dapm);
2594 break;
2595
2596 default:
2597 return -EINVAL;
2598 }
2599
9e6e96a1
MB		 2600 return 0;
2601}
2602
2603static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2604{
2605 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2606 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2607 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2608 int ms_reg;
2609 int aif1_reg;
435705e8
MB		 2610 int dac_reg;
2611 int adc_reg;
9e6e96a1
MB		 2612 int ms = 0;
2613 int aif1 = 0;
435705e8 2614 int lrclk = 0;
9e6e96a1
MB		 2615
2616 switch (dai->id) {
2617 case 1:
2618 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2619 aif1_reg = WM8994_AIF1_CONTROL_1;
435705e8
MB		 2620 dac_reg = WM8994_AIF1DAC_LRCLK;
2621 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2622 break;
2623 case 2:
2624 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2625 aif1_reg = WM8994_AIF2_CONTROL_1;
435705e8
MB		 2626 dac_reg = WM8994_AIF1DAC_LRCLK;
2627 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2628 break;
2629 default:
2630 return -EINVAL;
2631 }
2632
2633 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2634 case SND_SOC_DAIFMT_CBS_CFS:
2635 break;
2636 case SND_SOC_DAIFMT_CBM_CFM:
2637 ms = WM8994_AIF1_MSTR;
2638 break;
2639 default:
2640 return -EINVAL;
2641 }
2642
2643 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2644 case SND_SOC_DAIFMT_DSP_B:
2645 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2646 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2647 case SND_SOC_DAIFMT_DSP_A:
2648 aif1 |= 0x18;
2649 break;
2650 case SND_SOC_DAIFMT_I2S:
2651 aif1 |= 0x10;
2652 break;
2653 case SND_SOC_DAIFMT_RIGHT_J:
2654 break;
2655 case SND_SOC_DAIFMT_LEFT_J:
2656 aif1 |= 0x8;
2657 break;
2658 default:
2659 return -EINVAL;
2660 }
2661
2662 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2663 case SND_SOC_DAIFMT_DSP_A:
2664 case SND_SOC_DAIFMT_DSP_B:
2665 /* frame inversion not valid for DSP modes */
2666 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2667 case SND_SOC_DAIFMT_NB_NF:
2668 break;
2669 case SND_SOC_DAIFMT_IB_NF:
2670 aif1 |= WM8994_AIF1_BCLK_INV;
2671 break;
2672 default:
2673 return -EINVAL;
2674 }
2675 break;
2676
2677 case SND_SOC_DAIFMT_I2S:
2678 case SND_SOC_DAIFMT_RIGHT_J:
2679 case SND_SOC_DAIFMT_LEFT_J:
2680 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2681 case SND_SOC_DAIFMT_NB_NF:
2682 break;
2683 case SND_SOC_DAIFMT_IB_IF:
2684 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
435705e8 2685 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2686 break;
2687 case SND_SOC_DAIFMT_IB_NF:
2688 aif1 |= WM8994_AIF1_BCLK_INV;
2689 break;
2690 case SND_SOC_DAIFMT_NB_IF:
2691 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2692 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2693 break;
2694 default:
2695 return -EINVAL;
2696 }
2697 break;
2698 default:
2699 return -EINVAL;
2700 }
2701
c4431df0
MB		 2702 /* The AIF2 format configuration needs to be mirrored to AIF3
2703 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2704 switch (control->type) {
2705 case WM1811:
2706 case WM8958:
2707 if (dai->id == 2)
2708 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2709 WM8994_AIF1_LRCLK_INV |
2710 WM8958_AIF3_FMT_MASK, aif1);
2711 break;
2712
2713 default:
2714 break;
2715 }
c4431df0 2716
9e6e96a1
MB		 2717 snd_soc_update_bits(codec, aif1_reg,
2718 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2719 WM8994_AIF1_FMT_MASK,
2720 aif1);
2721 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2722 ms);
435705e8
MB		 2723 snd_soc_update_bits(codec, dac_reg,
2724 WM8958_AIF1_LRCLK_INV, lrclk);
2725 snd_soc_update_bits(codec, adc_reg,
2726 WM8958_AIF1_LRCLK_INV, lrclk);
9e6e96a1
MB		 2727
2728 return 0;
2729}
2730
2731static struct {
2732 int val, rate;
2733} srs[] = {
2734 { 0, 8000 },
2735 { 1, 11025 },
2736 { 2, 12000 },
2737 { 3, 16000 },
2738 { 4, 22050 },
2739 { 5, 24000 },
2740 { 6, 32000 },
2741 { 7, 44100 },
2742 { 8, 48000 },
2743 { 9, 88200 },
2744 { 10, 96000 },
2745};
2746
2747static int fs_ratios[] = {
2748 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2749};
2750
2751static int bclk_divs[] = {
2752 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2753 640, 880, 960, 1280, 1760, 1920
2754};
2755
2756static int wm8994_hw_params(struct snd_pcm_substream *substream,
2757 struct snd_pcm_hw_params *params,
2758 struct snd_soc_dai *dai)
2759{
2760 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2761 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3cf956ee
MB		 2762 struct wm8994 *control = wm8994->wm8994;
2763 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1 2764 int aif1_reg;
b1e43d93 2765 int aif2_reg;
9e6e96a1
MB		 2766 int bclk_reg;
2767 int lrclk_reg;
2768 int rate_reg;
2769 int aif1 = 0;
b1e43d93 2770 int aif2 = 0;
9e6e96a1
MB		 2771 int bclk = 0;
2772 int lrclk = 0;
2773 int rate_val = 0;
2774 int id = dai->id - 1;
2775
2776 int i, cur_val, best_val, bclk_rate, best;
2777
2778 switch (dai->id) {
2779 case 1:
2780 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2781 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2782 bclk_reg = WM8994_AIF1_BCLK;
2783 rate_reg = WM8994_AIF1_RATE;
2784 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2785 wm8994->lrclk_shared[0]) {
9e6e96a1 2786 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2787 } else {
9e6e96a1 2788 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2789 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2790 }
9e6e96a1
MB		 2791 break;
2792 case 2:
2793 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2794 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2795 bclk_reg = WM8994_AIF2_BCLK;
2796 rate_reg = WM8994_AIF2_RATE;
2797 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2798 wm8994->lrclk_shared[1]) {
9e6e96a1 2799 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2800 } else {
9e6e96a1 2801 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2802 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2803 }
9e6e96a1
MB		 2804 break;
2805 default:
2806 return -EINVAL;
2807 }
2808
79748cdb 2809 bclk_rate = params_rate(params);
9e6e96a1
MB		 2810 switch (params_format(params)) {
2811 case SNDRV_PCM_FORMAT_S16_LE:
2812 bclk_rate *= 16;
2813 break;
2814 case SNDRV_PCM_FORMAT_S20_3LE:
2815 bclk_rate *= 20;
2816 aif1 |= 0x20;
2817 break;
2818 case SNDRV_PCM_FORMAT_S24_LE:
2819 bclk_rate *= 24;
2820 aif1 |= 0x40;
2821 break;
2822 case SNDRV_PCM_FORMAT_S32_LE:
2823 bclk_rate *= 32;
2824 aif1 |= 0x60;
2825 break;
2826 default:
2827 return -EINVAL;
2828 }
2829
79748cdb 2830 wm8994->channels[id] = params_channels(params);
3cf956ee
MB		 2831 if (pdata->max_channels_clocked[id] &&
2832 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2833 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2834 pdata->max_channels_clocked[id], wm8994->channels[id]);
2835 wm8994->channels[id] = pdata->max_channels_clocked[id];
2836 }
2837
2838 switch (wm8994->channels[id]) {
79748cdb
MB		 2839 case 1:
2840 case 2:
2841 bclk_rate *= 2;
2842 break;
2843 default:
2844 bclk_rate *= 4;
2845 break;
2846 }
2847
9e6e96a1
MB		 2848 /* Try to find an appropriate sample rate; look for an exact match. */
2849 for (i = 0; i < ARRAY_SIZE(srs); i++)
2850 if (srs[i].rate == params_rate(params))
2851 break;
2852 if (i == ARRAY_SIZE(srs))
2853 return -EINVAL;
2854 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2855
2856 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2857 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2858 dai->id, wm8994->aifclk[id], bclk_rate);
2859
3cf956ee 2860 if (wm8994->channels[id] == 1 &&
b1e43d93
MB		 2861 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2862 aif2 |= WM8994_AIF1_MONO;
2863
9e6e96a1
MB		 2864 if (wm8994->aifclk[id] == 0) {
2865 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2866 return -EINVAL;
2867 }
2868
2869 /* AIFCLK/fs ratio; look for a close match in either direction */
2870 best = 0;
2871 best_val = abs((fs_ratios[0] * params_rate(params))
2872 - wm8994->aifclk[id]);
2873 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2874 cur_val = abs((fs_ratios[i] * params_rate(params))
2875 - wm8994->aifclk[id]);
2876 if (cur_val >= best_val)
2877 continue;
2878 best = i;
2879 best_val = cur_val;
2880 }
2881 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2882 dai->id, fs_ratios[best]);
2883 rate_val |= best;
2884
2885 /* We may not get quite the right frequency if using
2886 * approximate clocks so look for the closest match that is
2887 * higher than the target (we need to ensure that there enough
2888 * BCLKs to clock out the samples).
2889 */
2890 best = 0;
2891 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2892 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2893 if (cur_val < 0) /* BCLK table is sorted */
2894 break;
2895 best = i;
2896 }
07cd8ada 2897 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2898 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2899 bclk_divs[best], bclk_rate);
2900 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2901
2902 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2903 if (!lrclk) {
2904 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2905 bclk_rate);
2906 return -EINVAL;
2907 }
9e6e96a1
MB		 2908 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2909 lrclk, bclk_rate / lrclk);
2910
2911 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2912 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2913 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2914 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2915 lrclk);
2916 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2917 WM8994_AIF1CLK_RATE_MASK, rate_val);
2918
2919 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2920 switch (dai->id) {
2921 case 1:
2922 wm8994->dac_rates[0] = params_rate(params);
2923 wm8994_set_retune_mobile(codec, 0);
2924 wm8994_set_retune_mobile(codec, 1);
2925 break;
2926 case 2:
2927 wm8994->dac_rates[1] = params_rate(params);
2928 wm8994_set_retune_mobile(codec, 2);
2929 break;
2930 }
2931 }
2932
2933 return 0;
2934}
2935
c4431df0
MB		 2936static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2937 struct snd_pcm_hw_params *params,
2938 struct snd_soc_dai *dai)
2939{
2940 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2941 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2942 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2943 int aif1_reg;
2944 int aif1 = 0;
2945
2946 switch (dai->id) {
2947 case 3:
2948 switch (control->type) {
81204c84 2949 case WM1811:
c4431df0
MB		 2950 case WM8958:
2951 aif1_reg = WM8958_AIF3_CONTROL_1;
2952 break;
2953 default:
2954 return 0;
2955 }
4495e46f 2956 break;
c4431df0
MB		 2957 default:
2958 return 0;
2959 }
2960
2961 switch (params_format(params)) {
2962 case SNDRV_PCM_FORMAT_S16_LE:
2963 break;
2964 case SNDRV_PCM_FORMAT_S20_3LE:
2965 aif1 |= 0x20;
2966 break;
2967 case SNDRV_PCM_FORMAT_S24_LE:
2968 aif1 |= 0x40;
2969 break;
2970 case SNDRV_PCM_FORMAT_S32_LE:
2971 aif1 |= 0x60;
2972 break;
2973 default:
2974 return -EINVAL;
2975 }
2976
2977 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2978}
2979
9e6e96a1
MB		 2980static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2981{
2982 struct snd_soc_codec *codec = codec_dai->codec;
2983 int mute_reg;
2984 int reg;
2985
2986 switch (codec_dai->id) {
2987 case 1:
2988 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2989 break;
2990 case 2:
2991 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2992 break;
2993 default:
2994 return -EINVAL;
2995 }
2996
2997 if (mute)
2998 reg = WM8994_AIF1DAC1_MUTE;
2999 else
3000 reg = 0;
3001
3002 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3003
3004 return 0;
3005}
3006
778a76e2
MB		 3007static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3008{
3009 struct snd_soc_codec *codec = codec_dai->codec;
3010 int reg, val, mask;
3011
3012 switch (codec_dai->id) {
3013 case 1:
3014 reg = WM8994_AIF1_MASTER_SLAVE;
3015 mask = WM8994_AIF1_TRI;
3016 break;
3017 case 2:
3018 reg = WM8994_AIF2_MASTER_SLAVE;
3019 mask = WM8994_AIF2_TRI;
3020 break;
778a76e2
MB		 3021 default:
3022 return -EINVAL;
3023 }
3024
3025 if (tristate)
3026 val = mask;
3027 else
3028 val = 0;
3029
78b3fb46 3030 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 3031}
3032
d09f3ecf
MB		 3033static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3034{
3035 struct snd_soc_codec *codec = dai->codec;
3036
3037 /* Disable the pulls on the AIF if we're using it to save power. */
3038 snd_soc_update_bits(codec, WM8994_GPIO_3,
3039 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3040 snd_soc_update_bits(codec, WM8994_GPIO_4,
3041 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3042 snd_soc_update_bits(codec, WM8994_GPIO_5,
3043 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3044
3045 return 0;
3046}
3047
9e6e96a1
MB		 3048#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3049
3050#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 3051 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 3052
85e7652d 3053static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 3054 .set_sysclk = wm8994_set_dai_sysclk,
3055 .set_fmt = wm8994_set_dai_fmt,
3056 .hw_params = wm8994_hw_params,
3057 .digital_mute = wm8994_aif_mute,
3058 .set_pll = wm8994_set_fll,
778a76e2 3059 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 3060};
3061
85e7652d 3062static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 3063 .set_sysclk = wm8994_set_dai_sysclk,
3064 .set_fmt = wm8994_set_dai_fmt,
3065 .hw_params = wm8994_hw_params,
3066 .digital_mute = wm8994_aif_mute,
3067 .set_pll = wm8994_set_fll,
778a76e2
MB		 3068 .set_tristate = wm8994_set_tristate,
3069};
3070
85e7652d 3071static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 3072 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 3073};
3074
f0fba2ad 3075static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 3076 {
f0fba2ad 3077 .name = "wm8994-aif1",
8c7f78b3 3078 .id = 1,
9e6e96a1
MB		 3079 .playback = {
3080 .stream_name = "AIF1 Playback",
b1e43d93 3081 .channels_min = 1,
9e6e96a1
MB		 3082 .channels_max = 2,
3083 .rates = WM8994_RATES,
3084 .formats = WM8994_FORMATS,
99b0292d 3085 .sig_bits = 24,
9e6e96a1
MB		 3086 },
3087 .capture = {
3088 .stream_name = "AIF1 Capture",
b1e43d93 3089 .channels_min = 1,
9e6e96a1
MB		 3090 .channels_max = 2,
3091 .rates = WM8994_RATES,
3092 .formats = WM8994_FORMATS,
99b0292d 3093 .sig_bits = 24,
9e6e96a1
MB		 3094 },
3095 .ops = &wm8994_aif1_dai_ops,
3096 },
3097 {
f0fba2ad 3098 .name = "wm8994-aif2",
8c7f78b3 3099 .id = 2,
9e6e96a1
MB		 3100 .playback = {
3101 .stream_name = "AIF2 Playback",
b1e43d93 3102 .channels_min = 1,
9e6e96a1
MB		 3103 .channels_max = 2,
3104 .rates = WM8994_RATES,
3105 .formats = WM8994_FORMATS,
99b0292d 3106 .sig_bits = 24,
9e6e96a1
MB		 3107 },
3108 .capture = {
3109 .stream_name = "AIF2 Capture",
b1e43d93 3110 .channels_min = 1,
9e6e96a1
MB		 3111 .channels_max = 2,
3112 .rates = WM8994_RATES,
3113 .formats = WM8994_FORMATS,
99b0292d 3114 .sig_bits = 24,
9e6e96a1 3115 },
d09f3ecf 3116 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 3117 .ops = &wm8994_aif2_dai_ops,
3118 },
3119 {
f0fba2ad 3120 .name = "wm8994-aif3",
8c7f78b3 3121 .id = 3,
9e6e96a1
MB		 3122 .playback = {
3123 .stream_name = "AIF3 Playback",
b1e43d93 3124 .channels_min = 1,
9e6e96a1
MB		 3125 .channels_max = 2,
3126 .rates = WM8994_RATES,
3127 .formats = WM8994_FORMATS,
99b0292d 3128 .sig_bits = 24,
9e6e96a1 3129 },
a8462bde 3130 .capture = {
9e6e96a1 3131 .stream_name = "AIF3 Capture",
b1e43d93 3132 .channels_min = 1,
9e6e96a1
MB		 3133 .channels_max = 2,
3134 .rates = WM8994_RATES,
3135 .formats = WM8994_FORMATS,
99b0292d
MB		 3136 .sig_bits = 24,
3137 },
778a76e2 3138 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3139 }
3140};
9e6e96a1
MB		 3141
3142#ifdef CONFIG_PM
4752a887 3143static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3144{
b2c812e2 3145 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3146 int i, ret;
3147
3148 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3149 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3150 sizeof(struct wm8994_fll_config));
f0fba2ad 3151 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3152 if (ret < 0)
3153 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3154 i + 1, ret);
3155 }
3156
3157 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3158
3159 return 0;
3160}
3161
4752a887 3162static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3163{
b2c812e2 3164 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3165 int i, ret;
3166
9e6e96a1 3167 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3168 if (!wm8994->fll_suspend[i].out)
3169 continue;
3170
f0fba2ad 3171 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3172 wm8994->fll_suspend[i].src,
3173 wm8994->fll_suspend[i].in,
3174 wm8994->fll_suspend[i].out);
3175 if (ret < 0)
3176 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3177 i + 1, ret);
3178 }
3179
3180 return 0;
3181}
3182#else
4752a887
MB		 3183#define wm8994_codec_suspend NULL
3184#define wm8994_codec_resume NULL
9e6e96a1
MB		 3185#endif
3186
3187static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3188{
8cb8e83b 3189 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3190 struct wm8994 *control = wm8994->wm8994;
3191 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3192 struct snd_kcontrol_new controls[] = {
3193 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3194 wm8994->retune_mobile_enum,
3195 wm8994_get_retune_mobile_enum,
3196 wm8994_put_retune_mobile_enum),
3197 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3198 wm8994->retune_mobile_enum,
3199 wm8994_get_retune_mobile_enum,
3200 wm8994_put_retune_mobile_enum),
3201 SOC_ENUM_EXT("AIF2 EQ Mode",
3202 wm8994->retune_mobile_enum,
3203 wm8994_get_retune_mobile_enum,
3204 wm8994_put_retune_mobile_enum),
3205 };
3206 int ret, i, j;
3207 const char **t;
3208
3209 /* We need an array of texts for the enum API but the number
3210 * of texts is likely to be less than the number of
3211 * configurations due to the sample rate dependency of the
3212 * configurations. */
3213 wm8994->num_retune_mobile_texts = 0;
3214 wm8994->retune_mobile_texts = NULL;
3215 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3216 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3217 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3218 wm8994->retune_mobile_texts[j]) == 0)
3219 break;
3220 }
3221
3222 if (j != wm8994->num_retune_mobile_texts)
3223 continue;
3224
3225 /* Expand the array... */
3226 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3227 sizeof(char *) *
9e6e96a1
MB		 3228 (wm8994->num_retune_mobile_texts + 1),
3229 GFP_KERNEL);
3230 if (t == NULL)
3231 continue;
3232
3233 /* ...store the new entry... */
c1a4ecd9 3234 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3235 pdata->retune_mobile_cfgs[i].name;
3236
3237 /* ...and remember the new version. */
3238 wm8994->num_retune_mobile_texts++;
3239 wm8994->retune_mobile_texts = t;
3240 }
3241
3242 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3243 wm8994->num_retune_mobile_texts);
3244
3245 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3246 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3247
8cb8e83b 3248 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3249 ARRAY_SIZE(controls));
3250 if (ret != 0)
8cb8e83b 3251 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3252 "Failed to add ReTune Mobile controls: %d\n", ret);
3253}
3254
3255static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3256{
8cb8e83b 3257 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3258 struct wm8994 *control = wm8994->wm8994;
3259 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3260 int ret, i;
3261
3262 if (!pdata)
3263 return;
3264
3265 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3266 pdata->lineout2_diff,
3267 pdata->lineout1fb,
3268 pdata->lineout2fb,
3269 pdata->jd_scthr,
3270 pdata->jd_thr,
02e79476
MB		 3271 pdata->micb1_delay,
3272 pdata->micb2_delay,
9e6e96a1
MB		 3273 pdata->micbias1_lvl,
3274 pdata->micbias2_lvl);
3275
3276 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3277
3278 if (pdata->num_drc_cfgs) {
3279 struct snd_kcontrol_new controls[] = {
3280 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3281 wm8994_get_drc_enum, wm8994_put_drc_enum),
3282 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3283 wm8994_get_drc_enum, wm8994_put_drc_enum),
3284 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3285 wm8994_get_drc_enum, wm8994_put_drc_enum),
3286 };
3287
3288 /* We need an array of texts for the enum API */
8cb8e83b 3289 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3290 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3291 if (!wm8994->drc_texts) {
8cb8e83b 3292 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3293 "Failed to allocate %d DRC config texts\n",
3294 pdata->num_drc_cfgs);
3295 return;
3296 }
3297
3298 for (i = 0; i < pdata->num_drc_cfgs; i++)
3299 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3300
3301 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3302 wm8994->drc_enum.texts = wm8994->drc_texts;
3303
8cb8e83b 3304 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3305 ARRAY_SIZE(controls));
9e6e96a1
MB		 3306 for (i = 0; i < WM8994_NUM_DRC; i++)
3307 wm8994_set_drc(codec, i);
45a690f6
MB		 3308 } else {
3309 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3310 wm8994_drc_controls,
3311 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3312 }
3313
45a690f6
MB		 3314 if (ret != 0)
3315 dev_err(wm8994->hubs.codec->dev,
3316 "Failed to add DRC mode controls: %d\n", ret);
3317
3318
9e6e96a1
MB		 3319 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3320 pdata->num_retune_mobile_cfgs);
3321
3322 if (pdata->num_retune_mobile_cfgs)
3323 wm8994_handle_retune_mobile_pdata(wm8994);
3324 else
8cb8e83b 3325 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3326 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3327
3328 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3329 if (pdata->micbias[i]) {
3330 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3331 pdata->micbias[i] & 0xffff);
3332 }
3333 }
9e6e96a1
MB		 3334}
3335
88766984
MB		 3336/**
3337 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3338 *
3339 * @codec: WM8994 codec
3340 * @jack: jack to report detection events on
3341 * @micbias: microphone bias to detect on
88766984
MB		 3342 *
3343 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3344 * being used to bring out signals to the processor then only platform
5ab230a7 3345 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3346 * be configured using snd_soc_jack_add_gpios() instead.
3347 *
3348 * Configuration of detection levels is available via the micbias1_lvl
3349 * and micbias2_lvl platform data members.
3350 */
3351int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3352 int micbias)
88766984 3353{
b2c812e2 3354 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3355 struct wm8994_micdet *micdet;
2a8a856d 3356 struct wm8994 *control = wm8994->wm8994;
87092e3c 3357 int reg, ret;
88766984 3358
87092e3c
MB		 3359 if (control->type != WM8994) {
3360 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3361 return -EINVAL;
87092e3c 3362 }
3a423157 3363
88766984
MB		 3364 switch (micbias) {
3365 case 1:
3366 micdet = &wm8994->micdet[0];
87092e3c
MB		 3367 if (jack)
3368 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3369 "MICBIAS1");
3370 else
3371 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3372 "MICBIAS1");
88766984
MB		 3373 break;
3374 case 2:
3375 micdet = &wm8994->micdet[1];
87092e3c
MB		 3376 if (jack)
3377 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3378 "MICBIAS1");
3379 else
3380 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3381 "MICBIAS1");
88766984
MB		 3382 break;
3383 default:
87092e3c 3384 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3385 return -EINVAL;
87092e3c 3386 }
88766984 3387
87092e3c
MB		 3388 if (ret != 0)
3389 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3390 micbias, ret);
3391
3392 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3393 micbias, jack);
88766984
MB		 3394
3395 /* Store the configuration */
3396 micdet->jack = jack;
87092e3c 3397 micdet->detecting = true;
88766984
MB		 3398
3399 /* If either of the jacks is set up then enable detection */
3400 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3401 reg = WM8994_MICD_ENA;
87092e3c 3402 else
88766984
MB		 3403 reg = 0;
3404
3405 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3406
d9f34df7
CR		 3407 /* enable MICDET and MICSHRT deboune */
3408 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3409 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3410 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3411 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3412
87092e3c
MB		 3413 snd_soc_dapm_sync(&codec->dapm);
3414
88766984
MB		 3415 return 0;
3416}
3417EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3418
e9b54de4 3419static void wm8994_mic_work(struct work_struct *work)
88766984 3420{
e9b54de4
MB		 3421 struct wm8994_priv *priv = container_of(work,
3422 struct wm8994_priv,
3423 mic_work.work);
fdfc4f3e
MB		 3424 struct regmap *regmap = priv->wm8994->regmap;
3425 struct device *dev = priv->wm8994->dev;
3426 unsigned int reg;
3427 int ret;
88766984
MB		 3428 int report;
3429
b8176627
MB		 3430 pm_runtime_get_sync(dev);
3431
fdfc4f3e
MB		 3432 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3433 if (ret < 0) {
3434 dev_err(dev, "Failed to read microphone status: %d\n",
3435 ret);
b8176627 3436 pm_runtime_put(dev);
e9b54de4 3437 return;
88766984
MB		 3438 }
3439
fdfc4f3e 3440 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3441
3442 report = 0;
87092e3c
MB		 3443 if (reg & WM8994_MIC1_DET_STS) {
3444 if (priv->micdet[0].detecting)
3445 report = SND_JACK_HEADSET;
3446 }
3447 if (reg & WM8994_MIC1_SHRT_STS) {
3448 if (priv->micdet[0].detecting)
3449 report = SND_JACK_HEADPHONE;
3450 else
3451 report |= SND_JACK_BTN_0;
3452 }
3453 if (report)
3454 priv->micdet[0].detecting = false;
3455 else
3456 priv->micdet[0].detecting = true;
3457
88766984 3458 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3459 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3460
3461 report = 0;
87092e3c
MB		 3462 if (reg & WM8994_MIC2_DET_STS) {
3463 if (priv->micdet[1].detecting)
3464 report = SND_JACK_HEADSET;
3465 }
3466 if (reg & WM8994_MIC2_SHRT_STS) {
3467 if (priv->micdet[1].detecting)
3468 report = SND_JACK_HEADPHONE;
3469 else
3470 report |= SND_JACK_BTN_0;
3471 }
3472 if (report)
3473 priv->micdet[1].detecting = false;
3474 else
3475 priv->micdet[1].detecting = true;
3476
88766984 3477 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3478 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3479
3480 pm_runtime_put(dev);
e9b54de4
MB		 3481}
3482
3483static irqreturn_t wm8994_mic_irq(int irq, void *data)
3484{
3485 struct wm8994_priv *priv = data;
8cb8e83b 3486 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3487
3488#ifndef CONFIG_SND_SOC_WM8994_MODULE
3489 trace_snd_soc_jack_irq(dev_name(codec->dev));
3490#endif
3491
3492 pm_wakeup_event(codec->dev, 300);
3493
68defe58
MB		 3494 queue_delayed_work(system_power_efficient_wq,
3495 &priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3496
3497 return IRQ_HANDLED;
3498}
3499
f02b0de0
MB		 3500static void wm1811_micd_stop(struct snd_soc_codec *codec)
3501{
3502 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3503
3504 if (!wm8994->jackdet)
3505 return;
3506
3507 mutex_lock(&wm8994->accdet_lock);
3508
3509 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3510
3511 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3512
3513 mutex_unlock(&wm8994->accdet_lock);
3514
3515 if (wm8994->wm8994->pdata.jd_ext_cap)
3516 snd_soc_dapm_disable_pin(&codec->dapm,
3517 "MICBIAS2");
3518}
3519
78b76dbe 3520static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3521{
821edd2f 3522 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3523 int report;
821edd2f 3524
78b76dbe
MB		 3525 report = 0;
3526 if (status & 0x4)
3527 report |= SND_JACK_BTN_0;
3528
3529 if (status & 0x8)
3530 report |= SND_JACK_BTN_1;
3531
3532 if (status & 0x10)
3533 report |= SND_JACK_BTN_2;
3534
3535 if (status & 0x20)
3536 report |= SND_JACK_BTN_3;
3537
3538 if (status & 0x40)
3539 report |= SND_JACK_BTN_4;
3540
3541 if (status & 0x80)
3542 report |= SND_JACK_BTN_5;
3543
3544 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3545 wm8994->btn_mask);
3546}
3547
70bd3b29
MB		 3548static void wm8958_open_circuit_work(struct work_struct *work)
3549{
3550 struct wm8994_priv *wm8994 = container_of(work,
3551 struct wm8994_priv,
3552 open_circuit_work.work);
3553 struct device *dev = wm8994->wm8994->dev;
3554
3555 wm1811_micd_stop(wm8994->hubs.codec);
3556
3557 mutex_lock(&wm8994->accdet_lock);
3558
3559 dev_dbg(dev, "Reporting open circuit\n");
3560
3561 wm8994->jack_mic = false;
3562 wm8994->mic_detecting = true;
3563
3564 wm8958_micd_set_rate(wm8994->hubs.codec);
3565
3566 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3567 wm8994->btn_mask |
3568 SND_JACK_HEADSET);
3569
3570 mutex_unlock(&wm8994->accdet_lock);
3571}
3572
98869f68 3573static void wm8958_mic_id(void *data, u16 status)
78b76dbe 3574{
98869f68 3575 struct snd_soc_codec *codec = data;
78b76dbe 3576 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3577
af6b6fe4 3578 /* Either nothing present or just starting detection */
b00adf76 3579 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB		 3580 /* If nothing present then clear our statuses */
3581 dev_dbg(codec->dev, "Detected open circuit\n");
f02b0de0 3582
68defe58
MB		 3583 queue_delayed_work(system_power_efficient_wq,
3584 &wm8994->open_circuit_work,
3585 msecs_to_jiffies(2500));
b00adf76
MB		 3586 return;
3587 }
821edd2f 3588
b00adf76
MB		 3589 /* If the measurement is showing a high impedence we've got a
3590 * microphone.
3591 */
78b76dbe 3592 if (status & 0x600) {
b00adf76
MB		 3593 dev_dbg(codec->dev, "Detected microphone\n");
3594
157a75e6 3595 wm8994->mic_detecting = false;
b00adf76
MB		 3596 wm8994->jack_mic = true;
3597
3598 wm8958_micd_set_rate(codec);
3599
3600 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3601 SND_JACK_HEADSET);
3602 }
821edd2f 3603
b00adf76 3604
78b76dbe 3605 if (status & 0xfc) {
b00adf76 3606 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3607 wm8994->mic_detecting = false;
b00adf76
MB		 3608
3609 wm8958_micd_set_rate(codec);
3610
af6b6fe4 3611 /* If we have jackdet that will detect removal */
f02b0de0 3612 wm1811_micd_stop(codec);
ecd1732f
MB		 3613
3614 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3615 SND_JACK_HEADSET);
b00adf76 3616 }
821edd2f 3617}
b00adf76 3618
c0cc3f16
MB		 3619/* Deferred mic detection to allow for extra settling time */
3620static void wm1811_mic_work(struct work_struct *work)
3621{
3622 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3623 mic_work.work);
d9dd4ada 3624 struct wm8994 *control = wm8994->wm8994;
c0cc3f16 3625 struct snd_soc_codec *codec = wm8994->hubs.codec;
4585790d 3626
c0cc3f16 3627 pm_runtime_get_sync(codec->dev);
4585790d 3628
c0cc3f16 3629 /* If required for an external cap force MICBIAS on */
d9dd4ada 3630 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3631 snd_soc_dapm_force_enable_pin(&codec->dapm,
3632 "MICBIAS2");
3633 snd_soc_dapm_sync(&codec->dapm);
3634 }
4585790d 3635
c0cc3f16 3636 mutex_lock(&wm8994->accdet_lock);
4585790d 3637
c0cc3f16 3638 dev_dbg(codec->dev, "Starting mic detection\n");
4585790d 3639
63dd5452
MB		 3640 /* Use a user-supplied callback if we have one */
3641 if (wm8994->micd_cb) {
3642 wm8994->micd_cb(wm8994->micd_cb_data);
3643 } else {
3644 /*
3645 * Start off measument of microphone impedence to find out
3646 * what's actually there.
3647 */
3648 wm8994->mic_detecting = true;
3649 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
4585790d 3650
63dd5452
MB		 3651 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3652 WM8958_MICD_ENA, WM8958_MICD_ENA);
b00adf76 3653 }
c0cc3f16
MB		 3654
3655 mutex_unlock(&wm8994->accdet_lock);
3656
3657 pm_runtime_put(codec->dev);
821edd2f
MB		 3658}
3659
af6b6fe4
MB		 3660static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3661{
3662 struct wm8994_priv *wm8994 = data;
d9dd4ada 3663 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3664 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3665 int reg, delay;
c986564b 3666 bool present;
af6b6fe4 3667
b8176627
MB		 3668 pm_runtime_get_sync(codec->dev);
3669
2da1c4bf
MB		 3670 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3671
af6b6fe4
MB		 3672 mutex_lock(&wm8994->accdet_lock);
3673
3674 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3675 if (reg < 0) {
3676 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3677 mutex_unlock(&wm8994->accdet_lock);
b8176627 3678 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3679 return IRQ_NONE;
3680 }
3681
3682 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3683
c986564b 3684 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3685
c986564b
MB		 3686 if (present) {
3687 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3688
e9d9a968
MB		 3689 wm8958_micd_set_rate(codec);
3690
55a27786
MB		 3691 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3692 WM8958_MICB2_DISCH, 0);
3693
378ec0ca
MB		 3694 /* Disable debounce while inserted */
3695 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3696 WM1811_JACKDET_DB, 0);
3697
d9dd4ada 3698 delay = control->pdata.micdet_delay;
68defe58
MB		 3699 queue_delayed_work(system_power_efficient_wq,
3700 &wm8994->mic_work,
3701 msecs_to_jiffies(delay));
af6b6fe4
MB		 3702 } else {
3703 dev_dbg(codec->dev, "Jack not detected\n");
3704
c0cc3f16
MB		 3705 cancel_delayed_work_sync(&wm8994->mic_work);
3706
55a27786
MB		 3707 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3708 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3709
378ec0ca
MB		 3710 /* Enable debounce while removed */
3711 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3712 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3713
af6b6fe4
MB		 3714 wm8994->mic_detecting = false;
3715 wm8994->jack_mic = false;
3716 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3717 WM8958_MICD_ENA, 0);
3718 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3719 }
3720
3721 mutex_unlock(&wm8994->accdet_lock);
3722
c0cc3f16 3723 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3724 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3725 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3726
3727 if (present)
3728 snd_soc_jack_report(wm8994->micdet[0].jack,
3729 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3730 else
3731 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3732 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3733 wm8994->btn_mask);
3734
99af79df
MB		 3735 /* Since we only report deltas force an update, ensures we
3736 * avoid bootstrapping issues with the core. */
3737 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3738
b8176627 3739 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3740 return IRQ_HANDLED;
3741}
3742
99af79df
MB		 3743static void wm1811_jackdet_bootstrap(struct work_struct *work)
3744{
3745 struct wm8994_priv *wm8994 = container_of(work,
3746 struct wm8994_priv,
3747 jackdet_bootstrap.work);
3748 wm1811_jackdet_irq(0, wm8994);
3749}
3750
821edd2f
MB		 3751/**
3752 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3753 *
3754 * @codec: WM8958 codec
3755 * @jack: jack to report detection events on
3756 *
3757 * Enable microphone detection functionality for the WM8958. By
3758 * default simple detection which supports the detection of up to 6
3759 * buttons plus video and microphone functionality is supported.
3760 *
3761 * The WM8958 has an advanced jack detection facility which is able to
3762 * support complex accessory detection, especially when used in
3763 * conjunction with external circuitry. In order to provide maximum
3764 * flexiblity a callback is provided which allows a completely custom
3765 * detection algorithm.
3766 */
3767int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
98869f68
MB		 3768 wm1811_micdet_cb det_cb, void *det_cb_data,
3769 wm1811_mic_id_cb id_cb, void *id_cb_data)
821edd2f
MB		 3770{
3771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3772 struct wm8994 *control = wm8994->wm8994;
4585790d 3773 u16 micd_lvl_sel;
821edd2f 3774
81204c84
MB		 3775 switch (control->type) {
3776 case WM1811:
3777 case WM8958:
3778 break;
3779 default:
821edd2f 3780 return -EINVAL;
81204c84 3781 }
821edd2f
MB		 3782
3783 if (jack) {
4cdf5e49 3784 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3785 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3786
821edd2f 3787 wm8994->micdet[0].jack = jack;
821edd2f 3788
98869f68
MB		 3789 if (det_cb) {
3790 wm8994->micd_cb = det_cb;
3791 wm8994->micd_cb_data = det_cb_data;
63dd5452
MB		 3792 } else {
3793 wm8994->mic_detecting = true;
3794 wm8994->jack_mic = false;
3795 }
b00adf76 3796
98869f68
MB		 3797 if (id_cb) {
3798 wm8994->mic_id_cb = id_cb;
3799 wm8994->mic_id_cb_data = id_cb_data;
3800 } else {
3801 wm8994->mic_id_cb = wm8958_mic_id;
3802 wm8994->mic_id_cb_data = codec;
3803 }
b00adf76
MB		 3804
3805 wm8958_micd_set_rate(codec);
3806
4585790d 3807 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3808 if (control->pdata.micd_lvl_sel)
3809 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3810 else
3811 micd_lvl_sel = 0x41;
3812
3813 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3814 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3815 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3816
b00adf76 3817 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3818 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3819
af6b6fe4
MB		 3820 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3821
3822 /*
3823 * If we can use jack detection start off with that,
3824 * otherwise jump straight to microphone detection.
3825 */
3826 if (wm8994->jackdet) {
99af79df
MB		 3827 /* Disable debounce for the initial detect */
3828 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3829 WM1811_JACKDET_DB, 0);
3830
55a27786
MB		 3831 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3832 WM8958_MICB2_DISCH,
3833 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3834 snd_soc_update_bits(codec, WM8994_LDO_1,
3835 WM8994_LDO1_DISCH, 0);
3836 wm1811_jackdet_set_mode(codec,
3837 WM1811_JACKDET_MODE_JACK);
3838 } else {
3839 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3840 WM8958_MICD_ENA, WM8958_MICD_ENA);
3841 }
3842
821edd2f
MB		 3843 } else {
3844 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3845 WM8958_MICD_ENA, 0);
afaf1591 3846 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3847 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3848 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3849 }
3850
3851 return 0;
3852}
3853EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3854
2da1c4bf
MB		 3855static void wm8958_mic_work(struct work_struct *work)
3856{
3857 struct wm8994_priv *wm8994 = container_of(work,
3858 struct wm8994_priv,
3859 mic_complete_work.work);
3860 struct snd_soc_codec *codec = wm8994->hubs.codec;
3861
2da1c4bf
MB		 3862 pm_runtime_get_sync(codec->dev);
3863
3864 mutex_lock(&wm8994->accdet_lock);
3865
3866 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3867
3868 mutex_unlock(&wm8994->accdet_lock);
3869
3870 pm_runtime_put(codec->dev);
2da1c4bf
MB		 3871}
3872
821edd2f
MB		 3873static irqreturn_t wm8958_mic_irq(int irq, void *data)
3874{
3875 struct wm8994_priv *wm8994 = data;
8cb8e83b 3876 struct snd_soc_codec *codec = wm8994->hubs.codec;
2da1c4bf 3877 int reg, count, ret, id_delay;
821edd2f 3878
af6b6fe4
MB		 3879 /*
3880 * Jack detection may have detected a removal simulataneously
3881 * with an update of the MICDET status; if so it will have
3882 * stopped detection and we can ignore this interrupt.
3883 */
c986564b 3884 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3885 return IRQ_HANDLED;
af6b6fe4 3886
2da1c4bf 3887 cancel_delayed_work_sync(&wm8994->mic_complete_work);
70bd3b29
MB		 3888 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3889
b8176627
MB		 3890 pm_runtime_get_sync(codec->dev);
3891
19940b3d
MB		 3892 /* We may occasionally read a detection without an impedence
3893 * range being provided - if that happens loop again.
3894 */
3895 count = 10;
3896 do {
3897 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3898 if (reg < 0) {
3899 dev_err(codec->dev,
3900 "Failed to read mic detect status: %d\n",
3901 reg);
b8176627 3902 pm_runtime_put(codec->dev);
19940b3d
MB		 3903 return IRQ_NONE;
3904 }
821edd2f 3905
19940b3d
MB		 3906 if (!(reg & WM8958_MICD_VALID)) {
3907 dev_dbg(codec->dev, "Mic detect data not valid\n");
3908 goto out;
3909 }
3910
3911 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3912 break;
3913
3914 msleep(1);
3915 } while (count--);
3916
3917 if (count == 0)
ec8f53fb 3918 dev_warn(codec->dev, "No impedance range reported for jack\n");
821edd2f 3919
7116f452 3920#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3921 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3922#endif
2bbb5d66 3923
e874de43
MB		 3924 /* Avoid a transient report when the accessory is being removed */
3925 if (wm8994->jackdet) {
8afd0ef2
MB		 3926 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3927 if (ret < 0) {
e874de43 3928 dev_err(codec->dev, "Failed to read jack status: %d\n",
8afd0ef2
MB		 3929 ret);
3930 } else if (!(ret & WM1811_JACKDET_LVL)) {
e874de43 3931 dev_dbg(codec->dev, "Ignoring removed jack\n");
9e43088b 3932 goto out;
e874de43 3933 }
9767a58b
MB		 3934 } else if (!(reg & WM8958_MICD_STS)) {
3935 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3936 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3937 wm8994->btn_mask);
7afce3f5 3938 wm8994->mic_detecting = true;
9767a58b 3939 goto out;
e874de43
MB		 3940 }
3941
2da1c4bf
MB		 3942 wm8994->mic_status = reg;
3943 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3944
78b76dbe 3945 if (wm8994->mic_detecting)
68defe58
MB		 3946 queue_delayed_work(system_power_efficient_wq,
3947 &wm8994->mic_complete_work,
3948 msecs_to_jiffies(id_delay));
821edd2f 3949 else
78b76dbe 3950 wm8958_button_det(codec, reg);
821edd2f
MB		 3951
3952out:
b8176627 3953 pm_runtime_put(codec->dev);
821edd2f
MB		 3954 return IRQ_HANDLED;
3955}
3956
3b1af3f8
MB		 3957static irqreturn_t wm8994_fifo_error(int irq, void *data)
3958{
3959 struct snd_soc_codec *codec = data;
3960
3961 dev_err(codec->dev, "FIFO error\n");
3962
3963 return IRQ_HANDLED;
3964}
3965
f0b182b0
MB		 3966static irqreturn_t wm8994_temp_warn(int irq, void *data)
3967{
3968 struct snd_soc_codec *codec = data;
3969
3970 dev_err(codec->dev, "Thermal warning\n");
3971
3972 return IRQ_HANDLED;
3973}
3974
3975static irqreturn_t wm8994_temp_shut(int irq, void *data)
3976{
3977 struct snd_soc_codec *codec = data;
3978
3979 dev_crit(codec->dev, "Thermal shutdown\n");
3980
3981 return IRQ_HANDLED;
3982}
3983
f0fba2ad 3984static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3985{
d9a7666f 3986 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3987 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3988 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3989 unsigned int reg;
ec62dbd7 3990 int ret, i;
9e6e96a1 3991
8cb8e83b 3992 wm8994->hubs.codec = codec;
d9a7666f 3993 codec->control_data = control->regmap;
9e6e96a1 3994
d9a7666f 3995 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3996
af6b6fe4 3997 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3998 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3999 wm1811_jackdet_bootstrap);
70bd3b29
MB		 4000 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4001 wm8958_open_circuit_work);
af6b6fe4 4002
c0cc3f16
MB		 4003 switch (control->type) {
4004 case WM8994:
4005 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4006 break;
4007 case WM1811:
4008 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4009 break;
4010 default:
4011 break;
4012 }
4013
2da1c4bf
MB		 4014 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4015
c7ebf932
MB		 4016 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4017 init_completion(&wm8994->fll_locked[i]);
4018
d9dd4ada 4019 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 4020
f959dee9
MB		 4021 /* By default use idle_bias_off, will override for WM8994 */
4022 codec->dapm.idle_bias_off = 1;
4023
9e6e96a1 4024 /* Set revision-specific configuration */
3a423157
MB		 4025 switch (control->type) {
4026 case WM8994:
f959dee9 4027 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 4028 if (!control->pdata.lineout1_diff ||
4029 !control->pdata.lineout2_diff)
f959dee9
MB		 4030 codec->dapm.idle_bias_off = 0;
4031
da445afe 4032 switch (control->revision) {
3a423157
MB		 4033 case 2:
4034 case 3:
4537c4e7
MB		 4035 wm8994->hubs.dcs_codes_l = -5;
4036 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 4037 wm8994->hubs.hp_startup_mode = 1;
4038 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 4039 wm8994->hubs.series_startup = 1;
3a423157
MB		 4040 break;
4041 default:
79ef0abc 4042 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 4043 break;
4044 }
280ec8b7 4045 break;
3a423157
MB		 4046
4047 case WM8958:
8437f700 4048 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 4049 wm8994->hubs.hp_startup_mode = 1;
20dc24a9 4050
da445afe 4051 switch (control->revision) {
20dc24a9
MB		 4052 case 0:
4053 break;
4054 default:
4055 wm8994->fll_byp = true;
4056 break;
4057 }
9e6e96a1 4058 break;
3a423157 4059
81204c84
MB		 4060 case WM1811:
4061 wm8994->hubs.dcs_readback_mode = 2;
4062 wm8994->hubs.no_series_update = 1;
29fdc360 4063 wm8994->hubs.hp_startup_mode = 1;
af31a227 4064 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 4065 wm8994->fll_byp = true;
81204c84 4066
72222be3
MB		 4067 wm8994->hubs.dcs_codes_l = -9;
4068 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 4069
4070 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4071 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4072 break;
4073
9e6e96a1
MB		 4074 default:
4075 break;
4076 }
9e6e96a1 4077
2a8a856d 4078 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 4079 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 4080 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 4081 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 4082 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 4083 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 4084
3a423157
MB		 4085 switch (control->type) {
4086 case WM8994:
9b7c525d
MB		 4087 if (wm8994->micdet_irq) {
4088 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4089 wm8994_mic_irq,
4090 IRQF_TRIGGER_RISING,
4091 "Mic1 detect",
4092 wm8994);
4093 if (ret != 0)
4094 dev_warn(codec->dev,
4095 "Failed to request Mic1 detect IRQ: %d\n",
4096 ret);
4097 }
3a423157 4098
2a8a856d 4099 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4100 WM8994_IRQ_MIC1_SHRT,
4101 wm8994_mic_irq, "Mic 1 short",
4102 wm8994);
4103 if (ret != 0)
4104 dev_warn(codec->dev,
4105 "Failed to request Mic1 short IRQ: %d\n",
4106 ret);
4107
2a8a856d 4108 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4109 WM8994_IRQ_MIC2_DET,
4110 wm8994_mic_irq, "Mic 2 detect",
4111 wm8994);
4112 if (ret != 0)
4113 dev_warn(codec->dev,
4114 "Failed to request Mic2 detect IRQ: %d\n",
4115 ret);
4116
2a8a856d 4117 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4118 WM8994_IRQ_MIC2_SHRT,
4119 wm8994_mic_irq, "Mic 2 short",
4120 wm8994);
4121 if (ret != 0)
4122 dev_warn(codec->dev,
4123 "Failed to request Mic2 short IRQ: %d\n",
4124 ret);
4125 break;
821edd2f
MB		 4126
4127 case WM8958:
81204c84 4128 case WM1811:
9b7c525d
MB		 4129 if (wm8994->micdet_irq) {
4130 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4131 wm8958_mic_irq,
4132 IRQF_TRIGGER_RISING,
4133 "Mic detect",
4134 wm8994);
4135 if (ret != 0)
4136 dev_warn(codec->dev,
4137 "Failed to request Mic detect IRQ: %d\n",
4138 ret);
b4046d01
MB		 4139 } else {
4140 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4141 wm8958_mic_irq, "Mic detect",
4142 wm8994);
9b7c525d 4143 }
3a423157 4144 }
88766984 4145
af6b6fe4
MB		 4146 switch (control->type) {
4147 case WM1811:
da445afe 4148 if (control->cust_id > 1 || control->revision > 1) {
af6b6fe4
MB		 4149 ret = wm8994_request_irq(wm8994->wm8994,
4150 WM8994_IRQ_GPIO(6),
4151 wm1811_jackdet_irq, "JACKDET",
4152 wm8994);
4153 if (ret == 0)
4154 wm8994->jackdet = true;
4155 }
4156 break;
4157 default:
4158 break;
4159 }
4160
c7ebf932
MB		 4161 wm8994->fll_locked_irq = true;
4162 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 4163 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 4164 WM8994_IRQ_FLL1_LOCK + i,
4165 wm8994_fll_locked_irq, "FLL lock",
4166 &wm8994->fll_locked[i]);
4167 if (ret != 0)
4168 wm8994->fll_locked_irq = false;
4169 }
4170
27060b3c
MB		 4171 /* Make sure we can read from the GPIOs if they're inputs */
4172 pm_runtime_get_sync(codec->dev);
4173
9e6e96a1
MB		 4174 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4175 * configured on init - if a system wants to do this dynamically
4176 * at runtime we can deal with that then.
4177 */
d9a7666f 4178 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 4179 if (ret < 0) {
4180 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4181 goto err_irq;
9e6e96a1 4182 }
d9a7666f 4183 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4184 wm8994->lrclk_shared[0] = 1;
4185 wm8994_dai[0].symmetric_rates = 1;
4186 } else {
4187 wm8994->lrclk_shared[0] = 0;
4188 }
4189
d9a7666f 4190 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4191 if (ret < 0) {
4192 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4193 goto err_irq;
9e6e96a1 4194 }
d9a7666f 4195 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4196 wm8994->lrclk_shared[1] = 1;
4197 wm8994_dai[1].symmetric_rates = 1;
4198 } else {
4199 wm8994->lrclk_shared[1] = 0;
4200 }
4201
27060b3c
MB		 4202 pm_runtime_put(codec->dev);
4203
bfd37bb5
MB		 4204 /* Latch volume update bits */
4205 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4206 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4207 wm8994_vu_bits[i].mask,
4208 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4209
4210 /* Set the low bit of the 3D stereo depth so TLV matches */
4211 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4212 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4213 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4214 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4215 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4216 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4217 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4218 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4219 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4220
5b739670
MB		 4221 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4222 * use this; it only affects behaviour on idle TDM clock
4223 * cycles. */
4224 switch (control->type) {
4225 case WM8994:
4226 case WM8958:
4227 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4228 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4229 break;
4230 default:
4231 break;
4232 }
d1ce6b20 4233
500fa30e
MB		 4234 /* Put MICBIAS into bypass mode by default on newer devices */
4235 switch (control->type) {
4236 case WM8958:
4237 case WM1811:
4238 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4239 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4240 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4241 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4242 break;
4243 default:
4244 break;
4245 }
4246
c340304d
MB		 4247 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4248 wm_hubs_update_class_w(codec);
9e6e96a1 4249
f0fba2ad 4250 wm8994_handle_pdata(wm8994);
9e6e96a1 4251
f0fba2ad 4252 wm_hubs_add_analogue_controls(codec);
022658be 4253 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4254 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4255 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4256 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4257
4258 switch (control->type) {
4259 case WM8994:
4260 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4261 ARRAY_SIZE(wm8994_specific_dapm_widgets));
da445afe 4262 if (control->revision < 4) {
173efa09
DP		 4263 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4264 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4265 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4266 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4267 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4268 ARRAY_SIZE(wm8994_dac_revd_widgets));
4269 } else {
173efa09
DP		 4270 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4271 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4272 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4273 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4274 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4275 ARRAY_SIZE(wm8994_dac_widgets));
4276 }
c4431df0
MB		 4277 break;
4278 case WM8958:
022658be 4279 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4280 ARRAY_SIZE(wm8958_snd_controls));
4281 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4282 ARRAY_SIZE(wm8958_dapm_widgets));
da445afe 4283 if (control->revision < 1) {
780e2806
MB		 4284 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4285 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4286 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4287 ARRAY_SIZE(wm8994_adc_revd_widgets));
4288 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4289 ARRAY_SIZE(wm8994_dac_revd_widgets));
4290 } else {
4291 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4292 ARRAY_SIZE(wm8994_lateclk_widgets));
4293 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4294 ARRAY_SIZE(wm8994_adc_widgets));
4295 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4296 ARRAY_SIZE(wm8994_dac_widgets));
4297 }
c4431df0 4298 break;
81204c84
MB		 4299
4300 case WM1811:
022658be 4301 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4302 ARRAY_SIZE(wm8958_snd_controls));
4303 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4304 ARRAY_SIZE(wm8958_dapm_widgets));
4305 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4306 ARRAY_SIZE(wm8994_lateclk_widgets));
4307 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4308 ARRAY_SIZE(wm8994_adc_widgets));
4309 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4310 ARRAY_SIZE(wm8994_dac_widgets));
4311 break;
c4431df0 4312 }
c4431df0 4313
f0fba2ad 4314 wm_hubs_add_analogue_routes(codec, 0, 0);
b888edbc 4315 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4316 wm_hubs_dcs_done, "DC servo done",
4317 &wm8994->hubs);
4318 if (ret == 0)
4319 wm8994->hubs.dcs_done_irq = true;
ce6120cc 4320 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4321
c4431df0
MB		 4322 switch (control->type) {
4323 case WM8994:
4324 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4325 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4326
da445afe 4327 if (control->revision < 4) {
6ed8f148
MB		 4328 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4329 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4330 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4331 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4332 } else {
4333 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4334 ARRAY_SIZE(wm8994_lateclk_intercon));
4335 }
c4431df0
MB		 4336 break;
4337 case WM8958:
da445afe 4338 if (control->revision < 1) {
15676937
CR		 4339 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4340 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4341 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4342 ARRAY_SIZE(wm8994_revd_intercon));
4343 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4344 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4345 } else {
4346 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4347 ARRAY_SIZE(wm8994_lateclk_intercon));
4348 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4349 ARRAY_SIZE(wm8958_intercon));
4350 }
f701a2e5
MB		 4351
4352 wm8958_dsp2_init(codec);
c4431df0 4353 break;
81204c84
MB		 4354 case WM1811:
4355 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4356 ARRAY_SIZE(wm8994_lateclk_intercon));
4357 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4358 ARRAY_SIZE(wm8958_intercon));
4359 break;
c4431df0
MB		 4360 }
4361
9e6e96a1
MB		 4362 return 0;
4363
88766984 4364err_irq:
af6b6fe4
MB		 4365 if (wm8994->jackdet)
4366 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4367 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4368 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4369 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4370 if (wm8994->micdet_irq)
4371 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4372 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4374 &wm8994->fll_locked[i]);
2a8a856d 4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4376 &wm8994->hubs);
2a8a856d
MB		 4377 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4378 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4379 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4380
9e6e96a1
MB		 4381 return ret;
4382}
4383
34ff0f95 4384static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4385{
f0fba2ad 4386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4387 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4388 int i;
9e6e96a1
MB		 4389
4390 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4391
c7ebf932 4392 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4393 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4394 &wm8994->fll_locked[i]);
4395
2a8a856d 4396 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4397 &wm8994->hubs);
2a8a856d
MB		 4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4399 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4400 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4401
af6b6fe4
MB		 4402 if (wm8994->jackdet)
4403 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4404
3a423157
MB		 4405 switch (control->type) {
4406 case WM8994:
9b7c525d
MB		 4407 if (wm8994->micdet_irq)
4408 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4409 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4410 wm8994);
2a8a856d 4411 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4412 wm8994);
2a8a856d 4413 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4414 wm8994);
4415 break;
821edd2f 4416
81204c84 4417 case WM1811:
821edd2f 4418 case WM8958:
9b7c525d
MB		 4419 if (wm8994->micdet_irq)
4420 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4421 break;
3a423157 4422 }
34ff0f95
JJ		 4423 release_firmware(wm8994->mbc);
4424 release_firmware(wm8994->mbc_vss);
4425 release_firmware(wm8994->enh_eq);
24fb2b11 4426 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4427 return 0;
4428}
4429
f0fba2ad
LG		 4430static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4431 .probe = wm8994_codec_probe,
4432 .remove = wm8994_codec_remove,
4752a887
MB		 4433 .suspend = wm8994_codec_suspend,
4434 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4435 .set_bias_level = wm8994_set_bias_level,
4436};
4437
7a79e94e 4438static int wm8994_probe(struct platform_device *pdev)
f0fba2ad 4439{
2bc16ed8
MB		 4440 struct wm8994_priv *wm8994;
4441
4442 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4443 GFP_KERNEL);
4444 if (wm8994 == NULL)
4445 return -ENOMEM;
4446 platform_set_drvdata(pdev, wm8994);
4447
4448 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4449
57e265c8
MB		 4450 pm_runtime_enable(&pdev->dev);
4451 pm_runtime_idle(&pdev->dev);
4452
f0fba2ad
LG		 4453 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4454 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4455}
4456
7a79e94e 4457static int wm8994_remove(struct platform_device *pdev)
f0fba2ad
LG		 4458{
4459 snd_soc_unregister_codec(&pdev->dev);
57e265c8
MB		 4460 pm_runtime_disable(&pdev->dev);
4461
f0fba2ad
LG		 4462 return 0;
4463}
4464
4752a887
MB		 4465#ifdef CONFIG_PM_SLEEP
4466static int wm8994_suspend(struct device *dev)
4467{
4468 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4469
4470 /* Drop down to power saving mode when system is suspended */
4471 if (wm8994->jackdet && !wm8994->active_refcount)
4472 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4473 WM1811_JACKDET_MODE_MASK,
4474 wm8994->jackdet_mode);
4475
4476 return 0;
4477}
4478
4479static int wm8994_resume(struct device *dev)
4480{
4481 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4482
78b76dbe 4483 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB		 4484 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4485 WM1811_JACKDET_MODE_MASK,
4486 WM1811_JACKDET_MODE_AUDIO);
4487
4488 return 0;
4489}
4490#endif
4491
4492static const struct dev_pm_ops wm8994_pm_ops = {
4493 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4494};
4495
9e6e96a1
MB		 4496static struct platform_driver wm8994_codec_driver = {
4497 .driver = {
4752a887
MB		 4498 .name = "wm8994-codec",
4499 .owner = THIS_MODULE,
4500 .pm = &wm8994_pm_ops,
4501 },
f0fba2ad 4502 .probe = wm8994_probe,
7a79e94e 4503 .remove = wm8994_remove,
9e6e96a1
MB		 4504};
4505
5bbcc3c0 4506module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4507
4508MODULE_DESCRIPTION("ASoC WM8994 driver");
4509MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4510MODULE_LICENSE("GPL");
4511MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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