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ASoC: wm_hubs: Don't actively manage LINEOUT_VMID_BUF
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
28e33269
MB		 689 if (!wm8994->jackdet || !wm8994->jack_cb)
690 return;
691
af6b6fe4
MB		 692 if (wm8994->active_refcount)
693 mode = WM1811_JACKDET_MODE_AUDIO;
694
4752a887 695 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 696 return;
697
4752a887 698 wm8994->jackdet_mode = mode;
1defde2a 699
4752a887
MB		 700 /* Always use audio mode to detect while the system is active */
701 if (mode != WM1811_JACKDET_MODE_NONE)
702 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 703
4752a887
MB		 704 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
705 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 706}
707
708static void active_reference(struct snd_soc_codec *codec)
709{
710 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
711
712 mutex_lock(&wm8994->accdet_lock);
713
714 wm8994->active_refcount++;
715
716 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
717 wm8994->active_refcount);
718
1defde2a
MB		 719 /* If we're using jack detection go into audio mode */
720 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 721
722 mutex_unlock(&wm8994->accdet_lock);
723}
724
725static void active_dereference(struct snd_soc_codec *codec)
726{
727 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
728 u16 mode;
729
730 mutex_lock(&wm8994->accdet_lock);
731
732 wm8994->active_refcount--;
733
734 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
735 wm8994->active_refcount);
736
737 if (wm8994->active_refcount == 0) {
738 /* Go into appropriate detection only mode */
1defde2a
MB		 739 if (wm8994->jack_mic || wm8994->mic_detecting)
740 mode = WM1811_JACKDET_MODE_MIC;
741 else
742 mode = WM1811_JACKDET_MODE_JACK;
743
744 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 745 }
746
747 mutex_unlock(&wm8994->accdet_lock);
748}
749
9e6e96a1
MB		 750static int clk_sys_event(struct snd_soc_dapm_widget *w,
751 struct snd_kcontrol *kcontrol, int event)
752{
753 struct snd_soc_codec *codec = w->codec;
754
755 switch (event) {
756 case SND_SOC_DAPM_PRE_PMU:
757 return configure_clock(codec);
758
759 case SND_SOC_DAPM_POST_PMD:
760 configure_clock(codec);
761 break;
762 }
763
764 return 0;
765}
766
4b7ed83a
MB		 767static void vmid_reference(struct snd_soc_codec *codec)
768{
769 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
770
db966f8a
MB		 771 pm_runtime_get_sync(codec->dev);
772
4b7ed83a
MB		 773 wm8994->vmid_refcount++;
774
775 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
776 wm8994->vmid_refcount);
777
778 if (wm8994->vmid_refcount == 1) {
cc6d5a8c
MB		 779 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
780 WM8994_LINEOUT_VMID_BUF_ENA |
781 WM8994_LINEOUT1_DISCH |
782 WM8994_LINEOUT2_DISCH,
783 WM8994_LINEOUT_VMID_BUF_ENA);
784
f7085641
MB		 785 wm_hubs_vmid_ena(codec);
786
4b7ed83a
MB		 787 /* Startup bias, VMID ramp & buffer */
788 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
cc6d5a8c
MB		 789 WM8994_BIAS_SRC |
790 WM8994_VMID_DISCH |
4b7ed83a
MB		 791 WM8994_STARTUP_BIAS_ENA |
792 WM8994_VMID_BUF_ENA |
793 WM8994_VMID_RAMP_MASK,
cc6d5a8c 794 WM8994_BIAS_SRC |
4b7ed83a
MB		 795 WM8994_STARTUP_BIAS_ENA |
796 WM8994_VMID_BUF_ENA |
65f01ef0 797 (0x2 << WM8994_VMID_RAMP_SHIFT));
4b7ed83a
MB		 798
799 /* Main bias enable, VMID=2x40k */
800 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
801 WM8994_BIAS_ENA |
802 WM8994_VMID_SEL_MASK,
803 WM8994_BIAS_ENA | 0x2);
804
cc6d5a8c
MB		 805 msleep(50);
806
807 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
808 WM8994_VMID_RAMP_MASK | WM8994_BIAS_SRC,
809 0);
4b7ed83a
MB		 810 }
811}
812
813static void vmid_dereference(struct snd_soc_codec *codec)
814{
815 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
816
817 wm8994->vmid_refcount--;
818
819 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
820 wm8994->vmid_refcount);
821
822 if (wm8994->vmid_refcount == 0) {
823 /* Switch over to startup biases */
824 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
825 WM8994_BIAS_SRC |
826 WM8994_STARTUP_BIAS_ENA |
827 WM8994_VMID_BUF_ENA |
828 WM8994_VMID_RAMP_MASK,
829 WM8994_BIAS_SRC |
830 WM8994_STARTUP_BIAS_ENA |
831 WM8994_VMID_BUF_ENA |
832 (1 << WM8994_VMID_RAMP_SHIFT));
833
834 /* Disable main biases */
835 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
836 WM8994_BIAS_ENA |
837 WM8994_VMID_SEL_MASK, 0);
838
e85b26ce
MB		 839 /* Discharge VMID */
840 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
841 WM8994_VMID_DISCH, WM8994_VMID_DISCH);
842
4b7ed83a
MB		 843 /* Discharge line */
844 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
845 WM8994_LINEOUT1_DISCH |
846 WM8994_LINEOUT2_DISCH,
847 WM8994_LINEOUT1_DISCH |
848 WM8994_LINEOUT2_DISCH);
849
850 msleep(5);
851
852 /* Switch off startup biases */
853 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
854 WM8994_BIAS_SRC |
855 WM8994_STARTUP_BIAS_ENA |
856 WM8994_VMID_BUF_ENA |
857 WM8994_VMID_RAMP_MASK, 0);
858 }
db966f8a
MB		 859
860 pm_runtime_put(codec->dev);
4b7ed83a
MB		 861}
862
863static int vmid_event(struct snd_soc_dapm_widget *w,
864 struct snd_kcontrol *kcontrol, int event)
865{
866 struct snd_soc_codec *codec = w->codec;
867
868 switch (event) {
869 case SND_SOC_DAPM_PRE_PMU:
870 vmid_reference(codec);
871 break;
872
873 case SND_SOC_DAPM_POST_PMD:
874 vmid_dereference(codec);
875 break;
876 }
877
878 return 0;
879}
880
9e6e96a1
MB		 881static void wm8994_update_class_w(struct snd_soc_codec *codec)
882{
fec6dd83 883 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 884 int enable = 1;
885 int source = 0; /* GCC flow analysis can't track enable */
886 int reg, reg_r;
887
888 /* Only support direct DAC->headphone paths */
889 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
890 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 891 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 892 enable = 0;
893 }
894
895 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
896 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 897 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 898 enable = 0;
899 }
900
901 /* We also need the same setting for L/R and only one path */
902 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
903 switch (reg) {
904 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 905 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 906 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
907 break;
908 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 909 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 910 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
911 break;
912 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 913 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 914 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
915 break;
916 default:
ee839a21 917 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 918 enable = 0;
919 break;
920 }
921
922 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
923 if (reg_r != reg) {
ee839a21 924 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 925 enable = 0;
926 }
927
928 if (enable) {
929 dev_dbg(codec->dev, "Class W enabled\n");
930 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
931 WM8994_CP_DYN_PWR |
932 WM8994_CP_DYN_SRC_SEL_MASK,
933 source | WM8994_CP_DYN_PWR);
fec6dd83 934 wm8994->hubs.class_w = true;
9e6e96a1
MB		 935
936 } else {
937 dev_dbg(codec->dev, "Class W disabled\n");
938 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
939 WM8994_CP_DYN_PWR, 0);
fec6dd83 940 wm8994->hubs.class_w = false;
9e6e96a1
MB		 941 }
942}
943
173efa09
DP		 944static int late_enable_ev(struct snd_soc_dapm_widget *w,
945 struct snd_kcontrol *kcontrol, int event)
946{
947 struct snd_soc_codec *codec = w->codec;
948 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
949
950 switch (event) {
951 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 952 if (wm8994->aif1clk_enable) {
173efa09
DP		 953 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
954 WM8994_AIF1CLK_ENA_MASK,
955 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 956 wm8994->aif1clk_enable = 0;
957 }
958 if (wm8994->aif2clk_enable) {
173efa09
DP		 959 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
960 WM8994_AIF2CLK_ENA_MASK,
961 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 962 wm8994->aif2clk_enable = 0;
963 }
173efa09
DP		 964 break;
965 }
966
c6b7b570
MB		 967 /* We may also have postponed startup of DSP, handle that. */
968 wm8958_aif_ev(w, kcontrol, event);
969
173efa09
DP		 970 return 0;
971}
972
973static int late_disable_ev(struct snd_soc_dapm_widget *w,
974 struct snd_kcontrol *kcontrol, int event)
975{
976 struct snd_soc_codec *codec = w->codec;
977 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
978
979 switch (event) {
980 case SND_SOC_DAPM_POST_PMD:
a3cff81a 981 if (wm8994->aif1clk_disable) {
173efa09
DP		 982 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
983 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 984 wm8994->aif1clk_disable = 0;
173efa09 985 }
a3cff81a 986 if (wm8994->aif2clk_disable) {
173efa09
DP		 987 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
988 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 989 wm8994->aif2clk_disable = 0;
173efa09
DP		 990 }
991 break;
992 }
993
994 return 0;
995}
996
997static int aif1clk_ev(struct snd_soc_dapm_widget *w,
998 struct snd_kcontrol *kcontrol, int event)
999{
1000 struct snd_soc_codec *codec = w->codec;
1001 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1002
1003 switch (event) {
1004 case SND_SOC_DAPM_PRE_PMU:
1005 wm8994->aif1clk_enable = 1;
1006 break;
a3cff81a
DP		 1007 case SND_SOC_DAPM_POST_PMD:
1008 wm8994->aif1clk_disable = 1;
1009 break;
173efa09
DP		 1010 }
1011
1012 return 0;
1013}
1014
1015static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1016 struct snd_kcontrol *kcontrol, int event)
1017{
1018 struct snd_soc_codec *codec = w->codec;
1019 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1020
1021 switch (event) {
1022 case SND_SOC_DAPM_PRE_PMU:
1023 wm8994->aif2clk_enable = 1;
1024 break;
a3cff81a
DP		 1025 case SND_SOC_DAPM_POST_PMD:
1026 wm8994->aif2clk_disable = 1;
1027 break;
173efa09
DP		 1028 }
1029
1030 return 0;
1031}
1032
04d28681
DP		 1033static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1034 struct snd_kcontrol *kcontrol, int event)
1035{
1036 late_enable_ev(w, kcontrol, event);
1037 return 0;
1038}
1039
b462c6e6
DP		 1040static int micbias_ev(struct snd_soc_dapm_widget *w,
1041 struct snd_kcontrol *kcontrol, int event)
1042{
1043 late_enable_ev(w, kcontrol, event);
1044 return 0;
1045}
1046
c52fd021
DP		 1047static int dac_ev(struct snd_soc_dapm_widget *w,
1048 struct snd_kcontrol *kcontrol, int event)
1049{
1050 struct snd_soc_codec *codec = w->codec;
1051 unsigned int mask = 1 << w->shift;
1052
1053 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1054 mask, mask);
1055 return 0;
1056}
1057
9e6e96a1
MB		 1058static const char *hp_mux_text[] = {
1059 "Mixer",
1060 "DAC",
1061};
1062
1063#define WM8994_HP_ENUM(xname, xenum) \
1064{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1065 .info = snd_soc_info_enum_double, \
1066 .get = snd_soc_dapm_get_enum_double, \
1067 .put = wm8994_put_hp_enum, \
1068 .private_value = (unsigned long)&xenum }
1069
1070static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1071 struct snd_ctl_elem_value *ucontrol)
1072{
9d03545d
JN		 1073 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1074 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1075 struct snd_soc_codec *codec = w->codec;
1076 int ret;
1077
1078 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1079
1080 wm8994_update_class_w(codec);
1081
1082 return ret;
1083}
1084
1085static const struct soc_enum hpl_enum =
1086 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1087
1088static const struct snd_kcontrol_new hpl_mux =
1089 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1090
1091static const struct soc_enum hpr_enum =
1092 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1093
1094static const struct snd_kcontrol_new hpr_mux =
1095 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1096
1097static const char *adc_mux_text[] = {
1098 "ADC",
1099 "DMIC",
1100};
1101
1102static const struct soc_enum adc_enum =
1103 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1104
1105static const struct snd_kcontrol_new adcl_mux =
1106 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1107
1108static const struct snd_kcontrol_new adcr_mux =
1109 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1110
1111static const struct snd_kcontrol_new left_speaker_mixer[] = {
1112SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1113SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1114SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1115SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1116SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1117};
1118
1119static const struct snd_kcontrol_new right_speaker_mixer[] = {
1120SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1121SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1122SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1123SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1124SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1125};
1126
1127/* Debugging; dump chip status after DAPM transitions */
1128static int post_ev(struct snd_soc_dapm_widget *w,
1129 struct snd_kcontrol *kcontrol, int event)
1130{
1131 struct snd_soc_codec *codec = w->codec;
1132 dev_dbg(codec->dev, "SRC status: %x\n",
1133 snd_soc_read(codec,
1134 WM8994_RATE_STATUS));
1135 return 0;
1136}
1137
1138static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1139SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1140 1, 1, 0),
1141SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1142 0, 1, 0),
1143};
1144
1145static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1146SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1147 1, 1, 0),
1148SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1149 0, 1, 0),
1150};
1151
a3257ba8
MB		 1152static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1153SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1154 1, 1, 0),
1155SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1156 0, 1, 0),
1157};
1158
1159static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1160SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1161 1, 1, 0),
1162SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1163 0, 1, 0),
1164};
1165
9e6e96a1
MB		 1166static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1167SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1168 5, 1, 0),
1169SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1170 4, 1, 0),
1171SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1172 2, 1, 0),
1173SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1174 1, 1, 0),
1175SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1176 0, 1, 0),
1177};
1178
1179static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1180SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1181 5, 1, 0),
1182SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1183 4, 1, 0),
1184SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1185 2, 1, 0),
1186SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1187 1, 1, 0),
1188SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1189 0, 1, 0),
1190};
1191
1192#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1193{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1194 .info = snd_soc_info_volsw, \
1195 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1196 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1197
1198static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1199 struct snd_ctl_elem_value *ucontrol)
1200{
9d03545d
JN		 1201 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1202 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1203 struct snd_soc_codec *codec = w->codec;
1204 int ret;
1205
1206 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1207
1208 wm8994_update_class_w(codec);
1209
1210 return ret;
1211}
1212
1213static const struct snd_kcontrol_new dac1l_mix[] = {
1214WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1215 5, 1, 0),
1216WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1217 4, 1, 0),
1218WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1219 2, 1, 0),
1220WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1221 1, 1, 0),
1222WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1223 0, 1, 0),
1224};
1225
1226static const struct snd_kcontrol_new dac1r_mix[] = {
1227WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1228 5, 1, 0),
1229WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1230 4, 1, 0),
1231WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1232 2, 1, 0),
1233WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1234 1, 1, 0),
1235WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1236 0, 1, 0),
1237};
1238
1239static const char *sidetone_text[] = {
1240 "ADC/DMIC1", "DMIC2",
1241};
1242
1243static const struct soc_enum sidetone1_enum =
1244 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1245
1246static const struct snd_kcontrol_new sidetone1_mux =
1247 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1248
1249static const struct soc_enum sidetone2_enum =
1250 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1251
1252static const struct snd_kcontrol_new sidetone2_mux =
1253 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1254
1255static const char *aif1dac_text[] = {
1256 "AIF1DACDAT", "AIF3DACDAT",
1257};
1258
1259static const struct soc_enum aif1dac_enum =
1260 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1261
1262static const struct snd_kcontrol_new aif1dac_mux =
1263 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1264
1265static const char *aif2dac_text[] = {
1266 "AIF2DACDAT", "AIF3DACDAT",
1267};
1268
1269static const struct soc_enum aif2dac_enum =
1270 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1271
1272static const struct snd_kcontrol_new aif2dac_mux =
1273 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1274
1275static const char *aif2adc_text[] = {
1276 "AIF2ADCDAT", "AIF3DACDAT",
1277};
1278
1279static const struct soc_enum aif2adc_enum =
1280 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1281
1282static const struct snd_kcontrol_new aif2adc_mux =
1283 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1284
1285static const char *aif3adc_text[] = {
c4431df0 1286 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1287};
1288
c4431df0 1289static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1290 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1291
c4431df0
MB		 1292static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1293 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1294
1295static const struct soc_enum wm8958_aif3adc_enum =
1296 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1297
1298static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1299 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1300
1301static const char *mono_pcm_out_text[] = {
1302 "None", "AIF2ADCL", "AIF2ADCR",
1303};
1304
1305static const struct soc_enum mono_pcm_out_enum =
1306 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1307
1308static const struct snd_kcontrol_new mono_pcm_out_mux =
1309 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1310
1311static const char *aif2dac_src_text[] = {
1312 "AIF2", "AIF3",
1313};
1314
1315/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1316static const struct soc_enum aif2dacl_src_enum =
1317 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1318
1319static const struct snd_kcontrol_new aif2dacl_src_mux =
1320 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1321
1322static const struct soc_enum aif2dacr_src_enum =
1323 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1324
1325static const struct snd_kcontrol_new aif2dacr_src_mux =
1326 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1327
173efa09
DP		 1328static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1329SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1330 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1331SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1332 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1333
1334SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1335 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1336SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1337 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1339 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1340SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1341 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1342SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1343 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1344
1345SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1346 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1347 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1348SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1349 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1350 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1351SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1352 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1353SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1354 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1355
1356SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1357};
1358
1359static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1360SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1361SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1362SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1363SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1364 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1365SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1366 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1367SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1368SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1369};
1370
c52fd021
DP		 1371static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1372SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1373 dac_ev, SND_SOC_DAPM_PRE_PMU),
1374SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1375 dac_ev, SND_SOC_DAPM_PRE_PMU),
1376SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1377 dac_ev, SND_SOC_DAPM_PRE_PMU),
1378SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1379 dac_ev, SND_SOC_DAPM_PRE_PMU),
1380};
1381
1382static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1383SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1384SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1385SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1386SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1387};
1388
04d28681 1389static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1390SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1391 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1392SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1393 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1394};
1395
1396static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1397SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1398SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1399};
1400
9e6e96a1
MB		 1401static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1402SND_SOC_DAPM_INPUT("DMIC1DAT"),
1403SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1404SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1405
b462c6e6
DP		 1406SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1407 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1408SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1409 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1410
9e6e96a1
MB		 1411SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1412 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1413
1414SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1415SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1416SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1417
7f94de48 1418SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1419 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1420SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1421 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1422SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1423 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1424 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1425SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1426 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1427 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1428
7f94de48 1429SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1430 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1431SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1432 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1433SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1434 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1435 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1436SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1437 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1438 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1439
1440SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1441 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1442SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1443 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1444
a3257ba8
MB		 1445SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1446 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1447SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1448 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1449
9e6e96a1
MB		 1450SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1451 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1452SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1453 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1454
1455SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1456SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1457
1458SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1459 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1460SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1461 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1462
1463SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1464 WM8994_POWER_MANAGEMENT_4, 13, 0),
1465SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1466 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1467SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1468 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1469 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1470SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1471 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1472 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1473
5567d8c6
MB		 1474SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1475SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1476SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1477SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1478
1479SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1480SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1481SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1482
5567d8c6
MB		 1483SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1484SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1485
1486SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1487
1488SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1489SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1490SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1491SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1492
1493/* Power is done with the muxes since the ADC power also controls the
1494 * downsampling chain, the chip will automatically manage the analogue
1495 * specific portions.
1496 */
1497SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1498SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1499
9e6e96a1
MB		 1500SND_SOC_DAPM_POST("Debug log", post_ev),
1501};
1502
c4431df0
MB		 1503static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1504SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1505};
9e6e96a1 1506
c4431df0
MB		 1507static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1508SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1509SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1510SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1511SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1512};
1513
1514static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1515 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1516 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1517
1518 { "DSP1CLK", NULL, "CLK_SYS" },
1519 { "DSP2CLK", NULL, "CLK_SYS" },
1520 { "DSPINTCLK", NULL, "CLK_SYS" },
1521
1522 { "AIF1ADC1L", NULL, "AIF1CLK" },
1523 { "AIF1ADC1L", NULL, "DSP1CLK" },
1524 { "AIF1ADC1R", NULL, "AIF1CLK" },
1525 { "AIF1ADC1R", NULL, "DSP1CLK" },
1526 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1527
1528 { "AIF1DAC1L", NULL, "AIF1CLK" },
1529 { "AIF1DAC1L", NULL, "DSP1CLK" },
1530 { "AIF1DAC1R", NULL, "AIF1CLK" },
1531 { "AIF1DAC1R", NULL, "DSP1CLK" },
1532 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1533
1534 { "AIF1ADC2L", NULL, "AIF1CLK" },
1535 { "AIF1ADC2L", NULL, "DSP1CLK" },
1536 { "AIF1ADC2R", NULL, "AIF1CLK" },
1537 { "AIF1ADC2R", NULL, "DSP1CLK" },
1538 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1539
1540 { "AIF1DAC2L", NULL, "AIF1CLK" },
1541 { "AIF1DAC2L", NULL, "DSP1CLK" },
1542 { "AIF1DAC2R", NULL, "AIF1CLK" },
1543 { "AIF1DAC2R", NULL, "DSP1CLK" },
1544 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1545
1546 { "AIF2ADCL", NULL, "AIF2CLK" },
1547 { "AIF2ADCL", NULL, "DSP2CLK" },
1548 { "AIF2ADCR", NULL, "AIF2CLK" },
1549 { "AIF2ADCR", NULL, "DSP2CLK" },
1550 { "AIF2ADCR", NULL, "DSPINTCLK" },
1551
1552 { "AIF2DACL", NULL, "AIF2CLK" },
1553 { "AIF2DACL", NULL, "DSP2CLK" },
1554 { "AIF2DACR", NULL, "AIF2CLK" },
1555 { "AIF2DACR", NULL, "DSP2CLK" },
1556 { "AIF2DACR", NULL, "DSPINTCLK" },
1557
1558 { "DMIC1L", NULL, "DMIC1DAT" },
1559 { "DMIC1L", NULL, "CLK_SYS" },
1560 { "DMIC1R", NULL, "DMIC1DAT" },
1561 { "DMIC1R", NULL, "CLK_SYS" },
1562 { "DMIC2L", NULL, "DMIC2DAT" },
1563 { "DMIC2L", NULL, "CLK_SYS" },
1564 { "DMIC2R", NULL, "DMIC2DAT" },
1565 { "DMIC2R", NULL, "CLK_SYS" },
1566
1567 { "ADCL", NULL, "AIF1CLK" },
1568 { "ADCL", NULL, "DSP1CLK" },
1569 { "ADCL", NULL, "DSPINTCLK" },
1570
1571 { "ADCR", NULL, "AIF1CLK" },
1572 { "ADCR", NULL, "DSP1CLK" },
1573 { "ADCR", NULL, "DSPINTCLK" },
1574
1575 { "ADCL Mux", "ADC", "ADCL" },
1576 { "ADCL Mux", "DMIC", "DMIC1L" },
1577 { "ADCR Mux", "ADC", "ADCR" },
1578 { "ADCR Mux", "DMIC", "DMIC1R" },
1579
1580 { "DAC1L", NULL, "AIF1CLK" },
1581 { "DAC1L", NULL, "DSP1CLK" },
1582 { "DAC1L", NULL, "DSPINTCLK" },
1583
1584 { "DAC1R", NULL, "AIF1CLK" },
1585 { "DAC1R", NULL, "DSP1CLK" },
1586 { "DAC1R", NULL, "DSPINTCLK" },
1587
1588 { "DAC2L", NULL, "AIF2CLK" },
1589 { "DAC2L", NULL, "DSP2CLK" },
1590 { "DAC2L", NULL, "DSPINTCLK" },
1591
1592 { "DAC2R", NULL, "AIF2DACR" },
1593 { "DAC2R", NULL, "AIF2CLK" },
1594 { "DAC2R", NULL, "DSP2CLK" },
1595 { "DAC2R", NULL, "DSPINTCLK" },
1596
1597 { "TOCLK", NULL, "CLK_SYS" },
1598
5567d8c6
MB		 1599 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1600 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1601 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1602
1603 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1604 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1605 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1606
9e6e96a1
MB		 1607 /* AIF1 outputs */
1608 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1609 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1610 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1611
1612 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1613 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1614 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1615
a3257ba8
MB		 1616 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1617 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1618 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1619
1620 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1621 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1622 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1623
9e6e96a1
MB		 1624 /* Pin level routing for AIF3 */
1625 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1626 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1627 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1628 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1629
9e6e96a1
MB		 1630 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1631 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1632 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1633 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1634 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1635 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1636 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1637
1638 /* DAC1 inputs */
9e6e96a1
MB		 1639 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1640 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1641 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1642 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1643 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1644
9e6e96a1
MB		 1645 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1646 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1647 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1648 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1649 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1650
1651 /* DAC2/AIF2 outputs */
1652 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1653 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1654 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1655 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1656 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1657 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1658
1659 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1660 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1661 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1662 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1663 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1664 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1665
7f94de48
MB		 1666 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1667 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1668 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1669 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1670
9e6e96a1
MB		 1671 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1672
1673 /* AIF3 output */
1674 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1675 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1676 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1677 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1678 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1679 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1680 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1681 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1682
1683 /* Sidetone */
1684 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1685 { "Left Sidetone", "DMIC2", "DMIC2L" },
1686 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1687 { "Right Sidetone", "DMIC2", "DMIC2R" },
1688
1689 /* Output stages */
1690 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1691 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1692
1693 { "SPKL", "DAC1 Switch", "DAC1L" },
1694 { "SPKL", "DAC2 Switch", "DAC2L" },
1695
1696 { "SPKR", "DAC1 Switch", "DAC1R" },
1697 { "SPKR", "DAC2 Switch", "DAC2R" },
1698
1699 { "Left Headphone Mux", "DAC", "DAC1L" },
1700 { "Right Headphone Mux", "DAC", "DAC1R" },
1701};
1702
173efa09
DP		 1703static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1704 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1705 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1706 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1707 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1708 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1709 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1710 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1711 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1712};
1713
1714static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1715 { "DAC1L", NULL, "DAC1L Mixer" },
1716 { "DAC1R", NULL, "DAC1R Mixer" },
1717 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1718 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1719};
1720
6ed8f148
MB		 1721static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1722 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1723 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1724 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1725 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1726 { "MICBIAS1", NULL, "CLK_SYS" },
1727 { "MICBIAS1", NULL, "MICBIAS Supply" },
1728 { "MICBIAS2", NULL, "CLK_SYS" },
1729 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1730};
1731
c4431df0
MB		 1732static const struct snd_soc_dapm_route wm8994_intercon[] = {
1733 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1734 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1735 { "MICBIAS1", NULL, "VMID" },
1736 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1737};
1738
1739static const struct snd_soc_dapm_route wm8958_intercon[] = {
1740 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1741 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1742
1743 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1744 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1745 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1746 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1747
1748 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1749 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1750
1751 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1752};
1753
9e6e96a1
MB		 1754/* The size in bits of the FLL divide multiplied by 10
1755 * to allow rounding later */
1756#define FIXED_FLL_SIZE ((1 << 16) * 10)
1757
1758struct fll_div {
1759 u16 outdiv;
1760 u16 n;
1761 u16 k;
1762 u16 clk_ref_div;
1763 u16 fll_fratio;
1764};
1765
1766static int wm8994_get_fll_config(struct fll_div *fll,
1767 int freq_in, int freq_out)
1768{
1769 u64 Kpart;
1770 unsigned int K, Ndiv, Nmod;
1771
1772 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1773
1774 /* Scale the input frequency down to <= 13.5MHz */
1775 fll->clk_ref_div = 0;
1776 while (freq_in > 13500000) {
1777 fll->clk_ref_div++;
1778 freq_in /= 2;
1779
1780 if (fll->clk_ref_div > 3)
1781 return -EINVAL;
1782 }
1783 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1784
1785 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1786 fll->outdiv = 3;
1787 while (freq_out * (fll->outdiv + 1) < 90000000) {
1788 fll->outdiv++;
1789 if (fll->outdiv > 63)
1790 return -EINVAL;
1791 }
1792 freq_out *= fll->outdiv + 1;
1793 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1794
1795 if (freq_in > 1000000) {
1796 fll->fll_fratio = 0;
7d48a6ac
MB		 1797 } else if (freq_in > 256000) {
1798 fll->fll_fratio = 1;
1799 freq_in *= 2;
1800 } else if (freq_in > 128000) {
1801 fll->fll_fratio = 2;
1802 freq_in *= 4;
1803 } else if (freq_in > 64000) {
9e6e96a1
MB		 1804 fll->fll_fratio = 3;
1805 freq_in *= 8;
7d48a6ac
MB		 1806 } else {
1807 fll->fll_fratio = 4;
1808 freq_in *= 16;
9e6e96a1
MB		 1809 }
1810 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1811
1812 /* Now, calculate N.K */
1813 Ndiv = freq_out / freq_in;
1814
1815 fll->n = Ndiv;
1816 Nmod = freq_out % freq_in;
1817 pr_debug("Nmod=%d\n", Nmod);
1818
1819 /* Calculate fractional part - scale up so we can round. */
1820 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1821
1822 do_div(Kpart, freq_in);
1823
1824 K = Kpart & 0xFFFFFFFF;
1825
1826 if ((K % 10) >= 5)
1827 K += 5;
1828
1829 /* Move down to proper range now rounding is done */
1830 fll->k = K / 10;
1831
1832 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1833
1834 return 0;
1835}
1836
f0fba2ad 1837static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1838 unsigned int freq_in, unsigned int freq_out)
1839{
b2c812e2 1840 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1841 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1842 int reg_offset, ret;
1843 struct fll_div fll;
1844 u16 reg, aif1, aif2;
c7ebf932 1845 unsigned long timeout;
4b7ed83a 1846 bool was_enabled;
9e6e96a1
MB		 1847
1848 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1849 & WM8994_AIF1CLK_ENA;
1850
1851 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1852 & WM8994_AIF2CLK_ENA;
1853
1854 switch (id) {
1855 case WM8994_FLL1:
1856 reg_offset = 0;
1857 id = 0;
1858 break;
1859 case WM8994_FLL2:
1860 reg_offset = 0x20;
1861 id = 1;
1862 break;
1863 default:
1864 return -EINVAL;
1865 }
1866
4b7ed83a
MB		 1867 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1868 was_enabled = reg & WM8994_FLL1_ENA;
1869
136ff2a2 1870 switch (src) {
7add84aa
MB		 1871 case 0:
1872 /* Allow no source specification when stopping */
1873 if (freq_out)
1874 return -EINVAL;
4514e899 1875 src = wm8994->fll[id].src;
7add84aa 1876 break;
136ff2a2
MB		 1877 case WM8994_FLL_SRC_MCLK1:
1878 case WM8994_FLL_SRC_MCLK2:
1879 case WM8994_FLL_SRC_LRCLK:
1880 case WM8994_FLL_SRC_BCLK:
1881 break;
1882 default:
1883 return -EINVAL;
1884 }
1885
9e6e96a1
MB		 1886 /* Are we changing anything? */
1887 if (wm8994->fll[id].src == src &&
1888 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1889 return 0;
1890
1891 /* If we're stopping the FLL redo the old config - no
1892 * registers will actually be written but we avoid GCC flow
1893 * analysis bugs spewing warnings.
1894 */
1895 if (freq_out)
1896 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1897 else
1898 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1899 wm8994->fll[id].out);
1900 if (ret < 0)
1901 return ret;
1902
1903 /* Gate the AIF clocks while we reclock */
1904 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1905 WM8994_AIF1CLK_ENA, 0);
1906 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1907 WM8994_AIF2CLK_ENA, 0);
1908
1909 /* We always need to disable the FLL while reconfiguring */
1910 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1911 WM8994_FLL1_ENA, 0);
1912
1913 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1914 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1915 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1916 WM8994_FLL1_OUTDIV_MASK |
1917 WM8994_FLL1_FRATIO_MASK, reg);
1918
b16db745
MB		 1919 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1920 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 1921
1922 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1923 WM8994_FLL1_N_MASK,
1924 fll.n << WM8994_FLL1_N_SHIFT);
1925
1926 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1927 WM8994_FLL1_REFCLK_DIV_MASK |
1928 WM8994_FLL1_REFCLK_SRC_MASK,
1929 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1930 (src - 1));
9e6e96a1 1931
f0f5039c
MB		 1932 /* Clear any pending completion from a previous failure */
1933 try_wait_for_completion(&wm8994->fll_locked[id]);
1934
9e6e96a1
MB		 1935 /* Enable (with fractional mode if required) */
1936 if (freq_out) {
4b7ed83a
MB		 1937 /* Enable VMID if we need it */
1938 if (!was_enabled) {
af6b6fe4
MB		 1939 active_reference(codec);
1940
4b7ed83a
MB		 1941 switch (control->type) {
1942 case WM8994:
1943 vmid_reference(codec);
1944 break;
1945 case WM8958:
1946 if (wm8994->revision < 1)
1947 vmid_reference(codec);
1948 break;
1949 default:
1950 break;
1951 }
1952 }
1953
9e6e96a1
MB		 1954 if (fll.k)
1955 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1956 else
1957 reg = WM8994_FLL1_ENA;
1958 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1959 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1960 reg);
8e9ddf81 1961
c7ebf932
MB		 1962 if (wm8994->fll_locked_irq) {
1963 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1964 msecs_to_jiffies(10));
1965 if (timeout == 0)
1966 dev_warn(codec->dev,
1967 "Timed out waiting for FLL lock\n");
1968 } else {
1969 msleep(5);
1970 }
4b7ed83a
MB		 1971 } else {
1972 if (was_enabled) {
1973 switch (control->type) {
1974 case WM8994:
1975 vmid_dereference(codec);
1976 break;
1977 case WM8958:
1978 if (wm8994->revision < 1)
1979 vmid_dereference(codec);
1980 break;
1981 default:
1982 break;
1983 }
af6b6fe4
MB		 1984
1985 active_dereference(codec);
4b7ed83a 1986 }
9e6e96a1
MB		 1987 }
1988
1989 wm8994->fll[id].in = freq_in;
1990 wm8994->fll[id].out = freq_out;
136ff2a2 1991 wm8994->fll[id].src = src;
9e6e96a1
MB		 1992
1993 /* Enable any gated AIF clocks */
1994 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1995 WM8994_AIF1CLK_ENA, aif1);
1996 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1997 WM8994_AIF2CLK_ENA, aif2);
1998
1999 configure_clock(codec);
2000
2001 return 0;
2002}
2003
c7ebf932
MB		 2004static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2005{
2006 struct completion *completion = data;
2007
2008 complete(completion);
2009
2010 return IRQ_HANDLED;
2011}
f0fba2ad 2012
66b47fdb
MB		 2013static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2014
f0fba2ad
LG		 2015static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2016 unsigned int freq_in, unsigned int freq_out)
2017{
2018 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2019}
2020
9e6e96a1
MB		 2021static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2022 int clk_id, unsigned int freq, int dir)
2023{
2024 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2025 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2026 int i;
9e6e96a1
MB		 2027
2028 switch (dai->id) {
2029 case 1:
2030 case 2:
2031 break;
2032
2033 default:
2034 /* AIF3 shares clocking with AIF1/2 */
2035 return -EINVAL;
2036 }
2037
2038 switch (clk_id) {
2039 case WM8994_SYSCLK_MCLK1:
2040 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2041 wm8994->mclk[0] = freq;
2042 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2043 dai->id, freq);
2044 break;
2045
2046 case WM8994_SYSCLK_MCLK2:
2047 /* TODO: Set GPIO AF */
2048 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2049 wm8994->mclk[1] = freq;
2050 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2051 dai->id, freq);
2052 break;
2053
2054 case WM8994_SYSCLK_FLL1:
2055 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2056 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2057 break;
2058
2059 case WM8994_SYSCLK_FLL2:
2060 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2061 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2062 break;
2063
66b47fdb
MB		 2064 case WM8994_SYSCLK_OPCLK:
2065 /* Special case - a division (times 10) is given and
2066 * no effect on main clocking.
2067 */
2068 if (freq) {
2069 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2070 if (opclk_divs[i] == freq)
2071 break;
2072 if (i == ARRAY_SIZE(opclk_divs))
2073 return -EINVAL;
2074 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2075 WM8994_OPCLK_DIV_MASK, i);
2076 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2077 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2078 } else {
2079 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2080 WM8994_OPCLK_ENA, 0);
2081 }
2082
9e6e96a1
MB		 2083 default:
2084 return -EINVAL;
2085 }
2086
2087 configure_clock(codec);
2088
2089 return 0;
2090}
2091
2092static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2093 enum snd_soc_bias_level level)
2094{
b6b05691 2095 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2096 struct wm8994 *control = wm8994->wm8994;
b6b05691 2097
5f2f3890
MB		 2098 wm_hubs_set_bias_level(codec, level);
2099
9e6e96a1
MB		 2100 switch (level) {
2101 case SND_SOC_BIAS_ON:
2102 break;
2103
2104 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2105 /* MICBIAS into regulating mode */
2106 switch (control->type) {
2107 case WM8958:
2108 case WM1811:
2109 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2110 WM8958_MICB1_MODE, 0);
2111 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2112 WM8958_MICB2_MODE, 0);
2113 break;
2114 default:
2115 break;
2116 }
af6b6fe4
MB		 2117
2118 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2119 active_reference(codec);
9e6e96a1
MB		 2120 break;
2121
2122 case SND_SOC_BIAS_STANDBY:
ce6120cc 2123 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2
MB		 2124 switch (control->type) {
2125 case WM8994:
2126 if (wm8994->revision < 4) {
2127 /* Tweak DC servo and DSP
2128 * configuration for improved
2129 * performance. */
2130 snd_soc_write(codec, 0x102, 0x3);
2131 snd_soc_write(codec, 0x56, 0x3);
2132 snd_soc_write(codec, 0x817, 0);
2133 snd_soc_write(codec, 0x102, 0);
2134 }
2135 break;
2136
2137 case WM8958:
2138 if (wm8994->revision == 0) {
2139 /* Optimise performance for rev A */
2140 snd_soc_write(codec, 0x102, 0x3);
2141 snd_soc_write(codec, 0xcb, 0x81);
2142 snd_soc_write(codec, 0x817, 0);
2143 snd_soc_write(codec, 0x102, 0);
2144
2145 snd_soc_update_bits(codec,
2146 WM8958_CHARGE_PUMP_2,
2147 WM8958_CP_DISCH,
2148 WM8958_CP_DISCH);
2149 }
2150 break;
81204c84
MB		 2151
2152 case WM1811:
2153 if (wm8994->revision < 2) {
2154 snd_soc_write(codec, 0x102, 0x3);
2155 snd_soc_write(codec, 0x5d, 0x7e);
2156 snd_soc_write(codec, 0x5e, 0x0);
2157 snd_soc_write(codec, 0x102, 0x0);
2158 }
2159 break;
b6b05691 2160 }
9e6e96a1
MB		 2161
2162 /* Discharge LINEOUT1 & 2 */
2163 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2164 WM8994_LINEOUT1_DISCH |
2165 WM8994_LINEOUT2_DISCH,
2166 WM8994_LINEOUT1_DISCH |
2167 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2168 }
2169
af6b6fe4
MB		 2170 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2171 active_dereference(codec);
2172
500fa30e
MB		 2173 /* MICBIAS into bypass mode on newer devices */
2174 switch (control->type) {
2175 case WM8958:
2176 case WM1811:
2177 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2178 WM8958_MICB1_MODE,
2179 WM8958_MICB1_MODE);
2180 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2181 WM8958_MICB2_MODE,
2182 WM8958_MICB2_MODE);
2183 break;
2184 default:
2185 break;
2186 }
9e6e96a1
MB		 2187 break;
2188
2189 case SND_SOC_BIAS_OFF:
4105ab84 2190 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2191 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2192 break;
2193 }
5f2f3890 2194
ce6120cc 2195 codec->dapm.bias_level = level;
af6b6fe4 2196
9e6e96a1
MB		 2197 return 0;
2198}
2199
2200static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2201{
2202 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2203 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2204 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2205 int ms_reg;
2206 int aif1_reg;
2207 int ms = 0;
2208 int aif1 = 0;
2209
2210 switch (dai->id) {
2211 case 1:
2212 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2213 aif1_reg = WM8994_AIF1_CONTROL_1;
2214 break;
2215 case 2:
2216 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2217 aif1_reg = WM8994_AIF2_CONTROL_1;
2218 break;
2219 default:
2220 return -EINVAL;
2221 }
2222
2223 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2224 case SND_SOC_DAIFMT_CBS_CFS:
2225 break;
2226 case SND_SOC_DAIFMT_CBM_CFM:
2227 ms = WM8994_AIF1_MSTR;
2228 break;
2229 default:
2230 return -EINVAL;
2231 }
2232
2233 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2234 case SND_SOC_DAIFMT_DSP_B:
2235 aif1 |= WM8994_AIF1_LRCLK_INV;
2236 case SND_SOC_DAIFMT_DSP_A:
2237 aif1 |= 0x18;
2238 break;
2239 case SND_SOC_DAIFMT_I2S:
2240 aif1 |= 0x10;
2241 break;
2242 case SND_SOC_DAIFMT_RIGHT_J:
2243 break;
2244 case SND_SOC_DAIFMT_LEFT_J:
2245 aif1 |= 0x8;
2246 break;
2247 default:
2248 return -EINVAL;
2249 }
2250
2251 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2252 case SND_SOC_DAIFMT_DSP_A:
2253 case SND_SOC_DAIFMT_DSP_B:
2254 /* frame inversion not valid for DSP modes */
2255 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2256 case SND_SOC_DAIFMT_NB_NF:
2257 break;
2258 case SND_SOC_DAIFMT_IB_NF:
2259 aif1 |= WM8994_AIF1_BCLK_INV;
2260 break;
2261 default:
2262 return -EINVAL;
2263 }
2264 break;
2265
2266 case SND_SOC_DAIFMT_I2S:
2267 case SND_SOC_DAIFMT_RIGHT_J:
2268 case SND_SOC_DAIFMT_LEFT_J:
2269 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2270 case SND_SOC_DAIFMT_NB_NF:
2271 break;
2272 case SND_SOC_DAIFMT_IB_IF:
2273 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2274 break;
2275 case SND_SOC_DAIFMT_IB_NF:
2276 aif1 |= WM8994_AIF1_BCLK_INV;
2277 break;
2278 case SND_SOC_DAIFMT_NB_IF:
2279 aif1 |= WM8994_AIF1_LRCLK_INV;
2280 break;
2281 default:
2282 return -EINVAL;
2283 }
2284 break;
2285 default:
2286 return -EINVAL;
2287 }
2288
c4431df0
MB		 2289 /* The AIF2 format configuration needs to be mirrored to AIF3
2290 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2291 switch (control->type) {
2292 case WM1811:
2293 case WM8958:
2294 if (dai->id == 2)
2295 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2296 WM8994_AIF1_LRCLK_INV |
2297 WM8958_AIF3_FMT_MASK, aif1);
2298 break;
2299
2300 default:
2301 break;
2302 }
c4431df0 2303
9e6e96a1
MB		 2304 snd_soc_update_bits(codec, aif1_reg,
2305 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2306 WM8994_AIF1_FMT_MASK,
2307 aif1);
2308 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2309 ms);
2310
2311 return 0;
2312}
2313
2314static struct {
2315 int val, rate;
2316} srs[] = {
2317 { 0, 8000 },
2318 { 1, 11025 },
2319 { 2, 12000 },
2320 { 3, 16000 },
2321 { 4, 22050 },
2322 { 5, 24000 },
2323 { 6, 32000 },
2324 { 7, 44100 },
2325 { 8, 48000 },
2326 { 9, 88200 },
2327 { 10, 96000 },
2328};
2329
2330static int fs_ratios[] = {
2331 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2332};
2333
2334static int bclk_divs[] = {
2335 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2336 640, 880, 960, 1280, 1760, 1920
2337};
2338
2339static int wm8994_hw_params(struct snd_pcm_substream *substream,
2340 struct snd_pcm_hw_params *params,
2341 struct snd_soc_dai *dai)
2342{
2343 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2344 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2345 int aif1_reg;
b1e43d93 2346 int aif2_reg;
9e6e96a1
MB		 2347 int bclk_reg;
2348 int lrclk_reg;
2349 int rate_reg;
2350 int aif1 = 0;
b1e43d93 2351 int aif2 = 0;
9e6e96a1
MB		 2352 int bclk = 0;
2353 int lrclk = 0;
2354 int rate_val = 0;
2355 int id = dai->id - 1;
2356
2357 int i, cur_val, best_val, bclk_rate, best;
2358
2359 switch (dai->id) {
2360 case 1:
2361 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2362 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2363 bclk_reg = WM8994_AIF1_BCLK;
2364 rate_reg = WM8994_AIF1_RATE;
2365 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2366 wm8994->lrclk_shared[0]) {
9e6e96a1 2367 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2368 } else {
9e6e96a1 2369 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2370 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2371 }
9e6e96a1
MB		 2372 break;
2373 case 2:
2374 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2375 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2376 bclk_reg = WM8994_AIF2_BCLK;
2377 rate_reg = WM8994_AIF2_RATE;
2378 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2379 wm8994->lrclk_shared[1]) {
9e6e96a1 2380 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2381 } else {
9e6e96a1 2382 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2383 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2384 }
9e6e96a1
MB		 2385 break;
2386 default:
2387 return -EINVAL;
2388 }
2389
2390 bclk_rate = params_rate(params) * 2;
2391 switch (params_format(params)) {
2392 case SNDRV_PCM_FORMAT_S16_LE:
2393 bclk_rate *= 16;
2394 break;
2395 case SNDRV_PCM_FORMAT_S20_3LE:
2396 bclk_rate *= 20;
2397 aif1 |= 0x20;
2398 break;
2399 case SNDRV_PCM_FORMAT_S24_LE:
2400 bclk_rate *= 24;
2401 aif1 |= 0x40;
2402 break;
2403 case SNDRV_PCM_FORMAT_S32_LE:
2404 bclk_rate *= 32;
2405 aif1 |= 0x60;
2406 break;
2407 default:
2408 return -EINVAL;
2409 }
2410
2411 /* Try to find an appropriate sample rate; look for an exact match. */
2412 for (i = 0; i < ARRAY_SIZE(srs); i++)
2413 if (srs[i].rate == params_rate(params))
2414 break;
2415 if (i == ARRAY_SIZE(srs))
2416 return -EINVAL;
2417 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2418
2419 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2420 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2421 dai->id, wm8994->aifclk[id], bclk_rate);
2422
b1e43d93
MB		 2423 if (params_channels(params) == 1 &&
2424 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2425 aif2 |= WM8994_AIF1_MONO;
2426
9e6e96a1
MB		 2427 if (wm8994->aifclk[id] == 0) {
2428 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2429 return -EINVAL;
2430 }
2431
2432 /* AIFCLK/fs ratio; look for a close match in either direction */
2433 best = 0;
2434 best_val = abs((fs_ratios[0] * params_rate(params))
2435 - wm8994->aifclk[id]);
2436 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2437 cur_val = abs((fs_ratios[i] * params_rate(params))
2438 - wm8994->aifclk[id]);
2439 if (cur_val >= best_val)
2440 continue;
2441 best = i;
2442 best_val = cur_val;
2443 }
2444 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2445 dai->id, fs_ratios[best]);
2446 rate_val |= best;
2447
2448 /* We may not get quite the right frequency if using
2449 * approximate clocks so look for the closest match that is
2450 * higher than the target (we need to ensure that there enough
2451 * BCLKs to clock out the samples).
2452 */
2453 best = 0;
2454 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2455 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2456 if (cur_val < 0) /* BCLK table is sorted */
2457 break;
2458 best = i;
2459 }
07cd8ada 2460 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2461 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2462 bclk_divs[best], bclk_rate);
2463 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2464
2465 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2466 if (!lrclk) {
2467 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2468 bclk_rate);
2469 return -EINVAL;
2470 }
9e6e96a1
MB		 2471 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2472 lrclk, bclk_rate / lrclk);
2473
2474 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2475 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2476 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2477 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2478 lrclk);
2479 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2480 WM8994_AIF1CLK_RATE_MASK, rate_val);
2481
2482 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2483 switch (dai->id) {
2484 case 1:
2485 wm8994->dac_rates[0] = params_rate(params);
2486 wm8994_set_retune_mobile(codec, 0);
2487 wm8994_set_retune_mobile(codec, 1);
2488 break;
2489 case 2:
2490 wm8994->dac_rates[1] = params_rate(params);
2491 wm8994_set_retune_mobile(codec, 2);
2492 break;
2493 }
2494 }
2495
2496 return 0;
2497}
2498
c4431df0
MB		 2499static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2500 struct snd_pcm_hw_params *params,
2501 struct snd_soc_dai *dai)
2502{
2503 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2504 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2505 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2506 int aif1_reg;
2507 int aif1 = 0;
2508
2509 switch (dai->id) {
2510 case 3:
2511 switch (control->type) {
81204c84 2512 case WM1811:
c4431df0
MB		 2513 case WM8958:
2514 aif1_reg = WM8958_AIF3_CONTROL_1;
2515 break;
2516 default:
2517 return 0;
2518 }
2519 default:
2520 return 0;
2521 }
2522
2523 switch (params_format(params)) {
2524 case SNDRV_PCM_FORMAT_S16_LE:
2525 break;
2526 case SNDRV_PCM_FORMAT_S20_3LE:
2527 aif1 |= 0x20;
2528 break;
2529 case SNDRV_PCM_FORMAT_S24_LE:
2530 aif1 |= 0x40;
2531 break;
2532 case SNDRV_PCM_FORMAT_S32_LE:
2533 aif1 |= 0x60;
2534 break;
2535 default:
2536 return -EINVAL;
2537 }
2538
2539 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2540}
2541
7d02173c
MB		 2542static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2543 struct snd_soc_dai *dai)
2544{
2545 struct snd_soc_codec *codec = dai->codec;
2546 int rate_reg = 0;
2547
2548 switch (dai->id) {
2549 case 1:
2550 rate_reg = WM8994_AIF1_RATE;
2551 break;
2552 case 2:
c527e6aa 2553 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2554 break;
2555 default:
2556 break;
2557 }
2558
2559 /* If the DAI is idle then configure the divider tree for the
2560 * lowest output rate to save a little power if the clock is
2561 * still active (eg, because it is system clock).
2562 */
2563 if (rate_reg && !dai->playback_active && !dai->capture_active)
2564 snd_soc_update_bits(codec, rate_reg,
2565 WM8994_AIF1_SR_MASK |
2566 WM8994_AIF1CLK_RATE_MASK, 0x9);
2567}
2568
9e6e96a1
MB		 2569static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2570{
2571 struct snd_soc_codec *codec = codec_dai->codec;
2572 int mute_reg;
2573 int reg;
2574
2575 switch (codec_dai->id) {
2576 case 1:
2577 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2578 break;
2579 case 2:
2580 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2581 break;
2582 default:
2583 return -EINVAL;
2584 }
2585
2586 if (mute)
2587 reg = WM8994_AIF1DAC1_MUTE;
2588 else
2589 reg = 0;
2590
2591 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2592
2593 return 0;
2594}
2595
778a76e2
MB		 2596static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2597{
2598 struct snd_soc_codec *codec = codec_dai->codec;
2599 int reg, val, mask;
2600
2601 switch (codec_dai->id) {
2602 case 1:
2603 reg = WM8994_AIF1_MASTER_SLAVE;
2604 mask = WM8994_AIF1_TRI;
2605 break;
2606 case 2:
2607 reg = WM8994_AIF2_MASTER_SLAVE;
2608 mask = WM8994_AIF2_TRI;
2609 break;
2610 case 3:
2611 reg = WM8994_POWER_MANAGEMENT_6;
2612 mask = WM8994_AIF3_TRI;
2613 break;
2614 default:
2615 return -EINVAL;
2616 }
2617
2618 if (tristate)
2619 val = mask;
2620 else
2621 val = 0;
2622
78b3fb46 2623 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2624}
2625
d09f3ecf
MB		 2626static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2627{
2628 struct snd_soc_codec *codec = dai->codec;
2629
2630 /* Disable the pulls on the AIF if we're using it to save power. */
2631 snd_soc_update_bits(codec, WM8994_GPIO_3,
2632 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2633 snd_soc_update_bits(codec, WM8994_GPIO_4,
2634 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2635 snd_soc_update_bits(codec, WM8994_GPIO_5,
2636 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2637
2638 return 0;
2639}
2640
9e6e96a1
MB		 2641#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2642
2643#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2644 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2645
85e7652d 2646static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2647 .set_sysclk = wm8994_set_dai_sysclk,
2648 .set_fmt = wm8994_set_dai_fmt,
2649 .hw_params = wm8994_hw_params,
7d02173c 2650 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2651 .digital_mute = wm8994_aif_mute,
2652 .set_pll = wm8994_set_fll,
778a76e2 2653 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2654};
2655
85e7652d 2656static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2657 .set_sysclk = wm8994_set_dai_sysclk,
2658 .set_fmt = wm8994_set_dai_fmt,
2659 .hw_params = wm8994_hw_params,
7d02173c 2660 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2661 .digital_mute = wm8994_aif_mute,
2662 .set_pll = wm8994_set_fll,
778a76e2
MB		 2663 .set_tristate = wm8994_set_tristate,
2664};
2665
85e7652d 2666static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2667 .hw_params = wm8994_aif3_hw_params,
778a76e2 2668 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2669};
2670
f0fba2ad 2671static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2672 {
f0fba2ad 2673 .name = "wm8994-aif1",
8c7f78b3 2674 .id = 1,
9e6e96a1
MB		 2675 .playback = {
2676 .stream_name = "AIF1 Playback",
b1e43d93 2677 .channels_min = 1,
9e6e96a1
MB		 2678 .channels_max = 2,
2679 .rates = WM8994_RATES,
2680 .formats = WM8994_FORMATS,
99b0292d 2681 .sig_bits = 24,
9e6e96a1
MB		 2682 },
2683 .capture = {
2684 .stream_name = "AIF1 Capture",
b1e43d93 2685 .channels_min = 1,
9e6e96a1
MB		 2686 .channels_max = 2,
2687 .rates = WM8994_RATES,
2688 .formats = WM8994_FORMATS,
99b0292d 2689 .sig_bits = 24,
9e6e96a1
MB		 2690 },
2691 .ops = &wm8994_aif1_dai_ops,
2692 },
2693 {
f0fba2ad 2694 .name = "wm8994-aif2",
8c7f78b3 2695 .id = 2,
9e6e96a1
MB		 2696 .playback = {
2697 .stream_name = "AIF2 Playback",
b1e43d93 2698 .channels_min = 1,
9e6e96a1
MB		 2699 .channels_max = 2,
2700 .rates = WM8994_RATES,
2701 .formats = WM8994_FORMATS,
99b0292d 2702 .sig_bits = 24,
9e6e96a1
MB		 2703 },
2704 .capture = {
2705 .stream_name = "AIF2 Capture",
b1e43d93 2706 .channels_min = 1,
9e6e96a1
MB		 2707 .channels_max = 2,
2708 .rates = WM8994_RATES,
2709 .formats = WM8994_FORMATS,
99b0292d 2710 .sig_bits = 24,
9e6e96a1 2711 },
d09f3ecf 2712 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2713 .ops = &wm8994_aif2_dai_ops,
2714 },
2715 {
f0fba2ad 2716 .name = "wm8994-aif3",
8c7f78b3 2717 .id = 3,
9e6e96a1
MB		 2718 .playback = {
2719 .stream_name = "AIF3 Playback",
b1e43d93 2720 .channels_min = 1,
9e6e96a1
MB		 2721 .channels_max = 2,
2722 .rates = WM8994_RATES,
2723 .formats = WM8994_FORMATS,
99b0292d 2724 .sig_bits = 24,
9e6e96a1 2725 },
a8462bde 2726 .capture = {
9e6e96a1 2727 .stream_name = "AIF3 Capture",
b1e43d93 2728 .channels_min = 1,
9e6e96a1
MB		 2729 .channels_max = 2,
2730 .rates = WM8994_RATES,
2731 .formats = WM8994_FORMATS,
99b0292d
MB		 2732 .sig_bits = 24,
2733 },
778a76e2 2734 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2735 }
2736};
9e6e96a1
MB		 2737
2738#ifdef CONFIG_PM
4752a887 2739static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 2740{
b2c812e2 2741 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2742 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2743 int i, ret;
2744
ca629928
MB		 2745 switch (control->type) {
2746 case WM8994:
2747 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2748 break;
81204c84 2749 case WM1811:
af6b6fe4
MB		 2750 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2751 WM1811_JACKDET_MODE_MASK, 0);
2752 /* Fall through */
ca629928
MB		 2753 case WM8958:
2754 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2755 WM8958_MICD_ENA, 0);
2756 break;
2757 }
2758
9e6e96a1
MB		 2759 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2760 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2761 sizeof(struct wm8994_fll_config));
f0fba2ad 2762 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2763 if (ret < 0)
2764 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2765 i + 1, ret);
2766 }
2767
2768 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2769
2770 return 0;
2771}
2772
4752a887 2773static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 2774{
b2c812e2 2775 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2776 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2777 int i, ret;
c52fd021
DP		 2778 unsigned int val, mask;
2779
2780 if (wm8994->revision < 4) {
2781 /* force a HW read */
d9a7666f
MB		 2782 ret = regmap_read(control->regmap,
2783 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2784
2785 /* modify the cache only */
2786 codec->cache_only = 1;
2787 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2788 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2789 val &= mask;
2790 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2791 mask, val);
2792 codec->cache_only = 0;
2793 }
9e6e96a1 2794
9e6e96a1 2795 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2796 if (!wm8994->fll_suspend[i].out)
2797 continue;
2798
f0fba2ad 2799 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2800 wm8994->fll_suspend[i].src,
2801 wm8994->fll_suspend[i].in,
2802 wm8994->fll_suspend[i].out);
2803 if (ret < 0)
2804 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2805 i + 1, ret);
2806 }
2807
ca629928
MB		 2808 switch (control->type) {
2809 case WM8994:
2810 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2811 snd_soc_update_bits(codec, WM8994_MICBIAS,
2812 WM8994_MICD_ENA, WM8994_MICD_ENA);
2813 break;
81204c84 2814 case WM1811:
af6b6fe4
MB		 2815 if (wm8994->jackdet && wm8994->jack_cb) {
2816 /* Restart from idle */
2817 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2818 WM1811_JACKDET_MODE_MASK,
2819 WM1811_JACKDET_MODE_JACK);
2820 break;
2821 }
ca629928
MB		 2822 case WM8958:
2823 if (wm8994->jack_cb)
2824 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2825 WM8958_MICD_ENA, WM8958_MICD_ENA);
2826 break;
2827 }
2828
9e6e96a1
MB		 2829 return 0;
2830}
2831#else
4752a887
MB		 2832#define wm8994_codec_suspend NULL
2833#define wm8994_codec_resume NULL
9e6e96a1
MB		 2834#endif
2835
2836static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2837{
f0fba2ad 2838 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2839 struct wm8994_pdata *pdata = wm8994->pdata;
2840 struct snd_kcontrol_new controls[] = {
2841 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2842 wm8994->retune_mobile_enum,
2843 wm8994_get_retune_mobile_enum,
2844 wm8994_put_retune_mobile_enum),
2845 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2846 wm8994->retune_mobile_enum,
2847 wm8994_get_retune_mobile_enum,
2848 wm8994_put_retune_mobile_enum),
2849 SOC_ENUM_EXT("AIF2 EQ Mode",
2850 wm8994->retune_mobile_enum,
2851 wm8994_get_retune_mobile_enum,
2852 wm8994_put_retune_mobile_enum),
2853 };
2854 int ret, i, j;
2855 const char **t;
2856
2857 /* We need an array of texts for the enum API but the number
2858 * of texts is likely to be less than the number of
2859 * configurations due to the sample rate dependency of the
2860 * configurations. */
2861 wm8994->num_retune_mobile_texts = 0;
2862 wm8994->retune_mobile_texts = NULL;
2863 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2864 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2865 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2866 wm8994->retune_mobile_texts[j]) == 0)
2867 break;
2868 }
2869
2870 if (j != wm8994->num_retune_mobile_texts)
2871 continue;
2872
2873 /* Expand the array... */
2874 t = krealloc(wm8994->retune_mobile_texts,
2875 sizeof(char *) *
2876 (wm8994->num_retune_mobile_texts + 1),
2877 GFP_KERNEL);
2878 if (t == NULL)
2879 continue;
2880
2881 /* ...store the new entry... */
2882 t[wm8994->num_retune_mobile_texts] =
2883 pdata->retune_mobile_cfgs[i].name;
2884
2885 /* ...and remember the new version. */
2886 wm8994->num_retune_mobile_texts++;
2887 wm8994->retune_mobile_texts = t;
2888 }
2889
2890 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2891 wm8994->num_retune_mobile_texts);
2892
2893 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2894 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2895
022658be 2896 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2897 ARRAY_SIZE(controls));
2898 if (ret != 0)
f0fba2ad 2899 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2900 "Failed to add ReTune Mobile controls: %d\n", ret);
2901}
2902
2903static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2904{
f0fba2ad 2905 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2906 struct wm8994_pdata *pdata = wm8994->pdata;
2907 int ret, i;
2908
2909 if (!pdata)
2910 return;
2911
2912 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2913 pdata->lineout2_diff,
2914 pdata->lineout1fb,
2915 pdata->lineout2fb,
2916 pdata->jd_scthr,
2917 pdata->jd_thr,
2918 pdata->micbias1_lvl,
2919 pdata->micbias2_lvl);
2920
2921 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2922
2923 if (pdata->num_drc_cfgs) {
2924 struct snd_kcontrol_new controls[] = {
2925 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2926 wm8994_get_drc_enum, wm8994_put_drc_enum),
2927 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2928 wm8994_get_drc_enum, wm8994_put_drc_enum),
2929 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2930 wm8994_get_drc_enum, wm8994_put_drc_enum),
2931 };
2932
2933 /* We need an array of texts for the enum API */
7270cebe
MB		 2934 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2935 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2936 if (!wm8994->drc_texts) {
f0fba2ad 2937 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2938 "Failed to allocate %d DRC config texts\n",
2939 pdata->num_drc_cfgs);
2940 return;
2941 }
2942
2943 for (i = 0; i < pdata->num_drc_cfgs; i++)
2944 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2945
2946 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2947 wm8994->drc_enum.texts = wm8994->drc_texts;
2948
022658be 2949 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2950 ARRAY_SIZE(controls));
2951 if (ret != 0)
f0fba2ad 2952 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2953 "Failed to add DRC mode controls: %d\n", ret);
2954
2955 for (i = 0; i < WM8994_NUM_DRC; i++)
2956 wm8994_set_drc(codec, i);
2957 }
2958
2959 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2960 pdata->num_retune_mobile_cfgs);
2961
2962 if (pdata->num_retune_mobile_cfgs)
2963 wm8994_handle_retune_mobile_pdata(wm8994);
2964 else
022658be 2965 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2966 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2967
2968 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2969 if (pdata->micbias[i]) {
2970 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2971 pdata->micbias[i] & 0xffff);
2972 }
2973 }
9e6e96a1
MB		 2974}
2975
88766984
MB		 2976/**
2977 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2978 *
2979 * @codec: WM8994 codec
2980 * @jack: jack to report detection events on
2981 * @micbias: microphone bias to detect on
88766984
MB		 2982 *
2983 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2984 * being used to bring out signals to the processor then only platform
5ab230a7 2985 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2986 * be configured using snd_soc_jack_add_gpios() instead.
2987 *
2988 * Configuration of detection levels is available via the micbias1_lvl
2989 * and micbias2_lvl platform data members.
2990 */
2991int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 2992 int micbias)
88766984 2993{
b2c812e2 2994 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2995 struct wm8994_micdet *micdet;
2a8a856d 2996 struct wm8994 *control = wm8994->wm8994;
87092e3c 2997 int reg, ret;
88766984 2998
87092e3c
MB		 2999 if (control->type != WM8994) {
3000 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3001 return -EINVAL;
87092e3c 3002 }
3a423157 3003
88766984
MB		 3004 switch (micbias) {
3005 case 1:
3006 micdet = &wm8994->micdet[0];
87092e3c
MB		 3007 if (jack)
3008 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3009 "MICBIAS1");
3010 else
3011 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3012 "MICBIAS1");
88766984
MB		 3013 break;
3014 case 2:
3015 micdet = &wm8994->micdet[1];
87092e3c
MB		 3016 if (jack)
3017 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3018 "MICBIAS1");
3019 else
3020 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3021 "MICBIAS1");
88766984
MB		 3022 break;
3023 default:
87092e3c 3024 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3025 return -EINVAL;
87092e3c 3026 }
88766984 3027
87092e3c
MB		 3028 if (ret != 0)
3029 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3030 micbias, ret);
3031
3032 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3033 micbias, jack);
88766984
MB		 3034
3035 /* Store the configuration */
3036 micdet->jack = jack;
87092e3c 3037 micdet->detecting = true;
88766984
MB		 3038
3039 /* If either of the jacks is set up then enable detection */
3040 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3041 reg = WM8994_MICD_ENA;
87092e3c 3042 else
88766984
MB		 3043 reg = 0;
3044
3045 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3046
87092e3c
MB		 3047 snd_soc_dapm_sync(&codec->dapm);
3048
88766984
MB		 3049 return 0;
3050}
3051EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3052
3053static irqreturn_t wm8994_mic_irq(int irq, void *data)
3054{
3055 struct wm8994_priv *priv = data;
f0fba2ad 3056 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3057 int reg;
3058 int report;
3059
7116f452 3060#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3061 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3062#endif
2bbb5d66 3063
88766984
MB		 3064 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3065 if (reg < 0) {
3066 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3067 reg);
3068 return IRQ_HANDLED;
3069 }
3070
3071 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3072
3073 report = 0;
87092e3c
MB		 3074 if (reg & WM8994_MIC1_DET_STS) {
3075 if (priv->micdet[0].detecting)
3076 report = SND_JACK_HEADSET;
3077 }
3078 if (reg & WM8994_MIC1_SHRT_STS) {
3079 if (priv->micdet[0].detecting)
3080 report = SND_JACK_HEADPHONE;
3081 else
3082 report |= SND_JACK_BTN_0;
3083 }
3084 if (report)
3085 priv->micdet[0].detecting = false;
3086 else
3087 priv->micdet[0].detecting = true;
3088
88766984 3089 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3090 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3091
3092 report = 0;
87092e3c
MB		 3093 if (reg & WM8994_MIC2_DET_STS) {
3094 if (priv->micdet[1].detecting)
3095 report = SND_JACK_HEADSET;
3096 }
3097 if (reg & WM8994_MIC2_SHRT_STS) {
3098 if (priv->micdet[1].detecting)
3099 report = SND_JACK_HEADPHONE;
3100 else
3101 report |= SND_JACK_BTN_0;
3102 }
3103 if (report)
3104 priv->micdet[1].detecting = false;
3105 else
3106 priv->micdet[1].detecting = true;
3107
88766984 3108 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3109 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3110
3111 return IRQ_HANDLED;
3112}
3113
821edd2f
MB		 3114/* Default microphone detection handler for WM8958 - the user can
3115 * override this if they wish.
3116 */
3117static void wm8958_default_micdet(u16 status, void *data)
3118{
3119 struct snd_soc_codec *codec = data;
3120 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3121 int report;
821edd2f 3122
a1691343
MB		 3123 dev_dbg(codec->dev, "MICDET %x\n", status);
3124
af6b6fe4 3125 /* Either nothing present or just starting detection */
b00adf76 3126 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3127 if (!wm8994->jackdet) {
3128 /* If nothing present then clear our statuses */
3129 dev_dbg(codec->dev, "Detected open circuit\n");
3130 wm8994->jack_mic = false;
3131 wm8994->mic_detecting = true;
b00adf76 3132
af6b6fe4 3133 wm8958_micd_set_rate(codec);
b00adf76 3134
af6b6fe4
MB		 3135 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3136 wm8994->btn_mask |
3137 SND_JACK_HEADSET);
3138 }
b00adf76
MB		 3139 return;
3140 }
821edd2f 3141
b00adf76
MB		 3142 /* If the measurement is showing a high impedence we've got a
3143 * microphone.
3144 */
157a75e6 3145 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3146 dev_dbg(codec->dev, "Detected microphone\n");
3147
157a75e6 3148 wm8994->mic_detecting = false;
b00adf76
MB		 3149 wm8994->jack_mic = true;
3150
3151 wm8958_micd_set_rate(codec);
3152
3153 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3154 SND_JACK_HEADSET);
3155 }
821edd2f 3156
b00adf76 3157
7c08b51f 3158 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3159 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3160 wm8994->mic_detecting = false;
b00adf76
MB		 3161
3162 wm8958_micd_set_rate(codec);
3163
3164 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3165 SND_JACK_HEADSET);
af6b6fe4
MB		 3166
3167 /* If we have jackdet that will detect removal */
3168 if (wm8994->jackdet) {
c986564b
MB		 3169 mutex_lock(&wm8994->accdet_lock);
3170
af6b6fe4
MB		 3171 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3172 WM8958_MICD_ENA, 0);
3173
c986564b
MB		 3174 wm1811_jackdet_set_mode(codec,
3175 WM1811_JACKDET_MODE_JACK);
3176
3177 mutex_unlock(&wm8994->accdet_lock);
3178
07fb9d9e
MB		 3179 if (wm8994->pdata->jd_ext_cap) {
3180 mutex_lock(&codec->mutex);
3181 snd_soc_dapm_disable_pin(&codec->dapm,
3182 "MICBIAS2");
3183 snd_soc_dapm_sync(&codec->dapm);
3184 mutex_unlock(&codec->mutex);
3185 }
af6b6fe4 3186 }
b00adf76
MB		 3187 }
3188
3189 /* Report short circuit as a button */
3190 if (wm8994->jack_mic) {
4585790d 3191 report = 0;
b00adf76 3192 if (status & 0x4)
4585790d
MB		 3193 report |= SND_JACK_BTN_0;
3194
3195 if (status & 0x8)
3196 report |= SND_JACK_BTN_1;
3197
3198 if (status & 0x10)
3199 report |= SND_JACK_BTN_2;
3200
3201 if (status & 0x20)
3202 report |= SND_JACK_BTN_3;
3203
3204 if (status & 0x40)
3205 report |= SND_JACK_BTN_4;
3206
3207 if (status & 0x80)
3208 report |= SND_JACK_BTN_5;
3209
3210 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3211 wm8994->btn_mask);
b00adf76 3212 }
821edd2f
MB		 3213}
3214
af6b6fe4
MB		 3215static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3216{
3217 struct wm8994_priv *wm8994 = data;
3218 struct snd_soc_codec *codec = wm8994->codec;
3219 int reg;
c986564b 3220 bool present;
af6b6fe4
MB		 3221
3222 mutex_lock(&wm8994->accdet_lock);
3223
3224 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3225 if (reg < 0) {
3226 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3227 mutex_unlock(&wm8994->accdet_lock);
3228 return IRQ_NONE;
3229 }
3230
3231 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3232
c986564b 3233 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3234
c986564b
MB		 3235 if (present) {
3236 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3237
55a27786
MB		 3238 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3239 WM8958_MICB2_DISCH, 0);
3240
378ec0ca
MB		 3241 /* Disable debounce while inserted */
3242 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3243 WM1811_JACKDET_DB, 0);
3244
af6b6fe4
MB		 3245 /*
3246 * Start off measument of microphone impedence to find
3247 * out what's actually there.
3248 */
3249 wm8994->mic_detecting = true;
3250 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
b9e67e5e 3251
af6b6fe4
MB		 3252 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3253 WM8958_MICD_ENA, WM8958_MICD_ENA);
3254 } else {
3255 dev_dbg(codec->dev, "Jack not detected\n");
3256
55a27786
MB		 3257 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3258 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3259
378ec0ca
MB		 3260 /* Enable debounce while removed */
3261 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3262 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3263
af6b6fe4
MB		 3264 wm8994->mic_detecting = false;
3265 wm8994->jack_mic = false;
3266 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3267 WM8958_MICD_ENA, 0);
3268 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3269 }
3270
3271 mutex_unlock(&wm8994->accdet_lock);
3272
c986564b
MB		 3273 /* If required for an external cap force MICBIAS on */
3274 if (wm8994->pdata->jd_ext_cap) {
3275 mutex_lock(&codec->mutex);
3276
3277 if (present)
3278 snd_soc_dapm_force_enable_pin(&codec->dapm,
3279 "MICBIAS2");
3280 else
3281 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3282
3283 snd_soc_dapm_sync(&codec->dapm);
3284 mutex_unlock(&codec->mutex);
3285 }
3286
3287 if (present)
3288 snd_soc_jack_report(wm8994->micdet[0].jack,
3289 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3290 else
3291 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3292 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3293 wm8994->btn_mask);
3294
af6b6fe4
MB		 3295 return IRQ_HANDLED;
3296}
3297
821edd2f
MB		 3298/**
3299 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3300 *
3301 * @codec: WM8958 codec
3302 * @jack: jack to report detection events on
3303 *
3304 * Enable microphone detection functionality for the WM8958. By
3305 * default simple detection which supports the detection of up to 6
3306 * buttons plus video and microphone functionality is supported.
3307 *
3308 * The WM8958 has an advanced jack detection facility which is able to
3309 * support complex accessory detection, especially when used in
3310 * conjunction with external circuitry. In order to provide maximum
3311 * flexiblity a callback is provided which allows a completely custom
3312 * detection algorithm.
3313 */
3314int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3315 wm8958_micdet_cb cb, void *cb_data)
3316{
3317 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3318 struct wm8994 *control = wm8994->wm8994;
4585790d 3319 u16 micd_lvl_sel;
821edd2f 3320
81204c84
MB		 3321 switch (control->type) {
3322 case WM1811:
3323 case WM8958:
3324 break;
3325 default:
821edd2f 3326 return -EINVAL;
81204c84 3327 }
821edd2f
MB		 3328
3329 if (jack) {
3330 if (!cb) {
3331 dev_dbg(codec->dev, "Using default micdet callback\n");
3332 cb = wm8958_default_micdet;
3333 cb_data = codec;
3334 }
3335
4cdf5e49 3336 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3337 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3338
821edd2f
MB		 3339 wm8994->micdet[0].jack = jack;
3340 wm8994->jack_cb = cb;
3341 wm8994->jack_cb_data = cb_data;
3342
157a75e6 3343 wm8994->mic_detecting = true;
b00adf76
MB		 3344 wm8994->jack_mic = false;
3345
3346 wm8958_micd_set_rate(codec);
3347
4585790d
MB		 3348 /* Detect microphones and short circuits by default */
3349 if (wm8994->pdata->micd_lvl_sel)
3350 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3351 else
3352 micd_lvl_sel = 0x41;
3353
3354 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3355 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3356 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3357
b00adf76 3358 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3359 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3360
af6b6fe4
MB		 3361 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3362
3363 /*
3364 * If we can use jack detection start off with that,
3365 * otherwise jump straight to microphone detection.
3366 */
3367 if (wm8994->jackdet) {
55a27786
MB		 3368 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3369 WM8958_MICB2_DISCH,
3370 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3371 snd_soc_update_bits(codec, WM8994_LDO_1,
3372 WM8994_LDO1_DISCH, 0);
3373 wm1811_jackdet_set_mode(codec,
3374 WM1811_JACKDET_MODE_JACK);
3375 } else {
3376 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3377 WM8958_MICD_ENA, WM8958_MICD_ENA);
3378 }
3379
821edd2f
MB		 3380 } else {
3381 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3382 WM8958_MICD_ENA, 0);
afaf1591 3383 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3384 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3385 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3386 }
3387
3388 return 0;
3389}
3390EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3391
3392static irqreturn_t wm8958_mic_irq(int irq, void *data)
3393{
3394 struct wm8994_priv *wm8994 = data;
3395 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3396 int reg, count;
821edd2f 3397
af6b6fe4
MB		 3398 /*
3399 * Jack detection may have detected a removal simulataneously
3400 * with an update of the MICDET status; if so it will have
3401 * stopped detection and we can ignore this interrupt.
3402 */
c986564b 3403 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3404 return IRQ_HANDLED;
af6b6fe4 3405
19940b3d
MB		 3406 /* We may occasionally read a detection without an impedence
3407 * range being provided - if that happens loop again.
3408 */
3409 count = 10;
3410 do {
3411 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3412 if (reg < 0) {
3413 dev_err(codec->dev,
3414 "Failed to read mic detect status: %d\n",
3415 reg);
3416 return IRQ_NONE;
3417 }
821edd2f 3418
19940b3d
MB		 3419 if (!(reg & WM8958_MICD_VALID)) {
3420 dev_dbg(codec->dev, "Mic detect data not valid\n");
3421 goto out;
3422 }
3423
3424 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3425 break;
3426
3427 msleep(1);
3428 } while (count--);
3429
3430 if (count == 0)
3431 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3432
7116f452 3433#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3434 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3435#endif
2bbb5d66 3436
821edd2f
MB		 3437 if (wm8994->jack_cb)
3438 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3439 else
3440 dev_warn(codec->dev, "Accessory detection with no callback\n");
3441
3442out:
3443 return IRQ_HANDLED;
3444}
3445
3b1af3f8
MB		 3446static irqreturn_t wm8994_fifo_error(int irq, void *data)
3447{
3448 struct snd_soc_codec *codec = data;
3449
3450 dev_err(codec->dev, "FIFO error\n");
3451
3452 return IRQ_HANDLED;
3453}
3454
f0b182b0
MB		 3455static irqreturn_t wm8994_temp_warn(int irq, void *data)
3456{
3457 struct snd_soc_codec *codec = data;
3458
3459 dev_err(codec->dev, "Thermal warning\n");
3460
3461 return IRQ_HANDLED;
3462}
3463
3464static irqreturn_t wm8994_temp_shut(int irq, void *data)
3465{
3466 struct snd_soc_codec *codec = data;
3467
3468 dev_crit(codec->dev, "Thermal shutdown\n");
3469
3470 return IRQ_HANDLED;
3471}
3472
f0fba2ad 3473static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3474{
d9a7666f 3475 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3476 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3477 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3478 unsigned int reg;
ec62dbd7 3479 int ret, i;
9e6e96a1 3480
2bc16ed8 3481 wm8994->codec = codec;
d9a7666f 3482 codec->control_data = control->regmap;
9e6e96a1 3483
d9a7666f 3484 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3485
f0fba2ad 3486 wm8994->codec = codec;
9e6e96a1 3487
af6b6fe4
MB		 3488 mutex_init(&wm8994->accdet_lock);
3489
c7ebf932
MB		 3490 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3491 init_completion(&wm8994->fll_locked[i]);
3492
9b7c525d
MB		 3493 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3494 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3495 else if (wm8994->pdata && wm8994->pdata->irq_base)
3496 wm8994->micdet_irq = wm8994->pdata->irq_base +
3497 WM8994_IRQ_MIC1_DET;
3498
39fb51a1 3499 pm_runtime_enable(codec->dev);
5fab5174 3500 pm_runtime_idle(codec->dev);
39fb51a1 3501
f959dee9
MB		 3502 /* By default use idle_bias_off, will override for WM8994 */
3503 codec->dapm.idle_bias_off = 1;
3504
9e6e96a1 3505 /* Set revision-specific configuration */
b6b05691 3506 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3507 switch (control->type) {
3508 case WM8994:
f959dee9
MB		 3509 /* Single ended line outputs should have VMID on. */
3510 if (!wm8994->pdata->lineout1_diff ||
3511 !wm8994->pdata->lineout2_diff)
3512 codec->dapm.idle_bias_off = 0;
3513
3a423157
MB		 3514 switch (wm8994->revision) {
3515 case 2:
3516 case 3:
4537c4e7
MB		 3517 wm8994->hubs.dcs_codes_l = -5;
3518 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3519 wm8994->hubs.hp_startup_mode = 1;
3520 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3521 wm8994->hubs.series_startup = 1;
3a423157
MB		 3522 break;
3523 default:
79ef0abc 3524 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3525 break;
3526 }
280ec8b7 3527 break;
3a423157
MB		 3528
3529 case WM8958:
8437f700 3530 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3531 wm8994->hubs.hp_startup_mode = 1;
9e6e96a1 3532 break;
3a423157 3533
81204c84
MB		 3534 case WM1811:
3535 wm8994->hubs.dcs_readback_mode = 2;
3536 wm8994->hubs.no_series_update = 1;
29fdc360 3537 wm8994->hubs.hp_startup_mode = 1;
67109cbe 3538 wm8994->hubs.no_cache_class_w = true;
81204c84
MB		 3539
3540 switch (wm8994->revision) {
3541 case 0:
3542 case 1:
fc8e6e86
MB		 3543 case 2:
3544 case 3:
6473a148
MB		 3545 wm8994->hubs.dcs_codes_l = -9;
3546 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3547 break;
3548 default:
3549 break;
3550 }
3551
3552 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3553 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3554 break;
3555
9e6e96a1
MB		 3556 default:
3557 break;
3558 }
9e6e96a1 3559
2a8a856d 3560 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3561 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3562 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3563 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3564 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3565 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3566
2a8a856d 3567 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3568 wm_hubs_dcs_done, "DC servo done",
3569 &wm8994->hubs);
3570 if (ret == 0)
3571 wm8994->hubs.dcs_done_irq = true;
3572
3a423157
MB		 3573 switch (control->type) {
3574 case WM8994:
9b7c525d
MB		 3575 if (wm8994->micdet_irq) {
3576 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3577 wm8994_mic_irq,
3578 IRQF_TRIGGER_RISING,
3579 "Mic1 detect",
3580 wm8994);
3581 if (ret != 0)
3582 dev_warn(codec->dev,
3583 "Failed to request Mic1 detect IRQ: %d\n",
3584 ret);
3585 }
3a423157 3586
2a8a856d 3587 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3588 WM8994_IRQ_MIC1_SHRT,
3589 wm8994_mic_irq, "Mic 1 short",
3590 wm8994);
3591 if (ret != 0)
3592 dev_warn(codec->dev,
3593 "Failed to request Mic1 short IRQ: %d\n",
3594 ret);
3595
2a8a856d 3596 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3597 WM8994_IRQ_MIC2_DET,
3598 wm8994_mic_irq, "Mic 2 detect",
3599 wm8994);
3600 if (ret != 0)
3601 dev_warn(codec->dev,
3602 "Failed to request Mic2 detect IRQ: %d\n",
3603 ret);
3604
2a8a856d 3605 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3606 WM8994_IRQ_MIC2_SHRT,
3607 wm8994_mic_irq, "Mic 2 short",
3608 wm8994);
3609 if (ret != 0)
3610 dev_warn(codec->dev,
3611 "Failed to request Mic2 short IRQ: %d\n",
3612 ret);
3613 break;
821edd2f
MB		 3614
3615 case WM8958:
81204c84 3616 case WM1811:
9b7c525d
MB		 3617 if (wm8994->micdet_irq) {
3618 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3619 wm8958_mic_irq,
3620 IRQF_TRIGGER_RISING,
3621 "Mic detect",
3622 wm8994);
3623 if (ret != 0)
3624 dev_warn(codec->dev,
3625 "Failed to request Mic detect IRQ: %d\n",
3626 ret);
3627 }
3a423157 3628 }
88766984 3629
af6b6fe4
MB		 3630 switch (control->type) {
3631 case WM1811:
3632 if (wm8994->revision > 1) {
3633 ret = wm8994_request_irq(wm8994->wm8994,
3634 WM8994_IRQ_GPIO(6),
3635 wm1811_jackdet_irq, "JACKDET",
3636 wm8994);
3637 if (ret == 0)
3638 wm8994->jackdet = true;
3639 }
3640 break;
3641 default:
3642 break;
3643 }
3644
c7ebf932
MB		 3645 wm8994->fll_locked_irq = true;
3646 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3647 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3648 WM8994_IRQ_FLL1_LOCK + i,
3649 wm8994_fll_locked_irq, "FLL lock",
3650 &wm8994->fll_locked[i]);
3651 if (ret != 0)
3652 wm8994->fll_locked_irq = false;
3653 }
3654
27060b3c
MB		 3655 /* Make sure we can read from the GPIOs if they're inputs */
3656 pm_runtime_get_sync(codec->dev);
3657
9e6e96a1
MB		 3658 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3659 * configured on init - if a system wants to do this dynamically
3660 * at runtime we can deal with that then.
3661 */
d9a7666f 3662 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3663 if (ret < 0) {
3664 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3665 goto err_irq;
9e6e96a1 3666 }
d9a7666f 3667 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3668 wm8994->lrclk_shared[0] = 1;
3669 wm8994_dai[0].symmetric_rates = 1;
3670 } else {
3671 wm8994->lrclk_shared[0] = 0;
3672 }
3673
d9a7666f 3674 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3675 if (ret < 0) {
3676 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3677 goto err_irq;
9e6e96a1 3678 }
d9a7666f 3679 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3680 wm8994->lrclk_shared[1] = 1;
3681 wm8994_dai[1].symmetric_rates = 1;
3682 } else {
3683 wm8994->lrclk_shared[1] = 0;
3684 }
3685
27060b3c
MB		 3686 pm_runtime_put(codec->dev);
3687
9e6e96a1 3688 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3689 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3690 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3691 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3692 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3693 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3694 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3695 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3696 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3697 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3698 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3699 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3700 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3701 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3702 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3703 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3704 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3705 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3706 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3707 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3708 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3709 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3710 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3711 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3712 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3713 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3714 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3715 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3716 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3717 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3718 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3719 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3720 WM8994_DAC2_VU, WM8994_DAC2_VU);
3721
3722 /* Set the low bit of the 3D stereo depth so TLV matches */
3723 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3724 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3725 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3726 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3727 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3728 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3729 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3730 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3731 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3732
5b739670
MB		 3733 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3734 * use this; it only affects behaviour on idle TDM clock
3735 * cycles. */
3736 switch (control->type) {
3737 case WM8994:
3738 case WM8958:
3739 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3740 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3741 break;
3742 default:
3743 break;
3744 }
d1ce6b20 3745
500fa30e
MB		 3746 /* Put MICBIAS into bypass mode by default on newer devices */
3747 switch (control->type) {
3748 case WM8958:
3749 case WM1811:
3750 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3751 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3752 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3753 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3754 break;
3755 default:
3756 break;
3757 }
3758
9e6e96a1
MB		 3759 wm8994_update_class_w(codec);
3760
f0fba2ad 3761 wm8994_handle_pdata(wm8994);
9e6e96a1 3762
f0fba2ad 3763 wm_hubs_add_analogue_controls(codec);
022658be 3764 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3765 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3766 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3767 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3768
3769 switch (control->type) {
3770 case WM8994:
3771 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3772 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3773 if (wm8994->revision < 4) {
173efa09
DP		 3774 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3775 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3776 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3777 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3778 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3779 ARRAY_SIZE(wm8994_dac_revd_widgets));
3780 } else {
173efa09
DP		 3781 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3782 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3783 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3784 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3785 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3786 ARRAY_SIZE(wm8994_dac_widgets));
3787 }
c4431df0
MB		 3788 break;
3789 case WM8958:
022658be 3790 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3791 ARRAY_SIZE(wm8958_snd_controls));
3792 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3793 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3794 if (wm8994->revision < 1) {
3795 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3796 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3797 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3798 ARRAY_SIZE(wm8994_adc_revd_widgets));
3799 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3800 ARRAY_SIZE(wm8994_dac_revd_widgets));
3801 } else {
3802 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3803 ARRAY_SIZE(wm8994_lateclk_widgets));
3804 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3805 ARRAY_SIZE(wm8994_adc_widgets));
3806 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3807 ARRAY_SIZE(wm8994_dac_widgets));
3808 }
c4431df0 3809 break;
81204c84
MB		 3810
3811 case WM1811:
022658be 3812 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3813 ARRAY_SIZE(wm8958_snd_controls));
3814 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3815 ARRAY_SIZE(wm8958_dapm_widgets));
3816 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3817 ARRAY_SIZE(wm8994_lateclk_widgets));
3818 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3819 ARRAY_SIZE(wm8994_adc_widgets));
3820 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3821 ARRAY_SIZE(wm8994_dac_widgets));
3822 break;
c4431df0
MB		 3823 }
3824
3825
f0fba2ad 3826 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3827 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3828
c4431df0
MB		 3829 switch (control->type) {
3830 case WM8994:
3831 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3832 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3833
173efa09 3834 if (wm8994->revision < 4) {
6ed8f148
MB		 3835 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3836 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3837 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3838 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3839 } else {
3840 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3841 ARRAY_SIZE(wm8994_lateclk_intercon));
3842 }
c4431df0
MB		 3843 break;
3844 case WM8958:
780e2806
MB		 3845 if (wm8994->revision < 1) {
3846 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3847 ARRAY_SIZE(wm8994_revd_intercon));
3848 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3849 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3850 } else {
3851 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3852 ARRAY_SIZE(wm8994_lateclk_intercon));
3853 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3854 ARRAY_SIZE(wm8958_intercon));
3855 }
f701a2e5
MB		 3856
3857 wm8958_dsp2_init(codec);
c4431df0 3858 break;
81204c84
MB		 3859 case WM1811:
3860 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3861 ARRAY_SIZE(wm8994_lateclk_intercon));
3862 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3863 ARRAY_SIZE(wm8958_intercon));
3864 break;
c4431df0
MB		 3865 }
3866
9e6e96a1
MB		 3867 return 0;
3868
88766984 3869err_irq:
af6b6fe4
MB		 3870 if (wm8994->jackdet)
3871 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3872 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3873 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3874 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3875 if (wm8994->micdet_irq)
3876 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3877 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3878 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3879 &wm8994->fll_locked[i]);
2a8a856d 3880 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3881 &wm8994->hubs);
2a8a856d
MB		 3882 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3883 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3884 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3885
9e6e96a1
MB		 3886 return ret;
3887}
3888
f0fba2ad 3889static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3890{
f0fba2ad 3891 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3892 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3893 int i;
9e6e96a1
MB		 3894
3895 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3896
39fb51a1
MB		 3897 pm_runtime_disable(codec->dev);
3898
c7ebf932 3899 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3900 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3901 &wm8994->fll_locked[i]);
3902
2a8a856d 3903 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3904 &wm8994->hubs);
2a8a856d
MB		 3905 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3906 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3907 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3908
af6b6fe4
MB		 3909 if (wm8994->jackdet)
3910 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3911
3a423157
MB		 3912 switch (control->type) {
3913 case WM8994:
9b7c525d
MB		 3914 if (wm8994->micdet_irq)
3915 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3916 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3917 wm8994);
2a8a856d 3918 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3919 wm8994);
2a8a856d 3920 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3921 wm8994);
3922 break;
821edd2f 3923
81204c84 3924 case WM1811:
821edd2f 3925 case WM8958:
9b7c525d
MB		 3926 if (wm8994->micdet_irq)
3927 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3928 break;
3a423157 3929 }
fbbf5920
MB		 3930 if (wm8994->mbc)
3931 release_firmware(wm8994->mbc);
09e10d7f
MB		 3932 if (wm8994->mbc_vss)
3933 release_firmware(wm8994->mbc_vss);
31215871
MB		 3934 if (wm8994->enh_eq)
3935 release_firmware(wm8994->enh_eq);
24fb2b11 3936 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3937
3938 return 0;
3939}
3940
f0fba2ad
LG		 3941static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3942 .probe = wm8994_codec_probe,
3943 .remove = wm8994_codec_remove,
4752a887
MB		 3944 .suspend = wm8994_codec_suspend,
3945 .resume = wm8994_codec_resume,
f0fba2ad
LG		 3946 .set_bias_level = wm8994_set_bias_level,
3947};
3948
3949static int __devinit wm8994_probe(struct platform_device *pdev)
3950{
2bc16ed8
MB		 3951 struct wm8994_priv *wm8994;
3952
3953 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
3954 GFP_KERNEL);
3955 if (wm8994 == NULL)
3956 return -ENOMEM;
3957 platform_set_drvdata(pdev, wm8994);
3958
3959 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
3960 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
3961
f0fba2ad
LG		 3962 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3963 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3964}
3965
3966static int __devexit wm8994_remove(struct platform_device *pdev)
3967{
3968 snd_soc_unregister_codec(&pdev->dev);
3969 return 0;
3970}
3971
4752a887
MB		 3972#ifdef CONFIG_PM_SLEEP
3973static int wm8994_suspend(struct device *dev)
3974{
3975 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
3976
3977 /* Drop down to power saving mode when system is suspended */
3978 if (wm8994->jackdet && !wm8994->active_refcount)
3979 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
3980 WM1811_JACKDET_MODE_MASK,
3981 wm8994->jackdet_mode);
3982
3983 return 0;
3984}
3985
3986static int wm8994_resume(struct device *dev)
3987{
3988 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
3989
3990 if (wm8994->jackdet && wm8994->jack_cb)
3991 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
3992 WM1811_JACKDET_MODE_MASK,
3993 WM1811_JACKDET_MODE_AUDIO);
3994
3995 return 0;
3996}
3997#endif
3998
3999static const struct dev_pm_ops wm8994_pm_ops = {
4000 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4001};
4002
9e6e96a1
MB		 4003static struct platform_driver wm8994_codec_driver = {
4004 .driver = {
4752a887
MB		 4005 .name = "wm8994-codec",
4006 .owner = THIS_MODULE,
4007 .pm = &wm8994_pm_ops,
4008 },
f0fba2ad
LG		 4009 .probe = wm8994_probe,
4010 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 4011};
4012
5bbcc3c0 4013module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4014
4015MODULE_DESCRIPTION("ASoC WM8994 driver");
4016MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4017MODULE_LICENSE("GPL");
4018MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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