projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: wm_hubs: Disable cache of the DC servo calibration for WM1811
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
689 if (wm8994->active_refcount)
690 mode = WM1811_JACKDET_MODE_AUDIO;
691
692 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
693 WM1811_JACKDET_MODE_MASK, mode);
694
695 if (mode == WM1811_JACKDET_MODE_MIC)
696 msleep(2);
697}
698
699static void active_reference(struct snd_soc_codec *codec)
700{
701 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
702
703 mutex_lock(&wm8994->accdet_lock);
704
705 wm8994->active_refcount++;
706
707 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
708 wm8994->active_refcount);
709
710 if (wm8994->active_refcount == 1) {
711 /* If we're using jack detection go into audio mode */
712 if (wm8994->jackdet && wm8994->jack_cb) {
713 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
714 WM1811_JACKDET_MODE_MASK,
715 WM1811_JACKDET_MODE_AUDIO);
716 msleep(2);
717 }
718 }
719
720 mutex_unlock(&wm8994->accdet_lock);
721}
722
723static void active_dereference(struct snd_soc_codec *codec)
724{
725 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
726 u16 mode;
727
728 mutex_lock(&wm8994->accdet_lock);
729
730 wm8994->active_refcount--;
731
732 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
733 wm8994->active_refcount);
734
735 if (wm8994->active_refcount == 0) {
736 /* Go into appropriate detection only mode */
737 if (wm8994->jackdet && wm8994->jack_cb) {
738 if (wm8994->jack_mic || wm8994->mic_detecting)
739 mode = WM1811_JACKDET_MODE_MIC;
740 else
741 mode = WM1811_JACKDET_MODE_JACK;
742
743 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
744 WM1811_JACKDET_MODE_MASK,
745 mode);
746 }
747 }
748
749 mutex_unlock(&wm8994->accdet_lock);
750}
751
9e6e96a1
MB		 752static int clk_sys_event(struct snd_soc_dapm_widget *w,
753 struct snd_kcontrol *kcontrol, int event)
754{
755 struct snd_soc_codec *codec = w->codec;
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
759 return configure_clock(codec);
760
761 case SND_SOC_DAPM_POST_PMD:
762 configure_clock(codec);
763 break;
764 }
765
766 return 0;
767}
768
4b7ed83a
MB		 769static void vmid_reference(struct snd_soc_codec *codec)
770{
771 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
772
db966f8a
MB		 773 pm_runtime_get_sync(codec->dev);
774
4b7ed83a
MB		 775 wm8994->vmid_refcount++;
776
777 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
778 wm8994->vmid_refcount);
779
780 if (wm8994->vmid_refcount == 1) {
cc6d5a8c
MB		 781 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
782 WM8994_LINEOUT_VMID_BUF_ENA |
783 WM8994_LINEOUT1_DISCH |
784 WM8994_LINEOUT2_DISCH,
785 WM8994_LINEOUT_VMID_BUF_ENA);
786
f7085641
MB		 787 wm_hubs_vmid_ena(codec);
788
4b7ed83a
MB		 789 /* Startup bias, VMID ramp & buffer */
790 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
cc6d5a8c
MB		 791 WM8994_BIAS_SRC |
792 WM8994_VMID_DISCH |
4b7ed83a
MB		 793 WM8994_STARTUP_BIAS_ENA |
794 WM8994_VMID_BUF_ENA |
795 WM8994_VMID_RAMP_MASK,
cc6d5a8c 796 WM8994_BIAS_SRC |
4b7ed83a
MB		 797 WM8994_STARTUP_BIAS_ENA |
798 WM8994_VMID_BUF_ENA |
65f01ef0 799 (0x2 << WM8994_VMID_RAMP_SHIFT));
4b7ed83a
MB		 800
801 /* Main bias enable, VMID=2x40k */
802 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803 WM8994_BIAS_ENA |
804 WM8994_VMID_SEL_MASK,
805 WM8994_BIAS_ENA | 0x2);
806
cc6d5a8c
MB		 807 msleep(50);
808
809 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810 WM8994_VMID_RAMP_MASK | WM8994_BIAS_SRC,
811 0);
4b7ed83a
MB		 812 }
813}
814
815static void vmid_dereference(struct snd_soc_codec *codec)
816{
817 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
818
819 wm8994->vmid_refcount--;
820
821 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
822 wm8994->vmid_refcount);
823
824 if (wm8994->vmid_refcount == 0) {
825 /* Switch over to startup biases */
826 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
827 WM8994_BIAS_SRC |
828 WM8994_STARTUP_BIAS_ENA |
829 WM8994_VMID_BUF_ENA |
830 WM8994_VMID_RAMP_MASK,
831 WM8994_BIAS_SRC |
832 WM8994_STARTUP_BIAS_ENA |
833 WM8994_VMID_BUF_ENA |
834 (1 << WM8994_VMID_RAMP_SHIFT));
835
836 /* Disable main biases */
837 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
838 WM8994_BIAS_ENA |
839 WM8994_VMID_SEL_MASK, 0);
840
e85b26ce
MB		 841 /* Discharge VMID */
842 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
843 WM8994_VMID_DISCH, WM8994_VMID_DISCH);
844
4b7ed83a
MB		 845 /* Discharge line */
846 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
847 WM8994_LINEOUT1_DISCH |
848 WM8994_LINEOUT2_DISCH,
849 WM8994_LINEOUT1_DISCH |
850 WM8994_LINEOUT2_DISCH);
851
852 msleep(5);
853
854 /* Switch off startup biases */
855 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
856 WM8994_BIAS_SRC |
857 WM8994_STARTUP_BIAS_ENA |
858 WM8994_VMID_BUF_ENA |
859 WM8994_VMID_RAMP_MASK, 0);
860 }
db966f8a
MB		 861
862 pm_runtime_put(codec->dev);
4b7ed83a
MB		 863}
864
865static int vmid_event(struct snd_soc_dapm_widget *w,
866 struct snd_kcontrol *kcontrol, int event)
867{
868 struct snd_soc_codec *codec = w->codec;
869
870 switch (event) {
871 case SND_SOC_DAPM_PRE_PMU:
872 vmid_reference(codec);
873 break;
874
875 case SND_SOC_DAPM_POST_PMD:
876 vmid_dereference(codec);
877 break;
878 }
879
880 return 0;
881}
882
9e6e96a1
MB		 883static void wm8994_update_class_w(struct snd_soc_codec *codec)
884{
fec6dd83 885 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 886 int enable = 1;
887 int source = 0; /* GCC flow analysis can't track enable */
888 int reg, reg_r;
889
890 /* Only support direct DAC->headphone paths */
891 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
892 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 893 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 894 enable = 0;
895 }
896
897 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
898 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 899 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 900 enable = 0;
901 }
902
903 /* We also need the same setting for L/R and only one path */
904 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
905 switch (reg) {
906 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 907 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 908 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
909 break;
910 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 911 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 912 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
913 break;
914 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 915 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 916 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
917 break;
918 default:
ee839a21 919 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 920 enable = 0;
921 break;
922 }
923
924 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
925 if (reg_r != reg) {
ee839a21 926 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 927 enable = 0;
928 }
929
930 if (enable) {
931 dev_dbg(codec->dev, "Class W enabled\n");
932 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
933 WM8994_CP_DYN_PWR |
934 WM8994_CP_DYN_SRC_SEL_MASK,
935 source | WM8994_CP_DYN_PWR);
fec6dd83 936 wm8994->hubs.class_w = true;
9e6e96a1
MB		 937
938 } else {
939 dev_dbg(codec->dev, "Class W disabled\n");
940 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
941 WM8994_CP_DYN_PWR, 0);
fec6dd83 942 wm8994->hubs.class_w = false;
9e6e96a1
MB		 943 }
944}
945
173efa09
DP		 946static int late_enable_ev(struct snd_soc_dapm_widget *w,
947 struct snd_kcontrol *kcontrol, int event)
948{
949 struct snd_soc_codec *codec = w->codec;
950 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
951
952 switch (event) {
953 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 954 if (wm8994->aif1clk_enable) {
173efa09
DP		 955 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
956 WM8994_AIF1CLK_ENA_MASK,
957 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 958 wm8994->aif1clk_enable = 0;
959 }
960 if (wm8994->aif2clk_enable) {
173efa09
DP		 961 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
962 WM8994_AIF2CLK_ENA_MASK,
963 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 964 wm8994->aif2clk_enable = 0;
965 }
173efa09
DP		 966 break;
967 }
968
c6b7b570
MB		 969 /* We may also have postponed startup of DSP, handle that. */
970 wm8958_aif_ev(w, kcontrol, event);
971
173efa09
DP		 972 return 0;
973}
974
975static int late_disable_ev(struct snd_soc_dapm_widget *w,
976 struct snd_kcontrol *kcontrol, int event)
977{
978 struct snd_soc_codec *codec = w->codec;
979 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
980
981 switch (event) {
982 case SND_SOC_DAPM_POST_PMD:
a3cff81a 983 if (wm8994->aif1clk_disable) {
173efa09
DP		 984 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
985 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 986 wm8994->aif1clk_disable = 0;
173efa09 987 }
a3cff81a 988 if (wm8994->aif2clk_disable) {
173efa09
DP		 989 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
990 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 991 wm8994->aif2clk_disable = 0;
173efa09
DP		 992 }
993 break;
994 }
995
996 return 0;
997}
998
999static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1000 struct snd_kcontrol *kcontrol, int event)
1001{
1002 struct snd_soc_codec *codec = w->codec;
1003 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1004
1005 switch (event) {
1006 case SND_SOC_DAPM_PRE_PMU:
1007 wm8994->aif1clk_enable = 1;
1008 break;
a3cff81a
DP		 1009 case SND_SOC_DAPM_POST_PMD:
1010 wm8994->aif1clk_disable = 1;
1011 break;
173efa09
DP		 1012 }
1013
1014 return 0;
1015}
1016
1017static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1018 struct snd_kcontrol *kcontrol, int event)
1019{
1020 struct snd_soc_codec *codec = w->codec;
1021 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1022
1023 switch (event) {
1024 case SND_SOC_DAPM_PRE_PMU:
1025 wm8994->aif2clk_enable = 1;
1026 break;
a3cff81a
DP		 1027 case SND_SOC_DAPM_POST_PMD:
1028 wm8994->aif2clk_disable = 1;
1029 break;
173efa09
DP		 1030 }
1031
1032 return 0;
1033}
1034
04d28681
DP		 1035static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1036 struct snd_kcontrol *kcontrol, int event)
1037{
1038 late_enable_ev(w, kcontrol, event);
1039 return 0;
1040}
1041
b462c6e6
DP		 1042static int micbias_ev(struct snd_soc_dapm_widget *w,
1043 struct snd_kcontrol *kcontrol, int event)
1044{
1045 late_enable_ev(w, kcontrol, event);
1046 return 0;
1047}
1048
c52fd021
DP		 1049static int dac_ev(struct snd_soc_dapm_widget *w,
1050 struct snd_kcontrol *kcontrol, int event)
1051{
1052 struct snd_soc_codec *codec = w->codec;
1053 unsigned int mask = 1 << w->shift;
1054
1055 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1056 mask, mask);
1057 return 0;
1058}
1059
9e6e96a1
MB		 1060static const char *hp_mux_text[] = {
1061 "Mixer",
1062 "DAC",
1063};
1064
1065#define WM8994_HP_ENUM(xname, xenum) \
1066{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1067 .info = snd_soc_info_enum_double, \
1068 .get = snd_soc_dapm_get_enum_double, \
1069 .put = wm8994_put_hp_enum, \
1070 .private_value = (unsigned long)&xenum }
1071
1072static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1073 struct snd_ctl_elem_value *ucontrol)
1074{
9d03545d
JN		 1075 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1076 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1077 struct snd_soc_codec *codec = w->codec;
1078 int ret;
1079
1080 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1081
1082 wm8994_update_class_w(codec);
1083
1084 return ret;
1085}
1086
1087static const struct soc_enum hpl_enum =
1088 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1089
1090static const struct snd_kcontrol_new hpl_mux =
1091 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1092
1093static const struct soc_enum hpr_enum =
1094 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1095
1096static const struct snd_kcontrol_new hpr_mux =
1097 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1098
1099static const char *adc_mux_text[] = {
1100 "ADC",
1101 "DMIC",
1102};
1103
1104static const struct soc_enum adc_enum =
1105 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1106
1107static const struct snd_kcontrol_new adcl_mux =
1108 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1109
1110static const struct snd_kcontrol_new adcr_mux =
1111 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1112
1113static const struct snd_kcontrol_new left_speaker_mixer[] = {
1114SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1115SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1116SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1117SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1118SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1119};
1120
1121static const struct snd_kcontrol_new right_speaker_mixer[] = {
1122SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1123SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1124SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1125SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1126SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1127};
1128
1129/* Debugging; dump chip status after DAPM transitions */
1130static int post_ev(struct snd_soc_dapm_widget *w,
1131 struct snd_kcontrol *kcontrol, int event)
1132{
1133 struct snd_soc_codec *codec = w->codec;
1134 dev_dbg(codec->dev, "SRC status: %x\n",
1135 snd_soc_read(codec,
1136 WM8994_RATE_STATUS));
1137 return 0;
1138}
1139
1140static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1141SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1142 1, 1, 0),
1143SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1144 0, 1, 0),
1145};
1146
1147static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1148SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1149 1, 1, 0),
1150SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1151 0, 1, 0),
1152};
1153
a3257ba8
MB		 1154static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1155SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1156 1, 1, 0),
1157SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1158 0, 1, 0),
1159};
1160
1161static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1162SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1163 1, 1, 0),
1164SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1165 0, 1, 0),
1166};
1167
9e6e96a1
MB		 1168static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1169SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1170 5, 1, 0),
1171SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1172 4, 1, 0),
1173SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1174 2, 1, 0),
1175SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1176 1, 1, 0),
1177SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1178 0, 1, 0),
1179};
1180
1181static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1182SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1183 5, 1, 0),
1184SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1185 4, 1, 0),
1186SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1187 2, 1, 0),
1188SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1189 1, 1, 0),
1190SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1191 0, 1, 0),
1192};
1193
1194#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1195{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1196 .info = snd_soc_info_volsw, \
1197 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1198 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1199
1200static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1201 struct snd_ctl_elem_value *ucontrol)
1202{
9d03545d
JN		 1203 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1204 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1205 struct snd_soc_codec *codec = w->codec;
1206 int ret;
1207
1208 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1209
1210 wm8994_update_class_w(codec);
1211
1212 return ret;
1213}
1214
1215static const struct snd_kcontrol_new dac1l_mix[] = {
1216WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1217 5, 1, 0),
1218WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1219 4, 1, 0),
1220WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1221 2, 1, 0),
1222WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1223 1, 1, 0),
1224WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1225 0, 1, 0),
1226};
1227
1228static const struct snd_kcontrol_new dac1r_mix[] = {
1229WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1230 5, 1, 0),
1231WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1232 4, 1, 0),
1233WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1234 2, 1, 0),
1235WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1236 1, 1, 0),
1237WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1238 0, 1, 0),
1239};
1240
1241static const char *sidetone_text[] = {
1242 "ADC/DMIC1", "DMIC2",
1243};
1244
1245static const struct soc_enum sidetone1_enum =
1246 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1247
1248static const struct snd_kcontrol_new sidetone1_mux =
1249 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1250
1251static const struct soc_enum sidetone2_enum =
1252 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1253
1254static const struct snd_kcontrol_new sidetone2_mux =
1255 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1256
1257static const char *aif1dac_text[] = {
1258 "AIF1DACDAT", "AIF3DACDAT",
1259};
1260
1261static const struct soc_enum aif1dac_enum =
1262 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1263
1264static const struct snd_kcontrol_new aif1dac_mux =
1265 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1266
1267static const char *aif2dac_text[] = {
1268 "AIF2DACDAT", "AIF3DACDAT",
1269};
1270
1271static const struct soc_enum aif2dac_enum =
1272 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1273
1274static const struct snd_kcontrol_new aif2dac_mux =
1275 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1276
1277static const char *aif2adc_text[] = {
1278 "AIF2ADCDAT", "AIF3DACDAT",
1279};
1280
1281static const struct soc_enum aif2adc_enum =
1282 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1283
1284static const struct snd_kcontrol_new aif2adc_mux =
1285 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1286
1287static const char *aif3adc_text[] = {
c4431df0 1288 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1289};
1290
c4431df0 1291static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1292 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1293
c4431df0
MB		 1294static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1295 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1296
1297static const struct soc_enum wm8958_aif3adc_enum =
1298 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1299
1300static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1301 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1302
1303static const char *mono_pcm_out_text[] = {
1304 "None", "AIF2ADCL", "AIF2ADCR",
1305};
1306
1307static const struct soc_enum mono_pcm_out_enum =
1308 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1309
1310static const struct snd_kcontrol_new mono_pcm_out_mux =
1311 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1312
1313static const char *aif2dac_src_text[] = {
1314 "AIF2", "AIF3",
1315};
1316
1317/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1318static const struct soc_enum aif2dacl_src_enum =
1319 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1320
1321static const struct snd_kcontrol_new aif2dacl_src_mux =
1322 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1323
1324static const struct soc_enum aif2dacr_src_enum =
1325 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1326
1327static const struct snd_kcontrol_new aif2dacr_src_mux =
1328 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1329
173efa09
DP		 1330static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1331SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1332 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1333SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1334 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1335
1336SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1337 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1338SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1339 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1340SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1341 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1342SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1343 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1344SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1345 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1346
1347SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1348 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1349 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1350SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1351 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1352 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1353SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1354 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1355SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1356 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1357
1358SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1359};
1360
1361static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1362SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1363SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1364SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1365SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1366 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1367SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1368 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1369SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1370SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1371};
1372
c52fd021
DP		 1373static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1374SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1375 dac_ev, SND_SOC_DAPM_PRE_PMU),
1376SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1377 dac_ev, SND_SOC_DAPM_PRE_PMU),
1378SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1379 dac_ev, SND_SOC_DAPM_PRE_PMU),
1380SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1381 dac_ev, SND_SOC_DAPM_PRE_PMU),
1382};
1383
1384static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1385SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1386SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1387SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1388SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1389};
1390
04d28681 1391static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1392SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1393 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1394SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1395 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1396};
1397
1398static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1399SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1400SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1401};
1402
9e6e96a1
MB		 1403static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1404SND_SOC_DAPM_INPUT("DMIC1DAT"),
1405SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1406SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1407
b462c6e6
DP		 1408SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1409 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1410SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1411 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1412
9e6e96a1
MB		 1413SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1414 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1415
1416SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1417SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1418SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1419
7f94de48 1420SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1421 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1422SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1423 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1424SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1425 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1426 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1427SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1428 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1429 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1430
7f94de48 1431SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1432 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1433SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1434 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1435SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1436 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1437 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1438SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1439 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1440 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1441
1442SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1443 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1444SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1445 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1446
a3257ba8
MB		 1447SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1448 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1449SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1450 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1451
9e6e96a1
MB		 1452SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1453 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1454SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1455 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1456
1457SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1458SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1459
1460SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1461 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1462SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1463 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1464
1465SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1466 WM8994_POWER_MANAGEMENT_4, 13, 0),
1467SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1468 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1469SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1470 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1471 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1473 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1474 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1475
5567d8c6
MB		 1476SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1477SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1478SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1479SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1480
1481SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1482SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1483SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1484
5567d8c6
MB		 1485SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1486SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1487
1488SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1489
1490SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1491SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1492SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1493SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1494
1495/* Power is done with the muxes since the ADC power also controls the
1496 * downsampling chain, the chip will automatically manage the analogue
1497 * specific portions.
1498 */
1499SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1500SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1501
9e6e96a1
MB		 1502SND_SOC_DAPM_POST("Debug log", post_ev),
1503};
1504
c4431df0
MB		 1505static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1506SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1507};
9e6e96a1 1508
c4431df0
MB		 1509static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1510SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1511SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1512SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1513SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1514};
1515
1516static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1517 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1518 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1519
1520 { "DSP1CLK", NULL, "CLK_SYS" },
1521 { "DSP2CLK", NULL, "CLK_SYS" },
1522 { "DSPINTCLK", NULL, "CLK_SYS" },
1523
1524 { "AIF1ADC1L", NULL, "AIF1CLK" },
1525 { "AIF1ADC1L", NULL, "DSP1CLK" },
1526 { "AIF1ADC1R", NULL, "AIF1CLK" },
1527 { "AIF1ADC1R", NULL, "DSP1CLK" },
1528 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1529
1530 { "AIF1DAC1L", NULL, "AIF1CLK" },
1531 { "AIF1DAC1L", NULL, "DSP1CLK" },
1532 { "AIF1DAC1R", NULL, "AIF1CLK" },
1533 { "AIF1DAC1R", NULL, "DSP1CLK" },
1534 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1535
1536 { "AIF1ADC2L", NULL, "AIF1CLK" },
1537 { "AIF1ADC2L", NULL, "DSP1CLK" },
1538 { "AIF1ADC2R", NULL, "AIF1CLK" },
1539 { "AIF1ADC2R", NULL, "DSP1CLK" },
1540 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1541
1542 { "AIF1DAC2L", NULL, "AIF1CLK" },
1543 { "AIF1DAC2L", NULL, "DSP1CLK" },
1544 { "AIF1DAC2R", NULL, "AIF1CLK" },
1545 { "AIF1DAC2R", NULL, "DSP1CLK" },
1546 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1547
1548 { "AIF2ADCL", NULL, "AIF2CLK" },
1549 { "AIF2ADCL", NULL, "DSP2CLK" },
1550 { "AIF2ADCR", NULL, "AIF2CLK" },
1551 { "AIF2ADCR", NULL, "DSP2CLK" },
1552 { "AIF2ADCR", NULL, "DSPINTCLK" },
1553
1554 { "AIF2DACL", NULL, "AIF2CLK" },
1555 { "AIF2DACL", NULL, "DSP2CLK" },
1556 { "AIF2DACR", NULL, "AIF2CLK" },
1557 { "AIF2DACR", NULL, "DSP2CLK" },
1558 { "AIF2DACR", NULL, "DSPINTCLK" },
1559
1560 { "DMIC1L", NULL, "DMIC1DAT" },
1561 { "DMIC1L", NULL, "CLK_SYS" },
1562 { "DMIC1R", NULL, "DMIC1DAT" },
1563 { "DMIC1R", NULL, "CLK_SYS" },
1564 { "DMIC2L", NULL, "DMIC2DAT" },
1565 { "DMIC2L", NULL, "CLK_SYS" },
1566 { "DMIC2R", NULL, "DMIC2DAT" },
1567 { "DMIC2R", NULL, "CLK_SYS" },
1568
1569 { "ADCL", NULL, "AIF1CLK" },
1570 { "ADCL", NULL, "DSP1CLK" },
1571 { "ADCL", NULL, "DSPINTCLK" },
1572
1573 { "ADCR", NULL, "AIF1CLK" },
1574 { "ADCR", NULL, "DSP1CLK" },
1575 { "ADCR", NULL, "DSPINTCLK" },
1576
1577 { "ADCL Mux", "ADC", "ADCL" },
1578 { "ADCL Mux", "DMIC", "DMIC1L" },
1579 { "ADCR Mux", "ADC", "ADCR" },
1580 { "ADCR Mux", "DMIC", "DMIC1R" },
1581
1582 { "DAC1L", NULL, "AIF1CLK" },
1583 { "DAC1L", NULL, "DSP1CLK" },
1584 { "DAC1L", NULL, "DSPINTCLK" },
1585
1586 { "DAC1R", NULL, "AIF1CLK" },
1587 { "DAC1R", NULL, "DSP1CLK" },
1588 { "DAC1R", NULL, "DSPINTCLK" },
1589
1590 { "DAC2L", NULL, "AIF2CLK" },
1591 { "DAC2L", NULL, "DSP2CLK" },
1592 { "DAC2L", NULL, "DSPINTCLK" },
1593
1594 { "DAC2R", NULL, "AIF2DACR" },
1595 { "DAC2R", NULL, "AIF2CLK" },
1596 { "DAC2R", NULL, "DSP2CLK" },
1597 { "DAC2R", NULL, "DSPINTCLK" },
1598
1599 { "TOCLK", NULL, "CLK_SYS" },
1600
5567d8c6
MB		 1601 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1602 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1603 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1604
1605 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1606 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1607 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1608
9e6e96a1
MB		 1609 /* AIF1 outputs */
1610 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1611 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1612 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1613
1614 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1615 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1616 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1617
a3257ba8
MB		 1618 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1619 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1620 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1621
1622 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1623 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1624 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1625
9e6e96a1
MB		 1626 /* Pin level routing for AIF3 */
1627 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1628 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1629 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1630 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1631
9e6e96a1
MB		 1632 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1633 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1634 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1635 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1636 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1637 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1638 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1639
1640 /* DAC1 inputs */
9e6e96a1
MB		 1641 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1642 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1643 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1644 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1645 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1646
9e6e96a1
MB		 1647 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1648 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1649 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1650 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1651 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1652
1653 /* DAC2/AIF2 outputs */
1654 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1655 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1656 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1657 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1658 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1659 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1660
1661 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1662 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1663 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1664 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1665 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1666 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1667
7f94de48
MB		 1668 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1669 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1670 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1671 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1672
9e6e96a1
MB		 1673 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1674
1675 /* AIF3 output */
1676 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1677 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1678 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1679 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1680 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1681 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1682 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1683 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1684
1685 /* Sidetone */
1686 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1687 { "Left Sidetone", "DMIC2", "DMIC2L" },
1688 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1689 { "Right Sidetone", "DMIC2", "DMIC2R" },
1690
1691 /* Output stages */
1692 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1693 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1694
1695 { "SPKL", "DAC1 Switch", "DAC1L" },
1696 { "SPKL", "DAC2 Switch", "DAC2L" },
1697
1698 { "SPKR", "DAC1 Switch", "DAC1R" },
1699 { "SPKR", "DAC2 Switch", "DAC2R" },
1700
1701 { "Left Headphone Mux", "DAC", "DAC1L" },
1702 { "Right Headphone Mux", "DAC", "DAC1R" },
1703};
1704
173efa09
DP		 1705static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1706 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1707 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1708 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1709 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1710 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1711 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1712 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1713 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1714};
1715
1716static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1717 { "DAC1L", NULL, "DAC1L Mixer" },
1718 { "DAC1R", NULL, "DAC1R Mixer" },
1719 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1720 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1721};
1722
6ed8f148
MB		 1723static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1724 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1725 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1726 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1727 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1728 { "MICBIAS1", NULL, "CLK_SYS" },
1729 { "MICBIAS1", NULL, "MICBIAS Supply" },
1730 { "MICBIAS2", NULL, "CLK_SYS" },
1731 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1732};
1733
c4431df0
MB		 1734static const struct snd_soc_dapm_route wm8994_intercon[] = {
1735 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1736 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1737 { "MICBIAS1", NULL, "VMID" },
1738 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1739};
1740
1741static const struct snd_soc_dapm_route wm8958_intercon[] = {
1742 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1743 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1744
1745 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1746 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1747 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1748 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1749
1750 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1751 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1752
1753 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1754};
1755
9e6e96a1
MB		 1756/* The size in bits of the FLL divide multiplied by 10
1757 * to allow rounding later */
1758#define FIXED_FLL_SIZE ((1 << 16) * 10)
1759
1760struct fll_div {
1761 u16 outdiv;
1762 u16 n;
1763 u16 k;
1764 u16 clk_ref_div;
1765 u16 fll_fratio;
1766};
1767
1768static int wm8994_get_fll_config(struct fll_div *fll,
1769 int freq_in, int freq_out)
1770{
1771 u64 Kpart;
1772 unsigned int K, Ndiv, Nmod;
1773
1774 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1775
1776 /* Scale the input frequency down to <= 13.5MHz */
1777 fll->clk_ref_div = 0;
1778 while (freq_in > 13500000) {
1779 fll->clk_ref_div++;
1780 freq_in /= 2;
1781
1782 if (fll->clk_ref_div > 3)
1783 return -EINVAL;
1784 }
1785 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1786
1787 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1788 fll->outdiv = 3;
1789 while (freq_out * (fll->outdiv + 1) < 90000000) {
1790 fll->outdiv++;
1791 if (fll->outdiv > 63)
1792 return -EINVAL;
1793 }
1794 freq_out *= fll->outdiv + 1;
1795 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1796
1797 if (freq_in > 1000000) {
1798 fll->fll_fratio = 0;
7d48a6ac
MB		 1799 } else if (freq_in > 256000) {
1800 fll->fll_fratio = 1;
1801 freq_in *= 2;
1802 } else if (freq_in > 128000) {
1803 fll->fll_fratio = 2;
1804 freq_in *= 4;
1805 } else if (freq_in > 64000) {
9e6e96a1
MB		 1806 fll->fll_fratio = 3;
1807 freq_in *= 8;
7d48a6ac
MB		 1808 } else {
1809 fll->fll_fratio = 4;
1810 freq_in *= 16;
9e6e96a1
MB		 1811 }
1812 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1813
1814 /* Now, calculate N.K */
1815 Ndiv = freq_out / freq_in;
1816
1817 fll->n = Ndiv;
1818 Nmod = freq_out % freq_in;
1819 pr_debug("Nmod=%d\n", Nmod);
1820
1821 /* Calculate fractional part - scale up so we can round. */
1822 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1823
1824 do_div(Kpart, freq_in);
1825
1826 K = Kpart & 0xFFFFFFFF;
1827
1828 if ((K % 10) >= 5)
1829 K += 5;
1830
1831 /* Move down to proper range now rounding is done */
1832 fll->k = K / 10;
1833
1834 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1835
1836 return 0;
1837}
1838
f0fba2ad 1839static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1840 unsigned int freq_in, unsigned int freq_out)
1841{
b2c812e2 1842 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1843 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1844 int reg_offset, ret;
1845 struct fll_div fll;
1846 u16 reg, aif1, aif2;
c7ebf932 1847 unsigned long timeout;
4b7ed83a 1848 bool was_enabled;
9e6e96a1
MB		 1849
1850 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1851 & WM8994_AIF1CLK_ENA;
1852
1853 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1854 & WM8994_AIF2CLK_ENA;
1855
1856 switch (id) {
1857 case WM8994_FLL1:
1858 reg_offset = 0;
1859 id = 0;
1860 break;
1861 case WM8994_FLL2:
1862 reg_offset = 0x20;
1863 id = 1;
1864 break;
1865 default:
1866 return -EINVAL;
1867 }
1868
4b7ed83a
MB		 1869 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1870 was_enabled = reg & WM8994_FLL1_ENA;
1871
136ff2a2 1872 switch (src) {
7add84aa
MB		 1873 case 0:
1874 /* Allow no source specification when stopping */
1875 if (freq_out)
1876 return -EINVAL;
4514e899 1877 src = wm8994->fll[id].src;
7add84aa 1878 break;
136ff2a2
MB		 1879 case WM8994_FLL_SRC_MCLK1:
1880 case WM8994_FLL_SRC_MCLK2:
1881 case WM8994_FLL_SRC_LRCLK:
1882 case WM8994_FLL_SRC_BCLK:
1883 break;
1884 default:
1885 return -EINVAL;
1886 }
1887
9e6e96a1
MB		 1888 /* Are we changing anything? */
1889 if (wm8994->fll[id].src == src &&
1890 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1891 return 0;
1892
1893 /* If we're stopping the FLL redo the old config - no
1894 * registers will actually be written but we avoid GCC flow
1895 * analysis bugs spewing warnings.
1896 */
1897 if (freq_out)
1898 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1899 else
1900 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1901 wm8994->fll[id].out);
1902 if (ret < 0)
1903 return ret;
1904
1905 /* Gate the AIF clocks while we reclock */
1906 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1907 WM8994_AIF1CLK_ENA, 0);
1908 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1909 WM8994_AIF2CLK_ENA, 0);
1910
1911 /* We always need to disable the FLL while reconfiguring */
1912 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1913 WM8994_FLL1_ENA, 0);
1914
1915 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1916 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1917 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1918 WM8994_FLL1_OUTDIV_MASK |
1919 WM8994_FLL1_FRATIO_MASK, reg);
1920
b16db745
MB		 1921 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1922 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 1923
1924 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1925 WM8994_FLL1_N_MASK,
1926 fll.n << WM8994_FLL1_N_SHIFT);
1927
1928 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1929 WM8994_FLL1_REFCLK_DIV_MASK |
1930 WM8994_FLL1_REFCLK_SRC_MASK,
1931 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1932 (src - 1));
9e6e96a1 1933
f0f5039c
MB		 1934 /* Clear any pending completion from a previous failure */
1935 try_wait_for_completion(&wm8994->fll_locked[id]);
1936
9e6e96a1
MB		 1937 /* Enable (with fractional mode if required) */
1938 if (freq_out) {
4b7ed83a
MB		 1939 /* Enable VMID if we need it */
1940 if (!was_enabled) {
af6b6fe4
MB		 1941 active_reference(codec);
1942
4b7ed83a
MB		 1943 switch (control->type) {
1944 case WM8994:
1945 vmid_reference(codec);
1946 break;
1947 case WM8958:
1948 if (wm8994->revision < 1)
1949 vmid_reference(codec);
1950 break;
1951 default:
1952 break;
1953 }
1954 }
1955
9e6e96a1
MB		 1956 if (fll.k)
1957 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1958 else
1959 reg = WM8994_FLL1_ENA;
1960 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1961 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1962 reg);
8e9ddf81 1963
c7ebf932
MB		 1964 if (wm8994->fll_locked_irq) {
1965 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1966 msecs_to_jiffies(10));
1967 if (timeout == 0)
1968 dev_warn(codec->dev,
1969 "Timed out waiting for FLL lock\n");
1970 } else {
1971 msleep(5);
1972 }
4b7ed83a
MB		 1973 } else {
1974 if (was_enabled) {
1975 switch (control->type) {
1976 case WM8994:
1977 vmid_dereference(codec);
1978 break;
1979 case WM8958:
1980 if (wm8994->revision < 1)
1981 vmid_dereference(codec);
1982 break;
1983 default:
1984 break;
1985 }
af6b6fe4
MB		 1986
1987 active_dereference(codec);
4b7ed83a 1988 }
9e6e96a1
MB		 1989 }
1990
1991 wm8994->fll[id].in = freq_in;
1992 wm8994->fll[id].out = freq_out;
136ff2a2 1993 wm8994->fll[id].src = src;
9e6e96a1
MB		 1994
1995 /* Enable any gated AIF clocks */
1996 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1997 WM8994_AIF1CLK_ENA, aif1);
1998 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1999 WM8994_AIF2CLK_ENA, aif2);
2000
2001 configure_clock(codec);
2002
2003 return 0;
2004}
2005
c7ebf932
MB		 2006static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2007{
2008 struct completion *completion = data;
2009
2010 complete(completion);
2011
2012 return IRQ_HANDLED;
2013}
f0fba2ad 2014
66b47fdb
MB		 2015static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2016
f0fba2ad
LG		 2017static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2018 unsigned int freq_in, unsigned int freq_out)
2019{
2020 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2021}
2022
9e6e96a1
MB		 2023static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2024 int clk_id, unsigned int freq, int dir)
2025{
2026 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2027 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2028 int i;
9e6e96a1
MB		 2029
2030 switch (dai->id) {
2031 case 1:
2032 case 2:
2033 break;
2034
2035 default:
2036 /* AIF3 shares clocking with AIF1/2 */
2037 return -EINVAL;
2038 }
2039
2040 switch (clk_id) {
2041 case WM8994_SYSCLK_MCLK1:
2042 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2043 wm8994->mclk[0] = freq;
2044 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2045 dai->id, freq);
2046 break;
2047
2048 case WM8994_SYSCLK_MCLK2:
2049 /* TODO: Set GPIO AF */
2050 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2051 wm8994->mclk[1] = freq;
2052 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2053 dai->id, freq);
2054 break;
2055
2056 case WM8994_SYSCLK_FLL1:
2057 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2058 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2059 break;
2060
2061 case WM8994_SYSCLK_FLL2:
2062 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2063 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2064 break;
2065
66b47fdb
MB		 2066 case WM8994_SYSCLK_OPCLK:
2067 /* Special case - a division (times 10) is given and
2068 * no effect on main clocking.
2069 */
2070 if (freq) {
2071 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2072 if (opclk_divs[i] == freq)
2073 break;
2074 if (i == ARRAY_SIZE(opclk_divs))
2075 return -EINVAL;
2076 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2077 WM8994_OPCLK_DIV_MASK, i);
2078 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2079 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2080 } else {
2081 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2082 WM8994_OPCLK_ENA, 0);
2083 }
2084
9e6e96a1
MB		 2085 default:
2086 return -EINVAL;
2087 }
2088
2089 configure_clock(codec);
2090
2091 return 0;
2092}
2093
2094static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2095 enum snd_soc_bias_level level)
2096{
b6b05691 2097 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2098 struct wm8994 *control = wm8994->wm8994;
b6b05691 2099
5f2f3890
MB		 2100 wm_hubs_set_bias_level(codec, level);
2101
9e6e96a1
MB		 2102 switch (level) {
2103 case SND_SOC_BIAS_ON:
2104 break;
2105
2106 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2107 /* MICBIAS into regulating mode */
2108 switch (control->type) {
2109 case WM8958:
2110 case WM1811:
2111 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2112 WM8958_MICB1_MODE, 0);
2113 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2114 WM8958_MICB2_MODE, 0);
2115 break;
2116 default:
2117 break;
2118 }
af6b6fe4
MB		 2119
2120 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2121 active_reference(codec);
9e6e96a1
MB		 2122 break;
2123
2124 case SND_SOC_BIAS_STANDBY:
ce6120cc 2125 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2
MB		 2126 switch (control->type) {
2127 case WM8994:
2128 if (wm8994->revision < 4) {
2129 /* Tweak DC servo and DSP
2130 * configuration for improved
2131 * performance. */
2132 snd_soc_write(codec, 0x102, 0x3);
2133 snd_soc_write(codec, 0x56, 0x3);
2134 snd_soc_write(codec, 0x817, 0);
2135 snd_soc_write(codec, 0x102, 0);
2136 }
2137 break;
2138
2139 case WM8958:
2140 if (wm8994->revision == 0) {
2141 /* Optimise performance for rev A */
2142 snd_soc_write(codec, 0x102, 0x3);
2143 snd_soc_write(codec, 0xcb, 0x81);
2144 snd_soc_write(codec, 0x817, 0);
2145 snd_soc_write(codec, 0x102, 0);
2146
2147 snd_soc_update_bits(codec,
2148 WM8958_CHARGE_PUMP_2,
2149 WM8958_CP_DISCH,
2150 WM8958_CP_DISCH);
2151 }
2152 break;
81204c84
MB		 2153
2154 case WM1811:
2155 if (wm8994->revision < 2) {
2156 snd_soc_write(codec, 0x102, 0x3);
2157 snd_soc_write(codec, 0x5d, 0x7e);
2158 snd_soc_write(codec, 0x5e, 0x0);
2159 snd_soc_write(codec, 0x102, 0x0);
2160 }
2161 break;
b6b05691 2162 }
9e6e96a1
MB		 2163
2164 /* Discharge LINEOUT1 & 2 */
2165 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2166 WM8994_LINEOUT1_DISCH |
2167 WM8994_LINEOUT2_DISCH,
2168 WM8994_LINEOUT1_DISCH |
2169 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2170 }
2171
af6b6fe4
MB		 2172 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2173 active_dereference(codec);
2174
500fa30e
MB		 2175 /* MICBIAS into bypass mode on newer devices */
2176 switch (control->type) {
2177 case WM8958:
2178 case WM1811:
2179 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2180 WM8958_MICB1_MODE,
2181 WM8958_MICB1_MODE);
2182 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2183 WM8958_MICB2_MODE,
2184 WM8958_MICB2_MODE);
2185 break;
2186 default:
2187 break;
2188 }
9e6e96a1
MB		 2189 break;
2190
2191 case SND_SOC_BIAS_OFF:
4105ab84 2192 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2193 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2194 break;
2195 }
5f2f3890 2196
ce6120cc 2197 codec->dapm.bias_level = level;
af6b6fe4 2198
9e6e96a1
MB		 2199 return 0;
2200}
2201
2202static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2203{
2204 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2205 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2206 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2207 int ms_reg;
2208 int aif1_reg;
2209 int ms = 0;
2210 int aif1 = 0;
2211
2212 switch (dai->id) {
2213 case 1:
2214 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2215 aif1_reg = WM8994_AIF1_CONTROL_1;
2216 break;
2217 case 2:
2218 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2219 aif1_reg = WM8994_AIF2_CONTROL_1;
2220 break;
2221 default:
2222 return -EINVAL;
2223 }
2224
2225 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2226 case SND_SOC_DAIFMT_CBS_CFS:
2227 break;
2228 case SND_SOC_DAIFMT_CBM_CFM:
2229 ms = WM8994_AIF1_MSTR;
2230 break;
2231 default:
2232 return -EINVAL;
2233 }
2234
2235 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2236 case SND_SOC_DAIFMT_DSP_B:
2237 aif1 |= WM8994_AIF1_LRCLK_INV;
2238 case SND_SOC_DAIFMT_DSP_A:
2239 aif1 |= 0x18;
2240 break;
2241 case SND_SOC_DAIFMT_I2S:
2242 aif1 |= 0x10;
2243 break;
2244 case SND_SOC_DAIFMT_RIGHT_J:
2245 break;
2246 case SND_SOC_DAIFMT_LEFT_J:
2247 aif1 |= 0x8;
2248 break;
2249 default:
2250 return -EINVAL;
2251 }
2252
2253 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2254 case SND_SOC_DAIFMT_DSP_A:
2255 case SND_SOC_DAIFMT_DSP_B:
2256 /* frame inversion not valid for DSP modes */
2257 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2258 case SND_SOC_DAIFMT_NB_NF:
2259 break;
2260 case SND_SOC_DAIFMT_IB_NF:
2261 aif1 |= WM8994_AIF1_BCLK_INV;
2262 break;
2263 default:
2264 return -EINVAL;
2265 }
2266 break;
2267
2268 case SND_SOC_DAIFMT_I2S:
2269 case SND_SOC_DAIFMT_RIGHT_J:
2270 case SND_SOC_DAIFMT_LEFT_J:
2271 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2272 case SND_SOC_DAIFMT_NB_NF:
2273 break;
2274 case SND_SOC_DAIFMT_IB_IF:
2275 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2276 break;
2277 case SND_SOC_DAIFMT_IB_NF:
2278 aif1 |= WM8994_AIF1_BCLK_INV;
2279 break;
2280 case SND_SOC_DAIFMT_NB_IF:
2281 aif1 |= WM8994_AIF1_LRCLK_INV;
2282 break;
2283 default:
2284 return -EINVAL;
2285 }
2286 break;
2287 default:
2288 return -EINVAL;
2289 }
2290
c4431df0
MB		 2291 /* The AIF2 format configuration needs to be mirrored to AIF3
2292 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2293 switch (control->type) {
2294 case WM1811:
2295 case WM8958:
2296 if (dai->id == 2)
2297 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2298 WM8994_AIF1_LRCLK_INV |
2299 WM8958_AIF3_FMT_MASK, aif1);
2300 break;
2301
2302 default:
2303 break;
2304 }
c4431df0 2305
9e6e96a1
MB		 2306 snd_soc_update_bits(codec, aif1_reg,
2307 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2308 WM8994_AIF1_FMT_MASK,
2309 aif1);
2310 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2311 ms);
2312
2313 return 0;
2314}
2315
2316static struct {
2317 int val, rate;
2318} srs[] = {
2319 { 0, 8000 },
2320 { 1, 11025 },
2321 { 2, 12000 },
2322 { 3, 16000 },
2323 { 4, 22050 },
2324 { 5, 24000 },
2325 { 6, 32000 },
2326 { 7, 44100 },
2327 { 8, 48000 },
2328 { 9, 88200 },
2329 { 10, 96000 },
2330};
2331
2332static int fs_ratios[] = {
2333 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2334};
2335
2336static int bclk_divs[] = {
2337 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2338 640, 880, 960, 1280, 1760, 1920
2339};
2340
2341static int wm8994_hw_params(struct snd_pcm_substream *substream,
2342 struct snd_pcm_hw_params *params,
2343 struct snd_soc_dai *dai)
2344{
2345 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2346 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2347 int aif1_reg;
b1e43d93 2348 int aif2_reg;
9e6e96a1
MB		 2349 int bclk_reg;
2350 int lrclk_reg;
2351 int rate_reg;
2352 int aif1 = 0;
b1e43d93 2353 int aif2 = 0;
9e6e96a1
MB		 2354 int bclk = 0;
2355 int lrclk = 0;
2356 int rate_val = 0;
2357 int id = dai->id - 1;
2358
2359 int i, cur_val, best_val, bclk_rate, best;
2360
2361 switch (dai->id) {
2362 case 1:
2363 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2364 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2365 bclk_reg = WM8994_AIF1_BCLK;
2366 rate_reg = WM8994_AIF1_RATE;
2367 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2368 wm8994->lrclk_shared[0]) {
9e6e96a1 2369 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2370 } else {
9e6e96a1 2371 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2372 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2373 }
9e6e96a1
MB		 2374 break;
2375 case 2:
2376 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2377 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2378 bclk_reg = WM8994_AIF2_BCLK;
2379 rate_reg = WM8994_AIF2_RATE;
2380 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2381 wm8994->lrclk_shared[1]) {
9e6e96a1 2382 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2383 } else {
9e6e96a1 2384 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2385 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2386 }
9e6e96a1
MB		 2387 break;
2388 default:
2389 return -EINVAL;
2390 }
2391
2392 bclk_rate = params_rate(params) * 2;
2393 switch (params_format(params)) {
2394 case SNDRV_PCM_FORMAT_S16_LE:
2395 bclk_rate *= 16;
2396 break;
2397 case SNDRV_PCM_FORMAT_S20_3LE:
2398 bclk_rate *= 20;
2399 aif1 |= 0x20;
2400 break;
2401 case SNDRV_PCM_FORMAT_S24_LE:
2402 bclk_rate *= 24;
2403 aif1 |= 0x40;
2404 break;
2405 case SNDRV_PCM_FORMAT_S32_LE:
2406 bclk_rate *= 32;
2407 aif1 |= 0x60;
2408 break;
2409 default:
2410 return -EINVAL;
2411 }
2412
2413 /* Try to find an appropriate sample rate; look for an exact match. */
2414 for (i = 0; i < ARRAY_SIZE(srs); i++)
2415 if (srs[i].rate == params_rate(params))
2416 break;
2417 if (i == ARRAY_SIZE(srs))
2418 return -EINVAL;
2419 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2420
2421 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2422 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2423 dai->id, wm8994->aifclk[id], bclk_rate);
2424
b1e43d93
MB		 2425 if (params_channels(params) == 1 &&
2426 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2427 aif2 |= WM8994_AIF1_MONO;
2428
9e6e96a1
MB		 2429 if (wm8994->aifclk[id] == 0) {
2430 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2431 return -EINVAL;
2432 }
2433
2434 /* AIFCLK/fs ratio; look for a close match in either direction */
2435 best = 0;
2436 best_val = abs((fs_ratios[0] * params_rate(params))
2437 - wm8994->aifclk[id]);
2438 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2439 cur_val = abs((fs_ratios[i] * params_rate(params))
2440 - wm8994->aifclk[id]);
2441 if (cur_val >= best_val)
2442 continue;
2443 best = i;
2444 best_val = cur_val;
2445 }
2446 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2447 dai->id, fs_ratios[best]);
2448 rate_val |= best;
2449
2450 /* We may not get quite the right frequency if using
2451 * approximate clocks so look for the closest match that is
2452 * higher than the target (we need to ensure that there enough
2453 * BCLKs to clock out the samples).
2454 */
2455 best = 0;
2456 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2457 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2458 if (cur_val < 0) /* BCLK table is sorted */
2459 break;
2460 best = i;
2461 }
07cd8ada 2462 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2463 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2464 bclk_divs[best], bclk_rate);
2465 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2466
2467 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2468 if (!lrclk) {
2469 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2470 bclk_rate);
2471 return -EINVAL;
2472 }
9e6e96a1
MB		 2473 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2474 lrclk, bclk_rate / lrclk);
2475
2476 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2477 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2478 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2479 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2480 lrclk);
2481 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2482 WM8994_AIF1CLK_RATE_MASK, rate_val);
2483
2484 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2485 switch (dai->id) {
2486 case 1:
2487 wm8994->dac_rates[0] = params_rate(params);
2488 wm8994_set_retune_mobile(codec, 0);
2489 wm8994_set_retune_mobile(codec, 1);
2490 break;
2491 case 2:
2492 wm8994->dac_rates[1] = params_rate(params);
2493 wm8994_set_retune_mobile(codec, 2);
2494 break;
2495 }
2496 }
2497
2498 return 0;
2499}
2500
c4431df0
MB		 2501static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2502 struct snd_pcm_hw_params *params,
2503 struct snd_soc_dai *dai)
2504{
2505 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2506 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2507 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2508 int aif1_reg;
2509 int aif1 = 0;
2510
2511 switch (dai->id) {
2512 case 3:
2513 switch (control->type) {
81204c84 2514 case WM1811:
c4431df0
MB		 2515 case WM8958:
2516 aif1_reg = WM8958_AIF3_CONTROL_1;
2517 break;
2518 default:
2519 return 0;
2520 }
2521 default:
2522 return 0;
2523 }
2524
2525 switch (params_format(params)) {
2526 case SNDRV_PCM_FORMAT_S16_LE:
2527 break;
2528 case SNDRV_PCM_FORMAT_S20_3LE:
2529 aif1 |= 0x20;
2530 break;
2531 case SNDRV_PCM_FORMAT_S24_LE:
2532 aif1 |= 0x40;
2533 break;
2534 case SNDRV_PCM_FORMAT_S32_LE:
2535 aif1 |= 0x60;
2536 break;
2537 default:
2538 return -EINVAL;
2539 }
2540
2541 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2542}
2543
7d02173c
MB		 2544static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2545 struct snd_soc_dai *dai)
2546{
2547 struct snd_soc_codec *codec = dai->codec;
2548 int rate_reg = 0;
2549
2550 switch (dai->id) {
2551 case 1:
2552 rate_reg = WM8994_AIF1_RATE;
2553 break;
2554 case 2:
c527e6aa 2555 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2556 break;
2557 default:
2558 break;
2559 }
2560
2561 /* If the DAI is idle then configure the divider tree for the
2562 * lowest output rate to save a little power if the clock is
2563 * still active (eg, because it is system clock).
2564 */
2565 if (rate_reg && !dai->playback_active && !dai->capture_active)
2566 snd_soc_update_bits(codec, rate_reg,
2567 WM8994_AIF1_SR_MASK |
2568 WM8994_AIF1CLK_RATE_MASK, 0x9);
2569}
2570
9e6e96a1
MB		 2571static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2572{
2573 struct snd_soc_codec *codec = codec_dai->codec;
2574 int mute_reg;
2575 int reg;
2576
2577 switch (codec_dai->id) {
2578 case 1:
2579 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2580 break;
2581 case 2:
2582 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2583 break;
2584 default:
2585 return -EINVAL;
2586 }
2587
2588 if (mute)
2589 reg = WM8994_AIF1DAC1_MUTE;
2590 else
2591 reg = 0;
2592
2593 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2594
2595 return 0;
2596}
2597
778a76e2
MB		 2598static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2599{
2600 struct snd_soc_codec *codec = codec_dai->codec;
2601 int reg, val, mask;
2602
2603 switch (codec_dai->id) {
2604 case 1:
2605 reg = WM8994_AIF1_MASTER_SLAVE;
2606 mask = WM8994_AIF1_TRI;
2607 break;
2608 case 2:
2609 reg = WM8994_AIF2_MASTER_SLAVE;
2610 mask = WM8994_AIF2_TRI;
2611 break;
2612 case 3:
2613 reg = WM8994_POWER_MANAGEMENT_6;
2614 mask = WM8994_AIF3_TRI;
2615 break;
2616 default:
2617 return -EINVAL;
2618 }
2619
2620 if (tristate)
2621 val = mask;
2622 else
2623 val = 0;
2624
78b3fb46 2625 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2626}
2627
d09f3ecf
MB		 2628static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2629{
2630 struct snd_soc_codec *codec = dai->codec;
2631
2632 /* Disable the pulls on the AIF if we're using it to save power. */
2633 snd_soc_update_bits(codec, WM8994_GPIO_3,
2634 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2635 snd_soc_update_bits(codec, WM8994_GPIO_4,
2636 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2637 snd_soc_update_bits(codec, WM8994_GPIO_5,
2638 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2639
2640 return 0;
2641}
2642
9e6e96a1
MB		 2643#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2644
2645#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2646 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2647
85e7652d 2648static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2649 .set_sysclk = wm8994_set_dai_sysclk,
2650 .set_fmt = wm8994_set_dai_fmt,
2651 .hw_params = wm8994_hw_params,
7d02173c 2652 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2653 .digital_mute = wm8994_aif_mute,
2654 .set_pll = wm8994_set_fll,
778a76e2 2655 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2656};
2657
85e7652d 2658static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2659 .set_sysclk = wm8994_set_dai_sysclk,
2660 .set_fmt = wm8994_set_dai_fmt,
2661 .hw_params = wm8994_hw_params,
7d02173c 2662 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2663 .digital_mute = wm8994_aif_mute,
2664 .set_pll = wm8994_set_fll,
778a76e2
MB		 2665 .set_tristate = wm8994_set_tristate,
2666};
2667
85e7652d 2668static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2669 .hw_params = wm8994_aif3_hw_params,
778a76e2 2670 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2671};
2672
f0fba2ad 2673static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2674 {
f0fba2ad 2675 .name = "wm8994-aif1",
8c7f78b3 2676 .id = 1,
9e6e96a1
MB		 2677 .playback = {
2678 .stream_name = "AIF1 Playback",
b1e43d93 2679 .channels_min = 1,
9e6e96a1
MB		 2680 .channels_max = 2,
2681 .rates = WM8994_RATES,
2682 .formats = WM8994_FORMATS,
99b0292d 2683 .sig_bits = 24,
9e6e96a1
MB		 2684 },
2685 .capture = {
2686 .stream_name = "AIF1 Capture",
b1e43d93 2687 .channels_min = 1,
9e6e96a1
MB		 2688 .channels_max = 2,
2689 .rates = WM8994_RATES,
2690 .formats = WM8994_FORMATS,
99b0292d 2691 .sig_bits = 24,
9e6e96a1
MB		 2692 },
2693 .ops = &wm8994_aif1_dai_ops,
2694 },
2695 {
f0fba2ad 2696 .name = "wm8994-aif2",
8c7f78b3 2697 .id = 2,
9e6e96a1
MB		 2698 .playback = {
2699 .stream_name = "AIF2 Playback",
b1e43d93 2700 .channels_min = 1,
9e6e96a1
MB		 2701 .channels_max = 2,
2702 .rates = WM8994_RATES,
2703 .formats = WM8994_FORMATS,
99b0292d 2704 .sig_bits = 24,
9e6e96a1
MB		 2705 },
2706 .capture = {
2707 .stream_name = "AIF2 Capture",
b1e43d93 2708 .channels_min = 1,
9e6e96a1
MB		 2709 .channels_max = 2,
2710 .rates = WM8994_RATES,
2711 .formats = WM8994_FORMATS,
99b0292d 2712 .sig_bits = 24,
9e6e96a1 2713 },
d09f3ecf 2714 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2715 .ops = &wm8994_aif2_dai_ops,
2716 },
2717 {
f0fba2ad 2718 .name = "wm8994-aif3",
8c7f78b3 2719 .id = 3,
9e6e96a1
MB		 2720 .playback = {
2721 .stream_name = "AIF3 Playback",
b1e43d93 2722 .channels_min = 1,
9e6e96a1
MB		 2723 .channels_max = 2,
2724 .rates = WM8994_RATES,
2725 .formats = WM8994_FORMATS,
99b0292d 2726 .sig_bits = 24,
9e6e96a1 2727 },
a8462bde 2728 .capture = {
9e6e96a1 2729 .stream_name = "AIF3 Capture",
b1e43d93 2730 .channels_min = 1,
9e6e96a1
MB		 2731 .channels_max = 2,
2732 .rates = WM8994_RATES,
2733 .formats = WM8994_FORMATS,
99b0292d
MB		 2734 .sig_bits = 24,
2735 },
778a76e2 2736 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2737 }
2738};
9e6e96a1
MB		 2739
2740#ifdef CONFIG_PM
84b315ee 2741static int wm8994_suspend(struct snd_soc_codec *codec)
9e6e96a1 2742{
b2c812e2 2743 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2744 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2745 int i, ret;
2746
ca629928
MB		 2747 switch (control->type) {
2748 case WM8994:
2749 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2750 break;
81204c84 2751 case WM1811:
af6b6fe4
MB		 2752 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2753 WM1811_JACKDET_MODE_MASK, 0);
2754 /* Fall through */
ca629928
MB		 2755 case WM8958:
2756 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2757 WM8958_MICD_ENA, 0);
2758 break;
2759 }
2760
9e6e96a1
MB		 2761 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2762 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2763 sizeof(struct wm8994_fll_config));
f0fba2ad 2764 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2765 if (ret < 0)
2766 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2767 i + 1, ret);
2768 }
2769
2770 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2771
2772 return 0;
2773}
2774
f0fba2ad 2775static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2776{
b2c812e2 2777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2778 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2779 int i, ret;
c52fd021
DP		 2780 unsigned int val, mask;
2781
2782 if (wm8994->revision < 4) {
2783 /* force a HW read */
d9a7666f
MB		 2784 ret = regmap_read(control->regmap,
2785 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2786
2787 /* modify the cache only */
2788 codec->cache_only = 1;
2789 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2790 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2791 val &= mask;
2792 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2793 mask, val);
2794 codec->cache_only = 0;
2795 }
9e6e96a1 2796
9e6e96a1 2797 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2798 if (!wm8994->fll_suspend[i].out)
2799 continue;
2800
f0fba2ad 2801 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2802 wm8994->fll_suspend[i].src,
2803 wm8994->fll_suspend[i].in,
2804 wm8994->fll_suspend[i].out);
2805 if (ret < 0)
2806 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2807 i + 1, ret);
2808 }
2809
ca629928
MB		 2810 switch (control->type) {
2811 case WM8994:
2812 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2813 snd_soc_update_bits(codec, WM8994_MICBIAS,
2814 WM8994_MICD_ENA, WM8994_MICD_ENA);
2815 break;
81204c84 2816 case WM1811:
af6b6fe4
MB		 2817 if (wm8994->jackdet && wm8994->jack_cb) {
2818 /* Restart from idle */
2819 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2820 WM1811_JACKDET_MODE_MASK,
2821 WM1811_JACKDET_MODE_JACK);
2822 break;
2823 }
ca629928
MB		 2824 case WM8958:
2825 if (wm8994->jack_cb)
2826 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2827 WM8958_MICD_ENA, WM8958_MICD_ENA);
2828 break;
2829 }
2830
9e6e96a1
MB		 2831 return 0;
2832}
2833#else
2834#define wm8994_suspend NULL
2835#define wm8994_resume NULL
2836#endif
2837
2838static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2839{
f0fba2ad 2840 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2841 struct wm8994_pdata *pdata = wm8994->pdata;
2842 struct snd_kcontrol_new controls[] = {
2843 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2844 wm8994->retune_mobile_enum,
2845 wm8994_get_retune_mobile_enum,
2846 wm8994_put_retune_mobile_enum),
2847 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2848 wm8994->retune_mobile_enum,
2849 wm8994_get_retune_mobile_enum,
2850 wm8994_put_retune_mobile_enum),
2851 SOC_ENUM_EXT("AIF2 EQ Mode",
2852 wm8994->retune_mobile_enum,
2853 wm8994_get_retune_mobile_enum,
2854 wm8994_put_retune_mobile_enum),
2855 };
2856 int ret, i, j;
2857 const char **t;
2858
2859 /* We need an array of texts for the enum API but the number
2860 * of texts is likely to be less than the number of
2861 * configurations due to the sample rate dependency of the
2862 * configurations. */
2863 wm8994->num_retune_mobile_texts = 0;
2864 wm8994->retune_mobile_texts = NULL;
2865 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2866 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2867 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2868 wm8994->retune_mobile_texts[j]) == 0)
2869 break;
2870 }
2871
2872 if (j != wm8994->num_retune_mobile_texts)
2873 continue;
2874
2875 /* Expand the array... */
2876 t = krealloc(wm8994->retune_mobile_texts,
2877 sizeof(char *) *
2878 (wm8994->num_retune_mobile_texts + 1),
2879 GFP_KERNEL);
2880 if (t == NULL)
2881 continue;
2882
2883 /* ...store the new entry... */
2884 t[wm8994->num_retune_mobile_texts] =
2885 pdata->retune_mobile_cfgs[i].name;
2886
2887 /* ...and remember the new version. */
2888 wm8994->num_retune_mobile_texts++;
2889 wm8994->retune_mobile_texts = t;
2890 }
2891
2892 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2893 wm8994->num_retune_mobile_texts);
2894
2895 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2896 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2897
022658be 2898 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2899 ARRAY_SIZE(controls));
2900 if (ret != 0)
f0fba2ad 2901 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2902 "Failed to add ReTune Mobile controls: %d\n", ret);
2903}
2904
2905static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2906{
f0fba2ad 2907 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2908 struct wm8994_pdata *pdata = wm8994->pdata;
2909 int ret, i;
2910
2911 if (!pdata)
2912 return;
2913
2914 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2915 pdata->lineout2_diff,
2916 pdata->lineout1fb,
2917 pdata->lineout2fb,
2918 pdata->jd_scthr,
2919 pdata->jd_thr,
2920 pdata->micbias1_lvl,
2921 pdata->micbias2_lvl);
2922
2923 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2924
2925 if (pdata->num_drc_cfgs) {
2926 struct snd_kcontrol_new controls[] = {
2927 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2928 wm8994_get_drc_enum, wm8994_put_drc_enum),
2929 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2930 wm8994_get_drc_enum, wm8994_put_drc_enum),
2931 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2932 wm8994_get_drc_enum, wm8994_put_drc_enum),
2933 };
2934
2935 /* We need an array of texts for the enum API */
7270cebe
MB		 2936 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
2937 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 2938 if (!wm8994->drc_texts) {
f0fba2ad 2939 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2940 "Failed to allocate %d DRC config texts\n",
2941 pdata->num_drc_cfgs);
2942 return;
2943 }
2944
2945 for (i = 0; i < pdata->num_drc_cfgs; i++)
2946 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2947
2948 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2949 wm8994->drc_enum.texts = wm8994->drc_texts;
2950
022658be 2951 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2952 ARRAY_SIZE(controls));
2953 if (ret != 0)
f0fba2ad 2954 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2955 "Failed to add DRC mode controls: %d\n", ret);
2956
2957 for (i = 0; i < WM8994_NUM_DRC; i++)
2958 wm8994_set_drc(codec, i);
2959 }
2960
2961 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2962 pdata->num_retune_mobile_cfgs);
2963
2964 if (pdata->num_retune_mobile_cfgs)
2965 wm8994_handle_retune_mobile_pdata(wm8994);
2966 else
022658be 2967 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2968 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2969
2970 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2971 if (pdata->micbias[i]) {
2972 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2973 pdata->micbias[i] & 0xffff);
2974 }
2975 }
9e6e96a1
MB		 2976}
2977
88766984
MB		 2978/**
2979 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2980 *
2981 * @codec: WM8994 codec
2982 * @jack: jack to report detection events on
2983 * @micbias: microphone bias to detect on
88766984
MB		 2984 *
2985 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2986 * being used to bring out signals to the processor then only platform
5ab230a7 2987 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2988 * be configured using snd_soc_jack_add_gpios() instead.
2989 *
2990 * Configuration of detection levels is available via the micbias1_lvl
2991 * and micbias2_lvl platform data members.
2992 */
2993int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 2994 int micbias)
88766984 2995{
b2c812e2 2996 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2997 struct wm8994_micdet *micdet;
2a8a856d 2998 struct wm8994 *control = wm8994->wm8994;
87092e3c 2999 int reg, ret;
88766984 3000
87092e3c
MB		 3001 if (control->type != WM8994) {
3002 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3003 return -EINVAL;
87092e3c 3004 }
3a423157 3005
88766984
MB		 3006 switch (micbias) {
3007 case 1:
3008 micdet = &wm8994->micdet[0];
87092e3c
MB		 3009 if (jack)
3010 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3011 "MICBIAS1");
3012 else
3013 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3014 "MICBIAS1");
88766984
MB		 3015 break;
3016 case 2:
3017 micdet = &wm8994->micdet[1];
87092e3c
MB		 3018 if (jack)
3019 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3020 "MICBIAS1");
3021 else
3022 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3023 "MICBIAS1");
88766984
MB		 3024 break;
3025 default:
87092e3c 3026 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3027 return -EINVAL;
87092e3c 3028 }
88766984 3029
87092e3c
MB		 3030 if (ret != 0)
3031 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3032 micbias, ret);
3033
3034 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3035 micbias, jack);
88766984
MB		 3036
3037 /* Store the configuration */
3038 micdet->jack = jack;
87092e3c 3039 micdet->detecting = true;
88766984
MB		 3040
3041 /* If either of the jacks is set up then enable detection */
3042 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3043 reg = WM8994_MICD_ENA;
87092e3c 3044 else
88766984
MB		 3045 reg = 0;
3046
3047 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3048
87092e3c
MB		 3049 snd_soc_dapm_sync(&codec->dapm);
3050
88766984
MB		 3051 return 0;
3052}
3053EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3054
3055static irqreturn_t wm8994_mic_irq(int irq, void *data)
3056{
3057 struct wm8994_priv *priv = data;
f0fba2ad 3058 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3059 int reg;
3060 int report;
3061
7116f452 3062#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3063 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3064#endif
2bbb5d66 3065
88766984
MB		 3066 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3067 if (reg < 0) {
3068 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3069 reg);
3070 return IRQ_HANDLED;
3071 }
3072
3073 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3074
3075 report = 0;
87092e3c
MB		 3076 if (reg & WM8994_MIC1_DET_STS) {
3077 if (priv->micdet[0].detecting)
3078 report = SND_JACK_HEADSET;
3079 }
3080 if (reg & WM8994_MIC1_SHRT_STS) {
3081 if (priv->micdet[0].detecting)
3082 report = SND_JACK_HEADPHONE;
3083 else
3084 report |= SND_JACK_BTN_0;
3085 }
3086 if (report)
3087 priv->micdet[0].detecting = false;
3088 else
3089 priv->micdet[0].detecting = true;
3090
88766984 3091 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3092 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3093
3094 report = 0;
87092e3c
MB		 3095 if (reg & WM8994_MIC2_DET_STS) {
3096 if (priv->micdet[1].detecting)
3097 report = SND_JACK_HEADSET;
3098 }
3099 if (reg & WM8994_MIC2_SHRT_STS) {
3100 if (priv->micdet[1].detecting)
3101 report = SND_JACK_HEADPHONE;
3102 else
3103 report |= SND_JACK_BTN_0;
3104 }
3105 if (report)
3106 priv->micdet[1].detecting = false;
3107 else
3108 priv->micdet[1].detecting = true;
3109
88766984 3110 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3111 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3112
3113 return IRQ_HANDLED;
3114}
3115
821edd2f
MB		 3116/* Default microphone detection handler for WM8958 - the user can
3117 * override this if they wish.
3118 */
3119static void wm8958_default_micdet(u16 status, void *data)
3120{
3121 struct snd_soc_codec *codec = data;
3122 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3123 int report;
821edd2f 3124
a1691343
MB		 3125 dev_dbg(codec->dev, "MICDET %x\n", status);
3126
af6b6fe4 3127 /* Either nothing present or just starting detection */
b00adf76 3128 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3129 if (!wm8994->jackdet) {
3130 /* If nothing present then clear our statuses */
3131 dev_dbg(codec->dev, "Detected open circuit\n");
3132 wm8994->jack_mic = false;
3133 wm8994->mic_detecting = true;
b00adf76 3134
af6b6fe4 3135 wm8958_micd_set_rate(codec);
b00adf76 3136
af6b6fe4
MB		 3137 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3138 wm8994->btn_mask |
3139 SND_JACK_HEADSET);
3140 }
b00adf76
MB		 3141 return;
3142 }
821edd2f 3143
b00adf76
MB		 3144 /* If the measurement is showing a high impedence we've got a
3145 * microphone.
3146 */
157a75e6 3147 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3148 dev_dbg(codec->dev, "Detected microphone\n");
3149
157a75e6 3150 wm8994->mic_detecting = false;
b00adf76
MB		 3151 wm8994->jack_mic = true;
3152
3153 wm8958_micd_set_rate(codec);
3154
3155 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3156 SND_JACK_HEADSET);
3157 }
821edd2f 3158
b00adf76 3159
7c08b51f 3160 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3161 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3162 wm8994->mic_detecting = false;
b00adf76
MB		 3163
3164 wm8958_micd_set_rate(codec);
3165
3166 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3167 SND_JACK_HEADSET);
af6b6fe4
MB		 3168
3169 /* If we have jackdet that will detect removal */
3170 if (wm8994->jackdet) {
3171 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3172 WM8958_MICD_ENA, 0);
3173
07fb9d9e
MB		 3174 if (wm8994->pdata->jd_ext_cap) {
3175 mutex_lock(&codec->mutex);
3176 snd_soc_dapm_disable_pin(&codec->dapm,
3177 "MICBIAS2");
3178 snd_soc_dapm_sync(&codec->dapm);
3179 mutex_unlock(&codec->mutex);
3180 }
b9e67e5e
MB		 3181
3182 wm1811_jackdet_set_mode(codec,
3183 WM1811_JACKDET_MODE_JACK);
af6b6fe4 3184 }
b00adf76
MB		 3185 }
3186
3187 /* Report short circuit as a button */
3188 if (wm8994->jack_mic) {
4585790d 3189 report = 0;
b00adf76 3190 if (status & 0x4)
4585790d
MB		 3191 report |= SND_JACK_BTN_0;
3192
3193 if (status & 0x8)
3194 report |= SND_JACK_BTN_1;
3195
3196 if (status & 0x10)
3197 report |= SND_JACK_BTN_2;
3198
3199 if (status & 0x20)
3200 report |= SND_JACK_BTN_3;
3201
3202 if (status & 0x40)
3203 report |= SND_JACK_BTN_4;
3204
3205 if (status & 0x80)
3206 report |= SND_JACK_BTN_5;
3207
3208 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3209 wm8994->btn_mask);
b00adf76 3210 }
821edd2f
MB		 3211}
3212
af6b6fe4
MB		 3213static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3214{
3215 struct wm8994_priv *wm8994 = data;
3216 struct snd_soc_codec *codec = wm8994->codec;
3217 int reg;
3218
3219 mutex_lock(&wm8994->accdet_lock);
3220
3221 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3222 if (reg < 0) {
3223 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3224 mutex_unlock(&wm8994->accdet_lock);
3225 return IRQ_NONE;
3226 }
3227
3228 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3229
3230 if (reg & WM1811_JACKDET_LVL) {
3231 dev_dbg(codec->dev, "Jack detected\n");
3232
3233 snd_soc_jack_report(wm8994->micdet[0].jack,
3234 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3235
55a27786
MB		 3236 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3237 WM8958_MICB2_DISCH, 0);
3238
378ec0ca
MB		 3239 /* Disable debounce while inserted */
3240 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3241 WM1811_JACKDET_DB, 0);
3242
af6b6fe4
MB		 3243 /*
3244 * Start off measument of microphone impedence to find
3245 * out what's actually there.
3246 */
3247 wm8994->mic_detecting = true;
3248 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
b9e67e5e 3249
af6b6fe4
MB		 3250 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3251 WM8958_MICD_ENA, WM8958_MICD_ENA);
b9e67e5e
MB		 3252
3253 /* If required for an external cap force MICBIAS on */
3254 if (wm8994->pdata->jd_ext_cap) {
3255 mutex_lock(&codec->mutex);
3256 snd_soc_dapm_force_enable_pin(&codec->dapm,
3257 "MICBIAS2");
3258 snd_soc_dapm_sync(&codec->dapm);
3259 mutex_unlock(&codec->mutex);
3260 }
af6b6fe4
MB		 3261 } else {
3262 dev_dbg(codec->dev, "Jack not detected\n");
3263
55a27786
MB		 3264 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3265 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3266
07fb9d9e
MB		 3267 if (wm8994->pdata->jd_ext_cap) {
3268 mutex_lock(&codec->mutex);
3269 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3270 snd_soc_dapm_sync(&codec->dapm);
3271 mutex_unlock(&codec->mutex);
3272 }
3273
af6b6fe4
MB		 3274 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3275 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3276 wm8994->btn_mask);
3277
378ec0ca
MB		 3278 /* Enable debounce while removed */
3279 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3280 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3281
af6b6fe4
MB		 3282 wm8994->mic_detecting = false;
3283 wm8994->jack_mic = false;
3284 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3285 WM8958_MICD_ENA, 0);
3286 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3287 }
3288
3289 mutex_unlock(&wm8994->accdet_lock);
3290
3291 return IRQ_HANDLED;
3292}
3293
821edd2f
MB		 3294/**
3295 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3296 *
3297 * @codec: WM8958 codec
3298 * @jack: jack to report detection events on
3299 *
3300 * Enable microphone detection functionality for the WM8958. By
3301 * default simple detection which supports the detection of up to 6
3302 * buttons plus video and microphone functionality is supported.
3303 *
3304 * The WM8958 has an advanced jack detection facility which is able to
3305 * support complex accessory detection, especially when used in
3306 * conjunction with external circuitry. In order to provide maximum
3307 * flexiblity a callback is provided which allows a completely custom
3308 * detection algorithm.
3309 */
3310int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3311 wm8958_micdet_cb cb, void *cb_data)
3312{
3313 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3314 struct wm8994 *control = wm8994->wm8994;
4585790d 3315 u16 micd_lvl_sel;
821edd2f 3316
81204c84
MB		 3317 switch (control->type) {
3318 case WM1811:
3319 case WM8958:
3320 break;
3321 default:
821edd2f 3322 return -EINVAL;
81204c84 3323 }
821edd2f
MB		 3324
3325 if (jack) {
3326 if (!cb) {
3327 dev_dbg(codec->dev, "Using default micdet callback\n");
3328 cb = wm8958_default_micdet;
3329 cb_data = codec;
3330 }
3331
4cdf5e49
MB		 3332 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3333
821edd2f
MB		 3334 wm8994->micdet[0].jack = jack;
3335 wm8994->jack_cb = cb;
3336 wm8994->jack_cb_data = cb_data;
3337
157a75e6 3338 wm8994->mic_detecting = true;
b00adf76
MB		 3339 wm8994->jack_mic = false;
3340
3341 wm8958_micd_set_rate(codec);
3342
4585790d
MB		 3343 /* Detect microphones and short circuits by default */
3344 if (wm8994->pdata->micd_lvl_sel)
3345 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3346 else
3347 micd_lvl_sel = 0x41;
3348
3349 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3350 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3351 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3352
b00adf76 3353 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3354 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3355
af6b6fe4
MB		 3356 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3357
3358 /*
3359 * If we can use jack detection start off with that,
3360 * otherwise jump straight to microphone detection.
3361 */
3362 if (wm8994->jackdet) {
55a27786
MB		 3363 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3364 WM8958_MICB2_DISCH,
3365 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3366 snd_soc_update_bits(codec, WM8994_LDO_1,
3367 WM8994_LDO1_DISCH, 0);
3368 wm1811_jackdet_set_mode(codec,
3369 WM1811_JACKDET_MODE_JACK);
3370 } else {
3371 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3372 WM8958_MICD_ENA, WM8958_MICD_ENA);
3373 }
3374
821edd2f
MB		 3375 } else {
3376 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3377 WM8958_MICD_ENA, 0);
4cdf5e49 3378 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
821edd2f
MB		 3379 }
3380
3381 return 0;
3382}
3383EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3384
3385static irqreturn_t wm8958_mic_irq(int irq, void *data)
3386{
3387 struct wm8994_priv *wm8994 = data;
3388 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3389 int reg, count;
821edd2f 3390
af6b6fe4
MB		 3391 mutex_lock(&wm8994->accdet_lock);
3392
3393 /*
3394 * Jack detection may have detected a removal simulataneously
3395 * with an update of the MICDET status; if so it will have
3396 * stopped detection and we can ignore this interrupt.
3397 */
3398 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) {
3399 mutex_unlock(&wm8994->accdet_lock);
3400 return IRQ_HANDLED;
3401 }
3402
19940b3d
MB		 3403 /* We may occasionally read a detection without an impedence
3404 * range being provided - if that happens loop again.
3405 */
3406 count = 10;
3407 do {
3408 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3409 if (reg < 0) {
af6b6fe4 3410 mutex_unlock(&wm8994->accdet_lock);
19940b3d
MB		 3411 dev_err(codec->dev,
3412 "Failed to read mic detect status: %d\n",
3413 reg);
3414 return IRQ_NONE;
3415 }
821edd2f 3416
19940b3d
MB		 3417 if (!(reg & WM8958_MICD_VALID)) {
3418 dev_dbg(codec->dev, "Mic detect data not valid\n");
3419 goto out;
3420 }
3421
3422 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3423 break;
3424
3425 msleep(1);
3426 } while (count--);
3427
3428 if (count == 0)
3429 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3430
7116f452 3431#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3432 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3433#endif
2bbb5d66 3434
821edd2f
MB		 3435 if (wm8994->jack_cb)
3436 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3437 else
3438 dev_warn(codec->dev, "Accessory detection with no callback\n");
3439
3440out:
af6b6fe4
MB		 3441 mutex_unlock(&wm8994->accdet_lock);
3442
821edd2f
MB		 3443 return IRQ_HANDLED;
3444}
3445
3b1af3f8
MB		 3446static irqreturn_t wm8994_fifo_error(int irq, void *data)
3447{
3448 struct snd_soc_codec *codec = data;
3449
3450 dev_err(codec->dev, "FIFO error\n");
3451
3452 return IRQ_HANDLED;
3453}
3454
f0b182b0
MB		 3455static irqreturn_t wm8994_temp_warn(int irq, void *data)
3456{
3457 struct snd_soc_codec *codec = data;
3458
3459 dev_err(codec->dev, "Thermal warning\n");
3460
3461 return IRQ_HANDLED;
3462}
3463
3464static irqreturn_t wm8994_temp_shut(int irq, void *data)
3465{
3466 struct snd_soc_codec *codec = data;
3467
3468 dev_crit(codec->dev, "Thermal shutdown\n");
3469
3470 return IRQ_HANDLED;
3471}
3472
f0fba2ad 3473static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3474{
d9a7666f 3475 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3476 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3477 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3478 unsigned int reg;
ec62dbd7 3479 int ret, i;
9e6e96a1 3480
2bc16ed8 3481 wm8994->codec = codec;
d9a7666f 3482 codec->control_data = control->regmap;
9e6e96a1 3483
d9a7666f 3484 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3485
f0fba2ad 3486 wm8994->codec = codec;
9e6e96a1 3487
af6b6fe4
MB		 3488 mutex_init(&wm8994->accdet_lock);
3489
c7ebf932
MB		 3490 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3491 init_completion(&wm8994->fll_locked[i]);
3492
9b7c525d
MB		 3493 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3494 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3495 else if (wm8994->pdata && wm8994->pdata->irq_base)
3496 wm8994->micdet_irq = wm8994->pdata->irq_base +
3497 WM8994_IRQ_MIC1_DET;
3498
39fb51a1 3499 pm_runtime_enable(codec->dev);
5fab5174 3500 pm_runtime_idle(codec->dev);
39fb51a1 3501
f959dee9
MB		 3502 /* By default use idle_bias_off, will override for WM8994 */
3503 codec->dapm.idle_bias_off = 1;
3504
9e6e96a1 3505 /* Set revision-specific configuration */
b6b05691 3506 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3507 switch (control->type) {
3508 case WM8994:
f959dee9
MB		 3509 /* Single ended line outputs should have VMID on. */
3510 if (!wm8994->pdata->lineout1_diff ||
3511 !wm8994->pdata->lineout2_diff)
3512 codec->dapm.idle_bias_off = 0;
3513
3a423157
MB		 3514 switch (wm8994->revision) {
3515 case 2:
3516 case 3:
4537c4e7
MB		 3517 wm8994->hubs.dcs_codes_l = -5;
3518 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3519 wm8994->hubs.hp_startup_mode = 1;
3520 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3521 wm8994->hubs.series_startup = 1;
3a423157
MB		 3522 break;
3523 default:
79ef0abc 3524 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3525 break;
3526 }
280ec8b7 3527 break;
3a423157
MB		 3528
3529 case WM8958:
8437f700 3530 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3531 wm8994->hubs.hp_startup_mode = 1;
9e6e96a1 3532 break;
3a423157 3533
81204c84
MB		 3534 case WM1811:
3535 wm8994->hubs.dcs_readback_mode = 2;
3536 wm8994->hubs.no_series_update = 1;
29fdc360 3537 wm8994->hubs.hp_startup_mode = 1;
67109cbe 3538 wm8994->hubs.no_cache_class_w = true;
81204c84
MB		 3539
3540 switch (wm8994->revision) {
3541 case 0:
3542 case 1:
fc8e6e86
MB		 3543 case 2:
3544 case 3:
6473a148
MB		 3545 wm8994->hubs.dcs_codes_l = -9;
3546 wm8994->hubs.dcs_codes_r = -5;
81204c84
MB		 3547 break;
3548 default:
3549 break;
3550 }
3551
3552 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3553 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3554 break;
3555
9e6e96a1
MB		 3556 default:
3557 break;
3558 }
9e6e96a1 3559
2a8a856d 3560 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3561 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3562 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3563 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3564 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3565 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3566
2a8a856d 3567 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3568 wm_hubs_dcs_done, "DC servo done",
3569 &wm8994->hubs);
3570 if (ret == 0)
3571 wm8994->hubs.dcs_done_irq = true;
3572
3a423157
MB		 3573 switch (control->type) {
3574 case WM8994:
9b7c525d
MB		 3575 if (wm8994->micdet_irq) {
3576 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3577 wm8994_mic_irq,
3578 IRQF_TRIGGER_RISING,
3579 "Mic1 detect",
3580 wm8994);
3581 if (ret != 0)
3582 dev_warn(codec->dev,
3583 "Failed to request Mic1 detect IRQ: %d\n",
3584 ret);
3585 }
3a423157 3586
2a8a856d 3587 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3588 WM8994_IRQ_MIC1_SHRT,
3589 wm8994_mic_irq, "Mic 1 short",
3590 wm8994);
3591 if (ret != 0)
3592 dev_warn(codec->dev,
3593 "Failed to request Mic1 short IRQ: %d\n",
3594 ret);
3595
2a8a856d 3596 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3597 WM8994_IRQ_MIC2_DET,
3598 wm8994_mic_irq, "Mic 2 detect",
3599 wm8994);
3600 if (ret != 0)
3601 dev_warn(codec->dev,
3602 "Failed to request Mic2 detect IRQ: %d\n",
3603 ret);
3604
2a8a856d 3605 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3606 WM8994_IRQ_MIC2_SHRT,
3607 wm8994_mic_irq, "Mic 2 short",
3608 wm8994);
3609 if (ret != 0)
3610 dev_warn(codec->dev,
3611 "Failed to request Mic2 short IRQ: %d\n",
3612 ret);
3613 break;
821edd2f
MB		 3614
3615 case WM8958:
81204c84 3616 case WM1811:
9b7c525d
MB		 3617 if (wm8994->micdet_irq) {
3618 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3619 wm8958_mic_irq,
3620 IRQF_TRIGGER_RISING,
3621 "Mic detect",
3622 wm8994);
3623 if (ret != 0)
3624 dev_warn(codec->dev,
3625 "Failed to request Mic detect IRQ: %d\n",
3626 ret);
3627 }
3a423157 3628 }
88766984 3629
af6b6fe4
MB		 3630 switch (control->type) {
3631 case WM1811:
3632 if (wm8994->revision > 1) {
3633 ret = wm8994_request_irq(wm8994->wm8994,
3634 WM8994_IRQ_GPIO(6),
3635 wm1811_jackdet_irq, "JACKDET",
3636 wm8994);
3637 if (ret == 0)
3638 wm8994->jackdet = true;
3639 }
3640 break;
3641 default:
3642 break;
3643 }
3644
c7ebf932
MB		 3645 wm8994->fll_locked_irq = true;
3646 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3647 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3648 WM8994_IRQ_FLL1_LOCK + i,
3649 wm8994_fll_locked_irq, "FLL lock",
3650 &wm8994->fll_locked[i]);
3651 if (ret != 0)
3652 wm8994->fll_locked_irq = false;
3653 }
3654
27060b3c
MB		 3655 /* Make sure we can read from the GPIOs if they're inputs */
3656 pm_runtime_get_sync(codec->dev);
3657
9e6e96a1
MB		 3658 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3659 * configured on init - if a system wants to do this dynamically
3660 * at runtime we can deal with that then.
3661 */
d9a7666f 3662 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3663 if (ret < 0) {
3664 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3665 goto err_irq;
9e6e96a1 3666 }
d9a7666f 3667 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3668 wm8994->lrclk_shared[0] = 1;
3669 wm8994_dai[0].symmetric_rates = 1;
3670 } else {
3671 wm8994->lrclk_shared[0] = 0;
3672 }
3673
d9a7666f 3674 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3675 if (ret < 0) {
3676 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3677 goto err_irq;
9e6e96a1 3678 }
d9a7666f 3679 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3680 wm8994->lrclk_shared[1] = 1;
3681 wm8994_dai[1].symmetric_rates = 1;
3682 } else {
3683 wm8994->lrclk_shared[1] = 0;
3684 }
3685
27060b3c
MB		 3686 pm_runtime_put(codec->dev);
3687
9e6e96a1 3688 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3689 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3690 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3691 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3692 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3693 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3694 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3695 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3696 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3697 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3698 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3699 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3700 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3701 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3702 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3703 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3704 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3705 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3706 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3707 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3708 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3709 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3710 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3711 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3712 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3713 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3714 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3715 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3716 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3717 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3718 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3719 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3720 WM8994_DAC2_VU, WM8994_DAC2_VU);
3721
3722 /* Set the low bit of the 3D stereo depth so TLV matches */
3723 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3724 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3725 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3726 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3727 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3728 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3729 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3730 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3731 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3732
5b739670
MB		 3733 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3734 * use this; it only affects behaviour on idle TDM clock
3735 * cycles. */
3736 switch (control->type) {
3737 case WM8994:
3738 case WM8958:
3739 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3740 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3741 break;
3742 default:
3743 break;
3744 }
d1ce6b20 3745
500fa30e
MB		 3746 /* Put MICBIAS into bypass mode by default on newer devices */
3747 switch (control->type) {
3748 case WM8958:
3749 case WM1811:
3750 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3751 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3752 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3753 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3754 break;
3755 default:
3756 break;
3757 }
3758
9e6e96a1
MB		 3759 wm8994_update_class_w(codec);
3760
f0fba2ad 3761 wm8994_handle_pdata(wm8994);
9e6e96a1 3762
f0fba2ad 3763 wm_hubs_add_analogue_controls(codec);
022658be 3764 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3765 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3766 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3767 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3768
3769 switch (control->type) {
3770 case WM8994:
3771 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3772 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3773 if (wm8994->revision < 4) {
173efa09
DP		 3774 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3775 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3776 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3777 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3778 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3779 ARRAY_SIZE(wm8994_dac_revd_widgets));
3780 } else {
173efa09
DP		 3781 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3782 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3783 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3784 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3785 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3786 ARRAY_SIZE(wm8994_dac_widgets));
3787 }
c4431df0
MB		 3788 break;
3789 case WM8958:
022658be 3790 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3791 ARRAY_SIZE(wm8958_snd_controls));
3792 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3793 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3794 if (wm8994->revision < 1) {
3795 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3796 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3797 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3798 ARRAY_SIZE(wm8994_adc_revd_widgets));
3799 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3800 ARRAY_SIZE(wm8994_dac_revd_widgets));
3801 } else {
3802 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3803 ARRAY_SIZE(wm8994_lateclk_widgets));
3804 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3805 ARRAY_SIZE(wm8994_adc_widgets));
3806 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3807 ARRAY_SIZE(wm8994_dac_widgets));
3808 }
c4431df0 3809 break;
81204c84
MB		 3810
3811 case WM1811:
022658be 3812 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3813 ARRAY_SIZE(wm8958_snd_controls));
3814 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3815 ARRAY_SIZE(wm8958_dapm_widgets));
3816 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3817 ARRAY_SIZE(wm8994_lateclk_widgets));
3818 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3819 ARRAY_SIZE(wm8994_adc_widgets));
3820 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3821 ARRAY_SIZE(wm8994_dac_widgets));
3822 break;
c4431df0
MB		 3823 }
3824
3825
f0fba2ad 3826 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3827 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3828
c4431df0
MB		 3829 switch (control->type) {
3830 case WM8994:
3831 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3832 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3833
173efa09 3834 if (wm8994->revision < 4) {
6ed8f148
MB		 3835 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3836 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3837 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3838 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3839 } else {
3840 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3841 ARRAY_SIZE(wm8994_lateclk_intercon));
3842 }
c4431df0
MB		 3843 break;
3844 case WM8958:
780e2806
MB		 3845 if (wm8994->revision < 1) {
3846 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3847 ARRAY_SIZE(wm8994_revd_intercon));
3848 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3849 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3850 } else {
3851 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3852 ARRAY_SIZE(wm8994_lateclk_intercon));
3853 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3854 ARRAY_SIZE(wm8958_intercon));
3855 }
f701a2e5
MB		 3856
3857 wm8958_dsp2_init(codec);
c4431df0 3858 break;
81204c84
MB		 3859 case WM1811:
3860 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3861 ARRAY_SIZE(wm8994_lateclk_intercon));
3862 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3863 ARRAY_SIZE(wm8958_intercon));
3864 break;
c4431df0
MB		 3865 }
3866
9e6e96a1
MB		 3867 return 0;
3868
88766984 3869err_irq:
af6b6fe4
MB		 3870 if (wm8994->jackdet)
3871 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3872 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3873 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3874 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3875 if (wm8994->micdet_irq)
3876 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3877 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3878 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3879 &wm8994->fll_locked[i]);
2a8a856d 3880 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3881 &wm8994->hubs);
2a8a856d
MB		 3882 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3883 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3884 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3885
9e6e96a1
MB		 3886 return ret;
3887}
3888
f0fba2ad 3889static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3890{
f0fba2ad 3891 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3892 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3893 int i;
9e6e96a1
MB		 3894
3895 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3896
39fb51a1
MB		 3897 pm_runtime_disable(codec->dev);
3898
c7ebf932 3899 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3900 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3901 &wm8994->fll_locked[i]);
3902
2a8a856d 3903 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3904 &wm8994->hubs);
2a8a856d
MB		 3905 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3906 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3907 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3908
af6b6fe4
MB		 3909 if (wm8994->jackdet)
3910 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3911
3a423157
MB		 3912 switch (control->type) {
3913 case WM8994:
9b7c525d
MB		 3914 if (wm8994->micdet_irq)
3915 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3916 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3917 wm8994);
2a8a856d 3918 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3919 wm8994);
2a8a856d 3920 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3921 wm8994);
3922 break;
821edd2f 3923
81204c84 3924 case WM1811:
821edd2f 3925 case WM8958:
9b7c525d
MB		 3926 if (wm8994->micdet_irq)
3927 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3928 break;
3a423157 3929 }
fbbf5920
MB		 3930 if (wm8994->mbc)
3931 release_firmware(wm8994->mbc);
09e10d7f
MB		 3932 if (wm8994->mbc_vss)
3933 release_firmware(wm8994->mbc_vss);
31215871
MB		 3934 if (wm8994->enh_eq)
3935 release_firmware(wm8994->enh_eq);
24fb2b11 3936 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 3937
3938 return 0;
3939}
3940
f0fba2ad
LG		 3941static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3942 .probe = wm8994_codec_probe,
3943 .remove = wm8994_codec_remove,
3944 .suspend = wm8994_suspend,
3945 .resume = wm8994_resume,
f0fba2ad
LG		 3946 .set_bias_level = wm8994_set_bias_level,
3947};
3948
3949static int __devinit wm8994_probe(struct platform_device *pdev)
3950{
2bc16ed8
MB		 3951 struct wm8994_priv *wm8994;
3952
3953 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
3954 GFP_KERNEL);
3955 if (wm8994 == NULL)
3956 return -ENOMEM;
3957 platform_set_drvdata(pdev, wm8994);
3958
3959 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
3960 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
3961
f0fba2ad
LG		 3962 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3963 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3964}
3965
3966static int __devexit wm8994_remove(struct platform_device *pdev)
3967{
3968 snd_soc_unregister_codec(&pdev->dev);
3969 return 0;
3970}
3971
9e6e96a1
MB		 3972static struct platform_driver wm8994_codec_driver = {
3973 .driver = {
3974 .name = "wm8994-codec",
3975 .owner = THIS_MODULE,
3976 },
f0fba2ad
LG		 3977 .probe = wm8994_probe,
3978 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3979};
3980
5bbcc3c0 3981module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 3982
3983MODULE_DESCRIPTION("ASoC WM8994 driver");
3984MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3985MODULE_LICENSE("GPL");
3986MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
This page took 0.900321 seconds and 5 git commands to generate.