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ASoC: Use delayed work to debounce WM8350 jack IRQs
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include <linux/mfd/wm8994/core.h>
33#include <linux/mfd/wm8994/registers.h>
34#include <linux/mfd/wm8994/pdata.h>
35#include <linux/mfd/wm8994/gpio.h>
36
37#include "wm8994.h"
38#include "wm_hubs.h"
39
9e6e96a1
MB		 40struct fll_config {
41 int src;
42 int in;
43 int out;
44};
45
46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
88766984
MB		 61struct wm8994_micdet {
62 struct snd_soc_jack *jack;
63 int det;
64 int shrt;
65};
66
9e6e96a1
MB		 67/* codec private data */
68struct wm8994_priv {
69 struct wm_hubs_data hubs;
f0fba2ad
LG		 70 enum snd_soc_control_type control_type;
71 void *control_data;
72 struct snd_soc_codec *codec;
9e6e96a1
MB		 73 int sysclk[2];
74 int sysclk_rate[2];
75 int mclk[2];
76 int aifclk[2];
77 struct fll_config fll[2], fll_suspend[2];
78
79 int dac_rates[2];
80 int lrclk_shared[2];
81
d6addcc9
MB		 82 int mbc_ena[3];
83
9e6e96a1
MB		 84 /* Platform dependant DRC configuration */
85 const char **drc_texts;
86 int drc_cfg[WM8994_NUM_DRC];
87 struct soc_enum drc_enum;
88
89 /* Platform dependant ReTune mobile configuration */
90 int num_retune_mobile_texts;
91 const char **retune_mobile_texts;
92 int retune_mobile_cfg[WM8994_NUM_EQ];
93 struct soc_enum retune_mobile_enum;
94
131d8106
MB		 95 /* Platform dependant MBC configuration */
96 int mbc_cfg;
97 const char **mbc_texts;
98 struct soc_enum mbc_enum;
99
88766984
MB		 100 struct wm8994_micdet micdet[2];
101
821edd2f
MB		 102 wm8958_micdet_cb jack_cb;
103 void *jack_cb_data;
104 bool jack_is_mic;
105 bool jack_is_video;
106
b6b05691 107 int revision;
9e6e96a1
MB		 108 struct wm8994_pdata *pdata;
109};
110
9e6e96a1
MB		 111static int wm8994_readable(unsigned int reg)
112{
e88ff1e6
MB		 113 switch (reg) {
114 case WM8994_GPIO_1:
115 case WM8994_GPIO_2:
116 case WM8994_GPIO_3:
117 case WM8994_GPIO_4:
118 case WM8994_GPIO_5:
119 case WM8994_GPIO_6:
120 case WM8994_GPIO_7:
121 case WM8994_GPIO_8:
122 case WM8994_GPIO_9:
123 case WM8994_GPIO_10:
124 case WM8994_GPIO_11:
125 case WM8994_INTERRUPT_STATUS_1:
126 case WM8994_INTERRUPT_STATUS_2:
127 case WM8994_INTERRUPT_RAW_STATUS_2:
128 return 1;
129 default:
130 break;
131 }
132
7b306dae 133 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 134 return 0;
7b306dae 135 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 136}
137
138static int wm8994_volatile(unsigned int reg)
139{
ca9aef50 140 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 141 return 1;
142
143 switch (reg) {
144 case WM8994_SOFTWARE_RESET:
145 case WM8994_CHIP_REVISION:
146 case WM8994_DC_SERVO_1:
147 case WM8994_DC_SERVO_READBACK:
148 case WM8994_RATE_STATUS:
149 case WM8994_LDO_1:
150 case WM8994_LDO_2:
d6addcc9 151 case WM8958_DSP2_EXECCONTROL:
821edd2f 152 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 153 return 1;
154 default:
155 return 0;
156 }
157}
158
159static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
160 unsigned int value)
161{
ca9aef50 162 int ret;
9e6e96a1
MB		 163
164 BUG_ON(reg > WM8994_MAX_REGISTER);
165
ca9aef50
MB		 166 if (!wm8994_volatile(reg)) {
167 ret = snd_soc_cache_write(codec, reg, value);
168 if (ret != 0)
169 dev_err(codec->dev, "Cache write to %x failed: %d\n",
170 reg, ret);
171 }
9e6e96a1
MB		 172
173 return wm8994_reg_write(codec->control_data, reg, value);
174}
175
176static unsigned int wm8994_read(struct snd_soc_codec *codec,
177 unsigned int reg)
178{
ca9aef50
MB		 179 unsigned int val;
180 int ret;
9e6e96a1
MB		 181
182 BUG_ON(reg > WM8994_MAX_REGISTER);
183
ca9aef50
MB		 184 if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
185 reg < codec->driver->reg_cache_size) {
186 ret = snd_soc_cache_read(codec, reg, &val);
187 if (ret >= 0)
188 return val;
189 else
190 dev_err(codec->dev, "Cache read from %x failed: %d\n",
191 reg, ret);
192 }
193
194 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 195}
196
197static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
198{
b2c812e2 199 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 200 int rate;
201 int reg1 = 0;
202 int offset;
203
204 if (aif)
205 offset = 4;
206 else
207 offset = 0;
208
209 switch (wm8994->sysclk[aif]) {
210 case WM8994_SYSCLK_MCLK1:
211 rate = wm8994->mclk[0];
212 break;
213
214 case WM8994_SYSCLK_MCLK2:
215 reg1 |= 0x8;
216 rate = wm8994->mclk[1];
217 break;
218
219 case WM8994_SYSCLK_FLL1:
220 reg1 |= 0x10;
221 rate = wm8994->fll[0].out;
222 break;
223
224 case WM8994_SYSCLK_FLL2:
225 reg1 |= 0x18;
226 rate = wm8994->fll[1].out;
227 break;
228
229 default:
230 return -EINVAL;
231 }
232
233 if (rate >= 13500000) {
234 rate /= 2;
235 reg1 |= WM8994_AIF1CLK_DIV;
236
237 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
238 aif + 1, rate);
239 }
5e5e2bef
MB		 240
241 if (rate && rate < 3000000)
242 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
243 aif + 1, rate);
244
9e6e96a1
MB		 245 wm8994->aifclk[aif] = rate;
246
247 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
248 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
249 reg1);
250
251 return 0;
252}
253
254static int configure_clock(struct snd_soc_codec *codec)
255{
b2c812e2 256 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 257 int old, new;
258
259 /* Bring up the AIF clocks first */
260 configure_aif_clock(codec, 0);
261 configure_aif_clock(codec, 1);
262
263 /* Then switch CLK_SYS over to the higher of them; a change
264 * can only happen as a result of a clocking change which can
265 * only be made outside of DAPM so we can safely redo the
266 * clocking.
267 */
268
269 /* If they're equal it doesn't matter which is used */
270 if (wm8994->aifclk[0] == wm8994->aifclk[1])
271 return 0;
272
273 if (wm8994->aifclk[0] < wm8994->aifclk[1])
274 new = WM8994_SYSCLK_SRC;
275 else
276 new = 0;
277
278 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
279
280 /* If there's no change then we're done. */
281 if (old == new)
282 return 0;
283
284 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
285
ce6120cc 286 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 287
288 return 0;
289}
290
291static int check_clk_sys(struct snd_soc_dapm_widget *source,
292 struct snd_soc_dapm_widget *sink)
293{
294 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
295 const char *clk;
296
297 /* Check what we're currently using for CLK_SYS */
298 if (reg & WM8994_SYSCLK_SRC)
299 clk = "AIF2CLK";
300 else
301 clk = "AIF1CLK";
302
303 return strcmp(source->name, clk) == 0;
304}
305
306static const char *sidetone_hpf_text[] = {
307 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
308};
309
310static const struct soc_enum sidetone_hpf =
311 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
312
146fd574
UK		 313static const char *adc_hpf_text[] = {
314 "HiFi", "Voice 1", "Voice 2", "Voice 3"
315};
316
317static const struct soc_enum aif1adc1_hpf =
318 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
319
320static const struct soc_enum aif1adc2_hpf =
321 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
322
323static const struct soc_enum aif2adc_hpf =
324 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
325
9e6e96a1
MB		 326static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
327static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
328static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
329static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
330static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
331
332#define WM8994_DRC_SWITCH(xname, reg, shift) \
333{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
334 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
335 .put = wm8994_put_drc_sw, \
336 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
337
338static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
339 struct snd_ctl_elem_value *ucontrol)
340{
341 struct soc_mixer_control *mc =
342 (struct soc_mixer_control *)kcontrol->private_value;
343 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
344 int mask, ret;
345
346 /* Can't enable both ADC and DAC paths simultaneously */
347 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
348 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
349 WM8994_AIF1ADC1R_DRC_ENA_MASK;
350 else
351 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
352
353 ret = snd_soc_read(codec, mc->reg);
354 if (ret < 0)
355 return ret;
356 if (ret & mask)
357 return -EINVAL;
358
359 return snd_soc_put_volsw(kcontrol, ucontrol);
360}
361
9e6e96a1
MB		 362static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
363{
b2c812e2 364 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 365 struct wm8994_pdata *pdata = wm8994->pdata;
366 int base = wm8994_drc_base[drc];
367 int cfg = wm8994->drc_cfg[drc];
368 int save, i;
369
370 /* Save any enables; the configuration should clear them. */
371 save = snd_soc_read(codec, base);
372 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
373 WM8994_AIF1ADC1R_DRC_ENA;
374
375 for (i = 0; i < WM8994_DRC_REGS; i++)
376 snd_soc_update_bits(codec, base + i, 0xffff,
377 pdata->drc_cfgs[cfg].regs[i]);
378
379 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
380 WM8994_AIF1ADC1L_DRC_ENA |
381 WM8994_AIF1ADC1R_DRC_ENA, save);
382}
383
384/* Icky as hell but saves code duplication */
385static int wm8994_get_drc(const char *name)
386{
387 if (strcmp(name, "AIF1DRC1 Mode") == 0)
388 return 0;
389 if (strcmp(name, "AIF1DRC2 Mode") == 0)
390 return 1;
391 if (strcmp(name, "AIF2DRC Mode") == 0)
392 return 2;
393 return -EINVAL;
394}
395
396static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
397 struct snd_ctl_elem_value *ucontrol)
398{
399 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 400 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 401 struct wm8994_pdata *pdata = wm8994->pdata;
402 int drc = wm8994_get_drc(kcontrol->id.name);
403 int value = ucontrol->value.integer.value[0];
404
405 if (drc < 0)
406 return drc;
407
408 if (value >= pdata->num_drc_cfgs)
409 return -EINVAL;
410
411 wm8994->drc_cfg[drc] = value;
412
413 wm8994_set_drc(codec, drc);
414
415 return 0;
416}
417
418static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 422 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 423 int drc = wm8994_get_drc(kcontrol->id.name);
424
425 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
426
427 return 0;
428}
429
430static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
431{
b2c812e2 432 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 433 struct wm8994_pdata *pdata = wm8994->pdata;
434 int base = wm8994_retune_mobile_base[block];
435 int iface, best, best_val, save, i, cfg;
436
437 if (!pdata || !wm8994->num_retune_mobile_texts)
438 return;
439
440 switch (block) {
441 case 0:
442 case 1:
443 iface = 0;
444 break;
445 case 2:
446 iface = 1;
447 break;
448 default:
449 return;
450 }
451
452 /* Find the version of the currently selected configuration
453 * with the nearest sample rate. */
454 cfg = wm8994->retune_mobile_cfg[block];
455 best = 0;
456 best_val = INT_MAX;
457 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
458 if (strcmp(pdata->retune_mobile_cfgs[i].name,
459 wm8994->retune_mobile_texts[cfg]) == 0 &&
460 abs(pdata->retune_mobile_cfgs[i].rate
461 - wm8994->dac_rates[iface]) < best_val) {
462 best = i;
463 best_val = abs(pdata->retune_mobile_cfgs[i].rate
464 - wm8994->dac_rates[iface]);
465 }
466 }
467
468 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
469 block,
470 pdata->retune_mobile_cfgs[best].name,
471 pdata->retune_mobile_cfgs[best].rate,
472 wm8994->dac_rates[iface]);
473
474 /* The EQ will be disabled while reconfiguring it, remember the
475 * current configuration.
476 */
477 save = snd_soc_read(codec, base);
478 save &= WM8994_AIF1DAC1_EQ_ENA;
479
480 for (i = 0; i < WM8994_EQ_REGS; i++)
481 snd_soc_update_bits(codec, base + i, 0xffff,
482 pdata->retune_mobile_cfgs[best].regs[i]);
483
484 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
485}
486
487/* Icky as hell but saves code duplication */
488static int wm8994_get_retune_mobile_block(const char *name)
489{
490 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
491 return 0;
492 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
493 return 1;
494 if (strcmp(name, "AIF2 EQ Mode") == 0)
495 return 2;
496 return -EINVAL;
497}
498
499static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
500 struct snd_ctl_elem_value *ucontrol)
501{
502 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 503 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 504 struct wm8994_pdata *pdata = wm8994->pdata;
505 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
506 int value = ucontrol->value.integer.value[0];
507
508 if (block < 0)
509 return block;
510
511 if (value >= pdata->num_retune_mobile_cfgs)
512 return -EINVAL;
513
514 wm8994->retune_mobile_cfg[block] = value;
515
516 wm8994_set_retune_mobile(codec, block);
517
518 return 0;
519}
520
521static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
522 struct snd_ctl_elem_value *ucontrol)
523{
524 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 525 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 526 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
527
528 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
529
530 return 0;
531}
532
96b101ef 533static const char *aif_chan_src_text[] = {
f554885f
MB		 534 "Left", "Right"
535};
536
96b101ef
MB		 537static const struct soc_enum aif1adcl_src =
538 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
539
540static const struct soc_enum aif1adcr_src =
541 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
542
543static const struct soc_enum aif2adcl_src =
544 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
545
546static const struct soc_enum aif2adcr_src =
547 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
548
f554885f 549static const struct soc_enum aif1dacl_src =
96b101ef 550 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 551
552static const struct soc_enum aif1dacr_src =
96b101ef 553 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 554
555static const struct soc_enum aif2dacl_src =
96b101ef 556 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 557
558static const struct soc_enum aif2dacr_src =
96b101ef 559 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 560
154b26aa
MB		 561static const char *osr_text[] = {
562 "Low Power", "High Performance",
563};
564
565static const struct soc_enum dac_osr =
566 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
567
568static const struct soc_enum adc_osr =
569 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
570
d6addcc9
MB		 571static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
572{
573 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
131d8106 574 struct wm8994_pdata *pdata = wm8994->pdata;
d6addcc9 575 int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
131d8106 576 int ena, reg, aif, i;
d6addcc9
MB		 577
578 switch (mbc) {
579 case 0:
580 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
581 aif = 0;
582 break;
583 case 1:
584 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
585 aif = 0;
586 break;
587 case 2:
588 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
589 aif = 1;
590 break;
591 default:
592 BUG();
593 return;
594 }
595
596 /* We can only enable the MBC if the AIF is enabled and we
597 * want it to be enabled. */
598 ena = pwr_reg && wm8994->mbc_ena[mbc];
599
600 reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
601
602 dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
603 mbc, start, pwr_reg, reg);
604
605 if (start && ena) {
606 /* If the DSP is already running then noop */
607 if (reg & WM8958_DSP2_ENA)
608 return;
609
610 /* Switch the clock over to the appropriate AIF */
611 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
612 WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
613 aif << WM8958_DSP2CLK_SRC_SHIFT |
614 WM8958_DSP2CLK_ENA);
615
616 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
617 WM8958_DSP2_ENA, WM8958_DSP2_ENA);
618
131d8106
MB		 619 /* If we've got user supplied MBC settings use them */
620 if (pdata && pdata->num_mbc_cfgs) {
621 struct wm8958_mbc_cfg *cfg
622 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
623
624 for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
625 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
626 cfg->coeff_regs[i]);
627
628 for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
629 snd_soc_write(codec,
630 i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
631 cfg->cutoff_regs[i]);
632 }
d6addcc9
MB		 633
634 /* Run the DSP */
635 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
636 WM8958_DSP2_RUNR);
637
638 /* And we're off! */
639 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
640 WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
641 mbc << WM8958_MBC_SEL_SHIFT |
642 WM8958_MBC_ENA);
643 } else {
644 /* If the DSP is already stopped then noop */
645 if (!(reg & WM8958_DSP2_ENA))
646 return;
647
648 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
649 WM8958_MBC_ENA, 0);
650 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
651 WM8958_DSP2_ENA, 0);
652 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
653 WM8958_DSP2CLK_ENA, 0);
654 }
655}
656
657static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
658 struct snd_kcontrol *kcontrol, int event)
659{
660 struct snd_soc_codec *codec = w->codec;
661 int mbc;
662
663 switch (w->shift) {
664 case 13:
665 case 12:
666 mbc = 2;
667 break;
668 case 11:
669 case 10:
670 mbc = 1;
671 break;
672 case 9:
673 case 8:
674 mbc = 0;
675 break;
676 default:
677 BUG();
678 return -EINVAL;
679 }
680
681 switch (event) {
682 case SND_SOC_DAPM_POST_PMU:
683 wm8958_mbc_apply(codec, mbc, 1);
684 break;
685 case SND_SOC_DAPM_POST_PMD:
686 wm8958_mbc_apply(codec, mbc, 0);
687 break;
688 }
689
690 return 0;
691}
692
131d8106
MB		 693static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
694 struct snd_ctl_elem_value *ucontrol)
695{
696 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
697 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
698 struct wm8994_pdata *pdata = wm8994->pdata;
699 int value = ucontrol->value.integer.value[0];
700 int reg;
701
702 /* Don't allow on the fly reconfiguration */
703 reg = snd_soc_read(codec, WM8994_CLOCKING_1);
704 if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
705 return -EBUSY;
706
707 if (value >= pdata->num_mbc_cfgs)
708 return -EINVAL;
709
710 wm8994->mbc_cfg = value;
711
712 return 0;
713}
714
715static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
716 struct snd_ctl_elem_value *ucontrol)
717{
718 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
719 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
720
721 ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
722
723 return 0;
724}
725
d6addcc9
MB		 726static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
727 struct snd_ctl_elem_info *uinfo)
728{
729 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
730 uinfo->count = 1;
731 uinfo->value.integer.min = 0;
732 uinfo->value.integer.max = 1;
733 return 0;
734}
735
736static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
737 struct snd_ctl_elem_value *ucontrol)
738{
739 int mbc = kcontrol->private_value;
740 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
741 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
742
743 ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
744
745 return 0;
746}
747
748static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
749 struct snd_ctl_elem_value *ucontrol)
750{
751 int mbc = kcontrol->private_value;
752 int i;
753 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
754 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
755
756 if (ucontrol->value.integer.value[0] > 1)
757 return -EINVAL;
758
759 for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
760 if (mbc != i && wm8994->mbc_ena[i]) {
761 dev_dbg(codec->dev, "MBC %d active already\n", mbc);
762 return -EBUSY;
763 }
764 }
765
766 wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
767
768 wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
769
770 return 0;
771}
772
773#define WM8958_MBC_SWITCH(xname, xval) {\
774 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
775 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
776 .info = wm8958_mbc_info, \
777 .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
778 .private_value = xval }
779
9e6e96a1
MB		 780static const struct snd_kcontrol_new wm8994_snd_controls[] = {
781SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
782 WM8994_AIF1_ADC1_RIGHT_VOLUME,
783 1, 119, 0, digital_tlv),
784SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
785 WM8994_AIF1_ADC2_RIGHT_VOLUME,
786 1, 119, 0, digital_tlv),
787SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
788 WM8994_AIF2_ADC_RIGHT_VOLUME,
789 1, 119, 0, digital_tlv),
790
96b101ef
MB		 791SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
792SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 793SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
794SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 795
f554885f
MB		 796SOC_ENUM("AIF1DACL Source", aif1dacl_src),
797SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 798SOC_ENUM("AIF2DACL Source", aif2dacl_src),
799SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 800
9e6e96a1
MB		 801SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
802 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
803SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
804 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
805SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
806 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
807
808SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
809SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
810
811SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
812SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
813SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
814
815WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
816WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
817WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
818
819WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
820WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
821WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
822
823WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
824WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
825WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
826
827SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
828 5, 12, 0, st_tlv),
829SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
830 0, 12, 0, st_tlv),
831SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
832 5, 12, 0, st_tlv),
833SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
834 0, 12, 0, st_tlv),
835SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
836SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
837
146fd574
UK		 838SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
839SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
840
841SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
842SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
843
844SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
845SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
846
154b26aa
MB		 847SOC_ENUM("ADC OSR", adc_osr),
848SOC_ENUM("DAC OSR", dac_osr),
849
9e6e96a1
MB		 850SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
851 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
852SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
853 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
854
855SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
856 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
857SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
858 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
859
860SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
861 6, 1, 1, wm_hubs_spkmix_tlv),
862SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
863 2, 1, 1, wm_hubs_spkmix_tlv),
864
865SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
866 6, 1, 1, wm_hubs_spkmix_tlv),
867SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
868 2, 1, 1, wm_hubs_spkmix_tlv),
869
870SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
871 10, 15, 0, wm8994_3d_tlv),
458350b3 872SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 873 8, 1, 0),
874SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
875 10, 15, 0, wm8994_3d_tlv),
876SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
877 8, 1, 0),
458350b3 878SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 879 10, 15, 0, wm8994_3d_tlv),
458350b3 880SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 881 8, 1, 0),
882};
883
884static const struct snd_kcontrol_new wm8994_eq_controls[] = {
885SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
886 eq_tlv),
887SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
888 eq_tlv),
889SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
890 eq_tlv),
891SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
892 eq_tlv),
893SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
894 eq_tlv),
895
896SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
897 eq_tlv),
898SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
899 eq_tlv),
900SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
901 eq_tlv),
902SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
903 eq_tlv),
904SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
905 eq_tlv),
906
907SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
908 eq_tlv),
909SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
910 eq_tlv),
911SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
912 eq_tlv),
913SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
914 eq_tlv),
915SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
916 eq_tlv),
917};
918
c4431df0
MB		 919static const struct snd_kcontrol_new wm8958_snd_controls[] = {
920SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
d6addcc9
MB		 921WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
922WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
923WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
c4431df0
MB		 924};
925
9e6e96a1
MB		 926static int clk_sys_event(struct snd_soc_dapm_widget *w,
927 struct snd_kcontrol *kcontrol, int event)
928{
929 struct snd_soc_codec *codec = w->codec;
930
931 switch (event) {
932 case SND_SOC_DAPM_PRE_PMU:
933 return configure_clock(codec);
934
935 case SND_SOC_DAPM_POST_PMD:
936 configure_clock(codec);
937 break;
938 }
939
940 return 0;
941}
942
943static void wm8994_update_class_w(struct snd_soc_codec *codec)
944{
fec6dd83 945 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 946 int enable = 1;
947 int source = 0; /* GCC flow analysis can't track enable */
948 int reg, reg_r;
949
950 /* Only support direct DAC->headphone paths */
951 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
952 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 953 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 954 enable = 0;
955 }
956
957 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
958 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 959 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 960 enable = 0;
961 }
962
963 /* We also need the same setting for L/R and only one path */
964 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
965 switch (reg) {
966 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 967 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 968 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
969 break;
970 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 971 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 972 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
973 break;
974 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 975 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 976 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
977 break;
978 default:
ee839a21 979 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 980 enable = 0;
981 break;
982 }
983
984 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
985 if (reg_r != reg) {
ee839a21 986 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 987 enable = 0;
988 }
989
990 if (enable) {
991 dev_dbg(codec->dev, "Class W enabled\n");
992 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
993 WM8994_CP_DYN_PWR |
994 WM8994_CP_DYN_SRC_SEL_MASK,
995 source | WM8994_CP_DYN_PWR);
fec6dd83 996 wm8994->hubs.class_w = true;
9e6e96a1
MB		 997
998 } else {
999 dev_dbg(codec->dev, "Class W disabled\n");
1000 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1001 WM8994_CP_DYN_PWR, 0);
fec6dd83 1002 wm8994->hubs.class_w = false;
9e6e96a1
MB		 1003 }
1004}
1005
1006static const char *hp_mux_text[] = {
1007 "Mixer",
1008 "DAC",
1009};
1010
1011#define WM8994_HP_ENUM(xname, xenum) \
1012{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1013 .info = snd_soc_info_enum_double, \
1014 .get = snd_soc_dapm_get_enum_double, \
1015 .put = wm8994_put_hp_enum, \
1016 .private_value = (unsigned long)&xenum }
1017
1018static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1019 struct snd_ctl_elem_value *ucontrol)
1020{
1021 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1022 struct snd_soc_codec *codec = w->codec;
1023 int ret;
1024
1025 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1026
1027 wm8994_update_class_w(codec);
1028
1029 return ret;
1030}
1031
1032static const struct soc_enum hpl_enum =
1033 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1034
1035static const struct snd_kcontrol_new hpl_mux =
1036 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1037
1038static const struct soc_enum hpr_enum =
1039 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1040
1041static const struct snd_kcontrol_new hpr_mux =
1042 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1043
1044static const char *adc_mux_text[] = {
1045 "ADC",
1046 "DMIC",
1047};
1048
1049static const struct soc_enum adc_enum =
1050 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1051
1052static const struct snd_kcontrol_new adcl_mux =
1053 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1054
1055static const struct snd_kcontrol_new adcr_mux =
1056 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1057
1058static const struct snd_kcontrol_new left_speaker_mixer[] = {
1059SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1060SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1061SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1062SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1063SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1064};
1065
1066static const struct snd_kcontrol_new right_speaker_mixer[] = {
1067SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1068SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1069SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1070SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1071SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1072};
1073
1074/* Debugging; dump chip status after DAPM transitions */
1075static int post_ev(struct snd_soc_dapm_widget *w,
1076 struct snd_kcontrol *kcontrol, int event)
1077{
1078 struct snd_soc_codec *codec = w->codec;
1079 dev_dbg(codec->dev, "SRC status: %x\n",
1080 snd_soc_read(codec,
1081 WM8994_RATE_STATUS));
1082 return 0;
1083}
1084
1085static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1086SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1087 1, 1, 0),
1088SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1089 0, 1, 0),
1090};
1091
1092static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1093SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1094 1, 1, 0),
1095SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1096 0, 1, 0),
1097};
1098
a3257ba8
MB		 1099static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1100SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1101 1, 1, 0),
1102SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1103 0, 1, 0),
1104};
1105
1106static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1107SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1108 1, 1, 0),
1109SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1110 0, 1, 0),
1111};
1112
9e6e96a1
MB		 1113static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1114SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1115 5, 1, 0),
1116SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1117 4, 1, 0),
1118SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1119 2, 1, 0),
1120SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1121 1, 1, 0),
1122SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1123 0, 1, 0),
1124};
1125
1126static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1127SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1128 5, 1, 0),
1129SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1130 4, 1, 0),
1131SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1132 2, 1, 0),
1133SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1134 1, 1, 0),
1135SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1136 0, 1, 0),
1137};
1138
1139#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1140{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1141 .info = snd_soc_info_volsw, \
1142 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1143 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1144
1145static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1146 struct snd_ctl_elem_value *ucontrol)
1147{
1148 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1149 struct snd_soc_codec *codec = w->codec;
1150 int ret;
1151
1152 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1153
1154 wm8994_update_class_w(codec);
1155
1156 return ret;
1157}
1158
1159static const struct snd_kcontrol_new dac1l_mix[] = {
1160WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1161 5, 1, 0),
1162WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1163 4, 1, 0),
1164WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1165 2, 1, 0),
1166WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1167 1, 1, 0),
1168WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1169 0, 1, 0),
1170};
1171
1172static const struct snd_kcontrol_new dac1r_mix[] = {
1173WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1174 5, 1, 0),
1175WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1176 4, 1, 0),
1177WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1178 2, 1, 0),
1179WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1180 1, 1, 0),
1181WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1182 0, 1, 0),
1183};
1184
1185static const char *sidetone_text[] = {
1186 "ADC/DMIC1", "DMIC2",
1187};
1188
1189static const struct soc_enum sidetone1_enum =
1190 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1191
1192static const struct snd_kcontrol_new sidetone1_mux =
1193 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1194
1195static const struct soc_enum sidetone2_enum =
1196 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1197
1198static const struct snd_kcontrol_new sidetone2_mux =
1199 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1200
1201static const char *aif1dac_text[] = {
1202 "AIF1DACDAT", "AIF3DACDAT",
1203};
1204
1205static const struct soc_enum aif1dac_enum =
1206 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1207
1208static const struct snd_kcontrol_new aif1dac_mux =
1209 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1210
1211static const char *aif2dac_text[] = {
1212 "AIF2DACDAT", "AIF3DACDAT",
1213};
1214
1215static const struct soc_enum aif2dac_enum =
1216 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1217
1218static const struct snd_kcontrol_new aif2dac_mux =
1219 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1220
1221static const char *aif2adc_text[] = {
1222 "AIF2ADCDAT", "AIF3DACDAT",
1223};
1224
1225static const struct soc_enum aif2adc_enum =
1226 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1227
1228static const struct snd_kcontrol_new aif2adc_mux =
1229 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1230
1231static const char *aif3adc_text[] = {
c4431df0 1232 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1233};
1234
c4431df0 1235static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1236 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1237
c4431df0
MB		 1238static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1239 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1240
1241static const struct soc_enum wm8958_aif3adc_enum =
1242 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1243
1244static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1245 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1246
1247static const char *mono_pcm_out_text[] = {
1248 "None", "AIF2ADCL", "AIF2ADCR",
1249};
1250
1251static const struct soc_enum mono_pcm_out_enum =
1252 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1253
1254static const struct snd_kcontrol_new mono_pcm_out_mux =
1255 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1256
1257static const char *aif2dac_src_text[] = {
1258 "AIF2", "AIF3",
1259};
1260
1261/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1262static const struct soc_enum aif2dacl_src_enum =
1263 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1264
1265static const struct snd_kcontrol_new aif2dacl_src_mux =
1266 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1267
1268static const struct soc_enum aif2dacr_src_enum =
1269 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1270
1271static const struct snd_kcontrol_new aif2dacr_src_mux =
1272 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1
MB		 1273
1274static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1275SND_SOC_DAPM_INPUT("DMIC1DAT"),
1276SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1277SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 1278
1279SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1280 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1281
1282SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1283SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1284SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1285
1286SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1287SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1288
1289SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
1290 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1291SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
1292 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1293SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1294 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1295 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1296SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1297 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1298 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1299
1300SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
1301 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1302SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
1303 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1304SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1305 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1306 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1307SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1308 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1309 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1310
1311SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1312 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1313SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1314 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1315
a3257ba8
MB		 1316SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1317 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1318SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1319 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1320
9e6e96a1
MB		 1321SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1322 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1323SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1324 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1325
1326SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1327SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1328
1329SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1330 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1331SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1332 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1333
1334SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1335 WM8994_POWER_MANAGEMENT_4, 13, 0),
1336SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1337 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1338SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1339 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1340 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1341SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1342 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1343 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1344
1345SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1346SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1347SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1348
1349SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1350SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1351SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1352
1353SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1354SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1355
1356SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1357
1358SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1359SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1360SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1361SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1362
1363/* Power is done with the muxes since the ADC power also controls the
1364 * downsampling chain, the chip will automatically manage the analogue
1365 * specific portions.
1366 */
1367SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1368SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1369
1370SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1371SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1372
1373SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1374SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1375SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1376SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1377
1378SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1379SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1380
1381SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1382 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1383SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1384 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1385
1386SND_SOC_DAPM_POST("Debug log", post_ev),
1387};
1388
c4431df0
MB		 1389static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1390SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1391};
9e6e96a1 1392
c4431df0
MB		 1393static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1394SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1395SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1396SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1397SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1398};
1399
1400static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1401 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1402 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1403
1404 { "DSP1CLK", NULL, "CLK_SYS" },
1405 { "DSP2CLK", NULL, "CLK_SYS" },
1406 { "DSPINTCLK", NULL, "CLK_SYS" },
1407
1408 { "AIF1ADC1L", NULL, "AIF1CLK" },
1409 { "AIF1ADC1L", NULL, "DSP1CLK" },
1410 { "AIF1ADC1R", NULL, "AIF1CLK" },
1411 { "AIF1ADC1R", NULL, "DSP1CLK" },
1412 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1413
1414 { "AIF1DAC1L", NULL, "AIF1CLK" },
1415 { "AIF1DAC1L", NULL, "DSP1CLK" },
1416 { "AIF1DAC1R", NULL, "AIF1CLK" },
1417 { "AIF1DAC1R", NULL, "DSP1CLK" },
1418 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1419
1420 { "AIF1ADC2L", NULL, "AIF1CLK" },
1421 { "AIF1ADC2L", NULL, "DSP1CLK" },
1422 { "AIF1ADC2R", NULL, "AIF1CLK" },
1423 { "AIF1ADC2R", NULL, "DSP1CLK" },
1424 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1425
1426 { "AIF1DAC2L", NULL, "AIF1CLK" },
1427 { "AIF1DAC2L", NULL, "DSP1CLK" },
1428 { "AIF1DAC2R", NULL, "AIF1CLK" },
1429 { "AIF1DAC2R", NULL, "DSP1CLK" },
1430 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1431
1432 { "AIF2ADCL", NULL, "AIF2CLK" },
1433 { "AIF2ADCL", NULL, "DSP2CLK" },
1434 { "AIF2ADCR", NULL, "AIF2CLK" },
1435 { "AIF2ADCR", NULL, "DSP2CLK" },
1436 { "AIF2ADCR", NULL, "DSPINTCLK" },
1437
1438 { "AIF2DACL", NULL, "AIF2CLK" },
1439 { "AIF2DACL", NULL, "DSP2CLK" },
1440 { "AIF2DACR", NULL, "AIF2CLK" },
1441 { "AIF2DACR", NULL, "DSP2CLK" },
1442 { "AIF2DACR", NULL, "DSPINTCLK" },
1443
1444 { "DMIC1L", NULL, "DMIC1DAT" },
1445 { "DMIC1L", NULL, "CLK_SYS" },
1446 { "DMIC1R", NULL, "DMIC1DAT" },
1447 { "DMIC1R", NULL, "CLK_SYS" },
1448 { "DMIC2L", NULL, "DMIC2DAT" },
1449 { "DMIC2L", NULL, "CLK_SYS" },
1450 { "DMIC2R", NULL, "DMIC2DAT" },
1451 { "DMIC2R", NULL, "CLK_SYS" },
1452
1453 { "ADCL", NULL, "AIF1CLK" },
1454 { "ADCL", NULL, "DSP1CLK" },
1455 { "ADCL", NULL, "DSPINTCLK" },
1456
1457 { "ADCR", NULL, "AIF1CLK" },
1458 { "ADCR", NULL, "DSP1CLK" },
1459 { "ADCR", NULL, "DSPINTCLK" },
1460
1461 { "ADCL Mux", "ADC", "ADCL" },
1462 { "ADCL Mux", "DMIC", "DMIC1L" },
1463 { "ADCR Mux", "ADC", "ADCR" },
1464 { "ADCR Mux", "DMIC", "DMIC1R" },
1465
1466 { "DAC1L", NULL, "AIF1CLK" },
1467 { "DAC1L", NULL, "DSP1CLK" },
1468 { "DAC1L", NULL, "DSPINTCLK" },
1469
1470 { "DAC1R", NULL, "AIF1CLK" },
1471 { "DAC1R", NULL, "DSP1CLK" },
1472 { "DAC1R", NULL, "DSPINTCLK" },
1473
1474 { "DAC2L", NULL, "AIF2CLK" },
1475 { "DAC2L", NULL, "DSP2CLK" },
1476 { "DAC2L", NULL, "DSPINTCLK" },
1477
1478 { "DAC2R", NULL, "AIF2DACR" },
1479 { "DAC2R", NULL, "AIF2CLK" },
1480 { "DAC2R", NULL, "DSP2CLK" },
1481 { "DAC2R", NULL, "DSPINTCLK" },
1482
1483 { "TOCLK", NULL, "CLK_SYS" },
1484
1485 /* AIF1 outputs */
1486 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1487 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1488 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1489
1490 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1491 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1492 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1493
a3257ba8
MB		 1494 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1495 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1496 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1497
1498 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1499 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1500 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1501
9e6e96a1
MB		 1502 /* Pin level routing for AIF3 */
1503 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1504 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1505 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1506 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1507
9e6e96a1
MB		 1508 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1509 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1510 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1511 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1512 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1513 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1514 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1515
1516 /* DAC1 inputs */
1517 { "DAC1L", NULL, "DAC1L Mixer" },
1518 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1519 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1520 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1521 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1522 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1523
1524 { "DAC1R", NULL, "DAC1R Mixer" },
1525 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1526 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1527 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1528 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1529 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1530
1531 /* DAC2/AIF2 outputs */
1532 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1533 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1534 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1535 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1536 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1537 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1538 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1539
1540 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1541 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1542 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1543 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1544 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1545 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1546 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1547
1548 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1549
1550 /* AIF3 output */
1551 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1552 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1553 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1554 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1555 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1556 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1557 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1558 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1559
1560 /* Sidetone */
1561 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1562 { "Left Sidetone", "DMIC2", "DMIC2L" },
1563 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1564 { "Right Sidetone", "DMIC2", "DMIC2R" },
1565
1566 /* Output stages */
1567 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1568 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1569
1570 { "SPKL", "DAC1 Switch", "DAC1L" },
1571 { "SPKL", "DAC2 Switch", "DAC2L" },
1572
1573 { "SPKR", "DAC1 Switch", "DAC1R" },
1574 { "SPKR", "DAC2 Switch", "DAC2R" },
1575
1576 { "Left Headphone Mux", "DAC", "DAC1L" },
1577 { "Right Headphone Mux", "DAC", "DAC1R" },
1578};
1579
c4431df0
MB		 1580static const struct snd_soc_dapm_route wm8994_intercon[] = {
1581 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1582 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1583};
1584
1585static const struct snd_soc_dapm_route wm8958_intercon[] = {
1586 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1587 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1588
1589 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1590 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1591 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1592 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1593
1594 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1595 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1596
1597 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1598};
1599
9e6e96a1
MB		 1600/* The size in bits of the FLL divide multiplied by 10
1601 * to allow rounding later */
1602#define FIXED_FLL_SIZE ((1 << 16) * 10)
1603
1604struct fll_div {
1605 u16 outdiv;
1606 u16 n;
1607 u16 k;
1608 u16 clk_ref_div;
1609 u16 fll_fratio;
1610};
1611
1612static int wm8994_get_fll_config(struct fll_div *fll,
1613 int freq_in, int freq_out)
1614{
1615 u64 Kpart;
1616 unsigned int K, Ndiv, Nmod;
1617
1618 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1619
1620 /* Scale the input frequency down to <= 13.5MHz */
1621 fll->clk_ref_div = 0;
1622 while (freq_in > 13500000) {
1623 fll->clk_ref_div++;
1624 freq_in /= 2;
1625
1626 if (fll->clk_ref_div > 3)
1627 return -EINVAL;
1628 }
1629 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1630
1631 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1632 fll->outdiv = 3;
1633 while (freq_out * (fll->outdiv + 1) < 90000000) {
1634 fll->outdiv++;
1635 if (fll->outdiv > 63)
1636 return -EINVAL;
1637 }
1638 freq_out *= fll->outdiv + 1;
1639 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1640
1641 if (freq_in > 1000000) {
1642 fll->fll_fratio = 0;
7d48a6ac
MB		 1643 } else if (freq_in > 256000) {
1644 fll->fll_fratio = 1;
1645 freq_in *= 2;
1646 } else if (freq_in > 128000) {
1647 fll->fll_fratio = 2;
1648 freq_in *= 4;
1649 } else if (freq_in > 64000) {
9e6e96a1
MB		 1650 fll->fll_fratio = 3;
1651 freq_in *= 8;
7d48a6ac
MB		 1652 } else {
1653 fll->fll_fratio = 4;
1654 freq_in *= 16;
9e6e96a1
MB		 1655 }
1656 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1657
1658 /* Now, calculate N.K */
1659 Ndiv = freq_out / freq_in;
1660
1661 fll->n = Ndiv;
1662 Nmod = freq_out % freq_in;
1663 pr_debug("Nmod=%d\n", Nmod);
1664
1665 /* Calculate fractional part - scale up so we can round. */
1666 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1667
1668 do_div(Kpart, freq_in);
1669
1670 K = Kpart & 0xFFFFFFFF;
1671
1672 if ((K % 10) >= 5)
1673 K += 5;
1674
1675 /* Move down to proper range now rounding is done */
1676 fll->k = K / 10;
1677
1678 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1679
1680 return 0;
1681}
1682
f0fba2ad 1683static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1684 unsigned int freq_in, unsigned int freq_out)
1685{
b2c812e2 1686 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1687 int reg_offset, ret;
1688 struct fll_div fll;
1689 u16 reg, aif1, aif2;
1690
1691 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1692 & WM8994_AIF1CLK_ENA;
1693
1694 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1695 & WM8994_AIF2CLK_ENA;
1696
1697 switch (id) {
1698 case WM8994_FLL1:
1699 reg_offset = 0;
1700 id = 0;
1701 break;
1702 case WM8994_FLL2:
1703 reg_offset = 0x20;
1704 id = 1;
1705 break;
1706 default:
1707 return -EINVAL;
1708 }
1709
136ff2a2 1710 switch (src) {
7add84aa
MB		 1711 case 0:
1712 /* Allow no source specification when stopping */
1713 if (freq_out)
1714 return -EINVAL;
4514e899 1715 src = wm8994->fll[id].src;
7add84aa 1716 break;
136ff2a2
MB		 1717 case WM8994_FLL_SRC_MCLK1:
1718 case WM8994_FLL_SRC_MCLK2:
1719 case WM8994_FLL_SRC_LRCLK:
1720 case WM8994_FLL_SRC_BCLK:
1721 break;
1722 default:
1723 return -EINVAL;
1724 }
1725
9e6e96a1
MB		 1726 /* Are we changing anything? */
1727 if (wm8994->fll[id].src == src &&
1728 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1729 return 0;
1730
1731 /* If we're stopping the FLL redo the old config - no
1732 * registers will actually be written but we avoid GCC flow
1733 * analysis bugs spewing warnings.
1734 */
1735 if (freq_out)
1736 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1737 else
1738 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1739 wm8994->fll[id].out);
1740 if (ret < 0)
1741 return ret;
1742
1743 /* Gate the AIF clocks while we reclock */
1744 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1745 WM8994_AIF1CLK_ENA, 0);
1746 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1747 WM8994_AIF2CLK_ENA, 0);
1748
1749 /* We always need to disable the FLL while reconfiguring */
1750 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1751 WM8994_FLL1_ENA, 0);
1752
1753 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1754 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1755 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1756 WM8994_FLL1_OUTDIV_MASK |
1757 WM8994_FLL1_FRATIO_MASK, reg);
1758
1759 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1760
1761 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1762 WM8994_FLL1_N_MASK,
1763 fll.n << WM8994_FLL1_N_SHIFT);
1764
1765 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1766 WM8994_FLL1_REFCLK_DIV_MASK |
1767 WM8994_FLL1_REFCLK_SRC_MASK,
1768 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1769 (src - 1));
9e6e96a1
MB		 1770
1771 /* Enable (with fractional mode if required) */
1772 if (freq_out) {
1773 if (fll.k)
1774 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1775 else
1776 reg = WM8994_FLL1_ENA;
1777 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1778 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1779 reg);
1780 }
1781
1782 wm8994->fll[id].in = freq_in;
1783 wm8994->fll[id].out = freq_out;
136ff2a2 1784 wm8994->fll[id].src = src;
9e6e96a1
MB		 1785
1786 /* Enable any gated AIF clocks */
1787 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1788 WM8994_AIF1CLK_ENA, aif1);
1789 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1790 WM8994_AIF2CLK_ENA, aif2);
1791
1792 configure_clock(codec);
1793
1794 return 0;
1795}
1796
f0fba2ad 1797
66b47fdb
MB		 1798static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1799
f0fba2ad
LG		 1800static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1801 unsigned int freq_in, unsigned int freq_out)
1802{
1803 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1804}
1805
9e6e96a1
MB		 1806static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1807 int clk_id, unsigned int freq, int dir)
1808{
1809 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1810 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1811 int i;
9e6e96a1
MB		 1812
1813 switch (dai->id) {
1814 case 1:
1815 case 2:
1816 break;
1817
1818 default:
1819 /* AIF3 shares clocking with AIF1/2 */
1820 return -EINVAL;
1821 }
1822
1823 switch (clk_id) {
1824 case WM8994_SYSCLK_MCLK1:
1825 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1826 wm8994->mclk[0] = freq;
1827 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1828 dai->id, freq);
1829 break;
1830
1831 case WM8994_SYSCLK_MCLK2:
1832 /* TODO: Set GPIO AF */
1833 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1834 wm8994->mclk[1] = freq;
1835 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1836 dai->id, freq);
1837 break;
1838
1839 case WM8994_SYSCLK_FLL1:
1840 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1841 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1842 break;
1843
1844 case WM8994_SYSCLK_FLL2:
1845 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1846 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1847 break;
1848
66b47fdb
MB		 1849 case WM8994_SYSCLK_OPCLK:
1850 /* Special case - a division (times 10) is given and
1851 * no effect on main clocking.
1852 */
1853 if (freq) {
1854 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1855 if (opclk_divs[i] == freq)
1856 break;
1857 if (i == ARRAY_SIZE(opclk_divs))
1858 return -EINVAL;
1859 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1860 WM8994_OPCLK_DIV_MASK, i);
1861 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1862 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1863 } else {
1864 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1865 WM8994_OPCLK_ENA, 0);
1866 }
1867
9e6e96a1
MB		 1868 default:
1869 return -EINVAL;
1870 }
1871
1872 configure_clock(codec);
1873
1874 return 0;
1875}
1876
1877static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1878 enum snd_soc_bias_level level)
1879{
3a423157 1880 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1881 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1882
9e6e96a1
MB		 1883 switch (level) {
1884 case SND_SOC_BIAS_ON:
1885 break;
1886
1887 case SND_SOC_BIAS_PREPARE:
1888 /* VMID=2x40k */
1889 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1890 WM8994_VMID_SEL_MASK, 0x2);
1891 break;
1892
1893 case SND_SOC_BIAS_STANDBY:
ce6120cc 1894 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 1895 pm_runtime_get_sync(codec->dev);
1896
8bc3c2c2
MB		 1897 switch (control->type) {
1898 case WM8994:
1899 if (wm8994->revision < 4) {
1900 /* Tweak DC servo and DSP
1901 * configuration for improved
1902 * performance. */
1903 snd_soc_write(codec, 0x102, 0x3);
1904 snd_soc_write(codec, 0x56, 0x3);
1905 snd_soc_write(codec, 0x817, 0);
1906 snd_soc_write(codec, 0x102, 0);
1907 }
1908 break;
1909
1910 case WM8958:
1911 if (wm8994->revision == 0) {
1912 /* Optimise performance for rev A */
1913 snd_soc_write(codec, 0x102, 0x3);
1914 snd_soc_write(codec, 0xcb, 0x81);
1915 snd_soc_write(codec, 0x817, 0);
1916 snd_soc_write(codec, 0x102, 0);
1917
1918 snd_soc_update_bits(codec,
1919 WM8958_CHARGE_PUMP_2,
1920 WM8958_CP_DISCH,
1921 WM8958_CP_DISCH);
1922 }
1923 break;
b6b05691 1924 }
9e6e96a1
MB		 1925
1926 /* Discharge LINEOUT1 & 2 */
1927 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1928 WM8994_LINEOUT1_DISCH |
1929 WM8994_LINEOUT2_DISCH,
1930 WM8994_LINEOUT1_DISCH |
1931 WM8994_LINEOUT2_DISCH);
1932
1933 /* Startup bias, VMID ramp & buffer */
1934 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1935 WM8994_STARTUP_BIAS_ENA |
1936 WM8994_VMID_BUF_ENA |
1937 WM8994_VMID_RAMP_MASK,
1938 WM8994_STARTUP_BIAS_ENA |
1939 WM8994_VMID_BUF_ENA |
1940 (0x11 << WM8994_VMID_RAMP_SHIFT));
1941
1942 /* Main bias enable, VMID=2x40k */
1943 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1944 WM8994_BIAS_ENA |
1945 WM8994_VMID_SEL_MASK,
1946 WM8994_BIAS_ENA | 0x2);
1947
1948 msleep(20);
1949 }
1950
1951 /* VMID=2x500k */
1952 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1953 WM8994_VMID_SEL_MASK, 0x4);
1954
1955 break;
1956
1957 case SND_SOC_BIAS_OFF:
ce6120cc 1958 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1959 /* Switch over to startup biases */
1960 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1961 WM8994_BIAS_SRC |
1962 WM8994_STARTUP_BIAS_ENA |
1963 WM8994_VMID_BUF_ENA |
1964 WM8994_VMID_RAMP_MASK,
1965 WM8994_BIAS_SRC |
1966 WM8994_STARTUP_BIAS_ENA |
1967 WM8994_VMID_BUF_ENA |
1968 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1969
d522ffbf
MB		 1970 /* Disable main biases */
1971 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1972 WM8994_BIAS_ENA |
1973 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1974
d522ffbf
MB		 1975 /* Discharge line */
1976 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1977 WM8994_LINEOUT1_DISCH |
1978 WM8994_LINEOUT2_DISCH,
1979 WM8994_LINEOUT1_DISCH |
1980 WM8994_LINEOUT2_DISCH);
9e6e96a1 1981
d522ffbf 1982 msleep(5);
9e6e96a1 1983
d522ffbf
MB		 1984 /* Switch off startup biases */
1985 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1986 WM8994_BIAS_SRC |
1987 WM8994_STARTUP_BIAS_ENA |
1988 WM8994_VMID_BUF_ENA |
1989 WM8994_VMID_RAMP_MASK, 0);
39fb51a1
MB		 1990
1991 pm_runtime_put(codec->dev);
d522ffbf 1992 }
9e6e96a1
MB		 1993 break;
1994 }
ce6120cc 1995 codec->dapm.bias_level = level;
9e6e96a1
MB		 1996 return 0;
1997}
1998
1999static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2000{
2001 struct snd_soc_codec *codec = dai->codec;
c4431df0 2002 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2003 int ms_reg;
2004 int aif1_reg;
2005 int ms = 0;
2006 int aif1 = 0;
2007
2008 switch (dai->id) {
2009 case 1:
2010 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2011 aif1_reg = WM8994_AIF1_CONTROL_1;
2012 break;
2013 case 2:
2014 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2015 aif1_reg = WM8994_AIF2_CONTROL_1;
2016 break;
2017 default:
2018 return -EINVAL;
2019 }
2020
2021 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2022 case SND_SOC_DAIFMT_CBS_CFS:
2023 break;
2024 case SND_SOC_DAIFMT_CBM_CFM:
2025 ms = WM8994_AIF1_MSTR;
2026 break;
2027 default:
2028 return -EINVAL;
2029 }
2030
2031 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2032 case SND_SOC_DAIFMT_DSP_B:
2033 aif1 |= WM8994_AIF1_LRCLK_INV;
2034 case SND_SOC_DAIFMT_DSP_A:
2035 aif1 |= 0x18;
2036 break;
2037 case SND_SOC_DAIFMT_I2S:
2038 aif1 |= 0x10;
2039 break;
2040 case SND_SOC_DAIFMT_RIGHT_J:
2041 break;
2042 case SND_SOC_DAIFMT_LEFT_J:
2043 aif1 |= 0x8;
2044 break;
2045 default:
2046 return -EINVAL;
2047 }
2048
2049 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2050 case SND_SOC_DAIFMT_DSP_A:
2051 case SND_SOC_DAIFMT_DSP_B:
2052 /* frame inversion not valid for DSP modes */
2053 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2054 case SND_SOC_DAIFMT_NB_NF:
2055 break;
2056 case SND_SOC_DAIFMT_IB_NF:
2057 aif1 |= WM8994_AIF1_BCLK_INV;
2058 break;
2059 default:
2060 return -EINVAL;
2061 }
2062 break;
2063
2064 case SND_SOC_DAIFMT_I2S:
2065 case SND_SOC_DAIFMT_RIGHT_J:
2066 case SND_SOC_DAIFMT_LEFT_J:
2067 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2068 case SND_SOC_DAIFMT_NB_NF:
2069 break;
2070 case SND_SOC_DAIFMT_IB_IF:
2071 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2072 break;
2073 case SND_SOC_DAIFMT_IB_NF:
2074 aif1 |= WM8994_AIF1_BCLK_INV;
2075 break;
2076 case SND_SOC_DAIFMT_NB_IF:
2077 aif1 |= WM8994_AIF1_LRCLK_INV;
2078 break;
2079 default:
2080 return -EINVAL;
2081 }
2082 break;
2083 default:
2084 return -EINVAL;
2085 }
2086
c4431df0
MB		 2087 /* The AIF2 format configuration needs to be mirrored to AIF3
2088 * on WM8958 if it's in use so just do it all the time. */
2089 if (control->type == WM8958 && dai->id == 2)
2090 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2091 WM8994_AIF1_LRCLK_INV |
2092 WM8958_AIF3_FMT_MASK, aif1);
2093
9e6e96a1
MB		 2094 snd_soc_update_bits(codec, aif1_reg,
2095 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2096 WM8994_AIF1_FMT_MASK,
2097 aif1);
2098 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2099 ms);
2100
2101 return 0;
2102}
2103
2104static struct {
2105 int val, rate;
2106} srs[] = {
2107 { 0, 8000 },
2108 { 1, 11025 },
2109 { 2, 12000 },
2110 { 3, 16000 },
2111 { 4, 22050 },
2112 { 5, 24000 },
2113 { 6, 32000 },
2114 { 7, 44100 },
2115 { 8, 48000 },
2116 { 9, 88200 },
2117 { 10, 96000 },
2118};
2119
2120static int fs_ratios[] = {
2121 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2122};
2123
2124static int bclk_divs[] = {
2125 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2126 640, 880, 960, 1280, 1760, 1920
2127};
2128
2129static int wm8994_hw_params(struct snd_pcm_substream *substream,
2130 struct snd_pcm_hw_params *params,
2131 struct snd_soc_dai *dai)
2132{
2133 struct snd_soc_codec *codec = dai->codec;
c4431df0 2134 struct wm8994 *control = codec->control_data;
b2c812e2 2135 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2136 int aif1_reg;
b1e43d93 2137 int aif2_reg;
9e6e96a1
MB		 2138 int bclk_reg;
2139 int lrclk_reg;
2140 int rate_reg;
2141 int aif1 = 0;
b1e43d93 2142 int aif2 = 0;
9e6e96a1
MB		 2143 int bclk = 0;
2144 int lrclk = 0;
2145 int rate_val = 0;
2146 int id = dai->id - 1;
2147
2148 int i, cur_val, best_val, bclk_rate, best;
2149
2150 switch (dai->id) {
2151 case 1:
2152 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2153 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2154 bclk_reg = WM8994_AIF1_BCLK;
2155 rate_reg = WM8994_AIF1_RATE;
2156 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2157 wm8994->lrclk_shared[0]) {
9e6e96a1 2158 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2159 } else {
9e6e96a1 2160 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2161 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2162 }
9e6e96a1
MB		 2163 break;
2164 case 2:
2165 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2166 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2167 bclk_reg = WM8994_AIF2_BCLK;
2168 rate_reg = WM8994_AIF2_RATE;
2169 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2170 wm8994->lrclk_shared[1]) {
9e6e96a1 2171 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2172 } else {
9e6e96a1 2173 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2174 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2175 }
9e6e96a1 2176 break;
c4431df0
MB		 2177 case 3:
2178 switch (control->type) {
2179 case WM8958:
2180 aif1_reg = WM8958_AIF3_CONTROL_1;
2181 break;
2182 default:
2183 return 0;
2184 }
9e6e96a1
MB		 2185 default:
2186 return -EINVAL;
2187 }
2188
2189 bclk_rate = params_rate(params) * 2;
2190 switch (params_format(params)) {
2191 case SNDRV_PCM_FORMAT_S16_LE:
2192 bclk_rate *= 16;
2193 break;
2194 case SNDRV_PCM_FORMAT_S20_3LE:
2195 bclk_rate *= 20;
2196 aif1 |= 0x20;
2197 break;
2198 case SNDRV_PCM_FORMAT_S24_LE:
2199 bclk_rate *= 24;
2200 aif1 |= 0x40;
2201 break;
2202 case SNDRV_PCM_FORMAT_S32_LE:
2203 bclk_rate *= 32;
2204 aif1 |= 0x60;
2205 break;
2206 default:
2207 return -EINVAL;
2208 }
2209
2210 /* Try to find an appropriate sample rate; look for an exact match. */
2211 for (i = 0; i < ARRAY_SIZE(srs); i++)
2212 if (srs[i].rate == params_rate(params))
2213 break;
2214 if (i == ARRAY_SIZE(srs))
2215 return -EINVAL;
2216 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2217
2218 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2219 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2220 dai->id, wm8994->aifclk[id], bclk_rate);
2221
b1e43d93
MB		 2222 if (params_channels(params) == 1 &&
2223 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2224 aif2 |= WM8994_AIF1_MONO;
2225
9e6e96a1
MB		 2226 if (wm8994->aifclk[id] == 0) {
2227 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2228 return -EINVAL;
2229 }
2230
2231 /* AIFCLK/fs ratio; look for a close match in either direction */
2232 best = 0;
2233 best_val = abs((fs_ratios[0] * params_rate(params))
2234 - wm8994->aifclk[id]);
2235 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2236 cur_val = abs((fs_ratios[i] * params_rate(params))
2237 - wm8994->aifclk[id]);
2238 if (cur_val >= best_val)
2239 continue;
2240 best = i;
2241 best_val = cur_val;
2242 }
2243 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2244 dai->id, fs_ratios[best]);
2245 rate_val |= best;
2246
2247 /* We may not get quite the right frequency if using
2248 * approximate clocks so look for the closest match that is
2249 * higher than the target (we need to ensure that there enough
2250 * BCLKs to clock out the samples).
2251 */
2252 best = 0;
2253 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2254 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2255 if (cur_val < 0) /* BCLK table is sorted */
2256 break;
2257 best = i;
2258 }
07cd8ada 2259 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2260 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2261 bclk_divs[best], bclk_rate);
2262 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2263
2264 lrclk = bclk_rate / params_rate(params);
2265 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2266 lrclk, bclk_rate / lrclk);
2267
2268 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2269 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2270 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2271 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2272 lrclk);
2273 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2274 WM8994_AIF1CLK_RATE_MASK, rate_val);
2275
2276 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2277 switch (dai->id) {
2278 case 1:
2279 wm8994->dac_rates[0] = params_rate(params);
2280 wm8994_set_retune_mobile(codec, 0);
2281 wm8994_set_retune_mobile(codec, 1);
2282 break;
2283 case 2:
2284 wm8994->dac_rates[1] = params_rate(params);
2285 wm8994_set_retune_mobile(codec, 2);
2286 break;
2287 }
2288 }
2289
2290 return 0;
2291}
2292
c4431df0
MB		 2293static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2294 struct snd_pcm_hw_params *params,
2295 struct snd_soc_dai *dai)
2296{
2297 struct snd_soc_codec *codec = dai->codec;
2298 struct wm8994 *control = codec->control_data;
2299 int aif1_reg;
2300 int aif1 = 0;
2301
2302 switch (dai->id) {
2303 case 3:
2304 switch (control->type) {
2305 case WM8958:
2306 aif1_reg = WM8958_AIF3_CONTROL_1;
2307 break;
2308 default:
2309 return 0;
2310 }
2311 default:
2312 return 0;
2313 }
2314
2315 switch (params_format(params)) {
2316 case SNDRV_PCM_FORMAT_S16_LE:
2317 break;
2318 case SNDRV_PCM_FORMAT_S20_3LE:
2319 aif1 |= 0x20;
2320 break;
2321 case SNDRV_PCM_FORMAT_S24_LE:
2322 aif1 |= 0x40;
2323 break;
2324 case SNDRV_PCM_FORMAT_S32_LE:
2325 aif1 |= 0x60;
2326 break;
2327 default:
2328 return -EINVAL;
2329 }
2330
2331 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2332}
2333
9e6e96a1
MB		 2334static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2335{
2336 struct snd_soc_codec *codec = codec_dai->codec;
2337 int mute_reg;
2338 int reg;
2339
2340 switch (codec_dai->id) {
2341 case 1:
2342 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2343 break;
2344 case 2:
2345 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2346 break;
2347 default:
2348 return -EINVAL;
2349 }
2350
2351 if (mute)
2352 reg = WM8994_AIF1DAC1_MUTE;
2353 else
2354 reg = 0;
2355
2356 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2357
2358 return 0;
2359}
2360
778a76e2
MB		 2361static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2362{
2363 struct snd_soc_codec *codec = codec_dai->codec;
2364 int reg, val, mask;
2365
2366 switch (codec_dai->id) {
2367 case 1:
2368 reg = WM8994_AIF1_MASTER_SLAVE;
2369 mask = WM8994_AIF1_TRI;
2370 break;
2371 case 2:
2372 reg = WM8994_AIF2_MASTER_SLAVE;
2373 mask = WM8994_AIF2_TRI;
2374 break;
2375 case 3:
2376 reg = WM8994_POWER_MANAGEMENT_6;
2377 mask = WM8994_AIF3_TRI;
2378 break;
2379 default:
2380 return -EINVAL;
2381 }
2382
2383 if (tristate)
2384 val = mask;
2385 else
2386 val = 0;
2387
2388 return snd_soc_update_bits(codec, reg, mask, reg);
2389}
2390
9e6e96a1
MB		 2391#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2392
2393#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2394 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2395
2396static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2397 .set_sysclk = wm8994_set_dai_sysclk,
2398 .set_fmt = wm8994_set_dai_fmt,
2399 .hw_params = wm8994_hw_params,
2400 .digital_mute = wm8994_aif_mute,
2401 .set_pll = wm8994_set_fll,
778a76e2 2402 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2403};
2404
2405static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2406 .set_sysclk = wm8994_set_dai_sysclk,
2407 .set_fmt = wm8994_set_dai_fmt,
2408 .hw_params = wm8994_hw_params,
2409 .digital_mute = wm8994_aif_mute,
2410 .set_pll = wm8994_set_fll,
778a76e2
MB		 2411 .set_tristate = wm8994_set_tristate,
2412};
2413
2414static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2415 .hw_params = wm8994_aif3_hw_params,
778a76e2 2416 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2417};
2418
f0fba2ad 2419static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2420 {
f0fba2ad 2421 .name = "wm8994-aif1",
8c7f78b3 2422 .id = 1,
9e6e96a1
MB		 2423 .playback = {
2424 .stream_name = "AIF1 Playback",
b1e43d93 2425 .channels_min = 1,
9e6e96a1
MB		 2426 .channels_max = 2,
2427 .rates = WM8994_RATES,
2428 .formats = WM8994_FORMATS,
2429 },
2430 .capture = {
2431 .stream_name = "AIF1 Capture",
b1e43d93 2432 .channels_min = 1,
9e6e96a1
MB		 2433 .channels_max = 2,
2434 .rates = WM8994_RATES,
2435 .formats = WM8994_FORMATS,
2436 },
2437 .ops = &wm8994_aif1_dai_ops,
2438 },
2439 {
f0fba2ad 2440 .name = "wm8994-aif2",
8c7f78b3 2441 .id = 2,
9e6e96a1
MB		 2442 .playback = {
2443 .stream_name = "AIF2 Playback",
b1e43d93 2444 .channels_min = 1,
9e6e96a1
MB		 2445 .channels_max = 2,
2446 .rates = WM8994_RATES,
2447 .formats = WM8994_FORMATS,
2448 },
2449 .capture = {
2450 .stream_name = "AIF2 Capture",
b1e43d93 2451 .channels_min = 1,
9e6e96a1
MB		 2452 .channels_max = 2,
2453 .rates = WM8994_RATES,
2454 .formats = WM8994_FORMATS,
2455 },
2456 .ops = &wm8994_aif2_dai_ops,
2457 },
2458 {
f0fba2ad 2459 .name = "wm8994-aif3",
8c7f78b3 2460 .id = 3,
9e6e96a1
MB		 2461 .playback = {
2462 .stream_name = "AIF3 Playback",
b1e43d93 2463 .channels_min = 1,
9e6e96a1
MB		 2464 .channels_max = 2,
2465 .rates = WM8994_RATES,
2466 .formats = WM8994_FORMATS,
2467 },
a8462bde 2468 .capture = {
9e6e96a1 2469 .stream_name = "AIF3 Capture",
b1e43d93 2470 .channels_min = 1,
9e6e96a1
MB		 2471 .channels_max = 2,
2472 .rates = WM8994_RATES,
2473 .formats = WM8994_FORMATS,
2474 },
778a76e2 2475 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2476 }
2477};
9e6e96a1
MB		 2478
2479#ifdef CONFIG_PM
f0fba2ad 2480static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2481{
b2c812e2 2482 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2483 int i, ret;
2484
2485 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2486 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2487 sizeof(struct fll_config));
f0fba2ad 2488 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2489 if (ret < 0)
2490 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2491 i + 1, ret);
2492 }
2493
2494 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2495
2496 return 0;
2497}
2498
f0fba2ad 2499static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2500{
b2c812e2 2501 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2502 int i, ret;
2503
2504 /* Restore the registers */
ca9aef50
MB		 2505 ret = snd_soc_cache_sync(codec);
2506 if (ret != 0)
2507 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2508
2509 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2510
2511 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2512 if (!wm8994->fll_suspend[i].out)
2513 continue;
2514
f0fba2ad 2515 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2516 wm8994->fll_suspend[i].src,
2517 wm8994->fll_suspend[i].in,
2518 wm8994->fll_suspend[i].out);
2519 if (ret < 0)
2520 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2521 i + 1, ret);
2522 }
2523
2524 return 0;
2525}
2526#else
2527#define wm8994_suspend NULL
2528#define wm8994_resume NULL
2529#endif
2530
2531static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2532{
f0fba2ad 2533 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2534 struct wm8994_pdata *pdata = wm8994->pdata;
2535 struct snd_kcontrol_new controls[] = {
2536 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2537 wm8994->retune_mobile_enum,
2538 wm8994_get_retune_mobile_enum,
2539 wm8994_put_retune_mobile_enum),
2540 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2541 wm8994->retune_mobile_enum,
2542 wm8994_get_retune_mobile_enum,
2543 wm8994_put_retune_mobile_enum),
2544 SOC_ENUM_EXT("AIF2 EQ Mode",
2545 wm8994->retune_mobile_enum,
2546 wm8994_get_retune_mobile_enum,
2547 wm8994_put_retune_mobile_enum),
2548 };
2549 int ret, i, j;
2550 const char **t;
2551
2552 /* We need an array of texts for the enum API but the number
2553 * of texts is likely to be less than the number of
2554 * configurations due to the sample rate dependency of the
2555 * configurations. */
2556 wm8994->num_retune_mobile_texts = 0;
2557 wm8994->retune_mobile_texts = NULL;
2558 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2559 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2560 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2561 wm8994->retune_mobile_texts[j]) == 0)
2562 break;
2563 }
2564
2565 if (j != wm8994->num_retune_mobile_texts)
2566 continue;
2567
2568 /* Expand the array... */
2569 t = krealloc(wm8994->retune_mobile_texts,
2570 sizeof(char *) *
2571 (wm8994->num_retune_mobile_texts + 1),
2572 GFP_KERNEL);
2573 if (t == NULL)
2574 continue;
2575
2576 /* ...store the new entry... */
2577 t[wm8994->num_retune_mobile_texts] =
2578 pdata->retune_mobile_cfgs[i].name;
2579
2580 /* ...and remember the new version. */
2581 wm8994->num_retune_mobile_texts++;
2582 wm8994->retune_mobile_texts = t;
2583 }
2584
2585 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2586 wm8994->num_retune_mobile_texts);
2587
2588 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2589 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2590
f0fba2ad 2591 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2592 ARRAY_SIZE(controls));
2593 if (ret != 0)
f0fba2ad 2594 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2595 "Failed to add ReTune Mobile controls: %d\n", ret);
2596}
2597
2598static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2599{
f0fba2ad 2600 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2601 struct wm8994_pdata *pdata = wm8994->pdata;
2602 int ret, i;
2603
2604 if (!pdata)
2605 return;
2606
2607 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2608 pdata->lineout2_diff,
2609 pdata->lineout1fb,
2610 pdata->lineout2fb,
2611 pdata->jd_scthr,
2612 pdata->jd_thr,
2613 pdata->micbias1_lvl,
2614 pdata->micbias2_lvl);
2615
2616 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2617
2618 if (pdata->num_drc_cfgs) {
2619 struct snd_kcontrol_new controls[] = {
2620 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2621 wm8994_get_drc_enum, wm8994_put_drc_enum),
2622 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2623 wm8994_get_drc_enum, wm8994_put_drc_enum),
2624 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2625 wm8994_get_drc_enum, wm8994_put_drc_enum),
2626 };
2627
2628 /* We need an array of texts for the enum API */
2629 wm8994->drc_texts = kmalloc(sizeof(char *)
2630 * pdata->num_drc_cfgs, GFP_KERNEL);
2631 if (!wm8994->drc_texts) {
f0fba2ad 2632 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2633 "Failed to allocate %d DRC config texts\n",
2634 pdata->num_drc_cfgs);
2635 return;
2636 }
2637
2638 for (i = 0; i < pdata->num_drc_cfgs; i++)
2639 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2640
2641 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2642 wm8994->drc_enum.texts = wm8994->drc_texts;
2643
f0fba2ad 2644 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2645 ARRAY_SIZE(controls));
2646 if (ret != 0)
f0fba2ad 2647 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2648 "Failed to add DRC mode controls: %d\n", ret);
2649
2650 for (i = 0; i < WM8994_NUM_DRC; i++)
2651 wm8994_set_drc(codec, i);
2652 }
2653
2654 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2655 pdata->num_retune_mobile_cfgs);
2656
131d8106
MB		 2657 if (pdata->num_mbc_cfgs) {
2658 struct snd_kcontrol_new control[] = {
2659 SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2660 wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2661 };
2662
2663 /* We need an array of texts for the enum API */
2664 wm8994->mbc_texts = kmalloc(sizeof(char *)
2665 * pdata->num_mbc_cfgs, GFP_KERNEL);
2666 if (!wm8994->mbc_texts) {
2667 dev_err(wm8994->codec->dev,
2668 "Failed to allocate %d MBC config texts\n",
2669 pdata->num_mbc_cfgs);
2670 return;
2671 }
2672
2673 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2674 wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2675
2676 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2677 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2678
2679 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2680 if (ret != 0)
2681 dev_err(wm8994->codec->dev,
2682 "Failed to add MBC mode controls: %d\n", ret);
2683 }
2684
9e6e96a1
MB		 2685 if (pdata->num_retune_mobile_cfgs)
2686 wm8994_handle_retune_mobile_pdata(wm8994);
2687 else
f0fba2ad 2688 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2689 ARRAY_SIZE(wm8994_eq_controls));
2690}
2691
88766984
MB		 2692/**
2693 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2694 *
2695 * @codec: WM8994 codec
2696 * @jack: jack to report detection events on
2697 * @micbias: microphone bias to detect on
2698 * @det: value to report for presence detection
2699 * @shrt: value to report for short detection
2700 *
2701 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2702 * being used to bring out signals to the processor then only platform
5ab230a7 2703 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2704 * be configured using snd_soc_jack_add_gpios() instead.
2705 *
2706 * Configuration of detection levels is available via the micbias1_lvl
2707 * and micbias2_lvl platform data members.
2708 */
2709int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2710 int micbias, int det, int shrt)
2711{
b2c812e2 2712 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2713 struct wm8994_micdet *micdet;
3a423157 2714 struct wm8994 *control = codec->control_data;
88766984
MB		 2715 int reg;
2716
3a423157
MB		 2717 if (control->type != WM8994)
2718 return -EINVAL;
2719
88766984
MB		 2720 switch (micbias) {
2721 case 1:
2722 micdet = &wm8994->micdet[0];
2723 break;
2724 case 2:
2725 micdet = &wm8994->micdet[1];
2726 break;
2727 default:
2728 return -EINVAL;
2729 }
2730
2731 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2732 micbias, det, shrt);
2733
2734 /* Store the configuration */
2735 micdet->jack = jack;
2736 micdet->det = det;
2737 micdet->shrt = shrt;
2738
2739 /* If either of the jacks is set up then enable detection */
2740 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2741 reg = WM8994_MICD_ENA;
2742 else
2743 reg = 0;
2744
2745 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2746
2747 return 0;
2748}
2749EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2750
2751static irqreturn_t wm8994_mic_irq(int irq, void *data)
2752{
2753 struct wm8994_priv *priv = data;
f0fba2ad 2754 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2755 int reg;
2756 int report;
2757
2758 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2759 if (reg < 0) {
2760 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2761 reg);
2762 return IRQ_HANDLED;
2763 }
2764
2765 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2766
2767 report = 0;
2768 if (reg & WM8994_MIC1_DET_STS)
2769 report |= priv->micdet[0].det;
2770 if (reg & WM8994_MIC1_SHRT_STS)
2771 report |= priv->micdet[0].shrt;
2772 snd_soc_jack_report(priv->micdet[0].jack, report,
2773 priv->micdet[0].det | priv->micdet[0].shrt);
2774
2775 report = 0;
2776 if (reg & WM8994_MIC2_DET_STS)
2777 report |= priv->micdet[1].det;
2778 if (reg & WM8994_MIC2_SHRT_STS)
2779 report |= priv->micdet[1].shrt;
2780 snd_soc_jack_report(priv->micdet[1].jack, report,
2781 priv->micdet[1].det | priv->micdet[1].shrt);
2782
2783 return IRQ_HANDLED;
2784}
2785
821edd2f
MB		 2786/* Default microphone detection handler for WM8958 - the user can
2787 * override this if they wish.
2788 */
2789static void wm8958_default_micdet(u16 status, void *data)
2790{
2791 struct snd_soc_codec *codec = data;
2792 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2793 int report = 0;
2794
2795 /* If nothing present then clear our statuses */
2796 if (!(status & WM8958_MICD_STS)) {
2797 wm8994->jack_is_video = false;
2798 wm8994->jack_is_mic = false;
2799 goto done;
2800 }
2801
2802 /* Assume anything over 475 ohms is a microphone and remember
2803 * that we've seen one (since buttons override it) */
2804 if (status & 0x600)
2805 wm8994->jack_is_mic = true;
2806 if (wm8994->jack_is_mic)
2807 report |= SND_JACK_MICROPHONE;
2808
2809 /* Video has an impedence of approximately 75 ohms; assume
2810 * this isn't used as a button and remember it since buttons
2811 * override it. */
2812 if (status & 0x40)
2813 wm8994->jack_is_video = true;
2814 if (wm8994->jack_is_video)
2815 report |= SND_JACK_VIDEOOUT;
2816
2817 /* Everything else is buttons; just assign slots */
2818 if (status & 0x4)
2819 report |= SND_JACK_BTN_0;
2820 if (status & 0x8)
2821 report |= SND_JACK_BTN_1;
2822 if (status & 0x10)
2823 report |= SND_JACK_BTN_2;
2824 if (status & 0x20)
2825 report |= SND_JACK_BTN_3;
2826 if (status & 0x80)
2827 report |= SND_JACK_BTN_4;
2828 if (status & 0x100)
2829 report |= SND_JACK_BTN_5;
2830
2831done:
2832 snd_soc_jack_report(wm8994->micdet[0].jack,
2833 SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2834 SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2835 SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2836 report);
2837}
2838
2839/**
2840 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2841 *
2842 * @codec: WM8958 codec
2843 * @jack: jack to report detection events on
2844 *
2845 * Enable microphone detection functionality for the WM8958. By
2846 * default simple detection which supports the detection of up to 6
2847 * buttons plus video and microphone functionality is supported.
2848 *
2849 * The WM8958 has an advanced jack detection facility which is able to
2850 * support complex accessory detection, especially when used in
2851 * conjunction with external circuitry. In order to provide maximum
2852 * flexiblity a callback is provided which allows a completely custom
2853 * detection algorithm.
2854 */
2855int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2856 wm8958_micdet_cb cb, void *cb_data)
2857{
2858 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2859 struct wm8994 *control = codec->control_data;
2860
2861 if (control->type != WM8958)
2862 return -EINVAL;
2863
2864 if (jack) {
2865 if (!cb) {
2866 dev_dbg(codec->dev, "Using default micdet callback\n");
2867 cb = wm8958_default_micdet;
2868 cb_data = codec;
2869 }
2870
2871 wm8994->micdet[0].jack = jack;
2872 wm8994->jack_cb = cb;
2873 wm8994->jack_cb_data = cb_data;
2874
2875 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2876 WM8958_MICD_ENA, WM8958_MICD_ENA);
2877 } else {
2878 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2879 WM8958_MICD_ENA, 0);
2880 }
2881
2882 return 0;
2883}
2884EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2885
2886static irqreturn_t wm8958_mic_irq(int irq, void *data)
2887{
2888 struct wm8994_priv *wm8994 = data;
2889 struct snd_soc_codec *codec = wm8994->codec;
2890 int reg;
2891
2892 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2893 if (reg < 0) {
2894 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2895 reg);
2896 return IRQ_NONE;
2897 }
2898
2899 if (!(reg & WM8958_MICD_VALID)) {
2900 dev_dbg(codec->dev, "Mic detect data not valid\n");
2901 goto out;
2902 }
2903
2904 if (wm8994->jack_cb)
2905 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2906 else
2907 dev_warn(codec->dev, "Accessory detection with no callback\n");
2908
2909out:
2910 return IRQ_HANDLED;
2911}
2912
f0fba2ad 2913static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2914{
3a423157 2915 struct wm8994 *control;
9e6e96a1 2916 struct wm8994_priv *wm8994;
ce6120cc 2917 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2918 int ret, i;
9e6e96a1 2919
f0fba2ad 2920 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2921 control = codec->control_data;
9e6e96a1
MB		 2922
2923 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2924 if (wm8994 == NULL)
9e6e96a1 2925 return -ENOMEM;
b2c812e2 2926 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 2927
2928 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2929 wm8994->codec = codec;
9e6e96a1 2930
39fb51a1
MB		 2931 pm_runtime_enable(codec->dev);
2932 pm_runtime_resume(codec->dev);
2933
ca9aef50
MB		 2934 /* Read our current status back from the chip - we don't want to
2935 * reset as this may interfere with the GPIO or LDO operation. */
2936 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2937 if (!wm8994_readable(i) || wm8994_volatile(i))
2938 continue;
9e6e96a1 2939
ca9aef50
MB		 2940 ret = wm8994_reg_read(codec->control_data, i);
2941 if (ret <= 0)
2942 continue;
2943
2944 ret = snd_soc_cache_write(codec, i, ret);
2945 if (ret != 0) {
2946 dev_err(codec->dev,
2947 "Failed to initialise cache for 0x%x: %d\n",
2948 i, ret);
2949 goto err;
2950 }
2951 }
9e6e96a1
MB		 2952
2953 /* Set revision-specific configuration */
b6b05691 2954 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2955 switch (control->type) {
2956 case WM8994:
2957 switch (wm8994->revision) {
2958 case 2:
2959 case 3:
2960 wm8994->hubs.dcs_codes = -5;
2961 wm8994->hubs.hp_startup_mode = 1;
2962 wm8994->hubs.dcs_readback_mode = 1;
2963 break;
2964 default:
2965 wm8994->hubs.dcs_readback_mode = 1;
2966 break;
2967 }
2968
2969 case WM8958:
8437f700 2970 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2971 break;
3a423157 2972
9e6e96a1
MB		 2973 default:
2974 break;
2975 }
9e6e96a1 2976
3a423157
MB		 2977 switch (control->type) {
2978 case WM8994:
2979 ret = wm8994_request_irq(codec->control_data,
2980 WM8994_IRQ_MIC1_DET,
2981 wm8994_mic_irq, "Mic 1 detect",
2982 wm8994);
2983 if (ret != 0)
2984 dev_warn(codec->dev,
2985 "Failed to request Mic1 detect IRQ: %d\n",
2986 ret);
2987
2988 ret = wm8994_request_irq(codec->control_data,
2989 WM8994_IRQ_MIC1_SHRT,
2990 wm8994_mic_irq, "Mic 1 short",
2991 wm8994);
2992 if (ret != 0)
2993 dev_warn(codec->dev,
2994 "Failed to request Mic1 short IRQ: %d\n",
2995 ret);
2996
2997 ret = wm8994_request_irq(codec->control_data,
2998 WM8994_IRQ_MIC2_DET,
2999 wm8994_mic_irq, "Mic 2 detect",
3000 wm8994);
3001 if (ret != 0)
3002 dev_warn(codec->dev,
3003 "Failed to request Mic2 detect IRQ: %d\n",
3004 ret);
3005
3006 ret = wm8994_request_irq(codec->control_data,
3007 WM8994_IRQ_MIC2_SHRT,
3008 wm8994_mic_irq, "Mic 2 short",
3009 wm8994);
3010 if (ret != 0)
3011 dev_warn(codec->dev,
3012 "Failed to request Mic2 short IRQ: %d\n",
3013 ret);
3014 break;
821edd2f
MB		 3015
3016 case WM8958:
3017 ret = wm8994_request_irq(codec->control_data,
3018 WM8994_IRQ_MIC1_DET,
3019 wm8958_mic_irq, "Mic detect",
3020 wm8994);
3021 if (ret != 0)
3022 dev_warn(codec->dev,
3023 "Failed to request Mic detect IRQ: %d\n",
3024 ret);
3025 break;
3a423157 3026 }
88766984 3027
9e6e96a1
MB		 3028 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3029 * configured on init - if a system wants to do this dynamically
3030 * at runtime we can deal with that then.
3031 */
3032 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3033 if (ret < 0) {
3034 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3035 goto err_irq;
9e6e96a1
MB		 3036 }
3037 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3038 wm8994->lrclk_shared[0] = 1;
3039 wm8994_dai[0].symmetric_rates = 1;
3040 } else {
3041 wm8994->lrclk_shared[0] = 0;
3042 }
3043
3044 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3045 if (ret < 0) {
3046 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3047 goto err_irq;
9e6e96a1
MB		 3048 }
3049 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3050 wm8994->lrclk_shared[1] = 1;
3051 wm8994_dai[1].symmetric_rates = 1;
3052 } else {
3053 wm8994->lrclk_shared[1] = 0;
3054 }
3055
9e6e96a1
MB		 3056 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3057
9e6e96a1
MB		 3058 /* Latch volume updates (right only; we always do left then right). */
3059 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3060 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3061 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3062 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3063 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3064 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3065 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3066 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3067 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3068 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3069 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3070 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3071 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3072 WM8994_DAC1_VU, WM8994_DAC1_VU);
3073 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3074 WM8994_DAC2_VU, WM8994_DAC2_VU);
3075
3076 /* Set the low bit of the 3D stereo depth so TLV matches */
3077 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3078 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3079 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3080 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3081 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3082 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3083 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3084 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3085 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3086
d1ce6b20
MB		 3087 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3088 * behaviour on idle TDM clock cycles. */
3089 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3090 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3091
9e6e96a1
MB		 3092 wm8994_update_class_w(codec);
3093
f0fba2ad 3094 wm8994_handle_pdata(wm8994);
9e6e96a1 3095
f0fba2ad
LG		 3096 wm_hubs_add_analogue_controls(codec);
3097 snd_soc_add_controls(codec, wm8994_snd_controls,
3098 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3099 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3100 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3101
3102 switch (control->type) {
3103 case WM8994:
3104 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3105 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3106 break;
3107 case WM8958:
3108 snd_soc_add_controls(codec, wm8958_snd_controls,
3109 ARRAY_SIZE(wm8958_snd_controls));
3110 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3111 ARRAY_SIZE(wm8958_dapm_widgets));
3112 break;
3113 }
3114
3115
f0fba2ad 3116 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3117 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3118
c4431df0
MB		 3119 switch (control->type) {
3120 case WM8994:
3121 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3122 ARRAY_SIZE(wm8994_intercon));
3123 break;
3124 case WM8958:
3125 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3126 ARRAY_SIZE(wm8958_intercon));
3127 break;
3128 }
3129
9e6e96a1
MB		 3130 return 0;
3131
88766984
MB		 3132err_irq:
3133 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3134 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3135 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3136 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
9e6e96a1
MB		 3137err:
3138 kfree(wm8994);
3139 return ret;
3140}
3141
f0fba2ad 3142static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3143{
f0fba2ad 3144 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3145 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 3146
3147 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3148
39fb51a1
MB		 3149 pm_runtime_disable(codec->dev);
3150
3a423157
MB		 3151 switch (control->type) {
3152 case WM8994:
3153 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3154 wm8994);
3155 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3156 wm8994);
3157 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3158 wm8994);
3159 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3160 wm8994);
3161 break;
821edd2f
MB		 3162
3163 case WM8958:
3164 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3165 wm8994);
3166 break;
3a423157 3167 }
24fb2b11
AL		 3168 kfree(wm8994->retune_mobile_texts);
3169 kfree(wm8994->drc_texts);
9e6e96a1 3170 kfree(wm8994);
9e6e96a1
MB		 3171
3172 return 0;
3173}
3174
f0fba2ad
LG		 3175static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3176 .probe = wm8994_codec_probe,
3177 .remove = wm8994_codec_remove,
3178 .suspend = wm8994_suspend,
3179 .resume = wm8994_resume,
ca9aef50
MB		 3180 .read = wm8994_read,
3181 .write = wm8994_write,
eba19fdd
MB		 3182 .readable_register = wm8994_readable,
3183 .volatile_register = wm8994_volatile,
f0fba2ad 3184 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3185
3186 .reg_cache_size = WM8994_CACHE_SIZE,
3187 .reg_cache_default = wm8994_reg_defaults,
3188 .reg_word_size = 2,
2e19b0c8 3189 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3190};
3191
3192static int __devinit wm8994_probe(struct platform_device *pdev)
3193{
3194 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3195 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3196}
3197
3198static int __devexit wm8994_remove(struct platform_device *pdev)
3199{
3200 snd_soc_unregister_codec(&pdev->dev);
3201 return 0;
3202}
3203
9e6e96a1
MB		 3204static struct platform_driver wm8994_codec_driver = {
3205 .driver = {
3206 .name = "wm8994-codec",
3207 .owner = THIS_MODULE,
3208 },
f0fba2ad
LG		 3209 .probe = wm8994_probe,
3210 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3211};
3212
3213static __init int wm8994_init(void)
3214{
3215 return platform_driver_register(&wm8994_codec_driver);
3216}
3217module_init(wm8994_init);
3218
3219static __exit void wm8994_exit(void)
3220{
3221 platform_driver_unregister(&wm8994_codec_driver);
3222}
3223module_exit(wm8994_exit);
3224
3225
3226MODULE_DESCRIPTION("ASoC WM8994 driver");
3227MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3228MODULE_LICENSE("GPL");
3229MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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