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9e6e96a1 MB |
1 | /* |
2 | * wm8994.c -- WM8994 ALSA SoC Audio driver | |
3 | * | |
656baaeb | 4 | * Copyright 2009-12 Wolfson Microelectronics plc |
9e6e96a1 MB |
5 | * |
6 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/pm.h> | |
19 | #include <linux/i2c.h> | |
20 | #include <linux/platform_device.h> | |
39fb51a1 | 21 | #include <linux/pm_runtime.h> |
9e6e96a1 | 22 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 23 | #include <linux/slab.h> |
9e6e96a1 | 24 | #include <sound/core.h> |
821edd2f | 25 | #include <sound/jack.h> |
9e6e96a1 MB |
26 | #include <sound/pcm.h> |
27 | #include <sound/pcm_params.h> | |
28 | #include <sound/soc.h> | |
9e6e96a1 MB |
29 | #include <sound/initval.h> |
30 | #include <sound/tlv.h> | |
2bbb5d66 | 31 | #include <trace/events/asoc.h> |
9e6e96a1 MB |
32 | |
33 | #include <linux/mfd/wm8994/core.h> | |
34 | #include <linux/mfd/wm8994/registers.h> | |
35 | #include <linux/mfd/wm8994/pdata.h> | |
36 | #include <linux/mfd/wm8994/gpio.h> | |
37 | ||
38 | #include "wm8994.h" | |
39 | #include "wm_hubs.h" | |
40 | ||
af6b6fe4 MB |
41 | #define WM1811_JACKDET_MODE_NONE 0x0000 |
42 | #define WM1811_JACKDET_MODE_JACK 0x0100 | |
43 | #define WM1811_JACKDET_MODE_MIC 0x0080 | |
44 | #define WM1811_JACKDET_MODE_AUDIO 0x0180 | |
45 | ||
9e6e96a1 MB |
46 | #define WM8994_NUM_DRC 3 |
47 | #define WM8994_NUM_EQ 3 | |
48 | ||
bfd37bb5 MB |
49 | static struct { |
50 | unsigned int reg; | |
51 | unsigned int mask; | |
52 | } wm8994_vu_bits[] = { | |
53 | { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, | |
54 | { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU }, | |
55 | { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, | |
56 | { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU }, | |
57 | { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU }, | |
58 | { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU }, | |
59 | { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, | |
60 | { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU }, | |
61 | { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU }, | |
62 | { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU }, | |
63 | ||
64 | { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU }, | |
65 | { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU }, | |
66 | { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU }, | |
67 | { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU }, | |
68 | { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU }, | |
69 | { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU }, | |
70 | { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU }, | |
71 | { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU }, | |
72 | { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU }, | |
73 | { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, | |
74 | { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU }, | |
75 | { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU }, | |
76 | { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU }, | |
77 | { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU }, | |
78 | { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU }, | |
79 | { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU }, | |
80 | }; | |
81 | ||
9e6e96a1 MB |
82 | static int wm8994_drc_base[] = { |
83 | WM8994_AIF1_DRC1_1, | |
84 | WM8994_AIF1_DRC2_1, | |
85 | WM8994_AIF2_DRC_1, | |
86 | }; | |
87 | ||
88 | static int wm8994_retune_mobile_base[] = { | |
89 | WM8994_AIF1_DAC1_EQ_GAINS_1, | |
90 | WM8994_AIF1_DAC2_EQ_GAINS_1, | |
91 | WM8994_AIF2_EQ_GAINS_1, | |
92 | }; | |
93 | ||
af6b6fe4 | 94 | static const struct wm8958_micd_rate micdet_rates[] = { |
b00adf76 MB |
95 | { 32768, true, 1, 4 }, |
96 | { 32768, false, 1, 1 }, | |
604533de MB |
97 | { 44100 * 256, true, 7, 10 }, |
98 | { 44100 * 256, false, 7, 10 }, | |
b00adf76 MB |
99 | }; |
100 | ||
af6b6fe4 MB |
101 | static const struct wm8958_micd_rate jackdet_rates[] = { |
102 | { 32768, true, 0, 1 }, | |
103 | { 32768, false, 0, 1 }, | |
e9d9a968 MB |
104 | { 44100 * 256, true, 10, 10 }, |
105 | { 44100 * 256, false, 7, 8 }, | |
af6b6fe4 MB |
106 | }; |
107 | ||
b00adf76 MB |
108 | static void wm8958_micd_set_rate(struct snd_soc_codec *codec) |
109 | { | |
110 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
d9dd4ada | 111 | struct wm8994 *control = wm8994->wm8994; |
b00adf76 MB |
112 | int best, i, sysclk, val; |
113 | bool idle; | |
af6b6fe4 MB |
114 | const struct wm8958_micd_rate *rates; |
115 | int num_rates; | |
b00adf76 | 116 | |
b00adf76 MB |
117 | idle = !wm8994->jack_mic; |
118 | ||
119 | sysclk = snd_soc_read(codec, WM8994_CLOCKING_1); | |
120 | if (sysclk & WM8994_SYSCLK_SRC) | |
121 | sysclk = wm8994->aifclk[1]; | |
122 | else | |
123 | sysclk = wm8994->aifclk[0]; | |
124 | ||
d9dd4ada MB |
125 | if (control->pdata.micd_rates) { |
126 | rates = control->pdata.micd_rates; | |
127 | num_rates = control->pdata.num_micd_rates; | |
cd1707a9 | 128 | } else if (wm8994->jackdet) { |
af6b6fe4 MB |
129 | rates = jackdet_rates; |
130 | num_rates = ARRAY_SIZE(jackdet_rates); | |
131 | } else { | |
132 | rates = micdet_rates; | |
133 | num_rates = ARRAY_SIZE(micdet_rates); | |
134 | } | |
135 | ||
b00adf76 | 136 | best = 0; |
af6b6fe4 MB |
137 | for (i = 0; i < num_rates; i++) { |
138 | if (rates[i].idle != idle) | |
b00adf76 | 139 | continue; |
af6b6fe4 MB |
140 | if (abs(rates[i].sysclk - sysclk) < |
141 | abs(rates[best].sysclk - sysclk)) | |
b00adf76 | 142 | best = i; |
af6b6fe4 | 143 | else if (rates[best].idle != idle) |
b00adf76 MB |
144 | best = i; |
145 | } | |
146 | ||
af6b6fe4 MB |
147 | val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT |
148 | | rates[best].rate << WM8958_MICD_RATE_SHIFT; | |
b00adf76 | 149 | |
3a334ada MB |
150 | dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n", |
151 | rates[best].start, rates[best].rate, sysclk, | |
152 | idle ? "idle" : "active"); | |
153 | ||
b00adf76 MB |
154 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, |
155 | WM8958_MICD_BIAS_STARTTIME_MASK | | |
156 | WM8958_MICD_RATE_MASK, val); | |
157 | } | |
158 | ||
9e6e96a1 MB |
159 | static int configure_aif_clock(struct snd_soc_codec *codec, int aif) |
160 | { | |
b2c812e2 | 161 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
162 | int rate; |
163 | int reg1 = 0; | |
164 | int offset; | |
165 | ||
166 | if (aif) | |
167 | offset = 4; | |
168 | else | |
169 | offset = 0; | |
170 | ||
171 | switch (wm8994->sysclk[aif]) { | |
172 | case WM8994_SYSCLK_MCLK1: | |
173 | rate = wm8994->mclk[0]; | |
174 | break; | |
175 | ||
176 | case WM8994_SYSCLK_MCLK2: | |
177 | reg1 |= 0x8; | |
178 | rate = wm8994->mclk[1]; | |
179 | break; | |
180 | ||
181 | case WM8994_SYSCLK_FLL1: | |
182 | reg1 |= 0x10; | |
183 | rate = wm8994->fll[0].out; | |
184 | break; | |
185 | ||
186 | case WM8994_SYSCLK_FLL2: | |
187 | reg1 |= 0x18; | |
188 | rate = wm8994->fll[1].out; | |
189 | break; | |
190 | ||
191 | default: | |
192 | return -EINVAL; | |
193 | } | |
194 | ||
195 | if (rate >= 13500000) { | |
196 | rate /= 2; | |
197 | reg1 |= WM8994_AIF1CLK_DIV; | |
198 | ||
199 | dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", | |
200 | aif + 1, rate); | |
201 | } | |
5e5e2bef | 202 | |
9e6e96a1 MB |
203 | wm8994->aifclk[aif] = rate; |
204 | ||
205 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset, | |
206 | WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV, | |
207 | reg1); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int configure_clock(struct snd_soc_codec *codec) | |
213 | { | |
b2c812e2 | 214 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
04f45c49 | 215 | int change, new; |
9e6e96a1 MB |
216 | |
217 | /* Bring up the AIF clocks first */ | |
218 | configure_aif_clock(codec, 0); | |
219 | configure_aif_clock(codec, 1); | |
220 | ||
221 | /* Then switch CLK_SYS over to the higher of them; a change | |
222 | * can only happen as a result of a clocking change which can | |
223 | * only be made outside of DAPM so we can safely redo the | |
224 | * clocking. | |
225 | */ | |
226 | ||
227 | /* If they're equal it doesn't matter which is used */ | |
b00adf76 MB |
228 | if (wm8994->aifclk[0] == wm8994->aifclk[1]) { |
229 | wm8958_micd_set_rate(codec); | |
9e6e96a1 | 230 | return 0; |
b00adf76 | 231 | } |
9e6e96a1 MB |
232 | |
233 | if (wm8994->aifclk[0] < wm8994->aifclk[1]) | |
234 | new = WM8994_SYSCLK_SRC; | |
235 | else | |
236 | new = 0; | |
237 | ||
04f45c49 AL |
238 | change = snd_soc_update_bits(codec, WM8994_CLOCKING_1, |
239 | WM8994_SYSCLK_SRC, new); | |
52ac7ab2 MB |
240 | if (change) |
241 | snd_soc_dapm_sync(&codec->dapm); | |
9e6e96a1 | 242 | |
b00adf76 MB |
243 | wm8958_micd_set_rate(codec); |
244 | ||
9e6e96a1 MB |
245 | return 0; |
246 | } | |
247 | ||
248 | static int check_clk_sys(struct snd_soc_dapm_widget *source, | |
249 | struct snd_soc_dapm_widget *sink) | |
250 | { | |
251 | int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1); | |
252 | const char *clk; | |
253 | ||
254 | /* Check what we're currently using for CLK_SYS */ | |
255 | if (reg & WM8994_SYSCLK_SRC) | |
256 | clk = "AIF2CLK"; | |
257 | else | |
258 | clk = "AIF1CLK"; | |
259 | ||
260 | return strcmp(source->name, clk) == 0; | |
261 | } | |
262 | ||
263 | static const char *sidetone_hpf_text[] = { | |
264 | "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz" | |
265 | }; | |
266 | ||
267 | static const struct soc_enum sidetone_hpf = | |
268 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text); | |
269 | ||
146fd574 UK |
270 | static const char *adc_hpf_text[] = { |
271 | "HiFi", "Voice 1", "Voice 2", "Voice 3" | |
272 | }; | |
273 | ||
274 | static const struct soc_enum aif1adc1_hpf = | |
275 | SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text); | |
276 | ||
277 | static const struct soc_enum aif1adc2_hpf = | |
278 | SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text); | |
279 | ||
280 | static const struct soc_enum aif2adc_hpf = | |
281 | SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text); | |
282 | ||
9e6e96a1 MB |
283 | static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0); |
284 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
285 | static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); | |
286 | static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0); | |
287 | static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); | |
1ddc07d0 | 288 | static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0); |
81204c84 | 289 | static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0); |
9e6e96a1 MB |
290 | |
291 | #define WM8994_DRC_SWITCH(xname, reg, shift) \ | |
292 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
293 | .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ | |
294 | .put = wm8994_put_drc_sw, \ | |
295 | .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) } | |
296 | ||
297 | static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol, | |
298 | struct snd_ctl_elem_value *ucontrol) | |
299 | { | |
300 | struct soc_mixer_control *mc = | |
301 | (struct soc_mixer_control *)kcontrol->private_value; | |
302 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
303 | int mask, ret; | |
304 | ||
305 | /* Can't enable both ADC and DAC paths simultaneously */ | |
306 | if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT) | |
307 | mask = WM8994_AIF1ADC1L_DRC_ENA_MASK | | |
308 | WM8994_AIF1ADC1R_DRC_ENA_MASK; | |
309 | else | |
310 | mask = WM8994_AIF1DAC1_DRC_ENA_MASK; | |
311 | ||
312 | ret = snd_soc_read(codec, mc->reg); | |
313 | if (ret < 0) | |
314 | return ret; | |
315 | if (ret & mask) | |
316 | return -EINVAL; | |
317 | ||
318 | return snd_soc_put_volsw(kcontrol, ucontrol); | |
319 | } | |
320 | ||
9e6e96a1 MB |
321 | static void wm8994_set_drc(struct snd_soc_codec *codec, int drc) |
322 | { | |
b2c812e2 | 323 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
d9dd4ada MB |
324 | struct wm8994 *control = wm8994->wm8994; |
325 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 MB |
326 | int base = wm8994_drc_base[drc]; |
327 | int cfg = wm8994->drc_cfg[drc]; | |
328 | int save, i; | |
329 | ||
330 | /* Save any enables; the configuration should clear them. */ | |
331 | save = snd_soc_read(codec, base); | |
332 | save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | | |
333 | WM8994_AIF1ADC1R_DRC_ENA; | |
334 | ||
335 | for (i = 0; i < WM8994_DRC_REGS; i++) | |
336 | snd_soc_update_bits(codec, base + i, 0xffff, | |
337 | pdata->drc_cfgs[cfg].regs[i]); | |
338 | ||
339 | snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA | | |
340 | WM8994_AIF1ADC1L_DRC_ENA | | |
341 | WM8994_AIF1ADC1R_DRC_ENA, save); | |
342 | } | |
343 | ||
344 | /* Icky as hell but saves code duplication */ | |
345 | static int wm8994_get_drc(const char *name) | |
346 | { | |
347 | if (strcmp(name, "AIF1DRC1 Mode") == 0) | |
348 | return 0; | |
349 | if (strcmp(name, "AIF1DRC2 Mode") == 0) | |
350 | return 1; | |
351 | if (strcmp(name, "AIF2DRC Mode") == 0) | |
352 | return 2; | |
353 | return -EINVAL; | |
354 | } | |
355 | ||
356 | static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol, | |
357 | struct snd_ctl_elem_value *ucontrol) | |
358 | { | |
359 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 360 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
d9dd4ada MB |
361 | struct wm8994 *control = wm8994->wm8994; |
362 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 MB |
363 | int drc = wm8994_get_drc(kcontrol->id.name); |
364 | int value = ucontrol->value.integer.value[0]; | |
365 | ||
366 | if (drc < 0) | |
367 | return drc; | |
368 | ||
369 | if (value >= pdata->num_drc_cfgs) | |
370 | return -EINVAL; | |
371 | ||
372 | wm8994->drc_cfg[drc] = value; | |
373 | ||
374 | wm8994_set_drc(codec, drc); | |
375 | ||
376 | return 0; | |
377 | } | |
378 | ||
379 | static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol, | |
380 | struct snd_ctl_elem_value *ucontrol) | |
381 | { | |
382 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
b2c812e2 | 383 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
384 | int drc = wm8994_get_drc(kcontrol->id.name); |
385 | ||
7d6898be VK |
386 | if (drc < 0) |
387 | return drc; | |
9e6e96a1 MB |
388 | ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc]; |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block) | |
394 | { | |
b2c812e2 | 395 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
d9dd4ada MB |
396 | struct wm8994 *control = wm8994->wm8994; |
397 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 MB |
398 | int base = wm8994_retune_mobile_base[block]; |
399 | int iface, best, best_val, save, i, cfg; | |
400 | ||
401 | if (!pdata || !wm8994->num_retune_mobile_texts) | |
402 | return; | |
403 | ||
404 | switch (block) { | |
405 | case 0: | |
406 | case 1: | |
407 | iface = 0; | |
408 | break; | |
409 | case 2: | |
410 | iface = 1; | |
411 | break; | |
412 | default: | |
413 | return; | |
414 | } | |
415 | ||
416 | /* Find the version of the currently selected configuration | |
417 | * with the nearest sample rate. */ | |
418 | cfg = wm8994->retune_mobile_cfg[block]; | |
419 | best = 0; | |
420 | best_val = INT_MAX; | |
421 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
422 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
423 | wm8994->retune_mobile_texts[cfg]) == 0 && | |
424 | abs(pdata->retune_mobile_cfgs[i].rate | |
425 | - wm8994->dac_rates[iface]) < best_val) { | |
426 | best = i; | |
427 | best_val = abs(pdata->retune_mobile_cfgs[i].rate | |
428 | - wm8994->dac_rates[iface]); | |
429 | } | |
430 | } | |
431 | ||
432 | dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n", | |
433 | block, | |
434 | pdata->retune_mobile_cfgs[best].name, | |
435 | pdata->retune_mobile_cfgs[best].rate, | |
436 | wm8994->dac_rates[iface]); | |
437 | ||
438 | /* The EQ will be disabled while reconfiguring it, remember the | |
c1a4ecd9 | 439 | * current configuration. |
9e6e96a1 MB |
440 | */ |
441 | save = snd_soc_read(codec, base); | |
442 | save &= WM8994_AIF1DAC1_EQ_ENA; | |
443 | ||
444 | for (i = 0; i < WM8994_EQ_REGS; i++) | |
445 | snd_soc_update_bits(codec, base + i, 0xffff, | |
446 | pdata->retune_mobile_cfgs[best].regs[i]); | |
447 | ||
448 | snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save); | |
449 | } | |
450 | ||
451 | /* Icky as hell but saves code duplication */ | |
452 | static int wm8994_get_retune_mobile_block(const char *name) | |
453 | { | |
454 | if (strcmp(name, "AIF1.1 EQ Mode") == 0) | |
455 | return 0; | |
456 | if (strcmp(name, "AIF1.2 EQ Mode") == 0) | |
457 | return 1; | |
458 | if (strcmp(name, "AIF2 EQ Mode") == 0) | |
459 | return 2; | |
460 | return -EINVAL; | |
461 | } | |
462 | ||
463 | static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
464 | struct snd_ctl_elem_value *ucontrol) | |
465 | { | |
466 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
f0fba2ad | 467 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
d9dd4ada MB |
468 | struct wm8994 *control = wm8994->wm8994; |
469 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 MB |
470 | int block = wm8994_get_retune_mobile_block(kcontrol->id.name); |
471 | int value = ucontrol->value.integer.value[0]; | |
472 | ||
473 | if (block < 0) | |
474 | return block; | |
475 | ||
476 | if (value >= pdata->num_retune_mobile_cfgs) | |
477 | return -EINVAL; | |
478 | ||
479 | wm8994->retune_mobile_cfg[block] = value; | |
480 | ||
481 | wm8994_set_retune_mobile(codec, block); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol, | |
487 | struct snd_ctl_elem_value *ucontrol) | |
488 | { | |
489 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
4a8d929d | 490 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
491 | int block = wm8994_get_retune_mobile_block(kcontrol->id.name); |
492 | ||
7d6898be VK |
493 | if (block < 0) |
494 | return block; | |
495 | ||
9e6e96a1 MB |
496 | ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block]; |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
96b101ef | 501 | static const char *aif_chan_src_text[] = { |
f554885f MB |
502 | "Left", "Right" |
503 | }; | |
504 | ||
96b101ef MB |
505 | static const struct soc_enum aif1adcl_src = |
506 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text); | |
507 | ||
508 | static const struct soc_enum aif1adcr_src = | |
509 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text); | |
510 | ||
511 | static const struct soc_enum aif2adcl_src = | |
512 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text); | |
513 | ||
514 | static const struct soc_enum aif2adcr_src = | |
515 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text); | |
516 | ||
f554885f | 517 | static const struct soc_enum aif1dacl_src = |
96b101ef | 518 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text); |
f554885f MB |
519 | |
520 | static const struct soc_enum aif1dacr_src = | |
96b101ef | 521 | SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text); |
f554885f MB |
522 | |
523 | static const struct soc_enum aif2dacl_src = | |
96b101ef | 524 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text); |
f554885f MB |
525 | |
526 | static const struct soc_enum aif2dacr_src = | |
96b101ef | 527 | SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text); |
f554885f | 528 | |
154b26aa MB |
529 | static const char *osr_text[] = { |
530 | "Low Power", "High Performance", | |
531 | }; | |
532 | ||
533 | static const struct soc_enum dac_osr = | |
534 | SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text); | |
535 | ||
536 | static const struct soc_enum adc_osr = | |
537 | SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text); | |
538 | ||
9e6e96a1 MB |
539 | static const struct snd_kcontrol_new wm8994_snd_controls[] = { |
540 | SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME, | |
541 | WM8994_AIF1_ADC1_RIGHT_VOLUME, | |
542 | 1, 119, 0, digital_tlv), | |
543 | SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME, | |
544 | WM8994_AIF1_ADC2_RIGHT_VOLUME, | |
545 | 1, 119, 0, digital_tlv), | |
546 | SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME, | |
547 | WM8994_AIF2_ADC_RIGHT_VOLUME, | |
548 | 1, 119, 0, digital_tlv), | |
549 | ||
96b101ef MB |
550 | SOC_ENUM("AIF1ADCL Source", aif1adcl_src), |
551 | SOC_ENUM("AIF1ADCR Source", aif1adcr_src), | |
49db7e7b MB |
552 | SOC_ENUM("AIF2ADCL Source", aif2adcl_src), |
553 | SOC_ENUM("AIF2ADCR Source", aif2adcr_src), | |
96b101ef | 554 | |
f554885f MB |
555 | SOC_ENUM("AIF1DACL Source", aif1dacl_src), |
556 | SOC_ENUM("AIF1DACR Source", aif1dacr_src), | |
49db7e7b MB |
557 | SOC_ENUM("AIF2DACL Source", aif2dacl_src), |
558 | SOC_ENUM("AIF2DACR Source", aif2dacr_src), | |
f554885f | 559 | |
9e6e96a1 MB |
560 | SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME, |
561 | WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
562 | SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME, | |
563 | WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
564 | SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME, | |
565 | WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
566 | ||
567 | SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv), | |
568 | SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv), | |
569 | ||
570 | SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0), | |
571 | SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0), | |
572 | SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0), | |
573 | ||
574 | WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2), | |
575 | WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1), | |
576 | WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0), | |
577 | ||
578 | WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2), | |
579 | WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1), | |
580 | WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0), | |
581 | ||
582 | WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2), | |
583 | WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1), | |
584 | WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0), | |
585 | ||
586 | SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, | |
587 | 5, 12, 0, st_tlv), | |
588 | SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES, | |
589 | 0, 12, 0, st_tlv), | |
590 | SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, | |
591 | 5, 12, 0, st_tlv), | |
592 | SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES, | |
593 | 0, 12, 0, st_tlv), | |
594 | SOC_ENUM("Sidetone HPF Mux", sidetone_hpf), | |
595 | SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0), | |
596 | ||
146fd574 UK |
597 | SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf), |
598 | SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0), | |
599 | ||
600 | SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf), | |
601 | SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0), | |
602 | ||
603 | SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf), | |
604 | SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0), | |
605 | ||
154b26aa MB |
606 | SOC_ENUM("ADC OSR", adc_osr), |
607 | SOC_ENUM("DAC OSR", dac_osr), | |
608 | ||
9e6e96a1 MB |
609 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME, |
610 | WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
611 | SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME, | |
612 | WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
613 | ||
614 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME, | |
615 | WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv), | |
616 | SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME, | |
617 | WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
618 | ||
619 | SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION, | |
620 | 6, 1, 1, wm_hubs_spkmix_tlv), | |
621 | SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION, | |
622 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
623 | ||
624 | SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION, | |
625 | 6, 1, 1, wm_hubs_spkmix_tlv), | |
626 | SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION, | |
627 | 2, 1, 1, wm_hubs_spkmix_tlv), | |
628 | ||
629 | SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2, | |
630 | 10, 15, 0, wm8994_3d_tlv), | |
458350b3 | 631 | SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2, |
9e6e96a1 MB |
632 | 8, 1, 0), |
633 | SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2, | |
634 | 10, 15, 0, wm8994_3d_tlv), | |
635 | SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2, | |
636 | 8, 1, 0), | |
458350b3 | 637 | SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2, |
9e6e96a1 | 638 | 10, 15, 0, wm8994_3d_tlv), |
458350b3 | 639 | SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2, |
9e6e96a1 MB |
640 | 8, 1, 0), |
641 | }; | |
642 | ||
643 | static const struct snd_kcontrol_new wm8994_eq_controls[] = { | |
644 | SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0, | |
645 | eq_tlv), | |
646 | SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0, | |
647 | eq_tlv), | |
648 | SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0, | |
649 | eq_tlv), | |
650 | SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0, | |
651 | eq_tlv), | |
652 | SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0, | |
653 | eq_tlv), | |
654 | ||
655 | SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0, | |
656 | eq_tlv), | |
657 | SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0, | |
658 | eq_tlv), | |
659 | SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0, | |
660 | eq_tlv), | |
661 | SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0, | |
662 | eq_tlv), | |
663 | SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0, | |
664 | eq_tlv), | |
665 | ||
666 | SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0, | |
667 | eq_tlv), | |
668 | SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0, | |
669 | eq_tlv), | |
670 | SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0, | |
671 | eq_tlv), | |
672 | SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0, | |
673 | eq_tlv), | |
674 | SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0, | |
675 | eq_tlv), | |
676 | }; | |
677 | ||
45a690f6 MB |
678 | static const struct snd_kcontrol_new wm8994_drc_controls[] = { |
679 | SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5, | |
680 | WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA | | |
681 | WM8994_AIF1ADC1R_DRC_ENA), | |
682 | SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5, | |
683 | WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA | | |
684 | WM8994_AIF1ADC2R_DRC_ENA), | |
685 | SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5, | |
686 | WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA | | |
687 | WM8994_AIF2ADCR_DRC_ENA), | |
688 | }; | |
689 | ||
1ddc07d0 MB |
690 | static const char *wm8958_ng_text[] = { |
691 | "30ms", "125ms", "250ms", "500ms", | |
692 | }; | |
693 | ||
694 | static const struct soc_enum wm8958_aif1dac1_ng_hold = | |
695 | SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE, | |
696 | WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text); | |
697 | ||
698 | static const struct soc_enum wm8958_aif1dac2_ng_hold = | |
699 | SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE, | |
700 | WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text); | |
701 | ||
702 | static const struct soc_enum wm8958_aif2dac_ng_hold = | |
703 | SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE, | |
704 | WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text); | |
705 | ||
c4431df0 MB |
706 | static const struct snd_kcontrol_new wm8958_snd_controls[] = { |
707 | SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv), | |
1ddc07d0 MB |
708 | |
709 | SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE, | |
710 | WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0), | |
711 | SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold), | |
712 | SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume", | |
713 | WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT, | |
714 | 7, 1, ng_tlv), | |
715 | ||
716 | SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE, | |
717 | WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0), | |
718 | SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold), | |
719 | SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume", | |
720 | WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT, | |
721 | 7, 1, ng_tlv), | |
722 | ||
723 | SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE, | |
724 | WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0), | |
725 | SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold), | |
726 | SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume", | |
727 | WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT, | |
728 | 7, 1, ng_tlv), | |
c4431df0 MB |
729 | }; |
730 | ||
81204c84 MB |
731 | static const struct snd_kcontrol_new wm1811_snd_controls[] = { |
732 | SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0, | |
733 | mixin_boost_tlv), | |
734 | SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0, | |
735 | mixin_boost_tlv), | |
736 | }; | |
737 | ||
af6b6fe4 MB |
738 | /* We run all mode setting through a function to enforce audio mode */ |
739 | static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode) | |
740 | { | |
741 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
742 | ||
78b76dbe | 743 | if (!wm8994->jackdet || !wm8994->micdet[0].jack) |
28e33269 MB |
744 | return; |
745 | ||
af6b6fe4 MB |
746 | if (wm8994->active_refcount) |
747 | mode = WM1811_JACKDET_MODE_AUDIO; | |
748 | ||
4752a887 | 749 | if (mode == wm8994->jackdet_mode) |
1defde2a MB |
750 | return; |
751 | ||
4752a887 | 752 | wm8994->jackdet_mode = mode; |
1defde2a | 753 | |
4752a887 MB |
754 | /* Always use audio mode to detect while the system is active */ |
755 | if (mode != WM1811_JACKDET_MODE_NONE) | |
756 | mode = WM1811_JACKDET_MODE_AUDIO; | |
1defde2a | 757 | |
4752a887 MB |
758 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, |
759 | WM1811_JACKDET_MODE_MASK, mode); | |
af6b6fe4 MB |
760 | } |
761 | ||
762 | static void active_reference(struct snd_soc_codec *codec) | |
763 | { | |
764 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
765 | ||
766 | mutex_lock(&wm8994->accdet_lock); | |
767 | ||
768 | wm8994->active_refcount++; | |
769 | ||
770 | dev_dbg(codec->dev, "Active refcount incremented, now %d\n", | |
771 | wm8994->active_refcount); | |
772 | ||
1defde2a MB |
773 | /* If we're using jack detection go into audio mode */ |
774 | wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO); | |
af6b6fe4 MB |
775 | |
776 | mutex_unlock(&wm8994->accdet_lock); | |
777 | } | |
778 | ||
779 | static void active_dereference(struct snd_soc_codec *codec) | |
780 | { | |
781 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
782 | u16 mode; | |
783 | ||
784 | mutex_lock(&wm8994->accdet_lock); | |
785 | ||
786 | wm8994->active_refcount--; | |
787 | ||
788 | dev_dbg(codec->dev, "Active refcount decremented, now %d\n", | |
789 | wm8994->active_refcount); | |
790 | ||
791 | if (wm8994->active_refcount == 0) { | |
792 | /* Go into appropriate detection only mode */ | |
1defde2a MB |
793 | if (wm8994->jack_mic || wm8994->mic_detecting) |
794 | mode = WM1811_JACKDET_MODE_MIC; | |
795 | else | |
796 | mode = WM1811_JACKDET_MODE_JACK; | |
797 | ||
798 | wm1811_jackdet_set_mode(codec, mode); | |
af6b6fe4 MB |
799 | } |
800 | ||
801 | mutex_unlock(&wm8994->accdet_lock); | |
802 | } | |
803 | ||
9e6e96a1 MB |
804 | static int clk_sys_event(struct snd_soc_dapm_widget *w, |
805 | struct snd_kcontrol *kcontrol, int event) | |
806 | { | |
807 | struct snd_soc_codec *codec = w->codec; | |
99af79df | 808 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
809 | |
810 | switch (event) { | |
811 | case SND_SOC_DAPM_PRE_PMU: | |
812 | return configure_clock(codec); | |
813 | ||
99af79df MB |
814 | case SND_SOC_DAPM_POST_PMU: |
815 | /* | |
816 | * JACKDET won't run until we start the clock and it | |
817 | * only reports deltas, make sure we notify the state | |
818 | * up the stack on startup. Use a *very* generous | |
819 | * timeout for paranoia, there's no urgency and we | |
820 | * don't want false reports. | |
821 | */ | |
822 | if (wm8994->jackdet && !wm8994->clk_has_run) { | |
823 | schedule_delayed_work(&wm8994->jackdet_bootstrap, | |
824 | msecs_to_jiffies(1000)); | |
825 | wm8994->clk_has_run = true; | |
826 | } | |
827 | break; | |
828 | ||
9e6e96a1 MB |
829 | case SND_SOC_DAPM_POST_PMD: |
830 | configure_clock(codec); | |
831 | break; | |
832 | } | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
4b7ed83a MB |
837 | static void vmid_reference(struct snd_soc_codec *codec) |
838 | { | |
839 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
840 | ||
db966f8a MB |
841 | pm_runtime_get_sync(codec->dev); |
842 | ||
4b7ed83a MB |
843 | wm8994->vmid_refcount++; |
844 | ||
845 | dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n", | |
846 | wm8994->vmid_refcount); | |
847 | ||
848 | if (wm8994->vmid_refcount == 1) { | |
cc6d5a8c | 849 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, |
cc6d5a8c | 850 | WM8994_LINEOUT1_DISCH | |
22f8d055 | 851 | WM8994_LINEOUT2_DISCH, 0); |
cc6d5a8c | 852 | |
f7085641 MB |
853 | wm_hubs_vmid_ena(codec); |
854 | ||
22f8d055 MB |
855 | switch (wm8994->vmid_mode) { |
856 | default: | |
cbd71f30 | 857 | WARN_ON(NULL == "Invalid VMID mode"); |
22f8d055 MB |
858 | case WM8994_VMID_NORMAL: |
859 | /* Startup bias, VMID ramp & buffer */ | |
860 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
861 | WM8994_BIAS_SRC | | |
862 | WM8994_VMID_DISCH | | |
863 | WM8994_STARTUP_BIAS_ENA | | |
864 | WM8994_VMID_BUF_ENA | | |
865 | WM8994_VMID_RAMP_MASK, | |
866 | WM8994_BIAS_SRC | | |
867 | WM8994_STARTUP_BIAS_ENA | | |
868 | WM8994_VMID_BUF_ENA | | |
a3a1d9d2 | 869 | (0x2 << WM8994_VMID_RAMP_SHIFT)); |
22f8d055 MB |
870 | |
871 | /* Main bias enable, VMID=2x40k */ | |
872 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
873 | WM8994_BIAS_ENA | | |
874 | WM8994_VMID_SEL_MASK, | |
875 | WM8994_BIAS_ENA | 0x2); | |
876 | ||
a3a1d9d2 | 877 | msleep(300); |
22f8d055 MB |
878 | |
879 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
880 | WM8994_VMID_RAMP_MASK | | |
881 | WM8994_BIAS_SRC, | |
882 | 0); | |
883 | break; | |
cc6d5a8c | 884 | |
22f8d055 MB |
885 | case WM8994_VMID_FORCE: |
886 | /* Startup bias, slow VMID ramp & buffer */ | |
887 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
888 | WM8994_BIAS_SRC | | |
889 | WM8994_VMID_DISCH | | |
890 | WM8994_STARTUP_BIAS_ENA | | |
891 | WM8994_VMID_BUF_ENA | | |
892 | WM8994_VMID_RAMP_MASK, | |
893 | WM8994_BIAS_SRC | | |
894 | WM8994_STARTUP_BIAS_ENA | | |
895 | WM8994_VMID_BUF_ENA | | |
896 | (0x2 << WM8994_VMID_RAMP_SHIFT)); | |
897 | ||
898 | /* Main bias enable, VMID=2x40k */ | |
899 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
900 | WM8994_BIAS_ENA | | |
901 | WM8994_VMID_SEL_MASK, | |
902 | WM8994_BIAS_ENA | 0x2); | |
903 | ||
904 | msleep(400); | |
905 | ||
906 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
907 | WM8994_VMID_RAMP_MASK | | |
908 | WM8994_BIAS_SRC, | |
909 | 0); | |
910 | break; | |
911 | } | |
4b7ed83a MB |
912 | } |
913 | } | |
914 | ||
915 | static void vmid_dereference(struct snd_soc_codec *codec) | |
916 | { | |
917 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
918 | ||
919 | wm8994->vmid_refcount--; | |
920 | ||
921 | dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n", | |
922 | wm8994->vmid_refcount); | |
923 | ||
924 | if (wm8994->vmid_refcount == 0) { | |
22f8d055 MB |
925 | if (wm8994->hubs.lineout1_se) |
926 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, | |
927 | WM8994_LINEOUT1N_ENA | | |
928 | WM8994_LINEOUT1P_ENA, | |
929 | WM8994_LINEOUT1N_ENA | | |
930 | WM8994_LINEOUT1P_ENA); | |
931 | ||
932 | if (wm8994->hubs.lineout2_se) | |
933 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, | |
934 | WM8994_LINEOUT2N_ENA | | |
935 | WM8994_LINEOUT2P_ENA, | |
936 | WM8994_LINEOUT2N_ENA | | |
937 | WM8994_LINEOUT2P_ENA); | |
938 | ||
939 | /* Start discharging VMID */ | |
4b7ed83a MB |
940 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, |
941 | WM8994_BIAS_SRC | | |
22f8d055 | 942 | WM8994_VMID_DISCH, |
4b7ed83a | 943 | WM8994_BIAS_SRC | |
22f8d055 | 944 | WM8994_VMID_DISCH); |
4b7ed83a | 945 | |
f95be9d6 MB |
946 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, |
947 | WM8994_VMID_SEL_MASK, 0); | |
4b7ed83a | 948 | |
f95be9d6 | 949 | msleep(400); |
e85b26ce | 950 | |
22f8d055 | 951 | /* Active discharge */ |
4b7ed83a MB |
952 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, |
953 | WM8994_LINEOUT1_DISCH | | |
954 | WM8994_LINEOUT2_DISCH, | |
955 | WM8994_LINEOUT1_DISCH | | |
956 | WM8994_LINEOUT2_DISCH); | |
957 | ||
22f8d055 MB |
958 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3, |
959 | WM8994_LINEOUT1N_ENA | | |
960 | WM8994_LINEOUT1P_ENA | | |
961 | WM8994_LINEOUT2N_ENA | | |
962 | WM8994_LINEOUT2P_ENA, 0); | |
963 | ||
4b7ed83a MB |
964 | /* Switch off startup biases */ |
965 | snd_soc_update_bits(codec, WM8994_ANTIPOP_2, | |
966 | WM8994_BIAS_SRC | | |
967 | WM8994_STARTUP_BIAS_ENA | | |
968 | WM8994_VMID_BUF_ENA | | |
969 | WM8994_VMID_RAMP_MASK, 0); | |
22f8d055 MB |
970 | |
971 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1, | |
f95be9d6 | 972 | WM8994_VMID_SEL_MASK, 0); |
4b7ed83a | 973 | } |
db966f8a MB |
974 | |
975 | pm_runtime_put(codec->dev); | |
4b7ed83a MB |
976 | } |
977 | ||
978 | static int vmid_event(struct snd_soc_dapm_widget *w, | |
979 | struct snd_kcontrol *kcontrol, int event) | |
980 | { | |
981 | struct snd_soc_codec *codec = w->codec; | |
982 | ||
983 | switch (event) { | |
984 | case SND_SOC_DAPM_PRE_PMU: | |
985 | vmid_reference(codec); | |
986 | break; | |
987 | ||
988 | case SND_SOC_DAPM_POST_PMD: | |
989 | vmid_dereference(codec); | |
990 | break; | |
991 | } | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
c340304d | 996 | static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec) |
9e6e96a1 | 997 | { |
9e6e96a1 MB |
998 | int source = 0; /* GCC flow analysis can't track enable */ |
999 | int reg, reg_r; | |
1000 | ||
c340304d | 1001 | /* We also need the same AIF source for L/R and only one path */ |
9e6e96a1 MB |
1002 | reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING); |
1003 | switch (reg) { | |
1004 | case WM8994_AIF2DACL_TO_DAC1L: | |
ee839a21 | 1005 | dev_vdbg(codec->dev, "Class W source AIF2DAC\n"); |
9e6e96a1 MB |
1006 | source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
1007 | break; | |
1008 | case WM8994_AIF1DAC2L_TO_DAC1L: | |
ee839a21 | 1009 | dev_vdbg(codec->dev, "Class W source AIF1DAC2\n"); |
9e6e96a1 MB |
1010 | source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
1011 | break; | |
1012 | case WM8994_AIF1DAC1L_TO_DAC1L: | |
ee839a21 | 1013 | dev_vdbg(codec->dev, "Class W source AIF1DAC1\n"); |
9e6e96a1 MB |
1014 | source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT; |
1015 | break; | |
1016 | default: | |
ee839a21 | 1017 | dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg); |
c340304d | 1018 | return false; |
9e6e96a1 MB |
1019 | } |
1020 | ||
1021 | reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING); | |
1022 | if (reg_r != reg) { | |
ee839a21 | 1023 | dev_vdbg(codec->dev, "Left and right DAC mixers different\n"); |
c340304d | 1024 | return false; |
9e6e96a1 MB |
1025 | } |
1026 | ||
c340304d MB |
1027 | /* Set the source up */ |
1028 | snd_soc_update_bits(codec, WM8994_CLASS_W_1, | |
1029 | WM8994_CP_DYN_SRC_SEL_MASK, source); | |
c1a4ecd9 | 1030 | |
c340304d | 1031 | return true; |
9e6e96a1 MB |
1032 | } |
1033 | ||
1a38336b MB |
1034 | static int aif1clk_ev(struct snd_soc_dapm_widget *w, |
1035 | struct snd_kcontrol *kcontrol, int event) | |
173efa09 DP |
1036 | { |
1037 | struct snd_soc_codec *codec = w->codec; | |
79748cdb | 1038 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
d3134e21 | 1039 | struct wm8994 *control = wm8994->wm8994; |
1a38336b | 1040 | int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA; |
bfd37bb5 | 1041 | int i; |
1a38336b MB |
1042 | int dac; |
1043 | int adc; | |
1044 | int val; | |
1045 | ||
1046 | switch (control->type) { | |
1047 | case WM8994: | |
1048 | case WM8958: | |
1049 | mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA; | |
1050 | break; | |
1051 | default: | |
1052 | break; | |
1053 | } | |
173efa09 DP |
1054 | |
1055 | switch (event) { | |
1056 | case SND_SOC_DAPM_PRE_PMU: | |
79748cdb MB |
1057 | /* Don't enable timeslot 2 if not in use */ |
1058 | if (wm8994->channels[0] <= 2) | |
1059 | mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); | |
1060 | ||
1a38336b MB |
1061 | val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1); |
1062 | if ((val & WM8994_AIF1ADCL_SRC) && | |
1063 | (val & WM8994_AIF1ADCR_SRC)) | |
1064 | adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA; | |
1065 | else if (!(val & WM8994_AIF1ADCL_SRC) && | |
1066 | !(val & WM8994_AIF1ADCR_SRC)) | |
1067 | adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; | |
1068 | else | |
1069 | adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA | | |
1070 | WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA; | |
1071 | ||
1072 | val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2); | |
1073 | if ((val & WM8994_AIF1DACL_SRC) && | |
1074 | (val & WM8994_AIF1DACR_SRC)) | |
1075 | dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA; | |
1076 | else if (!(val & WM8994_AIF1DACL_SRC) && | |
1077 | !(val & WM8994_AIF1DACR_SRC)) | |
1078 | dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; | |
1079 | else | |
1080 | dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA | | |
1081 | WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA; | |
1082 | ||
1083 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, | |
1084 | mask, adc); | |
1085 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
1086 | mask, dac); | |
1087 | snd_soc_update_bits(codec, WM8994_CLOCKING_1, | |
1088 | WM8994_AIF1DSPCLK_ENA | | |
1089 | WM8994_SYSDSPCLK_ENA, | |
1090 | WM8994_AIF1DSPCLK_ENA | | |
1091 | WM8994_SYSDSPCLK_ENA); | |
1092 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask, | |
1093 | WM8994_AIF1ADC1R_ENA | | |
1094 | WM8994_AIF1ADC1L_ENA | | |
1095 | WM8994_AIF1ADC2R_ENA | | |
1096 | WM8994_AIF1ADC2L_ENA); | |
1097 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask, | |
1098 | WM8994_AIF1DAC1R_ENA | | |
1099 | WM8994_AIF1DAC1L_ENA | | |
1100 | WM8994_AIF1DAC2R_ENA | | |
1101 | WM8994_AIF1DAC2L_ENA); | |
173efa09 | 1102 | break; |
173efa09 | 1103 | |
bfd37bb5 MB |
1104 | case SND_SOC_DAPM_POST_PMU: |
1105 | for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) | |
1106 | snd_soc_write(codec, wm8994_vu_bits[i].reg, | |
1107 | snd_soc_read(codec, | |
1108 | wm8994_vu_bits[i].reg)); | |
1109 | break; | |
1110 | ||
1a38336b MB |
1111 | case SND_SOC_DAPM_PRE_PMD: |
1112 | case SND_SOC_DAPM_POST_PMD: | |
1113 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
1114 | mask, 0); | |
1115 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, | |
1116 | mask, 0); | |
1117 | ||
1118 | val = snd_soc_read(codec, WM8994_CLOCKING_1); | |
1119 | if (val & WM8994_AIF2DSPCLK_ENA) | |
1120 | val = WM8994_SYSDSPCLK_ENA; | |
1121 | else | |
1122 | val = 0; | |
1123 | snd_soc_update_bits(codec, WM8994_CLOCKING_1, | |
1124 | WM8994_SYSDSPCLK_ENA | | |
1125 | WM8994_AIF1DSPCLK_ENA, val); | |
1126 | break; | |
1127 | } | |
c6b7b570 | 1128 | |
173efa09 DP |
1129 | return 0; |
1130 | } | |
1131 | ||
1a38336b MB |
1132 | static int aif2clk_ev(struct snd_soc_dapm_widget *w, |
1133 | struct snd_kcontrol *kcontrol, int event) | |
173efa09 DP |
1134 | { |
1135 | struct snd_soc_codec *codec = w->codec; | |
bfd37bb5 | 1136 | int i; |
1a38336b MB |
1137 | int dac; |
1138 | int adc; | |
1139 | int val; | |
173efa09 DP |
1140 | |
1141 | switch (event) { | |
1a38336b MB |
1142 | case SND_SOC_DAPM_PRE_PMU: |
1143 | val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1); | |
1144 | if ((val & WM8994_AIF2ADCL_SRC) && | |
1145 | (val & WM8994_AIF2ADCR_SRC)) | |
1146 | adc = WM8994_AIF2ADCR_ENA; | |
1147 | else if (!(val & WM8994_AIF2ADCL_SRC) && | |
1148 | !(val & WM8994_AIF2ADCR_SRC)) | |
1149 | adc = WM8994_AIF2ADCL_ENA; | |
1150 | else | |
1151 | adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA; | |
1152 | ||
1153 | ||
1154 | val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2); | |
1155 | if ((val & WM8994_AIF2DACL_SRC) && | |
1156 | (val & WM8994_AIF2DACR_SRC)) | |
1157 | dac = WM8994_AIF2DACR_ENA; | |
1158 | else if (!(val & WM8994_AIF2DACL_SRC) && | |
1159 | !(val & WM8994_AIF2DACR_SRC)) | |
1160 | dac = WM8994_AIF2DACL_ENA; | |
1161 | else | |
1162 | dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA; | |
1163 | ||
1164 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, | |
1165 | WM8994_AIF2ADCL_ENA | | |
1166 | WM8994_AIF2ADCR_ENA, adc); | |
1167 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
1168 | WM8994_AIF2DACL_ENA | | |
1169 | WM8994_AIF2DACR_ENA, dac); | |
1170 | snd_soc_update_bits(codec, WM8994_CLOCKING_1, | |
1171 | WM8994_AIF2DSPCLK_ENA | | |
1172 | WM8994_SYSDSPCLK_ENA, | |
1173 | WM8994_AIF2DSPCLK_ENA | | |
1174 | WM8994_SYSDSPCLK_ENA); | |
1175 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, | |
1176 | WM8994_AIF2ADCL_ENA | | |
1177 | WM8994_AIF2ADCR_ENA, | |
1178 | WM8994_AIF2ADCL_ENA | | |
1179 | WM8994_AIF2ADCR_ENA); | |
1180 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
1181 | WM8994_AIF2DACL_ENA | | |
1182 | WM8994_AIF2DACR_ENA, | |
1183 | WM8994_AIF2DACL_ENA | | |
1184 | WM8994_AIF2DACR_ENA); | |
1185 | break; | |
1186 | ||
bfd37bb5 MB |
1187 | case SND_SOC_DAPM_POST_PMU: |
1188 | for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) | |
1189 | snd_soc_write(codec, wm8994_vu_bits[i].reg, | |
1190 | snd_soc_read(codec, | |
1191 | wm8994_vu_bits[i].reg)); | |
1192 | break; | |
1193 | ||
1a38336b | 1194 | case SND_SOC_DAPM_PRE_PMD: |
173efa09 | 1195 | case SND_SOC_DAPM_POST_PMD: |
1a38336b MB |
1196 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, |
1197 | WM8994_AIF2DACL_ENA | | |
1198 | WM8994_AIF2DACR_ENA, 0); | |
c7f5f238 | 1199 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, |
1a38336b MB |
1200 | WM8994_AIF2ADCL_ENA | |
1201 | WM8994_AIF2ADCR_ENA, 0); | |
1202 | ||
1203 | val = snd_soc_read(codec, WM8994_CLOCKING_1); | |
1204 | if (val & WM8994_AIF1DSPCLK_ENA) | |
1205 | val = WM8994_SYSDSPCLK_ENA; | |
1206 | else | |
1207 | val = 0; | |
1208 | snd_soc_update_bits(codec, WM8994_CLOCKING_1, | |
1209 | WM8994_SYSDSPCLK_ENA | | |
1210 | WM8994_AIF2DSPCLK_ENA, val); | |
173efa09 DP |
1211 | break; |
1212 | } | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
1a38336b MB |
1217 | static int aif1clk_late_ev(struct snd_soc_dapm_widget *w, |
1218 | struct snd_kcontrol *kcontrol, int event) | |
173efa09 DP |
1219 | { |
1220 | struct snd_soc_codec *codec = w->codec; | |
1221 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
1222 | ||
1223 | switch (event) { | |
1224 | case SND_SOC_DAPM_PRE_PMU: | |
1225 | wm8994->aif1clk_enable = 1; | |
1226 | break; | |
a3cff81a DP |
1227 | case SND_SOC_DAPM_POST_PMD: |
1228 | wm8994->aif1clk_disable = 1; | |
1229 | break; | |
173efa09 DP |
1230 | } |
1231 | ||
1232 | return 0; | |
1233 | } | |
1234 | ||
1a38336b MB |
1235 | static int aif2clk_late_ev(struct snd_soc_dapm_widget *w, |
1236 | struct snd_kcontrol *kcontrol, int event) | |
173efa09 DP |
1237 | { |
1238 | struct snd_soc_codec *codec = w->codec; | |
1239 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
1240 | ||
1241 | switch (event) { | |
1242 | case SND_SOC_DAPM_PRE_PMU: | |
1243 | wm8994->aif2clk_enable = 1; | |
1244 | break; | |
a3cff81a DP |
1245 | case SND_SOC_DAPM_POST_PMD: |
1246 | wm8994->aif2clk_disable = 1; | |
1247 | break; | |
173efa09 DP |
1248 | } |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1a38336b MB |
1253 | static int late_enable_ev(struct snd_soc_dapm_widget *w, |
1254 | struct snd_kcontrol *kcontrol, int event) | |
1255 | { | |
1256 | struct snd_soc_codec *codec = w->codec; | |
1257 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
1258 | ||
1259 | switch (event) { | |
1260 | case SND_SOC_DAPM_PRE_PMU: | |
1261 | if (wm8994->aif1clk_enable) { | |
c8fdc1b5 | 1262 | aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); |
1a38336b MB |
1263 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, |
1264 | WM8994_AIF1CLK_ENA_MASK, | |
1265 | WM8994_AIF1CLK_ENA); | |
c8fdc1b5 | 1266 | aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); |
1a38336b MB |
1267 | wm8994->aif1clk_enable = 0; |
1268 | } | |
1269 | if (wm8994->aif2clk_enable) { | |
c8fdc1b5 | 1270 | aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU); |
1a38336b MB |
1271 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, |
1272 | WM8994_AIF2CLK_ENA_MASK, | |
1273 | WM8994_AIF2CLK_ENA); | |
c8fdc1b5 | 1274 | aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU); |
1a38336b MB |
1275 | wm8994->aif2clk_enable = 0; |
1276 | } | |
1277 | break; | |
1278 | } | |
1279 | ||
1280 | /* We may also have postponed startup of DSP, handle that. */ | |
1281 | wm8958_aif_ev(w, kcontrol, event); | |
1282 | ||
1283 | return 0; | |
1284 | } | |
1285 | ||
1286 | static int late_disable_ev(struct snd_soc_dapm_widget *w, | |
1287 | struct snd_kcontrol *kcontrol, int event) | |
1288 | { | |
1289 | struct snd_soc_codec *codec = w->codec; | |
1290 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
1291 | ||
1292 | switch (event) { | |
1293 | case SND_SOC_DAPM_POST_PMD: | |
1294 | if (wm8994->aif1clk_disable) { | |
c8fdc1b5 | 1295 | aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); |
1a38336b MB |
1296 | snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1, |
1297 | WM8994_AIF1CLK_ENA_MASK, 0); | |
c8fdc1b5 | 1298 | aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); |
1a38336b MB |
1299 | wm8994->aif1clk_disable = 0; |
1300 | } | |
1301 | if (wm8994->aif2clk_disable) { | |
c8fdc1b5 | 1302 | aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD); |
1a38336b MB |
1303 | snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1, |
1304 | WM8994_AIF2CLK_ENA_MASK, 0); | |
c8fdc1b5 | 1305 | aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD); |
1a38336b MB |
1306 | wm8994->aif2clk_disable = 0; |
1307 | } | |
1308 | break; | |
1309 | } | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
04d28681 DP |
1314 | static int adc_mux_ev(struct snd_soc_dapm_widget *w, |
1315 | struct snd_kcontrol *kcontrol, int event) | |
1316 | { | |
1317 | late_enable_ev(w, kcontrol, event); | |
1318 | return 0; | |
1319 | } | |
1320 | ||
b462c6e6 DP |
1321 | static int micbias_ev(struct snd_soc_dapm_widget *w, |
1322 | struct snd_kcontrol *kcontrol, int event) | |
1323 | { | |
1324 | late_enable_ev(w, kcontrol, event); | |
1325 | return 0; | |
1326 | } | |
1327 | ||
c52fd021 DP |
1328 | static int dac_ev(struct snd_soc_dapm_widget *w, |
1329 | struct snd_kcontrol *kcontrol, int event) | |
1330 | { | |
1331 | struct snd_soc_codec *codec = w->codec; | |
1332 | unsigned int mask = 1 << w->shift; | |
1333 | ||
1334 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
1335 | mask, mask); | |
1336 | return 0; | |
1337 | } | |
1338 | ||
9e6e96a1 MB |
1339 | static const char *adc_mux_text[] = { |
1340 | "ADC", | |
1341 | "DMIC", | |
1342 | }; | |
1343 | ||
1344 | static const struct soc_enum adc_enum = | |
1345 | SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); | |
1346 | ||
1347 | static const struct snd_kcontrol_new adcl_mux = | |
1348 | SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); | |
1349 | ||
1350 | static const struct snd_kcontrol_new adcr_mux = | |
1351 | SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); | |
1352 | ||
1353 | static const struct snd_kcontrol_new left_speaker_mixer[] = { | |
1354 | SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0), | |
1355 | SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0), | |
1356 | SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0), | |
1357 | SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0), | |
1358 | SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0), | |
1359 | }; | |
1360 | ||
1361 | static const struct snd_kcontrol_new right_speaker_mixer[] = { | |
1362 | SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0), | |
1363 | SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0), | |
1364 | SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0), | |
1365 | SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0), | |
1366 | SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0), | |
1367 | }; | |
1368 | ||
1369 | /* Debugging; dump chip status after DAPM transitions */ | |
1370 | static int post_ev(struct snd_soc_dapm_widget *w, | |
1371 | struct snd_kcontrol *kcontrol, int event) | |
1372 | { | |
1373 | struct snd_soc_codec *codec = w->codec; | |
1374 | dev_dbg(codec->dev, "SRC status: %x\n", | |
1375 | snd_soc_read(codec, | |
1376 | WM8994_RATE_STATUS)); | |
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | static const struct snd_kcontrol_new aif1adc1l_mix[] = { | |
1381 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
1382 | 1, 1, 0), | |
1383 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
1384 | 0, 1, 0), | |
1385 | }; | |
1386 | ||
1387 | static const struct snd_kcontrol_new aif1adc1r_mix[] = { | |
1388 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
1389 | 1, 1, 0), | |
1390 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
1391 | 0, 1, 0), | |
1392 | }; | |
1393 | ||
a3257ba8 MB |
1394 | static const struct snd_kcontrol_new aif1adc2l_mix[] = { |
1395 | SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
1396 | 1, 1, 0), | |
1397 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
1398 | 0, 1, 0), | |
1399 | }; | |
1400 | ||
1401 | static const struct snd_kcontrol_new aif1adc2r_mix[] = { | |
1402 | SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
1403 | 1, 1, 0), | |
1404 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
1405 | 0, 1, 0), | |
1406 | }; | |
1407 | ||
9e6e96a1 MB |
1408 | static const struct snd_kcontrol_new aif2dac2l_mix[] = { |
1409 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1410 | 5, 1, 0), | |
1411 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1412 | 4, 1, 0), | |
1413 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1414 | 2, 1, 0), | |
1415 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1416 | 1, 1, 0), | |
1417 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING, | |
1418 | 0, 1, 0), | |
1419 | }; | |
1420 | ||
1421 | static const struct snd_kcontrol_new aif2dac2r_mix[] = { | |
1422 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1423 | 5, 1, 0), | |
1424 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1425 | 4, 1, 0), | |
1426 | SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1427 | 2, 1, 0), | |
1428 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1429 | 1, 1, 0), | |
1430 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING, | |
1431 | 0, 1, 0), | |
1432 | }; | |
1433 | ||
1434 | #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \ | |
1435 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ | |
1436 | .info = snd_soc_info_volsw, \ | |
1437 | .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \ | |
1438 | .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) } | |
1439 | ||
1440 | static int wm8994_put_class_w(struct snd_kcontrol *kcontrol, | |
1441 | struct snd_ctl_elem_value *ucontrol) | |
1442 | { | |
9d03545d JN |
1443 | struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); |
1444 | struct snd_soc_dapm_widget *w = wlist->widgets[0]; | |
9e6e96a1 MB |
1445 | struct snd_soc_codec *codec = w->codec; |
1446 | int ret; | |
1447 | ||
1448 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
1449 | ||
c340304d | 1450 | wm_hubs_update_class_w(codec); |
9e6e96a1 MB |
1451 | |
1452 | return ret; | |
1453 | } | |
1454 | ||
1455 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
1456 | WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1457 | 5, 1, 0), | |
1458 | WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1459 | 4, 1, 0), | |
1460 | WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1461 | 2, 1, 0), | |
1462 | WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1463 | 1, 1, 0), | |
1464 | WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING, | |
1465 | 0, 1, 0), | |
1466 | }; | |
1467 | ||
1468 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
1469 | WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1470 | 5, 1, 0), | |
1471 | WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1472 | 4, 1, 0), | |
1473 | WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1474 | 2, 1, 0), | |
1475 | WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1476 | 1, 1, 0), | |
1477 | WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING, | |
1478 | 0, 1, 0), | |
1479 | }; | |
1480 | ||
1481 | static const char *sidetone_text[] = { | |
1482 | "ADC/DMIC1", "DMIC2", | |
1483 | }; | |
1484 | ||
1485 | static const struct soc_enum sidetone1_enum = | |
1486 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text); | |
1487 | ||
1488 | static const struct snd_kcontrol_new sidetone1_mux = | |
1489 | SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); | |
1490 | ||
1491 | static const struct soc_enum sidetone2_enum = | |
1492 | SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text); | |
1493 | ||
1494 | static const struct snd_kcontrol_new sidetone2_mux = | |
1495 | SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); | |
1496 | ||
1497 | static const char *aif1dac_text[] = { | |
1498 | "AIF1DACDAT", "AIF3DACDAT", | |
1499 | }; | |
1500 | ||
1501 | static const struct soc_enum aif1dac_enum = | |
1502 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text); | |
1503 | ||
1504 | static const struct snd_kcontrol_new aif1dac_mux = | |
1505 | SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum); | |
1506 | ||
1507 | static const char *aif2dac_text[] = { | |
1508 | "AIF2DACDAT", "AIF3DACDAT", | |
1509 | }; | |
1510 | ||
1511 | static const struct soc_enum aif2dac_enum = | |
1512 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text); | |
1513 | ||
1514 | static const struct snd_kcontrol_new aif2dac_mux = | |
1515 | SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum); | |
1516 | ||
1517 | static const char *aif2adc_text[] = { | |
1518 | "AIF2ADCDAT", "AIF3DACDAT", | |
1519 | }; | |
1520 | ||
1521 | static const struct soc_enum aif2adc_enum = | |
1522 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text); | |
1523 | ||
1524 | static const struct snd_kcontrol_new aif2adc_mux = | |
1525 | SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum); | |
1526 | ||
1527 | static const char *aif3adc_text[] = { | |
c4431df0 | 1528 | "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM", |
9e6e96a1 MB |
1529 | }; |
1530 | ||
c4431df0 | 1531 | static const struct soc_enum wm8994_aif3adc_enum = |
9e6e96a1 MB |
1532 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text); |
1533 | ||
c4431df0 MB |
1534 | static const struct snd_kcontrol_new wm8994_aif3adc_mux = |
1535 | SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum); | |
1536 | ||
1537 | static const struct soc_enum wm8958_aif3adc_enum = | |
1538 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text); | |
1539 | ||
1540 | static const struct snd_kcontrol_new wm8958_aif3adc_mux = | |
1541 | SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum); | |
1542 | ||
1543 | static const char *mono_pcm_out_text[] = { | |
c1a4ecd9 | 1544 | "None", "AIF2ADCL", "AIF2ADCR", |
c4431df0 MB |
1545 | }; |
1546 | ||
1547 | static const struct soc_enum mono_pcm_out_enum = | |
1548 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text); | |
1549 | ||
1550 | static const struct snd_kcontrol_new mono_pcm_out_mux = | |
1551 | SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum); | |
1552 | ||
1553 | static const char *aif2dac_src_text[] = { | |
1554 | "AIF2", "AIF3", | |
1555 | }; | |
1556 | ||
1557 | /* Note that these two control shouldn't be simultaneously switched to AIF3 */ | |
1558 | static const struct soc_enum aif2dacl_src_enum = | |
1559 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text); | |
1560 | ||
1561 | static const struct snd_kcontrol_new aif2dacl_src_mux = | |
1562 | SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum); | |
1563 | ||
1564 | static const struct soc_enum aif2dacr_src_enum = | |
1565 | SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text); | |
1566 | ||
1567 | static const struct snd_kcontrol_new aif2dacr_src_mux = | |
1568 | SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum); | |
9e6e96a1 | 1569 | |
173efa09 | 1570 | static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = { |
1a38336b | 1571 | SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev, |
173efa09 | 1572 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
1a38336b | 1573 | SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev, |
173efa09 DP |
1574 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
1575 | ||
1576 | SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1577 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1578 | SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1579 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1580 | SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1581 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1582 | SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
1583 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
b70a51ba MB |
1584 | SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0, |
1585 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1586 | ||
1587 | SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, | |
1588 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer), | |
1589 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
1590 | SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, | |
1591 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer), | |
1592 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), | |
c340304d | 1593 | SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux, |
b70a51ba | 1594 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), |
c340304d | 1595 | SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux, |
b70a51ba | 1596 | late_enable_ev, SND_SOC_DAPM_PRE_PMU), |
173efa09 DP |
1597 | |
1598 | SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev) | |
1599 | }; | |
1600 | ||
1601 | static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = { | |
1a38336b | 1602 | SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev, |
bfd37bb5 MB |
1603 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1604 | SND_SOC_DAPM_PRE_PMD), | |
1a38336b | 1605 | SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev, |
bfd37bb5 MB |
1606 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1607 | SND_SOC_DAPM_PRE_PMD), | |
b70a51ba MB |
1608 | SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0), |
1609 | SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0, | |
1610 | left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)), | |
1611 | SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0, | |
1612 | right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)), | |
c340304d MB |
1613 | SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux), |
1614 | SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux), | |
173efa09 DP |
1615 | }; |
1616 | ||
c52fd021 DP |
1617 | static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = { |
1618 | SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0, | |
1619 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1620 | SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0, | |
1621 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1622 | SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0, | |
1623 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1624 | SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0, | |
1625 | dac_ev, SND_SOC_DAPM_PRE_PMU), | |
1626 | }; | |
1627 | ||
1628 | static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = { | |
1629 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0), | |
0627bd25 | 1630 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0), |
c52fd021 DP |
1631 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0), |
1632 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0), | |
1633 | }; | |
1634 | ||
04d28681 | 1635 | static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = { |
87b86ade MB |
1636 | SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux, |
1637 | adc_mux_ev, SND_SOC_DAPM_PRE_PMU), | |
1638 | SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux, | |
1639 | adc_mux_ev, SND_SOC_DAPM_PRE_PMU), | |
04d28681 DP |
1640 | }; |
1641 | ||
1642 | static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = { | |
87b86ade MB |
1643 | SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux), |
1644 | SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux), | |
04d28681 DP |
1645 | }; |
1646 | ||
9e6e96a1 MB |
1647 | static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = { |
1648 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
1649 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
66b47fdb | 1650 | SND_SOC_DAPM_INPUT("Clock"), |
9e6e96a1 | 1651 | |
b462c6e6 DP |
1652 | SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev, |
1653 | SND_SOC_DAPM_PRE_PMU), | |
4b7ed83a MB |
1654 | SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event, |
1655 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), | |
b462c6e6 | 1656 | |
9e6e96a1 | 1657 | SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, |
99af79df MB |
1658 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
1659 | SND_SOC_DAPM_PRE_PMD), | |
9e6e96a1 | 1660 | |
1a38336b MB |
1661 | SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0), |
1662 | SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0), | |
1663 | SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0), | |
9e6e96a1 | 1664 | |
7f94de48 | 1665 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL, |
1a38336b | 1666 | 0, SND_SOC_NOPM, 9, 0), |
7f94de48 | 1667 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL, |
1a38336b | 1668 | 0, SND_SOC_NOPM, 8, 0), |
d6addcc9 | 1669 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0, |
1a38336b | 1670 | SND_SOC_NOPM, 9, 0, wm8958_aif_ev, |
b2822a8c | 1671 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
d6addcc9 | 1672 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0, |
1a38336b | 1673 | SND_SOC_NOPM, 8, 0, wm8958_aif_ev, |
b2822a8c | 1674 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
9e6e96a1 | 1675 | |
7f94de48 | 1676 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL, |
1a38336b | 1677 | 0, SND_SOC_NOPM, 11, 0), |
7f94de48 | 1678 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL, |
1a38336b | 1679 | 0, SND_SOC_NOPM, 10, 0), |
d6addcc9 | 1680 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0, |
1a38336b | 1681 | SND_SOC_NOPM, 11, 0, wm8958_aif_ev, |
b2822a8c | 1682 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
d6addcc9 | 1683 | SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0, |
1a38336b | 1684 | SND_SOC_NOPM, 10, 0, wm8958_aif_ev, |
b2822a8c | 1685 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
9e6e96a1 MB |
1686 | |
1687 | SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, | |
1688 | aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), | |
1689 | SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, | |
1690 | aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), | |
1691 | ||
a3257ba8 MB |
1692 | SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, |
1693 | aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), | |
1694 | SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, | |
1695 | aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), | |
1696 | ||
9e6e96a1 MB |
1697 | SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, |
1698 | aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), | |
1699 | SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
1700 | aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), | |
1701 | ||
1702 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), | |
1703 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), | |
1704 | ||
1705 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, | |
1706 | dac1l_mix, ARRAY_SIZE(dac1l_mix)), | |
1707 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, | |
1708 | dac1r_mix, ARRAY_SIZE(dac1r_mix)), | |
1709 | ||
1710 | SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0, | |
1a38336b | 1711 | SND_SOC_NOPM, 13, 0), |
9e6e96a1 | 1712 | SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0, |
1a38336b | 1713 | SND_SOC_NOPM, 12, 0), |
d6addcc9 | 1714 | SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0, |
1a38336b | 1715 | SND_SOC_NOPM, 13, 0, wm8958_aif_ev, |
d6addcc9 MB |
1716 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
1717 | SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0, | |
1a38336b | 1718 | SND_SOC_NOPM, 12, 0, wm8958_aif_ev, |
d6addcc9 | 1719 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
9e6e96a1 | 1720 | |
5567d8c6 MB |
1721 | SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), |
1722 | SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1723 | SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), | |
1724 | SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), | |
9e6e96a1 MB |
1725 | |
1726 | SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux), | |
1727 | SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux), | |
1728 | SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux), | |
9e6e96a1 | 1729 | |
5567d8c6 MB |
1730 | SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0), |
1731 | SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0), | |
9e6e96a1 MB |
1732 | |
1733 | SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0), | |
1734 | ||
1735 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0), | |
1736 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0), | |
1737 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0), | |
1738 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0), | |
1739 | ||
1740 | /* Power is done with the muxes since the ADC power also controls the | |
1741 | * downsampling chain, the chip will automatically manage the analogue | |
1742 | * specific portions. | |
1743 | */ | |
1744 | SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0), | |
1745 | SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), | |
1746 | ||
9e6e96a1 MB |
1747 | SND_SOC_DAPM_POST("Debug log", post_ev), |
1748 | }; | |
1749 | ||
c4431df0 MB |
1750 | static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = { |
1751 | SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux), | |
1752 | }; | |
9e6e96a1 | 1753 | |
c4431df0 | 1754 | static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = { |
8c5b842b | 1755 | SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0), |
c4431df0 MB |
1756 | SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux), |
1757 | SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux), | |
1758 | SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux), | |
1759 | SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux), | |
1760 | }; | |
1761 | ||
1762 | static const struct snd_soc_dapm_route intercon[] = { | |
9e6e96a1 MB |
1763 | { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, |
1764 | { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, | |
1765 | ||
1766 | { "DSP1CLK", NULL, "CLK_SYS" }, | |
1767 | { "DSP2CLK", NULL, "CLK_SYS" }, | |
1768 | { "DSPINTCLK", NULL, "CLK_SYS" }, | |
1769 | ||
1770 | { "AIF1ADC1L", NULL, "AIF1CLK" }, | |
1771 | { "AIF1ADC1L", NULL, "DSP1CLK" }, | |
1772 | { "AIF1ADC1R", NULL, "AIF1CLK" }, | |
1773 | { "AIF1ADC1R", NULL, "DSP1CLK" }, | |
1774 | { "AIF1ADC1R", NULL, "DSPINTCLK" }, | |
1775 | ||
1776 | { "AIF1DAC1L", NULL, "AIF1CLK" }, | |
1777 | { "AIF1DAC1L", NULL, "DSP1CLK" }, | |
1778 | { "AIF1DAC1R", NULL, "AIF1CLK" }, | |
1779 | { "AIF1DAC1R", NULL, "DSP1CLK" }, | |
1780 | { "AIF1DAC1R", NULL, "DSPINTCLK" }, | |
1781 | ||
1782 | { "AIF1ADC2L", NULL, "AIF1CLK" }, | |
1783 | { "AIF1ADC2L", NULL, "DSP1CLK" }, | |
1784 | { "AIF1ADC2R", NULL, "AIF1CLK" }, | |
1785 | { "AIF1ADC2R", NULL, "DSP1CLK" }, | |
1786 | { "AIF1ADC2R", NULL, "DSPINTCLK" }, | |
1787 | ||
1788 | { "AIF1DAC2L", NULL, "AIF1CLK" }, | |
1789 | { "AIF1DAC2L", NULL, "DSP1CLK" }, | |
1790 | { "AIF1DAC2R", NULL, "AIF1CLK" }, | |
1791 | { "AIF1DAC2R", NULL, "DSP1CLK" }, | |
1792 | { "AIF1DAC2R", NULL, "DSPINTCLK" }, | |
1793 | ||
1794 | { "AIF2ADCL", NULL, "AIF2CLK" }, | |
1795 | { "AIF2ADCL", NULL, "DSP2CLK" }, | |
1796 | { "AIF2ADCR", NULL, "AIF2CLK" }, | |
1797 | { "AIF2ADCR", NULL, "DSP2CLK" }, | |
1798 | { "AIF2ADCR", NULL, "DSPINTCLK" }, | |
1799 | ||
1800 | { "AIF2DACL", NULL, "AIF2CLK" }, | |
1801 | { "AIF2DACL", NULL, "DSP2CLK" }, | |
1802 | { "AIF2DACR", NULL, "AIF2CLK" }, | |
1803 | { "AIF2DACR", NULL, "DSP2CLK" }, | |
1804 | { "AIF2DACR", NULL, "DSPINTCLK" }, | |
1805 | ||
1806 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
1807 | { "DMIC1L", NULL, "CLK_SYS" }, | |
1808 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
1809 | { "DMIC1R", NULL, "CLK_SYS" }, | |
1810 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
1811 | { "DMIC2L", NULL, "CLK_SYS" }, | |
1812 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
1813 | { "DMIC2R", NULL, "CLK_SYS" }, | |
1814 | ||
1815 | { "ADCL", NULL, "AIF1CLK" }, | |
1816 | { "ADCL", NULL, "DSP1CLK" }, | |
1817 | { "ADCL", NULL, "DSPINTCLK" }, | |
1818 | ||
1819 | { "ADCR", NULL, "AIF1CLK" }, | |
1820 | { "ADCR", NULL, "DSP1CLK" }, | |
1821 | { "ADCR", NULL, "DSPINTCLK" }, | |
1822 | ||
1823 | { "ADCL Mux", "ADC", "ADCL" }, | |
1824 | { "ADCL Mux", "DMIC", "DMIC1L" }, | |
1825 | { "ADCR Mux", "ADC", "ADCR" }, | |
1826 | { "ADCR Mux", "DMIC", "DMIC1R" }, | |
1827 | ||
1828 | { "DAC1L", NULL, "AIF1CLK" }, | |
1829 | { "DAC1L", NULL, "DSP1CLK" }, | |
1830 | { "DAC1L", NULL, "DSPINTCLK" }, | |
1831 | ||
1832 | { "DAC1R", NULL, "AIF1CLK" }, | |
1833 | { "DAC1R", NULL, "DSP1CLK" }, | |
1834 | { "DAC1R", NULL, "DSPINTCLK" }, | |
1835 | ||
1836 | { "DAC2L", NULL, "AIF2CLK" }, | |
1837 | { "DAC2L", NULL, "DSP2CLK" }, | |
1838 | { "DAC2L", NULL, "DSPINTCLK" }, | |
1839 | ||
1840 | { "DAC2R", NULL, "AIF2DACR" }, | |
1841 | { "DAC2R", NULL, "AIF2CLK" }, | |
1842 | { "DAC2R", NULL, "DSP2CLK" }, | |
1843 | { "DAC2R", NULL, "DSPINTCLK" }, | |
1844 | ||
1845 | { "TOCLK", NULL, "CLK_SYS" }, | |
1846 | ||
5567d8c6 MB |
1847 | { "AIF1DACDAT", NULL, "AIF1 Playback" }, |
1848 | { "AIF2DACDAT", NULL, "AIF2 Playback" }, | |
1849 | { "AIF3DACDAT", NULL, "AIF3 Playback" }, | |
1850 | ||
1851 | { "AIF1 Capture", NULL, "AIF1ADCDAT" }, | |
1852 | { "AIF2 Capture", NULL, "AIF2ADCDAT" }, | |
1853 | { "AIF3 Capture", NULL, "AIF3ADCDAT" }, | |
1854 | ||
9e6e96a1 MB |
1855 | /* AIF1 outputs */ |
1856 | { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, | |
1857 | { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, | |
1858 | { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
1859 | ||
1860 | { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, | |
1861 | { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, | |
1862 | { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
1863 | ||
a3257ba8 MB |
1864 | { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, |
1865 | { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, | |
1866 | { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" }, | |
1867 | ||
1868 | { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, | |
1869 | { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, | |
1870 | { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" }, | |
1871 | ||
9e6e96a1 MB |
1872 | /* Pin level routing for AIF3 */ |
1873 | { "AIF1DAC1L", NULL, "AIF1DAC Mux" }, | |
1874 | { "AIF1DAC1R", NULL, "AIF1DAC Mux" }, | |
1875 | { "AIF1DAC2L", NULL, "AIF1DAC Mux" }, | |
1876 | { "AIF1DAC2R", NULL, "AIF1DAC Mux" }, | |
1877 | ||
9e6e96a1 MB |
1878 | { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" }, |
1879 | { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, | |
1880 | { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" }, | |
1881 | { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" }, | |
1882 | { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" }, | |
1883 | { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" }, | |
1884 | { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" }, | |
1885 | ||
1886 | /* DAC1 inputs */ | |
9e6e96a1 MB |
1887 | { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" }, |
1888 | { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
1889 | { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
1890 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1891 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1892 | ||
9e6e96a1 MB |
1893 | { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" }, |
1894 | { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
1895 | { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
1896 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1897 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1898 | ||
1899 | /* DAC2/AIF2 outputs */ | |
1900 | { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" }, | |
9e6e96a1 MB |
1901 | { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" }, |
1902 | { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
1903 | { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
1904 | { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1905 | { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1906 | ||
1907 | { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" }, | |
9e6e96a1 MB |
1908 | { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" }, |
1909 | { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
1910 | { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
1911 | { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
1912 | { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
1913 | ||
7f94de48 MB |
1914 | { "AIF1ADCDAT", NULL, "AIF1ADC1L" }, |
1915 | { "AIF1ADCDAT", NULL, "AIF1ADC1R" }, | |
1916 | { "AIF1ADCDAT", NULL, "AIF1ADC2L" }, | |
1917 | { "AIF1ADCDAT", NULL, "AIF1ADC2R" }, | |
1918 | ||
9e6e96a1 MB |
1919 | { "AIF2ADCDAT", NULL, "AIF2ADC Mux" }, |
1920 | ||
1921 | /* AIF3 output */ | |
1922 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" }, | |
1923 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" }, | |
1924 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" }, | |
1925 | { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" }, | |
1926 | { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" }, | |
1927 | { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" }, | |
1928 | { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" }, | |
1929 | { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" }, | |
1930 | ||
1931 | /* Sidetone */ | |
1932 | { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" }, | |
1933 | { "Left Sidetone", "DMIC2", "DMIC2L" }, | |
1934 | { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" }, | |
1935 | { "Right Sidetone", "DMIC2", "DMIC2R" }, | |
1936 | ||
1937 | /* Output stages */ | |
1938 | { "Left Output Mixer", "DAC Switch", "DAC1L" }, | |
1939 | { "Right Output Mixer", "DAC Switch", "DAC1R" }, | |
1940 | ||
1941 | { "SPKL", "DAC1 Switch", "DAC1L" }, | |
1942 | { "SPKL", "DAC2 Switch", "DAC2L" }, | |
1943 | ||
1944 | { "SPKR", "DAC1 Switch", "DAC1R" }, | |
1945 | { "SPKR", "DAC2 Switch", "DAC2R" }, | |
1946 | ||
1947 | { "Left Headphone Mux", "DAC", "DAC1L" }, | |
1948 | { "Right Headphone Mux", "DAC", "DAC1R" }, | |
1949 | }; | |
1950 | ||
173efa09 DP |
1951 | static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = { |
1952 | { "DAC1L", NULL, "Late DAC1L Enable PGA" }, | |
1953 | { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" }, | |
1954 | { "DAC1R", NULL, "Late DAC1R Enable PGA" }, | |
1955 | { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" }, | |
1956 | { "DAC2L", NULL, "Late DAC2L Enable PGA" }, | |
1957 | { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" }, | |
1958 | { "DAC2R", NULL, "Late DAC2R Enable PGA" }, | |
1959 | { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" } | |
1960 | }; | |
1961 | ||
1962 | static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = { | |
1963 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
1964 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
1965 | { "DAC2L", NULL, "AIF2DAC2L Mixer" }, | |
1966 | { "DAC2R", NULL, "AIF2DAC2R Mixer" }, | |
1967 | }; | |
1968 | ||
6ed8f148 MB |
1969 | static const struct snd_soc_dapm_route wm8994_revd_intercon[] = { |
1970 | { "AIF1DACDAT", NULL, "AIF2DACDAT" }, | |
1971 | { "AIF2DACDAT", NULL, "AIF1DACDAT" }, | |
1972 | { "AIF1ADCDAT", NULL, "AIF2ADCDAT" }, | |
1973 | { "AIF2ADCDAT", NULL, "AIF1ADCDAT" }, | |
b793eb60 MB |
1974 | { "MICBIAS1", NULL, "CLK_SYS" }, |
1975 | { "MICBIAS1", NULL, "MICBIAS Supply" }, | |
1976 | { "MICBIAS2", NULL, "CLK_SYS" }, | |
1977 | { "MICBIAS2", NULL, "MICBIAS Supply" }, | |
6ed8f148 MB |
1978 | }; |
1979 | ||
c4431df0 MB |
1980 | static const struct snd_soc_dapm_route wm8994_intercon[] = { |
1981 | { "AIF2DACL", NULL, "AIF2DAC Mux" }, | |
1982 | { "AIF2DACR", NULL, "AIF2DAC Mux" }, | |
4e04adaf MB |
1983 | { "MICBIAS1", NULL, "VMID" }, |
1984 | { "MICBIAS2", NULL, "VMID" }, | |
c4431df0 MB |
1985 | }; |
1986 | ||
1987 | static const struct snd_soc_dapm_route wm8958_intercon[] = { | |
1988 | { "AIF2DACL", NULL, "AIF2DACL Mux" }, | |
1989 | { "AIF2DACR", NULL, "AIF2DACR Mux" }, | |
1990 | ||
1991 | { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" }, | |
1992 | { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" }, | |
1993 | { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" }, | |
1994 | { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" }, | |
1995 | ||
8c5b842b MB |
1996 | { "AIF3DACDAT", NULL, "AIF3" }, |
1997 | { "AIF3ADCDAT", NULL, "AIF3" }, | |
1998 | ||
c4431df0 MB |
1999 | { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" }, |
2000 | { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" }, | |
2001 | ||
2002 | { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" }, | |
2003 | }; | |
2004 | ||
9e6e96a1 MB |
2005 | /* The size in bits of the FLL divide multiplied by 10 |
2006 | * to allow rounding later */ | |
2007 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
2008 | ||
2009 | struct fll_div { | |
2010 | u16 outdiv; | |
2011 | u16 n; | |
2012 | u16 k; | |
2013 | u16 clk_ref_div; | |
2014 | u16 fll_fratio; | |
2015 | }; | |
2016 | ||
2017 | static int wm8994_get_fll_config(struct fll_div *fll, | |
2018 | int freq_in, int freq_out) | |
2019 | { | |
2020 | u64 Kpart; | |
2021 | unsigned int K, Ndiv, Nmod; | |
2022 | ||
2023 | pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); | |
2024 | ||
2025 | /* Scale the input frequency down to <= 13.5MHz */ | |
2026 | fll->clk_ref_div = 0; | |
2027 | while (freq_in > 13500000) { | |
2028 | fll->clk_ref_div++; | |
2029 | freq_in /= 2; | |
2030 | ||
2031 | if (fll->clk_ref_div > 3) | |
2032 | return -EINVAL; | |
2033 | } | |
2034 | pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); | |
2035 | ||
2036 | /* Scale the output to give 90MHz<=Fvco<=100MHz */ | |
2037 | fll->outdiv = 3; | |
2038 | while (freq_out * (fll->outdiv + 1) < 90000000) { | |
2039 | fll->outdiv++; | |
2040 | if (fll->outdiv > 63) | |
2041 | return -EINVAL; | |
2042 | } | |
2043 | freq_out *= fll->outdiv + 1; | |
2044 | pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); | |
2045 | ||
2046 | if (freq_in > 1000000) { | |
2047 | fll->fll_fratio = 0; | |
7d48a6ac MB |
2048 | } else if (freq_in > 256000) { |
2049 | fll->fll_fratio = 1; | |
2050 | freq_in *= 2; | |
2051 | } else if (freq_in > 128000) { | |
2052 | fll->fll_fratio = 2; | |
2053 | freq_in *= 4; | |
2054 | } else if (freq_in > 64000) { | |
9e6e96a1 MB |
2055 | fll->fll_fratio = 3; |
2056 | freq_in *= 8; | |
7d48a6ac MB |
2057 | } else { |
2058 | fll->fll_fratio = 4; | |
2059 | freq_in *= 16; | |
9e6e96a1 MB |
2060 | } |
2061 | pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); | |
2062 | ||
2063 | /* Now, calculate N.K */ | |
2064 | Ndiv = freq_out / freq_in; | |
2065 | ||
2066 | fll->n = Ndiv; | |
2067 | Nmod = freq_out % freq_in; | |
2068 | pr_debug("Nmod=%d\n", Nmod); | |
2069 | ||
2070 | /* Calculate fractional part - scale up so we can round. */ | |
2071 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
2072 | ||
2073 | do_div(Kpart, freq_in); | |
2074 | ||
2075 | K = Kpart & 0xFFFFFFFF; | |
2076 | ||
2077 | if ((K % 10) >= 5) | |
2078 | K += 5; | |
2079 | ||
2080 | /* Move down to proper range now rounding is done */ | |
2081 | fll->k = K / 10; | |
2082 | ||
2083 | pr_debug("N=%x K=%x\n", fll->n, fll->k); | |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
f0fba2ad | 2088 | static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src, |
9e6e96a1 MB |
2089 | unsigned int freq_in, unsigned int freq_out) |
2090 | { | |
b2c812e2 | 2091 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
2a8a856d | 2092 | struct wm8994 *control = wm8994->wm8994; |
9e6e96a1 MB |
2093 | int reg_offset, ret; |
2094 | struct fll_div fll; | |
e413ba88 | 2095 | u16 reg, clk1, aif_reg, aif_src; |
c7ebf932 | 2096 | unsigned long timeout; |
4b7ed83a | 2097 | bool was_enabled; |
9e6e96a1 | 2098 | |
9e6e96a1 MB |
2099 | switch (id) { |
2100 | case WM8994_FLL1: | |
2101 | reg_offset = 0; | |
2102 | id = 0; | |
e413ba88 | 2103 | aif_src = 0x10; |
9e6e96a1 MB |
2104 | break; |
2105 | case WM8994_FLL2: | |
2106 | reg_offset = 0x20; | |
2107 | id = 1; | |
e413ba88 | 2108 | aif_src = 0x18; |
9e6e96a1 MB |
2109 | break; |
2110 | default: | |
2111 | return -EINVAL; | |
2112 | } | |
2113 | ||
4b7ed83a MB |
2114 | reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset); |
2115 | was_enabled = reg & WM8994_FLL1_ENA; | |
2116 | ||
136ff2a2 | 2117 | switch (src) { |
7add84aa MB |
2118 | case 0: |
2119 | /* Allow no source specification when stopping */ | |
2120 | if (freq_out) | |
2121 | return -EINVAL; | |
4514e899 | 2122 | src = wm8994->fll[id].src; |
7add84aa | 2123 | break; |
136ff2a2 MB |
2124 | case WM8994_FLL_SRC_MCLK1: |
2125 | case WM8994_FLL_SRC_MCLK2: | |
2126 | case WM8994_FLL_SRC_LRCLK: | |
2127 | case WM8994_FLL_SRC_BCLK: | |
2128 | break; | |
fbfe6983 MB |
2129 | case WM8994_FLL_SRC_INTERNAL: |
2130 | freq_in = 12000000; | |
2131 | freq_out = 12000000; | |
2132 | break; | |
136ff2a2 MB |
2133 | default: |
2134 | return -EINVAL; | |
2135 | } | |
2136 | ||
9e6e96a1 MB |
2137 | /* Are we changing anything? */ |
2138 | if (wm8994->fll[id].src == src && | |
2139 | wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out) | |
2140 | return 0; | |
2141 | ||
2142 | /* If we're stopping the FLL redo the old config - no | |
2143 | * registers will actually be written but we avoid GCC flow | |
2144 | * analysis bugs spewing warnings. | |
2145 | */ | |
2146 | if (freq_out) | |
2147 | ret = wm8994_get_fll_config(&fll, freq_in, freq_out); | |
2148 | else | |
2149 | ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in, | |
2150 | wm8994->fll[id].out); | |
2151 | if (ret < 0) | |
2152 | return ret; | |
2153 | ||
e413ba88 MB |
2154 | /* Make sure that we're not providing SYSCLK right now */ |
2155 | clk1 = snd_soc_read(codec, WM8994_CLOCKING_1); | |
2156 | if (clk1 & WM8994_SYSCLK_SRC) | |
2157 | aif_reg = WM8994_AIF2_CLOCKING_1; | |
2158 | else | |
2159 | aif_reg = WM8994_AIF1_CLOCKING_1; | |
2160 | reg = snd_soc_read(codec, aif_reg); | |
2161 | ||
2162 | if ((reg & WM8994_AIF1CLK_ENA) && | |
2163 | (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) { | |
2164 | dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n", | |
2165 | id + 1); | |
2166 | return -EBUSY; | |
2167 | } | |
9e6e96a1 MB |
2168 | |
2169 | /* We always need to disable the FLL while reconfiguring */ | |
2170 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, | |
2171 | WM8994_FLL1_ENA, 0); | |
2172 | ||
20dc24a9 | 2173 | if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK && |
e05854dd | 2174 | freq_in == freq_out && freq_out) { |
20dc24a9 MB |
2175 | dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1); |
2176 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, | |
2177 | WM8958_FLL1_BYP, WM8958_FLL1_BYP); | |
2178 | goto out; | |
2179 | } | |
2180 | ||
9e6e96a1 MB |
2181 | reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) | |
2182 | (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT); | |
2183 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset, | |
2184 | WM8994_FLL1_OUTDIV_MASK | | |
2185 | WM8994_FLL1_FRATIO_MASK, reg); | |
2186 | ||
b16db745 MB |
2187 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset, |
2188 | WM8994_FLL1_K_MASK, fll.k); | |
9e6e96a1 MB |
2189 | |
2190 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset, | |
2191 | WM8994_FLL1_N_MASK, | |
7435d4ee | 2192 | fll.n << WM8994_FLL1_N_SHIFT); |
9e6e96a1 MB |
2193 | |
2194 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset, | |
fbfe6983 | 2195 | WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP | |
136ff2a2 MB |
2196 | WM8994_FLL1_REFCLK_DIV_MASK | |
2197 | WM8994_FLL1_REFCLK_SRC_MASK, | |
fbfe6983 MB |
2198 | ((src == WM8994_FLL_SRC_INTERNAL) |
2199 | << WM8994_FLL1_FRC_NCO_SHIFT) | | |
136ff2a2 MB |
2200 | (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) | |
2201 | (src - 1)); | |
9e6e96a1 | 2202 | |
f0f5039c MB |
2203 | /* Clear any pending completion from a previous failure */ |
2204 | try_wait_for_completion(&wm8994->fll_locked[id]); | |
2205 | ||
9e6e96a1 MB |
2206 | /* Enable (with fractional mode if required) */ |
2207 | if (freq_out) { | |
4b7ed83a MB |
2208 | /* Enable VMID if we need it */ |
2209 | if (!was_enabled) { | |
af6b6fe4 MB |
2210 | active_reference(codec); |
2211 | ||
4b7ed83a MB |
2212 | switch (control->type) { |
2213 | case WM8994: | |
2214 | vmid_reference(codec); | |
2215 | break; | |
2216 | case WM8958: | |
da445afe | 2217 | if (control->revision < 1) |
4b7ed83a MB |
2218 | vmid_reference(codec); |
2219 | break; | |
2220 | default: | |
2221 | break; | |
2222 | } | |
2223 | } | |
2224 | ||
fbfe6983 MB |
2225 | reg = WM8994_FLL1_ENA; |
2226 | ||
9e6e96a1 | 2227 | if (fll.k) |
fbfe6983 MB |
2228 | reg |= WM8994_FLL1_FRAC; |
2229 | if (src == WM8994_FLL_SRC_INTERNAL) | |
2230 | reg |= WM8994_FLL1_OSC_ENA; | |
2231 | ||
9e6e96a1 | 2232 | snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset, |
fbfe6983 MB |
2233 | WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA | |
2234 | WM8994_FLL1_FRAC, reg); | |
8e9ddf81 | 2235 | |
c7ebf932 MB |
2236 | if (wm8994->fll_locked_irq) { |
2237 | timeout = wait_for_completion_timeout(&wm8994->fll_locked[id], | |
2238 | msecs_to_jiffies(10)); | |
2239 | if (timeout == 0) | |
2240 | dev_warn(codec->dev, | |
2241 | "Timed out waiting for FLL lock\n"); | |
2242 | } else { | |
2243 | msleep(5); | |
2244 | } | |
4b7ed83a MB |
2245 | } else { |
2246 | if (was_enabled) { | |
2247 | switch (control->type) { | |
2248 | case WM8994: | |
2249 | vmid_dereference(codec); | |
2250 | break; | |
2251 | case WM8958: | |
da445afe | 2252 | if (control->revision < 1) |
4b7ed83a MB |
2253 | vmid_dereference(codec); |
2254 | break; | |
2255 | default: | |
2256 | break; | |
2257 | } | |
af6b6fe4 MB |
2258 | |
2259 | active_dereference(codec); | |
4b7ed83a | 2260 | } |
9e6e96a1 MB |
2261 | } |
2262 | ||
20dc24a9 | 2263 | out: |
9e6e96a1 MB |
2264 | wm8994->fll[id].in = freq_in; |
2265 | wm8994->fll[id].out = freq_out; | |
136ff2a2 | 2266 | wm8994->fll[id].src = src; |
9e6e96a1 | 2267 | |
9e6e96a1 MB |
2268 | configure_clock(codec); |
2269 | ||
cd22000a MB |
2270 | /* |
2271 | * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers | |
2272 | * for detection. | |
2273 | */ | |
2274 | if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { | |
2275 | dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); | |
d3725761 MB |
2276 | |
2277 | wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE) | |
2278 | & WM8994_AIF1CLK_RATE_MASK; | |
2279 | wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE) | |
2280 | & WM8994_AIF1CLK_RATE_MASK; | |
2281 | ||
cd22000a MB |
2282 | snd_soc_update_bits(codec, WM8994_AIF1_RATE, |
2283 | WM8994_AIF1CLK_RATE_MASK, 0x1); | |
2284 | snd_soc_update_bits(codec, WM8994_AIF2_RATE, | |
2285 | WM8994_AIF2CLK_RATE_MASK, 0x1); | |
d3725761 MB |
2286 | } else if (wm8994->aifdiv[0]) { |
2287 | snd_soc_update_bits(codec, WM8994_AIF1_RATE, | |
2288 | WM8994_AIF1CLK_RATE_MASK, | |
2289 | wm8994->aifdiv[0]); | |
2290 | snd_soc_update_bits(codec, WM8994_AIF2_RATE, | |
2291 | WM8994_AIF2CLK_RATE_MASK, | |
2292 | wm8994->aifdiv[1]); | |
2293 | ||
2294 | wm8994->aifdiv[0] = 0; | |
2295 | wm8994->aifdiv[1] = 0; | |
cd22000a MB |
2296 | } |
2297 | ||
9e6e96a1 MB |
2298 | return 0; |
2299 | } | |
2300 | ||
c7ebf932 MB |
2301 | static irqreturn_t wm8994_fll_locked_irq(int irq, void *data) |
2302 | { | |
2303 | struct completion *completion = data; | |
2304 | ||
2305 | complete(completion); | |
2306 | ||
2307 | return IRQ_HANDLED; | |
2308 | } | |
f0fba2ad | 2309 | |
66b47fdb MB |
2310 | static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 }; |
2311 | ||
f0fba2ad LG |
2312 | static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src, |
2313 | unsigned int freq_in, unsigned int freq_out) | |
2314 | { | |
2315 | return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out); | |
2316 | } | |
2317 | ||
9e6e96a1 MB |
2318 | static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai, |
2319 | int clk_id, unsigned int freq, int dir) | |
2320 | { | |
2321 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 2322 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
66b47fdb | 2323 | int i; |
9e6e96a1 MB |
2324 | |
2325 | switch (dai->id) { | |
2326 | case 1: | |
2327 | case 2: | |
2328 | break; | |
2329 | ||
2330 | default: | |
2331 | /* AIF3 shares clocking with AIF1/2 */ | |
2332 | return -EINVAL; | |
2333 | } | |
2334 | ||
2335 | switch (clk_id) { | |
2336 | case WM8994_SYSCLK_MCLK1: | |
2337 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1; | |
2338 | wm8994->mclk[0] = freq; | |
2339 | dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", | |
2340 | dai->id, freq); | |
2341 | break; | |
2342 | ||
2343 | case WM8994_SYSCLK_MCLK2: | |
2344 | /* TODO: Set GPIO AF */ | |
2345 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2; | |
2346 | wm8994->mclk[1] = freq; | |
2347 | dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", | |
2348 | dai->id, freq); | |
2349 | break; | |
2350 | ||
2351 | case WM8994_SYSCLK_FLL1: | |
2352 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1; | |
2353 | dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id); | |
2354 | break; | |
2355 | ||
2356 | case WM8994_SYSCLK_FLL2: | |
2357 | wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2; | |
2358 | dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id); | |
2359 | break; | |
2360 | ||
66b47fdb MB |
2361 | case WM8994_SYSCLK_OPCLK: |
2362 | /* Special case - a division (times 10) is given and | |
c1a4ecd9 | 2363 | * no effect on main clocking. |
66b47fdb MB |
2364 | */ |
2365 | if (freq) { | |
2366 | for (i = 0; i < ARRAY_SIZE(opclk_divs); i++) | |
2367 | if (opclk_divs[i] == freq) | |
2368 | break; | |
2369 | if (i == ARRAY_SIZE(opclk_divs)) | |
2370 | return -EINVAL; | |
2371 | snd_soc_update_bits(codec, WM8994_CLOCKING_2, | |
2372 | WM8994_OPCLK_DIV_MASK, i); | |
2373 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, | |
2374 | WM8994_OPCLK_ENA, WM8994_OPCLK_ENA); | |
2375 | } else { | |
2376 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2, | |
2377 | WM8994_OPCLK_ENA, 0); | |
2378 | } | |
2379 | ||
9e6e96a1 MB |
2380 | default: |
2381 | return -EINVAL; | |
2382 | } | |
2383 | ||
2384 | configure_clock(codec); | |
2385 | ||
6730049a MB |
2386 | /* |
2387 | * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers | |
2388 | * for detection. | |
2389 | */ | |
2390 | if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) { | |
2391 | dev_dbg(codec->dev, "Configuring AIFs for 128fs\n"); | |
d3725761 MB |
2392 | |
2393 | wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE) | |
2394 | & WM8994_AIF1CLK_RATE_MASK; | |
2395 | wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE) | |
2396 | & WM8994_AIF1CLK_RATE_MASK; | |
2397 | ||
6730049a MB |
2398 | snd_soc_update_bits(codec, WM8994_AIF1_RATE, |
2399 | WM8994_AIF1CLK_RATE_MASK, 0x1); | |
2400 | snd_soc_update_bits(codec, WM8994_AIF2_RATE, | |
2401 | WM8994_AIF2CLK_RATE_MASK, 0x1); | |
d3725761 MB |
2402 | } else if (wm8994->aifdiv[0]) { |
2403 | snd_soc_update_bits(codec, WM8994_AIF1_RATE, | |
2404 | WM8994_AIF1CLK_RATE_MASK, | |
2405 | wm8994->aifdiv[0]); | |
2406 | snd_soc_update_bits(codec, WM8994_AIF2_RATE, | |
2407 | WM8994_AIF2CLK_RATE_MASK, | |
2408 | wm8994->aifdiv[1]); | |
2409 | ||
2410 | wm8994->aifdiv[0] = 0; | |
2411 | wm8994->aifdiv[1] = 0; | |
6730049a MB |
2412 | } |
2413 | ||
9e6e96a1 MB |
2414 | return 0; |
2415 | } | |
2416 | ||
2417 | static int wm8994_set_bias_level(struct snd_soc_codec *codec, | |
2418 | enum snd_soc_bias_level level) | |
2419 | { | |
b6b05691 | 2420 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
2a8a856d | 2421 | struct wm8994 *control = wm8994->wm8994; |
b6b05691 | 2422 | |
5f2f3890 MB |
2423 | wm_hubs_set_bias_level(codec, level); |
2424 | ||
9e6e96a1 MB |
2425 | switch (level) { |
2426 | case SND_SOC_BIAS_ON: | |
2427 | break; | |
2428 | ||
2429 | case SND_SOC_BIAS_PREPARE: | |
500fa30e MB |
2430 | /* MICBIAS into regulating mode */ |
2431 | switch (control->type) { | |
2432 | case WM8958: | |
2433 | case WM1811: | |
2434 | snd_soc_update_bits(codec, WM8958_MICBIAS1, | |
2435 | WM8958_MICB1_MODE, 0); | |
2436 | snd_soc_update_bits(codec, WM8958_MICBIAS2, | |
2437 | WM8958_MICB2_MODE, 0); | |
2438 | break; | |
2439 | default: | |
2440 | break; | |
2441 | } | |
af6b6fe4 MB |
2442 | |
2443 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) | |
2444 | active_reference(codec); | |
9e6e96a1 MB |
2445 | break; |
2446 | ||
2447 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 2448 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
8bc3c2c2 | 2449 | switch (control->type) { |
8bc3c2c2 | 2450 | case WM8958: |
da445afe | 2451 | if (control->revision == 0) { |
8bc3c2c2 | 2452 | /* Optimise performance for rev A */ |
8bc3c2c2 MB |
2453 | snd_soc_update_bits(codec, |
2454 | WM8958_CHARGE_PUMP_2, | |
2455 | WM8958_CP_DISCH, | |
2456 | WM8958_CP_DISCH); | |
2457 | } | |
2458 | break; | |
81204c84 | 2459 | |
462835e4 | 2460 | default: |
81204c84 | 2461 | break; |
b6b05691 | 2462 | } |
9e6e96a1 MB |
2463 | |
2464 | /* Discharge LINEOUT1 & 2 */ | |
2465 | snd_soc_update_bits(codec, WM8994_ANTIPOP_1, | |
2466 | WM8994_LINEOUT1_DISCH | | |
2467 | WM8994_LINEOUT2_DISCH, | |
2468 | WM8994_LINEOUT1_DISCH | | |
2469 | WM8994_LINEOUT2_DISCH); | |
9e6e96a1 MB |
2470 | } |
2471 | ||
af6b6fe4 MB |
2472 | if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) |
2473 | active_dereference(codec); | |
2474 | ||
500fa30e MB |
2475 | /* MICBIAS into bypass mode on newer devices */ |
2476 | switch (control->type) { | |
2477 | case WM8958: | |
2478 | case WM1811: | |
2479 | snd_soc_update_bits(codec, WM8958_MICBIAS1, | |
2480 | WM8958_MICB1_MODE, | |
2481 | WM8958_MICB1_MODE); | |
2482 | snd_soc_update_bits(codec, WM8958_MICBIAS2, | |
2483 | WM8958_MICB2_MODE, | |
2484 | WM8958_MICB2_MODE); | |
2485 | break; | |
2486 | default: | |
2487 | break; | |
2488 | } | |
9e6e96a1 MB |
2489 | break; |
2490 | ||
2491 | case SND_SOC_BIAS_OFF: | |
4105ab84 | 2492 | if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) |
fbbf5920 | 2493 | wm8994->cur_fw = NULL; |
9e6e96a1 MB |
2494 | break; |
2495 | } | |
5f2f3890 | 2496 | |
ce6120cc | 2497 | codec->dapm.bias_level = level; |
af6b6fe4 | 2498 | |
22f8d055 MB |
2499 | return 0; |
2500 | } | |
2501 | ||
2502 | int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode) | |
2503 | { | |
2504 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
2505 | ||
2506 | switch (mode) { | |
2507 | case WM8994_VMID_NORMAL: | |
2508 | if (wm8994->hubs.lineout1_se) { | |
2509 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2510 | "LINEOUT1N Driver"); | |
2511 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2512 | "LINEOUT1P Driver"); | |
2513 | } | |
2514 | if (wm8994->hubs.lineout2_se) { | |
2515 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2516 | "LINEOUT2N Driver"); | |
2517 | snd_soc_dapm_disable_pin(&codec->dapm, | |
2518 | "LINEOUT2P Driver"); | |
2519 | } | |
2520 | ||
2521 | /* Do the sync with the old mode to allow it to clean up */ | |
2522 | snd_soc_dapm_sync(&codec->dapm); | |
2523 | wm8994->vmid_mode = mode; | |
2524 | break; | |
2525 | ||
2526 | case WM8994_VMID_FORCE: | |
2527 | if (wm8994->hubs.lineout1_se) { | |
2528 | snd_soc_dapm_force_enable_pin(&codec->dapm, | |
2529 | "LINEOUT1N Driver"); | |
2530 | snd_soc_dapm_force_enable_pin(&codec->dapm, | |
2531 | "LINEOUT1P Driver"); | |
2532 | } | |
2533 | if (wm8994->hubs.lineout2_se) { | |
2534 | snd_soc_dapm_force_enable_pin(&codec->dapm, | |
2535 | "LINEOUT2N Driver"); | |
2536 | snd_soc_dapm_force_enable_pin(&codec->dapm, | |
2537 | "LINEOUT2P Driver"); | |
2538 | } | |
2539 | ||
2540 | wm8994->vmid_mode = mode; | |
2541 | snd_soc_dapm_sync(&codec->dapm); | |
2542 | break; | |
2543 | ||
2544 | default: | |
2545 | return -EINVAL; | |
2546 | } | |
2547 | ||
9e6e96a1 MB |
2548 | return 0; |
2549 | } | |
2550 | ||
2551 | static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
2552 | { | |
2553 | struct snd_soc_codec *codec = dai->codec; | |
2a8a856d MB |
2554 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
2555 | struct wm8994 *control = wm8994->wm8994; | |
9e6e96a1 MB |
2556 | int ms_reg; |
2557 | int aif1_reg; | |
2558 | int ms = 0; | |
2559 | int aif1 = 0; | |
2560 | ||
2561 | switch (dai->id) { | |
2562 | case 1: | |
2563 | ms_reg = WM8994_AIF1_MASTER_SLAVE; | |
2564 | aif1_reg = WM8994_AIF1_CONTROL_1; | |
2565 | break; | |
2566 | case 2: | |
2567 | ms_reg = WM8994_AIF2_MASTER_SLAVE; | |
2568 | aif1_reg = WM8994_AIF2_CONTROL_1; | |
2569 | break; | |
2570 | default: | |
2571 | return -EINVAL; | |
2572 | } | |
2573 | ||
2574 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
2575 | case SND_SOC_DAIFMT_CBS_CFS: | |
2576 | break; | |
2577 | case SND_SOC_DAIFMT_CBM_CFM: | |
2578 | ms = WM8994_AIF1_MSTR; | |
2579 | break; | |
2580 | default: | |
2581 | return -EINVAL; | |
2582 | } | |
2583 | ||
2584 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
2585 | case SND_SOC_DAIFMT_DSP_B: | |
2586 | aif1 |= WM8994_AIF1_LRCLK_INV; | |
2587 | case SND_SOC_DAIFMT_DSP_A: | |
2588 | aif1 |= 0x18; | |
2589 | break; | |
2590 | case SND_SOC_DAIFMT_I2S: | |
2591 | aif1 |= 0x10; | |
2592 | break; | |
2593 | case SND_SOC_DAIFMT_RIGHT_J: | |
2594 | break; | |
2595 | case SND_SOC_DAIFMT_LEFT_J: | |
2596 | aif1 |= 0x8; | |
2597 | break; | |
2598 | default: | |
2599 | return -EINVAL; | |
2600 | } | |
2601 | ||
2602 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
2603 | case SND_SOC_DAIFMT_DSP_A: | |
2604 | case SND_SOC_DAIFMT_DSP_B: | |
2605 | /* frame inversion not valid for DSP modes */ | |
2606 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2607 | case SND_SOC_DAIFMT_NB_NF: | |
2608 | break; | |
2609 | case SND_SOC_DAIFMT_IB_NF: | |
2610 | aif1 |= WM8994_AIF1_BCLK_INV; | |
2611 | break; | |
2612 | default: | |
2613 | return -EINVAL; | |
2614 | } | |
2615 | break; | |
2616 | ||
2617 | case SND_SOC_DAIFMT_I2S: | |
2618 | case SND_SOC_DAIFMT_RIGHT_J: | |
2619 | case SND_SOC_DAIFMT_LEFT_J: | |
2620 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
2621 | case SND_SOC_DAIFMT_NB_NF: | |
2622 | break; | |
2623 | case SND_SOC_DAIFMT_IB_IF: | |
2624 | aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV; | |
2625 | break; | |
2626 | case SND_SOC_DAIFMT_IB_NF: | |
2627 | aif1 |= WM8994_AIF1_BCLK_INV; | |
2628 | break; | |
2629 | case SND_SOC_DAIFMT_NB_IF: | |
2630 | aif1 |= WM8994_AIF1_LRCLK_INV; | |
2631 | break; | |
2632 | default: | |
2633 | return -EINVAL; | |
2634 | } | |
2635 | break; | |
2636 | default: | |
2637 | return -EINVAL; | |
2638 | } | |
2639 | ||
c4431df0 MB |
2640 | /* The AIF2 format configuration needs to be mirrored to AIF3 |
2641 | * on WM8958 if it's in use so just do it all the time. */ | |
81204c84 MB |
2642 | switch (control->type) { |
2643 | case WM1811: | |
2644 | case WM8958: | |
2645 | if (dai->id == 2) | |
2646 | snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1, | |
2647 | WM8994_AIF1_LRCLK_INV | | |
2648 | WM8958_AIF3_FMT_MASK, aif1); | |
2649 | break; | |
2650 | ||
2651 | default: | |
2652 | break; | |
2653 | } | |
c4431df0 | 2654 | |
9e6e96a1 MB |
2655 | snd_soc_update_bits(codec, aif1_reg, |
2656 | WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV | | |
2657 | WM8994_AIF1_FMT_MASK, | |
2658 | aif1); | |
2659 | snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR, | |
2660 | ms); | |
2661 | ||
2662 | return 0; | |
2663 | } | |
2664 | ||
2665 | static struct { | |
2666 | int val, rate; | |
2667 | } srs[] = { | |
2668 | { 0, 8000 }, | |
2669 | { 1, 11025 }, | |
2670 | { 2, 12000 }, | |
2671 | { 3, 16000 }, | |
2672 | { 4, 22050 }, | |
2673 | { 5, 24000 }, | |
2674 | { 6, 32000 }, | |
2675 | { 7, 44100 }, | |
2676 | { 8, 48000 }, | |
2677 | { 9, 88200 }, | |
2678 | { 10, 96000 }, | |
2679 | }; | |
2680 | ||
2681 | static int fs_ratios[] = { | |
2682 | 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536 | |
2683 | }; | |
2684 | ||
2685 | static int bclk_divs[] = { | |
2686 | 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480, | |
2687 | 640, 880, 960, 1280, 1760, 1920 | |
2688 | }; | |
2689 | ||
2690 | static int wm8994_hw_params(struct snd_pcm_substream *substream, | |
2691 | struct snd_pcm_hw_params *params, | |
2692 | struct snd_soc_dai *dai) | |
2693 | { | |
2694 | struct snd_soc_codec *codec = dai->codec; | |
b2c812e2 | 2695 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
3cf956ee MB |
2696 | struct wm8994 *control = wm8994->wm8994; |
2697 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 | 2698 | int aif1_reg; |
b1e43d93 | 2699 | int aif2_reg; |
9e6e96a1 MB |
2700 | int bclk_reg; |
2701 | int lrclk_reg; | |
2702 | int rate_reg; | |
2703 | int aif1 = 0; | |
b1e43d93 | 2704 | int aif2 = 0; |
9e6e96a1 MB |
2705 | int bclk = 0; |
2706 | int lrclk = 0; | |
2707 | int rate_val = 0; | |
2708 | int id = dai->id - 1; | |
2709 | ||
2710 | int i, cur_val, best_val, bclk_rate, best; | |
2711 | ||
2712 | switch (dai->id) { | |
2713 | case 1: | |
2714 | aif1_reg = WM8994_AIF1_CONTROL_1; | |
b1e43d93 | 2715 | aif2_reg = WM8994_AIF1_CONTROL_2; |
9e6e96a1 MB |
2716 | bclk_reg = WM8994_AIF1_BCLK; |
2717 | rate_reg = WM8994_AIF1_RATE; | |
2718 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
7d83d213 | 2719 | wm8994->lrclk_shared[0]) { |
9e6e96a1 | 2720 | lrclk_reg = WM8994_AIF1DAC_LRCLK; |
7d83d213 | 2721 | } else { |
9e6e96a1 | 2722 | lrclk_reg = WM8994_AIF1ADC_LRCLK; |
7d83d213 MB |
2723 | dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); |
2724 | } | |
9e6e96a1 MB |
2725 | break; |
2726 | case 2: | |
2727 | aif1_reg = WM8994_AIF2_CONTROL_1; | |
b1e43d93 | 2728 | aif2_reg = WM8994_AIF2_CONTROL_2; |
9e6e96a1 MB |
2729 | bclk_reg = WM8994_AIF2_BCLK; |
2730 | rate_reg = WM8994_AIF2_RATE; | |
2731 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || | |
7d83d213 | 2732 | wm8994->lrclk_shared[1]) { |
9e6e96a1 | 2733 | lrclk_reg = WM8994_AIF2DAC_LRCLK; |
7d83d213 | 2734 | } else { |
9e6e96a1 | 2735 | lrclk_reg = WM8994_AIF2ADC_LRCLK; |
7d83d213 MB |
2736 | dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); |
2737 | } | |
9e6e96a1 MB |
2738 | break; |
2739 | default: | |
2740 | return -EINVAL; | |
2741 | } | |
2742 | ||
79748cdb | 2743 | bclk_rate = params_rate(params); |
9e6e96a1 MB |
2744 | switch (params_format(params)) { |
2745 | case SNDRV_PCM_FORMAT_S16_LE: | |
2746 | bclk_rate *= 16; | |
2747 | break; | |
2748 | case SNDRV_PCM_FORMAT_S20_3LE: | |
2749 | bclk_rate *= 20; | |
2750 | aif1 |= 0x20; | |
2751 | break; | |
2752 | case SNDRV_PCM_FORMAT_S24_LE: | |
2753 | bclk_rate *= 24; | |
2754 | aif1 |= 0x40; | |
2755 | break; | |
2756 | case SNDRV_PCM_FORMAT_S32_LE: | |
2757 | bclk_rate *= 32; | |
2758 | aif1 |= 0x60; | |
2759 | break; | |
2760 | default: | |
2761 | return -EINVAL; | |
2762 | } | |
2763 | ||
79748cdb | 2764 | wm8994->channels[id] = params_channels(params); |
3cf956ee MB |
2765 | if (pdata->max_channels_clocked[id] && |
2766 | wm8994->channels[id] > pdata->max_channels_clocked[id]) { | |
2767 | dev_dbg(dai->dev, "Constraining channels to %d from %d\n", | |
2768 | pdata->max_channels_clocked[id], wm8994->channels[id]); | |
2769 | wm8994->channels[id] = pdata->max_channels_clocked[id]; | |
2770 | } | |
2771 | ||
2772 | switch (wm8994->channels[id]) { | |
79748cdb MB |
2773 | case 1: |
2774 | case 2: | |
2775 | bclk_rate *= 2; | |
2776 | break; | |
2777 | default: | |
2778 | bclk_rate *= 4; | |
2779 | break; | |
2780 | } | |
2781 | ||
9e6e96a1 MB |
2782 | /* Try to find an appropriate sample rate; look for an exact match. */ |
2783 | for (i = 0; i < ARRAY_SIZE(srs); i++) | |
2784 | if (srs[i].rate == params_rate(params)) | |
2785 | break; | |
2786 | if (i == ARRAY_SIZE(srs)) | |
2787 | return -EINVAL; | |
2788 | rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT; | |
2789 | ||
2790 | dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate); | |
2791 | dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", | |
2792 | dai->id, wm8994->aifclk[id], bclk_rate); | |
2793 | ||
3cf956ee | 2794 | if (wm8994->channels[id] == 1 && |
b1e43d93 MB |
2795 | (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18) |
2796 | aif2 |= WM8994_AIF1_MONO; | |
2797 | ||
9e6e96a1 MB |
2798 | if (wm8994->aifclk[id] == 0) { |
2799 | dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id); | |
2800 | return -EINVAL; | |
2801 | } | |
2802 | ||
2803 | /* AIFCLK/fs ratio; look for a close match in either direction */ | |
2804 | best = 0; | |
2805 | best_val = abs((fs_ratios[0] * params_rate(params)) | |
2806 | - wm8994->aifclk[id]); | |
2807 | for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) { | |
2808 | cur_val = abs((fs_ratios[i] * params_rate(params)) | |
2809 | - wm8994->aifclk[id]); | |
2810 | if (cur_val >= best_val) | |
2811 | continue; | |
2812 | best = i; | |
2813 | best_val = cur_val; | |
2814 | } | |
2815 | dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", | |
2816 | dai->id, fs_ratios[best]); | |
2817 | rate_val |= best; | |
2818 | ||
2819 | /* We may not get quite the right frequency if using | |
2820 | * approximate clocks so look for the closest match that is | |
2821 | * higher than the target (we need to ensure that there enough | |
2822 | * BCLKs to clock out the samples). | |
2823 | */ | |
2824 | best = 0; | |
2825 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
07cd8ada | 2826 | cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate; |
9e6e96a1 MB |
2827 | if (cur_val < 0) /* BCLK table is sorted */ |
2828 | break; | |
2829 | best = i; | |
2830 | } | |
07cd8ada | 2831 | bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best]; |
9e6e96a1 MB |
2832 | dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", |
2833 | bclk_divs[best], bclk_rate); | |
2834 | bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT; | |
2835 | ||
2836 | lrclk = bclk_rate / params_rate(params); | |
fc07ecd8 MB |
2837 | if (!lrclk) { |
2838 | dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", | |
2839 | bclk_rate); | |
2840 | return -EINVAL; | |
2841 | } | |
9e6e96a1 MB |
2842 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", |
2843 | lrclk, bclk_rate / lrclk); | |
2844 | ||
2845 | snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); | |
b1e43d93 | 2846 | snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2); |
9e6e96a1 MB |
2847 | snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk); |
2848 | snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK, | |
2849 | lrclk); | |
2850 | snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK | | |
2851 | WM8994_AIF1CLK_RATE_MASK, rate_val); | |
2852 | ||
2853 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | |
2854 | switch (dai->id) { | |
2855 | case 1: | |
2856 | wm8994->dac_rates[0] = params_rate(params); | |
2857 | wm8994_set_retune_mobile(codec, 0); | |
2858 | wm8994_set_retune_mobile(codec, 1); | |
2859 | break; | |
2860 | case 2: | |
2861 | wm8994->dac_rates[1] = params_rate(params); | |
2862 | wm8994_set_retune_mobile(codec, 2); | |
2863 | break; | |
2864 | } | |
2865 | } | |
2866 | ||
2867 | return 0; | |
2868 | } | |
2869 | ||
c4431df0 MB |
2870 | static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream, |
2871 | struct snd_pcm_hw_params *params, | |
2872 | struct snd_soc_dai *dai) | |
2873 | { | |
2874 | struct snd_soc_codec *codec = dai->codec; | |
2a8a856d MB |
2875 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
2876 | struct wm8994 *control = wm8994->wm8994; | |
c4431df0 MB |
2877 | int aif1_reg; |
2878 | int aif1 = 0; | |
2879 | ||
2880 | switch (dai->id) { | |
2881 | case 3: | |
2882 | switch (control->type) { | |
81204c84 | 2883 | case WM1811: |
c4431df0 MB |
2884 | case WM8958: |
2885 | aif1_reg = WM8958_AIF3_CONTROL_1; | |
2886 | break; | |
2887 | default: | |
2888 | return 0; | |
2889 | } | |
4495e46f | 2890 | break; |
c4431df0 MB |
2891 | default: |
2892 | return 0; | |
2893 | } | |
2894 | ||
2895 | switch (params_format(params)) { | |
2896 | case SNDRV_PCM_FORMAT_S16_LE: | |
2897 | break; | |
2898 | case SNDRV_PCM_FORMAT_S20_3LE: | |
2899 | aif1 |= 0x20; | |
2900 | break; | |
2901 | case SNDRV_PCM_FORMAT_S24_LE: | |
2902 | aif1 |= 0x40; | |
2903 | break; | |
2904 | case SNDRV_PCM_FORMAT_S32_LE: | |
2905 | aif1 |= 0x60; | |
2906 | break; | |
2907 | default: | |
2908 | return -EINVAL; | |
2909 | } | |
2910 | ||
2911 | return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1); | |
2912 | } | |
2913 | ||
9e6e96a1 MB |
2914 | static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute) |
2915 | { | |
2916 | struct snd_soc_codec *codec = codec_dai->codec; | |
2917 | int mute_reg; | |
2918 | int reg; | |
2919 | ||
2920 | switch (codec_dai->id) { | |
2921 | case 1: | |
2922 | mute_reg = WM8994_AIF1_DAC1_FILTERS_1; | |
2923 | break; | |
2924 | case 2: | |
2925 | mute_reg = WM8994_AIF2_DAC_FILTERS_1; | |
2926 | break; | |
2927 | default: | |
2928 | return -EINVAL; | |
2929 | } | |
2930 | ||
2931 | if (mute) | |
2932 | reg = WM8994_AIF1DAC1_MUTE; | |
2933 | else | |
2934 | reg = 0; | |
2935 | ||
2936 | snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg); | |
2937 | ||
2938 | return 0; | |
2939 | } | |
2940 | ||
778a76e2 MB |
2941 | static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate) |
2942 | { | |
2943 | struct snd_soc_codec *codec = codec_dai->codec; | |
2944 | int reg, val, mask; | |
2945 | ||
2946 | switch (codec_dai->id) { | |
2947 | case 1: | |
2948 | reg = WM8994_AIF1_MASTER_SLAVE; | |
2949 | mask = WM8994_AIF1_TRI; | |
2950 | break; | |
2951 | case 2: | |
2952 | reg = WM8994_AIF2_MASTER_SLAVE; | |
2953 | mask = WM8994_AIF2_TRI; | |
2954 | break; | |
778a76e2 MB |
2955 | default: |
2956 | return -EINVAL; | |
2957 | } | |
2958 | ||
2959 | if (tristate) | |
2960 | val = mask; | |
2961 | else | |
2962 | val = 0; | |
2963 | ||
78b3fb46 | 2964 | return snd_soc_update_bits(codec, reg, mask, val); |
778a76e2 MB |
2965 | } |
2966 | ||
d09f3ecf MB |
2967 | static int wm8994_aif2_probe(struct snd_soc_dai *dai) |
2968 | { | |
2969 | struct snd_soc_codec *codec = dai->codec; | |
2970 | ||
2971 | /* Disable the pulls on the AIF if we're using it to save power. */ | |
2972 | snd_soc_update_bits(codec, WM8994_GPIO_3, | |
2973 | WM8994_GPN_PU | WM8994_GPN_PD, 0); | |
2974 | snd_soc_update_bits(codec, WM8994_GPIO_4, | |
2975 | WM8994_GPN_PU | WM8994_GPN_PD, 0); | |
2976 | snd_soc_update_bits(codec, WM8994_GPIO_5, | |
2977 | WM8994_GPN_PU | WM8994_GPN_PD, 0); | |
2978 | ||
2979 | return 0; | |
2980 | } | |
2981 | ||
9e6e96a1 MB |
2982 | #define WM8994_RATES SNDRV_PCM_RATE_8000_96000 |
2983 | ||
2984 | #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
3079aed5 | 2985 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) |
9e6e96a1 | 2986 | |
85e7652d | 2987 | static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = { |
9e6e96a1 MB |
2988 | .set_sysclk = wm8994_set_dai_sysclk, |
2989 | .set_fmt = wm8994_set_dai_fmt, | |
2990 | .hw_params = wm8994_hw_params, | |
2991 | .digital_mute = wm8994_aif_mute, | |
2992 | .set_pll = wm8994_set_fll, | |
778a76e2 | 2993 | .set_tristate = wm8994_set_tristate, |
9e6e96a1 MB |
2994 | }; |
2995 | ||
85e7652d | 2996 | static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = { |
9e6e96a1 MB |
2997 | .set_sysclk = wm8994_set_dai_sysclk, |
2998 | .set_fmt = wm8994_set_dai_fmt, | |
2999 | .hw_params = wm8994_hw_params, | |
3000 | .digital_mute = wm8994_aif_mute, | |
3001 | .set_pll = wm8994_set_fll, | |
778a76e2 MB |
3002 | .set_tristate = wm8994_set_tristate, |
3003 | }; | |
3004 | ||
85e7652d | 3005 | static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = { |
c4431df0 | 3006 | .hw_params = wm8994_aif3_hw_params, |
9e6e96a1 MB |
3007 | }; |
3008 | ||
f0fba2ad | 3009 | static struct snd_soc_dai_driver wm8994_dai[] = { |
9e6e96a1 | 3010 | { |
f0fba2ad | 3011 | .name = "wm8994-aif1", |
8c7f78b3 | 3012 | .id = 1, |
9e6e96a1 MB |
3013 | .playback = { |
3014 | .stream_name = "AIF1 Playback", | |
b1e43d93 | 3015 | .channels_min = 1, |
9e6e96a1 MB |
3016 | .channels_max = 2, |
3017 | .rates = WM8994_RATES, | |
3018 | .formats = WM8994_FORMATS, | |
99b0292d | 3019 | .sig_bits = 24, |
9e6e96a1 MB |
3020 | }, |
3021 | .capture = { | |
3022 | .stream_name = "AIF1 Capture", | |
b1e43d93 | 3023 | .channels_min = 1, |
9e6e96a1 MB |
3024 | .channels_max = 2, |
3025 | .rates = WM8994_RATES, | |
3026 | .formats = WM8994_FORMATS, | |
99b0292d | 3027 | .sig_bits = 24, |
9e6e96a1 MB |
3028 | }, |
3029 | .ops = &wm8994_aif1_dai_ops, | |
3030 | }, | |
3031 | { | |
f0fba2ad | 3032 | .name = "wm8994-aif2", |
8c7f78b3 | 3033 | .id = 2, |
9e6e96a1 MB |
3034 | .playback = { |
3035 | .stream_name = "AIF2 Playback", | |
b1e43d93 | 3036 | .channels_min = 1, |
9e6e96a1 MB |
3037 | .channels_max = 2, |
3038 | .rates = WM8994_RATES, | |
3039 | .formats = WM8994_FORMATS, | |
99b0292d | 3040 | .sig_bits = 24, |
9e6e96a1 MB |
3041 | }, |
3042 | .capture = { | |
3043 | .stream_name = "AIF2 Capture", | |
b1e43d93 | 3044 | .channels_min = 1, |
9e6e96a1 MB |
3045 | .channels_max = 2, |
3046 | .rates = WM8994_RATES, | |
3047 | .formats = WM8994_FORMATS, | |
99b0292d | 3048 | .sig_bits = 24, |
9e6e96a1 | 3049 | }, |
d09f3ecf | 3050 | .probe = wm8994_aif2_probe, |
9e6e96a1 MB |
3051 | .ops = &wm8994_aif2_dai_ops, |
3052 | }, | |
3053 | { | |
f0fba2ad | 3054 | .name = "wm8994-aif3", |
8c7f78b3 | 3055 | .id = 3, |
9e6e96a1 MB |
3056 | .playback = { |
3057 | .stream_name = "AIF3 Playback", | |
b1e43d93 | 3058 | .channels_min = 1, |
9e6e96a1 MB |
3059 | .channels_max = 2, |
3060 | .rates = WM8994_RATES, | |
3061 | .formats = WM8994_FORMATS, | |
99b0292d | 3062 | .sig_bits = 24, |
9e6e96a1 | 3063 | }, |
a8462bde | 3064 | .capture = { |
9e6e96a1 | 3065 | .stream_name = "AIF3 Capture", |
b1e43d93 | 3066 | .channels_min = 1, |
9e6e96a1 MB |
3067 | .channels_max = 2, |
3068 | .rates = WM8994_RATES, | |
3069 | .formats = WM8994_FORMATS, | |
99b0292d MB |
3070 | .sig_bits = 24, |
3071 | }, | |
778a76e2 | 3072 | .ops = &wm8994_aif3_dai_ops, |
9e6e96a1 MB |
3073 | } |
3074 | }; | |
9e6e96a1 MB |
3075 | |
3076 | #ifdef CONFIG_PM | |
4752a887 | 3077 | static int wm8994_codec_suspend(struct snd_soc_codec *codec) |
9e6e96a1 | 3078 | { |
b2c812e2 | 3079 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
9e6e96a1 MB |
3080 | int i, ret; |
3081 | ||
3082 | for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { | |
3083 | memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i], | |
f701a2e5 | 3084 | sizeof(struct wm8994_fll_config)); |
f0fba2ad | 3085 | ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0); |
9e6e96a1 MB |
3086 | if (ret < 0) |
3087 | dev_warn(codec->dev, "Failed to stop FLL%d: %d\n", | |
3088 | i + 1, ret); | |
3089 | } | |
3090 | ||
3091 | wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
3092 | ||
3093 | return 0; | |
3094 | } | |
3095 | ||
4752a887 | 3096 | static int wm8994_codec_resume(struct snd_soc_codec *codec) |
9e6e96a1 | 3097 | { |
b2c812e2 | 3098 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
2a8a856d | 3099 | struct wm8994 *control = wm8994->wm8994; |
9e6e96a1 | 3100 | int i, ret; |
c52fd021 DP |
3101 | unsigned int val, mask; |
3102 | ||
da445afe | 3103 | if (control->revision < 4) { |
c52fd021 | 3104 | /* force a HW read */ |
d9a7666f MB |
3105 | ret = regmap_read(control->regmap, |
3106 | WM8994_POWER_MANAGEMENT_5, &val); | |
c52fd021 DP |
3107 | |
3108 | /* modify the cache only */ | |
3109 | codec->cache_only = 1; | |
3110 | mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA | | |
3111 | WM8994_DAC2R_ENA | WM8994_DAC2L_ENA; | |
3112 | val &= mask; | |
3113 | snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, | |
3114 | mask, val); | |
3115 | codec->cache_only = 0; | |
3116 | } | |
9e6e96a1 | 3117 | |
9e6e96a1 | 3118 | for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) { |
6a2f1ee1 MB |
3119 | if (!wm8994->fll_suspend[i].out) |
3120 | continue; | |
3121 | ||
f0fba2ad | 3122 | ret = _wm8994_set_fll(codec, i + 1, |
9e6e96a1 MB |
3123 | wm8994->fll_suspend[i].src, |
3124 | wm8994->fll_suspend[i].in, | |
3125 | wm8994->fll_suspend[i].out); | |
3126 | if (ret < 0) | |
3127 | dev_warn(codec->dev, "Failed to restore FLL%d: %d\n", | |
3128 | i + 1, ret); | |
3129 | } | |
3130 | ||
3131 | return 0; | |
3132 | } | |
3133 | #else | |
4752a887 MB |
3134 | #define wm8994_codec_suspend NULL |
3135 | #define wm8994_codec_resume NULL | |
9e6e96a1 MB |
3136 | #endif |
3137 | ||
3138 | static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994) | |
3139 | { | |
8cb8e83b | 3140 | struct snd_soc_codec *codec = wm8994->hubs.codec; |
d9dd4ada MB |
3141 | struct wm8994 *control = wm8994->wm8994; |
3142 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 MB |
3143 | struct snd_kcontrol_new controls[] = { |
3144 | SOC_ENUM_EXT("AIF1.1 EQ Mode", | |
3145 | wm8994->retune_mobile_enum, | |
3146 | wm8994_get_retune_mobile_enum, | |
3147 | wm8994_put_retune_mobile_enum), | |
3148 | SOC_ENUM_EXT("AIF1.2 EQ Mode", | |
3149 | wm8994->retune_mobile_enum, | |
3150 | wm8994_get_retune_mobile_enum, | |
3151 | wm8994_put_retune_mobile_enum), | |
3152 | SOC_ENUM_EXT("AIF2 EQ Mode", | |
3153 | wm8994->retune_mobile_enum, | |
3154 | wm8994_get_retune_mobile_enum, | |
3155 | wm8994_put_retune_mobile_enum), | |
3156 | }; | |
3157 | int ret, i, j; | |
3158 | const char **t; | |
3159 | ||
3160 | /* We need an array of texts for the enum API but the number | |
3161 | * of texts is likely to be less than the number of | |
3162 | * configurations due to the sample rate dependency of the | |
3163 | * configurations. */ | |
3164 | wm8994->num_retune_mobile_texts = 0; | |
3165 | wm8994->retune_mobile_texts = NULL; | |
3166 | for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) { | |
3167 | for (j = 0; j < wm8994->num_retune_mobile_texts; j++) { | |
3168 | if (strcmp(pdata->retune_mobile_cfgs[i].name, | |
3169 | wm8994->retune_mobile_texts[j]) == 0) | |
3170 | break; | |
3171 | } | |
3172 | ||
3173 | if (j != wm8994->num_retune_mobile_texts) | |
3174 | continue; | |
3175 | ||
3176 | /* Expand the array... */ | |
3177 | t = krealloc(wm8994->retune_mobile_texts, | |
c1a4ecd9 | 3178 | sizeof(char *) * |
9e6e96a1 MB |
3179 | (wm8994->num_retune_mobile_texts + 1), |
3180 | GFP_KERNEL); | |
3181 | if (t == NULL) | |
3182 | continue; | |
3183 | ||
3184 | /* ...store the new entry... */ | |
c1a4ecd9 | 3185 | t[wm8994->num_retune_mobile_texts] = |
9e6e96a1 MB |
3186 | pdata->retune_mobile_cfgs[i].name; |
3187 | ||
3188 | /* ...and remember the new version. */ | |
3189 | wm8994->num_retune_mobile_texts++; | |
3190 | wm8994->retune_mobile_texts = t; | |
3191 | } | |
3192 | ||
3193 | dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n", | |
3194 | wm8994->num_retune_mobile_texts); | |
3195 | ||
3196 | wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts; | |
3197 | wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts; | |
3198 | ||
8cb8e83b | 3199 | ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, |
9e6e96a1 MB |
3200 | ARRAY_SIZE(controls)); |
3201 | if (ret != 0) | |
8cb8e83b | 3202 | dev_err(wm8994->hubs.codec->dev, |
9e6e96a1 MB |
3203 | "Failed to add ReTune Mobile controls: %d\n", ret); |
3204 | } | |
3205 | ||
3206 | static void wm8994_handle_pdata(struct wm8994_priv *wm8994) | |
3207 | { | |
8cb8e83b | 3208 | struct snd_soc_codec *codec = wm8994->hubs.codec; |
d9dd4ada MB |
3209 | struct wm8994 *control = wm8994->wm8994; |
3210 | struct wm8994_pdata *pdata = &control->pdata; | |
9e6e96a1 MB |
3211 | int ret, i; |
3212 | ||
3213 | if (!pdata) | |
3214 | return; | |
3215 | ||
3216 | wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff, | |
3217 | pdata->lineout2_diff, | |
3218 | pdata->lineout1fb, | |
3219 | pdata->lineout2fb, | |
3220 | pdata->jd_scthr, | |
3221 | pdata->jd_thr, | |
02e79476 MB |
3222 | pdata->micb1_delay, |
3223 | pdata->micb2_delay, | |
9e6e96a1 MB |
3224 | pdata->micbias1_lvl, |
3225 | pdata->micbias2_lvl); | |
3226 | ||
3227 | dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs); | |
3228 | ||
3229 | if (pdata->num_drc_cfgs) { | |
3230 | struct snd_kcontrol_new controls[] = { | |
3231 | SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum, | |
3232 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
3233 | SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum, | |
3234 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
3235 | SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum, | |
3236 | wm8994_get_drc_enum, wm8994_put_drc_enum), | |
3237 | }; | |
3238 | ||
3239 | /* We need an array of texts for the enum API */ | |
8cb8e83b | 3240 | wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev, |
7270cebe | 3241 | sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL); |
9e6e96a1 | 3242 | if (!wm8994->drc_texts) { |
8cb8e83b | 3243 | dev_err(wm8994->hubs.codec->dev, |
9e6e96a1 MB |
3244 | "Failed to allocate %d DRC config texts\n", |
3245 | pdata->num_drc_cfgs); | |
3246 | return; | |
3247 | } | |
3248 | ||
3249 | for (i = 0; i < pdata->num_drc_cfgs; i++) | |
3250 | wm8994->drc_texts[i] = pdata->drc_cfgs[i].name; | |
3251 | ||
3252 | wm8994->drc_enum.max = pdata->num_drc_cfgs; | |
3253 | wm8994->drc_enum.texts = wm8994->drc_texts; | |
3254 | ||
8cb8e83b | 3255 | ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls, |
9e6e96a1 | 3256 | ARRAY_SIZE(controls)); |
9e6e96a1 MB |
3257 | for (i = 0; i < WM8994_NUM_DRC; i++) |
3258 | wm8994_set_drc(codec, i); | |
45a690f6 MB |
3259 | } else { |
3260 | ret = snd_soc_add_codec_controls(wm8994->hubs.codec, | |
3261 | wm8994_drc_controls, | |
3262 | ARRAY_SIZE(wm8994_drc_controls)); | |
9e6e96a1 MB |
3263 | } |
3264 | ||
45a690f6 MB |
3265 | if (ret != 0) |
3266 | dev_err(wm8994->hubs.codec->dev, | |
3267 | "Failed to add DRC mode controls: %d\n", ret); | |
3268 | ||
3269 | ||
9e6e96a1 MB |
3270 | dev_dbg(codec->dev, "%d ReTune Mobile configurations\n", |
3271 | pdata->num_retune_mobile_cfgs); | |
3272 | ||
3273 | if (pdata->num_retune_mobile_cfgs) | |
3274 | wm8994_handle_retune_mobile_pdata(wm8994); | |
3275 | else | |
8cb8e83b | 3276 | snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls, |
9e6e96a1 | 3277 | ARRAY_SIZE(wm8994_eq_controls)); |
48e028ec MB |
3278 | |
3279 | for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) { | |
3280 | if (pdata->micbias[i]) { | |
3281 | snd_soc_write(codec, WM8958_MICBIAS1 + i, | |
3282 | pdata->micbias[i] & 0xffff); | |
3283 | } | |
3284 | } | |
9e6e96a1 MB |
3285 | } |
3286 | ||
88766984 MB |
3287 | /** |
3288 | * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ | |
3289 | * | |
3290 | * @codec: WM8994 codec | |
3291 | * @jack: jack to report detection events on | |
3292 | * @micbias: microphone bias to detect on | |
88766984 MB |
3293 | * |
3294 | * Enable microphone detection via IRQ on the WM8994. If GPIOs are | |
3295 | * being used to bring out signals to the processor then only platform | |
5ab230a7 | 3296 | * data configuration is needed for WM8994 and processor GPIOs should |
88766984 MB |
3297 | * be configured using snd_soc_jack_add_gpios() instead. |
3298 | * | |
3299 | * Configuration of detection levels is available via the micbias1_lvl | |
3300 | * and micbias2_lvl platform data members. | |
3301 | */ | |
3302 | int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
87092e3c | 3303 | int micbias) |
88766984 | 3304 | { |
b2c812e2 | 3305 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
88766984 | 3306 | struct wm8994_micdet *micdet; |
2a8a856d | 3307 | struct wm8994 *control = wm8994->wm8994; |
87092e3c | 3308 | int reg, ret; |
88766984 | 3309 | |
87092e3c MB |
3310 | if (control->type != WM8994) { |
3311 | dev_warn(codec->dev, "Not a WM8994\n"); | |
3a423157 | 3312 | return -EINVAL; |
87092e3c | 3313 | } |
3a423157 | 3314 | |
88766984 MB |
3315 | switch (micbias) { |
3316 | case 1: | |
3317 | micdet = &wm8994->micdet[0]; | |
87092e3c MB |
3318 | if (jack) |
3319 | ret = snd_soc_dapm_force_enable_pin(&codec->dapm, | |
3320 | "MICBIAS1"); | |
3321 | else | |
3322 | ret = snd_soc_dapm_disable_pin(&codec->dapm, | |
3323 | "MICBIAS1"); | |
88766984 MB |
3324 | break; |
3325 | case 2: | |
3326 | micdet = &wm8994->micdet[1]; | |
87092e3c MB |
3327 | if (jack) |
3328 | ret = snd_soc_dapm_force_enable_pin(&codec->dapm, | |
3329 | "MICBIAS1"); | |
3330 | else | |
3331 | ret = snd_soc_dapm_disable_pin(&codec->dapm, | |
3332 | "MICBIAS1"); | |
88766984 MB |
3333 | break; |
3334 | default: | |
87092e3c | 3335 | dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias); |
88766984 | 3336 | return -EINVAL; |
87092e3c | 3337 | } |
88766984 | 3338 | |
87092e3c MB |
3339 | if (ret != 0) |
3340 | dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n", | |
3341 | micbias, ret); | |
3342 | ||
3343 | dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n", | |
3344 | micbias, jack); | |
88766984 MB |
3345 | |
3346 | /* Store the configuration */ | |
3347 | micdet->jack = jack; | |
87092e3c | 3348 | micdet->detecting = true; |
88766984 MB |
3349 | |
3350 | /* If either of the jacks is set up then enable detection */ | |
3351 | if (wm8994->micdet[0].jack || wm8994->micdet[1].jack) | |
3352 | reg = WM8994_MICD_ENA; | |
87092e3c | 3353 | else |
88766984 MB |
3354 | reg = 0; |
3355 | ||
3356 | snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg); | |
3357 | ||
d9f34df7 CR |
3358 | /* enable MICDET and MICSHRT deboune */ |
3359 | snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE, | |
3360 | WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK | | |
3361 | WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK, | |
3362 | WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB); | |
3363 | ||
87092e3c MB |
3364 | snd_soc_dapm_sync(&codec->dapm); |
3365 | ||
88766984 MB |
3366 | return 0; |
3367 | } | |
3368 | EXPORT_SYMBOL_GPL(wm8994_mic_detect); | |
3369 | ||
e9b54de4 | 3370 | static void wm8994_mic_work(struct work_struct *work) |
88766984 | 3371 | { |
e9b54de4 MB |
3372 | struct wm8994_priv *priv = container_of(work, |
3373 | struct wm8994_priv, | |
3374 | mic_work.work); | |
fdfc4f3e MB |
3375 | struct regmap *regmap = priv->wm8994->regmap; |
3376 | struct device *dev = priv->wm8994->dev; | |
3377 | unsigned int reg; | |
3378 | int ret; | |
88766984 MB |
3379 | int report; |
3380 | ||
b8176627 MB |
3381 | pm_runtime_get_sync(dev); |
3382 | ||
fdfc4f3e MB |
3383 | ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®); |
3384 | if (ret < 0) { | |
3385 | dev_err(dev, "Failed to read microphone status: %d\n", | |
3386 | ret); | |
b8176627 | 3387 | pm_runtime_put(dev); |
e9b54de4 | 3388 | return; |
88766984 MB |
3389 | } |
3390 | ||
fdfc4f3e | 3391 | dev_dbg(dev, "Microphone status: %x\n", reg); |
88766984 MB |
3392 | |
3393 | report = 0; | |
87092e3c MB |
3394 | if (reg & WM8994_MIC1_DET_STS) { |
3395 | if (priv->micdet[0].detecting) | |
3396 | report = SND_JACK_HEADSET; | |
3397 | } | |
3398 | if (reg & WM8994_MIC1_SHRT_STS) { | |
3399 | if (priv->micdet[0].detecting) | |
3400 | report = SND_JACK_HEADPHONE; | |
3401 | else | |
3402 | report |= SND_JACK_BTN_0; | |
3403 | } | |
3404 | if (report) | |
3405 | priv->micdet[0].detecting = false; | |
3406 | else | |
3407 | priv->micdet[0].detecting = true; | |
3408 | ||
88766984 | 3409 | snd_soc_jack_report(priv->micdet[0].jack, report, |
87092e3c | 3410 | SND_JACK_HEADSET | SND_JACK_BTN_0); |
88766984 MB |
3411 | |
3412 | report = 0; | |
87092e3c MB |
3413 | if (reg & WM8994_MIC2_DET_STS) { |
3414 | if (priv->micdet[1].detecting) | |
3415 | report = SND_JACK_HEADSET; | |
3416 | } | |
3417 | if (reg & WM8994_MIC2_SHRT_STS) { | |
3418 | if (priv->micdet[1].detecting) | |
3419 | report = SND_JACK_HEADPHONE; | |
3420 | else | |
3421 | report |= SND_JACK_BTN_0; | |
3422 | } | |
3423 | if (report) | |
3424 | priv->micdet[1].detecting = false; | |
3425 | else | |
3426 | priv->micdet[1].detecting = true; | |
3427 | ||
88766984 | 3428 | snd_soc_jack_report(priv->micdet[1].jack, report, |
87092e3c | 3429 | SND_JACK_HEADSET | SND_JACK_BTN_0); |
b8176627 MB |
3430 | |
3431 | pm_runtime_put(dev); | |
e9b54de4 MB |
3432 | } |
3433 | ||
3434 | static irqreturn_t wm8994_mic_irq(int irq, void *data) | |
3435 | { | |
3436 | struct wm8994_priv *priv = data; | |
8cb8e83b | 3437 | struct snd_soc_codec *codec = priv->hubs.codec; |
e9b54de4 MB |
3438 | |
3439 | #ifndef CONFIG_SND_SOC_WM8994_MODULE | |
3440 | trace_snd_soc_jack_irq(dev_name(codec->dev)); | |
3441 | #endif | |
3442 | ||
3443 | pm_wakeup_event(codec->dev, 300); | |
3444 | ||
3445 | schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250)); | |
88766984 MB |
3446 | |
3447 | return IRQ_HANDLED; | |
3448 | } | |
3449 | ||
f02b0de0 MB |
3450 | static void wm1811_micd_stop(struct snd_soc_codec *codec) |
3451 | { | |
3452 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
3453 | ||
3454 | if (!wm8994->jackdet) | |
3455 | return; | |
3456 | ||
3457 | mutex_lock(&wm8994->accdet_lock); | |
3458 | ||
3459 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0); | |
3460 | ||
3461 | wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); | |
3462 | ||
3463 | mutex_unlock(&wm8994->accdet_lock); | |
3464 | ||
3465 | if (wm8994->wm8994->pdata.jd_ext_cap) | |
3466 | snd_soc_dapm_disable_pin(&codec->dapm, | |
3467 | "MICBIAS2"); | |
3468 | } | |
3469 | ||
78b76dbe | 3470 | static void wm8958_button_det(struct snd_soc_codec *codec, u16 status) |
821edd2f | 3471 | { |
821edd2f | 3472 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
4585790d | 3473 | int report; |
821edd2f | 3474 | |
78b76dbe MB |
3475 | report = 0; |
3476 | if (status & 0x4) | |
3477 | report |= SND_JACK_BTN_0; | |
3478 | ||
3479 | if (status & 0x8) | |
3480 | report |= SND_JACK_BTN_1; | |
3481 | ||
3482 | if (status & 0x10) | |
3483 | report |= SND_JACK_BTN_2; | |
3484 | ||
3485 | if (status & 0x20) | |
3486 | report |= SND_JACK_BTN_3; | |
3487 | ||
3488 | if (status & 0x40) | |
3489 | report |= SND_JACK_BTN_4; | |
3490 | ||
3491 | if (status & 0x80) | |
3492 | report |= SND_JACK_BTN_5; | |
3493 | ||
3494 | snd_soc_jack_report(wm8994->micdet[0].jack, report, | |
3495 | wm8994->btn_mask); | |
3496 | } | |
3497 | ||
98869f68 | 3498 | static void wm8958_mic_id(void *data, u16 status) |
78b76dbe | 3499 | { |
98869f68 | 3500 | struct snd_soc_codec *codec = data; |
78b76dbe | 3501 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
a1691343 | 3502 | |
af6b6fe4 | 3503 | /* Either nothing present or just starting detection */ |
b00adf76 | 3504 | if (!(status & WM8958_MICD_STS)) { |
f02b0de0 MB |
3505 | /* If nothing present then clear our statuses */ |
3506 | dev_dbg(codec->dev, "Detected open circuit\n"); | |
3507 | wm8994->jack_mic = false; | |
3508 | wm8994->mic_detecting = true; | |
b00adf76 | 3509 | |
f02b0de0 | 3510 | wm1811_micd_stop(codec); |
b00adf76 | 3511 | |
f02b0de0 MB |
3512 | wm8958_micd_set_rate(codec); |
3513 | ||
3514 | snd_soc_jack_report(wm8994->micdet[0].jack, 0, | |
3515 | wm8994->btn_mask | | |
3516 | SND_JACK_HEADSET); | |
b00adf76 MB |
3517 | return; |
3518 | } | |
821edd2f | 3519 | |
b00adf76 MB |
3520 | /* If the measurement is showing a high impedence we've got a |
3521 | * microphone. | |
3522 | */ | |
78b76dbe | 3523 | if (status & 0x600) { |
b00adf76 MB |
3524 | dev_dbg(codec->dev, "Detected microphone\n"); |
3525 | ||
157a75e6 | 3526 | wm8994->mic_detecting = false; |
b00adf76 MB |
3527 | wm8994->jack_mic = true; |
3528 | ||
3529 | wm8958_micd_set_rate(codec); | |
3530 | ||
3531 | snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET, | |
3532 | SND_JACK_HEADSET); | |
3533 | } | |
821edd2f | 3534 | |
b00adf76 | 3535 | |
78b76dbe | 3536 | if (status & 0xfc) { |
b00adf76 | 3537 | dev_dbg(codec->dev, "Detected headphone\n"); |
157a75e6 | 3538 | wm8994->mic_detecting = false; |
b00adf76 MB |
3539 | |
3540 | wm8958_micd_set_rate(codec); | |
3541 | ||
af6b6fe4 | 3542 | /* If we have jackdet that will detect removal */ |
f02b0de0 | 3543 | wm1811_micd_stop(codec); |
ecd1732f MB |
3544 | |
3545 | snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE, | |
3546 | SND_JACK_HEADSET); | |
b00adf76 | 3547 | } |
821edd2f | 3548 | } |
b00adf76 | 3549 | |
c0cc3f16 MB |
3550 | /* Deferred mic detection to allow for extra settling time */ |
3551 | static void wm1811_mic_work(struct work_struct *work) | |
3552 | { | |
3553 | struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv, | |
3554 | mic_work.work); | |
d9dd4ada | 3555 | struct wm8994 *control = wm8994->wm8994; |
c0cc3f16 | 3556 | struct snd_soc_codec *codec = wm8994->hubs.codec; |
4585790d | 3557 | |
c0cc3f16 | 3558 | pm_runtime_get_sync(codec->dev); |
4585790d | 3559 | |
c0cc3f16 | 3560 | /* If required for an external cap force MICBIAS on */ |
d9dd4ada | 3561 | if (control->pdata.jd_ext_cap) { |
c0cc3f16 MB |
3562 | snd_soc_dapm_force_enable_pin(&codec->dapm, |
3563 | "MICBIAS2"); | |
3564 | snd_soc_dapm_sync(&codec->dapm); | |
3565 | } | |
4585790d | 3566 | |
c0cc3f16 | 3567 | mutex_lock(&wm8994->accdet_lock); |
4585790d | 3568 | |
c0cc3f16 | 3569 | dev_dbg(codec->dev, "Starting mic detection\n"); |
4585790d | 3570 | |
63dd5452 MB |
3571 | /* Use a user-supplied callback if we have one */ |
3572 | if (wm8994->micd_cb) { | |
3573 | wm8994->micd_cb(wm8994->micd_cb_data); | |
3574 | } else { | |
3575 | /* | |
3576 | * Start off measument of microphone impedence to find out | |
3577 | * what's actually there. | |
3578 | */ | |
3579 | wm8994->mic_detecting = true; | |
3580 | wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC); | |
4585790d | 3581 | |
63dd5452 MB |
3582 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, |
3583 | WM8958_MICD_ENA, WM8958_MICD_ENA); | |
b00adf76 | 3584 | } |
c0cc3f16 MB |
3585 | |
3586 | mutex_unlock(&wm8994->accdet_lock); | |
3587 | ||
3588 | pm_runtime_put(codec->dev); | |
821edd2f MB |
3589 | } |
3590 | ||
af6b6fe4 MB |
3591 | static irqreturn_t wm1811_jackdet_irq(int irq, void *data) |
3592 | { | |
3593 | struct wm8994_priv *wm8994 = data; | |
d9dd4ada | 3594 | struct wm8994 *control = wm8994->wm8994; |
8cb8e83b | 3595 | struct snd_soc_codec *codec = wm8994->hubs.codec; |
c0cc3f16 | 3596 | int reg, delay; |
c986564b | 3597 | bool present; |
af6b6fe4 | 3598 | |
b8176627 MB |
3599 | pm_runtime_get_sync(codec->dev); |
3600 | ||
af6b6fe4 MB |
3601 | mutex_lock(&wm8994->accdet_lock); |
3602 | ||
3603 | reg = snd_soc_read(codec, WM1811_JACKDET_CTRL); | |
3604 | if (reg < 0) { | |
3605 | dev_err(codec->dev, "Failed to read jack status: %d\n", reg); | |
3606 | mutex_unlock(&wm8994->accdet_lock); | |
b8176627 | 3607 | pm_runtime_put(codec->dev); |
af6b6fe4 MB |
3608 | return IRQ_NONE; |
3609 | } | |
3610 | ||
3611 | dev_dbg(codec->dev, "JACKDET %x\n", reg); | |
3612 | ||
c986564b | 3613 | present = reg & WM1811_JACKDET_LVL; |
af6b6fe4 | 3614 | |
c986564b MB |
3615 | if (present) { |
3616 | dev_dbg(codec->dev, "Jack detected\n"); | |
af6b6fe4 | 3617 | |
e9d9a968 MB |
3618 | wm8958_micd_set_rate(codec); |
3619 | ||
55a27786 MB |
3620 | snd_soc_update_bits(codec, WM8958_MICBIAS2, |
3621 | WM8958_MICB2_DISCH, 0); | |
3622 | ||
378ec0ca MB |
3623 | /* Disable debounce while inserted */ |
3624 | snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, | |
3625 | WM1811_JACKDET_DB, 0); | |
3626 | ||
d9dd4ada | 3627 | delay = control->pdata.micdet_delay; |
c0cc3f16 MB |
3628 | schedule_delayed_work(&wm8994->mic_work, |
3629 | msecs_to_jiffies(delay)); | |
af6b6fe4 MB |
3630 | } else { |
3631 | dev_dbg(codec->dev, "Jack not detected\n"); | |
3632 | ||
c0cc3f16 MB |
3633 | cancel_delayed_work_sync(&wm8994->mic_work); |
3634 | ||
55a27786 MB |
3635 | snd_soc_update_bits(codec, WM8958_MICBIAS2, |
3636 | WM8958_MICB2_DISCH, WM8958_MICB2_DISCH); | |
3637 | ||
378ec0ca MB |
3638 | /* Enable debounce while removed */ |
3639 | snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, | |
3640 | WM1811_JACKDET_DB, WM1811_JACKDET_DB); | |
3641 | ||
af6b6fe4 MB |
3642 | wm8994->mic_detecting = false; |
3643 | wm8994->jack_mic = false; | |
3644 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
3645 | WM8958_MICD_ENA, 0); | |
3646 | wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK); | |
3647 | } | |
3648 | ||
3649 | mutex_unlock(&wm8994->accdet_lock); | |
3650 | ||
c0cc3f16 | 3651 | /* Turn off MICBIAS if it was on for an external cap */ |
d9dd4ada | 3652 | if (control->pdata.jd_ext_cap && !present) |
c0cc3f16 | 3653 | snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2"); |
c986564b MB |
3654 | |
3655 | if (present) | |
3656 | snd_soc_jack_report(wm8994->micdet[0].jack, | |
3657 | SND_JACK_MECHANICAL, SND_JACK_MECHANICAL); | |
3658 | else | |
3659 | snd_soc_jack_report(wm8994->micdet[0].jack, 0, | |
3660 | SND_JACK_MECHANICAL | SND_JACK_HEADSET | | |
3661 | wm8994->btn_mask); | |
3662 | ||
99af79df MB |
3663 | /* Since we only report deltas force an update, ensures we |
3664 | * avoid bootstrapping issues with the core. */ | |
3665 | snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0); | |
3666 | ||
b8176627 | 3667 | pm_runtime_put(codec->dev); |
af6b6fe4 MB |
3668 | return IRQ_HANDLED; |
3669 | } | |
3670 | ||
99af79df MB |
3671 | static void wm1811_jackdet_bootstrap(struct work_struct *work) |
3672 | { | |
3673 | struct wm8994_priv *wm8994 = container_of(work, | |
3674 | struct wm8994_priv, | |
3675 | jackdet_bootstrap.work); | |
3676 | wm1811_jackdet_irq(0, wm8994); | |
3677 | } | |
3678 | ||
821edd2f MB |
3679 | /** |
3680 | * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ | |
3681 | * | |
3682 | * @codec: WM8958 codec | |
3683 | * @jack: jack to report detection events on | |
3684 | * | |
3685 | * Enable microphone detection functionality for the WM8958. By | |
3686 | * default simple detection which supports the detection of up to 6 | |
3687 | * buttons plus video and microphone functionality is supported. | |
3688 | * | |
3689 | * The WM8958 has an advanced jack detection facility which is able to | |
3690 | * support complex accessory detection, especially when used in | |
3691 | * conjunction with external circuitry. In order to provide maximum | |
3692 | * flexiblity a callback is provided which allows a completely custom | |
3693 | * detection algorithm. | |
3694 | */ | |
3695 | int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack, | |
98869f68 MB |
3696 | wm1811_micdet_cb det_cb, void *det_cb_data, |
3697 | wm1811_mic_id_cb id_cb, void *id_cb_data) | |
821edd2f MB |
3698 | { |
3699 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); | |
2a8a856d | 3700 | struct wm8994 *control = wm8994->wm8994; |
4585790d | 3701 | u16 micd_lvl_sel; |
821edd2f | 3702 | |
81204c84 MB |
3703 | switch (control->type) { |
3704 | case WM1811: | |
3705 | case WM8958: | |
3706 | break; | |
3707 | default: | |
821edd2f | 3708 | return -EINVAL; |
81204c84 | 3709 | } |
821edd2f MB |
3710 | |
3711 | if (jack) { | |
4cdf5e49 | 3712 | snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS"); |
7d464b20 | 3713 | snd_soc_dapm_sync(&codec->dapm); |
4cdf5e49 | 3714 | |
821edd2f | 3715 | wm8994->micdet[0].jack = jack; |
821edd2f | 3716 | |
98869f68 MB |
3717 | if (det_cb) { |
3718 | wm8994->micd_cb = det_cb; | |
3719 | wm8994->micd_cb_data = det_cb_data; | |
63dd5452 MB |
3720 | } else { |
3721 | wm8994->mic_detecting = true; | |
3722 | wm8994->jack_mic = false; | |
3723 | } | |
b00adf76 | 3724 | |
98869f68 MB |
3725 | if (id_cb) { |
3726 | wm8994->mic_id_cb = id_cb; | |
3727 | wm8994->mic_id_cb_data = id_cb_data; | |
3728 | } else { | |
3729 | wm8994->mic_id_cb = wm8958_mic_id; | |
3730 | wm8994->mic_id_cb_data = codec; | |
3731 | } | |
b00adf76 MB |
3732 | |
3733 | wm8958_micd_set_rate(codec); | |
3734 | ||
4585790d | 3735 | /* Detect microphones and short circuits by default */ |
d9dd4ada MB |
3736 | if (control->pdata.micd_lvl_sel) |
3737 | micd_lvl_sel = control->pdata.micd_lvl_sel; | |
4585790d MB |
3738 | else |
3739 | micd_lvl_sel = 0x41; | |
3740 | ||
3741 | wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | | |
3742 | SND_JACK_BTN_2 | SND_JACK_BTN_3 | | |
3743 | SND_JACK_BTN_4 | SND_JACK_BTN_5; | |
3744 | ||
b00adf76 | 3745 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_2, |
4585790d | 3746 | WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel); |
b00adf76 | 3747 | |
af6b6fe4 MB |
3748 | WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY); |
3749 | ||
3750 | /* | |
3751 | * If we can use jack detection start off with that, | |
3752 | * otherwise jump straight to microphone detection. | |
3753 | */ | |
3754 | if (wm8994->jackdet) { | |
99af79df MB |
3755 | /* Disable debounce for the initial detect */ |
3756 | snd_soc_update_bits(codec, WM1811_JACKDET_CTRL, | |
3757 | WM1811_JACKDET_DB, 0); | |
3758 | ||
55a27786 MB |
3759 | snd_soc_update_bits(codec, WM8958_MICBIAS2, |
3760 | WM8958_MICB2_DISCH, | |
3761 | WM8958_MICB2_DISCH); | |
af6b6fe4 MB |
3762 | snd_soc_update_bits(codec, WM8994_LDO_1, |
3763 | WM8994_LDO1_DISCH, 0); | |
3764 | wm1811_jackdet_set_mode(codec, | |
3765 | WM1811_JACKDET_MODE_JACK); | |
3766 | } else { | |
3767 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
3768 | WM8958_MICD_ENA, WM8958_MICD_ENA); | |
3769 | } | |
3770 | ||
821edd2f MB |
3771 | } else { |
3772 | snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, | |
3773 | WM8958_MICD_ENA, 0); | |
afaf1591 | 3774 | wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE); |
4cdf5e49 | 3775 | snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS"); |
7d464b20 | 3776 | snd_soc_dapm_sync(&codec->dapm); |
821edd2f MB |
3777 | } |
3778 | ||
3779 | return 0; | |
3780 | } | |
3781 | EXPORT_SYMBOL_GPL(wm8958_mic_detect); | |
3782 | ||
3783 | static irqreturn_t wm8958_mic_irq(int irq, void *data) | |
3784 | { | |
3785 | struct wm8994_priv *wm8994 = data; | |
8cb8e83b | 3786 | struct snd_soc_codec *codec = wm8994->hubs.codec; |
8afd0ef2 | 3787 | int reg, count, ret; |
821edd2f | 3788 | |
af6b6fe4 MB |
3789 | /* |
3790 | * Jack detection may have detected a removal simulataneously | |
3791 | * with an update of the MICDET status; if so it will have | |
3792 | * stopped detection and we can ignore this interrupt. | |
3793 | */ | |
c986564b | 3794 | if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA)) |
af6b6fe4 | 3795 | return IRQ_HANDLED; |
af6b6fe4 | 3796 | |
b8176627 MB |
3797 | pm_runtime_get_sync(codec->dev); |
3798 | ||
19940b3d MB |
3799 | /* We may occasionally read a detection without an impedence |
3800 | * range being provided - if that happens loop again. | |
3801 | */ | |
3802 | count = 10; | |
3803 | do { | |
3804 | reg = snd_soc_read(codec, WM8958_MIC_DETECT_3); | |
3805 | if (reg < 0) { | |
3806 | dev_err(codec->dev, | |
3807 | "Failed to read mic detect status: %d\n", | |
3808 | reg); | |
b8176627 | 3809 | pm_runtime_put(codec->dev); |
19940b3d MB |
3810 | return IRQ_NONE; |
3811 | } | |
821edd2f | 3812 | |
19940b3d MB |
3813 | if (!(reg & WM8958_MICD_VALID)) { |
3814 | dev_dbg(codec->dev, "Mic detect data not valid\n"); | |
3815 | goto out; | |
3816 | } | |
3817 | ||
3818 | if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK)) | |
3819 | break; | |
3820 | ||
3821 | msleep(1); | |
3822 | } while (count--); | |
3823 | ||
3824 | if (count == 0) | |
ec8f53fb | 3825 | dev_warn(codec->dev, "No impedance range reported for jack\n"); |
821edd2f | 3826 | |
7116f452 | 3827 | #ifndef CONFIG_SND_SOC_WM8994_MODULE |
2bbb5d66 | 3828 | trace_snd_soc_jack_irq(dev_name(codec->dev)); |
7116f452 | 3829 | #endif |
2bbb5d66 | 3830 | |
e874de43 MB |
3831 | /* Avoid a transient report when the accessory is being removed */ |
3832 | if (wm8994->jackdet) { | |
8afd0ef2 MB |
3833 | ret = snd_soc_read(codec, WM1811_JACKDET_CTRL); |
3834 | if (ret < 0) { | |
e874de43 | 3835 | dev_err(codec->dev, "Failed to read jack status: %d\n", |
8afd0ef2 MB |
3836 | ret); |
3837 | } else if (!(ret & WM1811_JACKDET_LVL)) { | |
e874de43 MB |
3838 | dev_dbg(codec->dev, "Ignoring removed jack\n"); |
3839 | return IRQ_HANDLED; | |
3840 | } | |
9767a58b MB |
3841 | } else if (!(reg & WM8958_MICD_STS)) { |
3842 | snd_soc_jack_report(wm8994->micdet[0].jack, 0, | |
3843 | SND_JACK_MECHANICAL | SND_JACK_HEADSET | | |
3844 | wm8994->btn_mask); | |
3845 | goto out; | |
e874de43 MB |
3846 | } |
3847 | ||
78b76dbe | 3848 | if (wm8994->mic_detecting) |
98869f68 | 3849 | wm8994->mic_id_cb(wm8994->mic_id_cb_data, reg); |
821edd2f | 3850 | else |
78b76dbe | 3851 | wm8958_button_det(codec, reg); |
821edd2f MB |
3852 | |
3853 | out: | |
b8176627 | 3854 | pm_runtime_put(codec->dev); |
821edd2f MB |
3855 | return IRQ_HANDLED; |
3856 | } | |
3857 | ||
3b1af3f8 MB |
3858 | static irqreturn_t wm8994_fifo_error(int irq, void *data) |
3859 | { | |
3860 | struct snd_soc_codec *codec = data; | |
3861 | ||
3862 | dev_err(codec->dev, "FIFO error\n"); | |
3863 | ||
3864 | return IRQ_HANDLED; | |
3865 | } | |
3866 | ||
f0b182b0 MB |
3867 | static irqreturn_t wm8994_temp_warn(int irq, void *data) |
3868 | { | |
3869 | struct snd_soc_codec *codec = data; | |
3870 | ||
3871 | dev_err(codec->dev, "Thermal warning\n"); | |
3872 | ||
3873 | return IRQ_HANDLED; | |
3874 | } | |
3875 | ||
3876 | static irqreturn_t wm8994_temp_shut(int irq, void *data) | |
3877 | { | |
3878 | struct snd_soc_codec *codec = data; | |
3879 | ||
3880 | dev_crit(codec->dev, "Thermal shutdown\n"); | |
3881 | ||
3882 | return IRQ_HANDLED; | |
3883 | } | |
3884 | ||
f0fba2ad | 3885 | static int wm8994_codec_probe(struct snd_soc_codec *codec) |
9e6e96a1 | 3886 | { |
d9a7666f | 3887 | struct wm8994 *control = dev_get_drvdata(codec->dev->parent); |
2bc16ed8 | 3888 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
ce6120cc | 3889 | struct snd_soc_dapm_context *dapm = &codec->dapm; |
d9a7666f | 3890 | unsigned int reg; |
ec62dbd7 | 3891 | int ret, i; |
9e6e96a1 | 3892 | |
8cb8e83b | 3893 | wm8994->hubs.codec = codec; |
d9a7666f | 3894 | codec->control_data = control->regmap; |
9e6e96a1 | 3895 | |
d9a7666f | 3896 | snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); |
2a8a856d | 3897 | |
af6b6fe4 | 3898 | mutex_init(&wm8994->accdet_lock); |
99af79df MB |
3899 | INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap, |
3900 | wm1811_jackdet_bootstrap); | |
af6b6fe4 | 3901 | |
c0cc3f16 MB |
3902 | switch (control->type) { |
3903 | case WM8994: | |
3904 | INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work); | |
3905 | break; | |
3906 | case WM1811: | |
3907 | INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work); | |
3908 | break; | |
3909 | default: | |
3910 | break; | |
3911 | } | |
3912 | ||
c7ebf932 MB |
3913 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) |
3914 | init_completion(&wm8994->fll_locked[i]); | |
3915 | ||
d9dd4ada | 3916 | wm8994->micdet_irq = control->pdata.micdet_irq; |
9b7c525d | 3917 | |
39fb51a1 | 3918 | pm_runtime_enable(codec->dev); |
5fab5174 | 3919 | pm_runtime_idle(codec->dev); |
39fb51a1 | 3920 | |
f959dee9 MB |
3921 | /* By default use idle_bias_off, will override for WM8994 */ |
3922 | codec->dapm.idle_bias_off = 1; | |
3923 | ||
9e6e96a1 | 3924 | /* Set revision-specific configuration */ |
3a423157 MB |
3925 | switch (control->type) { |
3926 | case WM8994: | |
f959dee9 | 3927 | /* Single ended line outputs should have VMID on. */ |
d9dd4ada MB |
3928 | if (!control->pdata.lineout1_diff || |
3929 | !control->pdata.lineout2_diff) | |
f959dee9 MB |
3930 | codec->dapm.idle_bias_off = 0; |
3931 | ||
da445afe | 3932 | switch (control->revision) { |
3a423157 MB |
3933 | case 2: |
3934 | case 3: | |
4537c4e7 MB |
3935 | wm8994->hubs.dcs_codes_l = -5; |
3936 | wm8994->hubs.dcs_codes_r = -5; | |
3a423157 MB |
3937 | wm8994->hubs.hp_startup_mode = 1; |
3938 | wm8994->hubs.dcs_readback_mode = 1; | |
f9acf9fe | 3939 | wm8994->hubs.series_startup = 1; |
3a423157 MB |
3940 | break; |
3941 | default: | |
79ef0abc | 3942 | wm8994->hubs.dcs_readback_mode = 2; |
3a423157 MB |
3943 | break; |
3944 | } | |
280ec8b7 | 3945 | break; |
3a423157 MB |
3946 | |
3947 | case WM8958: | |
8437f700 | 3948 | wm8994->hubs.dcs_readback_mode = 1; |
29fdc360 | 3949 | wm8994->hubs.hp_startup_mode = 1; |
20dc24a9 | 3950 | |
da445afe | 3951 | switch (control->revision) { |
20dc24a9 MB |
3952 | case 0: |
3953 | break; | |
3954 | default: | |
3955 | wm8994->fll_byp = true; | |
3956 | break; | |
3957 | } | |
9e6e96a1 | 3958 | break; |
3a423157 | 3959 | |
81204c84 MB |
3960 | case WM1811: |
3961 | wm8994->hubs.dcs_readback_mode = 2; | |
3962 | wm8994->hubs.no_series_update = 1; | |
29fdc360 | 3963 | wm8994->hubs.hp_startup_mode = 1; |
af31a227 | 3964 | wm8994->hubs.no_cache_dac_hp_direct = true; |
20dc24a9 | 3965 | wm8994->fll_byp = true; |
81204c84 | 3966 | |
72222be3 MB |
3967 | wm8994->hubs.dcs_codes_l = -9; |
3968 | wm8994->hubs.dcs_codes_r = -7; | |
81204c84 MB |
3969 | |
3970 | snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1, | |
3971 | WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN); | |
3972 | break; | |
3973 | ||
9e6e96a1 MB |
3974 | default: |
3975 | break; | |
3976 | } | |
9e6e96a1 | 3977 | |
2a8a856d | 3978 | wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, |
3b1af3f8 | 3979 | wm8994_fifo_error, "FIFO error", codec); |
2a8a856d | 3980 | wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, |
f0b182b0 | 3981 | wm8994_temp_warn, "Thermal warning", codec); |
2a8a856d | 3982 | wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, |
f0b182b0 | 3983 | wm8994_temp_shut, "Thermal shutdown", codec); |
3b1af3f8 | 3984 | |
2a8a856d | 3985 | ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, |
b30ead5f MB |
3986 | wm_hubs_dcs_done, "DC servo done", |
3987 | &wm8994->hubs); | |
3988 | if (ret == 0) | |
3989 | wm8994->hubs.dcs_done_irq = true; | |
3990 | ||
3a423157 MB |
3991 | switch (control->type) { |
3992 | case WM8994: | |
9b7c525d MB |
3993 | if (wm8994->micdet_irq) { |
3994 | ret = request_threaded_irq(wm8994->micdet_irq, NULL, | |
3995 | wm8994_mic_irq, | |
3996 | IRQF_TRIGGER_RISING, | |
3997 | "Mic1 detect", | |
3998 | wm8994); | |
3999 | if (ret != 0) | |
4000 | dev_warn(codec->dev, | |
4001 | "Failed to request Mic1 detect IRQ: %d\n", | |
4002 | ret); | |
4003 | } | |
3a423157 | 4004 | |
2a8a856d | 4005 | ret = wm8994_request_irq(wm8994->wm8994, |
3a423157 MB |
4006 | WM8994_IRQ_MIC1_SHRT, |
4007 | wm8994_mic_irq, "Mic 1 short", | |
4008 | wm8994); | |
4009 | if (ret != 0) | |
4010 | dev_warn(codec->dev, | |
4011 | "Failed to request Mic1 short IRQ: %d\n", | |
4012 | ret); | |
4013 | ||
2a8a856d | 4014 | ret = wm8994_request_irq(wm8994->wm8994, |
3a423157 MB |
4015 | WM8994_IRQ_MIC2_DET, |
4016 | wm8994_mic_irq, "Mic 2 detect", | |
4017 | wm8994); | |
4018 | if (ret != 0) | |
4019 | dev_warn(codec->dev, | |
4020 | "Failed to request Mic2 detect IRQ: %d\n", | |
4021 | ret); | |
4022 | ||
2a8a856d | 4023 | ret = wm8994_request_irq(wm8994->wm8994, |
3a423157 MB |
4024 | WM8994_IRQ_MIC2_SHRT, |
4025 | wm8994_mic_irq, "Mic 2 short", | |
4026 | wm8994); | |
4027 | if (ret != 0) | |
4028 | dev_warn(codec->dev, | |
4029 | "Failed to request Mic2 short IRQ: %d\n", | |
4030 | ret); | |
4031 | break; | |
821edd2f MB |
4032 | |
4033 | case WM8958: | |
81204c84 | 4034 | case WM1811: |
9b7c525d MB |
4035 | if (wm8994->micdet_irq) { |
4036 | ret = request_threaded_irq(wm8994->micdet_irq, NULL, | |
4037 | wm8958_mic_irq, | |
4038 | IRQF_TRIGGER_RISING, | |
4039 | "Mic detect", | |
4040 | wm8994); | |
4041 | if (ret != 0) | |
4042 | dev_warn(codec->dev, | |
4043 | "Failed to request Mic detect IRQ: %d\n", | |
4044 | ret); | |
b4046d01 MB |
4045 | } else { |
4046 | wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, | |
4047 | wm8958_mic_irq, "Mic detect", | |
4048 | wm8994); | |
9b7c525d | 4049 | } |
3a423157 | 4050 | } |
88766984 | 4051 | |
af6b6fe4 MB |
4052 | switch (control->type) { |
4053 | case WM1811: | |
da445afe | 4054 | if (control->cust_id > 1 || control->revision > 1) { |
af6b6fe4 MB |
4055 | ret = wm8994_request_irq(wm8994->wm8994, |
4056 | WM8994_IRQ_GPIO(6), | |
4057 | wm1811_jackdet_irq, "JACKDET", | |
4058 | wm8994); | |
4059 | if (ret == 0) | |
4060 | wm8994->jackdet = true; | |
4061 | } | |
4062 | break; | |
4063 | default: | |
4064 | break; | |
4065 | } | |
4066 | ||
c7ebf932 MB |
4067 | wm8994->fll_locked_irq = true; |
4068 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) { | |
2a8a856d | 4069 | ret = wm8994_request_irq(wm8994->wm8994, |
c7ebf932 MB |
4070 | WM8994_IRQ_FLL1_LOCK + i, |
4071 | wm8994_fll_locked_irq, "FLL lock", | |
4072 | &wm8994->fll_locked[i]); | |
4073 | if (ret != 0) | |
4074 | wm8994->fll_locked_irq = false; | |
4075 | } | |
4076 | ||
27060b3c MB |
4077 | /* Make sure we can read from the GPIOs if they're inputs */ |
4078 | pm_runtime_get_sync(codec->dev); | |
4079 | ||
9e6e96a1 MB |
4080 | /* Remember if AIFnLRCLK is configured as a GPIO. This should be |
4081 | * configured on init - if a system wants to do this dynamically | |
4082 | * at runtime we can deal with that then. | |
4083 | */ | |
d9a7666f | 4084 | ret = regmap_read(control->regmap, WM8994_GPIO_1, ®); |
9e6e96a1 MB |
4085 | if (ret < 0) { |
4086 | dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret); | |
88766984 | 4087 | goto err_irq; |
9e6e96a1 | 4088 | } |
d9a7666f | 4089 | if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { |
9e6e96a1 MB |
4090 | wm8994->lrclk_shared[0] = 1; |
4091 | wm8994_dai[0].symmetric_rates = 1; | |
4092 | } else { | |
4093 | wm8994->lrclk_shared[0] = 0; | |
4094 | } | |
4095 | ||
d9a7666f | 4096 | ret = regmap_read(control->regmap, WM8994_GPIO_6, ®); |
9e6e96a1 MB |
4097 | if (ret < 0) { |
4098 | dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret); | |
88766984 | 4099 | goto err_irq; |
9e6e96a1 | 4100 | } |
d9a7666f | 4101 | if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) { |
9e6e96a1 MB |
4102 | wm8994->lrclk_shared[1] = 1; |
4103 | wm8994_dai[1].symmetric_rates = 1; | |
4104 | } else { | |
4105 | wm8994->lrclk_shared[1] = 0; | |
4106 | } | |
4107 | ||
27060b3c MB |
4108 | pm_runtime_put(codec->dev); |
4109 | ||
bfd37bb5 MB |
4110 | /* Latch volume update bits */ |
4111 | for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++) | |
4112 | snd_soc_update_bits(codec, wm8994_vu_bits[i].reg, | |
4113 | wm8994_vu_bits[i].mask, | |
4114 | wm8994_vu_bits[i].mask); | |
9e6e96a1 MB |
4115 | |
4116 | /* Set the low bit of the 3D stereo depth so TLV matches */ | |
4117 | snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2, | |
4118 | 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT, | |
4119 | 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT); | |
4120 | snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2, | |
4121 | 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT, | |
4122 | 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT); | |
4123 | snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2, | |
4124 | 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT, | |
4125 | 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT); | |
4126 | ||
5b739670 MB |
4127 | /* Unconditionally enable AIF1 ADC TDM mode on chips which can |
4128 | * use this; it only affects behaviour on idle TDM clock | |
4129 | * cycles. */ | |
4130 | switch (control->type) { | |
4131 | case WM8994: | |
4132 | case WM8958: | |
4133 | snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1, | |
4134 | WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM); | |
4135 | break; | |
4136 | default: | |
4137 | break; | |
4138 | } | |
d1ce6b20 | 4139 | |
500fa30e MB |
4140 | /* Put MICBIAS into bypass mode by default on newer devices */ |
4141 | switch (control->type) { | |
4142 | case WM8958: | |
4143 | case WM1811: | |
4144 | snd_soc_update_bits(codec, WM8958_MICBIAS1, | |
4145 | WM8958_MICB1_MODE, WM8958_MICB1_MODE); | |
4146 | snd_soc_update_bits(codec, WM8958_MICBIAS2, | |
4147 | WM8958_MICB2_MODE, WM8958_MICB2_MODE); | |
4148 | break; | |
4149 | default: | |
4150 | break; | |
4151 | } | |
4152 | ||
c340304d MB |
4153 | wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital; |
4154 | wm_hubs_update_class_w(codec); | |
9e6e96a1 | 4155 | |
f0fba2ad | 4156 | wm8994_handle_pdata(wm8994); |
9e6e96a1 | 4157 | |
f0fba2ad | 4158 | wm_hubs_add_analogue_controls(codec); |
022658be | 4159 | snd_soc_add_codec_controls(codec, wm8994_snd_controls, |
f0fba2ad | 4160 | ARRAY_SIZE(wm8994_snd_controls)); |
ce6120cc | 4161 | snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets, |
f0fba2ad | 4162 | ARRAY_SIZE(wm8994_dapm_widgets)); |
c4431df0 MB |
4163 | |
4164 | switch (control->type) { | |
4165 | case WM8994: | |
4166 | snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets, | |
4167 | ARRAY_SIZE(wm8994_specific_dapm_widgets)); | |
da445afe | 4168 | if (control->revision < 4) { |
173efa09 DP |
4169 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, |
4170 | ARRAY_SIZE(wm8994_lateclk_revd_widgets)); | |
04d28681 DP |
4171 | snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, |
4172 | ARRAY_SIZE(wm8994_adc_revd_widgets)); | |
c52fd021 DP |
4173 | snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, |
4174 | ARRAY_SIZE(wm8994_dac_revd_widgets)); | |
4175 | } else { | |
173efa09 DP |
4176 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, |
4177 | ARRAY_SIZE(wm8994_lateclk_widgets)); | |
04d28681 DP |
4178 | snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, |
4179 | ARRAY_SIZE(wm8994_adc_widgets)); | |
c52fd021 DP |
4180 | snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, |
4181 | ARRAY_SIZE(wm8994_dac_widgets)); | |
4182 | } | |
c4431df0 MB |
4183 | break; |
4184 | case WM8958: | |
022658be | 4185 | snd_soc_add_codec_controls(codec, wm8958_snd_controls, |
c4431df0 MB |
4186 | ARRAY_SIZE(wm8958_snd_controls)); |
4187 | snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, | |
4188 | ARRAY_SIZE(wm8958_dapm_widgets)); | |
da445afe | 4189 | if (control->revision < 1) { |
780e2806 MB |
4190 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets, |
4191 | ARRAY_SIZE(wm8994_lateclk_revd_widgets)); | |
4192 | snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets, | |
4193 | ARRAY_SIZE(wm8994_adc_revd_widgets)); | |
4194 | snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets, | |
4195 | ARRAY_SIZE(wm8994_dac_revd_widgets)); | |
4196 | } else { | |
4197 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, | |
4198 | ARRAY_SIZE(wm8994_lateclk_widgets)); | |
4199 | snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, | |
4200 | ARRAY_SIZE(wm8994_adc_widgets)); | |
4201 | snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, | |
4202 | ARRAY_SIZE(wm8994_dac_widgets)); | |
4203 | } | |
c4431df0 | 4204 | break; |
81204c84 MB |
4205 | |
4206 | case WM1811: | |
022658be | 4207 | snd_soc_add_codec_controls(codec, wm8958_snd_controls, |
81204c84 MB |
4208 | ARRAY_SIZE(wm8958_snd_controls)); |
4209 | snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets, | |
4210 | ARRAY_SIZE(wm8958_dapm_widgets)); | |
4211 | snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets, | |
4212 | ARRAY_SIZE(wm8994_lateclk_widgets)); | |
4213 | snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets, | |
4214 | ARRAY_SIZE(wm8994_adc_widgets)); | |
4215 | snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets, | |
4216 | ARRAY_SIZE(wm8994_dac_widgets)); | |
4217 | break; | |
c4431df0 | 4218 | } |
c4431df0 | 4219 | |
f0fba2ad | 4220 | wm_hubs_add_analogue_routes(codec, 0, 0); |
ce6120cc | 4221 | snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); |
9e6e96a1 | 4222 | |
c4431df0 MB |
4223 | switch (control->type) { |
4224 | case WM8994: | |
4225 | snd_soc_dapm_add_routes(dapm, wm8994_intercon, | |
4226 | ARRAY_SIZE(wm8994_intercon)); | |
6ed8f148 | 4227 | |
da445afe | 4228 | if (control->revision < 4) { |
6ed8f148 MB |
4229 | snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, |
4230 | ARRAY_SIZE(wm8994_revd_intercon)); | |
173efa09 DP |
4231 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, |
4232 | ARRAY_SIZE(wm8994_lateclk_revd_intercon)); | |
4233 | } else { | |
4234 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, | |
4235 | ARRAY_SIZE(wm8994_lateclk_intercon)); | |
4236 | } | |
c4431df0 MB |
4237 | break; |
4238 | case WM8958: | |
da445afe | 4239 | if (control->revision < 1) { |
15676937 CR |
4240 | snd_soc_dapm_add_routes(dapm, wm8994_intercon, |
4241 | ARRAY_SIZE(wm8994_intercon)); | |
780e2806 MB |
4242 | snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon, |
4243 | ARRAY_SIZE(wm8994_revd_intercon)); | |
4244 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon, | |
4245 | ARRAY_SIZE(wm8994_lateclk_revd_intercon)); | |
4246 | } else { | |
4247 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, | |
4248 | ARRAY_SIZE(wm8994_lateclk_intercon)); | |
4249 | snd_soc_dapm_add_routes(dapm, wm8958_intercon, | |
4250 | ARRAY_SIZE(wm8958_intercon)); | |
4251 | } | |
f701a2e5 MB |
4252 | |
4253 | wm8958_dsp2_init(codec); | |
c4431df0 | 4254 | break; |
81204c84 MB |
4255 | case WM1811: |
4256 | snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon, | |
4257 | ARRAY_SIZE(wm8994_lateclk_intercon)); | |
4258 | snd_soc_dapm_add_routes(dapm, wm8958_intercon, | |
4259 | ARRAY_SIZE(wm8958_intercon)); | |
4260 | break; | |
c4431df0 MB |
4261 | } |
4262 | ||
9e6e96a1 MB |
4263 | return 0; |
4264 | ||
88766984 | 4265 | err_irq: |
af6b6fe4 MB |
4266 | if (wm8994->jackdet) |
4267 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); | |
2a8a856d MB |
4268 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994); |
4269 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994); | |
4270 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994); | |
9b7c525d MB |
4271 | if (wm8994->micdet_irq) |
4272 | free_irq(wm8994->micdet_irq, wm8994); | |
c7ebf932 | 4273 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) |
2a8a856d | 4274 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, |
c7ebf932 | 4275 | &wm8994->fll_locked[i]); |
2a8a856d | 4276 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, |
b30ead5f | 4277 | &wm8994->hubs); |
2a8a856d MB |
4278 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); |
4279 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); | |
4280 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); | |
a421a0e4 | 4281 | |
9e6e96a1 MB |
4282 | return ret; |
4283 | } | |
4284 | ||
34ff0f95 | 4285 | static int wm8994_codec_remove(struct snd_soc_codec *codec) |
9e6e96a1 | 4286 | { |
f0fba2ad | 4287 | struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec); |
2a8a856d | 4288 | struct wm8994 *control = wm8994->wm8994; |
c7ebf932 | 4289 | int i; |
9e6e96a1 MB |
4290 | |
4291 | wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
f0fba2ad | 4292 | |
39fb51a1 MB |
4293 | pm_runtime_disable(codec->dev); |
4294 | ||
c7ebf932 | 4295 | for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) |
2a8a856d | 4296 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i, |
c7ebf932 MB |
4297 | &wm8994->fll_locked[i]); |
4298 | ||
2a8a856d | 4299 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE, |
b30ead5f | 4300 | &wm8994->hubs); |
2a8a856d MB |
4301 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec); |
4302 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec); | |
4303 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec); | |
b30ead5f | 4304 | |
af6b6fe4 MB |
4305 | if (wm8994->jackdet) |
4306 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994); | |
4307 | ||
3a423157 MB |
4308 | switch (control->type) { |
4309 | case WM8994: | |
9b7c525d MB |
4310 | if (wm8994->micdet_irq) |
4311 | free_irq(wm8994->micdet_irq, wm8994); | |
2a8a856d | 4312 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, |
3a423157 | 4313 | wm8994); |
2a8a856d | 4314 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, |
3a423157 | 4315 | wm8994); |
2a8a856d | 4316 | wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET, |
3a423157 MB |
4317 | wm8994); |
4318 | break; | |
821edd2f | 4319 | |
81204c84 | 4320 | case WM1811: |
821edd2f | 4321 | case WM8958: |
9b7c525d MB |
4322 | if (wm8994->micdet_irq) |
4323 | free_irq(wm8994->micdet_irq, wm8994); | |
821edd2f | 4324 | break; |
3a423157 | 4325 | } |
34ff0f95 JJ |
4326 | release_firmware(wm8994->mbc); |
4327 | release_firmware(wm8994->mbc_vss); | |
4328 | release_firmware(wm8994->enh_eq); | |
24fb2b11 | 4329 | kfree(wm8994->retune_mobile_texts); |
9e6e96a1 MB |
4330 | return 0; |
4331 | } | |
4332 | ||
f0fba2ad LG |
4333 | static struct snd_soc_codec_driver soc_codec_dev_wm8994 = { |
4334 | .probe = wm8994_codec_probe, | |
4335 | .remove = wm8994_codec_remove, | |
4752a887 MB |
4336 | .suspend = wm8994_codec_suspend, |
4337 | .resume = wm8994_codec_resume, | |
f0fba2ad LG |
4338 | .set_bias_level = wm8994_set_bias_level, |
4339 | }; | |
4340 | ||
7a79e94e | 4341 | static int wm8994_probe(struct platform_device *pdev) |
f0fba2ad | 4342 | { |
2bc16ed8 MB |
4343 | struct wm8994_priv *wm8994; |
4344 | ||
4345 | wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv), | |
4346 | GFP_KERNEL); | |
4347 | if (wm8994 == NULL) | |
4348 | return -ENOMEM; | |
4349 | platform_set_drvdata(pdev, wm8994); | |
4350 | ||
4351 | wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent); | |
2bc16ed8 | 4352 | |
f0fba2ad LG |
4353 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994, |
4354 | wm8994_dai, ARRAY_SIZE(wm8994_dai)); | |
4355 | } | |
4356 | ||
7a79e94e | 4357 | static int wm8994_remove(struct platform_device *pdev) |
f0fba2ad LG |
4358 | { |
4359 | snd_soc_unregister_codec(&pdev->dev); | |
4360 | return 0; | |
4361 | } | |
4362 | ||
4752a887 MB |
4363 | #ifdef CONFIG_PM_SLEEP |
4364 | static int wm8994_suspend(struct device *dev) | |
4365 | { | |
4366 | struct wm8994_priv *wm8994 = dev_get_drvdata(dev); | |
4367 | ||
4368 | /* Drop down to power saving mode when system is suspended */ | |
4369 | if (wm8994->jackdet && !wm8994->active_refcount) | |
4370 | regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, | |
4371 | WM1811_JACKDET_MODE_MASK, | |
4372 | wm8994->jackdet_mode); | |
4373 | ||
4374 | return 0; | |
4375 | } | |
4376 | ||
4377 | static int wm8994_resume(struct device *dev) | |
4378 | { | |
4379 | struct wm8994_priv *wm8994 = dev_get_drvdata(dev); | |
4380 | ||
78b76dbe | 4381 | if (wm8994->jackdet && wm8994->jackdet_mode) |
4752a887 MB |
4382 | regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2, |
4383 | WM1811_JACKDET_MODE_MASK, | |
4384 | WM1811_JACKDET_MODE_AUDIO); | |
4385 | ||
4386 | return 0; | |
4387 | } | |
4388 | #endif | |
4389 | ||
4390 | static const struct dev_pm_ops wm8994_pm_ops = { | |
4391 | SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume) | |
4392 | }; | |
4393 | ||
9e6e96a1 MB |
4394 | static struct platform_driver wm8994_codec_driver = { |
4395 | .driver = { | |
4752a887 MB |
4396 | .name = "wm8994-codec", |
4397 | .owner = THIS_MODULE, | |
4398 | .pm = &wm8994_pm_ops, | |
4399 | }, | |
f0fba2ad | 4400 | .probe = wm8994_probe, |
7a79e94e | 4401 | .remove = wm8994_remove, |
9e6e96a1 MB |
4402 | }; |
4403 | ||
5bbcc3c0 | 4404 | module_platform_driver(wm8994_codec_driver); |
9e6e96a1 MB |
4405 | |
4406 | MODULE_DESCRIPTION("ASoC WM8994 driver"); | |
4407 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
4408 | MODULE_LICENSE("GPL"); | |
4409 | MODULE_ALIAS("platform:wm8994-codec"); |