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mfd: wm8994: Store platform data in device
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
bfd37bb5
MB		 49static struct {
50 unsigned int reg;
51 unsigned int mask;
52} wm8994_vu_bits[] = {
53 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
54 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
56 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
58 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
59 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
60 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
62 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63
64 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
65 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
67 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
69 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
71 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
73 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
75 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
76 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
77 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
79 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
80};
81
9e6e96a1
MB		 82static int wm8994_drc_base[] = {
83 WM8994_AIF1_DRC1_1,
84 WM8994_AIF1_DRC2_1,
85 WM8994_AIF2_DRC_1,
86};
87
88static int wm8994_retune_mobile_base[] = {
89 WM8994_AIF1_DAC1_EQ_GAINS_1,
90 WM8994_AIF1_DAC2_EQ_GAINS_1,
91 WM8994_AIF2_EQ_GAINS_1,
92};
93
b00adf76
MB		 94static void wm8958_default_micdet(u16 status, void *data);
95
af6b6fe4 96static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 97 { 32768, true, 1, 4 },
98 { 32768, false, 1, 1 },
604533de
MB		 99 { 44100 * 256, true, 7, 10 },
100 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 101};
102
af6b6fe4
MB		 103static const struct wm8958_micd_rate jackdet_rates[] = {
104 { 32768, true, 0, 1 },
105 { 32768, false, 0, 1 },
e9d9a968
MB		 106 { 44100 * 256, true, 10, 10 },
107 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 108};
109
b00adf76
MB		 110static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
111{
112 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
113 int best, i, sysclk, val;
114 bool idle;
af6b6fe4
MB		 115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
fcdc4de7
MB		 118 if (!(wm8994->pdata && wm8994->pdata->micd_rates) &&
119 wm8994->jack_cb != wm8958_default_micdet)
b00adf76
MB		 120 return;
121
122 idle = !wm8994->jack_mic;
123
124 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
125 if (sysclk & WM8994_SYSCLK_SRC)
126 sysclk = wm8994->aifclk[1];
127 else
128 sysclk = wm8994->aifclk[0];
129
cd1707a9
MB		 130 if (wm8994->pdata && wm8994->pdata->micd_rates) {
131 rates = wm8994->pdata->micd_rates;
132 num_rates = wm8994->pdata->num_micd_rates;
133 } else if (wm8994->jackdet) {
af6b6fe4
MB		 134 rates = jackdet_rates;
135 num_rates = ARRAY_SIZE(jackdet_rates);
136 } else {
137 rates = micdet_rates;
138 num_rates = ARRAY_SIZE(micdet_rates);
139 }
140
b00adf76 141 best = 0;
af6b6fe4
MB		 142 for (i = 0; i < num_rates; i++) {
143 if (rates[i].idle != idle)
b00adf76 144 continue;
af6b6fe4
MB		 145 if (abs(rates[i].sysclk - sysclk) <
146 abs(rates[best].sysclk - sysclk))
b00adf76 147 best = i;
af6b6fe4 148 else if (rates[best].idle != idle)
b00adf76
MB		 149 best = i;
150 }
151
af6b6fe4
MB		 152 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
153 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 154
3a334ada
MB		 155 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
156 rates[best].start, rates[best].rate, sysclk,
157 idle ? "idle" : "active");
158
b00adf76
MB		 159 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
160 WM8958_MICD_BIAS_STARTTIME_MASK |
161 WM8958_MICD_RATE_MASK, val);
162}
163
9e6e96a1
MB		 164static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
165{
b2c812e2 166 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 167 int rate;
168 int reg1 = 0;
169 int offset;
170
171 if (aif)
172 offset = 4;
173 else
174 offset = 0;
175
176 switch (wm8994->sysclk[aif]) {
177 case WM8994_SYSCLK_MCLK1:
178 rate = wm8994->mclk[0];
179 break;
180
181 case WM8994_SYSCLK_MCLK2:
182 reg1 |= 0x8;
183 rate = wm8994->mclk[1];
184 break;
185
186 case WM8994_SYSCLK_FLL1:
187 reg1 |= 0x10;
188 rate = wm8994->fll[0].out;
189 break;
190
191 case WM8994_SYSCLK_FLL2:
192 reg1 |= 0x18;
193 rate = wm8994->fll[1].out;
194 break;
195
196 default:
197 return -EINVAL;
198 }
199
200 if (rate >= 13500000) {
201 rate /= 2;
202 reg1 |= WM8994_AIF1CLK_DIV;
203
204 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
205 aif + 1, rate);
206 }
5e5e2bef 207
9e6e96a1
MB		 208 wm8994->aifclk[aif] = rate;
209
210 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
211 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
212 reg1);
213
214 return 0;
215}
216
217static int configure_clock(struct snd_soc_codec *codec)
218{
b2c812e2 219 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 220 int change, new;
9e6e96a1
MB		 221
222 /* Bring up the AIF clocks first */
223 configure_aif_clock(codec, 0);
224 configure_aif_clock(codec, 1);
225
226 /* Then switch CLK_SYS over to the higher of them; a change
227 * can only happen as a result of a clocking change which can
228 * only be made outside of DAPM so we can safely redo the
229 * clocking.
230 */
231
232 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 233 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
234 wm8958_micd_set_rate(codec);
9e6e96a1 235 return 0;
b00adf76 236 }
9e6e96a1
MB		 237
238 if (wm8994->aifclk[0] < wm8994->aifclk[1])
239 new = WM8994_SYSCLK_SRC;
240 else
241 new = 0;
242
04f45c49
AL		 243 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
244 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 245 if (change)
246 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 247
b00adf76
MB		 248 wm8958_micd_set_rate(codec);
249
9e6e96a1
MB		 250 return 0;
251}
252
253static int check_clk_sys(struct snd_soc_dapm_widget *source,
254 struct snd_soc_dapm_widget *sink)
255{
256 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
257 const char *clk;
258
259 /* Check what we're currently using for CLK_SYS */
260 if (reg & WM8994_SYSCLK_SRC)
261 clk = "AIF2CLK";
262 else
263 clk = "AIF1CLK";
264
265 return strcmp(source->name, clk) == 0;
266}
267
268static const char *sidetone_hpf_text[] = {
269 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
270};
271
272static const struct soc_enum sidetone_hpf =
273 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
274
146fd574
UK		 275static const char *adc_hpf_text[] = {
276 "HiFi", "Voice 1", "Voice 2", "Voice 3"
277};
278
279static const struct soc_enum aif1adc1_hpf =
280 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
281
282static const struct soc_enum aif1adc2_hpf =
283 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
284
285static const struct soc_enum aif2adc_hpf =
286 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
287
9e6e96a1
MB		 288static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 293static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 294static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 295
296#define WM8994_DRC_SWITCH(xname, reg, shift) \
297{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
298 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
299 .put = wm8994_put_drc_sw, \
300 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
301
302static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
303 struct snd_ctl_elem_value *ucontrol)
304{
305 struct soc_mixer_control *mc =
306 (struct soc_mixer_control *)kcontrol->private_value;
307 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
308 int mask, ret;
309
310 /* Can't enable both ADC and DAC paths simultaneously */
311 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
312 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
313 WM8994_AIF1ADC1R_DRC_ENA_MASK;
314 else
315 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
316
317 ret = snd_soc_read(codec, mc->reg);
318 if (ret < 0)
319 return ret;
320 if (ret & mask)
321 return -EINVAL;
322
323 return snd_soc_put_volsw(kcontrol, ucontrol);
324}
325
9e6e96a1
MB		 326static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
327{
b2c812e2 328 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 329 struct wm8994_pdata *pdata = wm8994->pdata;
330 int base = wm8994_drc_base[drc];
331 int cfg = wm8994->drc_cfg[drc];
332 int save, i;
333
334 /* Save any enables; the configuration should clear them. */
335 save = snd_soc_read(codec, base);
336 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
337 WM8994_AIF1ADC1R_DRC_ENA;
338
339 for (i = 0; i < WM8994_DRC_REGS; i++)
340 snd_soc_update_bits(codec, base + i, 0xffff,
341 pdata->drc_cfgs[cfg].regs[i]);
342
343 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
344 WM8994_AIF1ADC1L_DRC_ENA |
345 WM8994_AIF1ADC1R_DRC_ENA, save);
346}
347
348/* Icky as hell but saves code duplication */
349static int wm8994_get_drc(const char *name)
350{
351 if (strcmp(name, "AIF1DRC1 Mode") == 0)
352 return 0;
353 if (strcmp(name, "AIF1DRC2 Mode") == 0)
354 return 1;
355 if (strcmp(name, "AIF2DRC Mode") == 0)
356 return 2;
357 return -EINVAL;
358}
359
360static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
361 struct snd_ctl_elem_value *ucontrol)
362{
363 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 364 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 365 struct wm8994_pdata *pdata = wm8994->pdata;
366 int drc = wm8994_get_drc(kcontrol->id.name);
367 int value = ucontrol->value.integer.value[0];
368
369 if (drc < 0)
370 return drc;
371
372 if (value >= pdata->num_drc_cfgs)
373 return -EINVAL;
374
375 wm8994->drc_cfg[drc] = value;
376
377 wm8994_set_drc(codec, drc);
378
379 return 0;
380}
381
382static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
383 struct snd_ctl_elem_value *ucontrol)
384{
385 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 387 int drc = wm8994_get_drc(kcontrol->id.name);
388
389 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
390
391 return 0;
392}
393
394static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
395{
b2c812e2 396 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 397 struct wm8994_pdata *pdata = wm8994->pdata;
398 int base = wm8994_retune_mobile_base[block];
399 int iface, best, best_val, save, i, cfg;
400
401 if (!pdata || !wm8994->num_retune_mobile_texts)
402 return;
403
404 switch (block) {
405 case 0:
406 case 1:
407 iface = 0;
408 break;
409 case 2:
410 iface = 1;
411 break;
412 default:
413 return;
414 }
415
416 /* Find the version of the currently selected configuration
417 * with the nearest sample rate. */
418 cfg = wm8994->retune_mobile_cfg[block];
419 best = 0;
420 best_val = INT_MAX;
421 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
422 if (strcmp(pdata->retune_mobile_cfgs[i].name,
423 wm8994->retune_mobile_texts[cfg]) == 0 &&
424 abs(pdata->retune_mobile_cfgs[i].rate
425 - wm8994->dac_rates[iface]) < best_val) {
426 best = i;
427 best_val = abs(pdata->retune_mobile_cfgs[i].rate
428 - wm8994->dac_rates[iface]);
429 }
430 }
431
432 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
433 block,
434 pdata->retune_mobile_cfgs[best].name,
435 pdata->retune_mobile_cfgs[best].rate,
436 wm8994->dac_rates[iface]);
437
438 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 439 * current configuration.
9e6e96a1
MB		 440 */
441 save = snd_soc_read(codec, base);
442 save &= WM8994_AIF1DAC1_EQ_ENA;
443
444 for (i = 0; i < WM8994_EQ_REGS; i++)
445 snd_soc_update_bits(codec, base + i, 0xffff,
446 pdata->retune_mobile_cfgs[best].regs[i]);
447
448 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
449}
450
451/* Icky as hell but saves code duplication */
452static int wm8994_get_retune_mobile_block(const char *name)
453{
454 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
455 return 0;
456 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
457 return 1;
458 if (strcmp(name, "AIF2 EQ Mode") == 0)
459 return 2;
460 return -EINVAL;
461}
462
463static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
465{
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 467 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 468 struct wm8994_pdata *pdata = wm8994->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
493
494 return 0;
495}
496
96b101ef 497static const char *aif_chan_src_text[] = {
f554885f
MB		 498 "Left", "Right"
499};
500
96b101ef
MB		 501static const struct soc_enum aif1adcl_src =
502 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
503
504static const struct soc_enum aif1adcr_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
506
507static const struct soc_enum aif2adcl_src =
508 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
509
510static const struct soc_enum aif2adcr_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
512
f554885f 513static const struct soc_enum aif1dacl_src =
96b101ef 514 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 515
516static const struct soc_enum aif1dacr_src =
96b101ef 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 518
519static const struct soc_enum aif2dacl_src =
96b101ef 520 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 521
522static const struct soc_enum aif2dacr_src =
96b101ef 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 524
154b26aa
MB		 525static const char *osr_text[] = {
526 "Low Power", "High Performance",
527};
528
529static const struct soc_enum dac_osr =
530 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
531
532static const struct soc_enum adc_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
534
9e6e96a1
MB		 535static const struct snd_kcontrol_new wm8994_snd_controls[] = {
536SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
537 WM8994_AIF1_ADC1_RIGHT_VOLUME,
538 1, 119, 0, digital_tlv),
539SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
540 WM8994_AIF1_ADC2_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
543 WM8994_AIF2_ADC_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545
96b101ef
MB		 546SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
547SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 548SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
549SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 550
f554885f
MB		 551SOC_ENUM("AIF1DACL Source", aif1dacl_src),
552SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 553SOC_ENUM("AIF2DACL Source", aif2dacl_src),
554SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 555
9e6e96a1
MB		 556SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
557 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
558SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
559 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
560SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
561 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
562
563SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
564SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
565
566SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
567SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
568SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
569
570WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
571WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
572WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
573
574WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
575WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
576WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
577
578WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
579WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
580WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
581
582SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
583 5, 12, 0, st_tlv),
584SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
585 0, 12, 0, st_tlv),
586SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
587 5, 12, 0, st_tlv),
588SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
589 0, 12, 0, st_tlv),
590SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
591SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
592
146fd574
UK		 593SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
594SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
595
596SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
597SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
600SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
601
154b26aa
MB		 602SOC_ENUM("ADC OSR", adc_osr),
603SOC_ENUM("DAC OSR", dac_osr),
604
9e6e96a1
MB		 605SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
606 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
607SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
609
610SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
611 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
612SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
613 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
614
615SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
616 6, 1, 1, wm_hubs_spkmix_tlv),
617SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
618 2, 1, 1, wm_hubs_spkmix_tlv),
619
620SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
621 6, 1, 1, wm_hubs_spkmix_tlv),
622SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
623 2, 1, 1, wm_hubs_spkmix_tlv),
624
625SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
626 10, 15, 0, wm8994_3d_tlv),
458350b3 627SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 628 8, 1, 0),
629SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
630 10, 15, 0, wm8994_3d_tlv),
631SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
632 8, 1, 0),
458350b3 633SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 634 10, 15, 0, wm8994_3d_tlv),
458350b3 635SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 636 8, 1, 0),
637};
638
639static const struct snd_kcontrol_new wm8994_eq_controls[] = {
640SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661
662SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
663 eq_tlv),
664SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
665 eq_tlv),
666SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
667 eq_tlv),
668SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
669 eq_tlv),
670SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
671 eq_tlv),
672};
673
45a690f6
MB		 674static const struct snd_kcontrol_new wm8994_drc_controls[] = {
675SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
676 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
677 WM8994_AIF1ADC1R_DRC_ENA),
678SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
679 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
680 WM8994_AIF1ADC2R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
682 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
683 WM8994_AIF2ADCR_DRC_ENA),
684};
685
1ddc07d0
MB		 686static const char *wm8958_ng_text[] = {
687 "30ms", "125ms", "250ms", "500ms",
688};
689
690static const struct soc_enum wm8958_aif1dac1_ng_hold =
691 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
692 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
693
694static const struct soc_enum wm8958_aif1dac2_ng_hold =
695 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
696 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
697
698static const struct soc_enum wm8958_aif2dac_ng_hold =
699 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
700 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
701
c4431df0
MB		 702static const struct snd_kcontrol_new wm8958_snd_controls[] = {
703SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 704
705SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
706 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
707SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
708SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
709 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
710 7, 1, ng_tlv),
711
712SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
713 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
714SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
715SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
716 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
717 7, 1, ng_tlv),
718
719SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
720 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
721SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
722SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
723 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
724 7, 1, ng_tlv),
c4431df0
MB		 725};
726
81204c84
MB		 727static const struct snd_kcontrol_new wm1811_snd_controls[] = {
728SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
729 mixin_boost_tlv),
730SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
731 mixin_boost_tlv),
732};
733
af6b6fe4
MB		 734/* We run all mode setting through a function to enforce audio mode */
735static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
736{
737 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
738
28e33269
MB		 739 if (!wm8994->jackdet || !wm8994->jack_cb)
740 return;
741
af6b6fe4
MB		 742 if (wm8994->active_refcount)
743 mode = WM1811_JACKDET_MODE_AUDIO;
744
4752a887 745 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 746 return;
747
4752a887 748 wm8994->jackdet_mode = mode;
1defde2a 749
4752a887
MB		 750 /* Always use audio mode to detect while the system is active */
751 if (mode != WM1811_JACKDET_MODE_NONE)
752 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 753
4752a887
MB		 754 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
755 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 756}
757
758static void active_reference(struct snd_soc_codec *codec)
759{
760 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
761
762 mutex_lock(&wm8994->accdet_lock);
763
764 wm8994->active_refcount++;
765
766 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
767 wm8994->active_refcount);
768
1defde2a
MB		 769 /* If we're using jack detection go into audio mode */
770 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 771
772 mutex_unlock(&wm8994->accdet_lock);
773}
774
775static void active_dereference(struct snd_soc_codec *codec)
776{
777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
778 u16 mode;
779
780 mutex_lock(&wm8994->accdet_lock);
781
782 wm8994->active_refcount--;
783
784 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
785 wm8994->active_refcount);
786
787 if (wm8994->active_refcount == 0) {
788 /* Go into appropriate detection only mode */
1defde2a
MB		 789 if (wm8994->jack_mic || wm8994->mic_detecting)
790 mode = WM1811_JACKDET_MODE_MIC;
791 else
792 mode = WM1811_JACKDET_MODE_JACK;
793
794 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 795 }
796
797 mutex_unlock(&wm8994->accdet_lock);
798}
799
9e6e96a1
MB		 800static int clk_sys_event(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802{
803 struct snd_soc_codec *codec = w->codec;
99af79df 804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 return configure_clock(codec);
809
99af79df
MB		 810 case SND_SOC_DAPM_POST_PMU:
811 /*
812 * JACKDET won't run until we start the clock and it
813 * only reports deltas, make sure we notify the state
814 * up the stack on startup. Use a *very* generous
815 * timeout for paranoia, there's no urgency and we
816 * don't want false reports.
817 */
818 if (wm8994->jackdet && !wm8994->clk_has_run) {
819 schedule_delayed_work(&wm8994->jackdet_bootstrap,
820 msecs_to_jiffies(1000));
821 wm8994->clk_has_run = true;
822 }
823 break;
824
9e6e96a1
MB		 825 case SND_SOC_DAPM_POST_PMD:
826 configure_clock(codec);
827 break;
828 }
829
830 return 0;
831}
832
4b7ed83a
MB		 833static void vmid_reference(struct snd_soc_codec *codec)
834{
835 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
836
db966f8a
MB		 837 pm_runtime_get_sync(codec->dev);
838
4b7ed83a
MB		 839 wm8994->vmid_refcount++;
840
841 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
842 wm8994->vmid_refcount);
843
844 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 845 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 846 WM8994_LINEOUT1_DISCH |
22f8d055 847 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 848
f7085641
MB		 849 wm_hubs_vmid_ena(codec);
850
22f8d055
MB		 851 switch (wm8994->vmid_mode) {
852 default:
cbd71f30 853 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 854 case WM8994_VMID_NORMAL:
855 /* Startup bias, VMID ramp & buffer */
856 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
857 WM8994_BIAS_SRC |
858 WM8994_VMID_DISCH |
859 WM8994_STARTUP_BIAS_ENA |
860 WM8994_VMID_BUF_ENA |
861 WM8994_VMID_RAMP_MASK,
862 WM8994_BIAS_SRC |
863 WM8994_STARTUP_BIAS_ENA |
864 WM8994_VMID_BUF_ENA |
a3a1d9d2 865 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 866
867 /* Main bias enable, VMID=2x40k */
868 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
869 WM8994_BIAS_ENA |
870 WM8994_VMID_SEL_MASK,
871 WM8994_BIAS_ENA | 0x2);
872
a3a1d9d2 873 msleep(300);
22f8d055
MB		 874
875 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
876 WM8994_VMID_RAMP_MASK |
877 WM8994_BIAS_SRC,
878 0);
879 break;
cc6d5a8c 880
22f8d055
MB		 881 case WM8994_VMID_FORCE:
882 /* Startup bias, slow VMID ramp & buffer */
883 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
884 WM8994_BIAS_SRC |
885 WM8994_VMID_DISCH |
886 WM8994_STARTUP_BIAS_ENA |
887 WM8994_VMID_BUF_ENA |
888 WM8994_VMID_RAMP_MASK,
889 WM8994_BIAS_SRC |
890 WM8994_STARTUP_BIAS_ENA |
891 WM8994_VMID_BUF_ENA |
892 (0x2 << WM8994_VMID_RAMP_SHIFT));
893
894 /* Main bias enable, VMID=2x40k */
895 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
896 WM8994_BIAS_ENA |
897 WM8994_VMID_SEL_MASK,
898 WM8994_BIAS_ENA | 0x2);
899
900 msleep(400);
901
902 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
903 WM8994_VMID_RAMP_MASK |
904 WM8994_BIAS_SRC,
905 0);
906 break;
907 }
4b7ed83a
MB		 908 }
909}
910
911static void vmid_dereference(struct snd_soc_codec *codec)
912{
913 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
914
915 wm8994->vmid_refcount--;
916
917 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
918 wm8994->vmid_refcount);
919
920 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 921 if (wm8994->hubs.lineout1_se)
922 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
923 WM8994_LINEOUT1N_ENA |
924 WM8994_LINEOUT1P_ENA,
925 WM8994_LINEOUT1N_ENA |
926 WM8994_LINEOUT1P_ENA);
927
928 if (wm8994->hubs.lineout2_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT2N_ENA |
931 WM8994_LINEOUT2P_ENA,
932 WM8994_LINEOUT2N_ENA |
933 WM8994_LINEOUT2P_ENA);
934
935 /* Start discharging VMID */
4b7ed83a
MB		 936 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
937 WM8994_BIAS_SRC |
22f8d055 938 WM8994_VMID_DISCH,
4b7ed83a 939 WM8994_BIAS_SRC |
22f8d055 940 WM8994_VMID_DISCH);
4b7ed83a 941
f95be9d6
MB		 942 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
943 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 944
f95be9d6 945 msleep(400);
e85b26ce 946
22f8d055 947 /* Active discharge */
4b7ed83a
MB		 948 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
949 WM8994_LINEOUT1_DISCH |
950 WM8994_LINEOUT2_DISCH,
951 WM8994_LINEOUT1_DISCH |
952 WM8994_LINEOUT2_DISCH);
953
22f8d055
MB		 954 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
955 WM8994_LINEOUT1N_ENA |
956 WM8994_LINEOUT1P_ENA |
957 WM8994_LINEOUT2N_ENA |
958 WM8994_LINEOUT2P_ENA, 0);
959
4b7ed83a
MB		 960 /* Switch off startup biases */
961 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
962 WM8994_BIAS_SRC |
963 WM8994_STARTUP_BIAS_ENA |
964 WM8994_VMID_BUF_ENA |
965 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 966
967 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 968 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 969 }
db966f8a
MB		 970
971 pm_runtime_put(codec->dev);
4b7ed83a
MB		 972}
973
974static int vmid_event(struct snd_soc_dapm_widget *w,
975 struct snd_kcontrol *kcontrol, int event)
976{
977 struct snd_soc_codec *codec = w->codec;
978
979 switch (event) {
980 case SND_SOC_DAPM_PRE_PMU:
981 vmid_reference(codec);
982 break;
983
984 case SND_SOC_DAPM_POST_PMD:
985 vmid_dereference(codec);
986 break;
987 }
988
989 return 0;
990}
991
c340304d 992static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 993{
9e6e96a1
MB		 994 int source = 0; /* GCC flow analysis can't track enable */
995 int reg, reg_r;
996
c340304d 997 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 998 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
999 switch (reg) {
1000 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1001 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1002 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1003 break;
1004 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1005 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1006 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1007 break;
1008 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1009 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1010 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1011 break;
1012 default:
ee839a21 1013 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1014 return false;
9e6e96a1
MB		 1015 }
1016
1017 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1018 if (reg_r != reg) {
ee839a21 1019 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1020 return false;
9e6e96a1
MB		 1021 }
1022
c340304d
MB		 1023 /* Set the source up */
1024 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1025 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1026
c340304d 1027 return true;
9e6e96a1
MB		 1028}
1029
1a38336b
MB		 1030static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1031 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1032{
1033 struct snd_soc_codec *codec = w->codec;
1a38336b
MB		 1034 struct wm8994 *control = codec->control_data;
1035 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1036 int i;
1a38336b
MB		 1037 int dac;
1038 int adc;
1039 int val;
1040
1041 switch (control->type) {
1042 case WM8994:
1043 case WM8958:
1044 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1045 break;
1046 default:
1047 break;
1048 }
173efa09
DP		 1049
1050 switch (event) {
1051 case SND_SOC_DAPM_PRE_PMU:
1a38336b
MB		 1052 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1053 if ((val & WM8994_AIF1ADCL_SRC) &&
1054 (val & WM8994_AIF1ADCR_SRC))
1055 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1056 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1057 !(val & WM8994_AIF1ADCR_SRC))
1058 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1059 else
1060 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1061 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1062
1063 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1064 if ((val & WM8994_AIF1DACL_SRC) &&
1065 (val & WM8994_AIF1DACR_SRC))
1066 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1067 else if (!(val & WM8994_AIF1DACL_SRC) &&
1068 !(val & WM8994_AIF1DACR_SRC))
1069 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1070 else
1071 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1072 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1073
1074 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1075 mask, adc);
1076 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1077 mask, dac);
1078 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1079 WM8994_AIF1DSPCLK_ENA |
1080 WM8994_SYSDSPCLK_ENA,
1081 WM8994_AIF1DSPCLK_ENA |
1082 WM8994_SYSDSPCLK_ENA);
1083 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1084 WM8994_AIF1ADC1R_ENA |
1085 WM8994_AIF1ADC1L_ENA |
1086 WM8994_AIF1ADC2R_ENA |
1087 WM8994_AIF1ADC2L_ENA);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1089 WM8994_AIF1DAC1R_ENA |
1090 WM8994_AIF1DAC1L_ENA |
1091 WM8994_AIF1DAC2R_ENA |
1092 WM8994_AIF1DAC2L_ENA);
173efa09 1093 break;
173efa09 1094
bfd37bb5
MB		 1095 case SND_SOC_DAPM_POST_PMU:
1096 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1097 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1098 snd_soc_read(codec,
1099 wm8994_vu_bits[i].reg));
1100 break;
1101
1a38336b
MB		 1102 case SND_SOC_DAPM_PRE_PMD:
1103 case SND_SOC_DAPM_POST_PMD:
1104 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1105 mask, 0);
1106 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1107 mask, 0);
1108
1109 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1110 if (val & WM8994_AIF2DSPCLK_ENA)
1111 val = WM8994_SYSDSPCLK_ENA;
1112 else
1113 val = 0;
1114 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1115 WM8994_SYSDSPCLK_ENA |
1116 WM8994_AIF1DSPCLK_ENA, val);
1117 break;
1118 }
c6b7b570 1119
173efa09
DP		 1120 return 0;
1121}
1122
1a38336b
MB		 1123static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1124 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1125{
1126 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1127 int i;
1a38336b
MB		 1128 int dac;
1129 int adc;
1130 int val;
173efa09
DP		 1131
1132 switch (event) {
1a38336b
MB		 1133 case SND_SOC_DAPM_PRE_PMU:
1134 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1135 if ((val & WM8994_AIF2ADCL_SRC) &&
1136 (val & WM8994_AIF2ADCR_SRC))
1137 adc = WM8994_AIF2ADCR_ENA;
1138 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1139 !(val & WM8994_AIF2ADCR_SRC))
1140 adc = WM8994_AIF2ADCL_ENA;
1141 else
1142 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1143
1144
1145 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1146 if ((val & WM8994_AIF2DACL_SRC) &&
1147 (val & WM8994_AIF2DACR_SRC))
1148 dac = WM8994_AIF2DACR_ENA;
1149 else if (!(val & WM8994_AIF2DACL_SRC) &&
1150 !(val & WM8994_AIF2DACR_SRC))
1151 dac = WM8994_AIF2DACL_ENA;
1152 else
1153 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1154
1155 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1156 WM8994_AIF2ADCL_ENA |
1157 WM8994_AIF2ADCR_ENA, adc);
1158 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1159 WM8994_AIF2DACL_ENA |
1160 WM8994_AIF2DACR_ENA, dac);
1161 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1162 WM8994_AIF2DSPCLK_ENA |
1163 WM8994_SYSDSPCLK_ENA,
1164 WM8994_AIF2DSPCLK_ENA |
1165 WM8994_SYSDSPCLK_ENA);
1166 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1167 WM8994_AIF2ADCL_ENA |
1168 WM8994_AIF2ADCR_ENA,
1169 WM8994_AIF2ADCL_ENA |
1170 WM8994_AIF2ADCR_ENA);
1171 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1172 WM8994_AIF2DACL_ENA |
1173 WM8994_AIF2DACR_ENA,
1174 WM8994_AIF2DACL_ENA |
1175 WM8994_AIF2DACR_ENA);
1176 break;
1177
bfd37bb5
MB		 1178 case SND_SOC_DAPM_POST_PMU:
1179 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1180 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1181 snd_soc_read(codec,
1182 wm8994_vu_bits[i].reg));
1183 break;
1184
1a38336b 1185 case SND_SOC_DAPM_PRE_PMD:
173efa09 1186 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1187 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1188 WM8994_AIF2DACL_ENA |
1189 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1190 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1191 WM8994_AIF2ADCL_ENA |
1192 WM8994_AIF2ADCR_ENA, 0);
1193
1194 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1195 if (val & WM8994_AIF1DSPCLK_ENA)
1196 val = WM8994_SYSDSPCLK_ENA;
1197 else
1198 val = 0;
1199 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1200 WM8994_SYSDSPCLK_ENA |
1201 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1202 break;
1203 }
1204
1205 return 0;
1206}
1207
1a38336b
MB		 1208static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1209 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1210{
1211 struct snd_soc_codec *codec = w->codec;
1212 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1213
1214 switch (event) {
1215 case SND_SOC_DAPM_PRE_PMU:
1216 wm8994->aif1clk_enable = 1;
1217 break;
a3cff81a
DP		 1218 case SND_SOC_DAPM_POST_PMD:
1219 wm8994->aif1clk_disable = 1;
1220 break;
173efa09
DP		 1221 }
1222
1223 return 0;
1224}
1225
1a38336b
MB		 1226static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1227 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1228{
1229 struct snd_soc_codec *codec = w->codec;
1230 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1231
1232 switch (event) {
1233 case SND_SOC_DAPM_PRE_PMU:
1234 wm8994->aif2clk_enable = 1;
1235 break;
a3cff81a
DP		 1236 case SND_SOC_DAPM_POST_PMD:
1237 wm8994->aif2clk_disable = 1;
1238 break;
173efa09
DP		 1239 }
1240
1241 return 0;
1242}
1243
1a38336b
MB		 1244static int late_enable_ev(struct snd_soc_dapm_widget *w,
1245 struct snd_kcontrol *kcontrol, int event)
1246{
1247 struct snd_soc_codec *codec = w->codec;
1248 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1249
1250 switch (event) {
1251 case SND_SOC_DAPM_PRE_PMU:
1252 if (wm8994->aif1clk_enable) {
c8fdc1b5 1253 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1254 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1255 WM8994_AIF1CLK_ENA_MASK,
1256 WM8994_AIF1CLK_ENA);
c8fdc1b5 1257 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1258 wm8994->aif1clk_enable = 0;
1259 }
1260 if (wm8994->aif2clk_enable) {
c8fdc1b5 1261 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1262 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1263 WM8994_AIF2CLK_ENA_MASK,
1264 WM8994_AIF2CLK_ENA);
c8fdc1b5 1265 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1266 wm8994->aif2clk_enable = 0;
1267 }
1268 break;
1269 }
1270
1271 /* We may also have postponed startup of DSP, handle that. */
1272 wm8958_aif_ev(w, kcontrol, event);
1273
1274 return 0;
1275}
1276
1277static int late_disable_ev(struct snd_soc_dapm_widget *w,
1278 struct snd_kcontrol *kcontrol, int event)
1279{
1280 struct snd_soc_codec *codec = w->codec;
1281 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1282
1283 switch (event) {
1284 case SND_SOC_DAPM_POST_PMD:
1285 if (wm8994->aif1clk_disable) {
c8fdc1b5 1286 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1287 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1288 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1289 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1290 wm8994->aif1clk_disable = 0;
1291 }
1292 if (wm8994->aif2clk_disable) {
c8fdc1b5 1293 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1294 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1295 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1296 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1297 wm8994->aif2clk_disable = 0;
1298 }
1299 break;
1300 }
1301
1302 return 0;
1303}
1304
04d28681
DP		 1305static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1306 struct snd_kcontrol *kcontrol, int event)
1307{
1308 late_enable_ev(w, kcontrol, event);
1309 return 0;
1310}
1311
b462c6e6
DP		 1312static int micbias_ev(struct snd_soc_dapm_widget *w,
1313 struct snd_kcontrol *kcontrol, int event)
1314{
1315 late_enable_ev(w, kcontrol, event);
1316 return 0;
1317}
1318
c52fd021
DP		 1319static int dac_ev(struct snd_soc_dapm_widget *w,
1320 struct snd_kcontrol *kcontrol, int event)
1321{
1322 struct snd_soc_codec *codec = w->codec;
1323 unsigned int mask = 1 << w->shift;
1324
1325 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1326 mask, mask);
1327 return 0;
1328}
1329
9e6e96a1
MB		 1330static const char *adc_mux_text[] = {
1331 "ADC",
1332 "DMIC",
1333};
1334
1335static const struct soc_enum adc_enum =
1336 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1337
1338static const struct snd_kcontrol_new adcl_mux =
1339 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1340
1341static const struct snd_kcontrol_new adcr_mux =
1342 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1343
1344static const struct snd_kcontrol_new left_speaker_mixer[] = {
1345SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1346SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1347SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1348SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1349SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1350};
1351
1352static const struct snd_kcontrol_new right_speaker_mixer[] = {
1353SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1354SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1355SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1356SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1357SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1358};
1359
1360/* Debugging; dump chip status after DAPM transitions */
1361static int post_ev(struct snd_soc_dapm_widget *w,
1362 struct snd_kcontrol *kcontrol, int event)
1363{
1364 struct snd_soc_codec *codec = w->codec;
1365 dev_dbg(codec->dev, "SRC status: %x\n",
1366 snd_soc_read(codec,
1367 WM8994_RATE_STATUS));
1368 return 0;
1369}
1370
1371static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1372SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1373 1, 1, 0),
1374SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1375 0, 1, 0),
1376};
1377
1378static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1379SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1380 1, 1, 0),
1381SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1382 0, 1, 0),
1383};
1384
a3257ba8
MB		 1385static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1386SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1387 1, 1, 0),
1388SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1389 0, 1, 0),
1390};
1391
1392static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1393SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1394 1, 1, 0),
1395SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1396 0, 1, 0),
1397};
1398
9e6e96a1
MB		 1399static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1400SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1401 5, 1, 0),
1402SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1403 4, 1, 0),
1404SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1405 2, 1, 0),
1406SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1407 1, 1, 0),
1408SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1409 0, 1, 0),
1410};
1411
1412static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1413SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1414 5, 1, 0),
1415SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1416 4, 1, 0),
1417SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1418 2, 1, 0),
1419SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1420 1, 1, 0),
1421SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1422 0, 1, 0),
1423};
1424
1425#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1426{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1427 .info = snd_soc_info_volsw, \
1428 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1429 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1430
1431static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1432 struct snd_ctl_elem_value *ucontrol)
1433{
9d03545d
JN		 1434 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1435 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1436 struct snd_soc_codec *codec = w->codec;
1437 int ret;
1438
1439 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1440
c340304d 1441 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1442
1443 return ret;
1444}
1445
1446static const struct snd_kcontrol_new dac1l_mix[] = {
1447WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1448 5, 1, 0),
1449WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1450 4, 1, 0),
1451WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1452 2, 1, 0),
1453WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1454 1, 1, 0),
1455WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 0, 1, 0),
1457};
1458
1459static const struct snd_kcontrol_new dac1r_mix[] = {
1460WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1461 5, 1, 0),
1462WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1463 4, 1, 0),
1464WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1465 2, 1, 0),
1466WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1467 1, 1, 0),
1468WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 0, 1, 0),
1470};
1471
1472static const char *sidetone_text[] = {
1473 "ADC/DMIC1", "DMIC2",
1474};
1475
1476static const struct soc_enum sidetone1_enum =
1477 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1478
1479static const struct snd_kcontrol_new sidetone1_mux =
1480 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1481
1482static const struct soc_enum sidetone2_enum =
1483 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1484
1485static const struct snd_kcontrol_new sidetone2_mux =
1486 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1487
1488static const char *aif1dac_text[] = {
1489 "AIF1DACDAT", "AIF3DACDAT",
1490};
1491
1492static const struct soc_enum aif1dac_enum =
1493 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1494
1495static const struct snd_kcontrol_new aif1dac_mux =
1496 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1497
1498static const char *aif2dac_text[] = {
1499 "AIF2DACDAT", "AIF3DACDAT",
1500};
1501
1502static const struct soc_enum aif2dac_enum =
1503 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1504
1505static const struct snd_kcontrol_new aif2dac_mux =
1506 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1507
1508static const char *aif2adc_text[] = {
1509 "AIF2ADCDAT", "AIF3DACDAT",
1510};
1511
1512static const struct soc_enum aif2adc_enum =
1513 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1514
1515static const struct snd_kcontrol_new aif2adc_mux =
1516 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1517
1518static const char *aif3adc_text[] = {
c4431df0 1519 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1520};
1521
c4431df0 1522static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1523 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1524
c4431df0
MB		 1525static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1526 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1527
1528static const struct soc_enum wm8958_aif3adc_enum =
1529 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1530
1531static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1532 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1533
1534static const char *mono_pcm_out_text[] = {
c1a4ecd9 1535 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1536};
1537
1538static const struct soc_enum mono_pcm_out_enum =
1539 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1540
1541static const struct snd_kcontrol_new mono_pcm_out_mux =
1542 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1543
1544static const char *aif2dac_src_text[] = {
1545 "AIF2", "AIF3",
1546};
1547
1548/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1549static const struct soc_enum aif2dacl_src_enum =
1550 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1551
1552static const struct snd_kcontrol_new aif2dacl_src_mux =
1553 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1554
1555static const struct soc_enum aif2dacr_src_enum =
1556 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1557
1558static const struct snd_kcontrol_new aif2dacr_src_mux =
1559 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1560
173efa09 1561static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1562SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1564SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1565 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1566
1567SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1568 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1569SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1570 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1571SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1572 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1573SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1574 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1575SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1576 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1577
1578SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1579 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1580 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1581SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1582 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1583 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1584SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1585 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1586SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1587 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1588
1589SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1590};
1591
1592static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1593SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1594 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1595 SND_SOC_DAPM_PRE_PMD),
1a38336b 1596SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1597 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1598 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1599SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1600SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1601 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1602SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1603 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1604SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1605SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1606};
1607
c52fd021
DP		 1608static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1609SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1610 dac_ev, SND_SOC_DAPM_PRE_PMU),
1611SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1612 dac_ev, SND_SOC_DAPM_PRE_PMU),
1613SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1614 dac_ev, SND_SOC_DAPM_PRE_PMU),
1615SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1616 dac_ev, SND_SOC_DAPM_PRE_PMU),
1617};
1618
1619static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1620SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1621SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1622SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1623SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1624};
1625
04d28681 1626static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1627SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1628 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1629SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1630 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1631};
1632
1633static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1634SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1635SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1636};
1637
9e6e96a1
MB		 1638static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1639SND_SOC_DAPM_INPUT("DMIC1DAT"),
1640SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1641SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1642
b462c6e6
DP		 1643SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1644 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1645SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1646 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1647
9e6e96a1 1648SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1649 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1650 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1651
1a38336b
MB		 1652SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1653SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1654SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1655
7f94de48 1656SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1657 0, SND_SOC_NOPM, 9, 0),
7f94de48 1658SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1659 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1660SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1661 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1662 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1663SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1664 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1665 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1666
7f94de48 1667SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1668 0, SND_SOC_NOPM, 11, 0),
7f94de48 1669SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1670 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1671SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1672 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1673 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1674SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1675 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1676 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1677
1678SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1679 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1680SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1681 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1682
a3257ba8
MB		 1683SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1684 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1685SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1686 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1687
9e6e96a1
MB		 1688SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1689 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1690SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1691 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1692
1693SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1694SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1695
1696SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1697 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1698SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1699 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1700
1701SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1702 SND_SOC_NOPM, 13, 0),
9e6e96a1 1703SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1704 SND_SOC_NOPM, 12, 0),
d6addcc9 1705SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1706 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1707 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1708SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1709 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1710 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1711
5567d8c6
MB		 1712SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1713SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1714SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1715SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1716
1717SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1718SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1719SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1720
5567d8c6
MB		 1721SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1722SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1723
1724SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1725
1726SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1727SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1728SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1729SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1730
1731/* Power is done with the muxes since the ADC power also controls the
1732 * downsampling chain, the chip will automatically manage the analogue
1733 * specific portions.
1734 */
1735SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1736SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1737
9e6e96a1
MB		 1738SND_SOC_DAPM_POST("Debug log", post_ev),
1739};
1740
c4431df0
MB		 1741static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1742SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1743};
9e6e96a1 1744
c4431df0 1745static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1746SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1747SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1748SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1749SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1750SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1751};
1752
1753static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1754 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1755 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1756
1757 { "DSP1CLK", NULL, "CLK_SYS" },
1758 { "DSP2CLK", NULL, "CLK_SYS" },
1759 { "DSPINTCLK", NULL, "CLK_SYS" },
1760
1761 { "AIF1ADC1L", NULL, "AIF1CLK" },
1762 { "AIF1ADC1L", NULL, "DSP1CLK" },
1763 { "AIF1ADC1R", NULL, "AIF1CLK" },
1764 { "AIF1ADC1R", NULL, "DSP1CLK" },
1765 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1766
1767 { "AIF1DAC1L", NULL, "AIF1CLK" },
1768 { "AIF1DAC1L", NULL, "DSP1CLK" },
1769 { "AIF1DAC1R", NULL, "AIF1CLK" },
1770 { "AIF1DAC1R", NULL, "DSP1CLK" },
1771 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1772
1773 { "AIF1ADC2L", NULL, "AIF1CLK" },
1774 { "AIF1ADC2L", NULL, "DSP1CLK" },
1775 { "AIF1ADC2R", NULL, "AIF1CLK" },
1776 { "AIF1ADC2R", NULL, "DSP1CLK" },
1777 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1778
1779 { "AIF1DAC2L", NULL, "AIF1CLK" },
1780 { "AIF1DAC2L", NULL, "DSP1CLK" },
1781 { "AIF1DAC2R", NULL, "AIF1CLK" },
1782 { "AIF1DAC2R", NULL, "DSP1CLK" },
1783 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1784
1785 { "AIF2ADCL", NULL, "AIF2CLK" },
1786 { "AIF2ADCL", NULL, "DSP2CLK" },
1787 { "AIF2ADCR", NULL, "AIF2CLK" },
1788 { "AIF2ADCR", NULL, "DSP2CLK" },
1789 { "AIF2ADCR", NULL, "DSPINTCLK" },
1790
1791 { "AIF2DACL", NULL, "AIF2CLK" },
1792 { "AIF2DACL", NULL, "DSP2CLK" },
1793 { "AIF2DACR", NULL, "AIF2CLK" },
1794 { "AIF2DACR", NULL, "DSP2CLK" },
1795 { "AIF2DACR", NULL, "DSPINTCLK" },
1796
1797 { "DMIC1L", NULL, "DMIC1DAT" },
1798 { "DMIC1L", NULL, "CLK_SYS" },
1799 { "DMIC1R", NULL, "DMIC1DAT" },
1800 { "DMIC1R", NULL, "CLK_SYS" },
1801 { "DMIC2L", NULL, "DMIC2DAT" },
1802 { "DMIC2L", NULL, "CLK_SYS" },
1803 { "DMIC2R", NULL, "DMIC2DAT" },
1804 { "DMIC2R", NULL, "CLK_SYS" },
1805
1806 { "ADCL", NULL, "AIF1CLK" },
1807 { "ADCL", NULL, "DSP1CLK" },
1808 { "ADCL", NULL, "DSPINTCLK" },
1809
1810 { "ADCR", NULL, "AIF1CLK" },
1811 { "ADCR", NULL, "DSP1CLK" },
1812 { "ADCR", NULL, "DSPINTCLK" },
1813
1814 { "ADCL Mux", "ADC", "ADCL" },
1815 { "ADCL Mux", "DMIC", "DMIC1L" },
1816 { "ADCR Mux", "ADC", "ADCR" },
1817 { "ADCR Mux", "DMIC", "DMIC1R" },
1818
1819 { "DAC1L", NULL, "AIF1CLK" },
1820 { "DAC1L", NULL, "DSP1CLK" },
1821 { "DAC1L", NULL, "DSPINTCLK" },
1822
1823 { "DAC1R", NULL, "AIF1CLK" },
1824 { "DAC1R", NULL, "DSP1CLK" },
1825 { "DAC1R", NULL, "DSPINTCLK" },
1826
1827 { "DAC2L", NULL, "AIF2CLK" },
1828 { "DAC2L", NULL, "DSP2CLK" },
1829 { "DAC2L", NULL, "DSPINTCLK" },
1830
1831 { "DAC2R", NULL, "AIF2DACR" },
1832 { "DAC2R", NULL, "AIF2CLK" },
1833 { "DAC2R", NULL, "DSP2CLK" },
1834 { "DAC2R", NULL, "DSPINTCLK" },
1835
1836 { "TOCLK", NULL, "CLK_SYS" },
1837
5567d8c6
MB		 1838 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1839 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1840 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1841
1842 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1843 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1844 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1845
9e6e96a1
MB		 1846 /* AIF1 outputs */
1847 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1848 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1849 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1850
1851 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1852 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1853 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1854
a3257ba8
MB		 1855 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1856 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1857 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1858
1859 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1860 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1861 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1862
9e6e96a1
MB		 1863 /* Pin level routing for AIF3 */
1864 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1865 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1866 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1867 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1868
9e6e96a1
MB		 1869 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1870 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1871 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1872 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1873 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1874 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1875 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1876
1877 /* DAC1 inputs */
9e6e96a1
MB		 1878 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1879 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1880 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1881 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1882 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1883
9e6e96a1
MB		 1884 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1885 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1886 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1887 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1888 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1889
1890 /* DAC2/AIF2 outputs */
1891 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1892 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1893 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1894 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1895 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1896 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1897
1898 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1899 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1900 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1901 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1902 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1903 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1904
7f94de48
MB		 1905 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1906 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1907 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1908 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1909
9e6e96a1
MB		 1910 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1911
1912 /* AIF3 output */
1913 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1914 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1915 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1916 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1917 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1918 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1919 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1920 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1921
1922 /* Sidetone */
1923 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1924 { "Left Sidetone", "DMIC2", "DMIC2L" },
1925 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1926 { "Right Sidetone", "DMIC2", "DMIC2R" },
1927
1928 /* Output stages */
1929 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1930 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1931
1932 { "SPKL", "DAC1 Switch", "DAC1L" },
1933 { "SPKL", "DAC2 Switch", "DAC2L" },
1934
1935 { "SPKR", "DAC1 Switch", "DAC1R" },
1936 { "SPKR", "DAC2 Switch", "DAC2R" },
1937
1938 { "Left Headphone Mux", "DAC", "DAC1L" },
1939 { "Right Headphone Mux", "DAC", "DAC1R" },
1940};
1941
173efa09
DP		 1942static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1943 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1944 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1945 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1946 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1947 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1948 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1949 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1950 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1951};
1952
1953static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1954 { "DAC1L", NULL, "DAC1L Mixer" },
1955 { "DAC1R", NULL, "DAC1R Mixer" },
1956 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1957 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1958};
1959
6ed8f148
MB		 1960static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1961 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1962 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1963 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1964 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1965 { "MICBIAS1", NULL, "CLK_SYS" },
1966 { "MICBIAS1", NULL, "MICBIAS Supply" },
1967 { "MICBIAS2", NULL, "CLK_SYS" },
1968 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1969};
1970
c4431df0
MB		 1971static const struct snd_soc_dapm_route wm8994_intercon[] = {
1972 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1973 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1974 { "MICBIAS1", NULL, "VMID" },
1975 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1976};
1977
1978static const struct snd_soc_dapm_route wm8958_intercon[] = {
1979 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1980 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1981
1982 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1983 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1984 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1985 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1986
8c5b842b
MB		 1987 { "AIF3DACDAT", NULL, "AIF3" },
1988 { "AIF3ADCDAT", NULL, "AIF3" },
1989
c4431df0
MB		 1990 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1991 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1992
1993 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1994};
1995
9e6e96a1
MB		 1996/* The size in bits of the FLL divide multiplied by 10
1997 * to allow rounding later */
1998#define FIXED_FLL_SIZE ((1 << 16) * 10)
1999
2000struct fll_div {
2001 u16 outdiv;
2002 u16 n;
2003 u16 k;
2004 u16 clk_ref_div;
2005 u16 fll_fratio;
2006};
2007
2008static int wm8994_get_fll_config(struct fll_div *fll,
2009 int freq_in, int freq_out)
2010{
2011 u64 Kpart;
2012 unsigned int K, Ndiv, Nmod;
2013
2014 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2015
2016 /* Scale the input frequency down to <= 13.5MHz */
2017 fll->clk_ref_div = 0;
2018 while (freq_in > 13500000) {
2019 fll->clk_ref_div++;
2020 freq_in /= 2;
2021
2022 if (fll->clk_ref_div > 3)
2023 return -EINVAL;
2024 }
2025 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2026
2027 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2028 fll->outdiv = 3;
2029 while (freq_out * (fll->outdiv + 1) < 90000000) {
2030 fll->outdiv++;
2031 if (fll->outdiv > 63)
2032 return -EINVAL;
2033 }
2034 freq_out *= fll->outdiv + 1;
2035 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2036
2037 if (freq_in > 1000000) {
2038 fll->fll_fratio = 0;
7d48a6ac
MB		 2039 } else if (freq_in > 256000) {
2040 fll->fll_fratio = 1;
2041 freq_in *= 2;
2042 } else if (freq_in > 128000) {
2043 fll->fll_fratio = 2;
2044 freq_in *= 4;
2045 } else if (freq_in > 64000) {
9e6e96a1
MB		 2046 fll->fll_fratio = 3;
2047 freq_in *= 8;
7d48a6ac
MB		 2048 } else {
2049 fll->fll_fratio = 4;
2050 freq_in *= 16;
9e6e96a1
MB		 2051 }
2052 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2053
2054 /* Now, calculate N.K */
2055 Ndiv = freq_out / freq_in;
2056
2057 fll->n = Ndiv;
2058 Nmod = freq_out % freq_in;
2059 pr_debug("Nmod=%d\n", Nmod);
2060
2061 /* Calculate fractional part - scale up so we can round. */
2062 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2063
2064 do_div(Kpart, freq_in);
2065
2066 K = Kpart & 0xFFFFFFFF;
2067
2068 if ((K % 10) >= 5)
2069 K += 5;
2070
2071 /* Move down to proper range now rounding is done */
2072 fll->k = K / 10;
2073
2074 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2075
2076 return 0;
2077}
2078
f0fba2ad 2079static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2080 unsigned int freq_in, unsigned int freq_out)
2081{
b2c812e2 2082 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2083 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2084 int reg_offset, ret;
2085 struct fll_div fll;
e413ba88 2086 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2087 unsigned long timeout;
4b7ed83a 2088 bool was_enabled;
9e6e96a1 2089
9e6e96a1
MB		 2090 switch (id) {
2091 case WM8994_FLL1:
2092 reg_offset = 0;
2093 id = 0;
e413ba88 2094 aif_src = 0x10;
9e6e96a1
MB		 2095 break;
2096 case WM8994_FLL2:
2097 reg_offset = 0x20;
2098 id = 1;
e413ba88 2099 aif_src = 0x18;
9e6e96a1
MB		 2100 break;
2101 default:
2102 return -EINVAL;
2103 }
2104
4b7ed83a
MB		 2105 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2106 was_enabled = reg & WM8994_FLL1_ENA;
2107
136ff2a2 2108 switch (src) {
7add84aa
MB		 2109 case 0:
2110 /* Allow no source specification when stopping */
2111 if (freq_out)
2112 return -EINVAL;
4514e899 2113 src = wm8994->fll[id].src;
7add84aa 2114 break;
136ff2a2
MB		 2115 case WM8994_FLL_SRC_MCLK1:
2116 case WM8994_FLL_SRC_MCLK2:
2117 case WM8994_FLL_SRC_LRCLK:
2118 case WM8994_FLL_SRC_BCLK:
2119 break;
fbfe6983
MB		 2120 case WM8994_FLL_SRC_INTERNAL:
2121 freq_in = 12000000;
2122 freq_out = 12000000;
2123 break;
136ff2a2
MB		 2124 default:
2125 return -EINVAL;
2126 }
2127
9e6e96a1
MB		 2128 /* Are we changing anything? */
2129 if (wm8994->fll[id].src == src &&
2130 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2131 return 0;
2132
2133 /* If we're stopping the FLL redo the old config - no
2134 * registers will actually be written but we avoid GCC flow
2135 * analysis bugs spewing warnings.
2136 */
2137 if (freq_out)
2138 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
2139 else
2140 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
2141 wm8994->fll[id].out);
2142 if (ret < 0)
2143 return ret;
2144
e413ba88
MB		 2145 /* Make sure that we're not providing SYSCLK right now */
2146 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2147 if (clk1 & WM8994_SYSCLK_SRC)
2148 aif_reg = WM8994_AIF2_CLOCKING_1;
2149 else
2150 aif_reg = WM8994_AIF1_CLOCKING_1;
2151 reg = snd_soc_read(codec, aif_reg);
2152
2153 if ((reg & WM8994_AIF1CLK_ENA) &&
2154 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2155 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2156 id + 1);
2157 return -EBUSY;
2158 }
9e6e96a1
MB		 2159
2160 /* We always need to disable the FLL while reconfiguring */
2161 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2162 WM8994_FLL1_ENA, 0);
2163
20dc24a9 2164 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2165 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2166 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2167 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2168 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2169 goto out;
2170 }
2171
9e6e96a1
MB		 2172 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2173 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2174 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2175 WM8994_FLL1_OUTDIV_MASK |
2176 WM8994_FLL1_FRATIO_MASK, reg);
2177
b16db745
MB		 2178 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2179 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2180
2181 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2182 WM8994_FLL1_N_MASK,
7435d4ee 2183 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1
MB		 2184
2185 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2186 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2187 WM8994_FLL1_REFCLK_DIV_MASK |
2188 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2189 ((src == WM8994_FLL_SRC_INTERNAL)
2190 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2191 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2192 (src - 1));
9e6e96a1 2193
f0f5039c
MB		 2194 /* Clear any pending completion from a previous failure */
2195 try_wait_for_completion(&wm8994->fll_locked[id]);
2196
9e6e96a1
MB		 2197 /* Enable (with fractional mode if required) */
2198 if (freq_out) {
4b7ed83a
MB		 2199 /* Enable VMID if we need it */
2200 if (!was_enabled) {
af6b6fe4
MB		 2201 active_reference(codec);
2202
4b7ed83a
MB		 2203 switch (control->type) {
2204 case WM8994:
2205 vmid_reference(codec);
2206 break;
2207 case WM8958:
2208 if (wm8994->revision < 1)
2209 vmid_reference(codec);
2210 break;
2211 default:
2212 break;
2213 }
2214 }
2215
fbfe6983
MB		 2216 reg = WM8994_FLL1_ENA;
2217
9e6e96a1 2218 if (fll.k)
fbfe6983
MB		 2219 reg |= WM8994_FLL1_FRAC;
2220 if (src == WM8994_FLL_SRC_INTERNAL)
2221 reg |= WM8994_FLL1_OSC_ENA;
2222
9e6e96a1 2223 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2224 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2225 WM8994_FLL1_FRAC, reg);
8e9ddf81 2226
c7ebf932
MB		 2227 if (wm8994->fll_locked_irq) {
2228 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2229 msecs_to_jiffies(10));
2230 if (timeout == 0)
2231 dev_warn(codec->dev,
2232 "Timed out waiting for FLL lock\n");
2233 } else {
2234 msleep(5);
2235 }
4b7ed83a
MB		 2236 } else {
2237 if (was_enabled) {
2238 switch (control->type) {
2239 case WM8994:
2240 vmid_dereference(codec);
2241 break;
2242 case WM8958:
2243 if (wm8994->revision < 1)
2244 vmid_dereference(codec);
2245 break;
2246 default:
2247 break;
2248 }
af6b6fe4
MB		 2249
2250 active_dereference(codec);
4b7ed83a 2251 }
9e6e96a1
MB		 2252 }
2253
20dc24a9 2254out:
9e6e96a1
MB		 2255 wm8994->fll[id].in = freq_in;
2256 wm8994->fll[id].out = freq_out;
136ff2a2 2257 wm8994->fll[id].src = src;
9e6e96a1 2258
9e6e96a1
MB		 2259 configure_clock(codec);
2260
cd22000a
MB		 2261 /*
2262 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2263 * for detection.
2264 */
2265 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2266 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2267 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2268 WM8994_AIF1CLK_RATE_MASK, 0x1);
2269 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2270 WM8994_AIF2CLK_RATE_MASK, 0x1);
2271 }
2272
9e6e96a1
MB		 2273 return 0;
2274}
2275
c7ebf932
MB		 2276static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2277{
2278 struct completion *completion = data;
2279
2280 complete(completion);
2281
2282 return IRQ_HANDLED;
2283}
f0fba2ad 2284
66b47fdb
MB		 2285static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2286
f0fba2ad
LG		 2287static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2288 unsigned int freq_in, unsigned int freq_out)
2289{
2290 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2291}
2292
9e6e96a1
MB		 2293static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2294 int clk_id, unsigned int freq, int dir)
2295{
2296 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2297 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2298 int i;
9e6e96a1
MB		 2299
2300 switch (dai->id) {
2301 case 1:
2302 case 2:
2303 break;
2304
2305 default:
2306 /* AIF3 shares clocking with AIF1/2 */
2307 return -EINVAL;
2308 }
2309
2310 switch (clk_id) {
2311 case WM8994_SYSCLK_MCLK1:
2312 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2313 wm8994->mclk[0] = freq;
2314 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2315 dai->id, freq);
2316 break;
2317
2318 case WM8994_SYSCLK_MCLK2:
2319 /* TODO: Set GPIO AF */
2320 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2321 wm8994->mclk[1] = freq;
2322 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2323 dai->id, freq);
2324 break;
2325
2326 case WM8994_SYSCLK_FLL1:
2327 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2328 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2329 break;
2330
2331 case WM8994_SYSCLK_FLL2:
2332 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2333 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2334 break;
2335
66b47fdb
MB		 2336 case WM8994_SYSCLK_OPCLK:
2337 /* Special case - a division (times 10) is given and
c1a4ecd9 2338 * no effect on main clocking.
66b47fdb
MB		 2339 */
2340 if (freq) {
2341 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2342 if (opclk_divs[i] == freq)
2343 break;
2344 if (i == ARRAY_SIZE(opclk_divs))
2345 return -EINVAL;
2346 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2347 WM8994_OPCLK_DIV_MASK, i);
2348 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2349 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2350 } else {
2351 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2352 WM8994_OPCLK_ENA, 0);
2353 }
2354
9e6e96a1
MB		 2355 default:
2356 return -EINVAL;
2357 }
2358
2359 configure_clock(codec);
2360
6730049a
MB		 2361 /*
2362 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2363 * for detection.
2364 */
2365 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2366 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2367 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2368 WM8994_AIF1CLK_RATE_MASK, 0x1);
2369 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2370 WM8994_AIF2CLK_RATE_MASK, 0x1);
2371 }
2372
9e6e96a1
MB		 2373 return 0;
2374}
2375
2376static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2377 enum snd_soc_bias_level level)
2378{
b6b05691 2379 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2380 struct wm8994 *control = wm8994->wm8994;
b6b05691 2381
5f2f3890
MB		 2382 wm_hubs_set_bias_level(codec, level);
2383
9e6e96a1
MB		 2384 switch (level) {
2385 case SND_SOC_BIAS_ON:
2386 break;
2387
2388 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2389 /* MICBIAS into regulating mode */
2390 switch (control->type) {
2391 case WM8958:
2392 case WM1811:
2393 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2394 WM8958_MICB1_MODE, 0);
2395 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2396 WM8958_MICB2_MODE, 0);
2397 break;
2398 default:
2399 break;
2400 }
af6b6fe4
MB		 2401
2402 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2403 active_reference(codec);
9e6e96a1
MB		 2404 break;
2405
2406 case SND_SOC_BIAS_STANDBY:
ce6120cc 2407 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2408 switch (control->type) {
8bc3c2c2
MB		 2409 case WM8958:
2410 if (wm8994->revision == 0) {
2411 /* Optimise performance for rev A */
8bc3c2c2
MB		 2412 snd_soc_update_bits(codec,
2413 WM8958_CHARGE_PUMP_2,
2414 WM8958_CP_DISCH,
2415 WM8958_CP_DISCH);
2416 }
2417 break;
81204c84 2418
462835e4 2419 default:
81204c84 2420 break;
b6b05691 2421 }
9e6e96a1
MB		 2422
2423 /* Discharge LINEOUT1 & 2 */
2424 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2425 WM8994_LINEOUT1_DISCH |
2426 WM8994_LINEOUT2_DISCH,
2427 WM8994_LINEOUT1_DISCH |
2428 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2429 }
2430
af6b6fe4
MB		 2431 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2432 active_dereference(codec);
2433
500fa30e
MB		 2434 /* MICBIAS into bypass mode on newer devices */
2435 switch (control->type) {
2436 case WM8958:
2437 case WM1811:
2438 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2439 WM8958_MICB1_MODE,
2440 WM8958_MICB1_MODE);
2441 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2442 WM8958_MICB2_MODE,
2443 WM8958_MICB2_MODE);
2444 break;
2445 default:
2446 break;
2447 }
9e6e96a1
MB		 2448 break;
2449
2450 case SND_SOC_BIAS_OFF:
4105ab84 2451 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2452 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2453 break;
2454 }
5f2f3890 2455
ce6120cc 2456 codec->dapm.bias_level = level;
af6b6fe4 2457
22f8d055
MB		 2458 return 0;
2459}
2460
2461int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2462{
2463 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2464
2465 switch (mode) {
2466 case WM8994_VMID_NORMAL:
2467 if (wm8994->hubs.lineout1_se) {
2468 snd_soc_dapm_disable_pin(&codec->dapm,
2469 "LINEOUT1N Driver");
2470 snd_soc_dapm_disable_pin(&codec->dapm,
2471 "LINEOUT1P Driver");
2472 }
2473 if (wm8994->hubs.lineout2_se) {
2474 snd_soc_dapm_disable_pin(&codec->dapm,
2475 "LINEOUT2N Driver");
2476 snd_soc_dapm_disable_pin(&codec->dapm,
2477 "LINEOUT2P Driver");
2478 }
2479
2480 /* Do the sync with the old mode to allow it to clean up */
2481 snd_soc_dapm_sync(&codec->dapm);
2482 wm8994->vmid_mode = mode;
2483 break;
2484
2485 case WM8994_VMID_FORCE:
2486 if (wm8994->hubs.lineout1_se) {
2487 snd_soc_dapm_force_enable_pin(&codec->dapm,
2488 "LINEOUT1N Driver");
2489 snd_soc_dapm_force_enable_pin(&codec->dapm,
2490 "LINEOUT1P Driver");
2491 }
2492 if (wm8994->hubs.lineout2_se) {
2493 snd_soc_dapm_force_enable_pin(&codec->dapm,
2494 "LINEOUT2N Driver");
2495 snd_soc_dapm_force_enable_pin(&codec->dapm,
2496 "LINEOUT2P Driver");
2497 }
2498
2499 wm8994->vmid_mode = mode;
2500 snd_soc_dapm_sync(&codec->dapm);
2501 break;
2502
2503 default:
2504 return -EINVAL;
2505 }
2506
9e6e96a1
MB		 2507 return 0;
2508}
2509
2510static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2511{
2512 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2513 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2514 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2515 int ms_reg;
2516 int aif1_reg;
2517 int ms = 0;
2518 int aif1 = 0;
2519
2520 switch (dai->id) {
2521 case 1:
2522 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2523 aif1_reg = WM8994_AIF1_CONTROL_1;
2524 break;
2525 case 2:
2526 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2527 aif1_reg = WM8994_AIF2_CONTROL_1;
2528 break;
2529 default:
2530 return -EINVAL;
2531 }
2532
2533 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2534 case SND_SOC_DAIFMT_CBS_CFS:
2535 break;
2536 case SND_SOC_DAIFMT_CBM_CFM:
2537 ms = WM8994_AIF1_MSTR;
2538 break;
2539 default:
2540 return -EINVAL;
2541 }
2542
2543 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2544 case SND_SOC_DAIFMT_DSP_B:
2545 aif1 |= WM8994_AIF1_LRCLK_INV;
2546 case SND_SOC_DAIFMT_DSP_A:
2547 aif1 |= 0x18;
2548 break;
2549 case SND_SOC_DAIFMT_I2S:
2550 aif1 |= 0x10;
2551 break;
2552 case SND_SOC_DAIFMT_RIGHT_J:
2553 break;
2554 case SND_SOC_DAIFMT_LEFT_J:
2555 aif1 |= 0x8;
2556 break;
2557 default:
2558 return -EINVAL;
2559 }
2560
2561 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2562 case SND_SOC_DAIFMT_DSP_A:
2563 case SND_SOC_DAIFMT_DSP_B:
2564 /* frame inversion not valid for DSP modes */
2565 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2566 case SND_SOC_DAIFMT_NB_NF:
2567 break;
2568 case SND_SOC_DAIFMT_IB_NF:
2569 aif1 |= WM8994_AIF1_BCLK_INV;
2570 break;
2571 default:
2572 return -EINVAL;
2573 }
2574 break;
2575
2576 case SND_SOC_DAIFMT_I2S:
2577 case SND_SOC_DAIFMT_RIGHT_J:
2578 case SND_SOC_DAIFMT_LEFT_J:
2579 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2580 case SND_SOC_DAIFMT_NB_NF:
2581 break;
2582 case SND_SOC_DAIFMT_IB_IF:
2583 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2584 break;
2585 case SND_SOC_DAIFMT_IB_NF:
2586 aif1 |= WM8994_AIF1_BCLK_INV;
2587 break;
2588 case SND_SOC_DAIFMT_NB_IF:
2589 aif1 |= WM8994_AIF1_LRCLK_INV;
2590 break;
2591 default:
2592 return -EINVAL;
2593 }
2594 break;
2595 default:
2596 return -EINVAL;
2597 }
2598
c4431df0
MB		 2599 /* The AIF2 format configuration needs to be mirrored to AIF3
2600 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2601 switch (control->type) {
2602 case WM1811:
2603 case WM8958:
2604 if (dai->id == 2)
2605 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2606 WM8994_AIF1_LRCLK_INV |
2607 WM8958_AIF3_FMT_MASK, aif1);
2608 break;
2609
2610 default:
2611 break;
2612 }
c4431df0 2613
9e6e96a1
MB		 2614 snd_soc_update_bits(codec, aif1_reg,
2615 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2616 WM8994_AIF1_FMT_MASK,
2617 aif1);
2618 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2619 ms);
2620
2621 return 0;
2622}
2623
2624static struct {
2625 int val, rate;
2626} srs[] = {
2627 { 0, 8000 },
2628 { 1, 11025 },
2629 { 2, 12000 },
2630 { 3, 16000 },
2631 { 4, 22050 },
2632 { 5, 24000 },
2633 { 6, 32000 },
2634 { 7, 44100 },
2635 { 8, 48000 },
2636 { 9, 88200 },
2637 { 10, 96000 },
2638};
2639
2640static int fs_ratios[] = {
2641 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2642};
2643
2644static int bclk_divs[] = {
2645 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2646 640, 880, 960, 1280, 1760, 1920
2647};
2648
2649static int wm8994_hw_params(struct snd_pcm_substream *substream,
2650 struct snd_pcm_hw_params *params,
2651 struct snd_soc_dai *dai)
2652{
2653 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2654 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2655 int aif1_reg;
b1e43d93 2656 int aif2_reg;
9e6e96a1
MB		 2657 int bclk_reg;
2658 int lrclk_reg;
2659 int rate_reg;
2660 int aif1 = 0;
b1e43d93 2661 int aif2 = 0;
9e6e96a1
MB		 2662 int bclk = 0;
2663 int lrclk = 0;
2664 int rate_val = 0;
2665 int id = dai->id - 1;
2666
2667 int i, cur_val, best_val, bclk_rate, best;
2668
2669 switch (dai->id) {
2670 case 1:
2671 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2672 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2673 bclk_reg = WM8994_AIF1_BCLK;
2674 rate_reg = WM8994_AIF1_RATE;
2675 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2676 wm8994->lrclk_shared[0]) {
9e6e96a1 2677 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2678 } else {
9e6e96a1 2679 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2680 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2681 }
9e6e96a1
MB		 2682 break;
2683 case 2:
2684 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2685 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2686 bclk_reg = WM8994_AIF2_BCLK;
2687 rate_reg = WM8994_AIF2_RATE;
2688 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2689 wm8994->lrclk_shared[1]) {
9e6e96a1 2690 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2691 } else {
9e6e96a1 2692 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2693 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2694 }
9e6e96a1
MB		 2695 break;
2696 default:
2697 return -EINVAL;
2698 }
2699
b8edf3e5 2700 bclk_rate = params_rate(params) * 4;
9e6e96a1
MB		 2701 switch (params_format(params)) {
2702 case SNDRV_PCM_FORMAT_S16_LE:
2703 bclk_rate *= 16;
2704 break;
2705 case SNDRV_PCM_FORMAT_S20_3LE:
2706 bclk_rate *= 20;
2707 aif1 |= 0x20;
2708 break;
2709 case SNDRV_PCM_FORMAT_S24_LE:
2710 bclk_rate *= 24;
2711 aif1 |= 0x40;
2712 break;
2713 case SNDRV_PCM_FORMAT_S32_LE:
2714 bclk_rate *= 32;
2715 aif1 |= 0x60;
2716 break;
2717 default:
2718 return -EINVAL;
2719 }
2720
2721 /* Try to find an appropriate sample rate; look for an exact match. */
2722 for (i = 0; i < ARRAY_SIZE(srs); i++)
2723 if (srs[i].rate == params_rate(params))
2724 break;
2725 if (i == ARRAY_SIZE(srs))
2726 return -EINVAL;
2727 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2728
2729 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2730 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2731 dai->id, wm8994->aifclk[id], bclk_rate);
2732
b1e43d93
MB		 2733 if (params_channels(params) == 1 &&
2734 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2735 aif2 |= WM8994_AIF1_MONO;
2736
9e6e96a1
MB		 2737 if (wm8994->aifclk[id] == 0) {
2738 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2739 return -EINVAL;
2740 }
2741
2742 /* AIFCLK/fs ratio; look for a close match in either direction */
2743 best = 0;
2744 best_val = abs((fs_ratios[0] * params_rate(params))
2745 - wm8994->aifclk[id]);
2746 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2747 cur_val = abs((fs_ratios[i] * params_rate(params))
2748 - wm8994->aifclk[id]);
2749 if (cur_val >= best_val)
2750 continue;
2751 best = i;
2752 best_val = cur_val;
2753 }
2754 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2755 dai->id, fs_ratios[best]);
2756 rate_val |= best;
2757
2758 /* We may not get quite the right frequency if using
2759 * approximate clocks so look for the closest match that is
2760 * higher than the target (we need to ensure that there enough
2761 * BCLKs to clock out the samples).
2762 */
2763 best = 0;
2764 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2765 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2766 if (cur_val < 0) /* BCLK table is sorted */
2767 break;
2768 best = i;
2769 }
07cd8ada 2770 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2771 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2772 bclk_divs[best], bclk_rate);
2773 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2774
2775 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2776 if (!lrclk) {
2777 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2778 bclk_rate);
2779 return -EINVAL;
2780 }
9e6e96a1
MB		 2781 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2782 lrclk, bclk_rate / lrclk);
2783
2784 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2785 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2786 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2787 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2788 lrclk);
2789 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2790 WM8994_AIF1CLK_RATE_MASK, rate_val);
2791
2792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2793 switch (dai->id) {
2794 case 1:
2795 wm8994->dac_rates[0] = params_rate(params);
2796 wm8994_set_retune_mobile(codec, 0);
2797 wm8994_set_retune_mobile(codec, 1);
2798 break;
2799 case 2:
2800 wm8994->dac_rates[1] = params_rate(params);
2801 wm8994_set_retune_mobile(codec, 2);
2802 break;
2803 }
2804 }
2805
2806 return 0;
2807}
2808
c4431df0
MB		 2809static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2810 struct snd_pcm_hw_params *params,
2811 struct snd_soc_dai *dai)
2812{
2813 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2814 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2815 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2816 int aif1_reg;
2817 int aif1 = 0;
2818
2819 switch (dai->id) {
2820 case 3:
2821 switch (control->type) {
81204c84 2822 case WM1811:
c4431df0
MB		 2823 case WM8958:
2824 aif1_reg = WM8958_AIF3_CONTROL_1;
2825 break;
2826 default:
2827 return 0;
2828 }
2829 default:
2830 return 0;
2831 }
2832
2833 switch (params_format(params)) {
2834 case SNDRV_PCM_FORMAT_S16_LE:
2835 break;
2836 case SNDRV_PCM_FORMAT_S20_3LE:
2837 aif1 |= 0x20;
2838 break;
2839 case SNDRV_PCM_FORMAT_S24_LE:
2840 aif1 |= 0x40;
2841 break;
2842 case SNDRV_PCM_FORMAT_S32_LE:
2843 aif1 |= 0x60;
2844 break;
2845 default:
2846 return -EINVAL;
2847 }
2848
2849 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2850}
2851
9e6e96a1
MB		 2852static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2853{
2854 struct snd_soc_codec *codec = codec_dai->codec;
2855 int mute_reg;
2856 int reg;
2857
2858 switch (codec_dai->id) {
2859 case 1:
2860 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2861 break;
2862 case 2:
2863 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2864 break;
2865 default:
2866 return -EINVAL;
2867 }
2868
2869 if (mute)
2870 reg = WM8994_AIF1DAC1_MUTE;
2871 else
2872 reg = 0;
2873
2874 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2875
2876 return 0;
2877}
2878
778a76e2
MB		 2879static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2880{
2881 struct snd_soc_codec *codec = codec_dai->codec;
2882 int reg, val, mask;
2883
2884 switch (codec_dai->id) {
2885 case 1:
2886 reg = WM8994_AIF1_MASTER_SLAVE;
2887 mask = WM8994_AIF1_TRI;
2888 break;
2889 case 2:
2890 reg = WM8994_AIF2_MASTER_SLAVE;
2891 mask = WM8994_AIF2_TRI;
2892 break;
778a76e2
MB		 2893 default:
2894 return -EINVAL;
2895 }
2896
2897 if (tristate)
2898 val = mask;
2899 else
2900 val = 0;
2901
78b3fb46 2902 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2903}
2904
d09f3ecf
MB		 2905static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2906{
2907 struct snd_soc_codec *codec = dai->codec;
2908
2909 /* Disable the pulls on the AIF if we're using it to save power. */
2910 snd_soc_update_bits(codec, WM8994_GPIO_3,
2911 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2912 snd_soc_update_bits(codec, WM8994_GPIO_4,
2913 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2914 snd_soc_update_bits(codec, WM8994_GPIO_5,
2915 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2916
2917 return 0;
2918}
2919
9e6e96a1
MB		 2920#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2921
2922#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2923 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2924
85e7652d 2925static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2926 .set_sysclk = wm8994_set_dai_sysclk,
2927 .set_fmt = wm8994_set_dai_fmt,
2928 .hw_params = wm8994_hw_params,
2929 .digital_mute = wm8994_aif_mute,
2930 .set_pll = wm8994_set_fll,
778a76e2 2931 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2932};
2933
85e7652d 2934static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2935 .set_sysclk = wm8994_set_dai_sysclk,
2936 .set_fmt = wm8994_set_dai_fmt,
2937 .hw_params = wm8994_hw_params,
2938 .digital_mute = wm8994_aif_mute,
2939 .set_pll = wm8994_set_fll,
778a76e2
MB		 2940 .set_tristate = wm8994_set_tristate,
2941};
2942
85e7652d 2943static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2944 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 2945};
2946
f0fba2ad 2947static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2948 {
f0fba2ad 2949 .name = "wm8994-aif1",
8c7f78b3 2950 .id = 1,
9e6e96a1
MB		 2951 .playback = {
2952 .stream_name = "AIF1 Playback",
b1e43d93 2953 .channels_min = 1,
9e6e96a1
MB		 2954 .channels_max = 2,
2955 .rates = WM8994_RATES,
2956 .formats = WM8994_FORMATS,
99b0292d 2957 .sig_bits = 24,
9e6e96a1
MB		 2958 },
2959 .capture = {
2960 .stream_name = "AIF1 Capture",
b1e43d93 2961 .channels_min = 1,
9e6e96a1
MB		 2962 .channels_max = 2,
2963 .rates = WM8994_RATES,
2964 .formats = WM8994_FORMATS,
99b0292d 2965 .sig_bits = 24,
9e6e96a1
MB		 2966 },
2967 .ops = &wm8994_aif1_dai_ops,
2968 },
2969 {
f0fba2ad 2970 .name = "wm8994-aif2",
8c7f78b3 2971 .id = 2,
9e6e96a1
MB		 2972 .playback = {
2973 .stream_name = "AIF2 Playback",
b1e43d93 2974 .channels_min = 1,
9e6e96a1
MB		 2975 .channels_max = 2,
2976 .rates = WM8994_RATES,
2977 .formats = WM8994_FORMATS,
99b0292d 2978 .sig_bits = 24,
9e6e96a1
MB		 2979 },
2980 .capture = {
2981 .stream_name = "AIF2 Capture",
b1e43d93 2982 .channels_min = 1,
9e6e96a1
MB		 2983 .channels_max = 2,
2984 .rates = WM8994_RATES,
2985 .formats = WM8994_FORMATS,
99b0292d 2986 .sig_bits = 24,
9e6e96a1 2987 },
d09f3ecf 2988 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2989 .ops = &wm8994_aif2_dai_ops,
2990 },
2991 {
f0fba2ad 2992 .name = "wm8994-aif3",
8c7f78b3 2993 .id = 3,
9e6e96a1
MB		 2994 .playback = {
2995 .stream_name = "AIF3 Playback",
b1e43d93 2996 .channels_min = 1,
9e6e96a1
MB		 2997 .channels_max = 2,
2998 .rates = WM8994_RATES,
2999 .formats = WM8994_FORMATS,
99b0292d 3000 .sig_bits = 24,
9e6e96a1 3001 },
a8462bde 3002 .capture = {
9e6e96a1 3003 .stream_name = "AIF3 Capture",
b1e43d93 3004 .channels_min = 1,
9e6e96a1
MB		 3005 .channels_max = 2,
3006 .rates = WM8994_RATES,
3007 .formats = WM8994_FORMATS,
99b0292d
MB		 3008 .sig_bits = 24,
3009 },
778a76e2 3010 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3011 }
3012};
9e6e96a1
MB		 3013
3014#ifdef CONFIG_PM
4752a887 3015static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3016{
b2c812e2 3017 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3018 int i, ret;
3019
3020 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3021 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3022 sizeof(struct wm8994_fll_config));
f0fba2ad 3023 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3024 if (ret < 0)
3025 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3026 i + 1, ret);
3027 }
3028
3029 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3030
3031 return 0;
3032}
3033
4752a887 3034static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3035{
b2c812e2 3036 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3037 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 3038 int i, ret;
c52fd021
DP		 3039 unsigned int val, mask;
3040
3041 if (wm8994->revision < 4) {
3042 /* force a HW read */
d9a7666f
MB		 3043 ret = regmap_read(control->regmap,
3044 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 3045
3046 /* modify the cache only */
3047 codec->cache_only = 1;
3048 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
3049 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
3050 val &= mask;
3051 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
3052 mask, val);
3053 codec->cache_only = 0;
3054 }
9e6e96a1 3055
9e6e96a1 3056 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3057 if (!wm8994->fll_suspend[i].out)
3058 continue;
3059
f0fba2ad 3060 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3061 wm8994->fll_suspend[i].src,
3062 wm8994->fll_suspend[i].in,
3063 wm8994->fll_suspend[i].out);
3064 if (ret < 0)
3065 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3066 i + 1, ret);
3067 }
3068
3069 return 0;
3070}
3071#else
4752a887
MB		 3072#define wm8994_codec_suspend NULL
3073#define wm8994_codec_resume NULL
9e6e96a1
MB		 3074#endif
3075
3076static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3077{
8cb8e83b 3078 struct snd_soc_codec *codec = wm8994->hubs.codec;
9e6e96a1
MB		 3079 struct wm8994_pdata *pdata = wm8994->pdata;
3080 struct snd_kcontrol_new controls[] = {
3081 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3082 wm8994->retune_mobile_enum,
3083 wm8994_get_retune_mobile_enum,
3084 wm8994_put_retune_mobile_enum),
3085 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3086 wm8994->retune_mobile_enum,
3087 wm8994_get_retune_mobile_enum,
3088 wm8994_put_retune_mobile_enum),
3089 SOC_ENUM_EXT("AIF2 EQ Mode",
3090 wm8994->retune_mobile_enum,
3091 wm8994_get_retune_mobile_enum,
3092 wm8994_put_retune_mobile_enum),
3093 };
3094 int ret, i, j;
3095 const char **t;
3096
3097 /* We need an array of texts for the enum API but the number
3098 * of texts is likely to be less than the number of
3099 * configurations due to the sample rate dependency of the
3100 * configurations. */
3101 wm8994->num_retune_mobile_texts = 0;
3102 wm8994->retune_mobile_texts = NULL;
3103 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3104 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3105 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3106 wm8994->retune_mobile_texts[j]) == 0)
3107 break;
3108 }
3109
3110 if (j != wm8994->num_retune_mobile_texts)
3111 continue;
3112
3113 /* Expand the array... */
3114 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3115 sizeof(char *) *
9e6e96a1
MB		 3116 (wm8994->num_retune_mobile_texts + 1),
3117 GFP_KERNEL);
3118 if (t == NULL)
3119 continue;
3120
3121 /* ...store the new entry... */
c1a4ecd9 3122 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3123 pdata->retune_mobile_cfgs[i].name;
3124
3125 /* ...and remember the new version. */
3126 wm8994->num_retune_mobile_texts++;
3127 wm8994->retune_mobile_texts = t;
3128 }
3129
3130 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3131 wm8994->num_retune_mobile_texts);
3132
3133 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3134 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3135
8cb8e83b 3136 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3137 ARRAY_SIZE(controls));
3138 if (ret != 0)
8cb8e83b 3139 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3140 "Failed to add ReTune Mobile controls: %d\n", ret);
3141}
3142
3143static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3144{
8cb8e83b 3145 struct snd_soc_codec *codec = wm8994->hubs.codec;
9e6e96a1
MB		 3146 struct wm8994_pdata *pdata = wm8994->pdata;
3147 int ret, i;
3148
3149 if (!pdata)
3150 return;
3151
3152 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3153 pdata->lineout2_diff,
3154 pdata->lineout1fb,
3155 pdata->lineout2fb,
3156 pdata->jd_scthr,
3157 pdata->jd_thr,
02e79476
MB		 3158 pdata->micb1_delay,
3159 pdata->micb2_delay,
9e6e96a1
MB		 3160 pdata->micbias1_lvl,
3161 pdata->micbias2_lvl);
3162
3163 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3164
3165 if (pdata->num_drc_cfgs) {
3166 struct snd_kcontrol_new controls[] = {
3167 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3168 wm8994_get_drc_enum, wm8994_put_drc_enum),
3169 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3170 wm8994_get_drc_enum, wm8994_put_drc_enum),
3171 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3172 wm8994_get_drc_enum, wm8994_put_drc_enum),
3173 };
3174
3175 /* We need an array of texts for the enum API */
8cb8e83b 3176 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3177 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3178 if (!wm8994->drc_texts) {
8cb8e83b 3179 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3180 "Failed to allocate %d DRC config texts\n",
3181 pdata->num_drc_cfgs);
3182 return;
3183 }
3184
3185 for (i = 0; i < pdata->num_drc_cfgs; i++)
3186 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3187
3188 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3189 wm8994->drc_enum.texts = wm8994->drc_texts;
3190
8cb8e83b 3191 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3192 ARRAY_SIZE(controls));
9e6e96a1
MB		 3193 for (i = 0; i < WM8994_NUM_DRC; i++)
3194 wm8994_set_drc(codec, i);
45a690f6
MB		 3195 } else {
3196 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3197 wm8994_drc_controls,
3198 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3199 }
3200
45a690f6
MB		 3201 if (ret != 0)
3202 dev_err(wm8994->hubs.codec->dev,
3203 "Failed to add DRC mode controls: %d\n", ret);
3204
3205
9e6e96a1
MB		 3206 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3207 pdata->num_retune_mobile_cfgs);
3208
3209 if (pdata->num_retune_mobile_cfgs)
3210 wm8994_handle_retune_mobile_pdata(wm8994);
3211 else
8cb8e83b 3212 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3213 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3214
3215 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3216 if (pdata->micbias[i]) {
3217 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3218 pdata->micbias[i] & 0xffff);
3219 }
3220 }
9e6e96a1
MB		 3221}
3222
88766984
MB		 3223/**
3224 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3225 *
3226 * @codec: WM8994 codec
3227 * @jack: jack to report detection events on
3228 * @micbias: microphone bias to detect on
88766984
MB		 3229 *
3230 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3231 * being used to bring out signals to the processor then only platform
5ab230a7 3232 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3233 * be configured using snd_soc_jack_add_gpios() instead.
3234 *
3235 * Configuration of detection levels is available via the micbias1_lvl
3236 * and micbias2_lvl platform data members.
3237 */
3238int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3239 int micbias)
88766984 3240{
b2c812e2 3241 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3242 struct wm8994_micdet *micdet;
2a8a856d 3243 struct wm8994 *control = wm8994->wm8994;
87092e3c 3244 int reg, ret;
88766984 3245
87092e3c
MB		 3246 if (control->type != WM8994) {
3247 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3248 return -EINVAL;
87092e3c 3249 }
3a423157 3250
88766984
MB		 3251 switch (micbias) {
3252 case 1:
3253 micdet = &wm8994->micdet[0];
87092e3c
MB		 3254 if (jack)
3255 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3256 "MICBIAS1");
3257 else
3258 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3259 "MICBIAS1");
88766984
MB		 3260 break;
3261 case 2:
3262 micdet = &wm8994->micdet[1];
87092e3c
MB		 3263 if (jack)
3264 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3265 "MICBIAS1");
3266 else
3267 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3268 "MICBIAS1");
88766984
MB		 3269 break;
3270 default:
87092e3c 3271 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3272 return -EINVAL;
87092e3c 3273 }
88766984 3274
87092e3c
MB		 3275 if (ret != 0)
3276 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3277 micbias, ret);
3278
3279 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3280 micbias, jack);
88766984
MB		 3281
3282 /* Store the configuration */
3283 micdet->jack = jack;
87092e3c 3284 micdet->detecting = true;
88766984
MB		 3285
3286 /* If either of the jacks is set up then enable detection */
3287 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3288 reg = WM8994_MICD_ENA;
87092e3c 3289 else
88766984
MB		 3290 reg = 0;
3291
3292 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3293
d9f34df7
CR		 3294 /* enable MICDET and MICSHRT deboune */
3295 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3296 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3297 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3298 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3299
87092e3c
MB		 3300 snd_soc_dapm_sync(&codec->dapm);
3301
88766984
MB		 3302 return 0;
3303}
3304EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3305
e9b54de4 3306static void wm8994_mic_work(struct work_struct *work)
88766984 3307{
e9b54de4
MB		 3308 struct wm8994_priv *priv = container_of(work,
3309 struct wm8994_priv,
3310 mic_work.work);
fdfc4f3e
MB		 3311 struct regmap *regmap = priv->wm8994->regmap;
3312 struct device *dev = priv->wm8994->dev;
3313 unsigned int reg;
3314 int ret;
88766984
MB		 3315 int report;
3316
b8176627
MB		 3317 pm_runtime_get_sync(dev);
3318
fdfc4f3e
MB		 3319 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3320 if (ret < 0) {
3321 dev_err(dev, "Failed to read microphone status: %d\n",
3322 ret);
b8176627 3323 pm_runtime_put(dev);
e9b54de4 3324 return;
88766984
MB		 3325 }
3326
fdfc4f3e 3327 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3328
3329 report = 0;
87092e3c
MB		 3330 if (reg & WM8994_MIC1_DET_STS) {
3331 if (priv->micdet[0].detecting)
3332 report = SND_JACK_HEADSET;
3333 }
3334 if (reg & WM8994_MIC1_SHRT_STS) {
3335 if (priv->micdet[0].detecting)
3336 report = SND_JACK_HEADPHONE;
3337 else
3338 report |= SND_JACK_BTN_0;
3339 }
3340 if (report)
3341 priv->micdet[0].detecting = false;
3342 else
3343 priv->micdet[0].detecting = true;
3344
88766984 3345 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3346 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3347
3348 report = 0;
87092e3c
MB		 3349 if (reg & WM8994_MIC2_DET_STS) {
3350 if (priv->micdet[1].detecting)
3351 report = SND_JACK_HEADSET;
3352 }
3353 if (reg & WM8994_MIC2_SHRT_STS) {
3354 if (priv->micdet[1].detecting)
3355 report = SND_JACK_HEADPHONE;
3356 else
3357 report |= SND_JACK_BTN_0;
3358 }
3359 if (report)
3360 priv->micdet[1].detecting = false;
3361 else
3362 priv->micdet[1].detecting = true;
3363
88766984 3364 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3365 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3366
3367 pm_runtime_put(dev);
e9b54de4
MB		 3368}
3369
3370static irqreturn_t wm8994_mic_irq(int irq, void *data)
3371{
3372 struct wm8994_priv *priv = data;
8cb8e83b 3373 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3374
3375#ifndef CONFIG_SND_SOC_WM8994_MODULE
3376 trace_snd_soc_jack_irq(dev_name(codec->dev));
3377#endif
3378
3379 pm_wakeup_event(codec->dev, 300);
3380
3381 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3382
3383 return IRQ_HANDLED;
3384}
3385
821edd2f
MB		 3386/* Default microphone detection handler for WM8958 - the user can
3387 * override this if they wish.
3388 */
3389static void wm8958_default_micdet(u16 status, void *data)
3390{
3391 struct snd_soc_codec *codec = data;
3392 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3393 int report;
821edd2f 3394
a1691343
MB		 3395 dev_dbg(codec->dev, "MICDET %x\n", status);
3396
af6b6fe4 3397 /* Either nothing present or just starting detection */
b00adf76 3398 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3399 if (!wm8994->jackdet) {
3400 /* If nothing present then clear our statuses */
3401 dev_dbg(codec->dev, "Detected open circuit\n");
3402 wm8994->jack_mic = false;
3403 wm8994->mic_detecting = true;
b00adf76 3404
af6b6fe4 3405 wm8958_micd_set_rate(codec);
b00adf76 3406
af6b6fe4
MB		 3407 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3408 wm8994->btn_mask |
7435d4ee 3409 SND_JACK_HEADSET);
af6b6fe4 3410 }
b00adf76
MB		 3411 return;
3412 }
821edd2f 3413
b00adf76
MB		 3414 /* If the measurement is showing a high impedence we've got a
3415 * microphone.
3416 */
157a75e6 3417 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3418 dev_dbg(codec->dev, "Detected microphone\n");
3419
157a75e6 3420 wm8994->mic_detecting = false;
b00adf76
MB		 3421 wm8994->jack_mic = true;
3422
3423 wm8958_micd_set_rate(codec);
3424
3425 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3426 SND_JACK_HEADSET);
3427 }
821edd2f 3428
b00adf76 3429
7c08b51f 3430 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3431 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3432 wm8994->mic_detecting = false;
b00adf76
MB		 3433
3434 wm8958_micd_set_rate(codec);
3435
af6b6fe4
MB		 3436 /* If we have jackdet that will detect removal */
3437 if (wm8994->jackdet) {
c986564b
MB		 3438 mutex_lock(&wm8994->accdet_lock);
3439
af6b6fe4
MB		 3440 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3441 WM8958_MICD_ENA, 0);
3442
c986564b
MB		 3443 wm1811_jackdet_set_mode(codec,
3444 WM1811_JACKDET_MODE_JACK);
3445
3446 mutex_unlock(&wm8994->accdet_lock);
3447
ecd1732f 3448 if (wm8994->pdata->jd_ext_cap)
07fb9d9e
MB		 3449 snd_soc_dapm_disable_pin(&codec->dapm,
3450 "MICBIAS2");
af6b6fe4 3451 }
ecd1732f
MB		 3452
3453 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3454 SND_JACK_HEADSET);
b00adf76
MB		 3455 }
3456
3457 /* Report short circuit as a button */
3458 if (wm8994->jack_mic) {
4585790d 3459 report = 0;
b00adf76 3460 if (status & 0x4)
4585790d
MB		 3461 report |= SND_JACK_BTN_0;
3462
3463 if (status & 0x8)
3464 report |= SND_JACK_BTN_1;
3465
3466 if (status & 0x10)
3467 report |= SND_JACK_BTN_2;
3468
3469 if (status & 0x20)
3470 report |= SND_JACK_BTN_3;
3471
3472 if (status & 0x40)
3473 report |= SND_JACK_BTN_4;
3474
3475 if (status & 0x80)
3476 report |= SND_JACK_BTN_5;
3477
3478 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3479 wm8994->btn_mask);
b00adf76 3480 }
821edd2f
MB		 3481}
3482
c0cc3f16
MB		 3483/* Deferred mic detection to allow for extra settling time */
3484static void wm1811_mic_work(struct work_struct *work)
3485{
3486 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3487 mic_work.work);
3488 struct snd_soc_codec *codec = wm8994->hubs.codec;
3489
3490 pm_runtime_get_sync(codec->dev);
3491
3492 /* If required for an external cap force MICBIAS on */
3493 if (wm8994->pdata->jd_ext_cap) {
3494 snd_soc_dapm_force_enable_pin(&codec->dapm,
3495 "MICBIAS2");
3496 snd_soc_dapm_sync(&codec->dapm);
3497 }
3498
3499 mutex_lock(&wm8994->accdet_lock);
3500
3501 dev_dbg(codec->dev, "Starting mic detection\n");
3502
3503 /*
3504 * Start off measument of microphone impedence to find out
3505 * what's actually there.
3506 */
3507 wm8994->mic_detecting = true;
3508 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3509
3510 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3511 WM8958_MICD_ENA, WM8958_MICD_ENA);
3512
3513 mutex_unlock(&wm8994->accdet_lock);
3514
3515 pm_runtime_put(codec->dev);
3516}
3517
af6b6fe4
MB		 3518static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3519{
3520 struct wm8994_priv *wm8994 = data;
8cb8e83b 3521 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3522 int reg, delay;
c986564b 3523 bool present;
af6b6fe4 3524
b8176627
MB		 3525 pm_runtime_get_sync(codec->dev);
3526
af6b6fe4
MB		 3527 mutex_lock(&wm8994->accdet_lock);
3528
3529 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3530 if (reg < 0) {
3531 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3532 mutex_unlock(&wm8994->accdet_lock);
b8176627 3533 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3534 return IRQ_NONE;
3535 }
3536
3537 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3538
c986564b 3539 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3540
c986564b
MB		 3541 if (present) {
3542 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3543
e9d9a968
MB		 3544 wm8958_micd_set_rate(codec);
3545
55a27786
MB		 3546 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3547 WM8958_MICB2_DISCH, 0);
3548
378ec0ca
MB		 3549 /* Disable debounce while inserted */
3550 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3551 WM1811_JACKDET_DB, 0);
3552
c0cc3f16
MB		 3553 delay = wm8994->pdata->micdet_delay;
3554 schedule_delayed_work(&wm8994->mic_work,
3555 msecs_to_jiffies(delay));
af6b6fe4
MB		 3556 } else {
3557 dev_dbg(codec->dev, "Jack not detected\n");
3558
c0cc3f16
MB		 3559 cancel_delayed_work_sync(&wm8994->mic_work);
3560
55a27786
MB		 3561 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3562 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3563
378ec0ca
MB		 3564 /* Enable debounce while removed */
3565 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3566 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3567
af6b6fe4
MB		 3568 wm8994->mic_detecting = false;
3569 wm8994->jack_mic = false;
3570 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3571 WM8958_MICD_ENA, 0);
3572 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3573 }
3574
3575 mutex_unlock(&wm8994->accdet_lock);
3576
c0cc3f16
MB		 3577 /* Turn off MICBIAS if it was on for an external cap */
3578 if (wm8994->pdata->jd_ext_cap && !present)
3579 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3580
3581 if (present)
3582 snd_soc_jack_report(wm8994->micdet[0].jack,
3583 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3584 else
3585 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3586 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3587 wm8994->btn_mask);
3588
99af79df
MB		 3589 /* Since we only report deltas force an update, ensures we
3590 * avoid bootstrapping issues with the core. */
3591 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3592
b8176627 3593 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3594 return IRQ_HANDLED;
3595}
3596
99af79df
MB		 3597static void wm1811_jackdet_bootstrap(struct work_struct *work)
3598{
3599 struct wm8994_priv *wm8994 = container_of(work,
3600 struct wm8994_priv,
3601 jackdet_bootstrap.work);
3602 wm1811_jackdet_irq(0, wm8994);
3603}
3604
821edd2f
MB		 3605/**
3606 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3607 *
3608 * @codec: WM8958 codec
3609 * @jack: jack to report detection events on
3610 *
3611 * Enable microphone detection functionality for the WM8958. By
3612 * default simple detection which supports the detection of up to 6
3613 * buttons plus video and microphone functionality is supported.
3614 *
3615 * The WM8958 has an advanced jack detection facility which is able to
3616 * support complex accessory detection, especially when used in
3617 * conjunction with external circuitry. In order to provide maximum
3618 * flexiblity a callback is provided which allows a completely custom
3619 * detection algorithm.
3620 */
3621int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3622 wm8958_micdet_cb cb, void *cb_data)
3623{
3624 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3625 struct wm8994 *control = wm8994->wm8994;
4585790d 3626 u16 micd_lvl_sel;
821edd2f 3627
81204c84
MB		 3628 switch (control->type) {
3629 case WM1811:
3630 case WM8958:
3631 break;
3632 default:
821edd2f 3633 return -EINVAL;
81204c84 3634 }
821edd2f
MB		 3635
3636 if (jack) {
3637 if (!cb) {
3638 dev_dbg(codec->dev, "Using default micdet callback\n");
3639 cb = wm8958_default_micdet;
3640 cb_data = codec;
3641 }
3642
4cdf5e49 3643 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3644 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3645
821edd2f
MB		 3646 wm8994->micdet[0].jack = jack;
3647 wm8994->jack_cb = cb;
3648 wm8994->jack_cb_data = cb_data;
3649
157a75e6 3650 wm8994->mic_detecting = true;
b00adf76
MB		 3651 wm8994->jack_mic = false;
3652
3653 wm8958_micd_set_rate(codec);
3654
4585790d
MB		 3655 /* Detect microphones and short circuits by default */
3656 if (wm8994->pdata->micd_lvl_sel)
3657 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3658 else
3659 micd_lvl_sel = 0x41;
3660
3661 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3662 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3663 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3664
b00adf76 3665 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3666 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3667
af6b6fe4
MB		 3668 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3669
3670 /*
3671 * If we can use jack detection start off with that,
3672 * otherwise jump straight to microphone detection.
3673 */
3674 if (wm8994->jackdet) {
99af79df
MB		 3675 /* Disable debounce for the initial detect */
3676 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3677 WM1811_JACKDET_DB, 0);
3678
55a27786
MB		 3679 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3680 WM8958_MICB2_DISCH,
3681 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3682 snd_soc_update_bits(codec, WM8994_LDO_1,
3683 WM8994_LDO1_DISCH, 0);
3684 wm1811_jackdet_set_mode(codec,
3685 WM1811_JACKDET_MODE_JACK);
3686 } else {
3687 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3688 WM8958_MICD_ENA, WM8958_MICD_ENA);
3689 }
3690
821edd2f
MB		 3691 } else {
3692 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3693 WM8958_MICD_ENA, 0);
afaf1591 3694 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3695 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3696 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3697 }
3698
3699 return 0;
3700}
3701EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3702
3703static irqreturn_t wm8958_mic_irq(int irq, void *data)
3704{
3705 struct wm8994_priv *wm8994 = data;
8cb8e83b 3706 struct snd_soc_codec *codec = wm8994->hubs.codec;
19940b3d 3707 int reg, count;
821edd2f 3708
af6b6fe4
MB		 3709 /*
3710 * Jack detection may have detected a removal simulataneously
3711 * with an update of the MICDET status; if so it will have
3712 * stopped detection and we can ignore this interrupt.
3713 */
c986564b 3714 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3715 return IRQ_HANDLED;
af6b6fe4 3716
b8176627
MB		 3717 pm_runtime_get_sync(codec->dev);
3718
19940b3d
MB		 3719 /* We may occasionally read a detection without an impedence
3720 * range being provided - if that happens loop again.
3721 */
3722 count = 10;
3723 do {
3724 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3725 if (reg < 0) {
3726 dev_err(codec->dev,
3727 "Failed to read mic detect status: %d\n",
3728 reg);
b8176627 3729 pm_runtime_put(codec->dev);
19940b3d
MB		 3730 return IRQ_NONE;
3731 }
821edd2f 3732
19940b3d
MB		 3733 if (!(reg & WM8958_MICD_VALID)) {
3734 dev_dbg(codec->dev, "Mic detect data not valid\n");
3735 goto out;
3736 }
3737
3738 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3739 break;
3740
3741 msleep(1);
3742 } while (count--);
3743
3744 if (count == 0)
3745 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3746
7116f452 3747#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3748 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3749#endif
2bbb5d66 3750
821edd2f
MB		 3751 if (wm8994->jack_cb)
3752 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3753 else
3754 dev_warn(codec->dev, "Accessory detection with no callback\n");
3755
3756out:
b8176627 3757 pm_runtime_put(codec->dev);
821edd2f
MB		 3758 return IRQ_HANDLED;
3759}
3760
3b1af3f8
MB		 3761static irqreturn_t wm8994_fifo_error(int irq, void *data)
3762{
3763 struct snd_soc_codec *codec = data;
3764
3765 dev_err(codec->dev, "FIFO error\n");
3766
3767 return IRQ_HANDLED;
3768}
3769
f0b182b0
MB		 3770static irqreturn_t wm8994_temp_warn(int irq, void *data)
3771{
3772 struct snd_soc_codec *codec = data;
3773
3774 dev_err(codec->dev, "Thermal warning\n");
3775
3776 return IRQ_HANDLED;
3777}
3778
3779static irqreturn_t wm8994_temp_shut(int irq, void *data)
3780{
3781 struct snd_soc_codec *codec = data;
3782
3783 dev_crit(codec->dev, "Thermal shutdown\n");
3784
3785 return IRQ_HANDLED;
3786}
3787
f0fba2ad 3788static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3789{
d9a7666f 3790 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3791 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3792 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3793 unsigned int reg;
ec62dbd7 3794 int ret, i;
9e6e96a1 3795
8cb8e83b 3796 wm8994->hubs.codec = codec;
d9a7666f 3797 codec->control_data = control->regmap;
9e6e96a1 3798
d9a7666f 3799 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3800
af6b6fe4 3801 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3802 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3803 wm1811_jackdet_bootstrap);
af6b6fe4 3804
c0cc3f16
MB		 3805 switch (control->type) {
3806 case WM8994:
3807 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
3808 break;
3809 case WM1811:
3810 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
3811 break;
3812 default:
3813 break;
3814 }
3815
c7ebf932
MB		 3816 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3817 init_completion(&wm8994->fll_locked[i]);
3818
9b7c525d
MB		 3819 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3820 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
9b7c525d 3821
39fb51a1 3822 pm_runtime_enable(codec->dev);
5fab5174 3823 pm_runtime_idle(codec->dev);
39fb51a1 3824
f959dee9
MB		 3825 /* By default use idle_bias_off, will override for WM8994 */
3826 codec->dapm.idle_bias_off = 1;
3827
9e6e96a1 3828 /* Set revision-specific configuration */
b6b05691 3829 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3830 switch (control->type) {
3831 case WM8994:
f959dee9
MB		 3832 /* Single ended line outputs should have VMID on. */
3833 if (!wm8994->pdata->lineout1_diff ||
3834 !wm8994->pdata->lineout2_diff)
3835 codec->dapm.idle_bias_off = 0;
3836
3a423157
MB		 3837 switch (wm8994->revision) {
3838 case 2:
3839 case 3:
4537c4e7
MB		 3840 wm8994->hubs.dcs_codes_l = -5;
3841 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3842 wm8994->hubs.hp_startup_mode = 1;
3843 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3844 wm8994->hubs.series_startup = 1;
3a423157
MB		 3845 break;
3846 default:
79ef0abc 3847 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3848 break;
3849 }
280ec8b7 3850 break;
3a423157
MB		 3851
3852 case WM8958:
8437f700 3853 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3854 wm8994->hubs.hp_startup_mode = 1;
20dc24a9
MB		 3855
3856 switch (wm8994->revision) {
3857 case 0:
3858 break;
3859 default:
3860 wm8994->fll_byp = true;
3861 break;
3862 }
9e6e96a1 3863 break;
3a423157 3864
81204c84
MB		 3865 case WM1811:
3866 wm8994->hubs.dcs_readback_mode = 2;
3867 wm8994->hubs.no_series_update = 1;
29fdc360 3868 wm8994->hubs.hp_startup_mode = 1;
af31a227 3869 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 3870 wm8994->fll_byp = true;
81204c84 3871
52ca1138 3872 switch (control->cust_id) {
81204c84 3873 case 0:
fc8e6e86 3874 case 2:
6473a148 3875 wm8994->hubs.dcs_codes_l = -9;
e1660585 3876 wm8994->hubs.dcs_codes_r = -7;
81204c84 3877 break;
52ca1138
MB		 3878 case 1:
3879 case 3:
3880 wm8994->hubs.dcs_codes_l = -8;
3881 wm8994->hubs.dcs_codes_r = -7;
3882 break;
81204c84
MB		 3883 default:
3884 break;
3885 }
3886
3887 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3888 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3889 break;
3890
9e6e96a1
MB		 3891 default:
3892 break;
3893 }
9e6e96a1 3894
2a8a856d 3895 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3896 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3897 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3898 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3899 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3900 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3901
2a8a856d 3902 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3903 wm_hubs_dcs_done, "DC servo done",
3904 &wm8994->hubs);
3905 if (ret == 0)
3906 wm8994->hubs.dcs_done_irq = true;
3907
3a423157
MB		 3908 switch (control->type) {
3909 case WM8994:
9b7c525d
MB		 3910 if (wm8994->micdet_irq) {
3911 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3912 wm8994_mic_irq,
3913 IRQF_TRIGGER_RISING,
3914 "Mic1 detect",
3915 wm8994);
3916 if (ret != 0)
3917 dev_warn(codec->dev,
3918 "Failed to request Mic1 detect IRQ: %d\n",
3919 ret);
3920 }
3a423157 3921
2a8a856d 3922 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3923 WM8994_IRQ_MIC1_SHRT,
3924 wm8994_mic_irq, "Mic 1 short",
3925 wm8994);
3926 if (ret != 0)
3927 dev_warn(codec->dev,
3928 "Failed to request Mic1 short IRQ: %d\n",
3929 ret);
3930
2a8a856d 3931 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3932 WM8994_IRQ_MIC2_DET,
3933 wm8994_mic_irq, "Mic 2 detect",
3934 wm8994);
3935 if (ret != 0)
3936 dev_warn(codec->dev,
3937 "Failed to request Mic2 detect IRQ: %d\n",
3938 ret);
3939
2a8a856d 3940 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3941 WM8994_IRQ_MIC2_SHRT,
3942 wm8994_mic_irq, "Mic 2 short",
3943 wm8994);
3944 if (ret != 0)
3945 dev_warn(codec->dev,
3946 "Failed to request Mic2 short IRQ: %d\n",
3947 ret);
3948 break;
821edd2f
MB		 3949
3950 case WM8958:
81204c84 3951 case WM1811:
9b7c525d
MB		 3952 if (wm8994->micdet_irq) {
3953 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3954 wm8958_mic_irq,
3955 IRQF_TRIGGER_RISING,
3956 "Mic detect",
3957 wm8994);
3958 if (ret != 0)
3959 dev_warn(codec->dev,
3960 "Failed to request Mic detect IRQ: %d\n",
3961 ret);
b4046d01
MB		 3962 } else {
3963 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3964 wm8958_mic_irq, "Mic detect",
3965 wm8994);
9b7c525d 3966 }
3a423157 3967 }
88766984 3968
af6b6fe4
MB		 3969 switch (control->type) {
3970 case WM1811:
52ca1138 3971 if (control->cust_id > 1 || wm8994->revision > 1) {
af6b6fe4
MB		 3972 ret = wm8994_request_irq(wm8994->wm8994,
3973 WM8994_IRQ_GPIO(6),
3974 wm1811_jackdet_irq, "JACKDET",
3975 wm8994);
3976 if (ret == 0)
3977 wm8994->jackdet = true;
3978 }
3979 break;
3980 default:
3981 break;
3982 }
3983
c7ebf932
MB		 3984 wm8994->fll_locked_irq = true;
3985 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3986 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3987 WM8994_IRQ_FLL1_LOCK + i,
3988 wm8994_fll_locked_irq, "FLL lock",
3989 &wm8994->fll_locked[i]);
3990 if (ret != 0)
3991 wm8994->fll_locked_irq = false;
3992 }
3993
27060b3c
MB		 3994 /* Make sure we can read from the GPIOs if they're inputs */
3995 pm_runtime_get_sync(codec->dev);
3996
9e6e96a1
MB		 3997 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3998 * configured on init - if a system wants to do this dynamically
3999 * at runtime we can deal with that then.
4000 */
d9a7666f 4001 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 4002 if (ret < 0) {
4003 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4004 goto err_irq;
9e6e96a1 4005 }
d9a7666f 4006 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4007 wm8994->lrclk_shared[0] = 1;
4008 wm8994_dai[0].symmetric_rates = 1;
4009 } else {
4010 wm8994->lrclk_shared[0] = 0;
4011 }
4012
d9a7666f 4013 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4014 if (ret < 0) {
4015 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4016 goto err_irq;
9e6e96a1 4017 }
d9a7666f 4018 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4019 wm8994->lrclk_shared[1] = 1;
4020 wm8994_dai[1].symmetric_rates = 1;
4021 } else {
4022 wm8994->lrclk_shared[1] = 0;
4023 }
4024
27060b3c
MB		 4025 pm_runtime_put(codec->dev);
4026
bfd37bb5
MB		 4027 /* Latch volume update bits */
4028 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4029 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4030 wm8994_vu_bits[i].mask,
4031 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4032
4033 /* Set the low bit of the 3D stereo depth so TLV matches */
4034 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4035 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4036 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4037 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4038 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4039 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4040 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4041 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4042 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4043
5b739670
MB		 4044 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4045 * use this; it only affects behaviour on idle TDM clock
4046 * cycles. */
4047 switch (control->type) {
4048 case WM8994:
4049 case WM8958:
4050 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4051 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4052 break;
4053 default:
4054 break;
4055 }
d1ce6b20 4056
500fa30e
MB		 4057 /* Put MICBIAS into bypass mode by default on newer devices */
4058 switch (control->type) {
4059 case WM8958:
4060 case WM1811:
4061 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4062 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4063 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4064 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4065 break;
4066 default:
4067 break;
4068 }
4069
c340304d
MB		 4070 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4071 wm_hubs_update_class_w(codec);
9e6e96a1 4072
f0fba2ad 4073 wm8994_handle_pdata(wm8994);
9e6e96a1 4074
f0fba2ad 4075 wm_hubs_add_analogue_controls(codec);
022658be 4076 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4077 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4078 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4079 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4080
4081 switch (control->type) {
4082 case WM8994:
4083 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4084 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 4085 if (wm8994->revision < 4) {
173efa09
DP		 4086 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4087 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4088 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4089 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4090 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4091 ARRAY_SIZE(wm8994_dac_revd_widgets));
4092 } else {
173efa09
DP		 4093 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4094 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4095 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4096 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4097 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4098 ARRAY_SIZE(wm8994_dac_widgets));
4099 }
c4431df0
MB		 4100 break;
4101 case WM8958:
022658be 4102 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4103 ARRAY_SIZE(wm8958_snd_controls));
4104 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4105 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 4106 if (wm8994->revision < 1) {
4107 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4108 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4109 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4110 ARRAY_SIZE(wm8994_adc_revd_widgets));
4111 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4112 ARRAY_SIZE(wm8994_dac_revd_widgets));
4113 } else {
4114 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4115 ARRAY_SIZE(wm8994_lateclk_widgets));
4116 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4117 ARRAY_SIZE(wm8994_adc_widgets));
4118 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4119 ARRAY_SIZE(wm8994_dac_widgets));
4120 }
c4431df0 4121 break;
81204c84
MB		 4122
4123 case WM1811:
022658be 4124 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4125 ARRAY_SIZE(wm8958_snd_controls));
4126 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4127 ARRAY_SIZE(wm8958_dapm_widgets));
4128 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4129 ARRAY_SIZE(wm8994_lateclk_widgets));
4130 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4131 ARRAY_SIZE(wm8994_adc_widgets));
4132 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4133 ARRAY_SIZE(wm8994_dac_widgets));
4134 break;
c4431df0 4135 }
c4431df0 4136
f0fba2ad 4137 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4138 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4139
c4431df0
MB		 4140 switch (control->type) {
4141 case WM8994:
4142 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4143 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4144
173efa09 4145 if (wm8994->revision < 4) {
6ed8f148
MB		 4146 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4147 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4148 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4149 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4150 } else {
4151 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4152 ARRAY_SIZE(wm8994_lateclk_intercon));
4153 }
c4431df0
MB		 4154 break;
4155 case WM8958:
780e2806 4156 if (wm8994->revision < 1) {
15676937
CR		 4157 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4158 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4159 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4160 ARRAY_SIZE(wm8994_revd_intercon));
4161 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4162 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4163 } else {
4164 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4165 ARRAY_SIZE(wm8994_lateclk_intercon));
4166 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4167 ARRAY_SIZE(wm8958_intercon));
4168 }
f701a2e5
MB		 4169
4170 wm8958_dsp2_init(codec);
c4431df0 4171 break;
81204c84
MB		 4172 case WM1811:
4173 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4174 ARRAY_SIZE(wm8994_lateclk_intercon));
4175 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4176 ARRAY_SIZE(wm8958_intercon));
4177 break;
c4431df0
MB		 4178 }
4179
9e6e96a1
MB		 4180 return 0;
4181
88766984 4182err_irq:
af6b6fe4
MB		 4183 if (wm8994->jackdet)
4184 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4185 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4186 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4187 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4188 if (wm8994->micdet_irq)
4189 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4190 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4191 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4192 &wm8994->fll_locked[i]);
2a8a856d 4193 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4194 &wm8994->hubs);
2a8a856d
MB		 4195 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4196 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4197 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4198
9e6e96a1
MB		 4199 return ret;
4200}
4201
34ff0f95 4202static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4203{
f0fba2ad 4204 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4205 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4206 int i;
9e6e96a1
MB		 4207
4208 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4209
39fb51a1
MB		 4210 pm_runtime_disable(codec->dev);
4211
c7ebf932 4212 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4213 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4214 &wm8994->fll_locked[i]);
4215
2a8a856d 4216 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4217 &wm8994->hubs);
2a8a856d
MB		 4218 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4219 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4220 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4221
af6b6fe4
MB		 4222 if (wm8994->jackdet)
4223 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4224
3a423157
MB		 4225 switch (control->type) {
4226 case WM8994:
9b7c525d
MB		 4227 if (wm8994->micdet_irq)
4228 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4229 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4230 wm8994);
2a8a856d 4231 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4232 wm8994);
2a8a856d 4233 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4234 wm8994);
4235 break;
821edd2f 4236
81204c84 4237 case WM1811:
821edd2f 4238 case WM8958:
9b7c525d
MB		 4239 if (wm8994->micdet_irq)
4240 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4241 break;
3a423157 4242 }
34ff0f95
JJ		 4243 release_firmware(wm8994->mbc);
4244 release_firmware(wm8994->mbc_vss);
4245 release_firmware(wm8994->enh_eq);
24fb2b11 4246 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4247 return 0;
4248}
4249
f0fba2ad
LG		 4250static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4251 .probe = wm8994_codec_probe,
4252 .remove = wm8994_codec_remove,
4752a887
MB		 4253 .suspend = wm8994_codec_suspend,
4254 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4255 .set_bias_level = wm8994_set_bias_level,
4256};
4257
4258static int __devinit wm8994_probe(struct platform_device *pdev)
4259{
2bc16ed8
MB		 4260 struct wm8994_priv *wm8994;
4261
4262 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4263 GFP_KERNEL);
4264 if (wm8994 == NULL)
4265 return -ENOMEM;
4266 platform_set_drvdata(pdev, wm8994);
4267
4268 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4269 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4270
f0fba2ad
LG		 4271 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4272 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4273}
4274
4275static int __devexit wm8994_remove(struct platform_device *pdev)
4276{
4277 snd_soc_unregister_codec(&pdev->dev);
4278 return 0;
4279}
4280
4752a887
MB		 4281#ifdef CONFIG_PM_SLEEP
4282static int wm8994_suspend(struct device *dev)
4283{
4284 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4285
4286 /* Drop down to power saving mode when system is suspended */
4287 if (wm8994->jackdet && !wm8994->active_refcount)
4288 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4289 WM1811_JACKDET_MODE_MASK,
4290 wm8994->jackdet_mode);
4291
4292 return 0;
4293}
4294
4295static int wm8994_resume(struct device *dev)
4296{
4297 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4298
4299 if (wm8994->jackdet && wm8994->jack_cb)
4300 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4301 WM1811_JACKDET_MODE_MASK,
4302 WM1811_JACKDET_MODE_AUDIO);
4303
4304 return 0;
4305}
4306#endif
4307
4308static const struct dev_pm_ops wm8994_pm_ops = {
4309 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4310};
4311
9e6e96a1
MB		 4312static struct platform_driver wm8994_codec_driver = {
4313 .driver = {
4752a887
MB		 4314 .name = "wm8994-codec",
4315 .owner = THIS_MODULE,
4316 .pm = &wm8994_pm_ops,
4317 },
f0fba2ad
LG		 4318 .probe = wm8994_probe,
4319 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 4320};
4321
5bbcc3c0 4322module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4323
4324MODULE_DESCRIPTION("ASoC WM8994 driver");
4325MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4326MODULE_LICENSE("GPL");
4327MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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