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Linux 3.11-rc1
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2009-12 Wolfson Microelectronics plc
9e6e96a1
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
d1a0a299 19#include <linux/gcd.h>
9e6e96a1
MB		 20#include <linux/i2c.h>
21#include <linux/platform_device.h>
39fb51a1 22#include <linux/pm_runtime.h>
9e6e96a1 23#include <linux/regulator/consumer.h>
5a0e3ad6 24#include <linux/slab.h>
9e6e96a1 25#include <sound/core.h>
821edd2f 26#include <sound/jack.h>
9e6e96a1
MB		 27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
9e6e96a1
MB		 30#include <sound/initval.h>
31#include <sound/tlv.h>
2bbb5d66 32#include <trace/events/asoc.h>
9e6e96a1
MB		 33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
af6b6fe4
MB		 42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
9e6e96a1
MB		 47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
bfd37bb5
MB		 50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
9e6e96a1
MB		 83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
af6b6fe4 95static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
604533de
MB		 98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 100};
101
af6b6fe4
MB		 102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
e9d9a968
MB		 105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
af6b6fe4
MB		 107};
108
b00adf76
MB		 109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada 112 struct wm8994 *control = wm8994->wm8994;
b00adf76
MB		 113 int best, i, sysclk, val;
114 bool idle;
af6b6fe4
MB		 115 const struct wm8958_micd_rate *rates;
116 int num_rates;
b00adf76 117
b00adf76
MB		 118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
d9dd4ada
MB		 126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
cd1707a9 129 } else if (wm8994->jackdet) {
af6b6fe4
MB		 130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
b00adf76 137 best = 0;
af6b6fe4
MB		 138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
b00adf76 140 continue;
af6b6fe4
MB		 141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
b00adf76 143 best = i;
af6b6fe4 144 else if (rates[best].idle != idle)
b00adf76
MB		 145 best = i;
146 }
147
af6b6fe4
MB		 148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76 150
3a334ada
MB		 151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
b00adf76
MB		 155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
9e6e96a1
MB		 160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
b2c812e2 162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
5e5e2bef 203
9e6e96a1
MB		 204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
b2c812e2 215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 216 int change, new;
9e6e96a1
MB		 217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
9e6e96a1 231 return 0;
b00adf76 232 }
9e6e96a1
MB		 233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
04f45c49
AL		 239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 243
b00adf76
MB		 244 wm8958_micd_set_rate(codec);
245
9e6e96a1
MB		 246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262}
263
264static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266};
267
268static const struct soc_enum sidetone_hpf =
269 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
270
146fd574
UK		 271static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273};
274
275static const struct soc_enum aif1adc1_hpf =
276 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
277
278static const struct soc_enum aif1adc2_hpf =
279 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
280
281static const struct soc_enum aif2adc_hpf =
282 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
283
9e6e96a1
MB		 284static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 289static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 290static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 291
292#define WM8994_DRC_SWITCH(xname, reg, shift) \
6e06509c
LPC		 293 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294 snd_soc_get_volsw, wm8994_put_drc_sw)
9e6e96a1
MB		 295
296static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298{
299 struct soc_mixer_control *mc =
300 (struct soc_mixer_control *)kcontrol->private_value;
301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
302 int mask, ret;
303
304 /* Can't enable both ADC and DAC paths simultaneously */
305 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307 WM8994_AIF1ADC1R_DRC_ENA_MASK;
308 else
309 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310
311 ret = snd_soc_read(codec, mc->reg);
312 if (ret < 0)
313 return ret;
314 if (ret & mask)
315 return -EINVAL;
316
317 return snd_soc_put_volsw(kcontrol, ucontrol);
318}
319
9e6e96a1
MB		 320static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321{
b2c812e2 322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 323 struct wm8994 *control = wm8994->wm8994;
324 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 325 int base = wm8994_drc_base[drc];
326 int cfg = wm8994->drc_cfg[drc];
327 int save, i;
328
329 /* Save any enables; the configuration should clear them. */
330 save = snd_soc_read(codec, base);
331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332 WM8994_AIF1ADC1R_DRC_ENA;
333
334 for (i = 0; i < WM8994_DRC_REGS; i++)
335 snd_soc_update_bits(codec, base + i, 0xffff,
336 pdata->drc_cfgs[cfg].regs[i]);
337
338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339 WM8994_AIF1ADC1L_DRC_ENA |
340 WM8994_AIF1ADC1R_DRC_ENA, save);
341}
342
343/* Icky as hell but saves code duplication */
344static int wm8994_get_drc(const char *name)
345{
346 if (strcmp(name, "AIF1DRC1 Mode") == 0)
347 return 0;
348 if (strcmp(name, "AIF1DRC2 Mode") == 0)
349 return 1;
350 if (strcmp(name, "AIF2DRC Mode") == 0)
351 return 2;
352 return -EINVAL;
353}
354
355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357{
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 360 struct wm8994 *control = wm8994->wm8994;
361 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 362 int drc = wm8994_get_drc(kcontrol->id.name);
363 int value = ucontrol->value.integer.value[0];
364
365 if (drc < 0)
366 return drc;
367
368 if (value >= pdata->num_drc_cfgs)
369 return -EINVAL;
370
371 wm8994->drc_cfg[drc] = value;
372
373 wm8994_set_drc(codec, drc);
374
375 return 0;
376}
377
378static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380{
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 383 int drc = wm8994_get_drc(kcontrol->id.name);
384
7d6898be
VK		 385 if (drc < 0)
386 return drc;
9e6e96a1
MB		 387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
c1a4ecd9 438 * current configuration.
9e6e96a1
MB		 439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448}
449
450/* Icky as hell but saves code duplication */
451static int wm8994_get_retune_mobile_block(const char *name)
452{
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460}
461
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d9dd4ada
MB		 467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
7d6898be
VK		 492 if (block < 0)
493 return block;
494
9e6e96a1
MB		 495 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496
497 return 0;
498}
499
96b101ef 500static const char *aif_chan_src_text[] = {
f554885f
MB		 501 "Left", "Right"
502};
503
96b101ef
MB		 504static const struct soc_enum aif1adcl_src =
505 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
506
507static const struct soc_enum aif1adcr_src =
508 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
509
510static const struct soc_enum aif2adcl_src =
511 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
512
513static const struct soc_enum aif2adcr_src =
514 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
515
f554885f 516static const struct soc_enum aif1dacl_src =
96b101ef 517 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 518
519static const struct soc_enum aif1dacr_src =
96b101ef 520 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 521
522static const struct soc_enum aif2dacl_src =
96b101ef 523 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 524
525static const struct soc_enum aif2dacr_src =
96b101ef 526 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 527
154b26aa
MB		 528static const char *osr_text[] = {
529 "Low Power", "High Performance",
530};
531
532static const struct soc_enum dac_osr =
533 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
534
535static const struct soc_enum adc_osr =
536 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
537
9e6e96a1
MB		 538static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540 WM8994_AIF1_ADC1_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543 WM8994_AIF1_ADC2_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546 WM8994_AIF2_ADC_RIGHT_VOLUME,
547 1, 119, 0, digital_tlv),
548
96b101ef
MB		 549SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 551SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 553
f554885f
MB		 554SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 556SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 558
9e6e96a1
MB		 559SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565
566SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568
569SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572
573WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576
577WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580
581WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584
585SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590 5, 12, 0, st_tlv),
591SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592 0, 12, 0, st_tlv),
593SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595
146fd574
UK		 596SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601
602SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604
154b26aa
MB		 605SOC_ENUM("ADC OSR", adc_osr),
606SOC_ENUM("DAC OSR", dac_osr),
607
9e6e96a1
MB		 608SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612
613SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617
618SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619 6, 1, 1, wm_hubs_spkmix_tlv),
620SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621 2, 1, 1, wm_hubs_spkmix_tlv),
622
623SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624 6, 1, 1, wm_hubs_spkmix_tlv),
625SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626 2, 1, 1, wm_hubs_spkmix_tlv),
627
628SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
458350b3 630SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 631 8, 1, 0),
632SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633 10, 15, 0, wm8994_3d_tlv),
634SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635 8, 1, 0),
458350b3 636SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 637 10, 15, 0, wm8994_3d_tlv),
458350b3 638SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 639 8, 1, 0),
640};
641
642static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648 eq_tlv),
649SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652 eq_tlv),
653
654SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659 eq_tlv),
660SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661 eq_tlv),
662SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663 eq_tlv),
664
665SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666 eq_tlv),
667SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668 eq_tlv),
669SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670 eq_tlv),
671SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672 eq_tlv),
673SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674 eq_tlv),
675};
676
45a690f6
MB		 677static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680 WM8994_AIF1ADC1R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683 WM8994_AIF1ADC2R_DRC_ENA),
684SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686 WM8994_AIF2ADCR_DRC_ENA),
687};
688
1ddc07d0
MB		 689static const char *wm8958_ng_text[] = {
690 "30ms", "125ms", "250ms", "500ms",
691};
692
693static const struct soc_enum wm8958_aif1dac1_ng_hold =
694 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
695 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
696
697static const struct soc_enum wm8958_aif1dac2_ng_hold =
698 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
699 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
700
701static const struct soc_enum wm8958_aif2dac_ng_hold =
702 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
703 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
704
c4431df0
MB		 705static const struct snd_kcontrol_new wm8958_snd_controls[] = {
706SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 707
708SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
709 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
710SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
711SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
712 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
713 7, 1, ng_tlv),
714
715SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
716 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
717SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
718SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
719 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
720 7, 1, ng_tlv),
721
722SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
723 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
724SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
725SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
726 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
727 7, 1, ng_tlv),
c4431df0
MB		 728};
729
81204c84
MB		 730static const struct snd_kcontrol_new wm1811_snd_controls[] = {
731SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
732 mixin_boost_tlv),
733SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
734 mixin_boost_tlv),
735};
736
af6b6fe4
MB		 737/* We run all mode setting through a function to enforce audio mode */
738static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
739{
740 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
741
78b76dbe 742 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
28e33269
MB		 743 return;
744
af6b6fe4
MB		 745 if (wm8994->active_refcount)
746 mode = WM1811_JACKDET_MODE_AUDIO;
747
4752a887 748 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 749 return;
750
4752a887 751 wm8994->jackdet_mode = mode;
1defde2a 752
4752a887
MB		 753 /* Always use audio mode to detect while the system is active */
754 if (mode != WM1811_JACKDET_MODE_NONE)
755 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 756
4752a887
MB		 757 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
758 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 759}
760
761static void active_reference(struct snd_soc_codec *codec)
762{
763 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
764
765 mutex_lock(&wm8994->accdet_lock);
766
767 wm8994->active_refcount++;
768
769 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
770 wm8994->active_refcount);
771
1defde2a
MB		 772 /* If we're using jack detection go into audio mode */
773 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 774
775 mutex_unlock(&wm8994->accdet_lock);
776}
777
778static void active_dereference(struct snd_soc_codec *codec)
779{
780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
781 u16 mode;
782
783 mutex_lock(&wm8994->accdet_lock);
784
785 wm8994->active_refcount--;
786
787 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
788 wm8994->active_refcount);
789
790 if (wm8994->active_refcount == 0) {
791 /* Go into appropriate detection only mode */
1defde2a
MB		 792 if (wm8994->jack_mic || wm8994->mic_detecting)
793 mode = WM1811_JACKDET_MODE_MIC;
794 else
795 mode = WM1811_JACKDET_MODE_JACK;
796
797 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 798 }
799
800 mutex_unlock(&wm8994->accdet_lock);
801}
802
9e6e96a1
MB		 803static int clk_sys_event(struct snd_soc_dapm_widget *w,
804 struct snd_kcontrol *kcontrol, int event)
805{
806 struct snd_soc_codec *codec = w->codec;
99af79df 807 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 808
809 switch (event) {
810 case SND_SOC_DAPM_PRE_PMU:
811 return configure_clock(codec);
812
99af79df
MB		 813 case SND_SOC_DAPM_POST_PMU:
814 /*
815 * JACKDET won't run until we start the clock and it
816 * only reports deltas, make sure we notify the state
817 * up the stack on startup. Use a *very* generous
818 * timeout for paranoia, there's no urgency and we
819 * don't want false reports.
820 */
821 if (wm8994->jackdet && !wm8994->clk_has_run) {
822 schedule_delayed_work(&wm8994->jackdet_bootstrap,
823 msecs_to_jiffies(1000));
824 wm8994->clk_has_run = true;
825 }
826 break;
827
9e6e96a1
MB		 828 case SND_SOC_DAPM_POST_PMD:
829 configure_clock(codec);
830 break;
831 }
832
833 return 0;
834}
835
4b7ed83a
MB		 836static void vmid_reference(struct snd_soc_codec *codec)
837{
838 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
839
db966f8a
MB		 840 pm_runtime_get_sync(codec->dev);
841
4b7ed83a
MB		 842 wm8994->vmid_refcount++;
843
844 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
845 wm8994->vmid_refcount);
846
847 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 848 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 849 WM8994_LINEOUT1_DISCH |
22f8d055 850 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 851
f7085641
MB		 852 wm_hubs_vmid_ena(codec);
853
22f8d055
MB		 854 switch (wm8994->vmid_mode) {
855 default:
cbd71f30 856 WARN_ON(NULL == "Invalid VMID mode");
22f8d055
MB		 857 case WM8994_VMID_NORMAL:
858 /* Startup bias, VMID ramp & buffer */
859 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
860 WM8994_BIAS_SRC |
861 WM8994_VMID_DISCH |
862 WM8994_STARTUP_BIAS_ENA |
863 WM8994_VMID_BUF_ENA |
864 WM8994_VMID_RAMP_MASK,
865 WM8994_BIAS_SRC |
866 WM8994_STARTUP_BIAS_ENA |
867 WM8994_VMID_BUF_ENA |
a3a1d9d2 868 (0x2 << WM8994_VMID_RAMP_SHIFT));
22f8d055
MB		 869
870 /* Main bias enable, VMID=2x40k */
871 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
872 WM8994_BIAS_ENA |
873 WM8994_VMID_SEL_MASK,
874 WM8994_BIAS_ENA | 0x2);
875
a3a1d9d2 876 msleep(300);
22f8d055
MB		 877
878 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
879 WM8994_VMID_RAMP_MASK |
880 WM8994_BIAS_SRC,
881 0);
882 break;
cc6d5a8c 883
22f8d055
MB		 884 case WM8994_VMID_FORCE:
885 /* Startup bias, slow VMID ramp & buffer */
886 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
887 WM8994_BIAS_SRC |
888 WM8994_VMID_DISCH |
889 WM8994_STARTUP_BIAS_ENA |
890 WM8994_VMID_BUF_ENA |
891 WM8994_VMID_RAMP_MASK,
892 WM8994_BIAS_SRC |
893 WM8994_STARTUP_BIAS_ENA |
894 WM8994_VMID_BUF_ENA |
895 (0x2 << WM8994_VMID_RAMP_SHIFT));
896
897 /* Main bias enable, VMID=2x40k */
898 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
899 WM8994_BIAS_ENA |
900 WM8994_VMID_SEL_MASK,
901 WM8994_BIAS_ENA | 0x2);
902
903 msleep(400);
904
905 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
906 WM8994_VMID_RAMP_MASK |
907 WM8994_BIAS_SRC,
908 0);
909 break;
910 }
4b7ed83a
MB		 911 }
912}
913
914static void vmid_dereference(struct snd_soc_codec *codec)
915{
916 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
917
918 wm8994->vmid_refcount--;
919
920 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
921 wm8994->vmid_refcount);
922
923 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 924 if (wm8994->hubs.lineout1_se)
925 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
926 WM8994_LINEOUT1N_ENA |
927 WM8994_LINEOUT1P_ENA,
928 WM8994_LINEOUT1N_ENA |
929 WM8994_LINEOUT1P_ENA);
930
931 if (wm8994->hubs.lineout2_se)
932 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
933 WM8994_LINEOUT2N_ENA |
934 WM8994_LINEOUT2P_ENA,
935 WM8994_LINEOUT2N_ENA |
936 WM8994_LINEOUT2P_ENA);
937
938 /* Start discharging VMID */
4b7ed83a
MB		 939 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
940 WM8994_BIAS_SRC |
22f8d055 941 WM8994_VMID_DISCH,
4b7ed83a 942 WM8994_BIAS_SRC |
22f8d055 943 WM8994_VMID_DISCH);
4b7ed83a 944
f95be9d6
MB		 945 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
946 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 947
f95be9d6 948 msleep(400);
e85b26ce 949
22f8d055 950 /* Active discharge */
4b7ed83a
MB		 951 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
952 WM8994_LINEOUT1_DISCH |
953 WM8994_LINEOUT2_DISCH,
954 WM8994_LINEOUT1_DISCH |
955 WM8994_LINEOUT2_DISCH);
956
22f8d055
MB		 957 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
958 WM8994_LINEOUT1N_ENA |
959 WM8994_LINEOUT1P_ENA |
960 WM8994_LINEOUT2N_ENA |
961 WM8994_LINEOUT2P_ENA, 0);
962
4b7ed83a
MB		 963 /* Switch off startup biases */
964 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
965 WM8994_BIAS_SRC |
966 WM8994_STARTUP_BIAS_ENA |
967 WM8994_VMID_BUF_ENA |
968 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 969
970 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
f95be9d6 971 WM8994_VMID_SEL_MASK, 0);
4b7ed83a 972 }
db966f8a
MB		 973
974 pm_runtime_put(codec->dev);
4b7ed83a
MB		 975}
976
977static int vmid_event(struct snd_soc_dapm_widget *w,
978 struct snd_kcontrol *kcontrol, int event)
979{
980 struct snd_soc_codec *codec = w->codec;
981
982 switch (event) {
983 case SND_SOC_DAPM_PRE_PMU:
984 vmid_reference(codec);
985 break;
986
987 case SND_SOC_DAPM_POST_PMD:
988 vmid_dereference(codec);
989 break;
990 }
991
992 return 0;
993}
994
c340304d 995static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
9e6e96a1 996{
9e6e96a1
MB		 997 int source = 0; /* GCC flow analysis can't track enable */
998 int reg, reg_r;
999
c340304d 1000 /* We also need the same AIF source for L/R and only one path */
9e6e96a1
MB		 1001 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1002 switch (reg) {
1003 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 1004 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 1005 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1006 break;
1007 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 1008 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 1009 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010 break;
1011 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 1012 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 1013 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014 break;
1015 default:
ee839a21 1016 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
c340304d 1017 return false;
9e6e96a1
MB		 1018 }
1019
1020 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1021 if (reg_r != reg) {
ee839a21 1022 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
c340304d 1023 return false;
9e6e96a1
MB		 1024 }
1025
c340304d
MB		 1026 /* Set the source up */
1027 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1028 WM8994_CP_DYN_SRC_SEL_MASK, source);
c1a4ecd9 1029
c340304d 1030 return true;
9e6e96a1
MB		 1031}
1032
1a38336b
MB		 1033static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1034 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1035{
1036 struct snd_soc_codec *codec = w->codec;
79748cdb 1037 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
d3134e21 1038 struct wm8994 *control = wm8994->wm8994;
1a38336b 1039 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
bfd37bb5 1040 int i;
1a38336b
MB		 1041 int dac;
1042 int adc;
1043 int val;
1044
1045 switch (control->type) {
1046 case WM8994:
1047 case WM8958:
1048 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1049 break;
1050 default:
1051 break;
1052 }
173efa09
DP		 1053
1054 switch (event) {
1055 case SND_SOC_DAPM_PRE_PMU:
79748cdb
MB		 1056 /* Don't enable timeslot 2 if not in use */
1057 if (wm8994->channels[0] <= 2)
1058 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1059
1a38336b
MB		 1060 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1061 if ((val & WM8994_AIF1ADCL_SRC) &&
1062 (val & WM8994_AIF1ADCR_SRC))
1063 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1064 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1065 !(val & WM8994_AIF1ADCR_SRC))
1066 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1067 else
1068 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1069 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1070
1071 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1072 if ((val & WM8994_AIF1DACL_SRC) &&
1073 (val & WM8994_AIF1DACR_SRC))
1074 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1075 else if (!(val & WM8994_AIF1DACL_SRC) &&
1076 !(val & WM8994_AIF1DACR_SRC))
1077 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1078 else
1079 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1080 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1081
1082 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1083 mask, adc);
1084 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1085 mask, dac);
1086 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1087 WM8994_AIF1DSPCLK_ENA |
1088 WM8994_SYSDSPCLK_ENA,
1089 WM8994_AIF1DSPCLK_ENA |
1090 WM8994_SYSDSPCLK_ENA);
1091 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1092 WM8994_AIF1ADC1R_ENA |
1093 WM8994_AIF1ADC1L_ENA |
1094 WM8994_AIF1ADC2R_ENA |
1095 WM8994_AIF1ADC2L_ENA);
1096 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1097 WM8994_AIF1DAC1R_ENA |
1098 WM8994_AIF1DAC1L_ENA |
1099 WM8994_AIF1DAC2R_ENA |
1100 WM8994_AIF1DAC2L_ENA);
173efa09 1101 break;
173efa09 1102
bfd37bb5
MB		 1103 case SND_SOC_DAPM_POST_PMU:
1104 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1105 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1106 snd_soc_read(codec,
1107 wm8994_vu_bits[i].reg));
1108 break;
1109
1a38336b
MB		 1110 case SND_SOC_DAPM_PRE_PMD:
1111 case SND_SOC_DAPM_POST_PMD:
1112 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1113 mask, 0);
1114 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1115 mask, 0);
1116
1117 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1118 if (val & WM8994_AIF2DSPCLK_ENA)
1119 val = WM8994_SYSDSPCLK_ENA;
1120 else
1121 val = 0;
1122 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1123 WM8994_SYSDSPCLK_ENA |
1124 WM8994_AIF1DSPCLK_ENA, val);
1125 break;
1126 }
c6b7b570 1127
173efa09
DP		 1128 return 0;
1129}
1130
1a38336b
MB		 1131static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1132 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1133{
1134 struct snd_soc_codec *codec = w->codec;
bfd37bb5 1135 int i;
1a38336b
MB		 1136 int dac;
1137 int adc;
1138 int val;
173efa09
DP		 1139
1140 switch (event) {
1a38336b
MB		 1141 case SND_SOC_DAPM_PRE_PMU:
1142 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1143 if ((val & WM8994_AIF2ADCL_SRC) &&
1144 (val & WM8994_AIF2ADCR_SRC))
1145 adc = WM8994_AIF2ADCR_ENA;
1146 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1147 !(val & WM8994_AIF2ADCR_SRC))
1148 adc = WM8994_AIF2ADCL_ENA;
1149 else
1150 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1151
1152
1153 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1154 if ((val & WM8994_AIF2DACL_SRC) &&
1155 (val & WM8994_AIF2DACR_SRC))
1156 dac = WM8994_AIF2DACR_ENA;
1157 else if (!(val & WM8994_AIF2DACL_SRC) &&
1158 !(val & WM8994_AIF2DACR_SRC))
1159 dac = WM8994_AIF2DACL_ENA;
1160 else
1161 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1162
1163 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1164 WM8994_AIF2ADCL_ENA |
1165 WM8994_AIF2ADCR_ENA, adc);
1166 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1167 WM8994_AIF2DACL_ENA |
1168 WM8994_AIF2DACR_ENA, dac);
1169 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1170 WM8994_AIF2DSPCLK_ENA |
1171 WM8994_SYSDSPCLK_ENA,
1172 WM8994_AIF2DSPCLK_ENA |
1173 WM8994_SYSDSPCLK_ENA);
1174 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1175 WM8994_AIF2ADCL_ENA |
1176 WM8994_AIF2ADCR_ENA,
1177 WM8994_AIF2ADCL_ENA |
1178 WM8994_AIF2ADCR_ENA);
1179 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1180 WM8994_AIF2DACL_ENA |
1181 WM8994_AIF2DACR_ENA,
1182 WM8994_AIF2DACL_ENA |
1183 WM8994_AIF2DACR_ENA);
1184 break;
1185
bfd37bb5
MB		 1186 case SND_SOC_DAPM_POST_PMU:
1187 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1188 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1189 snd_soc_read(codec,
1190 wm8994_vu_bits[i].reg));
1191 break;
1192
1a38336b 1193 case SND_SOC_DAPM_PRE_PMD:
173efa09 1194 case SND_SOC_DAPM_POST_PMD:
1a38336b
MB		 1195 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1196 WM8994_AIF2DACL_ENA |
1197 WM8994_AIF2DACR_ENA, 0);
c7f5f238 1198 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1a38336b
MB		 1199 WM8994_AIF2ADCL_ENA |
1200 WM8994_AIF2ADCR_ENA, 0);
1201
1202 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1203 if (val & WM8994_AIF1DSPCLK_ENA)
1204 val = WM8994_SYSDSPCLK_ENA;
1205 else
1206 val = 0;
1207 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1208 WM8994_SYSDSPCLK_ENA |
1209 WM8994_AIF2DSPCLK_ENA, val);
173efa09
DP		 1210 break;
1211 }
1212
1213 return 0;
1214}
1215
1a38336b
MB		 1216static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1217 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1218{
1219 struct snd_soc_codec *codec = w->codec;
1220 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1221
1222 switch (event) {
1223 case SND_SOC_DAPM_PRE_PMU:
1224 wm8994->aif1clk_enable = 1;
1225 break;
a3cff81a
DP		 1226 case SND_SOC_DAPM_POST_PMD:
1227 wm8994->aif1clk_disable = 1;
1228 break;
173efa09
DP		 1229 }
1230
1231 return 0;
1232}
1233
1a38336b
MB		 1234static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1235 struct snd_kcontrol *kcontrol, int event)
173efa09
DP		 1236{
1237 struct snd_soc_codec *codec = w->codec;
1238 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1239
1240 switch (event) {
1241 case SND_SOC_DAPM_PRE_PMU:
1242 wm8994->aif2clk_enable = 1;
1243 break;
a3cff81a
DP		 1244 case SND_SOC_DAPM_POST_PMD:
1245 wm8994->aif2clk_disable = 1;
1246 break;
173efa09
DP		 1247 }
1248
1249 return 0;
1250}
1251
1a38336b
MB		 1252static int late_enable_ev(struct snd_soc_dapm_widget *w,
1253 struct snd_kcontrol *kcontrol, int event)
1254{
1255 struct snd_soc_codec *codec = w->codec;
1256 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1257
1258 switch (event) {
1259 case SND_SOC_DAPM_PRE_PMU:
1260 if (wm8994->aif1clk_enable) {
c8fdc1b5 1261 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1262 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1263 WM8994_AIF1CLK_ENA_MASK,
1264 WM8994_AIF1CLK_ENA);
c8fdc1b5 1265 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1266 wm8994->aif1clk_enable = 0;
1267 }
1268 if (wm8994->aif2clk_enable) {
c8fdc1b5 1269 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1a38336b
MB		 1270 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1271 WM8994_AIF2CLK_ENA_MASK,
1272 WM8994_AIF2CLK_ENA);
c8fdc1b5 1273 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1a38336b
MB		 1274 wm8994->aif2clk_enable = 0;
1275 }
1276 break;
1277 }
1278
1279 /* We may also have postponed startup of DSP, handle that. */
1280 wm8958_aif_ev(w, kcontrol, event);
1281
1282 return 0;
1283}
1284
1285static int late_disable_ev(struct snd_soc_dapm_widget *w,
1286 struct snd_kcontrol *kcontrol, int event)
1287{
1288 struct snd_soc_codec *codec = w->codec;
1289 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1290
1291 switch (event) {
1292 case SND_SOC_DAPM_POST_PMD:
1293 if (wm8994->aif1clk_disable) {
c8fdc1b5 1294 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1295 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1296 WM8994_AIF1CLK_ENA_MASK, 0);
c8fdc1b5 1297 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1298 wm8994->aif1clk_disable = 0;
1299 }
1300 if (wm8994->aif2clk_disable) {
c8fdc1b5 1301 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1a38336b
MB		 1302 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1303 WM8994_AIF2CLK_ENA_MASK, 0);
c8fdc1b5 1304 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1a38336b
MB		 1305 wm8994->aif2clk_disable = 0;
1306 }
1307 break;
1308 }
1309
1310 return 0;
1311}
1312
04d28681
DP		 1313static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1314 struct snd_kcontrol *kcontrol, int event)
1315{
1316 late_enable_ev(w, kcontrol, event);
1317 return 0;
1318}
1319
b462c6e6
DP		 1320static int micbias_ev(struct snd_soc_dapm_widget *w,
1321 struct snd_kcontrol *kcontrol, int event)
1322{
1323 late_enable_ev(w, kcontrol, event);
1324 return 0;
1325}
1326
c52fd021
DP		 1327static int dac_ev(struct snd_soc_dapm_widget *w,
1328 struct snd_kcontrol *kcontrol, int event)
1329{
1330 struct snd_soc_codec *codec = w->codec;
1331 unsigned int mask = 1 << w->shift;
1332
1333 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1334 mask, mask);
1335 return 0;
1336}
1337
9e6e96a1
MB		 1338static const char *adc_mux_text[] = {
1339 "ADC",
1340 "DMIC",
1341};
1342
1343static const struct soc_enum adc_enum =
1344 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1345
1346static const struct snd_kcontrol_new adcl_mux =
1347 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1348
1349static const struct snd_kcontrol_new adcr_mux =
1350 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1351
1352static const struct snd_kcontrol_new left_speaker_mixer[] = {
1353SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1354SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1355SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1356SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1357SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1358};
1359
1360static const struct snd_kcontrol_new right_speaker_mixer[] = {
1361SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1362SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1363SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1364SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1365SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1366};
1367
1368/* Debugging; dump chip status after DAPM transitions */
1369static int post_ev(struct snd_soc_dapm_widget *w,
1370 struct snd_kcontrol *kcontrol, int event)
1371{
1372 struct snd_soc_codec *codec = w->codec;
1373 dev_dbg(codec->dev, "SRC status: %x\n",
1374 snd_soc_read(codec,
1375 WM8994_RATE_STATUS));
1376 return 0;
1377}
1378
1379static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1380SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1381 1, 1, 0),
1382SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1383 0, 1, 0),
1384};
1385
1386static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1387SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1388 1, 1, 0),
1389SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1390 0, 1, 0),
1391};
1392
a3257ba8
MB		 1393static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1394SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1395 1, 1, 0),
1396SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1397 0, 1, 0),
1398};
1399
1400static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1401SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1402 1, 1, 0),
1403SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1404 0, 1, 0),
1405};
1406
9e6e96a1
MB		 1407static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1408SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1409 5, 1, 0),
1410SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1411 4, 1, 0),
1412SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1413 2, 1, 0),
1414SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1415 1, 1, 0),
1416SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1417 0, 1, 0),
1418};
1419
1420static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1421SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1422 5, 1, 0),
1423SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1424 4, 1, 0),
1425SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1426 2, 1, 0),
1427SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1428 1, 1, 0),
1429SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1430 0, 1, 0),
1431};
1432
1433#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
6e06509c
LPC		 1434 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1435 snd_soc_get_volsw, wm8994_put_class_w)
9e6e96a1
MB		 1436
1437static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1438 struct snd_ctl_elem_value *ucontrol)
1439{
9d03545d
JN		 1440 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1441 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1442 struct snd_soc_codec *codec = w->codec;
1443 int ret;
1444
1445 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1446
c340304d 1447 wm_hubs_update_class_w(codec);
9e6e96a1
MB		 1448
1449 return ret;
1450}
1451
1452static const struct snd_kcontrol_new dac1l_mix[] = {
1453WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1454 5, 1, 0),
1455WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1456 4, 1, 0),
1457WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1458 2, 1, 0),
1459WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1460 1, 1, 0),
1461WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1462 0, 1, 0),
1463};
1464
1465static const struct snd_kcontrol_new dac1r_mix[] = {
1466WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1467 5, 1, 0),
1468WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1469 4, 1, 0),
1470WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1471 2, 1, 0),
1472WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1473 1, 1, 0),
1474WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1475 0, 1, 0),
1476};
1477
1478static const char *sidetone_text[] = {
1479 "ADC/DMIC1", "DMIC2",
1480};
1481
1482static const struct soc_enum sidetone1_enum =
1483 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1484
1485static const struct snd_kcontrol_new sidetone1_mux =
1486 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1487
1488static const struct soc_enum sidetone2_enum =
1489 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1490
1491static const struct snd_kcontrol_new sidetone2_mux =
1492 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1493
1494static const char *aif1dac_text[] = {
1495 "AIF1DACDAT", "AIF3DACDAT",
1496};
1497
50941968
MB		 1498static const char *loopback_text[] = {
1499 "None", "ADCDAT",
1500};
1501
1502static const struct soc_enum aif1_loopback_enum =
1503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, WM8994_AIF1_LOOPBACK_SHIFT, 2,
1504 loopback_text);
1505
1506static const struct snd_kcontrol_new aif1_loopback =
1507 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1508
1509static const struct soc_enum aif2_loopback_enum =
1510 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, WM8994_AIF2_LOOPBACK_SHIFT, 2,
1511 loopback_text);
1512
1513static const struct snd_kcontrol_new aif2_loopback =
1514 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1515
9e6e96a1
MB		 1516static const struct soc_enum aif1dac_enum =
1517 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1518
1519static const struct snd_kcontrol_new aif1dac_mux =
1520 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1521
1522static const char *aif2dac_text[] = {
1523 "AIF2DACDAT", "AIF3DACDAT",
1524};
1525
1526static const struct soc_enum aif2dac_enum =
1527 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1528
1529static const struct snd_kcontrol_new aif2dac_mux =
1530 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1531
1532static const char *aif2adc_text[] = {
1533 "AIF2ADCDAT", "AIF3DACDAT",
1534};
1535
1536static const struct soc_enum aif2adc_enum =
1537 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1538
1539static const struct snd_kcontrol_new aif2adc_mux =
1540 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1541
1542static const char *aif3adc_text[] = {
c4431df0 1543 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1544};
1545
c4431df0 1546static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1547 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1548
c4431df0
MB		 1549static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1550 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1551
1552static const struct soc_enum wm8958_aif3adc_enum =
1553 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1554
1555static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1556 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1557
1558static const char *mono_pcm_out_text[] = {
c1a4ecd9 1559 "None", "AIF2ADCL", "AIF2ADCR",
c4431df0
MB		 1560};
1561
1562static const struct soc_enum mono_pcm_out_enum =
1563 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1564
1565static const struct snd_kcontrol_new mono_pcm_out_mux =
1566 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1567
1568static const char *aif2dac_src_text[] = {
1569 "AIF2", "AIF3",
1570};
1571
1572/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1573static const struct soc_enum aif2dacl_src_enum =
1574 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1575
1576static const struct snd_kcontrol_new aif2dacl_src_mux =
1577 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1578
1579static const struct soc_enum aif2dacr_src_enum =
1580 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1581
1582static const struct snd_kcontrol_new aif2dacr_src_mux =
1583 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1584
173efa09 1585static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1a38336b 1586SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
173efa09 1587 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1a38336b 1588SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
173efa09
DP		 1589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1590
1591SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1592 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1593SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1594 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1595SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1596 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1597SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1598 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1599SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1600 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1601
1602SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1603 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1604 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1605SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1606 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1607 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1608SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
b70a51ba 1609 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
c340304d 1610SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
b70a51ba 1611 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1612
1613SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1614};
1615
1616static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1a38336b 1617SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
bfd37bb5
MB		 1618 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1619 SND_SOC_DAPM_PRE_PMD),
1a38336b 1620SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
bfd37bb5
MB		 1621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1622 SND_SOC_DAPM_PRE_PMD),
b70a51ba
MB		 1623SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1624SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1625 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1626SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1627 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
c340304d
MB		 1628SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1629SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
173efa09
DP		 1630};
1631
c52fd021
DP		 1632static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1633SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1634 dac_ev, SND_SOC_DAPM_PRE_PMU),
1635SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1636 dac_ev, SND_SOC_DAPM_PRE_PMU),
1637SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1638 dac_ev, SND_SOC_DAPM_PRE_PMU),
1639SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1640 dac_ev, SND_SOC_DAPM_PRE_PMU),
1641};
1642
1643static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1644SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1645SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1646SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1647SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1648};
1649
04d28681 1650static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1651SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1652 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1653SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1654 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1655};
1656
1657static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1658SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1659SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1660};
1661
9e6e96a1
MB		 1662static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1663SND_SOC_DAPM_INPUT("DMIC1DAT"),
1664SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1665SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1666
b462c6e6
DP		 1667SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1668 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1669SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1670 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1671
9e6e96a1 1672SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
99af79df
MB		 1673 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1674 SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1675
1a38336b
MB		 1676SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1677SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1678SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
9e6e96a1 1679
7f94de48 1680SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1a38336b 1681 0, SND_SOC_NOPM, 9, 0),
7f94de48 1682SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1a38336b 1683 0, SND_SOC_NOPM, 8, 0),
d6addcc9 1684SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1a38336b 1685 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
b2822a8c 1686 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1687SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1a38336b 1688 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
b2822a8c 1689 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1690
7f94de48 1691SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1a38336b 1692 0, SND_SOC_NOPM, 11, 0),
7f94de48 1693SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1a38336b 1694 0, SND_SOC_NOPM, 10, 0),
d6addcc9 1695SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1a38336b 1696 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
b2822a8c 1697 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9 1698SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1a38336b 1699 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
b2822a8c 1700 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1701
1702SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1703 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1704SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1705 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1706
a3257ba8
MB		 1707SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1708 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1709SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1710 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1711
9e6e96a1
MB		 1712SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1713 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1714SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1715 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1716
1717SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1718SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1719
1720SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1721 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1722SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1723 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1724
1725SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1a38336b 1726 SND_SOC_NOPM, 13, 0),
9e6e96a1 1727SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1a38336b 1728 SND_SOC_NOPM, 12, 0),
d6addcc9 1729SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1a38336b 1730 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
d6addcc9
MB		 1731 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1732SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1a38336b 1733 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
d6addcc9 1734 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1735
5567d8c6
MB		 1736SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1737SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1738SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1739SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1740
1741SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1742SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1743SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1744
5567d8c6
MB		 1745SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1746SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1747
1748SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1749
1750SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1751SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1752SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1753SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1754
1755/* Power is done with the muxes since the ADC power also controls the
1756 * downsampling chain, the chip will automatically manage the analogue
1757 * specific portions.
1758 */
1759SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1760SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1761
50941968
MB		 1762SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1763SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1764
9e6e96a1
MB		 1765SND_SOC_DAPM_POST("Debug log", post_ev),
1766};
1767
c4431df0
MB		 1768static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1769SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1770};
9e6e96a1 1771
c4431df0 1772static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
8c5b842b 1773SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
c4431df0
MB		 1774SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1775SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1776SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1777SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1778};
1779
1780static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1781 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1782 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1783
1784 { "DSP1CLK", NULL, "CLK_SYS" },
1785 { "DSP2CLK", NULL, "CLK_SYS" },
1786 { "DSPINTCLK", NULL, "CLK_SYS" },
1787
1788 { "AIF1ADC1L", NULL, "AIF1CLK" },
1789 { "AIF1ADC1L", NULL, "DSP1CLK" },
1790 { "AIF1ADC1R", NULL, "AIF1CLK" },
1791 { "AIF1ADC1R", NULL, "DSP1CLK" },
1792 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1793
1794 { "AIF1DAC1L", NULL, "AIF1CLK" },
1795 { "AIF1DAC1L", NULL, "DSP1CLK" },
1796 { "AIF1DAC1R", NULL, "AIF1CLK" },
1797 { "AIF1DAC1R", NULL, "DSP1CLK" },
1798 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1799
1800 { "AIF1ADC2L", NULL, "AIF1CLK" },
1801 { "AIF1ADC2L", NULL, "DSP1CLK" },
1802 { "AIF1ADC2R", NULL, "AIF1CLK" },
1803 { "AIF1ADC2R", NULL, "DSP1CLK" },
1804 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1805
1806 { "AIF1DAC2L", NULL, "AIF1CLK" },
1807 { "AIF1DAC2L", NULL, "DSP1CLK" },
1808 { "AIF1DAC2R", NULL, "AIF1CLK" },
1809 { "AIF1DAC2R", NULL, "DSP1CLK" },
1810 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1811
1812 { "AIF2ADCL", NULL, "AIF2CLK" },
1813 { "AIF2ADCL", NULL, "DSP2CLK" },
1814 { "AIF2ADCR", NULL, "AIF2CLK" },
1815 { "AIF2ADCR", NULL, "DSP2CLK" },
1816 { "AIF2ADCR", NULL, "DSPINTCLK" },
1817
1818 { "AIF2DACL", NULL, "AIF2CLK" },
1819 { "AIF2DACL", NULL, "DSP2CLK" },
1820 { "AIF2DACR", NULL, "AIF2CLK" },
1821 { "AIF2DACR", NULL, "DSP2CLK" },
1822 { "AIF2DACR", NULL, "DSPINTCLK" },
1823
1824 { "DMIC1L", NULL, "DMIC1DAT" },
1825 { "DMIC1L", NULL, "CLK_SYS" },
1826 { "DMIC1R", NULL, "DMIC1DAT" },
1827 { "DMIC1R", NULL, "CLK_SYS" },
1828 { "DMIC2L", NULL, "DMIC2DAT" },
1829 { "DMIC2L", NULL, "CLK_SYS" },
1830 { "DMIC2R", NULL, "DMIC2DAT" },
1831 { "DMIC2R", NULL, "CLK_SYS" },
1832
1833 { "ADCL", NULL, "AIF1CLK" },
1834 { "ADCL", NULL, "DSP1CLK" },
1835 { "ADCL", NULL, "DSPINTCLK" },
1836
1837 { "ADCR", NULL, "AIF1CLK" },
1838 { "ADCR", NULL, "DSP1CLK" },
1839 { "ADCR", NULL, "DSPINTCLK" },
1840
1841 { "ADCL Mux", "ADC", "ADCL" },
1842 { "ADCL Mux", "DMIC", "DMIC1L" },
1843 { "ADCR Mux", "ADC", "ADCR" },
1844 { "ADCR Mux", "DMIC", "DMIC1R" },
1845
1846 { "DAC1L", NULL, "AIF1CLK" },
1847 { "DAC1L", NULL, "DSP1CLK" },
1848 { "DAC1L", NULL, "DSPINTCLK" },
1849
1850 { "DAC1R", NULL, "AIF1CLK" },
1851 { "DAC1R", NULL, "DSP1CLK" },
1852 { "DAC1R", NULL, "DSPINTCLK" },
1853
1854 { "DAC2L", NULL, "AIF2CLK" },
1855 { "DAC2L", NULL, "DSP2CLK" },
1856 { "DAC2L", NULL, "DSPINTCLK" },
1857
1858 { "DAC2R", NULL, "AIF2DACR" },
1859 { "DAC2R", NULL, "AIF2CLK" },
1860 { "DAC2R", NULL, "DSP2CLK" },
1861 { "DAC2R", NULL, "DSPINTCLK" },
1862
1863 { "TOCLK", NULL, "CLK_SYS" },
1864
5567d8c6
MB		 1865 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1866 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1867 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1868
1869 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1870 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1871 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1872
9e6e96a1
MB		 1873 /* AIF1 outputs */
1874 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1875 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1876 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1877
1878 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1879 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1880 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1881
a3257ba8
MB		 1882 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1883 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1884 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1885
1886 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1887 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1888 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1889
9e6e96a1
MB		 1890 /* Pin level routing for AIF3 */
1891 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1892 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1893 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1894 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1895
50941968 1896 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
9e6e96a1 1897 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
50941968 1898 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
9e6e96a1
MB		 1899 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1900 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1901 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1902 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1903
1904 /* DAC1 inputs */
9e6e96a1
MB		 1905 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1906 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1907 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1908 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1909 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1910
9e6e96a1
MB		 1911 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1912 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1913 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1914 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1915 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1916
1917 /* DAC2/AIF2 outputs */
1918 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1919 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1920 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1921 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1922 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1923 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1924
1925 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1926 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1927 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1928 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1929 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1930 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1931
7f94de48
MB		 1932 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1933 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1934 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1935 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1936
9e6e96a1
MB		 1937 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1938
1939 /* AIF3 output */
1940 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1941 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1942 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1943 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1944 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1945 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1946 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1947 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1948
50941968
MB		 1949 /* Loopback */
1950 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1951 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1952 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1953 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1954
9e6e96a1
MB		 1955 /* Sidetone */
1956 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1957 { "Left Sidetone", "DMIC2", "DMIC2L" },
1958 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1959 { "Right Sidetone", "DMIC2", "DMIC2R" },
1960
1961 /* Output stages */
1962 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1963 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1964
1965 { "SPKL", "DAC1 Switch", "DAC1L" },
1966 { "SPKL", "DAC2 Switch", "DAC2L" },
1967
1968 { "SPKR", "DAC1 Switch", "DAC1R" },
1969 { "SPKR", "DAC2 Switch", "DAC2R" },
1970
1971 { "Left Headphone Mux", "DAC", "DAC1L" },
1972 { "Right Headphone Mux", "DAC", "DAC1R" },
1973};
1974
173efa09
DP		 1975static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1976 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1977 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1978 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1979 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1980 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1981 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1982 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1983 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1984};
1985
1986static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1987 { "DAC1L", NULL, "DAC1L Mixer" },
1988 { "DAC1R", NULL, "DAC1R Mixer" },
1989 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1990 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1991};
1992
6ed8f148
MB		 1993static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1994 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1995 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1996 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1997 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1998 { "MICBIAS1", NULL, "CLK_SYS" },
1999 { "MICBIAS1", NULL, "MICBIAS Supply" },
2000 { "MICBIAS2", NULL, "CLK_SYS" },
2001 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 2002};
2003
c4431df0
MB		 2004static const struct snd_soc_dapm_route wm8994_intercon[] = {
2005 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2006 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 2007 { "MICBIAS1", NULL, "VMID" },
2008 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 2009};
2010
2011static const struct snd_soc_dapm_route wm8958_intercon[] = {
2012 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2013 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2014
2015 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2016 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2017 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2018 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2019
8c5b842b
MB		 2020 { "AIF3DACDAT", NULL, "AIF3" },
2021 { "AIF3ADCDAT", NULL, "AIF3" },
2022
c4431df0
MB		 2023 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2024 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2025
2026 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2027};
2028
9e6e96a1
MB		 2029/* The size in bits of the FLL divide multiplied by 10
2030 * to allow rounding later */
2031#define FIXED_FLL_SIZE ((1 << 16) * 10)
2032
2033struct fll_div {
2034 u16 outdiv;
2035 u16 n;
2036 u16 k;
d1a0a299 2037 u16 lambda;
9e6e96a1
MB		 2038 u16 clk_ref_div;
2039 u16 fll_fratio;
2040};
2041
d1a0a299 2042static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
9e6e96a1
MB		 2043 int freq_in, int freq_out)
2044{
2045 u64 Kpart;
d1a0a299 2046 unsigned int K, Ndiv, Nmod, gcd_fll;
9e6e96a1
MB		 2047
2048 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2049
2050 /* Scale the input frequency down to <= 13.5MHz */
2051 fll->clk_ref_div = 0;
2052 while (freq_in > 13500000) {
2053 fll->clk_ref_div++;
2054 freq_in /= 2;
2055
2056 if (fll->clk_ref_div > 3)
2057 return -EINVAL;
2058 }
2059 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2060
2061 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2062 fll->outdiv = 3;
2063 while (freq_out * (fll->outdiv + 1) < 90000000) {
2064 fll->outdiv++;
2065 if (fll->outdiv > 63)
2066 return -EINVAL;
2067 }
2068 freq_out *= fll->outdiv + 1;
2069 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2070
2071 if (freq_in > 1000000) {
2072 fll->fll_fratio = 0;
7d48a6ac
MB		 2073 } else if (freq_in > 256000) {
2074 fll->fll_fratio = 1;
2075 freq_in *= 2;
2076 } else if (freq_in > 128000) {
2077 fll->fll_fratio = 2;
2078 freq_in *= 4;
2079 } else if (freq_in > 64000) {
9e6e96a1
MB		 2080 fll->fll_fratio = 3;
2081 freq_in *= 8;
7d48a6ac
MB		 2082 } else {
2083 fll->fll_fratio = 4;
2084 freq_in *= 16;
9e6e96a1
MB		 2085 }
2086 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2087
2088 /* Now, calculate N.K */
2089 Ndiv = freq_out / freq_in;
2090
2091 fll->n = Ndiv;
2092 Nmod = freq_out % freq_in;
2093 pr_debug("Nmod=%d\n", Nmod);
2094
d1a0a299
MB		 2095 switch (control->type) {
2096 case WM8994:
2097 /* Calculate fractional part - scale up so we can round. */
2098 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
9e6e96a1 2099
d1a0a299 2100 do_div(Kpart, freq_in);
9e6e96a1 2101
d1a0a299 2102 K = Kpart & 0xFFFFFFFF;
9e6e96a1 2103
d1a0a299
MB		 2104 if ((K % 10) >= 5)
2105 K += 5;
9e6e96a1 2106
d1a0a299
MB		 2107 /* Move down to proper range now rounding is done */
2108 fll->k = K / 10;
f7dbd399 2109 fll->lambda = 0;
9e6e96a1 2110
d1a0a299 2111 pr_debug("N=%x K=%x\n", fll->n, fll->k);
571ab6c6 2112 break;
9e6e96a1 2113
d1a0a299
MB		 2114 default:
2115 gcd_fll = gcd(freq_out, freq_in);
9e6e96a1 2116
d1a0a299
MB		 2117 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2118 fll->lambda = freq_in / gcd_fll;
2119
2120 }
9e6e96a1
MB		 2121
2122 return 0;
2123}
2124
f0fba2ad 2125static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 2126 unsigned int freq_in, unsigned int freq_out)
2127{
b2c812e2 2128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2129 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2130 int reg_offset, ret;
2131 struct fll_div fll;
e413ba88 2132 u16 reg, clk1, aif_reg, aif_src;
c7ebf932 2133 unsigned long timeout;
4b7ed83a 2134 bool was_enabled;
9e6e96a1 2135
9e6e96a1
MB		 2136 switch (id) {
2137 case WM8994_FLL1:
2138 reg_offset = 0;
2139 id = 0;
e413ba88 2140 aif_src = 0x10;
9e6e96a1
MB		 2141 break;
2142 case WM8994_FLL2:
2143 reg_offset = 0x20;
2144 id = 1;
e413ba88 2145 aif_src = 0x18;
9e6e96a1
MB		 2146 break;
2147 default:
2148 return -EINVAL;
2149 }
2150
4b7ed83a
MB		 2151 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2152 was_enabled = reg & WM8994_FLL1_ENA;
2153
136ff2a2 2154 switch (src) {
7add84aa
MB		 2155 case 0:
2156 /* Allow no source specification when stopping */
2157 if (freq_out)
2158 return -EINVAL;
4514e899 2159 src = wm8994->fll[id].src;
7add84aa 2160 break;
136ff2a2
MB		 2161 case WM8994_FLL_SRC_MCLK1:
2162 case WM8994_FLL_SRC_MCLK2:
2163 case WM8994_FLL_SRC_LRCLK:
2164 case WM8994_FLL_SRC_BCLK:
2165 break;
fbfe6983
MB		 2166 case WM8994_FLL_SRC_INTERNAL:
2167 freq_in = 12000000;
2168 freq_out = 12000000;
2169 break;
136ff2a2
MB		 2170 default:
2171 return -EINVAL;
2172 }
2173
9e6e96a1
MB		 2174 /* Are we changing anything? */
2175 if (wm8994->fll[id].src == src &&
2176 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2177 return 0;
2178
2179 /* If we're stopping the FLL redo the old config - no
2180 * registers will actually be written but we avoid GCC flow
2181 * analysis bugs spewing warnings.
2182 */
2183 if (freq_out)
d1a0a299 2184 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
9e6e96a1 2185 else
d1a0a299 2186 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
9e6e96a1
MB		 2187 wm8994->fll[id].out);
2188 if (ret < 0)
2189 return ret;
2190
e413ba88
MB		 2191 /* Make sure that we're not providing SYSCLK right now */
2192 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2193 if (clk1 & WM8994_SYSCLK_SRC)
2194 aif_reg = WM8994_AIF2_CLOCKING_1;
2195 else
2196 aif_reg = WM8994_AIF1_CLOCKING_1;
2197 reg = snd_soc_read(codec, aif_reg);
2198
2199 if ((reg & WM8994_AIF1CLK_ENA) &&
2200 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2201 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2202 id + 1);
2203 return -EBUSY;
2204 }
9e6e96a1
MB		 2205
2206 /* We always need to disable the FLL while reconfiguring */
2207 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2208 WM8994_FLL1_ENA, 0);
2209
20dc24a9 2210 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
e05854dd 2211 freq_in == freq_out && freq_out) {
20dc24a9
MB		 2212 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2213 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2214 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2215 goto out;
2216 }
2217
9e6e96a1
MB		 2218 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2219 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2220 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2221 WM8994_FLL1_OUTDIV_MASK |
2222 WM8994_FLL1_FRATIO_MASK, reg);
2223
b16db745
MB		 2224 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2225 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 2226
2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2228 WM8994_FLL1_N_MASK,
7435d4ee 2229 fll.n << WM8994_FLL1_N_SHIFT);
9e6e96a1 2230
d1a0a299
MB		 2231 if (fll.lambda) {
2232 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2233 WM8958_FLL1_LAMBDA_MASK,
2234 fll.lambda);
2235 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2236 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2237 } else {
2238 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2239 WM8958_FLL1_EFS_ENA, 0);
2240 }
2241
9e6e96a1 2242 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
fbfe6983 2243 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
136ff2a2
MB		 2244 WM8994_FLL1_REFCLK_DIV_MASK |
2245 WM8994_FLL1_REFCLK_SRC_MASK,
fbfe6983
MB		 2246 ((src == WM8994_FLL_SRC_INTERNAL)
2247 << WM8994_FLL1_FRC_NCO_SHIFT) |
136ff2a2
MB		 2248 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2249 (src - 1));
9e6e96a1 2250
f0f5039c
MB		 2251 /* Clear any pending completion from a previous failure */
2252 try_wait_for_completion(&wm8994->fll_locked[id]);
2253
9e6e96a1
MB		 2254 /* Enable (with fractional mode if required) */
2255 if (freq_out) {
4b7ed83a
MB		 2256 /* Enable VMID if we need it */
2257 if (!was_enabled) {
af6b6fe4
MB		 2258 active_reference(codec);
2259
4b7ed83a
MB		 2260 switch (control->type) {
2261 case WM8994:
2262 vmid_reference(codec);
2263 break;
2264 case WM8958:
da445afe 2265 if (control->revision < 1)
4b7ed83a
MB		 2266 vmid_reference(codec);
2267 break;
2268 default:
2269 break;
2270 }
2271 }
2272
fbfe6983
MB		 2273 reg = WM8994_FLL1_ENA;
2274
9e6e96a1 2275 if (fll.k)
fbfe6983
MB		 2276 reg |= WM8994_FLL1_FRAC;
2277 if (src == WM8994_FLL_SRC_INTERNAL)
2278 reg |= WM8994_FLL1_OSC_ENA;
2279
9e6e96a1 2280 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
fbfe6983
MB		 2281 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2282 WM8994_FLL1_FRAC, reg);
8e9ddf81 2283
c7ebf932
MB		 2284 if (wm8994->fll_locked_irq) {
2285 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2286 msecs_to_jiffies(10));
2287 if (timeout == 0)
2288 dev_warn(codec->dev,
2289 "Timed out waiting for FLL lock\n");
2290 } else {
2291 msleep(5);
2292 }
4b7ed83a
MB		 2293 } else {
2294 if (was_enabled) {
2295 switch (control->type) {
2296 case WM8994:
2297 vmid_dereference(codec);
2298 break;
2299 case WM8958:
da445afe 2300 if (control->revision < 1)
4b7ed83a
MB		 2301 vmid_dereference(codec);
2302 break;
2303 default:
2304 break;
2305 }
af6b6fe4
MB		 2306
2307 active_dereference(codec);
4b7ed83a 2308 }
9e6e96a1
MB		 2309 }
2310
20dc24a9 2311out:
9e6e96a1
MB		 2312 wm8994->fll[id].in = freq_in;
2313 wm8994->fll[id].out = freq_out;
136ff2a2 2314 wm8994->fll[id].src = src;
9e6e96a1 2315
9e6e96a1
MB		 2316 configure_clock(codec);
2317
cd22000a
MB		 2318 /*
2319 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2320 * for detection.
2321 */
2322 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2323 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2324
2325 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2326 & WM8994_AIF1CLK_RATE_MASK;
2327 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2328 & WM8994_AIF1CLK_RATE_MASK;
2329
cd22000a
MB		 2330 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2331 WM8994_AIF1CLK_RATE_MASK, 0x1);
2332 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2333 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2334 } else if (wm8994->aifdiv[0]) {
2335 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2336 WM8994_AIF1CLK_RATE_MASK,
2337 wm8994->aifdiv[0]);
2338 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2339 WM8994_AIF2CLK_RATE_MASK,
2340 wm8994->aifdiv[1]);
2341
2342 wm8994->aifdiv[0] = 0;
2343 wm8994->aifdiv[1] = 0;
cd22000a
MB		 2344 }
2345
9e6e96a1
MB		 2346 return 0;
2347}
2348
c7ebf932
MB		 2349static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2350{
2351 struct completion *completion = data;
2352
2353 complete(completion);
2354
2355 return IRQ_HANDLED;
2356}
f0fba2ad 2357
66b47fdb
MB		 2358static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2359
f0fba2ad
LG		 2360static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2361 unsigned int freq_in, unsigned int freq_out)
2362{
2363 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2364}
2365
9e6e96a1
MB		 2366static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2367 int clk_id, unsigned int freq, int dir)
2368{
2369 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2370 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2371 int i;
9e6e96a1
MB		 2372
2373 switch (dai->id) {
2374 case 1:
2375 case 2:
2376 break;
2377
2378 default:
2379 /* AIF3 shares clocking with AIF1/2 */
2380 return -EINVAL;
2381 }
2382
2383 switch (clk_id) {
2384 case WM8994_SYSCLK_MCLK1:
2385 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2386 wm8994->mclk[0] = freq;
2387 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2388 dai->id, freq);
2389 break;
2390
2391 case WM8994_SYSCLK_MCLK2:
2392 /* TODO: Set GPIO AF */
2393 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2394 wm8994->mclk[1] = freq;
2395 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2396 dai->id, freq);
2397 break;
2398
2399 case WM8994_SYSCLK_FLL1:
2400 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2401 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2402 break;
2403
2404 case WM8994_SYSCLK_FLL2:
2405 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2406 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2407 break;
2408
66b47fdb
MB		 2409 case WM8994_SYSCLK_OPCLK:
2410 /* Special case - a division (times 10) is given and
c1a4ecd9 2411 * no effect on main clocking.
66b47fdb
MB		 2412 */
2413 if (freq) {
2414 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2415 if (opclk_divs[i] == freq)
2416 break;
2417 if (i == ARRAY_SIZE(opclk_divs))
2418 return -EINVAL;
2419 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2420 WM8994_OPCLK_DIV_MASK, i);
2421 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2422 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2423 } else {
2424 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2425 WM8994_OPCLK_ENA, 0);
2426 }
2427
9e6e96a1
MB		 2428 default:
2429 return -EINVAL;
2430 }
2431
2432 configure_clock(codec);
2433
6730049a
MB		 2434 /*
2435 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2436 * for detection.
2437 */
2438 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2439 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
d3725761
MB		 2440
2441 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2442 & WM8994_AIF1CLK_RATE_MASK;
2443 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2444 & WM8994_AIF1CLK_RATE_MASK;
2445
6730049a
MB		 2446 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2447 WM8994_AIF1CLK_RATE_MASK, 0x1);
2448 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2449 WM8994_AIF2CLK_RATE_MASK, 0x1);
d3725761
MB		 2450 } else if (wm8994->aifdiv[0]) {
2451 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2452 WM8994_AIF1CLK_RATE_MASK,
2453 wm8994->aifdiv[0]);
2454 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2455 WM8994_AIF2CLK_RATE_MASK,
2456 wm8994->aifdiv[1]);
2457
2458 wm8994->aifdiv[0] = 0;
2459 wm8994->aifdiv[1] = 0;
6730049a
MB		 2460 }
2461
9e6e96a1
MB		 2462 return 0;
2463}
2464
2465static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2466 enum snd_soc_bias_level level)
2467{
b6b05691 2468 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2469 struct wm8994 *control = wm8994->wm8994;
b6b05691 2470
5f2f3890
MB		 2471 wm_hubs_set_bias_level(codec, level);
2472
9e6e96a1
MB		 2473 switch (level) {
2474 case SND_SOC_BIAS_ON:
2475 break;
2476
2477 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2478 /* MICBIAS into regulating mode */
2479 switch (control->type) {
2480 case WM8958:
2481 case WM1811:
2482 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2483 WM8958_MICB1_MODE, 0);
2484 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2485 WM8958_MICB2_MODE, 0);
2486 break;
2487 default:
2488 break;
2489 }
af6b6fe4
MB		 2490
2491 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2492 active_reference(codec);
9e6e96a1
MB		 2493 break;
2494
2495 case SND_SOC_BIAS_STANDBY:
ce6120cc 2496 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2497 switch (control->type) {
8bc3c2c2 2498 case WM8958:
da445afe 2499 if (control->revision == 0) {
8bc3c2c2 2500 /* Optimise performance for rev A */
8bc3c2c2
MB		 2501 snd_soc_update_bits(codec,
2502 WM8958_CHARGE_PUMP_2,
2503 WM8958_CP_DISCH,
2504 WM8958_CP_DISCH);
2505 }
2506 break;
81204c84 2507
462835e4 2508 default:
81204c84 2509 break;
b6b05691 2510 }
9e6e96a1
MB		 2511
2512 /* Discharge LINEOUT1 & 2 */
2513 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2514 WM8994_LINEOUT1_DISCH |
2515 WM8994_LINEOUT2_DISCH,
2516 WM8994_LINEOUT1_DISCH |
2517 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2518 }
2519
af6b6fe4
MB		 2520 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2521 active_dereference(codec);
2522
500fa30e
MB		 2523 /* MICBIAS into bypass mode on newer devices */
2524 switch (control->type) {
2525 case WM8958:
2526 case WM1811:
2527 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2528 WM8958_MICB1_MODE,
2529 WM8958_MICB1_MODE);
2530 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2531 WM8958_MICB2_MODE,
2532 WM8958_MICB2_MODE);
2533 break;
2534 default:
2535 break;
2536 }
9e6e96a1
MB		 2537 break;
2538
2539 case SND_SOC_BIAS_OFF:
4105ab84 2540 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2541 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2542 break;
2543 }
5f2f3890 2544
ce6120cc 2545 codec->dapm.bias_level = level;
af6b6fe4 2546
22f8d055
MB		 2547 return 0;
2548}
2549
2550int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2551{
2552 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2553
2554 switch (mode) {
2555 case WM8994_VMID_NORMAL:
2556 if (wm8994->hubs.lineout1_se) {
2557 snd_soc_dapm_disable_pin(&codec->dapm,
2558 "LINEOUT1N Driver");
2559 snd_soc_dapm_disable_pin(&codec->dapm,
2560 "LINEOUT1P Driver");
2561 }
2562 if (wm8994->hubs.lineout2_se) {
2563 snd_soc_dapm_disable_pin(&codec->dapm,
2564 "LINEOUT2N Driver");
2565 snd_soc_dapm_disable_pin(&codec->dapm,
2566 "LINEOUT2P Driver");
2567 }
2568
2569 /* Do the sync with the old mode to allow it to clean up */
2570 snd_soc_dapm_sync(&codec->dapm);
2571 wm8994->vmid_mode = mode;
2572 break;
2573
2574 case WM8994_VMID_FORCE:
2575 if (wm8994->hubs.lineout1_se) {
2576 snd_soc_dapm_force_enable_pin(&codec->dapm,
2577 "LINEOUT1N Driver");
2578 snd_soc_dapm_force_enable_pin(&codec->dapm,
2579 "LINEOUT1P Driver");
2580 }
2581 if (wm8994->hubs.lineout2_se) {
2582 snd_soc_dapm_force_enable_pin(&codec->dapm,
2583 "LINEOUT2N Driver");
2584 snd_soc_dapm_force_enable_pin(&codec->dapm,
2585 "LINEOUT2P Driver");
2586 }
2587
2588 wm8994->vmid_mode = mode;
2589 snd_soc_dapm_sync(&codec->dapm);
2590 break;
2591
2592 default:
2593 return -EINVAL;
2594 }
2595
9e6e96a1
MB		 2596 return 0;
2597}
2598
2599static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2600{
2601 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2602 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2603 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2604 int ms_reg;
2605 int aif1_reg;
435705e8
MB		 2606 int dac_reg;
2607 int adc_reg;
9e6e96a1
MB		 2608 int ms = 0;
2609 int aif1 = 0;
435705e8 2610 int lrclk = 0;
9e6e96a1
MB		 2611
2612 switch (dai->id) {
2613 case 1:
2614 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2615 aif1_reg = WM8994_AIF1_CONTROL_1;
435705e8
MB		 2616 dac_reg = WM8994_AIF1DAC_LRCLK;
2617 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2618 break;
2619 case 2:
2620 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2621 aif1_reg = WM8994_AIF2_CONTROL_1;
435705e8
MB		 2622 dac_reg = WM8994_AIF1DAC_LRCLK;
2623 adc_reg = WM8994_AIF1ADC_LRCLK;
9e6e96a1
MB		 2624 break;
2625 default:
2626 return -EINVAL;
2627 }
2628
2629 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2630 case SND_SOC_DAIFMT_CBS_CFS:
2631 break;
2632 case SND_SOC_DAIFMT_CBM_CFM:
2633 ms = WM8994_AIF1_MSTR;
2634 break;
2635 default:
2636 return -EINVAL;
2637 }
2638
2639 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2640 case SND_SOC_DAIFMT_DSP_B:
2641 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2642 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2643 case SND_SOC_DAIFMT_DSP_A:
2644 aif1 |= 0x18;
2645 break;
2646 case SND_SOC_DAIFMT_I2S:
2647 aif1 |= 0x10;
2648 break;
2649 case SND_SOC_DAIFMT_RIGHT_J:
2650 break;
2651 case SND_SOC_DAIFMT_LEFT_J:
2652 aif1 |= 0x8;
2653 break;
2654 default:
2655 return -EINVAL;
2656 }
2657
2658 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2659 case SND_SOC_DAIFMT_DSP_A:
2660 case SND_SOC_DAIFMT_DSP_B:
2661 /* frame inversion not valid for DSP modes */
2662 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2663 case SND_SOC_DAIFMT_NB_NF:
2664 break;
2665 case SND_SOC_DAIFMT_IB_NF:
2666 aif1 |= WM8994_AIF1_BCLK_INV;
2667 break;
2668 default:
2669 return -EINVAL;
2670 }
2671 break;
2672
2673 case SND_SOC_DAIFMT_I2S:
2674 case SND_SOC_DAIFMT_RIGHT_J:
2675 case SND_SOC_DAIFMT_LEFT_J:
2676 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2677 case SND_SOC_DAIFMT_NB_NF:
2678 break;
2679 case SND_SOC_DAIFMT_IB_IF:
2680 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
435705e8 2681 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2682 break;
2683 case SND_SOC_DAIFMT_IB_NF:
2684 aif1 |= WM8994_AIF1_BCLK_INV;
2685 break;
2686 case SND_SOC_DAIFMT_NB_IF:
2687 aif1 |= WM8994_AIF1_LRCLK_INV;
435705e8 2688 lrclk |= WM8958_AIF1_LRCLK_INV;
9e6e96a1
MB		 2689 break;
2690 default:
2691 return -EINVAL;
2692 }
2693 break;
2694 default:
2695 return -EINVAL;
2696 }
2697
c4431df0
MB		 2698 /* The AIF2 format configuration needs to be mirrored to AIF3
2699 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2700 switch (control->type) {
2701 case WM1811:
2702 case WM8958:
2703 if (dai->id == 2)
2704 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2705 WM8994_AIF1_LRCLK_INV |
2706 WM8958_AIF3_FMT_MASK, aif1);
2707 break;
2708
2709 default:
2710 break;
2711 }
c4431df0 2712
9e6e96a1
MB		 2713 snd_soc_update_bits(codec, aif1_reg,
2714 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2715 WM8994_AIF1_FMT_MASK,
2716 aif1);
2717 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2718 ms);
435705e8
MB		 2719 snd_soc_update_bits(codec, dac_reg,
2720 WM8958_AIF1_LRCLK_INV, lrclk);
2721 snd_soc_update_bits(codec, adc_reg,
2722 WM8958_AIF1_LRCLK_INV, lrclk);
9e6e96a1
MB		 2723
2724 return 0;
2725}
2726
2727static struct {
2728 int val, rate;
2729} srs[] = {
2730 { 0, 8000 },
2731 { 1, 11025 },
2732 { 2, 12000 },
2733 { 3, 16000 },
2734 { 4, 22050 },
2735 { 5, 24000 },
2736 { 6, 32000 },
2737 { 7, 44100 },
2738 { 8, 48000 },
2739 { 9, 88200 },
2740 { 10, 96000 },
2741};
2742
2743static int fs_ratios[] = {
2744 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2745};
2746
2747static int bclk_divs[] = {
2748 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2749 640, 880, 960, 1280, 1760, 1920
2750};
2751
2752static int wm8994_hw_params(struct snd_pcm_substream *substream,
2753 struct snd_pcm_hw_params *params,
2754 struct snd_soc_dai *dai)
2755{
2756 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2757 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3cf956ee
MB		 2758 struct wm8994 *control = wm8994->wm8994;
2759 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1 2760 int aif1_reg;
b1e43d93 2761 int aif2_reg;
9e6e96a1
MB		 2762 int bclk_reg;
2763 int lrclk_reg;
2764 int rate_reg;
2765 int aif1 = 0;
b1e43d93 2766 int aif2 = 0;
9e6e96a1
MB		 2767 int bclk = 0;
2768 int lrclk = 0;
2769 int rate_val = 0;
2770 int id = dai->id - 1;
2771
2772 int i, cur_val, best_val, bclk_rate, best;
2773
2774 switch (dai->id) {
2775 case 1:
2776 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2777 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2778 bclk_reg = WM8994_AIF1_BCLK;
2779 rate_reg = WM8994_AIF1_RATE;
2780 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2781 wm8994->lrclk_shared[0]) {
9e6e96a1 2782 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2783 } else {
9e6e96a1 2784 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2785 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2786 }
9e6e96a1
MB		 2787 break;
2788 case 2:
2789 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2790 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2791 bclk_reg = WM8994_AIF2_BCLK;
2792 rate_reg = WM8994_AIF2_RATE;
2793 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2794 wm8994->lrclk_shared[1]) {
9e6e96a1 2795 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2796 } else {
9e6e96a1 2797 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2798 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2799 }
9e6e96a1
MB		 2800 break;
2801 default:
2802 return -EINVAL;
2803 }
2804
79748cdb 2805 bclk_rate = params_rate(params);
9e6e96a1
MB		 2806 switch (params_format(params)) {
2807 case SNDRV_PCM_FORMAT_S16_LE:
2808 bclk_rate *= 16;
2809 break;
2810 case SNDRV_PCM_FORMAT_S20_3LE:
2811 bclk_rate *= 20;
2812 aif1 |= 0x20;
2813 break;
2814 case SNDRV_PCM_FORMAT_S24_LE:
2815 bclk_rate *= 24;
2816 aif1 |= 0x40;
2817 break;
2818 case SNDRV_PCM_FORMAT_S32_LE:
2819 bclk_rate *= 32;
2820 aif1 |= 0x60;
2821 break;
2822 default:
2823 return -EINVAL;
2824 }
2825
79748cdb 2826 wm8994->channels[id] = params_channels(params);
3cf956ee
MB		 2827 if (pdata->max_channels_clocked[id] &&
2828 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2829 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2830 pdata->max_channels_clocked[id], wm8994->channels[id]);
2831 wm8994->channels[id] = pdata->max_channels_clocked[id];
2832 }
2833
2834 switch (wm8994->channels[id]) {
79748cdb
MB		 2835 case 1:
2836 case 2:
2837 bclk_rate *= 2;
2838 break;
2839 default:
2840 bclk_rate *= 4;
2841 break;
2842 }
2843
9e6e96a1
MB		 2844 /* Try to find an appropriate sample rate; look for an exact match. */
2845 for (i = 0; i < ARRAY_SIZE(srs); i++)
2846 if (srs[i].rate == params_rate(params))
2847 break;
2848 if (i == ARRAY_SIZE(srs))
2849 return -EINVAL;
2850 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2851
2852 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2853 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2854 dai->id, wm8994->aifclk[id], bclk_rate);
2855
3cf956ee 2856 if (wm8994->channels[id] == 1 &&
b1e43d93
MB		 2857 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2858 aif2 |= WM8994_AIF1_MONO;
2859
9e6e96a1
MB		 2860 if (wm8994->aifclk[id] == 0) {
2861 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2862 return -EINVAL;
2863 }
2864
2865 /* AIFCLK/fs ratio; look for a close match in either direction */
2866 best = 0;
2867 best_val = abs((fs_ratios[0] * params_rate(params))
2868 - wm8994->aifclk[id]);
2869 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2870 cur_val = abs((fs_ratios[i] * params_rate(params))
2871 - wm8994->aifclk[id]);
2872 if (cur_val >= best_val)
2873 continue;
2874 best = i;
2875 best_val = cur_val;
2876 }
2877 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2878 dai->id, fs_ratios[best]);
2879 rate_val |= best;
2880
2881 /* We may not get quite the right frequency if using
2882 * approximate clocks so look for the closest match that is
2883 * higher than the target (we need to ensure that there enough
2884 * BCLKs to clock out the samples).
2885 */
2886 best = 0;
2887 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2888 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2889 if (cur_val < 0) /* BCLK table is sorted */
2890 break;
2891 best = i;
2892 }
07cd8ada 2893 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2894 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2895 bclk_divs[best], bclk_rate);
2896 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2897
2898 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2899 if (!lrclk) {
2900 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2901 bclk_rate);
2902 return -EINVAL;
2903 }
9e6e96a1
MB		 2904 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2905 lrclk, bclk_rate / lrclk);
2906
2907 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2908 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2909 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2910 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2911 lrclk);
2912 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2913 WM8994_AIF1CLK_RATE_MASK, rate_val);
2914
2915 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2916 switch (dai->id) {
2917 case 1:
2918 wm8994->dac_rates[0] = params_rate(params);
2919 wm8994_set_retune_mobile(codec, 0);
2920 wm8994_set_retune_mobile(codec, 1);
2921 break;
2922 case 2:
2923 wm8994->dac_rates[1] = params_rate(params);
2924 wm8994_set_retune_mobile(codec, 2);
2925 break;
2926 }
2927 }
2928
2929 return 0;
2930}
2931
c4431df0
MB		 2932static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2933 struct snd_pcm_hw_params *params,
2934 struct snd_soc_dai *dai)
2935{
2936 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2937 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2938 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2939 int aif1_reg;
2940 int aif1 = 0;
2941
2942 switch (dai->id) {
2943 case 3:
2944 switch (control->type) {
81204c84 2945 case WM1811:
c4431df0
MB		 2946 case WM8958:
2947 aif1_reg = WM8958_AIF3_CONTROL_1;
2948 break;
2949 default:
2950 return 0;
2951 }
4495e46f 2952 break;
c4431df0
MB		 2953 default:
2954 return 0;
2955 }
2956
2957 switch (params_format(params)) {
2958 case SNDRV_PCM_FORMAT_S16_LE:
2959 break;
2960 case SNDRV_PCM_FORMAT_S20_3LE:
2961 aif1 |= 0x20;
2962 break;
2963 case SNDRV_PCM_FORMAT_S24_LE:
2964 aif1 |= 0x40;
2965 break;
2966 case SNDRV_PCM_FORMAT_S32_LE:
2967 aif1 |= 0x60;
2968 break;
2969 default:
2970 return -EINVAL;
2971 }
2972
2973 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2974}
2975
9e6e96a1
MB		 2976static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2977{
2978 struct snd_soc_codec *codec = codec_dai->codec;
2979 int mute_reg;
2980 int reg;
2981
2982 switch (codec_dai->id) {
2983 case 1:
2984 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2985 break;
2986 case 2:
2987 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2988 break;
2989 default:
2990 return -EINVAL;
2991 }
2992
2993 if (mute)
2994 reg = WM8994_AIF1DAC1_MUTE;
2995 else
2996 reg = 0;
2997
2998 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2999
3000 return 0;
3001}
3002
778a76e2
MB		 3003static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3004{
3005 struct snd_soc_codec *codec = codec_dai->codec;
3006 int reg, val, mask;
3007
3008 switch (codec_dai->id) {
3009 case 1:
3010 reg = WM8994_AIF1_MASTER_SLAVE;
3011 mask = WM8994_AIF1_TRI;
3012 break;
3013 case 2:
3014 reg = WM8994_AIF2_MASTER_SLAVE;
3015 mask = WM8994_AIF2_TRI;
3016 break;
778a76e2
MB		 3017 default:
3018 return -EINVAL;
3019 }
3020
3021 if (tristate)
3022 val = mask;
3023 else
3024 val = 0;
3025
78b3fb46 3026 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 3027}
3028
d09f3ecf
MB		 3029static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3030{
3031 struct snd_soc_codec *codec = dai->codec;
3032
3033 /* Disable the pulls on the AIF if we're using it to save power. */
3034 snd_soc_update_bits(codec, WM8994_GPIO_3,
3035 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3036 snd_soc_update_bits(codec, WM8994_GPIO_4,
3037 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3038 snd_soc_update_bits(codec, WM8994_GPIO_5,
3039 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3040
3041 return 0;
3042}
3043
9e6e96a1
MB		 3044#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3045
3046#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 3047 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 3048
85e7652d 3049static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 3050 .set_sysclk = wm8994_set_dai_sysclk,
3051 .set_fmt = wm8994_set_dai_fmt,
3052 .hw_params = wm8994_hw_params,
3053 .digital_mute = wm8994_aif_mute,
3054 .set_pll = wm8994_set_fll,
778a76e2 3055 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 3056};
3057
85e7652d 3058static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 3059 .set_sysclk = wm8994_set_dai_sysclk,
3060 .set_fmt = wm8994_set_dai_fmt,
3061 .hw_params = wm8994_hw_params,
3062 .digital_mute = wm8994_aif_mute,
3063 .set_pll = wm8994_set_fll,
778a76e2
MB		 3064 .set_tristate = wm8994_set_tristate,
3065};
3066
85e7652d 3067static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 3068 .hw_params = wm8994_aif3_hw_params,
9e6e96a1
MB		 3069};
3070
f0fba2ad 3071static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 3072 {
f0fba2ad 3073 .name = "wm8994-aif1",
8c7f78b3 3074 .id = 1,
9e6e96a1
MB		 3075 .playback = {
3076 .stream_name = "AIF1 Playback",
b1e43d93 3077 .channels_min = 1,
9e6e96a1
MB		 3078 .channels_max = 2,
3079 .rates = WM8994_RATES,
3080 .formats = WM8994_FORMATS,
99b0292d 3081 .sig_bits = 24,
9e6e96a1
MB		 3082 },
3083 .capture = {
3084 .stream_name = "AIF1 Capture",
b1e43d93 3085 .channels_min = 1,
9e6e96a1
MB		 3086 .channels_max = 2,
3087 .rates = WM8994_RATES,
3088 .formats = WM8994_FORMATS,
99b0292d 3089 .sig_bits = 24,
9e6e96a1
MB		 3090 },
3091 .ops = &wm8994_aif1_dai_ops,
3092 },
3093 {
f0fba2ad 3094 .name = "wm8994-aif2",
8c7f78b3 3095 .id = 2,
9e6e96a1
MB		 3096 .playback = {
3097 .stream_name = "AIF2 Playback",
b1e43d93 3098 .channels_min = 1,
9e6e96a1
MB		 3099 .channels_max = 2,
3100 .rates = WM8994_RATES,
3101 .formats = WM8994_FORMATS,
99b0292d 3102 .sig_bits = 24,
9e6e96a1
MB		 3103 },
3104 .capture = {
3105 .stream_name = "AIF2 Capture",
b1e43d93 3106 .channels_min = 1,
9e6e96a1
MB		 3107 .channels_max = 2,
3108 .rates = WM8994_RATES,
3109 .formats = WM8994_FORMATS,
99b0292d 3110 .sig_bits = 24,
9e6e96a1 3111 },
d09f3ecf 3112 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 3113 .ops = &wm8994_aif2_dai_ops,
3114 },
3115 {
f0fba2ad 3116 .name = "wm8994-aif3",
8c7f78b3 3117 .id = 3,
9e6e96a1
MB		 3118 .playback = {
3119 .stream_name = "AIF3 Playback",
b1e43d93 3120 .channels_min = 1,
9e6e96a1
MB		 3121 .channels_max = 2,
3122 .rates = WM8994_RATES,
3123 .formats = WM8994_FORMATS,
99b0292d 3124 .sig_bits = 24,
9e6e96a1 3125 },
a8462bde 3126 .capture = {
9e6e96a1 3127 .stream_name = "AIF3 Capture",
b1e43d93 3128 .channels_min = 1,
9e6e96a1
MB		 3129 .channels_max = 2,
3130 .rates = WM8994_RATES,
3131 .formats = WM8994_FORMATS,
99b0292d
MB		 3132 .sig_bits = 24,
3133 },
778a76e2 3134 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 3135 }
3136};
9e6e96a1
MB		 3137
3138#ifdef CONFIG_PM
4752a887 3139static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 3140{
b2c812e2 3141 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3142 int i, ret;
3143
3144 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3145 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 3146 sizeof(struct wm8994_fll_config));
f0fba2ad 3147 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 3148 if (ret < 0)
3149 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3150 i + 1, ret);
3151 }
3152
3153 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3154
3155 return 0;
3156}
3157
4752a887 3158static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 3159{
b2c812e2 3160 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 3161 int i, ret;
3162
9e6e96a1 3163 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 3164 if (!wm8994->fll_suspend[i].out)
3165 continue;
3166
f0fba2ad 3167 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 3168 wm8994->fll_suspend[i].src,
3169 wm8994->fll_suspend[i].in,
3170 wm8994->fll_suspend[i].out);
3171 if (ret < 0)
3172 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3173 i + 1, ret);
3174 }
3175
3176 return 0;
3177}
3178#else
4752a887
MB		 3179#define wm8994_codec_suspend NULL
3180#define wm8994_codec_resume NULL
9e6e96a1
MB		 3181#endif
3182
3183static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3184{
8cb8e83b 3185 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3186 struct wm8994 *control = wm8994->wm8994;
3187 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3188 struct snd_kcontrol_new controls[] = {
3189 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3190 wm8994->retune_mobile_enum,
3191 wm8994_get_retune_mobile_enum,
3192 wm8994_put_retune_mobile_enum),
3193 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3194 wm8994->retune_mobile_enum,
3195 wm8994_get_retune_mobile_enum,
3196 wm8994_put_retune_mobile_enum),
3197 SOC_ENUM_EXT("AIF2 EQ Mode",
3198 wm8994->retune_mobile_enum,
3199 wm8994_get_retune_mobile_enum,
3200 wm8994_put_retune_mobile_enum),
3201 };
3202 int ret, i, j;
3203 const char **t;
3204
3205 /* We need an array of texts for the enum API but the number
3206 * of texts is likely to be less than the number of
3207 * configurations due to the sample rate dependency of the
3208 * configurations. */
3209 wm8994->num_retune_mobile_texts = 0;
3210 wm8994->retune_mobile_texts = NULL;
3211 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3212 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3213 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3214 wm8994->retune_mobile_texts[j]) == 0)
3215 break;
3216 }
3217
3218 if (j != wm8994->num_retune_mobile_texts)
3219 continue;
3220
3221 /* Expand the array... */
3222 t = krealloc(wm8994->retune_mobile_texts,
c1a4ecd9 3223 sizeof(char *) *
9e6e96a1
MB		 3224 (wm8994->num_retune_mobile_texts + 1),
3225 GFP_KERNEL);
3226 if (t == NULL)
3227 continue;
3228
3229 /* ...store the new entry... */
c1a4ecd9 3230 t[wm8994->num_retune_mobile_texts] =
9e6e96a1
MB		 3231 pdata->retune_mobile_cfgs[i].name;
3232
3233 /* ...and remember the new version. */
3234 wm8994->num_retune_mobile_texts++;
3235 wm8994->retune_mobile_texts = t;
3236 }
3237
3238 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3239 wm8994->num_retune_mobile_texts);
3240
3241 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
3242 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3243
8cb8e83b 3244 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1
MB		 3245 ARRAY_SIZE(controls));
3246 if (ret != 0)
8cb8e83b 3247 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3248 "Failed to add ReTune Mobile controls: %d\n", ret);
3249}
3250
3251static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3252{
8cb8e83b 3253 struct snd_soc_codec *codec = wm8994->hubs.codec;
d9dd4ada
MB		 3254 struct wm8994 *control = wm8994->wm8994;
3255 struct wm8994_pdata *pdata = &control->pdata;
9e6e96a1
MB		 3256 int ret, i;
3257
3258 if (!pdata)
3259 return;
3260
3261 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3262 pdata->lineout2_diff,
3263 pdata->lineout1fb,
3264 pdata->lineout2fb,
3265 pdata->jd_scthr,
3266 pdata->jd_thr,
02e79476
MB		 3267 pdata->micb1_delay,
3268 pdata->micb2_delay,
9e6e96a1
MB		 3269 pdata->micbias1_lvl,
3270 pdata->micbias2_lvl);
3271
3272 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3273
3274 if (pdata->num_drc_cfgs) {
3275 struct snd_kcontrol_new controls[] = {
3276 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3277 wm8994_get_drc_enum, wm8994_put_drc_enum),
3278 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3279 wm8994_get_drc_enum, wm8994_put_drc_enum),
3280 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3281 wm8994_get_drc_enum, wm8994_put_drc_enum),
3282 };
3283
3284 /* We need an array of texts for the enum API */
8cb8e83b 3285 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
7270cebe 3286 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3287 if (!wm8994->drc_texts) {
8cb8e83b 3288 dev_err(wm8994->hubs.codec->dev,
9e6e96a1
MB		 3289 "Failed to allocate %d DRC config texts\n",
3290 pdata->num_drc_cfgs);
3291 return;
3292 }
3293
3294 for (i = 0; i < pdata->num_drc_cfgs; i++)
3295 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3296
3297 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3298 wm8994->drc_enum.texts = wm8994->drc_texts;
3299
8cb8e83b 3300 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
9e6e96a1 3301 ARRAY_SIZE(controls));
9e6e96a1
MB		 3302 for (i = 0; i < WM8994_NUM_DRC; i++)
3303 wm8994_set_drc(codec, i);
45a690f6
MB		 3304 } else {
3305 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3306 wm8994_drc_controls,
3307 ARRAY_SIZE(wm8994_drc_controls));
9e6e96a1
MB		 3308 }
3309
45a690f6
MB		 3310 if (ret != 0)
3311 dev_err(wm8994->hubs.codec->dev,
3312 "Failed to add DRC mode controls: %d\n", ret);
3313
3314
9e6e96a1
MB		 3315 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3316 pdata->num_retune_mobile_cfgs);
3317
3318 if (pdata->num_retune_mobile_cfgs)
3319 wm8994_handle_retune_mobile_pdata(wm8994);
3320 else
8cb8e83b 3321 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
9e6e96a1 3322 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3323
3324 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3325 if (pdata->micbias[i]) {
3326 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3327 pdata->micbias[i] & 0xffff);
3328 }
3329 }
9e6e96a1
MB		 3330}
3331
88766984
MB		 3332/**
3333 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3334 *
3335 * @codec: WM8994 codec
3336 * @jack: jack to report detection events on
3337 * @micbias: microphone bias to detect on
88766984
MB		 3338 *
3339 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3340 * being used to bring out signals to the processor then only platform
5ab230a7 3341 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3342 * be configured using snd_soc_jack_add_gpios() instead.
3343 *
3344 * Configuration of detection levels is available via the micbias1_lvl
3345 * and micbias2_lvl platform data members.
3346 */
3347int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3348 int micbias)
88766984 3349{
b2c812e2 3350 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3351 struct wm8994_micdet *micdet;
2a8a856d 3352 struct wm8994 *control = wm8994->wm8994;
87092e3c 3353 int reg, ret;
88766984 3354
87092e3c
MB		 3355 if (control->type != WM8994) {
3356 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3357 return -EINVAL;
87092e3c 3358 }
3a423157 3359
88766984
MB		 3360 switch (micbias) {
3361 case 1:
3362 micdet = &wm8994->micdet[0];
87092e3c
MB		 3363 if (jack)
3364 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3365 "MICBIAS1");
3366 else
3367 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3368 "MICBIAS1");
88766984
MB		 3369 break;
3370 case 2:
3371 micdet = &wm8994->micdet[1];
87092e3c
MB		 3372 if (jack)
3373 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3374 "MICBIAS1");
3375 else
3376 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3377 "MICBIAS1");
88766984
MB		 3378 break;
3379 default:
87092e3c 3380 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3381 return -EINVAL;
87092e3c 3382 }
88766984 3383
87092e3c
MB		 3384 if (ret != 0)
3385 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3386 micbias, ret);
3387
3388 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3389 micbias, jack);
88766984
MB		 3390
3391 /* Store the configuration */
3392 micdet->jack = jack;
87092e3c 3393 micdet->detecting = true;
88766984
MB		 3394
3395 /* If either of the jacks is set up then enable detection */
3396 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3397 reg = WM8994_MICD_ENA;
87092e3c 3398 else
88766984
MB		 3399 reg = 0;
3400
3401 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3402
d9f34df7
CR		 3403 /* enable MICDET and MICSHRT deboune */
3404 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3405 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3406 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3407 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3408
87092e3c
MB		 3409 snd_soc_dapm_sync(&codec->dapm);
3410
88766984
MB		 3411 return 0;
3412}
3413EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3414
e9b54de4 3415static void wm8994_mic_work(struct work_struct *work)
88766984 3416{
e9b54de4
MB		 3417 struct wm8994_priv *priv = container_of(work,
3418 struct wm8994_priv,
3419 mic_work.work);
fdfc4f3e
MB		 3420 struct regmap *regmap = priv->wm8994->regmap;
3421 struct device *dev = priv->wm8994->dev;
3422 unsigned int reg;
3423 int ret;
88766984
MB		 3424 int report;
3425
b8176627
MB		 3426 pm_runtime_get_sync(dev);
3427
fdfc4f3e
MB		 3428 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, &reg);
3429 if (ret < 0) {
3430 dev_err(dev, "Failed to read microphone status: %d\n",
3431 ret);
b8176627 3432 pm_runtime_put(dev);
e9b54de4 3433 return;
88766984
MB		 3434 }
3435
fdfc4f3e 3436 dev_dbg(dev, "Microphone status: %x\n", reg);
88766984
MB		 3437
3438 report = 0;
87092e3c
MB		 3439 if (reg & WM8994_MIC1_DET_STS) {
3440 if (priv->micdet[0].detecting)
3441 report = SND_JACK_HEADSET;
3442 }
3443 if (reg & WM8994_MIC1_SHRT_STS) {
3444 if (priv->micdet[0].detecting)
3445 report = SND_JACK_HEADPHONE;
3446 else
3447 report |= SND_JACK_BTN_0;
3448 }
3449 if (report)
3450 priv->micdet[0].detecting = false;
3451 else
3452 priv->micdet[0].detecting = true;
3453
88766984 3454 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3455 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3456
3457 report = 0;
87092e3c
MB		 3458 if (reg & WM8994_MIC2_DET_STS) {
3459 if (priv->micdet[1].detecting)
3460 report = SND_JACK_HEADSET;
3461 }
3462 if (reg & WM8994_MIC2_SHRT_STS) {
3463 if (priv->micdet[1].detecting)
3464 report = SND_JACK_HEADPHONE;
3465 else
3466 report |= SND_JACK_BTN_0;
3467 }
3468 if (report)
3469 priv->micdet[1].detecting = false;
3470 else
3471 priv->micdet[1].detecting = true;
3472
88766984 3473 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3474 SND_JACK_HEADSET | SND_JACK_BTN_0);
b8176627
MB		 3475
3476 pm_runtime_put(dev);
e9b54de4
MB		 3477}
3478
3479static irqreturn_t wm8994_mic_irq(int irq, void *data)
3480{
3481 struct wm8994_priv *priv = data;
8cb8e83b 3482 struct snd_soc_codec *codec = priv->hubs.codec;
e9b54de4
MB		 3483
3484#ifndef CONFIG_SND_SOC_WM8994_MODULE
3485 trace_snd_soc_jack_irq(dev_name(codec->dev));
3486#endif
3487
3488 pm_wakeup_event(codec->dev, 300);
3489
3490 schedule_delayed_work(&priv->mic_work, msecs_to_jiffies(250));
88766984
MB		 3491
3492 return IRQ_HANDLED;
3493}
3494
f02b0de0
MB		 3495static void wm1811_micd_stop(struct snd_soc_codec *codec)
3496{
3497 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3498
3499 if (!wm8994->jackdet)
3500 return;
3501
3502 mutex_lock(&wm8994->accdet_lock);
3503
3504 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3505
3506 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3507
3508 mutex_unlock(&wm8994->accdet_lock);
3509
3510 if (wm8994->wm8994->pdata.jd_ext_cap)
3511 snd_soc_dapm_disable_pin(&codec->dapm,
3512 "MICBIAS2");
3513}
3514
78b76dbe 3515static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
821edd2f 3516{
821edd2f 3517 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3518 int report;
821edd2f 3519
78b76dbe
MB		 3520 report = 0;
3521 if (status & 0x4)
3522 report |= SND_JACK_BTN_0;
3523
3524 if (status & 0x8)
3525 report |= SND_JACK_BTN_1;
3526
3527 if (status & 0x10)
3528 report |= SND_JACK_BTN_2;
3529
3530 if (status & 0x20)
3531 report |= SND_JACK_BTN_3;
3532
3533 if (status & 0x40)
3534 report |= SND_JACK_BTN_4;
3535
3536 if (status & 0x80)
3537 report |= SND_JACK_BTN_5;
3538
3539 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3540 wm8994->btn_mask);
3541}
3542
70bd3b29
MB		 3543static void wm8958_open_circuit_work(struct work_struct *work)
3544{
3545 struct wm8994_priv *wm8994 = container_of(work,
3546 struct wm8994_priv,
3547 open_circuit_work.work);
3548 struct device *dev = wm8994->wm8994->dev;
3549
3550 wm1811_micd_stop(wm8994->hubs.codec);
3551
3552 mutex_lock(&wm8994->accdet_lock);
3553
3554 dev_dbg(dev, "Reporting open circuit\n");
3555
3556 wm8994->jack_mic = false;
3557 wm8994->mic_detecting = true;
3558
3559 wm8958_micd_set_rate(wm8994->hubs.codec);
3560
3561 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3562 wm8994->btn_mask |
3563 SND_JACK_HEADSET);
3564
3565 mutex_unlock(&wm8994->accdet_lock);
3566}
3567
98869f68 3568static void wm8958_mic_id(void *data, u16 status)
78b76dbe 3569{
98869f68 3570 struct snd_soc_codec *codec = data;
78b76dbe 3571 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
a1691343 3572
af6b6fe4 3573 /* Either nothing present or just starting detection */
b00adf76 3574 if (!(status & WM8958_MICD_STS)) {
f02b0de0
MB		 3575 /* If nothing present then clear our statuses */
3576 dev_dbg(codec->dev, "Detected open circuit\n");
f02b0de0 3577
70bd3b29
MB		 3578 schedule_delayed_work(&wm8994->open_circuit_work,
3579 msecs_to_jiffies(2500));
b00adf76
MB		 3580 return;
3581 }
821edd2f 3582
b00adf76
MB		 3583 /* If the measurement is showing a high impedence we've got a
3584 * microphone.
3585 */
78b76dbe 3586 if (status & 0x600) {
b00adf76
MB		 3587 dev_dbg(codec->dev, "Detected microphone\n");
3588
157a75e6 3589 wm8994->mic_detecting = false;
b00adf76
MB		 3590 wm8994->jack_mic = true;
3591
3592 wm8958_micd_set_rate(codec);
3593
3594 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3595 SND_JACK_HEADSET);
3596 }
821edd2f 3597
b00adf76 3598
78b76dbe 3599 if (status & 0xfc) {
b00adf76 3600 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3601 wm8994->mic_detecting = false;
b00adf76
MB		 3602
3603 wm8958_micd_set_rate(codec);
3604
af6b6fe4 3605 /* If we have jackdet that will detect removal */
f02b0de0 3606 wm1811_micd_stop(codec);
ecd1732f
MB		 3607
3608 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3609 SND_JACK_HEADSET);
b00adf76 3610 }
821edd2f 3611}
b00adf76 3612
c0cc3f16
MB		 3613/* Deferred mic detection to allow for extra settling time */
3614static void wm1811_mic_work(struct work_struct *work)
3615{
3616 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3617 mic_work.work);
d9dd4ada 3618 struct wm8994 *control = wm8994->wm8994;
c0cc3f16 3619 struct snd_soc_codec *codec = wm8994->hubs.codec;
4585790d 3620
c0cc3f16 3621 pm_runtime_get_sync(codec->dev);
4585790d 3622
c0cc3f16 3623 /* If required for an external cap force MICBIAS on */
d9dd4ada 3624 if (control->pdata.jd_ext_cap) {
c0cc3f16
MB		 3625 snd_soc_dapm_force_enable_pin(&codec->dapm,
3626 "MICBIAS2");
3627 snd_soc_dapm_sync(&codec->dapm);
3628 }
4585790d 3629
c0cc3f16 3630 mutex_lock(&wm8994->accdet_lock);
4585790d 3631
c0cc3f16 3632 dev_dbg(codec->dev, "Starting mic detection\n");
4585790d 3633
63dd5452
MB		 3634 /* Use a user-supplied callback if we have one */
3635 if (wm8994->micd_cb) {
3636 wm8994->micd_cb(wm8994->micd_cb_data);
3637 } else {
3638 /*
3639 * Start off measument of microphone impedence to find out
3640 * what's actually there.
3641 */
3642 wm8994->mic_detecting = true;
3643 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
4585790d 3644
63dd5452
MB		 3645 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3646 WM8958_MICD_ENA, WM8958_MICD_ENA);
b00adf76 3647 }
c0cc3f16
MB		 3648
3649 mutex_unlock(&wm8994->accdet_lock);
3650
3651 pm_runtime_put(codec->dev);
821edd2f
MB		 3652}
3653
af6b6fe4
MB		 3654static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3655{
3656 struct wm8994_priv *wm8994 = data;
d9dd4ada 3657 struct wm8994 *control = wm8994->wm8994;
8cb8e83b 3658 struct snd_soc_codec *codec = wm8994->hubs.codec;
c0cc3f16 3659 int reg, delay;
c986564b 3660 bool present;
af6b6fe4 3661
b8176627
MB		 3662 pm_runtime_get_sync(codec->dev);
3663
2da1c4bf
MB		 3664 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3665
af6b6fe4
MB		 3666 mutex_lock(&wm8994->accdet_lock);
3667
3668 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3669 if (reg < 0) {
3670 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3671 mutex_unlock(&wm8994->accdet_lock);
b8176627 3672 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3673 return IRQ_NONE;
3674 }
3675
3676 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3677
c986564b 3678 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3679
c986564b
MB		 3680 if (present) {
3681 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3682
e9d9a968
MB		 3683 wm8958_micd_set_rate(codec);
3684
55a27786
MB		 3685 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3686 WM8958_MICB2_DISCH, 0);
3687
378ec0ca
MB		 3688 /* Disable debounce while inserted */
3689 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3690 WM1811_JACKDET_DB, 0);
3691
d9dd4ada 3692 delay = control->pdata.micdet_delay;
c0cc3f16
MB		 3693 schedule_delayed_work(&wm8994->mic_work,
3694 msecs_to_jiffies(delay));
af6b6fe4
MB		 3695 } else {
3696 dev_dbg(codec->dev, "Jack not detected\n");
3697
c0cc3f16
MB		 3698 cancel_delayed_work_sync(&wm8994->mic_work);
3699
55a27786
MB		 3700 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3701 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3702
378ec0ca
MB		 3703 /* Enable debounce while removed */
3704 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3705 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3706
af6b6fe4
MB		 3707 wm8994->mic_detecting = false;
3708 wm8994->jack_mic = false;
3709 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3710 WM8958_MICD_ENA, 0);
3711 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3712 }
3713
3714 mutex_unlock(&wm8994->accdet_lock);
3715
c0cc3f16 3716 /* Turn off MICBIAS if it was on for an external cap */
d9dd4ada 3717 if (control->pdata.jd_ext_cap && !present)
c0cc3f16 3718 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3719
3720 if (present)
3721 snd_soc_jack_report(wm8994->micdet[0].jack,
3722 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3723 else
3724 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3725 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3726 wm8994->btn_mask);
3727
99af79df
MB		 3728 /* Since we only report deltas force an update, ensures we
3729 * avoid bootstrapping issues with the core. */
3730 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3731
b8176627 3732 pm_runtime_put(codec->dev);
af6b6fe4
MB		 3733 return IRQ_HANDLED;
3734}
3735
99af79df
MB		 3736static void wm1811_jackdet_bootstrap(struct work_struct *work)
3737{
3738 struct wm8994_priv *wm8994 = container_of(work,
3739 struct wm8994_priv,
3740 jackdet_bootstrap.work);
3741 wm1811_jackdet_irq(0, wm8994);
3742}
3743
821edd2f
MB		 3744/**
3745 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3746 *
3747 * @codec: WM8958 codec
3748 * @jack: jack to report detection events on
3749 *
3750 * Enable microphone detection functionality for the WM8958. By
3751 * default simple detection which supports the detection of up to 6
3752 * buttons plus video and microphone functionality is supported.
3753 *
3754 * The WM8958 has an advanced jack detection facility which is able to
3755 * support complex accessory detection, especially when used in
3756 * conjunction with external circuitry. In order to provide maximum
3757 * flexiblity a callback is provided which allows a completely custom
3758 * detection algorithm.
3759 */
3760int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
98869f68
MB		 3761 wm1811_micdet_cb det_cb, void *det_cb_data,
3762 wm1811_mic_id_cb id_cb, void *id_cb_data)
821edd2f
MB		 3763{
3764 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3765 struct wm8994 *control = wm8994->wm8994;
4585790d 3766 u16 micd_lvl_sel;
821edd2f 3767
81204c84
MB		 3768 switch (control->type) {
3769 case WM1811:
3770 case WM8958:
3771 break;
3772 default:
821edd2f 3773 return -EINVAL;
81204c84 3774 }
821edd2f
MB		 3775
3776 if (jack) {
4cdf5e49 3777 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3778 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3779
821edd2f 3780 wm8994->micdet[0].jack = jack;
821edd2f 3781
98869f68
MB		 3782 if (det_cb) {
3783 wm8994->micd_cb = det_cb;
3784 wm8994->micd_cb_data = det_cb_data;
63dd5452
MB		 3785 } else {
3786 wm8994->mic_detecting = true;
3787 wm8994->jack_mic = false;
3788 }
b00adf76 3789
98869f68
MB		 3790 if (id_cb) {
3791 wm8994->mic_id_cb = id_cb;
3792 wm8994->mic_id_cb_data = id_cb_data;
3793 } else {
3794 wm8994->mic_id_cb = wm8958_mic_id;
3795 wm8994->mic_id_cb_data = codec;
3796 }
b00adf76
MB		 3797
3798 wm8958_micd_set_rate(codec);
3799
4585790d 3800 /* Detect microphones and short circuits by default */
d9dd4ada
MB		 3801 if (control->pdata.micd_lvl_sel)
3802 micd_lvl_sel = control->pdata.micd_lvl_sel;
4585790d
MB		 3803 else
3804 micd_lvl_sel = 0x41;
3805
3806 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3807 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3808 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3809
b00adf76 3810 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3811 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3812
af6b6fe4
MB		 3813 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3814
3815 /*
3816 * If we can use jack detection start off with that,
3817 * otherwise jump straight to microphone detection.
3818 */
3819 if (wm8994->jackdet) {
99af79df
MB		 3820 /* Disable debounce for the initial detect */
3821 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3822 WM1811_JACKDET_DB, 0);
3823
55a27786
MB		 3824 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3825 WM8958_MICB2_DISCH,
3826 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3827 snd_soc_update_bits(codec, WM8994_LDO_1,
3828 WM8994_LDO1_DISCH, 0);
3829 wm1811_jackdet_set_mode(codec,
3830 WM1811_JACKDET_MODE_JACK);
3831 } else {
3832 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3833 WM8958_MICD_ENA, WM8958_MICD_ENA);
3834 }
3835
821edd2f
MB		 3836 } else {
3837 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3838 WM8958_MICD_ENA, 0);
afaf1591 3839 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3840 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3841 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3842 }
3843
3844 return 0;
3845}
3846EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3847
2da1c4bf
MB		 3848static void wm8958_mic_work(struct work_struct *work)
3849{
3850 struct wm8994_priv *wm8994 = container_of(work,
3851 struct wm8994_priv,
3852 mic_complete_work.work);
3853 struct snd_soc_codec *codec = wm8994->hubs.codec;
3854
3855 dev_crit(codec->dev, "MIC WORK %x\n", wm8994->mic_status);
3856
3857 pm_runtime_get_sync(codec->dev);
3858
3859 mutex_lock(&wm8994->accdet_lock);
3860
3861 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3862
3863 mutex_unlock(&wm8994->accdet_lock);
3864
3865 pm_runtime_put(codec->dev);
3866
3867 dev_crit(codec->dev, "MIC WORK %x DONE\n", wm8994->mic_status);
3868}
3869
821edd2f
MB		 3870static irqreturn_t wm8958_mic_irq(int irq, void *data)
3871{
3872 struct wm8994_priv *wm8994 = data;
8cb8e83b 3873 struct snd_soc_codec *codec = wm8994->hubs.codec;
2da1c4bf 3874 int reg, count, ret, id_delay;
821edd2f 3875
af6b6fe4
MB		 3876 /*
3877 * Jack detection may have detected a removal simulataneously
3878 * with an update of the MICDET status; if so it will have
3879 * stopped detection and we can ignore this interrupt.
3880 */
c986564b 3881 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3882 return IRQ_HANDLED;
af6b6fe4 3883
2da1c4bf 3884 cancel_delayed_work_sync(&wm8994->mic_complete_work);
70bd3b29
MB		 3885 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3886
b8176627
MB		 3887 pm_runtime_get_sync(codec->dev);
3888
19940b3d
MB		 3889 /* We may occasionally read a detection without an impedence
3890 * range being provided - if that happens loop again.
3891 */
3892 count = 10;
3893 do {
3894 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3895 if (reg < 0) {
3896 dev_err(codec->dev,
3897 "Failed to read mic detect status: %d\n",
3898 reg);
b8176627 3899 pm_runtime_put(codec->dev);
19940b3d
MB		 3900 return IRQ_NONE;
3901 }
821edd2f 3902
19940b3d
MB		 3903 if (!(reg & WM8958_MICD_VALID)) {
3904 dev_dbg(codec->dev, "Mic detect data not valid\n");
3905 goto out;
3906 }
3907
3908 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3909 break;
3910
3911 msleep(1);
3912 } while (count--);
3913
3914 if (count == 0)
ec8f53fb 3915 dev_warn(codec->dev, "No impedance range reported for jack\n");
821edd2f 3916
7116f452 3917#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3918 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3919#endif
2bbb5d66 3920
e874de43
MB		 3921 /* Avoid a transient report when the accessory is being removed */
3922 if (wm8994->jackdet) {
8afd0ef2
MB		 3923 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3924 if (ret < 0) {
e874de43 3925 dev_err(codec->dev, "Failed to read jack status: %d\n",
8afd0ef2
MB		 3926 ret);
3927 } else if (!(ret & WM1811_JACKDET_LVL)) {
e874de43 3928 dev_dbg(codec->dev, "Ignoring removed jack\n");
9e43088b 3929 goto out;
e874de43 3930 }
9767a58b
MB		 3931 } else if (!(reg & WM8958_MICD_STS)) {
3932 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3933 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3934 wm8994->btn_mask);
7afce3f5 3935 wm8994->mic_detecting = true;
9767a58b 3936 goto out;
e874de43
MB		 3937 }
3938
2da1c4bf
MB		 3939 wm8994->mic_status = reg;
3940 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3941
78b76dbe 3942 if (wm8994->mic_detecting)
2da1c4bf
MB		 3943 schedule_delayed_work(&wm8994->mic_complete_work,
3944 msecs_to_jiffies(id_delay));
821edd2f 3945 else
78b76dbe 3946 wm8958_button_det(codec, reg);
821edd2f
MB		 3947
3948out:
b8176627 3949 pm_runtime_put(codec->dev);
821edd2f
MB		 3950 return IRQ_HANDLED;
3951}
3952
3b1af3f8
MB		 3953static irqreturn_t wm8994_fifo_error(int irq, void *data)
3954{
3955 struct snd_soc_codec *codec = data;
3956
3957 dev_err(codec->dev, "FIFO error\n");
3958
3959 return IRQ_HANDLED;
3960}
3961
f0b182b0
MB		 3962static irqreturn_t wm8994_temp_warn(int irq, void *data)
3963{
3964 struct snd_soc_codec *codec = data;
3965
3966 dev_err(codec->dev, "Thermal warning\n");
3967
3968 return IRQ_HANDLED;
3969}
3970
3971static irqreturn_t wm8994_temp_shut(int irq, void *data)
3972{
3973 struct snd_soc_codec *codec = data;
3974
3975 dev_crit(codec->dev, "Thermal shutdown\n");
3976
3977 return IRQ_HANDLED;
3978}
3979
f0fba2ad 3980static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3981{
d9a7666f 3982 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3983 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3984 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3985 unsigned int reg;
ec62dbd7 3986 int ret, i;
9e6e96a1 3987
8cb8e83b 3988 wm8994->hubs.codec = codec;
d9a7666f 3989 codec->control_data = control->regmap;
9e6e96a1 3990
d9a7666f 3991 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3992
af6b6fe4 3993 mutex_init(&wm8994->accdet_lock);
99af79df
MB		 3994 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
3995 wm1811_jackdet_bootstrap);
70bd3b29
MB		 3996 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
3997 wm8958_open_circuit_work);
af6b6fe4 3998
c0cc3f16
MB		 3999 switch (control->type) {
4000 case WM8994:
4001 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4002 break;
4003 case WM1811:
4004 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4005 break;
4006 default:
4007 break;
4008 }
4009
2da1c4bf
MB		 4010 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4011
c7ebf932
MB		 4012 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4013 init_completion(&wm8994->fll_locked[i]);
4014
d9dd4ada 4015 wm8994->micdet_irq = control->pdata.micdet_irq;
9b7c525d 4016
39fb51a1 4017 pm_runtime_enable(codec->dev);
5fab5174 4018 pm_runtime_idle(codec->dev);
39fb51a1 4019
f959dee9
MB		 4020 /* By default use idle_bias_off, will override for WM8994 */
4021 codec->dapm.idle_bias_off = 1;
4022
9e6e96a1 4023 /* Set revision-specific configuration */
3a423157
MB		 4024 switch (control->type) {
4025 case WM8994:
f959dee9 4026 /* Single ended line outputs should have VMID on. */
d9dd4ada
MB		 4027 if (!control->pdata.lineout1_diff ||
4028 !control->pdata.lineout2_diff)
f959dee9
MB		 4029 codec->dapm.idle_bias_off = 0;
4030
da445afe 4031 switch (control->revision) {
3a423157
MB		 4032 case 2:
4033 case 3:
4537c4e7
MB		 4034 wm8994->hubs.dcs_codes_l = -5;
4035 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 4036 wm8994->hubs.hp_startup_mode = 1;
4037 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 4038 wm8994->hubs.series_startup = 1;
3a423157
MB		 4039 break;
4040 default:
79ef0abc 4041 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 4042 break;
4043 }
280ec8b7 4044 break;
3a423157
MB		 4045
4046 case WM8958:
8437f700 4047 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 4048 wm8994->hubs.hp_startup_mode = 1;
20dc24a9 4049
da445afe 4050 switch (control->revision) {
20dc24a9
MB		 4051 case 0:
4052 break;
4053 default:
4054 wm8994->fll_byp = true;
4055 break;
4056 }
9e6e96a1 4057 break;
3a423157 4058
81204c84
MB		 4059 case WM1811:
4060 wm8994->hubs.dcs_readback_mode = 2;
4061 wm8994->hubs.no_series_update = 1;
29fdc360 4062 wm8994->hubs.hp_startup_mode = 1;
af31a227 4063 wm8994->hubs.no_cache_dac_hp_direct = true;
20dc24a9 4064 wm8994->fll_byp = true;
81204c84 4065
72222be3
MB		 4066 wm8994->hubs.dcs_codes_l = -9;
4067 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 4068
4069 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4070 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4071 break;
4072
9e6e96a1
MB		 4073 default:
4074 break;
4075 }
9e6e96a1 4076
2a8a856d 4077 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 4078 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 4079 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 4080 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 4081 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 4082 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 4083
2a8a856d 4084 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 4085 wm_hubs_dcs_done, "DC servo done",
4086 &wm8994->hubs);
4087 if (ret == 0)
4088 wm8994->hubs.dcs_done_irq = true;
4089
3a423157
MB		 4090 switch (control->type) {
4091 case WM8994:
9b7c525d
MB		 4092 if (wm8994->micdet_irq) {
4093 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4094 wm8994_mic_irq,
4095 IRQF_TRIGGER_RISING,
4096 "Mic1 detect",
4097 wm8994);
4098 if (ret != 0)
4099 dev_warn(codec->dev,
4100 "Failed to request Mic1 detect IRQ: %d\n",
4101 ret);
4102 }
3a423157 4103
2a8a856d 4104 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4105 WM8994_IRQ_MIC1_SHRT,
4106 wm8994_mic_irq, "Mic 1 short",
4107 wm8994);
4108 if (ret != 0)
4109 dev_warn(codec->dev,
4110 "Failed to request Mic1 short IRQ: %d\n",
4111 ret);
4112
2a8a856d 4113 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4114 WM8994_IRQ_MIC2_DET,
4115 wm8994_mic_irq, "Mic 2 detect",
4116 wm8994);
4117 if (ret != 0)
4118 dev_warn(codec->dev,
4119 "Failed to request Mic2 detect IRQ: %d\n",
4120 ret);
4121
2a8a856d 4122 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 4123 WM8994_IRQ_MIC2_SHRT,
4124 wm8994_mic_irq, "Mic 2 short",
4125 wm8994);
4126 if (ret != 0)
4127 dev_warn(codec->dev,
4128 "Failed to request Mic2 short IRQ: %d\n",
4129 ret);
4130 break;
821edd2f
MB		 4131
4132 case WM8958:
81204c84 4133 case WM1811:
9b7c525d
MB		 4134 if (wm8994->micdet_irq) {
4135 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4136 wm8958_mic_irq,
4137 IRQF_TRIGGER_RISING,
4138 "Mic detect",
4139 wm8994);
4140 if (ret != 0)
4141 dev_warn(codec->dev,
4142 "Failed to request Mic detect IRQ: %d\n",
4143 ret);
b4046d01
MB		 4144 } else {
4145 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4146 wm8958_mic_irq, "Mic detect",
4147 wm8994);
9b7c525d 4148 }
3a423157 4149 }
88766984 4150
af6b6fe4
MB		 4151 switch (control->type) {
4152 case WM1811:
da445afe 4153 if (control->cust_id > 1 || control->revision > 1) {
af6b6fe4
MB		 4154 ret = wm8994_request_irq(wm8994->wm8994,
4155 WM8994_IRQ_GPIO(6),
4156 wm1811_jackdet_irq, "JACKDET",
4157 wm8994);
4158 if (ret == 0)
4159 wm8994->jackdet = true;
4160 }
4161 break;
4162 default:
4163 break;
4164 }
4165
c7ebf932
MB		 4166 wm8994->fll_locked_irq = true;
4167 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 4168 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 4169 WM8994_IRQ_FLL1_LOCK + i,
4170 wm8994_fll_locked_irq, "FLL lock",
4171 &wm8994->fll_locked[i]);
4172 if (ret != 0)
4173 wm8994->fll_locked_irq = false;
4174 }
4175
27060b3c
MB		 4176 /* Make sure we can read from the GPIOs if they're inputs */
4177 pm_runtime_get_sync(codec->dev);
4178
9e6e96a1
MB		 4179 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4180 * configured on init - if a system wants to do this dynamically
4181 * at runtime we can deal with that then.
4182 */
d9a7666f 4183 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 4184 if (ret < 0) {
4185 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 4186 goto err_irq;
9e6e96a1 4187 }
d9a7666f 4188 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4189 wm8994->lrclk_shared[0] = 1;
4190 wm8994_dai[0].symmetric_rates = 1;
4191 } else {
4192 wm8994->lrclk_shared[0] = 0;
4193 }
4194
d9a7666f 4195 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 4196 if (ret < 0) {
4197 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 4198 goto err_irq;
9e6e96a1 4199 }
d9a7666f 4200 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 4201 wm8994->lrclk_shared[1] = 1;
4202 wm8994_dai[1].symmetric_rates = 1;
4203 } else {
4204 wm8994->lrclk_shared[1] = 0;
4205 }
4206
27060b3c
MB		 4207 pm_runtime_put(codec->dev);
4208
bfd37bb5
MB		 4209 /* Latch volume update bits */
4210 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4211 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4212 wm8994_vu_bits[i].mask,
4213 wm8994_vu_bits[i].mask);
9e6e96a1
MB		 4214
4215 /* Set the low bit of the 3D stereo depth so TLV matches */
4216 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4217 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4218 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4219 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4220 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4221 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4222 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4223 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4224 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4225
5b739670
MB		 4226 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4227 * use this; it only affects behaviour on idle TDM clock
4228 * cycles. */
4229 switch (control->type) {
4230 case WM8994:
4231 case WM8958:
4232 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4233 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4234 break;
4235 default:
4236 break;
4237 }
d1ce6b20 4238
500fa30e
MB		 4239 /* Put MICBIAS into bypass mode by default on newer devices */
4240 switch (control->type) {
4241 case WM8958:
4242 case WM1811:
4243 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4244 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4245 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4246 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4247 break;
4248 default:
4249 break;
4250 }
4251
c340304d
MB		 4252 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4253 wm_hubs_update_class_w(codec);
9e6e96a1 4254
f0fba2ad 4255 wm8994_handle_pdata(wm8994);
9e6e96a1 4256
f0fba2ad 4257 wm_hubs_add_analogue_controls(codec);
022658be 4258 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 4259 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 4260 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 4261 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 4262
4263 switch (control->type) {
4264 case WM8994:
4265 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4266 ARRAY_SIZE(wm8994_specific_dapm_widgets));
da445afe 4267 if (control->revision < 4) {
173efa09
DP		 4268 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4269 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 4270 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4271 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 4272 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4273 ARRAY_SIZE(wm8994_dac_revd_widgets));
4274 } else {
173efa09
DP		 4275 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4276 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 4277 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4278 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 4279 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4280 ARRAY_SIZE(wm8994_dac_widgets));
4281 }
c4431df0
MB		 4282 break;
4283 case WM8958:
022658be 4284 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 4285 ARRAY_SIZE(wm8958_snd_controls));
4286 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4287 ARRAY_SIZE(wm8958_dapm_widgets));
da445afe 4288 if (control->revision < 1) {
780e2806
MB		 4289 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4290 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4291 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4292 ARRAY_SIZE(wm8994_adc_revd_widgets));
4293 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4294 ARRAY_SIZE(wm8994_dac_revd_widgets));
4295 } else {
4296 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4297 ARRAY_SIZE(wm8994_lateclk_widgets));
4298 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4299 ARRAY_SIZE(wm8994_adc_widgets));
4300 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4301 ARRAY_SIZE(wm8994_dac_widgets));
4302 }
c4431df0 4303 break;
81204c84
MB		 4304
4305 case WM1811:
022658be 4306 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 4307 ARRAY_SIZE(wm8958_snd_controls));
4308 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4309 ARRAY_SIZE(wm8958_dapm_widgets));
4310 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4311 ARRAY_SIZE(wm8994_lateclk_widgets));
4312 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4313 ARRAY_SIZE(wm8994_adc_widgets));
4314 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4315 ARRAY_SIZE(wm8994_dac_widgets));
4316 break;
c4431df0 4317 }
c4431df0 4318
f0fba2ad 4319 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 4320 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 4321
c4431df0
MB		 4322 switch (control->type) {
4323 case WM8994:
4324 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4325 ARRAY_SIZE(wm8994_intercon));
6ed8f148 4326
da445afe 4327 if (control->revision < 4) {
6ed8f148
MB		 4328 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4329 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 4330 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4331 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4332 } else {
4333 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4334 ARRAY_SIZE(wm8994_lateclk_intercon));
4335 }
c4431df0
MB		 4336 break;
4337 case WM8958:
da445afe 4338 if (control->revision < 1) {
15676937
CR		 4339 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4340 ARRAY_SIZE(wm8994_intercon));
780e2806
MB		 4341 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4342 ARRAY_SIZE(wm8994_revd_intercon));
4343 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4344 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4345 } else {
4346 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4347 ARRAY_SIZE(wm8994_lateclk_intercon));
4348 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4349 ARRAY_SIZE(wm8958_intercon));
4350 }
f701a2e5
MB		 4351
4352 wm8958_dsp2_init(codec);
c4431df0 4353 break;
81204c84
MB		 4354 case WM1811:
4355 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4356 ARRAY_SIZE(wm8994_lateclk_intercon));
4357 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4358 ARRAY_SIZE(wm8958_intercon));
4359 break;
c4431df0
MB		 4360 }
4361
9e6e96a1
MB		 4362 return 0;
4363
88766984 4364err_irq:
af6b6fe4
MB		 4365 if (wm8994->jackdet)
4366 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 4367 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4368 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4369 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 4370 if (wm8994->micdet_irq)
4371 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 4372 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 4374 &wm8994->fll_locked[i]);
2a8a856d 4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4376 &wm8994->hubs);
2a8a856d
MB		 4377 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4378 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4379 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 4380
9e6e96a1
MB		 4381 return ret;
4382}
4383
34ff0f95 4384static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 4385{
f0fba2ad 4386 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 4387 struct wm8994 *control = wm8994->wm8994;
c7ebf932 4388 int i;
9e6e96a1
MB		 4389
4390 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 4391
39fb51a1
MB		 4392 pm_runtime_disable(codec->dev);
4393
c7ebf932 4394 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 4395 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 4396 &wm8994->fll_locked[i]);
4397
2a8a856d 4398 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 4399 &wm8994->hubs);
2a8a856d
MB		 4400 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4401 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4402 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 4403
af6b6fe4
MB		 4404 if (wm8994->jackdet)
4405 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4406
3a423157
MB		 4407 switch (control->type) {
4408 case WM8994:
9b7c525d
MB		 4409 if (wm8994->micdet_irq)
4410 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 4411 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 4412 wm8994);
2a8a856d 4413 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 4414 wm8994);
2a8a856d 4415 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 4416 wm8994);
4417 break;
821edd2f 4418
81204c84 4419 case WM1811:
821edd2f 4420 case WM8958:
9b7c525d
MB		 4421 if (wm8994->micdet_irq)
4422 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4423 break;
3a423157 4424 }
34ff0f95
JJ		 4425 release_firmware(wm8994->mbc);
4426 release_firmware(wm8994->mbc_vss);
4427 release_firmware(wm8994->enh_eq);
24fb2b11 4428 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4429 return 0;
4430}
4431
f0fba2ad
LG		 4432static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4433 .probe = wm8994_codec_probe,
4434 .remove = wm8994_codec_remove,
4752a887
MB		 4435 .suspend = wm8994_codec_suspend,
4436 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4437 .set_bias_level = wm8994_set_bias_level,
4438};
4439
7a79e94e 4440static int wm8994_probe(struct platform_device *pdev)
f0fba2ad 4441{
2bc16ed8
MB		 4442 struct wm8994_priv *wm8994;
4443
4444 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4445 GFP_KERNEL);
4446 if (wm8994 == NULL)
4447 return -ENOMEM;
4448 platform_set_drvdata(pdev, wm8994);
4449
4450 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
2bc16ed8 4451
f0fba2ad
LG		 4452 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4453 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4454}
4455
7a79e94e 4456static int wm8994_remove(struct platform_device *pdev)
f0fba2ad
LG		 4457{
4458 snd_soc_unregister_codec(&pdev->dev);
4459 return 0;
4460}
4461
4752a887
MB		 4462#ifdef CONFIG_PM_SLEEP
4463static int wm8994_suspend(struct device *dev)
4464{
4465 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4466
4467 /* Drop down to power saving mode when system is suspended */
4468 if (wm8994->jackdet && !wm8994->active_refcount)
4469 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4470 WM1811_JACKDET_MODE_MASK,
4471 wm8994->jackdet_mode);
4472
4473 return 0;
4474}
4475
4476static int wm8994_resume(struct device *dev)
4477{
4478 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4479
78b76dbe 4480 if (wm8994->jackdet && wm8994->jackdet_mode)
4752a887
MB		 4481 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4482 WM1811_JACKDET_MODE_MASK,
4483 WM1811_JACKDET_MODE_AUDIO);
4484
4485 return 0;
4486}
4487#endif
4488
4489static const struct dev_pm_ops wm8994_pm_ops = {
4490 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4491};
4492
9e6e96a1
MB		 4493static struct platform_driver wm8994_codec_driver = {
4494 .driver = {
4752a887
MB		 4495 .name = "wm8994-codec",
4496 .owner = THIS_MODULE,
4497 .pm = &wm8994_pm_ops,
4498 },
f0fba2ad 4499 .probe = wm8994_probe,
7a79e94e 4500 .remove = wm8994_remove,
9e6e96a1
MB		 4501};
4502
5bbcc3c0 4503module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4504
4505MODULE_DESCRIPTION("ASoC WM8994 driver");
4506MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4507MODULE_LICENSE("GPL");
4508MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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