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ASoC: Implement support for enhanced AIF3 on WM8958
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
5a0e3ad6 22#include <linux/slab.h>
9e6e96a1
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
9e6e96a1
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <linux/mfd/wm8994/core.h>
31#include <linux/mfd/wm8994/registers.h>
32#include <linux/mfd/wm8994/pdata.h>
33#include <linux/mfd/wm8994/gpio.h>
34
35#include "wm8994.h"
36#include "wm_hubs.h"
37
9e6e96a1
MB		 38struct fll_config {
39 int src;
40 int in;
41 int out;
42};
43
44#define WM8994_NUM_DRC 3
45#define WM8994_NUM_EQ 3
46
47static int wm8994_drc_base[] = {
48 WM8994_AIF1_DRC1_1,
49 WM8994_AIF1_DRC2_1,
50 WM8994_AIF2_DRC_1,
51};
52
53static int wm8994_retune_mobile_base[] = {
54 WM8994_AIF1_DAC1_EQ_GAINS_1,
55 WM8994_AIF1_DAC2_EQ_GAINS_1,
56 WM8994_AIF2_EQ_GAINS_1,
57};
58
59#define WM8994_REG_CACHE_SIZE 0x621
60
88766984
MB		 61struct wm8994_micdet {
62 struct snd_soc_jack *jack;
63 int det;
64 int shrt;
65};
66
9e6e96a1
MB		 67/* codec private data */
68struct wm8994_priv {
69 struct wm_hubs_data hubs;
f0fba2ad
LG		 70 enum snd_soc_control_type control_type;
71 void *control_data;
72 struct snd_soc_codec *codec;
9e6e96a1
MB		 73 u16 reg_cache[WM8994_REG_CACHE_SIZE + 1];
74 int sysclk[2];
75 int sysclk_rate[2];
76 int mclk[2];
77 int aifclk[2];
78 struct fll_config fll[2], fll_suspend[2];
79
80 int dac_rates[2];
81 int lrclk_shared[2];
82
83 /* Platform dependant DRC configuration */
84 const char **drc_texts;
85 int drc_cfg[WM8994_NUM_DRC];
86 struct soc_enum drc_enum;
87
88 /* Platform dependant ReTune mobile configuration */
89 int num_retune_mobile_texts;
90 const char **retune_mobile_texts;
91 int retune_mobile_cfg[WM8994_NUM_EQ];
92 struct soc_enum retune_mobile_enum;
93
88766984
MB		 94 struct wm8994_micdet micdet[2];
95
b6b05691 96 int revision;
9e6e96a1
MB		 97 struct wm8994_pdata *pdata;
98};
99
9e6e96a1
MB		 100static int wm8994_readable(unsigned int reg)
101{
e88ff1e6
MB		 102 switch (reg) {
103 case WM8994_GPIO_1:
104 case WM8994_GPIO_2:
105 case WM8994_GPIO_3:
106 case WM8994_GPIO_4:
107 case WM8994_GPIO_5:
108 case WM8994_GPIO_6:
109 case WM8994_GPIO_7:
110 case WM8994_GPIO_8:
111 case WM8994_GPIO_9:
112 case WM8994_GPIO_10:
113 case WM8994_GPIO_11:
114 case WM8994_INTERRUPT_STATUS_1:
115 case WM8994_INTERRUPT_STATUS_2:
116 case WM8994_INTERRUPT_RAW_STATUS_2:
117 return 1;
118 default:
119 break;
120 }
121
7b306dae 122 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 123 return 0;
7b306dae 124 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 125}
126
127static int wm8994_volatile(unsigned int reg)
128{
129 if (reg >= WM8994_REG_CACHE_SIZE)
130 return 1;
131
132 switch (reg) {
133 case WM8994_SOFTWARE_RESET:
134 case WM8994_CHIP_REVISION:
135 case WM8994_DC_SERVO_1:
136 case WM8994_DC_SERVO_READBACK:
137 case WM8994_RATE_STATUS:
138 case WM8994_LDO_1:
139 case WM8994_LDO_2:
140 return 1;
141 default:
142 return 0;
143 }
144}
145
146static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
147 unsigned int value)
148{
b2c812e2 149 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 150
151 BUG_ON(reg > WM8994_MAX_REGISTER);
152
153 if (!wm8994_volatile(reg))
154 wm8994->reg_cache[reg] = value;
155
156 return wm8994_reg_write(codec->control_data, reg, value);
157}
158
159static unsigned int wm8994_read(struct snd_soc_codec *codec,
160 unsigned int reg)
161{
162 u16 *reg_cache = codec->reg_cache;
163
164 BUG_ON(reg > WM8994_MAX_REGISTER);
165
166 if (wm8994_volatile(reg))
167 return wm8994_reg_read(codec->control_data, reg);
168 else
169 return reg_cache[reg];
170}
171
172static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
173{
b2c812e2 174 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 175 int rate;
176 int reg1 = 0;
177 int offset;
178
179 if (aif)
180 offset = 4;
181 else
182 offset = 0;
183
184 switch (wm8994->sysclk[aif]) {
185 case WM8994_SYSCLK_MCLK1:
186 rate = wm8994->mclk[0];
187 break;
188
189 case WM8994_SYSCLK_MCLK2:
190 reg1 |= 0x8;
191 rate = wm8994->mclk[1];
192 break;
193
194 case WM8994_SYSCLK_FLL1:
195 reg1 |= 0x10;
196 rate = wm8994->fll[0].out;
197 break;
198
199 case WM8994_SYSCLK_FLL2:
200 reg1 |= 0x18;
201 rate = wm8994->fll[1].out;
202 break;
203
204 default:
205 return -EINVAL;
206 }
207
208 if (rate >= 13500000) {
209 rate /= 2;
210 reg1 |= WM8994_AIF1CLK_DIV;
211
212 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
213 aif + 1, rate);
214 }
5e5e2bef
MB		 215
216 if (rate && rate < 3000000)
217 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
218 aif + 1, rate);
219
9e6e96a1
MB		 220 wm8994->aifclk[aif] = rate;
221
222 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
223 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
224 reg1);
225
226 return 0;
227}
228
229static int configure_clock(struct snd_soc_codec *codec)
230{
b2c812e2 231 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 232 int old, new;
233
234 /* Bring up the AIF clocks first */
235 configure_aif_clock(codec, 0);
236 configure_aif_clock(codec, 1);
237
238 /* Then switch CLK_SYS over to the higher of them; a change
239 * can only happen as a result of a clocking change which can
240 * only be made outside of DAPM so we can safely redo the
241 * clocking.
242 */
243
244 /* If they're equal it doesn't matter which is used */
245 if (wm8994->aifclk[0] == wm8994->aifclk[1])
246 return 0;
247
248 if (wm8994->aifclk[0] < wm8994->aifclk[1])
249 new = WM8994_SYSCLK_SRC;
250 else
251 new = 0;
252
253 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
254
255 /* If there's no change then we're done. */
256 if (old == new)
257 return 0;
258
259 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
260
ce6120cc 261 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 262
263 return 0;
264}
265
266static int check_clk_sys(struct snd_soc_dapm_widget *source,
267 struct snd_soc_dapm_widget *sink)
268{
269 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
270 const char *clk;
271
272 /* Check what we're currently using for CLK_SYS */
273 if (reg & WM8994_SYSCLK_SRC)
274 clk = "AIF2CLK";
275 else
276 clk = "AIF1CLK";
277
278 return strcmp(source->name, clk) == 0;
279}
280
281static const char *sidetone_hpf_text[] = {
282 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
283};
284
285static const struct soc_enum sidetone_hpf =
286 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
287
288static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
289static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
290static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
291static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
292static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
293
294#define WM8994_DRC_SWITCH(xname, reg, shift) \
295{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
296 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
297 .put = wm8994_put_drc_sw, \
298 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
299
300static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
301 struct snd_ctl_elem_value *ucontrol)
302{
303 struct soc_mixer_control *mc =
304 (struct soc_mixer_control *)kcontrol->private_value;
305 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
306 int mask, ret;
307
308 /* Can't enable both ADC and DAC paths simultaneously */
309 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
310 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
311 WM8994_AIF1ADC1R_DRC_ENA_MASK;
312 else
313 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
314
315 ret = snd_soc_read(codec, mc->reg);
316 if (ret < 0)
317 return ret;
318 if (ret & mask)
319 return -EINVAL;
320
321 return snd_soc_put_volsw(kcontrol, ucontrol);
322}
323
9e6e96a1
MB		 324static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
325{
b2c812e2 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int base = wm8994_drc_base[drc];
329 int cfg = wm8994->drc_cfg[drc];
330 int save, i;
331
332 /* Save any enables; the configuration should clear them. */
333 save = snd_soc_read(codec, base);
334 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
335 WM8994_AIF1ADC1R_DRC_ENA;
336
337 for (i = 0; i < WM8994_DRC_REGS; i++)
338 snd_soc_update_bits(codec, base + i, 0xffff,
339 pdata->drc_cfgs[cfg].regs[i]);
340
341 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
342 WM8994_AIF1ADC1L_DRC_ENA |
343 WM8994_AIF1ADC1R_DRC_ENA, save);
344}
345
346/* Icky as hell but saves code duplication */
347static int wm8994_get_drc(const char *name)
348{
349 if (strcmp(name, "AIF1DRC1 Mode") == 0)
350 return 0;
351 if (strcmp(name, "AIF1DRC2 Mode") == 0)
352 return 1;
353 if (strcmp(name, "AIF2DRC Mode") == 0)
354 return 2;
355 return -EINVAL;
356}
357
358static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
359 struct snd_ctl_elem_value *ucontrol)
360{
361 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 362 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 363 struct wm8994_pdata *pdata = wm8994->pdata;
364 int drc = wm8994_get_drc(kcontrol->id.name);
365 int value = ucontrol->value.integer.value[0];
366
367 if (drc < 0)
368 return drc;
369
370 if (value >= pdata->num_drc_cfgs)
371 return -EINVAL;
372
373 wm8994->drc_cfg[drc] = value;
374
375 wm8994_set_drc(codec, drc);
376
377 return 0;
378}
379
380static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
381 struct snd_ctl_elem_value *ucontrol)
382{
383 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 384 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 385 int drc = wm8994_get_drc(kcontrol->id.name);
386
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
b2c812e2 394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 395 struct wm8994_pdata *pdata = wm8994->pdata;
396 int base = wm8994_retune_mobile_base[block];
397 int iface, best, best_val, save, i, cfg;
398
399 if (!pdata || !wm8994->num_retune_mobile_texts)
400 return;
401
402 switch (block) {
403 case 0:
404 case 1:
405 iface = 0;
406 break;
407 case 2:
408 iface = 1;
409 break;
410 default:
411 return;
412 }
413
414 /* Find the version of the currently selected configuration
415 * with the nearest sample rate. */
416 cfg = wm8994->retune_mobile_cfg[block];
417 best = 0;
418 best_val = INT_MAX;
419 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
420 if (strcmp(pdata->retune_mobile_cfgs[i].name,
421 wm8994->retune_mobile_texts[cfg]) == 0 &&
422 abs(pdata->retune_mobile_cfgs[i].rate
423 - wm8994->dac_rates[iface]) < best_val) {
424 best = i;
425 best_val = abs(pdata->retune_mobile_cfgs[i].rate
426 - wm8994->dac_rates[iface]);
427 }
428 }
429
430 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
431 block,
432 pdata->retune_mobile_cfgs[best].name,
433 pdata->retune_mobile_cfgs[best].rate,
434 wm8994->dac_rates[iface]);
435
436 /* The EQ will be disabled while reconfiguring it, remember the
437 * current configuration.
438 */
439 save = snd_soc_read(codec, base);
440 save &= WM8994_AIF1DAC1_EQ_ENA;
441
442 for (i = 0; i < WM8994_EQ_REGS; i++)
443 snd_soc_update_bits(codec, base + i, 0xffff,
444 pdata->retune_mobile_cfgs[best].regs[i]);
445
446 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
447}
448
449/* Icky as hell but saves code duplication */
450static int wm8994_get_retune_mobile_block(const char *name)
451{
452 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
453 return 0;
454 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
455 return 1;
456 if (strcmp(name, "AIF2 EQ Mode") == 0)
457 return 2;
458 return -EINVAL;
459}
460
461static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
462 struct snd_ctl_elem_value *ucontrol)
463{
464 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 465 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 466 struct wm8994_pdata *pdata = wm8994->pdata;
467 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
468 int value = ucontrol->value.integer.value[0];
469
470 if (block < 0)
471 return block;
472
473 if (value >= pdata->num_retune_mobile_cfgs)
474 return -EINVAL;
475
476 wm8994->retune_mobile_cfg[block] = value;
477
478 wm8994_set_retune_mobile(codec, block);
479
480 return 0;
481}
482
483static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
484 struct snd_ctl_elem_value *ucontrol)
485{
486 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 487 struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 488 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
489
490 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
491
492 return 0;
493}
494
96b101ef 495static const char *aif_chan_src_text[] = {
f554885f
MB		 496 "Left", "Right"
497};
498
96b101ef
MB		 499static const struct soc_enum aif1adcl_src =
500 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
501
502static const struct soc_enum aif1adcr_src =
503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
504
505static const struct soc_enum aif2adcl_src =
506 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
507
508static const struct soc_enum aif2adcr_src =
509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
510
f554885f 511static const struct soc_enum aif1dacl_src =
96b101ef 512 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 513
514static const struct soc_enum aif1dacr_src =
96b101ef 515 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 516
517static const struct soc_enum aif2dacl_src =
96b101ef 518 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 519
520static const struct soc_enum aif2dacr_src =
96b101ef 521 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 522
9e6e96a1
MB		 523static const struct snd_kcontrol_new wm8994_snd_controls[] = {
524SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
525 WM8994_AIF1_ADC1_RIGHT_VOLUME,
526 1, 119, 0, digital_tlv),
527SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
528 WM8994_AIF1_ADC2_RIGHT_VOLUME,
529 1, 119, 0, digital_tlv),
530SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
531 WM8994_AIF2_ADC_RIGHT_VOLUME,
532 1, 119, 0, digital_tlv),
533
96b101ef
MB		 534SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
535SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
536SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
537SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
538
f554885f
MB		 539SOC_ENUM("AIF1DACL Source", aif1dacl_src),
540SOC_ENUM("AIF1DACR Source", aif1dacr_src),
541SOC_ENUM("AIF2DACL Source", aif1dacl_src),
542SOC_ENUM("AIF2DACR Source", aif1dacr_src),
543
9e6e96a1
MB		 544SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
545 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
546SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
547 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
548SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
549 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
550
551SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
552SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
553
554SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
555SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
556SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
557
558WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
559WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
560WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
561
562WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
563WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
564WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
565
566WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
567WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
568WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
569
570SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
571 5, 12, 0, st_tlv),
572SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
573 0, 12, 0, st_tlv),
574SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
575 5, 12, 0, st_tlv),
576SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
577 0, 12, 0, st_tlv),
578SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
579SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
580
581SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
582 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
583SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
584 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
585
586SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
587 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
588SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
589 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
590
591SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
592 6, 1, 1, wm_hubs_spkmix_tlv),
593SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
594 2, 1, 1, wm_hubs_spkmix_tlv),
595
596SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
597 6, 1, 1, wm_hubs_spkmix_tlv),
598SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
599 2, 1, 1, wm_hubs_spkmix_tlv),
600
601SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
602 10, 15, 0, wm8994_3d_tlv),
603SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
604 8, 1, 0),
605SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
606 10, 15, 0, wm8994_3d_tlv),
607SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
608 8, 1, 0),
609SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
610 10, 15, 0, wm8994_3d_tlv),
611SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
612 8, 1, 0),
613};
614
615static const struct snd_kcontrol_new wm8994_eq_controls[] = {
616SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
617 eq_tlv),
618SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
619 eq_tlv),
620SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
621 eq_tlv),
622SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
623 eq_tlv),
624SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
625 eq_tlv),
626
627SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
628 eq_tlv),
629SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
630 eq_tlv),
631SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
632 eq_tlv),
633SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
634 eq_tlv),
635SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
636 eq_tlv),
637
638SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
639 eq_tlv),
640SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
647 eq_tlv),
648};
649
c4431df0
MB		 650static const struct snd_kcontrol_new wm8958_snd_controls[] = {
651SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
652};
653
9e6e96a1
MB		 654static int clk_sys_event(struct snd_soc_dapm_widget *w,
655 struct snd_kcontrol *kcontrol, int event)
656{
657 struct snd_soc_codec *codec = w->codec;
658
659 switch (event) {
660 case SND_SOC_DAPM_PRE_PMU:
661 return configure_clock(codec);
662
663 case SND_SOC_DAPM_POST_PMD:
664 configure_clock(codec);
665 break;
666 }
667
668 return 0;
669}
670
671static void wm8994_update_class_w(struct snd_soc_codec *codec)
672{
fec6dd83 673 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 674 int enable = 1;
675 int source = 0; /* GCC flow analysis can't track enable */
676 int reg, reg_r;
677
678 /* Only support direct DAC->headphone paths */
679 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
680 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 681 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 682 enable = 0;
683 }
684
685 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
686 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 687 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 688 enable = 0;
689 }
690
691 /* We also need the same setting for L/R and only one path */
692 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
693 switch (reg) {
694 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 695 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 696 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
697 break;
698 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 699 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 700 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
701 break;
702 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 703 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 704 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
705 break;
706 default:
ee839a21 707 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 708 enable = 0;
709 break;
710 }
711
712 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
713 if (reg_r != reg) {
ee839a21 714 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 715 enable = 0;
716 }
717
718 if (enable) {
719 dev_dbg(codec->dev, "Class W enabled\n");
720 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
721 WM8994_CP_DYN_PWR |
722 WM8994_CP_DYN_SRC_SEL_MASK,
723 source | WM8994_CP_DYN_PWR);
fec6dd83 724 wm8994->hubs.class_w = true;
9e6e96a1
MB		 725
726 } else {
727 dev_dbg(codec->dev, "Class W disabled\n");
728 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
729 WM8994_CP_DYN_PWR, 0);
fec6dd83 730 wm8994->hubs.class_w = false;
9e6e96a1
MB		 731 }
732}
733
734static const char *hp_mux_text[] = {
735 "Mixer",
736 "DAC",
737};
738
739#define WM8994_HP_ENUM(xname, xenum) \
740{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
741 .info = snd_soc_info_enum_double, \
742 .get = snd_soc_dapm_get_enum_double, \
743 .put = wm8994_put_hp_enum, \
744 .private_value = (unsigned long)&xenum }
745
746static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
747 struct snd_ctl_elem_value *ucontrol)
748{
749 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
750 struct snd_soc_codec *codec = w->codec;
751 int ret;
752
753 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
754
755 wm8994_update_class_w(codec);
756
757 return ret;
758}
759
760static const struct soc_enum hpl_enum =
761 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
762
763static const struct snd_kcontrol_new hpl_mux =
764 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
765
766static const struct soc_enum hpr_enum =
767 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
768
769static const struct snd_kcontrol_new hpr_mux =
770 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
771
772static const char *adc_mux_text[] = {
773 "ADC",
774 "DMIC",
775};
776
777static const struct soc_enum adc_enum =
778 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
779
780static const struct snd_kcontrol_new adcl_mux =
781 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
782
783static const struct snd_kcontrol_new adcr_mux =
784 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
785
786static const struct snd_kcontrol_new left_speaker_mixer[] = {
787SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
788SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
789SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
790SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
791SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
792};
793
794static const struct snd_kcontrol_new right_speaker_mixer[] = {
795SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
796SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
797SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
798SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
799SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
800};
801
802/* Debugging; dump chip status after DAPM transitions */
803static int post_ev(struct snd_soc_dapm_widget *w,
804 struct snd_kcontrol *kcontrol, int event)
805{
806 struct snd_soc_codec *codec = w->codec;
807 dev_dbg(codec->dev, "SRC status: %x\n",
808 snd_soc_read(codec,
809 WM8994_RATE_STATUS));
810 return 0;
811}
812
813static const struct snd_kcontrol_new aif1adc1l_mix[] = {
814SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
815 1, 1, 0),
816SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
817 0, 1, 0),
818};
819
820static const struct snd_kcontrol_new aif1adc1r_mix[] = {
821SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
822 1, 1, 0),
823SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
824 0, 1, 0),
825};
826
a3257ba8
MB		 827static const struct snd_kcontrol_new aif1adc2l_mix[] = {
828SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
829 1, 1, 0),
830SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
831 0, 1, 0),
832};
833
834static const struct snd_kcontrol_new aif1adc2r_mix[] = {
835SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
836 1, 1, 0),
837SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
838 0, 1, 0),
839};
840
9e6e96a1
MB		 841static const struct snd_kcontrol_new aif2dac2l_mix[] = {
842SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
843 5, 1, 0),
844SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
845 4, 1, 0),
846SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
847 2, 1, 0),
848SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
849 1, 1, 0),
850SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
851 0, 1, 0),
852};
853
854static const struct snd_kcontrol_new aif2dac2r_mix[] = {
855SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
856 5, 1, 0),
857SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
858 4, 1, 0),
859SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
860 2, 1, 0),
861SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
862 1, 1, 0),
863SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
864 0, 1, 0),
865};
866
867#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
868{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
869 .info = snd_soc_info_volsw, \
870 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
871 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
872
873static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
875{
876 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
877 struct snd_soc_codec *codec = w->codec;
878 int ret;
879
880 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
881
882 wm8994_update_class_w(codec);
883
884 return ret;
885}
886
887static const struct snd_kcontrol_new dac1l_mix[] = {
888WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
889 5, 1, 0),
890WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
891 4, 1, 0),
892WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
893 2, 1, 0),
894WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
895 1, 1, 0),
896WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
897 0, 1, 0),
898};
899
900static const struct snd_kcontrol_new dac1r_mix[] = {
901WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
902 5, 1, 0),
903WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
904 4, 1, 0),
905WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
906 2, 1, 0),
907WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
908 1, 1, 0),
909WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
910 0, 1, 0),
911};
912
913static const char *sidetone_text[] = {
914 "ADC/DMIC1", "DMIC2",
915};
916
917static const struct soc_enum sidetone1_enum =
918 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
919
920static const struct snd_kcontrol_new sidetone1_mux =
921 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
922
923static const struct soc_enum sidetone2_enum =
924 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
925
926static const struct snd_kcontrol_new sidetone2_mux =
927 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
928
929static const char *aif1dac_text[] = {
930 "AIF1DACDAT", "AIF3DACDAT",
931};
932
933static const struct soc_enum aif1dac_enum =
934 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
935
936static const struct snd_kcontrol_new aif1dac_mux =
937 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
938
939static const char *aif2dac_text[] = {
940 "AIF2DACDAT", "AIF3DACDAT",
941};
942
943static const struct soc_enum aif2dac_enum =
944 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
945
946static const struct snd_kcontrol_new aif2dac_mux =
947 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
948
949static const char *aif2adc_text[] = {
950 "AIF2ADCDAT", "AIF3DACDAT",
951};
952
953static const struct soc_enum aif2adc_enum =
954 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
955
956static const struct snd_kcontrol_new aif2adc_mux =
957 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
958
959static const char *aif3adc_text[] = {
c4431df0 960 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 961};
962
c4431df0 963static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 964 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
965
c4431df0
MB		 966static const struct snd_kcontrol_new wm8994_aif3adc_mux =
967 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
968
969static const struct soc_enum wm8958_aif3adc_enum =
970 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
971
972static const struct snd_kcontrol_new wm8958_aif3adc_mux =
973 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
974
975static const char *mono_pcm_out_text[] = {
976 "None", "AIF2ADCL", "AIF2ADCR",
977};
978
979static const struct soc_enum mono_pcm_out_enum =
980 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
981
982static const struct snd_kcontrol_new mono_pcm_out_mux =
983 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
984
985static const char *aif2dac_src_text[] = {
986 "AIF2", "AIF3",
987};
988
989/* Note that these two control shouldn't be simultaneously switched to AIF3 */
990static const struct soc_enum aif2dacl_src_enum =
991 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
992
993static const struct snd_kcontrol_new aif2dacl_src_mux =
994 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
995
996static const struct soc_enum aif2dacr_src_enum =
997 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
998
999static const struct snd_kcontrol_new aif2dacr_src_mux =
1000 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1
MB		 1001
1002static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1003SND_SOC_DAPM_INPUT("DMIC1DAT"),
1004SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1005SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1
MB		 1006
1007SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1008 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1009
1010SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1011SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1012SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1013
1014SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1015SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1016
1017SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
1018 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1019SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
1020 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1021SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0,
1022 WM8994_POWER_MANAGEMENT_5, 9, 0),
1023SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0,
1024 WM8994_POWER_MANAGEMENT_5, 8, 0),
1025
1026SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
1027 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1028SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
1029 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1030SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0,
1031 WM8994_POWER_MANAGEMENT_5, 11, 0),
1032SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0,
1033 WM8994_POWER_MANAGEMENT_5, 10, 0),
1034
1035SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1036 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1037SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1038 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1039
a3257ba8
MB		 1040SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1041 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1042SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1043 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1044
9e6e96a1
MB		 1045SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1046 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1047SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1048 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1049
1050SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1051SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1052
1053SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1054 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1055SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1056 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1057
1058SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1059 WM8994_POWER_MANAGEMENT_4, 13, 0),
1060SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1061 WM8994_POWER_MANAGEMENT_4, 12, 0),
1062SND_SOC_DAPM_AIF_IN("AIF2DACL", NULL, 0,
1063 WM8994_POWER_MANAGEMENT_5, 13, 0),
1064SND_SOC_DAPM_AIF_IN("AIF2DACR", NULL, 0,
1065 WM8994_POWER_MANAGEMENT_5, 12, 0),
1066
1067SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1068SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1069SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1070
1071SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1072SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1073SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1074
1075SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1076SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1077
1078SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1079
1080SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1081SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1082SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1083SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1084
1085/* Power is done with the muxes since the ADC power also controls the
1086 * downsampling chain, the chip will automatically manage the analogue
1087 * specific portions.
1088 */
1089SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1090SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1091
1092SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1093SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1094
1095SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1096SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1097SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1098SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1099
1100SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1101SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1102
1103SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1104 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1105SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1106 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1107
1108SND_SOC_DAPM_POST("Debug log", post_ev),
1109};
1110
c4431df0
MB		 1111static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1112SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1113};
9e6e96a1 1114
c4431df0
MB		 1115static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1116SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1117SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1118SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1119SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1120};
1121
1122static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1123 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1124 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1125
1126 { "DSP1CLK", NULL, "CLK_SYS" },
1127 { "DSP2CLK", NULL, "CLK_SYS" },
1128 { "DSPINTCLK", NULL, "CLK_SYS" },
1129
1130 { "AIF1ADC1L", NULL, "AIF1CLK" },
1131 { "AIF1ADC1L", NULL, "DSP1CLK" },
1132 { "AIF1ADC1R", NULL, "AIF1CLK" },
1133 { "AIF1ADC1R", NULL, "DSP1CLK" },
1134 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1135
1136 { "AIF1DAC1L", NULL, "AIF1CLK" },
1137 { "AIF1DAC1L", NULL, "DSP1CLK" },
1138 { "AIF1DAC1R", NULL, "AIF1CLK" },
1139 { "AIF1DAC1R", NULL, "DSP1CLK" },
1140 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1141
1142 { "AIF1ADC2L", NULL, "AIF1CLK" },
1143 { "AIF1ADC2L", NULL, "DSP1CLK" },
1144 { "AIF1ADC2R", NULL, "AIF1CLK" },
1145 { "AIF1ADC2R", NULL, "DSP1CLK" },
1146 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1147
1148 { "AIF1DAC2L", NULL, "AIF1CLK" },
1149 { "AIF1DAC2L", NULL, "DSP1CLK" },
1150 { "AIF1DAC2R", NULL, "AIF1CLK" },
1151 { "AIF1DAC2R", NULL, "DSP1CLK" },
1152 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1153
1154 { "AIF2ADCL", NULL, "AIF2CLK" },
1155 { "AIF2ADCL", NULL, "DSP2CLK" },
1156 { "AIF2ADCR", NULL, "AIF2CLK" },
1157 { "AIF2ADCR", NULL, "DSP2CLK" },
1158 { "AIF2ADCR", NULL, "DSPINTCLK" },
1159
1160 { "AIF2DACL", NULL, "AIF2CLK" },
1161 { "AIF2DACL", NULL, "DSP2CLK" },
1162 { "AIF2DACR", NULL, "AIF2CLK" },
1163 { "AIF2DACR", NULL, "DSP2CLK" },
1164 { "AIF2DACR", NULL, "DSPINTCLK" },
1165
1166 { "DMIC1L", NULL, "DMIC1DAT" },
1167 { "DMIC1L", NULL, "CLK_SYS" },
1168 { "DMIC1R", NULL, "DMIC1DAT" },
1169 { "DMIC1R", NULL, "CLK_SYS" },
1170 { "DMIC2L", NULL, "DMIC2DAT" },
1171 { "DMIC2L", NULL, "CLK_SYS" },
1172 { "DMIC2R", NULL, "DMIC2DAT" },
1173 { "DMIC2R", NULL, "CLK_SYS" },
1174
1175 { "ADCL", NULL, "AIF1CLK" },
1176 { "ADCL", NULL, "DSP1CLK" },
1177 { "ADCL", NULL, "DSPINTCLK" },
1178
1179 { "ADCR", NULL, "AIF1CLK" },
1180 { "ADCR", NULL, "DSP1CLK" },
1181 { "ADCR", NULL, "DSPINTCLK" },
1182
1183 { "ADCL Mux", "ADC", "ADCL" },
1184 { "ADCL Mux", "DMIC", "DMIC1L" },
1185 { "ADCR Mux", "ADC", "ADCR" },
1186 { "ADCR Mux", "DMIC", "DMIC1R" },
1187
1188 { "DAC1L", NULL, "AIF1CLK" },
1189 { "DAC1L", NULL, "DSP1CLK" },
1190 { "DAC1L", NULL, "DSPINTCLK" },
1191
1192 { "DAC1R", NULL, "AIF1CLK" },
1193 { "DAC1R", NULL, "DSP1CLK" },
1194 { "DAC1R", NULL, "DSPINTCLK" },
1195
1196 { "DAC2L", NULL, "AIF2CLK" },
1197 { "DAC2L", NULL, "DSP2CLK" },
1198 { "DAC2L", NULL, "DSPINTCLK" },
1199
1200 { "DAC2R", NULL, "AIF2DACR" },
1201 { "DAC2R", NULL, "AIF2CLK" },
1202 { "DAC2R", NULL, "DSP2CLK" },
1203 { "DAC2R", NULL, "DSPINTCLK" },
1204
1205 { "TOCLK", NULL, "CLK_SYS" },
1206
1207 /* AIF1 outputs */
1208 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1209 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1210 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1211
1212 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1213 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1214 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1215
a3257ba8
MB		 1216 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1217 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1218 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1219
1220 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1221 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1222 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1223
9e6e96a1
MB		 1224 /* Pin level routing for AIF3 */
1225 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1226 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1227 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1228 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1229
9e6e96a1
MB		 1230 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1231 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1232 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1233 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1234 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1235 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1236 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1237
1238 /* DAC1 inputs */
1239 { "DAC1L", NULL, "DAC1L Mixer" },
1240 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1241 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1242 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1243 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1244 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1245
1246 { "DAC1R", NULL, "DAC1R Mixer" },
1247 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1248 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1249 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1250 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1251 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1252
1253 /* DAC2/AIF2 outputs */
1254 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1255 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1256 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1257 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1258 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1259 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1260 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1261
1262 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1263 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1264 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1265 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1266 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1267 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1268 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1269
1270 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1271
1272 /* AIF3 output */
1273 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1274 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1275 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1276 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1277 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1278 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1279 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1280 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1281
1282 /* Sidetone */
1283 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1284 { "Left Sidetone", "DMIC2", "DMIC2L" },
1285 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1286 { "Right Sidetone", "DMIC2", "DMIC2R" },
1287
1288 /* Output stages */
1289 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1290 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1291
1292 { "SPKL", "DAC1 Switch", "DAC1L" },
1293 { "SPKL", "DAC2 Switch", "DAC2L" },
1294
1295 { "SPKR", "DAC1 Switch", "DAC1R" },
1296 { "SPKR", "DAC2 Switch", "DAC2R" },
1297
1298 { "Left Headphone Mux", "DAC", "DAC1L" },
1299 { "Right Headphone Mux", "DAC", "DAC1R" },
1300};
1301
c4431df0
MB		 1302static const struct snd_soc_dapm_route wm8994_intercon[] = {
1303 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1304 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1305};
1306
1307static const struct snd_soc_dapm_route wm8958_intercon[] = {
1308 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1309 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1310
1311 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1312 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1313 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1314 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1315
1316 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1317 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1318
1319 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1320};
1321
9e6e96a1
MB		 1322/* The size in bits of the FLL divide multiplied by 10
1323 * to allow rounding later */
1324#define FIXED_FLL_SIZE ((1 << 16) * 10)
1325
1326struct fll_div {
1327 u16 outdiv;
1328 u16 n;
1329 u16 k;
1330 u16 clk_ref_div;
1331 u16 fll_fratio;
1332};
1333
1334static int wm8994_get_fll_config(struct fll_div *fll,
1335 int freq_in, int freq_out)
1336{
1337 u64 Kpart;
1338 unsigned int K, Ndiv, Nmod;
1339
1340 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1341
1342 /* Scale the input frequency down to <= 13.5MHz */
1343 fll->clk_ref_div = 0;
1344 while (freq_in > 13500000) {
1345 fll->clk_ref_div++;
1346 freq_in /= 2;
1347
1348 if (fll->clk_ref_div > 3)
1349 return -EINVAL;
1350 }
1351 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1352
1353 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1354 fll->outdiv = 3;
1355 while (freq_out * (fll->outdiv + 1) < 90000000) {
1356 fll->outdiv++;
1357 if (fll->outdiv > 63)
1358 return -EINVAL;
1359 }
1360 freq_out *= fll->outdiv + 1;
1361 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1362
1363 if (freq_in > 1000000) {
1364 fll->fll_fratio = 0;
7d48a6ac
MB		 1365 } else if (freq_in > 256000) {
1366 fll->fll_fratio = 1;
1367 freq_in *= 2;
1368 } else if (freq_in > 128000) {
1369 fll->fll_fratio = 2;
1370 freq_in *= 4;
1371 } else if (freq_in > 64000) {
9e6e96a1
MB		 1372 fll->fll_fratio = 3;
1373 freq_in *= 8;
7d48a6ac
MB		 1374 } else {
1375 fll->fll_fratio = 4;
1376 freq_in *= 16;
9e6e96a1
MB		 1377 }
1378 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1379
1380 /* Now, calculate N.K */
1381 Ndiv = freq_out / freq_in;
1382
1383 fll->n = Ndiv;
1384 Nmod = freq_out % freq_in;
1385 pr_debug("Nmod=%d\n", Nmod);
1386
1387 /* Calculate fractional part - scale up so we can round. */
1388 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1389
1390 do_div(Kpart, freq_in);
1391
1392 K = Kpart & 0xFFFFFFFF;
1393
1394 if ((K % 10) >= 5)
1395 K += 5;
1396
1397 /* Move down to proper range now rounding is done */
1398 fll->k = K / 10;
1399
1400 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1401
1402 return 0;
1403}
1404
f0fba2ad 1405static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1406 unsigned int freq_in, unsigned int freq_out)
1407{
b2c812e2 1408 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1409 int reg_offset, ret;
1410 struct fll_div fll;
1411 u16 reg, aif1, aif2;
1412
1413 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1414 & WM8994_AIF1CLK_ENA;
1415
1416 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1417 & WM8994_AIF2CLK_ENA;
1418
1419 switch (id) {
1420 case WM8994_FLL1:
1421 reg_offset = 0;
1422 id = 0;
1423 break;
1424 case WM8994_FLL2:
1425 reg_offset = 0x20;
1426 id = 1;
1427 break;
1428 default:
1429 return -EINVAL;
1430 }
1431
136ff2a2 1432 switch (src) {
7add84aa
MB		 1433 case 0:
1434 /* Allow no source specification when stopping */
1435 if (freq_out)
1436 return -EINVAL;
1437 break;
136ff2a2
MB		 1438 case WM8994_FLL_SRC_MCLK1:
1439 case WM8994_FLL_SRC_MCLK2:
1440 case WM8994_FLL_SRC_LRCLK:
1441 case WM8994_FLL_SRC_BCLK:
1442 break;
1443 default:
1444 return -EINVAL;
1445 }
1446
9e6e96a1
MB		 1447 /* Are we changing anything? */
1448 if (wm8994->fll[id].src == src &&
1449 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1450 return 0;
1451
1452 /* If we're stopping the FLL redo the old config - no
1453 * registers will actually be written but we avoid GCC flow
1454 * analysis bugs spewing warnings.
1455 */
1456 if (freq_out)
1457 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1458 else
1459 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1460 wm8994->fll[id].out);
1461 if (ret < 0)
1462 return ret;
1463
1464 /* Gate the AIF clocks while we reclock */
1465 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1466 WM8994_AIF1CLK_ENA, 0);
1467 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1468 WM8994_AIF2CLK_ENA, 0);
1469
1470 /* We always need to disable the FLL while reconfiguring */
1471 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1472 WM8994_FLL1_ENA, 0);
1473
1474 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1475 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1476 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1477 WM8994_FLL1_OUTDIV_MASK |
1478 WM8994_FLL1_FRATIO_MASK, reg);
1479
1480 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1481
1482 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1483 WM8994_FLL1_N_MASK,
1484 fll.n << WM8994_FLL1_N_SHIFT);
1485
1486 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1487 WM8994_FLL1_REFCLK_DIV_MASK |
1488 WM8994_FLL1_REFCLK_SRC_MASK,
1489 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1490 (src - 1));
9e6e96a1
MB		 1491
1492 /* Enable (with fractional mode if required) */
1493 if (freq_out) {
1494 if (fll.k)
1495 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1496 else
1497 reg = WM8994_FLL1_ENA;
1498 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1499 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1500 reg);
1501 }
1502
1503 wm8994->fll[id].in = freq_in;
1504 wm8994->fll[id].out = freq_out;
136ff2a2 1505 wm8994->fll[id].src = src;
9e6e96a1
MB		 1506
1507 /* Enable any gated AIF clocks */
1508 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1509 WM8994_AIF1CLK_ENA, aif1);
1510 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1511 WM8994_AIF2CLK_ENA, aif2);
1512
1513 configure_clock(codec);
1514
1515 return 0;
1516}
1517
f0fba2ad 1518
66b47fdb
MB		 1519static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1520
f0fba2ad
LG		 1521static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1522 unsigned int freq_in, unsigned int freq_out)
1523{
1524 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1525}
1526
9e6e96a1
MB		 1527static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1528 int clk_id, unsigned int freq, int dir)
1529{
1530 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1531 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1532 int i;
9e6e96a1
MB		 1533
1534 switch (dai->id) {
1535 case 1:
1536 case 2:
1537 break;
1538
1539 default:
1540 /* AIF3 shares clocking with AIF1/2 */
1541 return -EINVAL;
1542 }
1543
1544 switch (clk_id) {
1545 case WM8994_SYSCLK_MCLK1:
1546 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1547 wm8994->mclk[0] = freq;
1548 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1549 dai->id, freq);
1550 break;
1551
1552 case WM8994_SYSCLK_MCLK2:
1553 /* TODO: Set GPIO AF */
1554 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1555 wm8994->mclk[1] = freq;
1556 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1557 dai->id, freq);
1558 break;
1559
1560 case WM8994_SYSCLK_FLL1:
1561 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1562 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1563 break;
1564
1565 case WM8994_SYSCLK_FLL2:
1566 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1567 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1568 break;
1569
66b47fdb
MB		 1570 case WM8994_SYSCLK_OPCLK:
1571 /* Special case - a division (times 10) is given and
1572 * no effect on main clocking.
1573 */
1574 if (freq) {
1575 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1576 if (opclk_divs[i] == freq)
1577 break;
1578 if (i == ARRAY_SIZE(opclk_divs))
1579 return -EINVAL;
1580 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1581 WM8994_OPCLK_DIV_MASK, i);
1582 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1583 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1584 } else {
1585 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1586 WM8994_OPCLK_ENA, 0);
1587 }
1588
9e6e96a1
MB		 1589 default:
1590 return -EINVAL;
1591 }
1592
1593 configure_clock(codec);
1594
1595 return 0;
1596}
1597
1598static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1599 enum snd_soc_bias_level level)
1600{
3a423157 1601 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1602 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1603
9e6e96a1
MB		 1604 switch (level) {
1605 case SND_SOC_BIAS_ON:
1606 break;
1607
1608 case SND_SOC_BIAS_PREPARE:
1609 /* VMID=2x40k */
1610 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1611 WM8994_VMID_SEL_MASK, 0x2);
1612 break;
1613
1614 case SND_SOC_BIAS_STANDBY:
ce6120cc 1615 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0c17b393
MB		 1616 /* Tweak DC servo and DSP configuration for
1617 * improved performance. */
3a423157 1618 if (control->type == WM8994 && wm8994->revision < 4) {
b6b05691
MB		 1619 /* Tweak DC servo and DSP configuration for
1620 * improved performance. */
1621 snd_soc_write(codec, 0x102, 0x3);
1622 snd_soc_write(codec, 0x56, 0x3);
1623 snd_soc_write(codec, 0x817, 0);
1624 snd_soc_write(codec, 0x102, 0);
1625 }
9e6e96a1
MB		 1626
1627 /* Discharge LINEOUT1 & 2 */
1628 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1629 WM8994_LINEOUT1_DISCH |
1630 WM8994_LINEOUT2_DISCH,
1631 WM8994_LINEOUT1_DISCH |
1632 WM8994_LINEOUT2_DISCH);
1633
1634 /* Startup bias, VMID ramp & buffer */
1635 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1636 WM8994_STARTUP_BIAS_ENA |
1637 WM8994_VMID_BUF_ENA |
1638 WM8994_VMID_RAMP_MASK,
1639 WM8994_STARTUP_BIAS_ENA |
1640 WM8994_VMID_BUF_ENA |
1641 (0x11 << WM8994_VMID_RAMP_SHIFT));
1642
1643 /* Main bias enable, VMID=2x40k */
1644 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1645 WM8994_BIAS_ENA |
1646 WM8994_VMID_SEL_MASK,
1647 WM8994_BIAS_ENA | 0x2);
1648
1649 msleep(20);
1650 }
1651
1652 /* VMID=2x500k */
1653 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1654 WM8994_VMID_SEL_MASK, 0x4);
1655
1656 break;
1657
1658 case SND_SOC_BIAS_OFF:
ce6120cc 1659 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1660 /* Switch over to startup biases */
1661 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1662 WM8994_BIAS_SRC |
1663 WM8994_STARTUP_BIAS_ENA |
1664 WM8994_VMID_BUF_ENA |
1665 WM8994_VMID_RAMP_MASK,
1666 WM8994_BIAS_SRC |
1667 WM8994_STARTUP_BIAS_ENA |
1668 WM8994_VMID_BUF_ENA |
1669 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1670
d522ffbf
MB		 1671 /* Disable main biases */
1672 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1673 WM8994_BIAS_ENA |
1674 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1675
d522ffbf
MB		 1676 /* Discharge line */
1677 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1678 WM8994_LINEOUT1_DISCH |
1679 WM8994_LINEOUT2_DISCH,
1680 WM8994_LINEOUT1_DISCH |
1681 WM8994_LINEOUT2_DISCH);
9e6e96a1 1682
d522ffbf 1683 msleep(5);
9e6e96a1 1684
d522ffbf
MB		 1685 /* Switch off startup biases */
1686 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1687 WM8994_BIAS_SRC |
1688 WM8994_STARTUP_BIAS_ENA |
1689 WM8994_VMID_BUF_ENA |
1690 WM8994_VMID_RAMP_MASK, 0);
1691 }
9e6e96a1
MB		 1692 break;
1693 }
ce6120cc 1694 codec->dapm.bias_level = level;
9e6e96a1
MB		 1695 return 0;
1696}
1697
1698static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1699{
1700 struct snd_soc_codec *codec = dai->codec;
c4431df0 1701 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 1702 int ms_reg;
1703 int aif1_reg;
1704 int ms = 0;
1705 int aif1 = 0;
1706
1707 switch (dai->id) {
1708 case 1:
1709 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1710 aif1_reg = WM8994_AIF1_CONTROL_1;
1711 break;
1712 case 2:
1713 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1714 aif1_reg = WM8994_AIF2_CONTROL_1;
1715 break;
1716 default:
1717 return -EINVAL;
1718 }
1719
1720 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1721 case SND_SOC_DAIFMT_CBS_CFS:
1722 break;
1723 case SND_SOC_DAIFMT_CBM_CFM:
1724 ms = WM8994_AIF1_MSTR;
1725 break;
1726 default:
1727 return -EINVAL;
1728 }
1729
1730 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1731 case SND_SOC_DAIFMT_DSP_B:
1732 aif1 |= WM8994_AIF1_LRCLK_INV;
1733 case SND_SOC_DAIFMT_DSP_A:
1734 aif1 |= 0x18;
1735 break;
1736 case SND_SOC_DAIFMT_I2S:
1737 aif1 |= 0x10;
1738 break;
1739 case SND_SOC_DAIFMT_RIGHT_J:
1740 break;
1741 case SND_SOC_DAIFMT_LEFT_J:
1742 aif1 |= 0x8;
1743 break;
1744 default:
1745 return -EINVAL;
1746 }
1747
1748 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1749 case SND_SOC_DAIFMT_DSP_A:
1750 case SND_SOC_DAIFMT_DSP_B:
1751 /* frame inversion not valid for DSP modes */
1752 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1753 case SND_SOC_DAIFMT_NB_NF:
1754 break;
1755 case SND_SOC_DAIFMT_IB_NF:
1756 aif1 |= WM8994_AIF1_BCLK_INV;
1757 break;
1758 default:
1759 return -EINVAL;
1760 }
1761 break;
1762
1763 case SND_SOC_DAIFMT_I2S:
1764 case SND_SOC_DAIFMT_RIGHT_J:
1765 case SND_SOC_DAIFMT_LEFT_J:
1766 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1767 case SND_SOC_DAIFMT_NB_NF:
1768 break;
1769 case SND_SOC_DAIFMT_IB_IF:
1770 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
1771 break;
1772 case SND_SOC_DAIFMT_IB_NF:
1773 aif1 |= WM8994_AIF1_BCLK_INV;
1774 break;
1775 case SND_SOC_DAIFMT_NB_IF:
1776 aif1 |= WM8994_AIF1_LRCLK_INV;
1777 break;
1778 default:
1779 return -EINVAL;
1780 }
1781 break;
1782 default:
1783 return -EINVAL;
1784 }
1785
c4431df0
MB		 1786 /* The AIF2 format configuration needs to be mirrored to AIF3
1787 * on WM8958 if it's in use so just do it all the time. */
1788 if (control->type == WM8958 && dai->id == 2)
1789 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
1790 WM8994_AIF1_LRCLK_INV |
1791 WM8958_AIF3_FMT_MASK, aif1);
1792
9e6e96a1
MB		 1793 snd_soc_update_bits(codec, aif1_reg,
1794 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
1795 WM8994_AIF1_FMT_MASK,
1796 aif1);
1797 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
1798 ms);
1799
1800 return 0;
1801}
1802
1803static struct {
1804 int val, rate;
1805} srs[] = {
1806 { 0, 8000 },
1807 { 1, 11025 },
1808 { 2, 12000 },
1809 { 3, 16000 },
1810 { 4, 22050 },
1811 { 5, 24000 },
1812 { 6, 32000 },
1813 { 7, 44100 },
1814 { 8, 48000 },
1815 { 9, 88200 },
1816 { 10, 96000 },
1817};
1818
1819static int fs_ratios[] = {
1820 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
1821};
1822
1823static int bclk_divs[] = {
1824 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
1825 640, 880, 960, 1280, 1760, 1920
1826};
1827
1828static int wm8994_hw_params(struct snd_pcm_substream *substream,
1829 struct snd_pcm_hw_params *params,
1830 struct snd_soc_dai *dai)
1831{
1832 struct snd_soc_codec *codec = dai->codec;
c4431df0 1833 struct wm8994 *control = codec->control_data;
b2c812e2 1834 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1835 int aif1_reg;
1836 int bclk_reg;
1837 int lrclk_reg;
1838 int rate_reg;
1839 int aif1 = 0;
1840 int bclk = 0;
1841 int lrclk = 0;
1842 int rate_val = 0;
1843 int id = dai->id - 1;
1844
1845 int i, cur_val, best_val, bclk_rate, best;
1846
1847 switch (dai->id) {
1848 case 1:
1849 aif1_reg = WM8994_AIF1_CONTROL_1;
1850 bclk_reg = WM8994_AIF1_BCLK;
1851 rate_reg = WM8994_AIF1_RATE;
1852 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 1853 wm8994->lrclk_shared[0]) {
9e6e96a1 1854 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 1855 } else {
9e6e96a1 1856 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 1857 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
1858 }
9e6e96a1
MB		 1859 break;
1860 case 2:
1861 aif1_reg = WM8994_AIF2_CONTROL_1;
1862 bclk_reg = WM8994_AIF2_BCLK;
1863 rate_reg = WM8994_AIF2_RATE;
1864 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 1865 wm8994->lrclk_shared[1]) {
9e6e96a1 1866 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 1867 } else {
9e6e96a1 1868 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 1869 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
1870 }
9e6e96a1 1871 break;
c4431df0
MB		 1872 case 3:
1873 switch (control->type) {
1874 case WM8958:
1875 aif1_reg = WM8958_AIF3_CONTROL_1;
1876 break;
1877 default:
1878 return 0;
1879 }
9e6e96a1
MB		 1880 default:
1881 return -EINVAL;
1882 }
1883
1884 bclk_rate = params_rate(params) * 2;
1885 switch (params_format(params)) {
1886 case SNDRV_PCM_FORMAT_S16_LE:
1887 bclk_rate *= 16;
1888 break;
1889 case SNDRV_PCM_FORMAT_S20_3LE:
1890 bclk_rate *= 20;
1891 aif1 |= 0x20;
1892 break;
1893 case SNDRV_PCM_FORMAT_S24_LE:
1894 bclk_rate *= 24;
1895 aif1 |= 0x40;
1896 break;
1897 case SNDRV_PCM_FORMAT_S32_LE:
1898 bclk_rate *= 32;
1899 aif1 |= 0x60;
1900 break;
1901 default:
1902 return -EINVAL;
1903 }
1904
1905 /* Try to find an appropriate sample rate; look for an exact match. */
1906 for (i = 0; i < ARRAY_SIZE(srs); i++)
1907 if (srs[i].rate == params_rate(params))
1908 break;
1909 if (i == ARRAY_SIZE(srs))
1910 return -EINVAL;
1911 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
1912
1913 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
1914 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
1915 dai->id, wm8994->aifclk[id], bclk_rate);
1916
1917 if (wm8994->aifclk[id] == 0) {
1918 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
1919 return -EINVAL;
1920 }
1921
1922 /* AIFCLK/fs ratio; look for a close match in either direction */
1923 best = 0;
1924 best_val = abs((fs_ratios[0] * params_rate(params))
1925 - wm8994->aifclk[id]);
1926 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
1927 cur_val = abs((fs_ratios[i] * params_rate(params))
1928 - wm8994->aifclk[id]);
1929 if (cur_val >= best_val)
1930 continue;
1931 best = i;
1932 best_val = cur_val;
1933 }
1934 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
1935 dai->id, fs_ratios[best]);
1936 rate_val |= best;
1937
1938 /* We may not get quite the right frequency if using
1939 * approximate clocks so look for the closest match that is
1940 * higher than the target (we need to ensure that there enough
1941 * BCLKs to clock out the samples).
1942 */
1943 best = 0;
1944 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 1945 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 1946 if (cur_val < 0) /* BCLK table is sorted */
1947 break;
1948 best = i;
1949 }
07cd8ada 1950 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 1951 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1952 bclk_divs[best], bclk_rate);
1953 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
1954
1955 lrclk = bclk_rate / params_rate(params);
1956 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1957 lrclk, bclk_rate / lrclk);
1958
1959 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
1960 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
1961 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
1962 lrclk);
1963 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
1964 WM8994_AIF1CLK_RATE_MASK, rate_val);
1965
1966 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1967 switch (dai->id) {
1968 case 1:
1969 wm8994->dac_rates[0] = params_rate(params);
1970 wm8994_set_retune_mobile(codec, 0);
1971 wm8994_set_retune_mobile(codec, 1);
1972 break;
1973 case 2:
1974 wm8994->dac_rates[1] = params_rate(params);
1975 wm8994_set_retune_mobile(codec, 2);
1976 break;
1977 }
1978 }
1979
1980 return 0;
1981}
1982
c4431df0
MB		 1983static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
1984 struct snd_pcm_hw_params *params,
1985 struct snd_soc_dai *dai)
1986{
1987 struct snd_soc_codec *codec = dai->codec;
1988 struct wm8994 *control = codec->control_data;
1989 int aif1_reg;
1990 int aif1 = 0;
1991
1992 switch (dai->id) {
1993 case 3:
1994 switch (control->type) {
1995 case WM8958:
1996 aif1_reg = WM8958_AIF3_CONTROL_1;
1997 break;
1998 default:
1999 return 0;
2000 }
2001 default:
2002 return 0;
2003 }
2004
2005 switch (params_format(params)) {
2006 case SNDRV_PCM_FORMAT_S16_LE:
2007 break;
2008 case SNDRV_PCM_FORMAT_S20_3LE:
2009 aif1 |= 0x20;
2010 break;
2011 case SNDRV_PCM_FORMAT_S24_LE:
2012 aif1 |= 0x40;
2013 break;
2014 case SNDRV_PCM_FORMAT_S32_LE:
2015 aif1 |= 0x60;
2016 break;
2017 default:
2018 return -EINVAL;
2019 }
2020
2021 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2022}
2023
9e6e96a1
MB		 2024static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2025{
2026 struct snd_soc_codec *codec = codec_dai->codec;
2027 int mute_reg;
2028 int reg;
2029
2030 switch (codec_dai->id) {
2031 case 1:
2032 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2033 break;
2034 case 2:
2035 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2036 break;
2037 default:
2038 return -EINVAL;
2039 }
2040
2041 if (mute)
2042 reg = WM8994_AIF1DAC1_MUTE;
2043 else
2044 reg = 0;
2045
2046 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2047
2048 return 0;
2049}
2050
778a76e2
MB		 2051static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2052{
2053 struct snd_soc_codec *codec = codec_dai->codec;
2054 int reg, val, mask;
2055
2056 switch (codec_dai->id) {
2057 case 1:
2058 reg = WM8994_AIF1_MASTER_SLAVE;
2059 mask = WM8994_AIF1_TRI;
2060 break;
2061 case 2:
2062 reg = WM8994_AIF2_MASTER_SLAVE;
2063 mask = WM8994_AIF2_TRI;
2064 break;
2065 case 3:
2066 reg = WM8994_POWER_MANAGEMENT_6;
2067 mask = WM8994_AIF3_TRI;
2068 break;
2069 default:
2070 return -EINVAL;
2071 }
2072
2073 if (tristate)
2074 val = mask;
2075 else
2076 val = 0;
2077
2078 return snd_soc_update_bits(codec, reg, mask, reg);
2079}
2080
9e6e96a1
MB		 2081#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2082
2083#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2084 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2085
2086static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2087 .set_sysclk = wm8994_set_dai_sysclk,
2088 .set_fmt = wm8994_set_dai_fmt,
2089 .hw_params = wm8994_hw_params,
2090 .digital_mute = wm8994_aif_mute,
2091 .set_pll = wm8994_set_fll,
778a76e2 2092 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2093};
2094
2095static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2096 .set_sysclk = wm8994_set_dai_sysclk,
2097 .set_fmt = wm8994_set_dai_fmt,
2098 .hw_params = wm8994_hw_params,
2099 .digital_mute = wm8994_aif_mute,
2100 .set_pll = wm8994_set_fll,
778a76e2
MB		 2101 .set_tristate = wm8994_set_tristate,
2102};
2103
2104static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2105 .hw_params = wm8994_aif3_hw_params,
778a76e2 2106 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2107};
2108
f0fba2ad 2109static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2110 {
f0fba2ad 2111 .name = "wm8994-aif1",
8c7f78b3 2112 .id = 1,
9e6e96a1
MB		 2113 .playback = {
2114 .stream_name = "AIF1 Playback",
2115 .channels_min = 2,
2116 .channels_max = 2,
2117 .rates = WM8994_RATES,
2118 .formats = WM8994_FORMATS,
2119 },
2120 .capture = {
2121 .stream_name = "AIF1 Capture",
2122 .channels_min = 2,
2123 .channels_max = 2,
2124 .rates = WM8994_RATES,
2125 .formats = WM8994_FORMATS,
2126 },
2127 .ops = &wm8994_aif1_dai_ops,
2128 },
2129 {
f0fba2ad 2130 .name = "wm8994-aif2",
8c7f78b3 2131 .id = 2,
9e6e96a1
MB		 2132 .playback = {
2133 .stream_name = "AIF2 Playback",
2134 .channels_min = 2,
2135 .channels_max = 2,
2136 .rates = WM8994_RATES,
2137 .formats = WM8994_FORMATS,
2138 },
2139 .capture = {
2140 .stream_name = "AIF2 Capture",
2141 .channels_min = 2,
2142 .channels_max = 2,
2143 .rates = WM8994_RATES,
2144 .formats = WM8994_FORMATS,
2145 },
2146 .ops = &wm8994_aif2_dai_ops,
2147 },
2148 {
f0fba2ad 2149 .name = "wm8994-aif3",
8c7f78b3 2150 .id = 3,
9e6e96a1
MB		 2151 .playback = {
2152 .stream_name = "AIF3 Playback",
2153 .channels_min = 2,
2154 .channels_max = 2,
2155 .rates = WM8994_RATES,
2156 .formats = WM8994_FORMATS,
2157 },
a8462bde 2158 .capture = {
9e6e96a1
MB		 2159 .stream_name = "AIF3 Capture",
2160 .channels_min = 2,
2161 .channels_max = 2,
2162 .rates = WM8994_RATES,
2163 .formats = WM8994_FORMATS,
2164 },
778a76e2 2165 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2166 }
2167};
9e6e96a1
MB		 2168
2169#ifdef CONFIG_PM
f0fba2ad 2170static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2171{
b2c812e2 2172 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2173 int i, ret;
2174
2175 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2176 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2177 sizeof(struct fll_config));
f0fba2ad 2178 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2179 if (ret < 0)
2180 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2181 i + 1, ret);
2182 }
2183
2184 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2185
2186 return 0;
2187}
2188
f0fba2ad 2189static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2190{
b2c812e2 2191 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 2192 u16 *reg_cache = codec->reg_cache;
2193 int i, ret;
2194
2195 /* Restore the registers */
2196 for (i = 1; i < ARRAY_SIZE(wm8994->reg_cache); i++) {
2197 switch (i) {
2198 case WM8994_LDO_1:
2199 case WM8994_LDO_2:
2200 case WM8994_SOFTWARE_RESET:
2201 /* Handled by other MFD drivers */
2202 continue;
2203 default:
2204 break;
2205 }
2206
7b306dae 2207 if (!wm8994_access_masks[i].writable)
9e6e96a1
MB		 2208 continue;
2209
2210 wm8994_reg_write(codec->control_data, i, reg_cache[i]);
2211 }
2212
2213 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2214
2215 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2216 if (!wm8994->fll_suspend[i].out)
2217 continue;
2218
f0fba2ad 2219 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2220 wm8994->fll_suspend[i].src,
2221 wm8994->fll_suspend[i].in,
2222 wm8994->fll_suspend[i].out);
2223 if (ret < 0)
2224 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2225 i + 1, ret);
2226 }
2227
2228 return 0;
2229}
2230#else
2231#define wm8994_suspend NULL
2232#define wm8994_resume NULL
2233#endif
2234
2235static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2236{
f0fba2ad 2237 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2238 struct wm8994_pdata *pdata = wm8994->pdata;
2239 struct snd_kcontrol_new controls[] = {
2240 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2241 wm8994->retune_mobile_enum,
2242 wm8994_get_retune_mobile_enum,
2243 wm8994_put_retune_mobile_enum),
2244 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2245 wm8994->retune_mobile_enum,
2246 wm8994_get_retune_mobile_enum,
2247 wm8994_put_retune_mobile_enum),
2248 SOC_ENUM_EXT("AIF2 EQ Mode",
2249 wm8994->retune_mobile_enum,
2250 wm8994_get_retune_mobile_enum,
2251 wm8994_put_retune_mobile_enum),
2252 };
2253 int ret, i, j;
2254 const char **t;
2255
2256 /* We need an array of texts for the enum API but the number
2257 * of texts is likely to be less than the number of
2258 * configurations due to the sample rate dependency of the
2259 * configurations. */
2260 wm8994->num_retune_mobile_texts = 0;
2261 wm8994->retune_mobile_texts = NULL;
2262 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2263 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2264 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2265 wm8994->retune_mobile_texts[j]) == 0)
2266 break;
2267 }
2268
2269 if (j != wm8994->num_retune_mobile_texts)
2270 continue;
2271
2272 /* Expand the array... */
2273 t = krealloc(wm8994->retune_mobile_texts,
2274 sizeof(char *) *
2275 (wm8994->num_retune_mobile_texts + 1),
2276 GFP_KERNEL);
2277 if (t == NULL)
2278 continue;
2279
2280 /* ...store the new entry... */
2281 t[wm8994->num_retune_mobile_texts] =
2282 pdata->retune_mobile_cfgs[i].name;
2283
2284 /* ...and remember the new version. */
2285 wm8994->num_retune_mobile_texts++;
2286 wm8994->retune_mobile_texts = t;
2287 }
2288
2289 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2290 wm8994->num_retune_mobile_texts);
2291
2292 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2293 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2294
f0fba2ad 2295 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2296 ARRAY_SIZE(controls));
2297 if (ret != 0)
f0fba2ad 2298 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2299 "Failed to add ReTune Mobile controls: %d\n", ret);
2300}
2301
2302static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2303{
f0fba2ad 2304 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2305 struct wm8994_pdata *pdata = wm8994->pdata;
2306 int ret, i;
2307
2308 if (!pdata)
2309 return;
2310
2311 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2312 pdata->lineout2_diff,
2313 pdata->lineout1fb,
2314 pdata->lineout2fb,
2315 pdata->jd_scthr,
2316 pdata->jd_thr,
2317 pdata->micbias1_lvl,
2318 pdata->micbias2_lvl);
2319
2320 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2321
2322 if (pdata->num_drc_cfgs) {
2323 struct snd_kcontrol_new controls[] = {
2324 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2325 wm8994_get_drc_enum, wm8994_put_drc_enum),
2326 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2327 wm8994_get_drc_enum, wm8994_put_drc_enum),
2328 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2329 wm8994_get_drc_enum, wm8994_put_drc_enum),
2330 };
2331
2332 /* We need an array of texts for the enum API */
2333 wm8994->drc_texts = kmalloc(sizeof(char *)
2334 * pdata->num_drc_cfgs, GFP_KERNEL);
2335 if (!wm8994->drc_texts) {
f0fba2ad 2336 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2337 "Failed to allocate %d DRC config texts\n",
2338 pdata->num_drc_cfgs);
2339 return;
2340 }
2341
2342 for (i = 0; i < pdata->num_drc_cfgs; i++)
2343 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2344
2345 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2346 wm8994->drc_enum.texts = wm8994->drc_texts;
2347
f0fba2ad 2348 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2349 ARRAY_SIZE(controls));
2350 if (ret != 0)
f0fba2ad 2351 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2352 "Failed to add DRC mode controls: %d\n", ret);
2353
2354 for (i = 0; i < WM8994_NUM_DRC; i++)
2355 wm8994_set_drc(codec, i);
2356 }
2357
2358 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2359 pdata->num_retune_mobile_cfgs);
2360
2361 if (pdata->num_retune_mobile_cfgs)
2362 wm8994_handle_retune_mobile_pdata(wm8994);
2363 else
f0fba2ad 2364 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1
MB		 2365 ARRAY_SIZE(wm8994_eq_controls));
2366}
2367
88766984
MB		 2368/**
2369 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2370 *
2371 * @codec: WM8994 codec
2372 * @jack: jack to report detection events on
2373 * @micbias: microphone bias to detect on
2374 * @det: value to report for presence detection
2375 * @shrt: value to report for short detection
2376 *
2377 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2378 * being used to bring out signals to the processor then only platform
5ab230a7 2379 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2380 * be configured using snd_soc_jack_add_gpios() instead.
2381 *
2382 * Configuration of detection levels is available via the micbias1_lvl
2383 * and micbias2_lvl platform data members.
2384 */
2385int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2386 int micbias, int det, int shrt)
2387{
b2c812e2 2388 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2389 struct wm8994_micdet *micdet;
3a423157 2390 struct wm8994 *control = codec->control_data;
88766984
MB		 2391 int reg;
2392
3a423157
MB		 2393 if (control->type != WM8994)
2394 return -EINVAL;
2395
88766984
MB		 2396 switch (micbias) {
2397 case 1:
2398 micdet = &wm8994->micdet[0];
2399 break;
2400 case 2:
2401 micdet = &wm8994->micdet[1];
2402 break;
2403 default:
2404 return -EINVAL;
2405 }
2406
2407 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2408 micbias, det, shrt);
2409
2410 /* Store the configuration */
2411 micdet->jack = jack;
2412 micdet->det = det;
2413 micdet->shrt = shrt;
2414
2415 /* If either of the jacks is set up then enable detection */
2416 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2417 reg = WM8994_MICD_ENA;
2418 else
2419 reg = 0;
2420
2421 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2422
2423 return 0;
2424}
2425EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2426
2427static irqreturn_t wm8994_mic_irq(int irq, void *data)
2428{
2429 struct wm8994_priv *priv = data;
f0fba2ad 2430 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2431 int reg;
2432 int report;
2433
2434 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2435 if (reg < 0) {
2436 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2437 reg);
2438 return IRQ_HANDLED;
2439 }
2440
2441 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2442
2443 report = 0;
2444 if (reg & WM8994_MIC1_DET_STS)
2445 report |= priv->micdet[0].det;
2446 if (reg & WM8994_MIC1_SHRT_STS)
2447 report |= priv->micdet[0].shrt;
2448 snd_soc_jack_report(priv->micdet[0].jack, report,
2449 priv->micdet[0].det | priv->micdet[0].shrt);
2450
2451 report = 0;
2452 if (reg & WM8994_MIC2_DET_STS)
2453 report |= priv->micdet[1].det;
2454 if (reg & WM8994_MIC2_SHRT_STS)
2455 report |= priv->micdet[1].shrt;
2456 snd_soc_jack_report(priv->micdet[1].jack, report,
2457 priv->micdet[1].det | priv->micdet[1].shrt);
2458
2459 return IRQ_HANDLED;
2460}
2461
f0fba2ad 2462static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2463{
3a423157 2464 struct wm8994 *control;
9e6e96a1 2465 struct wm8994_priv *wm8994;
ce6120cc 2466 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2467 int ret, i;
9e6e96a1 2468
f0fba2ad 2469 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2470 control = codec->control_data;
9e6e96a1
MB		 2471
2472 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2473 if (wm8994 == NULL)
9e6e96a1 2474 return -ENOMEM;
b2c812e2 2475 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad 2476
11e713a0
MB		 2477 codec->reg_cache = &wm8994->reg_cache;
2478
f0fba2ad
LG		 2479 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2480 wm8994->codec = codec;
9e6e96a1
MB		 2481
2482 /* Fill the cache with physical values we inherited; don't reset */
2483 ret = wm8994_bulk_read(codec->control_data, 0,
2484 ARRAY_SIZE(wm8994->reg_cache) - 1,
2485 codec->reg_cache);
2486 if (ret < 0) {
2487 dev_err(codec->dev, "Failed to fill register cache: %d\n",
2488 ret);
2489 goto err;
2490 }
2491
2492 /* Clear the cached values for unreadable/volatile registers to
2493 * avoid potential confusion.
2494 */
2495 for (i = 0; i < ARRAY_SIZE(wm8994->reg_cache); i++)
2496 if (wm8994_volatile(i) || !wm8994_readable(i))
2497 wm8994->reg_cache[i] = 0;
2498
2499 /* Set revision-specific configuration */
b6b05691 2500 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2501 switch (control->type) {
2502 case WM8994:
2503 switch (wm8994->revision) {
2504 case 2:
2505 case 3:
2506 wm8994->hubs.dcs_codes = -5;
2507 wm8994->hubs.hp_startup_mode = 1;
2508 wm8994->hubs.dcs_readback_mode = 1;
2509 break;
2510 default:
2511 wm8994->hubs.dcs_readback_mode = 1;
2512 break;
2513 }
2514
2515 case WM8958:
8437f700 2516 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2517 break;
3a423157 2518
9e6e96a1
MB		 2519 default:
2520 break;
2521 }
9e6e96a1 2522
3a423157
MB		 2523 switch (control->type) {
2524 case WM8994:
2525 ret = wm8994_request_irq(codec->control_data,
2526 WM8994_IRQ_MIC1_DET,
2527 wm8994_mic_irq, "Mic 1 detect",
2528 wm8994);
2529 if (ret != 0)
2530 dev_warn(codec->dev,
2531 "Failed to request Mic1 detect IRQ: %d\n",
2532 ret);
2533
2534 ret = wm8994_request_irq(codec->control_data,
2535 WM8994_IRQ_MIC1_SHRT,
2536 wm8994_mic_irq, "Mic 1 short",
2537 wm8994);
2538 if (ret != 0)
2539 dev_warn(codec->dev,
2540 "Failed to request Mic1 short IRQ: %d\n",
2541 ret);
2542
2543 ret = wm8994_request_irq(codec->control_data,
2544 WM8994_IRQ_MIC2_DET,
2545 wm8994_mic_irq, "Mic 2 detect",
2546 wm8994);
2547 if (ret != 0)
2548 dev_warn(codec->dev,
2549 "Failed to request Mic2 detect IRQ: %d\n",
2550 ret);
2551
2552 ret = wm8994_request_irq(codec->control_data,
2553 WM8994_IRQ_MIC2_SHRT,
2554 wm8994_mic_irq, "Mic 2 short",
2555 wm8994);
2556 if (ret != 0)
2557 dev_warn(codec->dev,
2558 "Failed to request Mic2 short IRQ: %d\n",
2559 ret);
2560 break;
2561 }
88766984 2562
9e6e96a1
MB		 2563 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2564 * configured on init - if a system wants to do this dynamically
2565 * at runtime we can deal with that then.
2566 */
2567 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2568 if (ret < 0) {
2569 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 2570 goto err_irq;
9e6e96a1
MB		 2571 }
2572 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2573 wm8994->lrclk_shared[0] = 1;
2574 wm8994_dai[0].symmetric_rates = 1;
2575 } else {
2576 wm8994->lrclk_shared[0] = 0;
2577 }
2578
2579 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2580 if (ret < 0) {
2581 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 2582 goto err_irq;
9e6e96a1
MB		 2583 }
2584 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2585 wm8994->lrclk_shared[1] = 1;
2586 wm8994_dai[1].symmetric_rates = 1;
2587 } else {
2588 wm8994->lrclk_shared[1] = 0;
2589 }
2590
9e6e96a1
MB		 2591 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2592
9e6e96a1
MB		 2593 /* Latch volume updates (right only; we always do left then right). */
2594 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
2595 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
2596 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
2597 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
2598 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
2599 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
2600 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
2601 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
2602 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
2603 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
2604 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
2605 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
2606 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
2607 WM8994_DAC1_VU, WM8994_DAC1_VU);
2608 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
2609 WM8994_DAC2_VU, WM8994_DAC2_VU);
2610
2611 /* Set the low bit of the 3D stereo depth so TLV matches */
2612 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
2613 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
2614 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
2615 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
2616 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
2617 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
2618 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
2619 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
2620 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
2621
d1ce6b20
MB		 2622 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
2623 * behaviour on idle TDM clock cycles. */
2624 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
2625 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
2626
9e6e96a1
MB		 2627 wm8994_update_class_w(codec);
2628
f0fba2ad 2629 wm8994_handle_pdata(wm8994);
9e6e96a1 2630
f0fba2ad
LG		 2631 wm_hubs_add_analogue_controls(codec);
2632 snd_soc_add_controls(codec, wm8994_snd_controls,
2633 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 2634 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 2635 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 2636
2637 switch (control->type) {
2638 case WM8994:
2639 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
2640 ARRAY_SIZE(wm8994_specific_dapm_widgets));
2641 break;
2642 case WM8958:
2643 snd_soc_add_controls(codec, wm8958_snd_controls,
2644 ARRAY_SIZE(wm8958_snd_controls));
2645 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
2646 ARRAY_SIZE(wm8958_dapm_widgets));
2647 break;
2648 }
2649
2650
f0fba2ad 2651 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 2652 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 2653
c4431df0
MB		 2654 switch (control->type) {
2655 case WM8994:
2656 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
2657 ARRAY_SIZE(wm8994_intercon));
2658 break;
2659 case WM8958:
2660 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
2661 ARRAY_SIZE(wm8958_intercon));
2662 break;
2663 }
2664
9e6e96a1
MB		 2665 return 0;
2666
88766984
MB		 2667err_irq:
2668 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
2669 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
2670 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
2671 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
9e6e96a1
MB		 2672err:
2673 kfree(wm8994);
2674 return ret;
2675}
2676
f0fba2ad 2677static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 2678{
f0fba2ad 2679 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 2680 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2681
2682 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 2683
3a423157
MB		 2684 switch (control->type) {
2685 case WM8994:
2686 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
2687 wm8994);
2688 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
2689 wm8994);
2690 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
2691 wm8994);
2692 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
2693 wm8994);
2694 break;
2695 }
24fb2b11
AL		 2696 kfree(wm8994->retune_mobile_texts);
2697 kfree(wm8994->drc_texts);
9e6e96a1 2698 kfree(wm8994);
9e6e96a1
MB		 2699
2700 return 0;
2701}
2702
f0fba2ad
LG		 2703static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
2704 .probe = wm8994_codec_probe,
2705 .remove = wm8994_codec_remove,
2706 .suspend = wm8994_suspend,
2707 .resume = wm8994_resume,
2708 .read = wm8994_read,
2709 .write = wm8994_write,
eba19fdd
MB		 2710 .readable_register = wm8994_readable,
2711 .volatile_register = wm8994_volatile,
f0fba2ad
LG		 2712 .set_bias_level = wm8994_set_bias_level,
2713};
2714
2715static int __devinit wm8994_probe(struct platform_device *pdev)
2716{
2717 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
2718 wm8994_dai, ARRAY_SIZE(wm8994_dai));
2719}
2720
2721static int __devexit wm8994_remove(struct platform_device *pdev)
2722{
2723 snd_soc_unregister_codec(&pdev->dev);
2724 return 0;
2725}
2726
9e6e96a1
MB		 2727static struct platform_driver wm8994_codec_driver = {
2728 .driver = {
2729 .name = "wm8994-codec",
2730 .owner = THIS_MODULE,
2731 },
f0fba2ad
LG		 2732 .probe = wm8994_probe,
2733 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 2734};
2735
2736static __init int wm8994_init(void)
2737{
2738 return platform_driver_register(&wm8994_codec_driver);
2739}
2740module_init(wm8994_init);
2741
2742static __exit void wm8994_exit(void)
2743{
2744 platform_driver_unregister(&wm8994_codec_driver);
2745}
2746module_exit(wm8994_exit);
2747
2748
2749MODULE_DESCRIPTION("ASoC WM8994 driver");
2750MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2751MODULE_LICENSE("GPL");
2752MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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