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ASoC: wm8994: Don't lock CODEC mutex to do DAPM sync
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
af6b6fe4
MB		 41#define WM1811_JACKDET_MODE_NONE 0x0000
42#define WM1811_JACKDET_MODE_JACK 0x0100
43#define WM1811_JACKDET_MODE_MIC 0x0080
44#define WM1811_JACKDET_MODE_AUDIO 0x0180
45
9e6e96a1
MB		 46#define WM8994_NUM_DRC 3
47#define WM8994_NUM_EQ 3
48
49static int wm8994_drc_base[] = {
50 WM8994_AIF1_DRC1_1,
51 WM8994_AIF1_DRC2_1,
52 WM8994_AIF2_DRC_1,
53};
54
55static int wm8994_retune_mobile_base[] = {
56 WM8994_AIF1_DAC1_EQ_GAINS_1,
57 WM8994_AIF1_DAC2_EQ_GAINS_1,
58 WM8994_AIF2_EQ_GAINS_1,
59};
60
b00adf76
MB		 61static void wm8958_default_micdet(u16 status, void *data);
62
af6b6fe4 63static const struct wm8958_micd_rate micdet_rates[] = {
b00adf76
MB		 64 { 32768, true, 1, 4 },
65 { 32768, false, 1, 1 },
604533de
MB		 66 { 44100 * 256, true, 7, 10 },
67 { 44100 * 256, false, 7, 10 },
b00adf76
MB		 68};
69
af6b6fe4
MB		 70static const struct wm8958_micd_rate jackdet_rates[] = {
71 { 32768, true, 0, 1 },
72 { 32768, false, 0, 1 },
73 { 44100 * 256, true, 7, 10 },
74 { 44100 * 256, false, 7, 10 },
75};
76
b00adf76
MB		 77static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
78{
79 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
80 int best, i, sysclk, val;
81 bool idle;
af6b6fe4
MB		 82 const struct wm8958_micd_rate *rates;
83 int num_rates;
b00adf76
MB		 84
85 if (wm8994->jack_cb != wm8958_default_micdet)
86 return;
87
88 idle = !wm8994->jack_mic;
89
90 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
91 if (sysclk & WM8994_SYSCLK_SRC)
92 sysclk = wm8994->aifclk[1];
93 else
94 sysclk = wm8994->aifclk[0];
95
cd1707a9
MB		 96 if (wm8994->pdata && wm8994->pdata->micd_rates) {
97 rates = wm8994->pdata->micd_rates;
98 num_rates = wm8994->pdata->num_micd_rates;
99 } else if (wm8994->jackdet) {
af6b6fe4
MB		 100 rates = jackdet_rates;
101 num_rates = ARRAY_SIZE(jackdet_rates);
102 } else {
103 rates = micdet_rates;
104 num_rates = ARRAY_SIZE(micdet_rates);
105 }
106
b00adf76 107 best = 0;
af6b6fe4
MB		 108 for (i = 0; i < num_rates; i++) {
109 if (rates[i].idle != idle)
b00adf76 110 continue;
af6b6fe4
MB		 111 if (abs(rates[i].sysclk - sysclk) <
112 abs(rates[best].sysclk - sysclk))
b00adf76 113 best = i;
af6b6fe4 114 else if (rates[best].idle != idle)
b00adf76
MB		 115 best = i;
116 }
117
af6b6fe4
MB		 118 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
119 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
b00adf76
MB		 120
121 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
122 WM8958_MICD_BIAS_STARTTIME_MASK |
123 WM8958_MICD_RATE_MASK, val);
124}
125
9e6e96a1
MB		 126static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
127{
b2c812e2 128 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 129 int rate;
130 int reg1 = 0;
131 int offset;
132
133 if (aif)
134 offset = 4;
135 else
136 offset = 0;
137
138 switch (wm8994->sysclk[aif]) {
139 case WM8994_SYSCLK_MCLK1:
140 rate = wm8994->mclk[0];
141 break;
142
143 case WM8994_SYSCLK_MCLK2:
144 reg1 |= 0x8;
145 rate = wm8994->mclk[1];
146 break;
147
148 case WM8994_SYSCLK_FLL1:
149 reg1 |= 0x10;
150 rate = wm8994->fll[0].out;
151 break;
152
153 case WM8994_SYSCLK_FLL2:
154 reg1 |= 0x18;
155 rate = wm8994->fll[1].out;
156 break;
157
158 default:
159 return -EINVAL;
160 }
161
162 if (rate >= 13500000) {
163 rate /= 2;
164 reg1 |= WM8994_AIF1CLK_DIV;
165
166 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
167 aif + 1, rate);
168 }
5e5e2bef 169
9e6e96a1
MB		 170 wm8994->aifclk[aif] = rate;
171
172 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
173 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
174 reg1);
175
176 return 0;
177}
178
179static int configure_clock(struct snd_soc_codec *codec)
180{
b2c812e2 181 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
04f45c49 182 int change, new;
9e6e96a1
MB		 183
184 /* Bring up the AIF clocks first */
185 configure_aif_clock(codec, 0);
186 configure_aif_clock(codec, 1);
187
188 /* Then switch CLK_SYS over to the higher of them; a change
189 * can only happen as a result of a clocking change which can
190 * only be made outside of DAPM so we can safely redo the
191 * clocking.
192 */
193
194 /* If they're equal it doesn't matter which is used */
b00adf76
MB		 195 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
196 wm8958_micd_set_rate(codec);
9e6e96a1 197 return 0;
b00adf76 198 }
9e6e96a1
MB		 199
200 if (wm8994->aifclk[0] < wm8994->aifclk[1])
201 new = WM8994_SYSCLK_SRC;
202 else
203 new = 0;
204
04f45c49
AL		 205 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
206 WM8994_SYSCLK_SRC, new);
52ac7ab2
MB		 207 if (change)
208 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1 209
b00adf76
MB		 210 wm8958_micd_set_rate(codec);
211
9e6e96a1
MB		 212 return 0;
213}
214
215static int check_clk_sys(struct snd_soc_dapm_widget *source,
216 struct snd_soc_dapm_widget *sink)
217{
218 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
219 const char *clk;
220
221 /* Check what we're currently using for CLK_SYS */
222 if (reg & WM8994_SYSCLK_SRC)
223 clk = "AIF2CLK";
224 else
225 clk = "AIF1CLK";
226
227 return strcmp(source->name, clk) == 0;
228}
229
230static const char *sidetone_hpf_text[] = {
231 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
232};
233
234static const struct soc_enum sidetone_hpf =
235 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
236
146fd574
UK		 237static const char *adc_hpf_text[] = {
238 "HiFi", "Voice 1", "Voice 2", "Voice 3"
239};
240
241static const struct soc_enum aif1adc1_hpf =
242 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
243
244static const struct soc_enum aif1adc2_hpf =
245 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
246
247static const struct soc_enum aif2adc_hpf =
248 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
249
9e6e96a1
MB		 250static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
251static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
252static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
253static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
254static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1ddc07d0 255static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
81204c84 256static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
9e6e96a1
MB		 257
258#define WM8994_DRC_SWITCH(xname, reg, shift) \
259{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
260 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
261 .put = wm8994_put_drc_sw, \
262 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
263
264static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
265 struct snd_ctl_elem_value *ucontrol)
266{
267 struct soc_mixer_control *mc =
268 (struct soc_mixer_control *)kcontrol->private_value;
269 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
270 int mask, ret;
271
272 /* Can't enable both ADC and DAC paths simultaneously */
273 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
274 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
275 WM8994_AIF1ADC1R_DRC_ENA_MASK;
276 else
277 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
278
279 ret = snd_soc_read(codec, mc->reg);
280 if (ret < 0)
281 return ret;
282 if (ret & mask)
283 return -EINVAL;
284
285 return snd_soc_put_volsw(kcontrol, ucontrol);
286}
287
9e6e96a1
MB		 288static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
289{
b2c812e2 290 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 291 struct wm8994_pdata *pdata = wm8994->pdata;
292 int base = wm8994_drc_base[drc];
293 int cfg = wm8994->drc_cfg[drc];
294 int save, i;
295
296 /* Save any enables; the configuration should clear them. */
297 save = snd_soc_read(codec, base);
298 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
299 WM8994_AIF1ADC1R_DRC_ENA;
300
301 for (i = 0; i < WM8994_DRC_REGS; i++)
302 snd_soc_update_bits(codec, base + i, 0xffff,
303 pdata->drc_cfgs[cfg].regs[i]);
304
305 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
306 WM8994_AIF1ADC1L_DRC_ENA |
307 WM8994_AIF1ADC1R_DRC_ENA, save);
308}
309
310/* Icky as hell but saves code duplication */
311static int wm8994_get_drc(const char *name)
312{
313 if (strcmp(name, "AIF1DRC1 Mode") == 0)
314 return 0;
315 if (strcmp(name, "AIF1DRC2 Mode") == 0)
316 return 1;
317 if (strcmp(name, "AIF2DRC Mode") == 0)
318 return 2;
319 return -EINVAL;
320}
321
322static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_value *ucontrol)
324{
325 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 326 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 327 struct wm8994_pdata *pdata = wm8994->pdata;
328 int drc = wm8994_get_drc(kcontrol->id.name);
329 int value = ucontrol->value.integer.value[0];
330
331 if (drc < 0)
332 return drc;
333
334 if (value >= pdata->num_drc_cfgs)
335 return -EINVAL;
336
337 wm8994->drc_cfg[drc] = value;
338
339 wm8994_set_drc(codec, drc);
340
341 return 0;
342}
343
344static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
345 struct snd_ctl_elem_value *ucontrol)
346{
347 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 348 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 349 int drc = wm8994_get_drc(kcontrol->id.name);
350
351 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
352
353 return 0;
354}
355
356static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
357{
b2c812e2 358 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 359 struct wm8994_pdata *pdata = wm8994->pdata;
360 int base = wm8994_retune_mobile_base[block];
361 int iface, best, best_val, save, i, cfg;
362
363 if (!pdata || !wm8994->num_retune_mobile_texts)
364 return;
365
366 switch (block) {
367 case 0:
368 case 1:
369 iface = 0;
370 break;
371 case 2:
372 iface = 1;
373 break;
374 default:
375 return;
376 }
377
378 /* Find the version of the currently selected configuration
379 * with the nearest sample rate. */
380 cfg = wm8994->retune_mobile_cfg[block];
381 best = 0;
382 best_val = INT_MAX;
383 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
384 if (strcmp(pdata->retune_mobile_cfgs[i].name,
385 wm8994->retune_mobile_texts[cfg]) == 0 &&
386 abs(pdata->retune_mobile_cfgs[i].rate
387 - wm8994->dac_rates[iface]) < best_val) {
388 best = i;
389 best_val = abs(pdata->retune_mobile_cfgs[i].rate
390 - wm8994->dac_rates[iface]);
391 }
392 }
393
394 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
395 block,
396 pdata->retune_mobile_cfgs[best].name,
397 pdata->retune_mobile_cfgs[best].rate,
398 wm8994->dac_rates[iface]);
399
400 /* The EQ will be disabled while reconfiguring it, remember the
401 * current configuration.
402 */
403 save = snd_soc_read(codec, base);
404 save &= WM8994_AIF1DAC1_EQ_ENA;
405
406 for (i = 0; i < WM8994_EQ_REGS; i++)
407 snd_soc_update_bits(codec, base + i, 0xffff,
408 pdata->retune_mobile_cfgs[best].regs[i]);
409
410 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
411}
412
413/* Icky as hell but saves code duplication */
414static int wm8994_get_retune_mobile_block(const char *name)
415{
416 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
417 return 0;
418 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
419 return 1;
420 if (strcmp(name, "AIF2 EQ Mode") == 0)
421 return 2;
422 return -EINVAL;
423}
424
425static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
426 struct snd_ctl_elem_value *ucontrol)
427{
428 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 430 struct wm8994_pdata *pdata = wm8994->pdata;
431 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
432 int value = ucontrol->value.integer.value[0];
433
434 if (block < 0)
435 return block;
436
437 if (value >= pdata->num_retune_mobile_cfgs)
438 return -EINVAL;
439
440 wm8994->retune_mobile_cfg[block] = value;
441
442 wm8994_set_retune_mobile(codec, block);
443
444 return 0;
445}
446
447static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
448 struct snd_ctl_elem_value *ucontrol)
449{
450 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 451 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 452 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
453
454 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
455
456 return 0;
457}
458
96b101ef 459static const char *aif_chan_src_text[] = {
f554885f
MB		 460 "Left", "Right"
461};
462
96b101ef
MB		 463static const struct soc_enum aif1adcl_src =
464 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
465
466static const struct soc_enum aif1adcr_src =
467 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
468
469static const struct soc_enum aif2adcl_src =
470 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
471
472static const struct soc_enum aif2adcr_src =
473 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
474
f554885f 475static const struct soc_enum aif1dacl_src =
96b101ef 476 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 477
478static const struct soc_enum aif1dacr_src =
96b101ef 479 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 480
481static const struct soc_enum aif2dacl_src =
96b101ef 482 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 483
484static const struct soc_enum aif2dacr_src =
96b101ef 485 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 486
154b26aa
MB		 487static const char *osr_text[] = {
488 "Low Power", "High Performance",
489};
490
491static const struct soc_enum dac_osr =
492 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
493
494static const struct soc_enum adc_osr =
495 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
496
9e6e96a1
MB		 497static const struct snd_kcontrol_new wm8994_snd_controls[] = {
498SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
499 WM8994_AIF1_ADC1_RIGHT_VOLUME,
500 1, 119, 0, digital_tlv),
501SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
502 WM8994_AIF1_ADC2_RIGHT_VOLUME,
503 1, 119, 0, digital_tlv),
504SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
505 WM8994_AIF2_ADC_RIGHT_VOLUME,
506 1, 119, 0, digital_tlv),
507
96b101ef
MB		 508SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
509SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 510SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
511SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 512
f554885f
MB		 513SOC_ENUM("AIF1DACL Source", aif1dacl_src),
514SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 515SOC_ENUM("AIF2DACL Source", aif2dacl_src),
516SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 517
9e6e96a1
MB		 518SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
519 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
520SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
521 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
522SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
523 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
524
525SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
526SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
527
528SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
529SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
530SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
531
532WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
533WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
534WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
535
536WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
537WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
538WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
539
540WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
541WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
542WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
543
544SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
545 5, 12, 0, st_tlv),
546SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
547 0, 12, 0, st_tlv),
548SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
549 5, 12, 0, st_tlv),
550SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
551 0, 12, 0, st_tlv),
552SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
553SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
554
146fd574
UK		 555SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
556SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
557
558SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
559SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
560
561SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
562SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
563
154b26aa
MB		 564SOC_ENUM("ADC OSR", adc_osr),
565SOC_ENUM("DAC OSR", dac_osr),
566
9e6e96a1
MB		 567SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
568 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
569SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
570 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
571
572SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
573 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
574SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
575 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
576
577SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
578 6, 1, 1, wm_hubs_spkmix_tlv),
579SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
580 2, 1, 1, wm_hubs_spkmix_tlv),
581
582SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
583 6, 1, 1, wm_hubs_spkmix_tlv),
584SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
585 2, 1, 1, wm_hubs_spkmix_tlv),
586
587SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
588 10, 15, 0, wm8994_3d_tlv),
458350b3 589SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 590 8, 1, 0),
591SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
592 10, 15, 0, wm8994_3d_tlv),
593SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
594 8, 1, 0),
458350b3 595SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 596 10, 15, 0, wm8994_3d_tlv),
458350b3 597SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 598 8, 1, 0),
599};
600
601static const struct snd_kcontrol_new wm8994_eq_controls[] = {
602SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
603 eq_tlv),
604SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
605 eq_tlv),
606SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
607 eq_tlv),
608SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
609 eq_tlv),
610SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
611 eq_tlv),
612
613SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
614 eq_tlv),
615SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
616 eq_tlv),
617SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
618 eq_tlv),
619SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
620 eq_tlv),
621SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
622 eq_tlv),
623
624SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
625 eq_tlv),
626SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
627 eq_tlv),
628SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
629 eq_tlv),
630SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
631 eq_tlv),
632SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
633 eq_tlv),
634};
635
1ddc07d0
MB		 636static const char *wm8958_ng_text[] = {
637 "30ms", "125ms", "250ms", "500ms",
638};
639
640static const struct soc_enum wm8958_aif1dac1_ng_hold =
641 SOC_ENUM_SINGLE(WM8958_AIF1_DAC1_NOISE_GATE,
642 WM8958_AIF1DAC1_NG_THR_SHIFT, 4, wm8958_ng_text);
643
644static const struct soc_enum wm8958_aif1dac2_ng_hold =
645 SOC_ENUM_SINGLE(WM8958_AIF1_DAC2_NOISE_GATE,
646 WM8958_AIF1DAC2_NG_THR_SHIFT, 4, wm8958_ng_text);
647
648static const struct soc_enum wm8958_aif2dac_ng_hold =
649 SOC_ENUM_SINGLE(WM8958_AIF2_DAC_NOISE_GATE,
650 WM8958_AIF2DAC_NG_THR_SHIFT, 4, wm8958_ng_text);
651
c4431df0
MB		 652static const struct snd_kcontrol_new wm8958_snd_controls[] = {
653SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
1ddc07d0
MB		 654
655SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
656 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
657SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
658SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
659 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
660 7, 1, ng_tlv),
661
662SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
663 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
664SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
665SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
666 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
667 7, 1, ng_tlv),
668
669SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
670 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
671SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
672SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
673 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
674 7, 1, ng_tlv),
c4431df0
MB		 675};
676
81204c84
MB		 677static const struct snd_kcontrol_new wm1811_snd_controls[] = {
678SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
679 mixin_boost_tlv),
680SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
681 mixin_boost_tlv),
682};
683
af6b6fe4
MB		 684/* We run all mode setting through a function to enforce audio mode */
685static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
686{
687 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
688
28e33269
MB		 689 if (!wm8994->jackdet || !wm8994->jack_cb)
690 return;
691
af6b6fe4
MB		 692 if (wm8994->active_refcount)
693 mode = WM1811_JACKDET_MODE_AUDIO;
694
4752a887 695 if (mode == wm8994->jackdet_mode)
1defde2a
MB		 696 return;
697
4752a887 698 wm8994->jackdet_mode = mode;
1defde2a 699
4752a887
MB		 700 /* Always use audio mode to detect while the system is active */
701 if (mode != WM1811_JACKDET_MODE_NONE)
702 mode = WM1811_JACKDET_MODE_AUDIO;
1defde2a 703
4752a887
MB		 704 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
705 WM1811_JACKDET_MODE_MASK, mode);
af6b6fe4
MB		 706}
707
708static void active_reference(struct snd_soc_codec *codec)
709{
710 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
711
712 mutex_lock(&wm8994->accdet_lock);
713
714 wm8994->active_refcount++;
715
716 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
717 wm8994->active_refcount);
718
1defde2a
MB		 719 /* If we're using jack detection go into audio mode */
720 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
af6b6fe4
MB		 721
722 mutex_unlock(&wm8994->accdet_lock);
723}
724
725static void active_dereference(struct snd_soc_codec *codec)
726{
727 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
728 u16 mode;
729
730 mutex_lock(&wm8994->accdet_lock);
731
732 wm8994->active_refcount--;
733
734 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
735 wm8994->active_refcount);
736
737 if (wm8994->active_refcount == 0) {
738 /* Go into appropriate detection only mode */
1defde2a
MB		 739 if (wm8994->jack_mic || wm8994->mic_detecting)
740 mode = WM1811_JACKDET_MODE_MIC;
741 else
742 mode = WM1811_JACKDET_MODE_JACK;
743
744 wm1811_jackdet_set_mode(codec, mode);
af6b6fe4
MB		 745 }
746
747 mutex_unlock(&wm8994->accdet_lock);
748}
749
9e6e96a1
MB		 750static int clk_sys_event(struct snd_soc_dapm_widget *w,
751 struct snd_kcontrol *kcontrol, int event)
752{
753 struct snd_soc_codec *codec = w->codec;
754
755 switch (event) {
756 case SND_SOC_DAPM_PRE_PMU:
757 return configure_clock(codec);
758
759 case SND_SOC_DAPM_POST_PMD:
760 configure_clock(codec);
761 break;
762 }
763
764 return 0;
765}
766
4b7ed83a
MB		 767static void vmid_reference(struct snd_soc_codec *codec)
768{
769 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
770
db966f8a
MB		 771 pm_runtime_get_sync(codec->dev);
772
4b7ed83a
MB		 773 wm8994->vmid_refcount++;
774
775 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
776 wm8994->vmid_refcount);
777
778 if (wm8994->vmid_refcount == 1) {
cc6d5a8c 779 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
cc6d5a8c 780 WM8994_LINEOUT1_DISCH |
22f8d055 781 WM8994_LINEOUT2_DISCH, 0);
cc6d5a8c 782
f7085641
MB		 783 wm_hubs_vmid_ena(codec);
784
22f8d055
MB		 785 switch (wm8994->vmid_mode) {
786 default:
787 WARN_ON(0 == "Invalid VMID mode");
788 case WM8994_VMID_NORMAL:
789 /* Startup bias, VMID ramp & buffer */
790 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
791 WM8994_BIAS_SRC |
792 WM8994_VMID_DISCH |
793 WM8994_STARTUP_BIAS_ENA |
794 WM8994_VMID_BUF_ENA |
795 WM8994_VMID_RAMP_MASK,
796 WM8994_BIAS_SRC |
797 WM8994_STARTUP_BIAS_ENA |
798 WM8994_VMID_BUF_ENA |
799 (0x3 << WM8994_VMID_RAMP_SHIFT));
800
801 /* Main bias enable, VMID=2x40k */
802 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
803 WM8994_BIAS_ENA |
804 WM8994_VMID_SEL_MASK,
805 WM8994_BIAS_ENA | 0x2);
806
807 msleep(50);
808
809 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
810 WM8994_VMID_RAMP_MASK |
811 WM8994_BIAS_SRC,
812 0);
813 break;
cc6d5a8c 814
22f8d055
MB		 815 case WM8994_VMID_FORCE:
816 /* Startup bias, slow VMID ramp & buffer */
817 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
818 WM8994_BIAS_SRC |
819 WM8994_VMID_DISCH |
820 WM8994_STARTUP_BIAS_ENA |
821 WM8994_VMID_BUF_ENA |
822 WM8994_VMID_RAMP_MASK,
823 WM8994_BIAS_SRC |
824 WM8994_STARTUP_BIAS_ENA |
825 WM8994_VMID_BUF_ENA |
826 (0x2 << WM8994_VMID_RAMP_SHIFT));
827
828 /* Main bias enable, VMID=2x40k */
829 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
830 WM8994_BIAS_ENA |
831 WM8994_VMID_SEL_MASK,
832 WM8994_BIAS_ENA | 0x2);
833
834 msleep(400);
835
836 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
837 WM8994_VMID_RAMP_MASK |
838 WM8994_BIAS_SRC,
839 0);
840 break;
841 }
4b7ed83a
MB		 842 }
843}
844
845static void vmid_dereference(struct snd_soc_codec *codec)
846{
847 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
848
849 wm8994->vmid_refcount--;
850
851 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
852 wm8994->vmid_refcount);
853
854 if (wm8994->vmid_refcount == 0) {
22f8d055
MB		 855 if (wm8994->hubs.lineout1_se)
856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
857 WM8994_LINEOUT1N_ENA |
858 WM8994_LINEOUT1P_ENA,
859 WM8994_LINEOUT1N_ENA |
860 WM8994_LINEOUT1P_ENA);
861
862 if (wm8994->hubs.lineout2_se)
863 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
864 WM8994_LINEOUT2N_ENA |
865 WM8994_LINEOUT2P_ENA,
866 WM8994_LINEOUT2N_ENA |
867 WM8994_LINEOUT2P_ENA);
868
869 /* Start discharging VMID */
4b7ed83a
MB		 870 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
871 WM8994_BIAS_SRC |
22f8d055 872 WM8994_VMID_DISCH,
4b7ed83a 873 WM8994_BIAS_SRC |
22f8d055 874 WM8994_VMID_DISCH);
4b7ed83a 875
22f8d055
MB		 876 switch (wm8994->vmid_mode) {
877 case WM8994_VMID_FORCE:
878 msleep(350);
879 break;
880 default:
881 break;
882 }
4b7ed83a 883
22f8d055
MB		 884 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
885 WM8994_VROI, WM8994_VROI);
e85b26ce 886
22f8d055 887 /* Active discharge */
4b7ed83a
MB		 888 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
889 WM8994_LINEOUT1_DISCH |
890 WM8994_LINEOUT2_DISCH,
891 WM8994_LINEOUT1_DISCH |
892 WM8994_LINEOUT2_DISCH);
893
22f8d055
MB		 894 msleep(150);
895
896 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
897 WM8994_LINEOUT1N_ENA |
898 WM8994_LINEOUT1P_ENA |
899 WM8994_LINEOUT2N_ENA |
900 WM8994_LINEOUT2P_ENA, 0);
901
902 snd_soc_update_bits(codec, WM8994_ADDITIONAL_CONTROL,
903 WM8994_VROI, 0);
4b7ed83a
MB		 904
905 /* Switch off startup biases */
906 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
907 WM8994_BIAS_SRC |
908 WM8994_STARTUP_BIAS_ENA |
909 WM8994_VMID_BUF_ENA |
910 WM8994_VMID_RAMP_MASK, 0);
22f8d055
MB		 911
912 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
913 WM8994_BIAS_ENA | WM8994_VMID_SEL_MASK, 0);
914
915 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
916 WM8994_VMID_RAMP_MASK, 0);
4b7ed83a 917 }
db966f8a
MB		 918
919 pm_runtime_put(codec->dev);
4b7ed83a
MB		 920}
921
922static int vmid_event(struct snd_soc_dapm_widget *w,
923 struct snd_kcontrol *kcontrol, int event)
924{
925 struct snd_soc_codec *codec = w->codec;
926
927 switch (event) {
928 case SND_SOC_DAPM_PRE_PMU:
929 vmid_reference(codec);
930 break;
931
932 case SND_SOC_DAPM_POST_PMD:
933 vmid_dereference(codec);
934 break;
935 }
936
937 return 0;
938}
939
9e6e96a1
MB		 940static void wm8994_update_class_w(struct snd_soc_codec *codec)
941{
fec6dd83 942 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 943 int enable = 1;
944 int source = 0; /* GCC flow analysis can't track enable */
945 int reg, reg_r;
946
947 /* Only support direct DAC->headphone paths */
948 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
949 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 950 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 951 enable = 0;
952 }
953
954 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
955 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 956 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 957 enable = 0;
958 }
959
960 /* We also need the same setting for L/R and only one path */
961 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
962 switch (reg) {
963 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 964 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 965 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
966 break;
967 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 968 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 969 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
970 break;
971 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 972 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 973 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
974 break;
975 default:
ee839a21 976 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 977 enable = 0;
978 break;
979 }
980
981 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
982 if (reg_r != reg) {
ee839a21 983 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 984 enable = 0;
985 }
986
987 if (enable) {
988 dev_dbg(codec->dev, "Class W enabled\n");
989 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
990 WM8994_CP_DYN_PWR |
991 WM8994_CP_DYN_SRC_SEL_MASK,
992 source | WM8994_CP_DYN_PWR);
fec6dd83 993 wm8994->hubs.class_w = true;
9e6e96a1
MB		 994
995 } else {
996 dev_dbg(codec->dev, "Class W disabled\n");
997 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
998 WM8994_CP_DYN_PWR, 0);
fec6dd83 999 wm8994->hubs.class_w = false;
9e6e96a1
MB		 1000 }
1001}
1002
173efa09
DP		 1003static int late_enable_ev(struct snd_soc_dapm_widget *w,
1004 struct snd_kcontrol *kcontrol, int event)
1005{
1006 struct snd_soc_codec *codec = w->codec;
1007 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1008
1009 switch (event) {
1010 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 1011 if (wm8994->aif1clk_enable) {
173efa09
DP		 1012 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1013 WM8994_AIF1CLK_ENA_MASK,
1014 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 1015 wm8994->aif1clk_enable = 0;
1016 }
1017 if (wm8994->aif2clk_enable) {
173efa09
DP		 1018 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1019 WM8994_AIF2CLK_ENA_MASK,
1020 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 1021 wm8994->aif2clk_enable = 0;
1022 }
173efa09
DP		 1023 break;
1024 }
1025
c6b7b570
MB		 1026 /* We may also have postponed startup of DSP, handle that. */
1027 wm8958_aif_ev(w, kcontrol, event);
1028
173efa09
DP		 1029 return 0;
1030}
1031
1032static int late_disable_ev(struct snd_soc_dapm_widget *w,
1033 struct snd_kcontrol *kcontrol, int event)
1034{
1035 struct snd_soc_codec *codec = w->codec;
1036 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1037
1038 switch (event) {
1039 case SND_SOC_DAPM_POST_PMD:
a3cff81a 1040 if (wm8994->aif1clk_disable) {
173efa09
DP		 1041 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1042 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 1043 wm8994->aif1clk_disable = 0;
173efa09 1044 }
a3cff81a 1045 if (wm8994->aif2clk_disable) {
173efa09
DP		 1046 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1047 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 1048 wm8994->aif2clk_disable = 0;
173efa09
DP		 1049 }
1050 break;
1051 }
1052
1053 return 0;
1054}
1055
1056static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1057 struct snd_kcontrol *kcontrol, int event)
1058{
1059 struct snd_soc_codec *codec = w->codec;
1060 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1061
1062 switch (event) {
1063 case SND_SOC_DAPM_PRE_PMU:
1064 wm8994->aif1clk_enable = 1;
1065 break;
a3cff81a
DP		 1066 case SND_SOC_DAPM_POST_PMD:
1067 wm8994->aif1clk_disable = 1;
1068 break;
173efa09
DP		 1069 }
1070
1071 return 0;
1072}
1073
1074static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1075 struct snd_kcontrol *kcontrol, int event)
1076{
1077 struct snd_soc_codec *codec = w->codec;
1078 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1079
1080 switch (event) {
1081 case SND_SOC_DAPM_PRE_PMU:
1082 wm8994->aif2clk_enable = 1;
1083 break;
a3cff81a
DP		 1084 case SND_SOC_DAPM_POST_PMD:
1085 wm8994->aif2clk_disable = 1;
1086 break;
173efa09
DP		 1087 }
1088
1089 return 0;
1090}
1091
04d28681
DP		 1092static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1093 struct snd_kcontrol *kcontrol, int event)
1094{
1095 late_enable_ev(w, kcontrol, event);
1096 return 0;
1097}
1098
b462c6e6
DP		 1099static int micbias_ev(struct snd_soc_dapm_widget *w,
1100 struct snd_kcontrol *kcontrol, int event)
1101{
1102 late_enable_ev(w, kcontrol, event);
1103 return 0;
1104}
1105
c52fd021
DP		 1106static int dac_ev(struct snd_soc_dapm_widget *w,
1107 struct snd_kcontrol *kcontrol, int event)
1108{
1109 struct snd_soc_codec *codec = w->codec;
1110 unsigned int mask = 1 << w->shift;
1111
1112 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1113 mask, mask);
1114 return 0;
1115}
1116
9e6e96a1
MB		 1117static const char *hp_mux_text[] = {
1118 "Mixer",
1119 "DAC",
1120};
1121
1122#define WM8994_HP_ENUM(xname, xenum) \
1123{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1124 .info = snd_soc_info_enum_double, \
1125 .get = snd_soc_dapm_get_enum_double, \
1126 .put = wm8994_put_hp_enum, \
1127 .private_value = (unsigned long)&xenum }
1128
1129static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
1130 struct snd_ctl_elem_value *ucontrol)
1131{
9d03545d
JN		 1132 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1133 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1134 struct snd_soc_codec *codec = w->codec;
1135 int ret;
1136
1137 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
1138
1139 wm8994_update_class_w(codec);
1140
1141 return ret;
1142}
1143
1144static const struct soc_enum hpl_enum =
1145 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
1146
1147static const struct snd_kcontrol_new hpl_mux =
1148 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1149
1150static const struct soc_enum hpr_enum =
1151 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1152
1153static const struct snd_kcontrol_new hpr_mux =
1154 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1155
1156static const char *adc_mux_text[] = {
1157 "ADC",
1158 "DMIC",
1159};
1160
1161static const struct soc_enum adc_enum =
1162 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1163
1164static const struct snd_kcontrol_new adcl_mux =
1165 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1166
1167static const struct snd_kcontrol_new adcr_mux =
1168 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1169
1170static const struct snd_kcontrol_new left_speaker_mixer[] = {
1171SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1172SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1173SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1174SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1175SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1176};
1177
1178static const struct snd_kcontrol_new right_speaker_mixer[] = {
1179SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1180SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1181SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1182SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1183SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1184};
1185
1186/* Debugging; dump chip status after DAPM transitions */
1187static int post_ev(struct snd_soc_dapm_widget *w,
1188 struct snd_kcontrol *kcontrol, int event)
1189{
1190 struct snd_soc_codec *codec = w->codec;
1191 dev_dbg(codec->dev, "SRC status: %x\n",
1192 snd_soc_read(codec,
1193 WM8994_RATE_STATUS));
1194 return 0;
1195}
1196
1197static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1198SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1199 1, 1, 0),
1200SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1201 0, 1, 0),
1202};
1203
1204static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1205SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1206 1, 1, 0),
1207SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1208 0, 1, 0),
1209};
1210
a3257ba8
MB		 1211static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1212SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1213 1, 1, 0),
1214SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1215 0, 1, 0),
1216};
1217
1218static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1219SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1220 1, 1, 0),
1221SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1222 0, 1, 0),
1223};
1224
9e6e96a1
MB		 1225static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1226SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1227 5, 1, 0),
1228SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1229 4, 1, 0),
1230SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1231 2, 1, 0),
1232SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1233 1, 1, 0),
1234SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1235 0, 1, 0),
1236};
1237
1238static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1239SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1240 5, 1, 0),
1241SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1242 4, 1, 0),
1243SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1244 2, 1, 0),
1245SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1246 1, 1, 0),
1247SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1248 0, 1, 0),
1249};
1250
1251#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1252{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1253 .info = snd_soc_info_volsw, \
1254 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1255 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1256
1257static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1258 struct snd_ctl_elem_value *ucontrol)
1259{
9d03545d
JN		 1260 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1261 struct snd_soc_dapm_widget *w = wlist->widgets[0];
9e6e96a1
MB		 1262 struct snd_soc_codec *codec = w->codec;
1263 int ret;
1264
1265 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1266
1267 wm8994_update_class_w(codec);
1268
1269 return ret;
1270}
1271
1272static const struct snd_kcontrol_new dac1l_mix[] = {
1273WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1274 5, 1, 0),
1275WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1276 4, 1, 0),
1277WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1278 2, 1, 0),
1279WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1280 1, 1, 0),
1281WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1282 0, 1, 0),
1283};
1284
1285static const struct snd_kcontrol_new dac1r_mix[] = {
1286WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1287 5, 1, 0),
1288WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1289 4, 1, 0),
1290WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1291 2, 1, 0),
1292WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1293 1, 1, 0),
1294WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1295 0, 1, 0),
1296};
1297
1298static const char *sidetone_text[] = {
1299 "ADC/DMIC1", "DMIC2",
1300};
1301
1302static const struct soc_enum sidetone1_enum =
1303 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1304
1305static const struct snd_kcontrol_new sidetone1_mux =
1306 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1307
1308static const struct soc_enum sidetone2_enum =
1309 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1310
1311static const struct snd_kcontrol_new sidetone2_mux =
1312 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1313
1314static const char *aif1dac_text[] = {
1315 "AIF1DACDAT", "AIF3DACDAT",
1316};
1317
1318static const struct soc_enum aif1dac_enum =
1319 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1320
1321static const struct snd_kcontrol_new aif1dac_mux =
1322 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1323
1324static const char *aif2dac_text[] = {
1325 "AIF2DACDAT", "AIF3DACDAT",
1326};
1327
1328static const struct soc_enum aif2dac_enum =
1329 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1330
1331static const struct snd_kcontrol_new aif2dac_mux =
1332 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1333
1334static const char *aif2adc_text[] = {
1335 "AIF2ADCDAT", "AIF3DACDAT",
1336};
1337
1338static const struct soc_enum aif2adc_enum =
1339 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1340
1341static const struct snd_kcontrol_new aif2adc_mux =
1342 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1343
1344static const char *aif3adc_text[] = {
c4431df0 1345 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1346};
1347
c4431df0 1348static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1349 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1350
c4431df0
MB		 1351static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1352 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1353
1354static const struct soc_enum wm8958_aif3adc_enum =
1355 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1356
1357static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1358 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1359
1360static const char *mono_pcm_out_text[] = {
1361 "None", "AIF2ADCL", "AIF2ADCR",
1362};
1363
1364static const struct soc_enum mono_pcm_out_enum =
1365 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1366
1367static const struct snd_kcontrol_new mono_pcm_out_mux =
1368 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1369
1370static const char *aif2dac_src_text[] = {
1371 "AIF2", "AIF3",
1372};
1373
1374/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1375static const struct soc_enum aif2dacl_src_enum =
1376 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1377
1378static const struct snd_kcontrol_new aif2dacl_src_mux =
1379 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1380
1381static const struct soc_enum aif2dacr_src_enum =
1382 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1383
1384static const struct snd_kcontrol_new aif2dacr_src_mux =
1385 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1386
173efa09
DP		 1387static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1388SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1389 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1390SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1391 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1392
1393SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1394 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1395SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1396 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1397SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1398 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1399SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1400 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
b70a51ba
MB		 1401SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1402 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1403
1404SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1405 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1406 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1407SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1408 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1409 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1410SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1411 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1412SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1413 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
173efa09
DP		 1414
1415SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1416};
1417
1418static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1419SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
b70a51ba
MB		 1420SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1421SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1422SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1423 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1424SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1425 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1426SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1427SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
173efa09
DP		 1428};
1429
c52fd021
DP		 1430static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1431SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1432 dac_ev, SND_SOC_DAPM_PRE_PMU),
1433SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1434 dac_ev, SND_SOC_DAPM_PRE_PMU),
1435SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1436 dac_ev, SND_SOC_DAPM_PRE_PMU),
1437SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1438 dac_ev, SND_SOC_DAPM_PRE_PMU),
1439};
1440
1441static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1442SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1443SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1444SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1445SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1446};
1447
04d28681 1448static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
87b86ade
MB		 1449SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1450 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1451SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1452 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
04d28681
DP		 1453};
1454
1455static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
87b86ade
MB		 1456SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1457SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
04d28681
DP		 1458};
1459
9e6e96a1
MB		 1460static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1461SND_SOC_DAPM_INPUT("DMIC1DAT"),
1462SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1463SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1464
b462c6e6
DP		 1465SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1466 SND_SOC_DAPM_PRE_PMU),
4b7ed83a
MB		 1467SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1468 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
b462c6e6 1469
9e6e96a1
MB		 1470SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1471 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1472
1473SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1474SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1475SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1476
7f94de48 1477SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1478 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1479SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1480 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1481SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1482 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1483 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1484SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1485 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1486 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1487
7f94de48 1488SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1489 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1490SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1491 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1492SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1493 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1494 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1495SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1496 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1497 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1498
1499SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1500 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1501SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1502 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1503
a3257ba8
MB		 1504SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1505 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1506SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1507 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1508
9e6e96a1
MB		 1509SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1510 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1511SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1512 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1513
1514SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1515SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1516
1517SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1518 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1519SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1520 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1521
1522SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1523 WM8994_POWER_MANAGEMENT_4, 13, 0),
1524SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1525 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1526SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1527 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1528 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1529SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1530 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1531 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1 1532
5567d8c6
MB		 1533SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1534SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1535SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1536SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1537
1538SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1539SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1540SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1 1541
5567d8c6
MB		 1542SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1543SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1544
1545SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1546
1547SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1548SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1549SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1550SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1551
1552/* Power is done with the muxes since the ADC power also controls the
1553 * downsampling chain, the chip will automatically manage the analogue
1554 * specific portions.
1555 */
1556SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1557SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1558
9e6e96a1
MB		 1559SND_SOC_DAPM_POST("Debug log", post_ev),
1560};
1561
c4431df0
MB		 1562static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1563SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1564};
9e6e96a1 1565
c4431df0
MB		 1566static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1567SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1568SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1569SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1570SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1571};
1572
1573static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1574 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1575 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1576
1577 { "DSP1CLK", NULL, "CLK_SYS" },
1578 { "DSP2CLK", NULL, "CLK_SYS" },
1579 { "DSPINTCLK", NULL, "CLK_SYS" },
1580
1581 { "AIF1ADC1L", NULL, "AIF1CLK" },
1582 { "AIF1ADC1L", NULL, "DSP1CLK" },
1583 { "AIF1ADC1R", NULL, "AIF1CLK" },
1584 { "AIF1ADC1R", NULL, "DSP1CLK" },
1585 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1586
1587 { "AIF1DAC1L", NULL, "AIF1CLK" },
1588 { "AIF1DAC1L", NULL, "DSP1CLK" },
1589 { "AIF1DAC1R", NULL, "AIF1CLK" },
1590 { "AIF1DAC1R", NULL, "DSP1CLK" },
1591 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1592
1593 { "AIF1ADC2L", NULL, "AIF1CLK" },
1594 { "AIF1ADC2L", NULL, "DSP1CLK" },
1595 { "AIF1ADC2R", NULL, "AIF1CLK" },
1596 { "AIF1ADC2R", NULL, "DSP1CLK" },
1597 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1598
1599 { "AIF1DAC2L", NULL, "AIF1CLK" },
1600 { "AIF1DAC2L", NULL, "DSP1CLK" },
1601 { "AIF1DAC2R", NULL, "AIF1CLK" },
1602 { "AIF1DAC2R", NULL, "DSP1CLK" },
1603 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1604
1605 { "AIF2ADCL", NULL, "AIF2CLK" },
1606 { "AIF2ADCL", NULL, "DSP2CLK" },
1607 { "AIF2ADCR", NULL, "AIF2CLK" },
1608 { "AIF2ADCR", NULL, "DSP2CLK" },
1609 { "AIF2ADCR", NULL, "DSPINTCLK" },
1610
1611 { "AIF2DACL", NULL, "AIF2CLK" },
1612 { "AIF2DACL", NULL, "DSP2CLK" },
1613 { "AIF2DACR", NULL, "AIF2CLK" },
1614 { "AIF2DACR", NULL, "DSP2CLK" },
1615 { "AIF2DACR", NULL, "DSPINTCLK" },
1616
1617 { "DMIC1L", NULL, "DMIC1DAT" },
1618 { "DMIC1L", NULL, "CLK_SYS" },
1619 { "DMIC1R", NULL, "DMIC1DAT" },
1620 { "DMIC1R", NULL, "CLK_SYS" },
1621 { "DMIC2L", NULL, "DMIC2DAT" },
1622 { "DMIC2L", NULL, "CLK_SYS" },
1623 { "DMIC2R", NULL, "DMIC2DAT" },
1624 { "DMIC2R", NULL, "CLK_SYS" },
1625
1626 { "ADCL", NULL, "AIF1CLK" },
1627 { "ADCL", NULL, "DSP1CLK" },
1628 { "ADCL", NULL, "DSPINTCLK" },
1629
1630 { "ADCR", NULL, "AIF1CLK" },
1631 { "ADCR", NULL, "DSP1CLK" },
1632 { "ADCR", NULL, "DSPINTCLK" },
1633
1634 { "ADCL Mux", "ADC", "ADCL" },
1635 { "ADCL Mux", "DMIC", "DMIC1L" },
1636 { "ADCR Mux", "ADC", "ADCR" },
1637 { "ADCR Mux", "DMIC", "DMIC1R" },
1638
1639 { "DAC1L", NULL, "AIF1CLK" },
1640 { "DAC1L", NULL, "DSP1CLK" },
1641 { "DAC1L", NULL, "DSPINTCLK" },
1642
1643 { "DAC1R", NULL, "AIF1CLK" },
1644 { "DAC1R", NULL, "DSP1CLK" },
1645 { "DAC1R", NULL, "DSPINTCLK" },
1646
1647 { "DAC2L", NULL, "AIF2CLK" },
1648 { "DAC2L", NULL, "DSP2CLK" },
1649 { "DAC2L", NULL, "DSPINTCLK" },
1650
1651 { "DAC2R", NULL, "AIF2DACR" },
1652 { "DAC2R", NULL, "AIF2CLK" },
1653 { "DAC2R", NULL, "DSP2CLK" },
1654 { "DAC2R", NULL, "DSPINTCLK" },
1655
1656 { "TOCLK", NULL, "CLK_SYS" },
1657
5567d8c6
MB		 1658 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1659 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1660 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1661
1662 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1663 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1664 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1665
9e6e96a1
MB		 1666 /* AIF1 outputs */
1667 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1668 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1669 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1670
1671 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1672 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1673 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1674
a3257ba8
MB		 1675 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1676 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1677 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1678
1679 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1680 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1681 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1682
9e6e96a1
MB		 1683 /* Pin level routing for AIF3 */
1684 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1685 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1686 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1687 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1688
9e6e96a1
MB		 1689 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1690 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1691 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1692 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1693 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1694 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1695 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1696
1697 /* DAC1 inputs */
9e6e96a1
MB		 1698 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1699 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1700 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1701 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1702 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1703
9e6e96a1
MB		 1704 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1705 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1706 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1707 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1708 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1709
1710 /* DAC2/AIF2 outputs */
1711 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1712 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1713 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1714 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1715 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1716 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1717
1718 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1719 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1720 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1721 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1722 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1723 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1724
7f94de48
MB		 1725 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1726 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1727 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1728 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1729
9e6e96a1
MB		 1730 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1731
1732 /* AIF3 output */
1733 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1734 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1735 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1736 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1737 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1738 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1739 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1740 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1741
1742 /* Sidetone */
1743 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1744 { "Left Sidetone", "DMIC2", "DMIC2L" },
1745 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1746 { "Right Sidetone", "DMIC2", "DMIC2R" },
1747
1748 /* Output stages */
1749 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1750 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1751
1752 { "SPKL", "DAC1 Switch", "DAC1L" },
1753 { "SPKL", "DAC2 Switch", "DAC2L" },
1754
1755 { "SPKR", "DAC1 Switch", "DAC1R" },
1756 { "SPKR", "DAC2 Switch", "DAC2R" },
1757
1758 { "Left Headphone Mux", "DAC", "DAC1L" },
1759 { "Right Headphone Mux", "DAC", "DAC1R" },
1760};
1761
173efa09
DP		 1762static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1763 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1764 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1765 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1766 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1767 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1768 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1769 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1770 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1771};
1772
1773static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1774 { "DAC1L", NULL, "DAC1L Mixer" },
1775 { "DAC1R", NULL, "DAC1R Mixer" },
1776 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1777 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1778};
1779
6ed8f148
MB		 1780static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1781 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1782 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1783 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1784 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b793eb60
MB		 1785 { "MICBIAS1", NULL, "CLK_SYS" },
1786 { "MICBIAS1", NULL, "MICBIAS Supply" },
1787 { "MICBIAS2", NULL, "CLK_SYS" },
1788 { "MICBIAS2", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1789};
1790
c4431df0
MB		 1791static const struct snd_soc_dapm_route wm8994_intercon[] = {
1792 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1793 { "AIF2DACR", NULL, "AIF2DAC Mux" },
4e04adaf
MB		 1794 { "MICBIAS1", NULL, "VMID" },
1795 { "MICBIAS2", NULL, "VMID" },
c4431df0
MB		 1796};
1797
1798static const struct snd_soc_dapm_route wm8958_intercon[] = {
1799 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1800 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1801
1802 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1803 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1804 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1805 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1806
1807 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1808 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1809
1810 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1811};
1812
9e6e96a1
MB		 1813/* The size in bits of the FLL divide multiplied by 10
1814 * to allow rounding later */
1815#define FIXED_FLL_SIZE ((1 << 16) * 10)
1816
1817struct fll_div {
1818 u16 outdiv;
1819 u16 n;
1820 u16 k;
1821 u16 clk_ref_div;
1822 u16 fll_fratio;
1823};
1824
1825static int wm8994_get_fll_config(struct fll_div *fll,
1826 int freq_in, int freq_out)
1827{
1828 u64 Kpart;
1829 unsigned int K, Ndiv, Nmod;
1830
1831 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1832
1833 /* Scale the input frequency down to <= 13.5MHz */
1834 fll->clk_ref_div = 0;
1835 while (freq_in > 13500000) {
1836 fll->clk_ref_div++;
1837 freq_in /= 2;
1838
1839 if (fll->clk_ref_div > 3)
1840 return -EINVAL;
1841 }
1842 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1843
1844 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1845 fll->outdiv = 3;
1846 while (freq_out * (fll->outdiv + 1) < 90000000) {
1847 fll->outdiv++;
1848 if (fll->outdiv > 63)
1849 return -EINVAL;
1850 }
1851 freq_out *= fll->outdiv + 1;
1852 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1853
1854 if (freq_in > 1000000) {
1855 fll->fll_fratio = 0;
7d48a6ac
MB		 1856 } else if (freq_in > 256000) {
1857 fll->fll_fratio = 1;
1858 freq_in *= 2;
1859 } else if (freq_in > 128000) {
1860 fll->fll_fratio = 2;
1861 freq_in *= 4;
1862 } else if (freq_in > 64000) {
9e6e96a1
MB		 1863 fll->fll_fratio = 3;
1864 freq_in *= 8;
7d48a6ac
MB		 1865 } else {
1866 fll->fll_fratio = 4;
1867 freq_in *= 16;
9e6e96a1
MB		 1868 }
1869 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1870
1871 /* Now, calculate N.K */
1872 Ndiv = freq_out / freq_in;
1873
1874 fll->n = Ndiv;
1875 Nmod = freq_out % freq_in;
1876 pr_debug("Nmod=%d\n", Nmod);
1877
1878 /* Calculate fractional part - scale up so we can round. */
1879 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1880
1881 do_div(Kpart, freq_in);
1882
1883 K = Kpart & 0xFFFFFFFF;
1884
1885 if ((K % 10) >= 5)
1886 K += 5;
1887
1888 /* Move down to proper range now rounding is done */
1889 fll->k = K / 10;
1890
1891 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1892
1893 return 0;
1894}
1895
f0fba2ad 1896static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1897 unsigned int freq_in, unsigned int freq_out)
1898{
b2c812e2 1899 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 1900 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 1901 int reg_offset, ret;
1902 struct fll_div fll;
1903 u16 reg, aif1, aif2;
c7ebf932 1904 unsigned long timeout;
4b7ed83a 1905 bool was_enabled;
9e6e96a1
MB		 1906
1907 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1908 & WM8994_AIF1CLK_ENA;
1909
1910 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1911 & WM8994_AIF2CLK_ENA;
1912
1913 switch (id) {
1914 case WM8994_FLL1:
1915 reg_offset = 0;
1916 id = 0;
1917 break;
1918 case WM8994_FLL2:
1919 reg_offset = 0x20;
1920 id = 1;
1921 break;
1922 default:
1923 return -EINVAL;
1924 }
1925
4b7ed83a
MB		 1926 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
1927 was_enabled = reg & WM8994_FLL1_ENA;
1928
136ff2a2 1929 switch (src) {
7add84aa
MB		 1930 case 0:
1931 /* Allow no source specification when stopping */
1932 if (freq_out)
1933 return -EINVAL;
4514e899 1934 src = wm8994->fll[id].src;
7add84aa 1935 break;
136ff2a2
MB		 1936 case WM8994_FLL_SRC_MCLK1:
1937 case WM8994_FLL_SRC_MCLK2:
1938 case WM8994_FLL_SRC_LRCLK:
1939 case WM8994_FLL_SRC_BCLK:
1940 break;
1941 default:
1942 return -EINVAL;
1943 }
1944
9e6e96a1
MB		 1945 /* Are we changing anything? */
1946 if (wm8994->fll[id].src == src &&
1947 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1948 return 0;
1949
1950 /* If we're stopping the FLL redo the old config - no
1951 * registers will actually be written but we avoid GCC flow
1952 * analysis bugs spewing warnings.
1953 */
1954 if (freq_out)
1955 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1956 else
1957 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1958 wm8994->fll[id].out);
1959 if (ret < 0)
1960 return ret;
1961
1962 /* Gate the AIF clocks while we reclock */
1963 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1964 WM8994_AIF1CLK_ENA, 0);
1965 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1966 WM8994_AIF2CLK_ENA, 0);
1967
1968 /* We always need to disable the FLL while reconfiguring */
1969 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1970 WM8994_FLL1_ENA, 0);
1971
1972 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1973 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1974 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1975 WM8994_FLL1_OUTDIV_MASK |
1976 WM8994_FLL1_FRATIO_MASK, reg);
1977
b16db745
MB		 1978 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
1979 WM8994_FLL1_K_MASK, fll.k);
9e6e96a1
MB		 1980
1981 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1982 WM8994_FLL1_N_MASK,
1983 fll.n << WM8994_FLL1_N_SHIFT);
1984
1985 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1986 WM8994_FLL1_REFCLK_DIV_MASK |
1987 WM8994_FLL1_REFCLK_SRC_MASK,
1988 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1989 (src - 1));
9e6e96a1 1990
f0f5039c
MB		 1991 /* Clear any pending completion from a previous failure */
1992 try_wait_for_completion(&wm8994->fll_locked[id]);
1993
9e6e96a1
MB		 1994 /* Enable (with fractional mode if required) */
1995 if (freq_out) {
4b7ed83a
MB		 1996 /* Enable VMID if we need it */
1997 if (!was_enabled) {
af6b6fe4
MB		 1998 active_reference(codec);
1999
4b7ed83a
MB		 2000 switch (control->type) {
2001 case WM8994:
2002 vmid_reference(codec);
2003 break;
2004 case WM8958:
2005 if (wm8994->revision < 1)
2006 vmid_reference(codec);
2007 break;
2008 default:
2009 break;
2010 }
2011 }
2012
9e6e96a1
MB		 2013 if (fll.k)
2014 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
2015 else
2016 reg = WM8994_FLL1_ENA;
2017 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2018 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
2019 reg);
8e9ddf81 2020
c7ebf932
MB		 2021 if (wm8994->fll_locked_irq) {
2022 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2023 msecs_to_jiffies(10));
2024 if (timeout == 0)
2025 dev_warn(codec->dev,
2026 "Timed out waiting for FLL lock\n");
2027 } else {
2028 msleep(5);
2029 }
4b7ed83a
MB		 2030 } else {
2031 if (was_enabled) {
2032 switch (control->type) {
2033 case WM8994:
2034 vmid_dereference(codec);
2035 break;
2036 case WM8958:
2037 if (wm8994->revision < 1)
2038 vmid_dereference(codec);
2039 break;
2040 default:
2041 break;
2042 }
af6b6fe4
MB		 2043
2044 active_dereference(codec);
4b7ed83a 2045 }
9e6e96a1
MB		 2046 }
2047
2048 wm8994->fll[id].in = freq_in;
2049 wm8994->fll[id].out = freq_out;
136ff2a2 2050 wm8994->fll[id].src = src;
9e6e96a1
MB		 2051
2052 /* Enable any gated AIF clocks */
2053 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
2054 WM8994_AIF1CLK_ENA, aif1);
2055 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
2056 WM8994_AIF2CLK_ENA, aif2);
2057
2058 configure_clock(codec);
2059
2060 return 0;
2061}
2062
c7ebf932
MB		 2063static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2064{
2065 struct completion *completion = data;
2066
2067 complete(completion);
2068
2069 return IRQ_HANDLED;
2070}
f0fba2ad 2071
66b47fdb
MB		 2072static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2073
f0fba2ad
LG		 2074static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2075 unsigned int freq_in, unsigned int freq_out)
2076{
2077 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2078}
2079
9e6e96a1
MB		 2080static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2081 int clk_id, unsigned int freq, int dir)
2082{
2083 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2084 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 2085 int i;
9e6e96a1
MB		 2086
2087 switch (dai->id) {
2088 case 1:
2089 case 2:
2090 break;
2091
2092 default:
2093 /* AIF3 shares clocking with AIF1/2 */
2094 return -EINVAL;
2095 }
2096
2097 switch (clk_id) {
2098 case WM8994_SYSCLK_MCLK1:
2099 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2100 wm8994->mclk[0] = freq;
2101 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2102 dai->id, freq);
2103 break;
2104
2105 case WM8994_SYSCLK_MCLK2:
2106 /* TODO: Set GPIO AF */
2107 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2108 wm8994->mclk[1] = freq;
2109 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2110 dai->id, freq);
2111 break;
2112
2113 case WM8994_SYSCLK_FLL1:
2114 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2115 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2116 break;
2117
2118 case WM8994_SYSCLK_FLL2:
2119 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2120 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2121 break;
2122
66b47fdb
MB		 2123 case WM8994_SYSCLK_OPCLK:
2124 /* Special case - a division (times 10) is given and
2125 * no effect on main clocking.
2126 */
2127 if (freq) {
2128 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2129 if (opclk_divs[i] == freq)
2130 break;
2131 if (i == ARRAY_SIZE(opclk_divs))
2132 return -EINVAL;
2133 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2134 WM8994_OPCLK_DIV_MASK, i);
2135 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2136 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2137 } else {
2138 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2139 WM8994_OPCLK_ENA, 0);
2140 }
2141
9e6e96a1
MB		 2142 default:
2143 return -EINVAL;
2144 }
2145
2146 configure_clock(codec);
2147
2148 return 0;
2149}
2150
2151static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2152 enum snd_soc_bias_level level)
2153{
b6b05691 2154 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2155 struct wm8994 *control = wm8994->wm8994;
b6b05691 2156
5f2f3890
MB		 2157 wm_hubs_set_bias_level(codec, level);
2158
9e6e96a1
MB		 2159 switch (level) {
2160 case SND_SOC_BIAS_ON:
2161 break;
2162
2163 case SND_SOC_BIAS_PREPARE:
500fa30e
MB		 2164 /* MICBIAS into regulating mode */
2165 switch (control->type) {
2166 case WM8958:
2167 case WM1811:
2168 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2169 WM8958_MICB1_MODE, 0);
2170 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2171 WM8958_MICB2_MODE, 0);
2172 break;
2173 default:
2174 break;
2175 }
af6b6fe4
MB		 2176
2177 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2178 active_reference(codec);
9e6e96a1
MB		 2179 break;
2180
2181 case SND_SOC_BIAS_STANDBY:
ce6120cc 2182 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8bc3c2c2 2183 switch (control->type) {
8bc3c2c2
MB		 2184 case WM8958:
2185 if (wm8994->revision == 0) {
2186 /* Optimise performance for rev A */
8bc3c2c2
MB		 2187 snd_soc_update_bits(codec,
2188 WM8958_CHARGE_PUMP_2,
2189 WM8958_CP_DISCH,
2190 WM8958_CP_DISCH);
2191 }
2192 break;
81204c84 2193
462835e4 2194 default:
81204c84 2195 break;
b6b05691 2196 }
9e6e96a1
MB		 2197
2198 /* Discharge LINEOUT1 & 2 */
2199 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2200 WM8994_LINEOUT1_DISCH |
2201 WM8994_LINEOUT2_DISCH,
2202 WM8994_LINEOUT1_DISCH |
2203 WM8994_LINEOUT2_DISCH);
9e6e96a1
MB		 2204 }
2205
af6b6fe4
MB		 2206 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2207 active_dereference(codec);
2208
500fa30e
MB		 2209 /* MICBIAS into bypass mode on newer devices */
2210 switch (control->type) {
2211 case WM8958:
2212 case WM1811:
2213 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2214 WM8958_MICB1_MODE,
2215 WM8958_MICB1_MODE);
2216 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2217 WM8958_MICB2_MODE,
2218 WM8958_MICB2_MODE);
2219 break;
2220 default:
2221 break;
2222 }
9e6e96a1
MB		 2223 break;
2224
2225 case SND_SOC_BIAS_OFF:
4105ab84 2226 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
fbbf5920 2227 wm8994->cur_fw = NULL;
9e6e96a1
MB		 2228 break;
2229 }
5f2f3890 2230
ce6120cc 2231 codec->dapm.bias_level = level;
af6b6fe4 2232
22f8d055
MB		 2233 return 0;
2234}
2235
2236int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2237{
2238 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2239
2240 switch (mode) {
2241 case WM8994_VMID_NORMAL:
2242 if (wm8994->hubs.lineout1_se) {
2243 snd_soc_dapm_disable_pin(&codec->dapm,
2244 "LINEOUT1N Driver");
2245 snd_soc_dapm_disable_pin(&codec->dapm,
2246 "LINEOUT1P Driver");
2247 }
2248 if (wm8994->hubs.lineout2_se) {
2249 snd_soc_dapm_disable_pin(&codec->dapm,
2250 "LINEOUT2N Driver");
2251 snd_soc_dapm_disable_pin(&codec->dapm,
2252 "LINEOUT2P Driver");
2253 }
2254
2255 /* Do the sync with the old mode to allow it to clean up */
2256 snd_soc_dapm_sync(&codec->dapm);
2257 wm8994->vmid_mode = mode;
2258 break;
2259
2260 case WM8994_VMID_FORCE:
2261 if (wm8994->hubs.lineout1_se) {
2262 snd_soc_dapm_force_enable_pin(&codec->dapm,
2263 "LINEOUT1N Driver");
2264 snd_soc_dapm_force_enable_pin(&codec->dapm,
2265 "LINEOUT1P Driver");
2266 }
2267 if (wm8994->hubs.lineout2_se) {
2268 snd_soc_dapm_force_enable_pin(&codec->dapm,
2269 "LINEOUT2N Driver");
2270 snd_soc_dapm_force_enable_pin(&codec->dapm,
2271 "LINEOUT2P Driver");
2272 }
2273
2274 wm8994->vmid_mode = mode;
2275 snd_soc_dapm_sync(&codec->dapm);
2276 break;
2277
2278 default:
2279 return -EINVAL;
2280 }
2281
9e6e96a1
MB		 2282 return 0;
2283}
2284
2285static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2286{
2287 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2288 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2289 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2290 int ms_reg;
2291 int aif1_reg;
2292 int ms = 0;
2293 int aif1 = 0;
2294
2295 switch (dai->id) {
2296 case 1:
2297 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2298 aif1_reg = WM8994_AIF1_CONTROL_1;
2299 break;
2300 case 2:
2301 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2302 aif1_reg = WM8994_AIF2_CONTROL_1;
2303 break;
2304 default:
2305 return -EINVAL;
2306 }
2307
2308 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2309 case SND_SOC_DAIFMT_CBS_CFS:
2310 break;
2311 case SND_SOC_DAIFMT_CBM_CFM:
2312 ms = WM8994_AIF1_MSTR;
2313 break;
2314 default:
2315 return -EINVAL;
2316 }
2317
2318 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2319 case SND_SOC_DAIFMT_DSP_B:
2320 aif1 |= WM8994_AIF1_LRCLK_INV;
2321 case SND_SOC_DAIFMT_DSP_A:
2322 aif1 |= 0x18;
2323 break;
2324 case SND_SOC_DAIFMT_I2S:
2325 aif1 |= 0x10;
2326 break;
2327 case SND_SOC_DAIFMT_RIGHT_J:
2328 break;
2329 case SND_SOC_DAIFMT_LEFT_J:
2330 aif1 |= 0x8;
2331 break;
2332 default:
2333 return -EINVAL;
2334 }
2335
2336 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2337 case SND_SOC_DAIFMT_DSP_A:
2338 case SND_SOC_DAIFMT_DSP_B:
2339 /* frame inversion not valid for DSP modes */
2340 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2341 case SND_SOC_DAIFMT_NB_NF:
2342 break;
2343 case SND_SOC_DAIFMT_IB_NF:
2344 aif1 |= WM8994_AIF1_BCLK_INV;
2345 break;
2346 default:
2347 return -EINVAL;
2348 }
2349 break;
2350
2351 case SND_SOC_DAIFMT_I2S:
2352 case SND_SOC_DAIFMT_RIGHT_J:
2353 case SND_SOC_DAIFMT_LEFT_J:
2354 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2355 case SND_SOC_DAIFMT_NB_NF:
2356 break;
2357 case SND_SOC_DAIFMT_IB_IF:
2358 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2359 break;
2360 case SND_SOC_DAIFMT_IB_NF:
2361 aif1 |= WM8994_AIF1_BCLK_INV;
2362 break;
2363 case SND_SOC_DAIFMT_NB_IF:
2364 aif1 |= WM8994_AIF1_LRCLK_INV;
2365 break;
2366 default:
2367 return -EINVAL;
2368 }
2369 break;
2370 default:
2371 return -EINVAL;
2372 }
2373
c4431df0
MB		 2374 /* The AIF2 format configuration needs to be mirrored to AIF3
2375 * on WM8958 if it's in use so just do it all the time. */
81204c84
MB		 2376 switch (control->type) {
2377 case WM1811:
2378 case WM8958:
2379 if (dai->id == 2)
2380 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2381 WM8994_AIF1_LRCLK_INV |
2382 WM8958_AIF3_FMT_MASK, aif1);
2383 break;
2384
2385 default:
2386 break;
2387 }
c4431df0 2388
9e6e96a1
MB		 2389 snd_soc_update_bits(codec, aif1_reg,
2390 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2391 WM8994_AIF1_FMT_MASK,
2392 aif1);
2393 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2394 ms);
2395
2396 return 0;
2397}
2398
2399static struct {
2400 int val, rate;
2401} srs[] = {
2402 { 0, 8000 },
2403 { 1, 11025 },
2404 { 2, 12000 },
2405 { 3, 16000 },
2406 { 4, 22050 },
2407 { 5, 24000 },
2408 { 6, 32000 },
2409 { 7, 44100 },
2410 { 8, 48000 },
2411 { 9, 88200 },
2412 { 10, 96000 },
2413};
2414
2415static int fs_ratios[] = {
2416 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2417};
2418
2419static int bclk_divs[] = {
2420 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2421 640, 880, 960, 1280, 1760, 1920
2422};
2423
2424static int wm8994_hw_params(struct snd_pcm_substream *substream,
2425 struct snd_pcm_hw_params *params,
2426 struct snd_soc_dai *dai)
2427{
2428 struct snd_soc_codec *codec = dai->codec;
b2c812e2 2429 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2430 int aif1_reg;
b1e43d93 2431 int aif2_reg;
9e6e96a1
MB		 2432 int bclk_reg;
2433 int lrclk_reg;
2434 int rate_reg;
2435 int aif1 = 0;
b1e43d93 2436 int aif2 = 0;
9e6e96a1
MB		 2437 int bclk = 0;
2438 int lrclk = 0;
2439 int rate_val = 0;
2440 int id = dai->id - 1;
2441
2442 int i, cur_val, best_val, bclk_rate, best;
2443
2444 switch (dai->id) {
2445 case 1:
2446 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2447 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2448 bclk_reg = WM8994_AIF1_BCLK;
2449 rate_reg = WM8994_AIF1_RATE;
2450 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2451 wm8994->lrclk_shared[0]) {
9e6e96a1 2452 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2453 } else {
9e6e96a1 2454 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2455 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2456 }
9e6e96a1
MB		 2457 break;
2458 case 2:
2459 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2460 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2461 bclk_reg = WM8994_AIF2_BCLK;
2462 rate_reg = WM8994_AIF2_RATE;
2463 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2464 wm8994->lrclk_shared[1]) {
9e6e96a1 2465 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2466 } else {
9e6e96a1 2467 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2468 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2469 }
9e6e96a1
MB		 2470 break;
2471 default:
2472 return -EINVAL;
2473 }
2474
2475 bclk_rate = params_rate(params) * 2;
2476 switch (params_format(params)) {
2477 case SNDRV_PCM_FORMAT_S16_LE:
2478 bclk_rate *= 16;
2479 break;
2480 case SNDRV_PCM_FORMAT_S20_3LE:
2481 bclk_rate *= 20;
2482 aif1 |= 0x20;
2483 break;
2484 case SNDRV_PCM_FORMAT_S24_LE:
2485 bclk_rate *= 24;
2486 aif1 |= 0x40;
2487 break;
2488 case SNDRV_PCM_FORMAT_S32_LE:
2489 bclk_rate *= 32;
2490 aif1 |= 0x60;
2491 break;
2492 default:
2493 return -EINVAL;
2494 }
2495
2496 /* Try to find an appropriate sample rate; look for an exact match. */
2497 for (i = 0; i < ARRAY_SIZE(srs); i++)
2498 if (srs[i].rate == params_rate(params))
2499 break;
2500 if (i == ARRAY_SIZE(srs))
2501 return -EINVAL;
2502 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2503
2504 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2505 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2506 dai->id, wm8994->aifclk[id], bclk_rate);
2507
b1e43d93
MB		 2508 if (params_channels(params) == 1 &&
2509 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2510 aif2 |= WM8994_AIF1_MONO;
2511
9e6e96a1
MB		 2512 if (wm8994->aifclk[id] == 0) {
2513 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2514 return -EINVAL;
2515 }
2516
2517 /* AIFCLK/fs ratio; look for a close match in either direction */
2518 best = 0;
2519 best_val = abs((fs_ratios[0] * params_rate(params))
2520 - wm8994->aifclk[id]);
2521 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2522 cur_val = abs((fs_ratios[i] * params_rate(params))
2523 - wm8994->aifclk[id]);
2524 if (cur_val >= best_val)
2525 continue;
2526 best = i;
2527 best_val = cur_val;
2528 }
2529 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2530 dai->id, fs_ratios[best]);
2531 rate_val |= best;
2532
2533 /* We may not get quite the right frequency if using
2534 * approximate clocks so look for the closest match that is
2535 * higher than the target (we need to ensure that there enough
2536 * BCLKs to clock out the samples).
2537 */
2538 best = 0;
2539 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2540 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2541 if (cur_val < 0) /* BCLK table is sorted */
2542 break;
2543 best = i;
2544 }
07cd8ada 2545 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2546 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2547 bclk_divs[best], bclk_rate);
2548 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2549
2550 lrclk = bclk_rate / params_rate(params);
fc07ecd8
MB		 2551 if (!lrclk) {
2552 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2553 bclk_rate);
2554 return -EINVAL;
2555 }
9e6e96a1
MB		 2556 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2557 lrclk, bclk_rate / lrclk);
2558
2559 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2560 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2561 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2562 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2563 lrclk);
2564 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2565 WM8994_AIF1CLK_RATE_MASK, rate_val);
2566
2567 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2568 switch (dai->id) {
2569 case 1:
2570 wm8994->dac_rates[0] = params_rate(params);
2571 wm8994_set_retune_mobile(codec, 0);
2572 wm8994_set_retune_mobile(codec, 1);
2573 break;
2574 case 2:
2575 wm8994->dac_rates[1] = params_rate(params);
2576 wm8994_set_retune_mobile(codec, 2);
2577 break;
2578 }
2579 }
2580
2581 return 0;
2582}
2583
c4431df0
MB		 2584static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2585 struct snd_pcm_hw_params *params,
2586 struct snd_soc_dai *dai)
2587{
2588 struct snd_soc_codec *codec = dai->codec;
2a8a856d
MB		 2589 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2590 struct wm8994 *control = wm8994->wm8994;
c4431df0
MB		 2591 int aif1_reg;
2592 int aif1 = 0;
2593
2594 switch (dai->id) {
2595 case 3:
2596 switch (control->type) {
81204c84 2597 case WM1811:
c4431df0
MB		 2598 case WM8958:
2599 aif1_reg = WM8958_AIF3_CONTROL_1;
2600 break;
2601 default:
2602 return 0;
2603 }
2604 default:
2605 return 0;
2606 }
2607
2608 switch (params_format(params)) {
2609 case SNDRV_PCM_FORMAT_S16_LE:
2610 break;
2611 case SNDRV_PCM_FORMAT_S20_3LE:
2612 aif1 |= 0x20;
2613 break;
2614 case SNDRV_PCM_FORMAT_S24_LE:
2615 aif1 |= 0x40;
2616 break;
2617 case SNDRV_PCM_FORMAT_S32_LE:
2618 aif1 |= 0x60;
2619 break;
2620 default:
2621 return -EINVAL;
2622 }
2623
2624 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2625}
2626
7d02173c
MB		 2627static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2628 struct snd_soc_dai *dai)
2629{
2630 struct snd_soc_codec *codec = dai->codec;
2631 int rate_reg = 0;
2632
2633 switch (dai->id) {
2634 case 1:
2635 rate_reg = WM8994_AIF1_RATE;
2636 break;
2637 case 2:
c527e6aa 2638 rate_reg = WM8994_AIF2_RATE;
7d02173c
MB		 2639 break;
2640 default:
2641 break;
2642 }
2643
2644 /* If the DAI is idle then configure the divider tree for the
2645 * lowest output rate to save a little power if the clock is
2646 * still active (eg, because it is system clock).
2647 */
2648 if (rate_reg && !dai->playback_active && !dai->capture_active)
2649 snd_soc_update_bits(codec, rate_reg,
2650 WM8994_AIF1_SR_MASK |
2651 WM8994_AIF1CLK_RATE_MASK, 0x9);
2652}
2653
9e6e96a1
MB		 2654static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2655{
2656 struct snd_soc_codec *codec = codec_dai->codec;
2657 int mute_reg;
2658 int reg;
2659
2660 switch (codec_dai->id) {
2661 case 1:
2662 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2663 break;
2664 case 2:
2665 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2666 break;
2667 default:
2668 return -EINVAL;
2669 }
2670
2671 if (mute)
2672 reg = WM8994_AIF1DAC1_MUTE;
2673 else
2674 reg = 0;
2675
2676 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2677
2678 return 0;
2679}
2680
778a76e2
MB		 2681static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2682{
2683 struct snd_soc_codec *codec = codec_dai->codec;
2684 int reg, val, mask;
2685
2686 switch (codec_dai->id) {
2687 case 1:
2688 reg = WM8994_AIF1_MASTER_SLAVE;
2689 mask = WM8994_AIF1_TRI;
2690 break;
2691 case 2:
2692 reg = WM8994_AIF2_MASTER_SLAVE;
2693 mask = WM8994_AIF2_TRI;
2694 break;
2695 case 3:
2696 reg = WM8994_POWER_MANAGEMENT_6;
2697 mask = WM8994_AIF3_TRI;
2698 break;
2699 default:
2700 return -EINVAL;
2701 }
2702
2703 if (tristate)
2704 val = mask;
2705 else
2706 val = 0;
2707
78b3fb46 2708 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2709}
2710
d09f3ecf
MB		 2711static int wm8994_aif2_probe(struct snd_soc_dai *dai)
2712{
2713 struct snd_soc_codec *codec = dai->codec;
2714
2715 /* Disable the pulls on the AIF if we're using it to save power. */
2716 snd_soc_update_bits(codec, WM8994_GPIO_3,
2717 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2718 snd_soc_update_bits(codec, WM8994_GPIO_4,
2719 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2720 snd_soc_update_bits(codec, WM8994_GPIO_5,
2721 WM8994_GPN_PU | WM8994_GPN_PD, 0);
2722
2723 return 0;
2724}
2725
9e6e96a1
MB		 2726#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2727
2728#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2729 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1 2730
85e7652d 2731static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
9e6e96a1
MB		 2732 .set_sysclk = wm8994_set_dai_sysclk,
2733 .set_fmt = wm8994_set_dai_fmt,
2734 .hw_params = wm8994_hw_params,
7d02173c 2735 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2736 .digital_mute = wm8994_aif_mute,
2737 .set_pll = wm8994_set_fll,
778a76e2 2738 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2739};
2740
85e7652d 2741static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
9e6e96a1
MB		 2742 .set_sysclk = wm8994_set_dai_sysclk,
2743 .set_fmt = wm8994_set_dai_fmt,
2744 .hw_params = wm8994_hw_params,
7d02173c 2745 .shutdown = wm8994_aif_shutdown,
9e6e96a1
MB		 2746 .digital_mute = wm8994_aif_mute,
2747 .set_pll = wm8994_set_fll,
778a76e2
MB		 2748 .set_tristate = wm8994_set_tristate,
2749};
2750
85e7652d 2751static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2752 .hw_params = wm8994_aif3_hw_params,
778a76e2 2753 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2754};
2755
f0fba2ad 2756static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2757 {
f0fba2ad 2758 .name = "wm8994-aif1",
8c7f78b3 2759 .id = 1,
9e6e96a1
MB		 2760 .playback = {
2761 .stream_name = "AIF1 Playback",
b1e43d93 2762 .channels_min = 1,
9e6e96a1
MB		 2763 .channels_max = 2,
2764 .rates = WM8994_RATES,
2765 .formats = WM8994_FORMATS,
99b0292d 2766 .sig_bits = 24,
9e6e96a1
MB		 2767 },
2768 .capture = {
2769 .stream_name = "AIF1 Capture",
b1e43d93 2770 .channels_min = 1,
9e6e96a1
MB		 2771 .channels_max = 2,
2772 .rates = WM8994_RATES,
2773 .formats = WM8994_FORMATS,
99b0292d 2774 .sig_bits = 24,
9e6e96a1
MB		 2775 },
2776 .ops = &wm8994_aif1_dai_ops,
2777 },
2778 {
f0fba2ad 2779 .name = "wm8994-aif2",
8c7f78b3 2780 .id = 2,
9e6e96a1
MB		 2781 .playback = {
2782 .stream_name = "AIF2 Playback",
b1e43d93 2783 .channels_min = 1,
9e6e96a1
MB		 2784 .channels_max = 2,
2785 .rates = WM8994_RATES,
2786 .formats = WM8994_FORMATS,
99b0292d 2787 .sig_bits = 24,
9e6e96a1
MB		 2788 },
2789 .capture = {
2790 .stream_name = "AIF2 Capture",
b1e43d93 2791 .channels_min = 1,
9e6e96a1
MB		 2792 .channels_max = 2,
2793 .rates = WM8994_RATES,
2794 .formats = WM8994_FORMATS,
99b0292d 2795 .sig_bits = 24,
9e6e96a1 2796 },
d09f3ecf 2797 .probe = wm8994_aif2_probe,
9e6e96a1
MB		 2798 .ops = &wm8994_aif2_dai_ops,
2799 },
2800 {
f0fba2ad 2801 .name = "wm8994-aif3",
8c7f78b3 2802 .id = 3,
9e6e96a1
MB		 2803 .playback = {
2804 .stream_name = "AIF3 Playback",
b1e43d93 2805 .channels_min = 1,
9e6e96a1
MB		 2806 .channels_max = 2,
2807 .rates = WM8994_RATES,
2808 .formats = WM8994_FORMATS,
99b0292d 2809 .sig_bits = 24,
9e6e96a1 2810 },
a8462bde 2811 .capture = {
9e6e96a1 2812 .stream_name = "AIF3 Capture",
b1e43d93 2813 .channels_min = 1,
9e6e96a1
MB		 2814 .channels_max = 2,
2815 .rates = WM8994_RATES,
2816 .formats = WM8994_FORMATS,
99b0292d
MB		 2817 .sig_bits = 24,
2818 },
778a76e2 2819 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2820 }
2821};
9e6e96a1
MB		 2822
2823#ifdef CONFIG_PM
4752a887 2824static int wm8994_codec_suspend(struct snd_soc_codec *codec)
9e6e96a1 2825{
b2c812e2 2826 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2827 struct wm8994 *control = wm8994->wm8994;
9e6e96a1
MB		 2828 int i, ret;
2829
ca629928
MB		 2830 switch (control->type) {
2831 case WM8994:
2832 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2833 break;
81204c84 2834 case WM1811:
af6b6fe4
MB		 2835 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2836 WM1811_JACKDET_MODE_MASK, 0);
2837 /* Fall through */
ca629928
MB		 2838 case WM8958:
2839 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2840 WM8958_MICD_ENA, 0);
2841 break;
2842 }
2843
9e6e96a1
MB		 2844 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2845 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2846 sizeof(struct wm8994_fll_config));
f0fba2ad 2847 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2848 if (ret < 0)
2849 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2850 i + 1, ret);
2851 }
2852
2853 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2854
2855 return 0;
2856}
2857
4752a887 2858static int wm8994_codec_resume(struct snd_soc_codec *codec)
9e6e96a1 2859{
b2c812e2 2860 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 2861 struct wm8994 *control = wm8994->wm8994;
9e6e96a1 2862 int i, ret;
c52fd021
DP		 2863 unsigned int val, mask;
2864
2865 if (wm8994->revision < 4) {
2866 /* force a HW read */
d9a7666f
MB		 2867 ret = regmap_read(control->regmap,
2868 WM8994_POWER_MANAGEMENT_5, &val);
c52fd021
DP		 2869
2870 /* modify the cache only */
2871 codec->cache_only = 1;
2872 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2873 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2874 val &= mask;
2875 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2876 mask, val);
2877 codec->cache_only = 0;
2878 }
9e6e96a1 2879
9e6e96a1 2880 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2881 if (!wm8994->fll_suspend[i].out)
2882 continue;
2883
f0fba2ad 2884 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2885 wm8994->fll_suspend[i].src,
2886 wm8994->fll_suspend[i].in,
2887 wm8994->fll_suspend[i].out);
2888 if (ret < 0)
2889 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2890 i + 1, ret);
2891 }
2892
ca629928
MB		 2893 switch (control->type) {
2894 case WM8994:
2895 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2896 snd_soc_update_bits(codec, WM8994_MICBIAS,
2897 WM8994_MICD_ENA, WM8994_MICD_ENA);
2898 break;
81204c84 2899 case WM1811:
af6b6fe4
MB		 2900 if (wm8994->jackdet && wm8994->jack_cb) {
2901 /* Restart from idle */
2902 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
2903 WM1811_JACKDET_MODE_MASK,
2904 WM1811_JACKDET_MODE_JACK);
2905 break;
2906 }
6f8270cc 2907 break;
ca629928
MB		 2908 case WM8958:
2909 if (wm8994->jack_cb)
2910 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2911 WM8958_MICD_ENA, WM8958_MICD_ENA);
2912 break;
2913 }
2914
9e6e96a1
MB		 2915 return 0;
2916}
2917#else
4752a887
MB		 2918#define wm8994_codec_suspend NULL
2919#define wm8994_codec_resume NULL
9e6e96a1
MB		 2920#endif
2921
2922static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2923{
f0fba2ad 2924 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2925 struct wm8994_pdata *pdata = wm8994->pdata;
2926 struct snd_kcontrol_new controls[] = {
2927 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2928 wm8994->retune_mobile_enum,
2929 wm8994_get_retune_mobile_enum,
2930 wm8994_put_retune_mobile_enum),
2931 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2932 wm8994->retune_mobile_enum,
2933 wm8994_get_retune_mobile_enum,
2934 wm8994_put_retune_mobile_enum),
2935 SOC_ENUM_EXT("AIF2 EQ Mode",
2936 wm8994->retune_mobile_enum,
2937 wm8994_get_retune_mobile_enum,
2938 wm8994_put_retune_mobile_enum),
2939 };
2940 int ret, i, j;
2941 const char **t;
2942
2943 /* We need an array of texts for the enum API but the number
2944 * of texts is likely to be less than the number of
2945 * configurations due to the sample rate dependency of the
2946 * configurations. */
2947 wm8994->num_retune_mobile_texts = 0;
2948 wm8994->retune_mobile_texts = NULL;
2949 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2950 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2951 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2952 wm8994->retune_mobile_texts[j]) == 0)
2953 break;
2954 }
2955
2956 if (j != wm8994->num_retune_mobile_texts)
2957 continue;
2958
2959 /* Expand the array... */
2960 t = krealloc(wm8994->retune_mobile_texts,
2961 sizeof(char *) *
2962 (wm8994->num_retune_mobile_texts + 1),
2963 GFP_KERNEL);
2964 if (t == NULL)
2965 continue;
2966
2967 /* ...store the new entry... */
2968 t[wm8994->num_retune_mobile_texts] =
2969 pdata->retune_mobile_cfgs[i].name;
2970
2971 /* ...and remember the new version. */
2972 wm8994->num_retune_mobile_texts++;
2973 wm8994->retune_mobile_texts = t;
2974 }
2975
2976 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2977 wm8994->num_retune_mobile_texts);
2978
2979 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2980 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2981
022658be 2982 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 2983 ARRAY_SIZE(controls));
2984 if (ret != 0)
f0fba2ad 2985 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2986 "Failed to add ReTune Mobile controls: %d\n", ret);
2987}
2988
2989static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2990{
f0fba2ad 2991 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2992 struct wm8994_pdata *pdata = wm8994->pdata;
2993 int ret, i;
2994
2995 if (!pdata)
2996 return;
2997
2998 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2999 pdata->lineout2_diff,
3000 pdata->lineout1fb,
3001 pdata->lineout2fb,
3002 pdata->jd_scthr,
3003 pdata->jd_thr,
3004 pdata->micbias1_lvl,
3005 pdata->micbias2_lvl);
3006
3007 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3008
3009 if (pdata->num_drc_cfgs) {
3010 struct snd_kcontrol_new controls[] = {
3011 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3012 wm8994_get_drc_enum, wm8994_put_drc_enum),
3013 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3014 wm8994_get_drc_enum, wm8994_put_drc_enum),
3015 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3016 wm8994_get_drc_enum, wm8994_put_drc_enum),
3017 };
3018
3019 /* We need an array of texts for the enum API */
7270cebe
MB		 3020 wm8994->drc_texts = devm_kzalloc(wm8994->codec->dev,
3021 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
9e6e96a1 3022 if (!wm8994->drc_texts) {
f0fba2ad 3023 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3024 "Failed to allocate %d DRC config texts\n",
3025 pdata->num_drc_cfgs);
3026 return;
3027 }
3028
3029 for (i = 0; i < pdata->num_drc_cfgs; i++)
3030 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3031
3032 wm8994->drc_enum.max = pdata->num_drc_cfgs;
3033 wm8994->drc_enum.texts = wm8994->drc_texts;
3034
022658be 3035 ret = snd_soc_add_codec_controls(wm8994->codec, controls,
9e6e96a1
MB		 3036 ARRAY_SIZE(controls));
3037 if (ret != 0)
f0fba2ad 3038 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 3039 "Failed to add DRC mode controls: %d\n", ret);
3040
3041 for (i = 0; i < WM8994_NUM_DRC; i++)
3042 wm8994_set_drc(codec, i);
3043 }
3044
3045 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3046 pdata->num_retune_mobile_cfgs);
3047
3048 if (pdata->num_retune_mobile_cfgs)
3049 wm8994_handle_retune_mobile_pdata(wm8994);
3050 else
022658be 3051 snd_soc_add_codec_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 3052 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 3053
3054 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3055 if (pdata->micbias[i]) {
3056 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3057 pdata->micbias[i] & 0xffff);
3058 }
3059 }
9e6e96a1
MB		 3060}
3061
88766984
MB		 3062/**
3063 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3064 *
3065 * @codec: WM8994 codec
3066 * @jack: jack to report detection events on
3067 * @micbias: microphone bias to detect on
88766984
MB		 3068 *
3069 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3070 * being used to bring out signals to the processor then only platform
5ab230a7 3071 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 3072 * be configured using snd_soc_jack_add_gpios() instead.
3073 *
3074 * Configuration of detection levels is available via the micbias1_lvl
3075 * and micbias2_lvl platform data members.
3076 */
3077int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
87092e3c 3078 int micbias)
88766984 3079{
b2c812e2 3080 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 3081 struct wm8994_micdet *micdet;
2a8a856d 3082 struct wm8994 *control = wm8994->wm8994;
87092e3c 3083 int reg, ret;
88766984 3084
87092e3c
MB		 3085 if (control->type != WM8994) {
3086 dev_warn(codec->dev, "Not a WM8994\n");
3a423157 3087 return -EINVAL;
87092e3c 3088 }
3a423157 3089
88766984
MB		 3090 switch (micbias) {
3091 case 1:
3092 micdet = &wm8994->micdet[0];
87092e3c
MB		 3093 if (jack)
3094 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3095 "MICBIAS1");
3096 else
3097 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3098 "MICBIAS1");
88766984
MB		 3099 break;
3100 case 2:
3101 micdet = &wm8994->micdet[1];
87092e3c
MB		 3102 if (jack)
3103 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3104 "MICBIAS1");
3105 else
3106 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3107 "MICBIAS1");
88766984
MB		 3108 break;
3109 default:
87092e3c 3110 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
88766984 3111 return -EINVAL;
87092e3c 3112 }
88766984 3113
87092e3c
MB		 3114 if (ret != 0)
3115 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3116 micbias, ret);
3117
3118 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3119 micbias, jack);
88766984
MB		 3120
3121 /* Store the configuration */
3122 micdet->jack = jack;
87092e3c 3123 micdet->detecting = true;
88766984
MB		 3124
3125 /* If either of the jacks is set up then enable detection */
3126 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3127 reg = WM8994_MICD_ENA;
87092e3c 3128 else
88766984
MB		 3129 reg = 0;
3130
3131 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3132
87092e3c
MB		 3133 snd_soc_dapm_sync(&codec->dapm);
3134
88766984
MB		 3135 return 0;
3136}
3137EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3138
3139static irqreturn_t wm8994_mic_irq(int irq, void *data)
3140{
3141 struct wm8994_priv *priv = data;
f0fba2ad 3142 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 3143 int reg;
3144 int report;
3145
7116f452 3146#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3147 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3148#endif
2bbb5d66 3149
88766984
MB		 3150 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
3151 if (reg < 0) {
3152 dev_err(codec->dev, "Failed to read microphone status: %d\n",
3153 reg);
3154 return IRQ_HANDLED;
3155 }
3156
3157 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
3158
3159 report = 0;
87092e3c
MB		 3160 if (reg & WM8994_MIC1_DET_STS) {
3161 if (priv->micdet[0].detecting)
3162 report = SND_JACK_HEADSET;
3163 }
3164 if (reg & WM8994_MIC1_SHRT_STS) {
3165 if (priv->micdet[0].detecting)
3166 report = SND_JACK_HEADPHONE;
3167 else
3168 report |= SND_JACK_BTN_0;
3169 }
3170 if (report)
3171 priv->micdet[0].detecting = false;
3172 else
3173 priv->micdet[0].detecting = true;
3174
88766984 3175 snd_soc_jack_report(priv->micdet[0].jack, report,
87092e3c 3176 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3177
3178 report = 0;
87092e3c
MB		 3179 if (reg & WM8994_MIC2_DET_STS) {
3180 if (priv->micdet[1].detecting)
3181 report = SND_JACK_HEADSET;
3182 }
3183 if (reg & WM8994_MIC2_SHRT_STS) {
3184 if (priv->micdet[1].detecting)
3185 report = SND_JACK_HEADPHONE;
3186 else
3187 report |= SND_JACK_BTN_0;
3188 }
3189 if (report)
3190 priv->micdet[1].detecting = false;
3191 else
3192 priv->micdet[1].detecting = true;
3193
88766984 3194 snd_soc_jack_report(priv->micdet[1].jack, report,
87092e3c 3195 SND_JACK_HEADSET | SND_JACK_BTN_0);
88766984
MB		 3196
3197 return IRQ_HANDLED;
3198}
3199
821edd2f
MB		 3200/* Default microphone detection handler for WM8958 - the user can
3201 * override this if they wish.
3202 */
3203static void wm8958_default_micdet(u16 status, void *data)
3204{
3205 struct snd_soc_codec *codec = data;
3206 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4585790d 3207 int report;
821edd2f 3208
a1691343
MB		 3209 dev_dbg(codec->dev, "MICDET %x\n", status);
3210
af6b6fe4 3211 /* Either nothing present or just starting detection */
b00adf76 3212 if (!(status & WM8958_MICD_STS)) {
af6b6fe4
MB		 3213 if (!wm8994->jackdet) {
3214 /* If nothing present then clear our statuses */
3215 dev_dbg(codec->dev, "Detected open circuit\n");
3216 wm8994->jack_mic = false;
3217 wm8994->mic_detecting = true;
b00adf76 3218
af6b6fe4 3219 wm8958_micd_set_rate(codec);
b00adf76 3220
af6b6fe4
MB		 3221 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3222 wm8994->btn_mask |
3223 SND_JACK_HEADSET);
3224 }
b00adf76
MB		 3225 return;
3226 }
821edd2f 3227
b00adf76
MB		 3228 /* If the measurement is showing a high impedence we've got a
3229 * microphone.
3230 */
157a75e6 3231 if (wm8994->mic_detecting && (status & 0x600)) {
b00adf76
MB		 3232 dev_dbg(codec->dev, "Detected microphone\n");
3233
157a75e6 3234 wm8994->mic_detecting = false;
b00adf76
MB		 3235 wm8994->jack_mic = true;
3236
3237 wm8958_micd_set_rate(codec);
3238
3239 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3240 SND_JACK_HEADSET);
3241 }
821edd2f 3242
b00adf76 3243
7c08b51f 3244 if (wm8994->mic_detecting && status & 0xfc) {
b00adf76 3245 dev_dbg(codec->dev, "Detected headphone\n");
157a75e6 3246 wm8994->mic_detecting = false;
b00adf76
MB		 3247
3248 wm8958_micd_set_rate(codec);
3249
af6b6fe4
MB		 3250 /* If we have jackdet that will detect removal */
3251 if (wm8994->jackdet) {
c986564b
MB		 3252 mutex_lock(&wm8994->accdet_lock);
3253
af6b6fe4
MB		 3254 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3255 WM8958_MICD_ENA, 0);
3256
c986564b
MB		 3257 wm1811_jackdet_set_mode(codec,
3258 WM1811_JACKDET_MODE_JACK);
3259
3260 mutex_unlock(&wm8994->accdet_lock);
3261
ecd1732f 3262 if (wm8994->pdata->jd_ext_cap)
07fb9d9e
MB		 3263 snd_soc_dapm_disable_pin(&codec->dapm,
3264 "MICBIAS2");
af6b6fe4 3265 }
ecd1732f
MB		 3266
3267 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3268 SND_JACK_HEADSET);
b00adf76
MB		 3269 }
3270
3271 /* Report short circuit as a button */
3272 if (wm8994->jack_mic) {
4585790d 3273 report = 0;
b00adf76 3274 if (status & 0x4)
4585790d
MB		 3275 report |= SND_JACK_BTN_0;
3276
3277 if (status & 0x8)
3278 report |= SND_JACK_BTN_1;
3279
3280 if (status & 0x10)
3281 report |= SND_JACK_BTN_2;
3282
3283 if (status & 0x20)
3284 report |= SND_JACK_BTN_3;
3285
3286 if (status & 0x40)
3287 report |= SND_JACK_BTN_4;
3288
3289 if (status & 0x80)
3290 report |= SND_JACK_BTN_5;
3291
3292 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3293 wm8994->btn_mask);
b00adf76 3294 }
821edd2f
MB		 3295}
3296
af6b6fe4
MB		 3297static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3298{
3299 struct wm8994_priv *wm8994 = data;
3300 struct snd_soc_codec *codec = wm8994->codec;
3301 int reg;
c986564b 3302 bool present;
af6b6fe4
MB		 3303
3304 mutex_lock(&wm8994->accdet_lock);
3305
3306 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3307 if (reg < 0) {
3308 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3309 mutex_unlock(&wm8994->accdet_lock);
3310 return IRQ_NONE;
3311 }
3312
3313 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3314
c986564b 3315 present = reg & WM1811_JACKDET_LVL;
af6b6fe4 3316
c986564b
MB		 3317 if (present) {
3318 dev_dbg(codec->dev, "Jack detected\n");
af6b6fe4 3319
55a27786
MB		 3320 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3321 WM8958_MICB2_DISCH, 0);
3322
378ec0ca
MB		 3323 /* Disable debounce while inserted */
3324 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3325 WM1811_JACKDET_DB, 0);
3326
af6b6fe4
MB		 3327 /*
3328 * Start off measument of microphone impedence to find
3329 * out what's actually there.
3330 */
3331 wm8994->mic_detecting = true;
3332 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
b9e67e5e 3333
af6b6fe4
MB		 3334 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3335 WM8958_MICD_ENA, WM8958_MICD_ENA);
3336 } else {
3337 dev_dbg(codec->dev, "Jack not detected\n");
3338
55a27786
MB		 3339 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3340 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3341
378ec0ca
MB		 3342 /* Enable debounce while removed */
3343 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3344 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3345
af6b6fe4
MB		 3346 wm8994->mic_detecting = false;
3347 wm8994->jack_mic = false;
3348 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3349 WM8958_MICD_ENA, 0);
3350 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3351 }
3352
3353 mutex_unlock(&wm8994->accdet_lock);
3354
c986564b
MB		 3355 /* If required for an external cap force MICBIAS on */
3356 if (wm8994->pdata->jd_ext_cap) {
c986564b
MB		 3357 if (present)
3358 snd_soc_dapm_force_enable_pin(&codec->dapm,
3359 "MICBIAS2");
3360 else
3361 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
c986564b
MB		 3362 }
3363
3364 if (present)
3365 snd_soc_jack_report(wm8994->micdet[0].jack,
3366 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3367 else
3368 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3369 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3370 wm8994->btn_mask);
3371
af6b6fe4
MB		 3372 return IRQ_HANDLED;
3373}
3374
821edd2f
MB		 3375/**
3376 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3377 *
3378 * @codec: WM8958 codec
3379 * @jack: jack to report detection events on
3380 *
3381 * Enable microphone detection functionality for the WM8958. By
3382 * default simple detection which supports the detection of up to 6
3383 * buttons plus video and microphone functionality is supported.
3384 *
3385 * The WM8958 has an advanced jack detection facility which is able to
3386 * support complex accessory detection, especially when used in
3387 * conjunction with external circuitry. In order to provide maximum
3388 * flexiblity a callback is provided which allows a completely custom
3389 * detection algorithm.
3390 */
3391int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3392 wm8958_micdet_cb cb, void *cb_data)
3393{
3394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3395 struct wm8994 *control = wm8994->wm8994;
4585790d 3396 u16 micd_lvl_sel;
821edd2f 3397
81204c84
MB		 3398 switch (control->type) {
3399 case WM1811:
3400 case WM8958:
3401 break;
3402 default:
821edd2f 3403 return -EINVAL;
81204c84 3404 }
821edd2f
MB		 3405
3406 if (jack) {
3407 if (!cb) {
3408 dev_dbg(codec->dev, "Using default micdet callback\n");
3409 cb = wm8958_default_micdet;
3410 cb_data = codec;
3411 }
3412
4cdf5e49 3413 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3414 snd_soc_dapm_sync(&codec->dapm);
4cdf5e49 3415
821edd2f
MB		 3416 wm8994->micdet[0].jack = jack;
3417 wm8994->jack_cb = cb;
3418 wm8994->jack_cb_data = cb_data;
3419
157a75e6 3420 wm8994->mic_detecting = true;
b00adf76
MB		 3421 wm8994->jack_mic = false;
3422
3423 wm8958_micd_set_rate(codec);
3424
4585790d
MB		 3425 /* Detect microphones and short circuits by default */
3426 if (wm8994->pdata->micd_lvl_sel)
3427 micd_lvl_sel = wm8994->pdata->micd_lvl_sel;
3428 else
3429 micd_lvl_sel = 0x41;
3430
3431 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3432 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3433 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3434
b00adf76 3435 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
4585790d 3436 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
b00adf76 3437
af6b6fe4
MB		 3438 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3439
3440 /*
3441 * If we can use jack detection start off with that,
3442 * otherwise jump straight to microphone detection.
3443 */
3444 if (wm8994->jackdet) {
55a27786
MB		 3445 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3446 WM8958_MICB2_DISCH,
3447 WM8958_MICB2_DISCH);
af6b6fe4
MB		 3448 snd_soc_update_bits(codec, WM8994_LDO_1,
3449 WM8994_LDO1_DISCH, 0);
3450 wm1811_jackdet_set_mode(codec,
3451 WM1811_JACKDET_MODE_JACK);
3452 } else {
3453 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3454 WM8958_MICD_ENA, WM8958_MICD_ENA);
3455 }
3456
821edd2f
MB		 3457 } else {
3458 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3459 WM8958_MICD_ENA, 0);
afaf1591 3460 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
4cdf5e49 3461 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
7d464b20 3462 snd_soc_dapm_sync(&codec->dapm);
821edd2f
MB		 3463 }
3464
3465 return 0;
3466}
3467EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3468
3469static irqreturn_t wm8958_mic_irq(int irq, void *data)
3470{
3471 struct wm8994_priv *wm8994 = data;
3472 struct snd_soc_codec *codec = wm8994->codec;
19940b3d 3473 int reg, count;
821edd2f 3474
af6b6fe4
MB		 3475 /*
3476 * Jack detection may have detected a removal simulataneously
3477 * with an update of the MICDET status; if so it will have
3478 * stopped detection and we can ignore this interrupt.
3479 */
c986564b 3480 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
af6b6fe4 3481 return IRQ_HANDLED;
af6b6fe4 3482
19940b3d
MB		 3483 /* We may occasionally read a detection without an impedence
3484 * range being provided - if that happens loop again.
3485 */
3486 count = 10;
3487 do {
3488 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3489 if (reg < 0) {
3490 dev_err(codec->dev,
3491 "Failed to read mic detect status: %d\n",
3492 reg);
3493 return IRQ_NONE;
3494 }
821edd2f 3495
19940b3d
MB		 3496 if (!(reg & WM8958_MICD_VALID)) {
3497 dev_dbg(codec->dev, "Mic detect data not valid\n");
3498 goto out;
3499 }
3500
3501 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3502 break;
3503
3504 msleep(1);
3505 } while (count--);
3506
3507 if (count == 0)
3508 dev_warn(codec->dev, "No impedence range reported for jack\n");
821edd2f 3509
7116f452 3510#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 3511 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 3512#endif
2bbb5d66 3513
821edd2f
MB		 3514 if (wm8994->jack_cb)
3515 wm8994->jack_cb(reg, wm8994->jack_cb_data);
3516 else
3517 dev_warn(codec->dev, "Accessory detection with no callback\n");
3518
3519out:
3520 return IRQ_HANDLED;
3521}
3522
3b1af3f8
MB		 3523static irqreturn_t wm8994_fifo_error(int irq, void *data)
3524{
3525 struct snd_soc_codec *codec = data;
3526
3527 dev_err(codec->dev, "FIFO error\n");
3528
3529 return IRQ_HANDLED;
3530}
3531
f0b182b0
MB		 3532static irqreturn_t wm8994_temp_warn(int irq, void *data)
3533{
3534 struct snd_soc_codec *codec = data;
3535
3536 dev_err(codec->dev, "Thermal warning\n");
3537
3538 return IRQ_HANDLED;
3539}
3540
3541static irqreturn_t wm8994_temp_shut(int irq, void *data)
3542{
3543 struct snd_soc_codec *codec = data;
3544
3545 dev_crit(codec->dev, "Thermal shutdown\n");
3546
3547 return IRQ_HANDLED;
3548}
3549
f0fba2ad 3550static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 3551{
d9a7666f 3552 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
2bc16ed8 3553 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ce6120cc 3554 struct snd_soc_dapm_context *dapm = &codec->dapm;
d9a7666f 3555 unsigned int reg;
ec62dbd7 3556 int ret, i;
9e6e96a1 3557
2bc16ed8 3558 wm8994->codec = codec;
d9a7666f 3559 codec->control_data = control->regmap;
9e6e96a1 3560
d9a7666f 3561 snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
2a8a856d 3562
f0fba2ad 3563 wm8994->codec = codec;
9e6e96a1 3564
af6b6fe4
MB		 3565 mutex_init(&wm8994->accdet_lock);
3566
c7ebf932
MB		 3567 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3568 init_completion(&wm8994->fll_locked[i]);
3569
9b7c525d
MB		 3570 if (wm8994->pdata && wm8994->pdata->micdet_irq)
3571 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
3572 else if (wm8994->pdata && wm8994->pdata->irq_base)
3573 wm8994->micdet_irq = wm8994->pdata->irq_base +
3574 WM8994_IRQ_MIC1_DET;
3575
39fb51a1 3576 pm_runtime_enable(codec->dev);
5fab5174 3577 pm_runtime_idle(codec->dev);
39fb51a1 3578
f959dee9
MB		 3579 /* By default use idle_bias_off, will override for WM8994 */
3580 codec->dapm.idle_bias_off = 1;
3581
9e6e96a1 3582 /* Set revision-specific configuration */
b6b05691 3583 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 3584 switch (control->type) {
3585 case WM8994:
f959dee9
MB		 3586 /* Single ended line outputs should have VMID on. */
3587 if (!wm8994->pdata->lineout1_diff ||
3588 !wm8994->pdata->lineout2_diff)
3589 codec->dapm.idle_bias_off = 0;
3590
3a423157
MB		 3591 switch (wm8994->revision) {
3592 case 2:
3593 case 3:
4537c4e7
MB		 3594 wm8994->hubs.dcs_codes_l = -5;
3595 wm8994->hubs.dcs_codes_r = -5;
3a423157
MB		 3596 wm8994->hubs.hp_startup_mode = 1;
3597 wm8994->hubs.dcs_readback_mode = 1;
f9acf9fe 3598 wm8994->hubs.series_startup = 1;
3a423157
MB		 3599 break;
3600 default:
79ef0abc 3601 wm8994->hubs.dcs_readback_mode = 2;
3a423157
MB		 3602 break;
3603 }
280ec8b7 3604 break;
3a423157
MB		 3605
3606 case WM8958:
8437f700 3607 wm8994->hubs.dcs_readback_mode = 1;
29fdc360 3608 wm8994->hubs.hp_startup_mode = 1;
9e6e96a1 3609 break;
3a423157 3610
81204c84
MB		 3611 case WM1811:
3612 wm8994->hubs.dcs_readback_mode = 2;
3613 wm8994->hubs.no_series_update = 1;
29fdc360 3614 wm8994->hubs.hp_startup_mode = 1;
67109cbe 3615 wm8994->hubs.no_cache_class_w = true;
81204c84
MB		 3616
3617 switch (wm8994->revision) {
3618 case 0:
3619 case 1:
fc8e6e86
MB		 3620 case 2:
3621 case 3:
6473a148 3622 wm8994->hubs.dcs_codes_l = -9;
e1660585 3623 wm8994->hubs.dcs_codes_r = -7;
81204c84
MB		 3624 break;
3625 default:
3626 break;
3627 }
3628
3629 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
3630 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
3631 break;
3632
9e6e96a1
MB		 3633 default:
3634 break;
3635 }
9e6e96a1 3636
2a8a856d 3637 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
3b1af3f8 3638 wm8994_fifo_error, "FIFO error", codec);
2a8a856d 3639 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
f0b182b0 3640 wm8994_temp_warn, "Thermal warning", codec);
2a8a856d 3641 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
f0b182b0 3642 wm8994_temp_shut, "Thermal shutdown", codec);
3b1af3f8 3643
2a8a856d 3644 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f
MB		 3645 wm_hubs_dcs_done, "DC servo done",
3646 &wm8994->hubs);
3647 if (ret == 0)
3648 wm8994->hubs.dcs_done_irq = true;
3649
3a423157
MB		 3650 switch (control->type) {
3651 case WM8994:
9b7c525d
MB		 3652 if (wm8994->micdet_irq) {
3653 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3654 wm8994_mic_irq,
3655 IRQF_TRIGGER_RISING,
3656 "Mic1 detect",
3657 wm8994);
3658 if (ret != 0)
3659 dev_warn(codec->dev,
3660 "Failed to request Mic1 detect IRQ: %d\n",
3661 ret);
3662 }
3a423157 3663
2a8a856d 3664 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3665 WM8994_IRQ_MIC1_SHRT,
3666 wm8994_mic_irq, "Mic 1 short",
3667 wm8994);
3668 if (ret != 0)
3669 dev_warn(codec->dev,
3670 "Failed to request Mic1 short IRQ: %d\n",
3671 ret);
3672
2a8a856d 3673 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3674 WM8994_IRQ_MIC2_DET,
3675 wm8994_mic_irq, "Mic 2 detect",
3676 wm8994);
3677 if (ret != 0)
3678 dev_warn(codec->dev,
3679 "Failed to request Mic2 detect IRQ: %d\n",
3680 ret);
3681
2a8a856d 3682 ret = wm8994_request_irq(wm8994->wm8994,
3a423157
MB		 3683 WM8994_IRQ_MIC2_SHRT,
3684 wm8994_mic_irq, "Mic 2 short",
3685 wm8994);
3686 if (ret != 0)
3687 dev_warn(codec->dev,
3688 "Failed to request Mic2 short IRQ: %d\n",
3689 ret);
3690 break;
821edd2f
MB		 3691
3692 case WM8958:
81204c84 3693 case WM1811:
9b7c525d
MB		 3694 if (wm8994->micdet_irq) {
3695 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3696 wm8958_mic_irq,
3697 IRQF_TRIGGER_RISING,
3698 "Mic detect",
3699 wm8994);
3700 if (ret != 0)
3701 dev_warn(codec->dev,
3702 "Failed to request Mic detect IRQ: %d\n",
3703 ret);
3704 }
3a423157 3705 }
88766984 3706
af6b6fe4
MB		 3707 switch (control->type) {
3708 case WM1811:
3709 if (wm8994->revision > 1) {
3710 ret = wm8994_request_irq(wm8994->wm8994,
3711 WM8994_IRQ_GPIO(6),
3712 wm1811_jackdet_irq, "JACKDET",
3713 wm8994);
3714 if (ret == 0)
3715 wm8994->jackdet = true;
3716 }
3717 break;
3718 default:
3719 break;
3720 }
3721
c7ebf932
MB		 3722 wm8994->fll_locked_irq = true;
3723 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
2a8a856d 3724 ret = wm8994_request_irq(wm8994->wm8994,
c7ebf932
MB		 3725 WM8994_IRQ_FLL1_LOCK + i,
3726 wm8994_fll_locked_irq, "FLL lock",
3727 &wm8994->fll_locked[i]);
3728 if (ret != 0)
3729 wm8994->fll_locked_irq = false;
3730 }
3731
27060b3c
MB		 3732 /* Make sure we can read from the GPIOs if they're inputs */
3733 pm_runtime_get_sync(codec->dev);
3734
9e6e96a1
MB		 3735 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3736 * configured on init - if a system wants to do this dynamically
3737 * at runtime we can deal with that then.
3738 */
d9a7666f 3739 ret = regmap_read(control->regmap, WM8994_GPIO_1, &reg);
9e6e96a1
MB		 3740 if (ret < 0) {
3741 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 3742 goto err_irq;
9e6e96a1 3743 }
d9a7666f 3744 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3745 wm8994->lrclk_shared[0] = 1;
3746 wm8994_dai[0].symmetric_rates = 1;
3747 } else {
3748 wm8994->lrclk_shared[0] = 0;
3749 }
3750
d9a7666f 3751 ret = regmap_read(control->regmap, WM8994_GPIO_6, &reg);
9e6e96a1
MB		 3752 if (ret < 0) {
3753 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 3754 goto err_irq;
9e6e96a1 3755 }
d9a7666f 3756 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
9e6e96a1
MB		 3757 wm8994->lrclk_shared[1] = 1;
3758 wm8994_dai[1].symmetric_rates = 1;
3759 } else {
3760 wm8994->lrclk_shared[1] = 0;
3761 }
3762
27060b3c
MB		 3763 pm_runtime_put(codec->dev);
3764
9e6e96a1 3765 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3766 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3767 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3768 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3769 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3770 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3771 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3772 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3773 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3774 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3775 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3776 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3777 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3778 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3779 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3780 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3781 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3782 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3783 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3784 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3785 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3786 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3787 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3788 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3789 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3790 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3791 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3792 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3793 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3794 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3795 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3796 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3797 WM8994_DAC2_VU, WM8994_DAC2_VU);
3798
3799 /* Set the low bit of the 3D stereo depth so TLV matches */
3800 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3801 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3802 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3803 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3804 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3805 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3806 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3807 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3808 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3809
5b739670
MB		 3810 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3811 * use this; it only affects behaviour on idle TDM clock
3812 * cycles. */
3813 switch (control->type) {
3814 case WM8994:
3815 case WM8958:
3816 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3817 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3818 break;
3819 default:
3820 break;
3821 }
d1ce6b20 3822
500fa30e
MB		 3823 /* Put MICBIAS into bypass mode by default on newer devices */
3824 switch (control->type) {
3825 case WM8958:
3826 case WM1811:
3827 snd_soc_update_bits(codec, WM8958_MICBIAS1,
3828 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
3829 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3830 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
3831 break;
3832 default:
3833 break;
3834 }
3835
9e6e96a1
MB		 3836 wm8994_update_class_w(codec);
3837
f0fba2ad 3838 wm8994_handle_pdata(wm8994);
9e6e96a1 3839
f0fba2ad 3840 wm_hubs_add_analogue_controls(codec);
022658be 3841 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
f0fba2ad 3842 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3843 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3844 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3845
3846 switch (control->type) {
3847 case WM8994:
3848 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3849 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3850 if (wm8994->revision < 4) {
173efa09
DP		 3851 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3852 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3853 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3854 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3855 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3856 ARRAY_SIZE(wm8994_dac_revd_widgets));
3857 } else {
173efa09
DP		 3858 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3859 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3860 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3861 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3862 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3863 ARRAY_SIZE(wm8994_dac_widgets));
3864 }
c4431df0
MB		 3865 break;
3866 case WM8958:
022658be 3867 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
c4431df0
MB		 3868 ARRAY_SIZE(wm8958_snd_controls));
3869 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3870 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3871 if (wm8994->revision < 1) {
3872 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3873 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3874 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3875 ARRAY_SIZE(wm8994_adc_revd_widgets));
3876 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3877 ARRAY_SIZE(wm8994_dac_revd_widgets));
3878 } else {
3879 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3880 ARRAY_SIZE(wm8994_lateclk_widgets));
3881 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3882 ARRAY_SIZE(wm8994_adc_widgets));
3883 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3884 ARRAY_SIZE(wm8994_dac_widgets));
3885 }
c4431df0 3886 break;
81204c84
MB		 3887
3888 case WM1811:
022658be 3889 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
81204c84
MB		 3890 ARRAY_SIZE(wm8958_snd_controls));
3891 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3892 ARRAY_SIZE(wm8958_dapm_widgets));
3893 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3894 ARRAY_SIZE(wm8994_lateclk_widgets));
3895 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3896 ARRAY_SIZE(wm8994_adc_widgets));
3897 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3898 ARRAY_SIZE(wm8994_dac_widgets));
3899 break;
c4431df0
MB		 3900 }
3901
3902
f0fba2ad 3903 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3904 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3905
c4431df0
MB		 3906 switch (control->type) {
3907 case WM8994:
3908 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3909 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3910
173efa09 3911 if (wm8994->revision < 4) {
6ed8f148
MB		 3912 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3913 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3914 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3915 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3916 } else {
3917 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3918 ARRAY_SIZE(wm8994_lateclk_intercon));
3919 }
c4431df0
MB		 3920 break;
3921 case WM8958:
780e2806
MB		 3922 if (wm8994->revision < 1) {
3923 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3924 ARRAY_SIZE(wm8994_revd_intercon));
3925 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3926 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3927 } else {
3928 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3929 ARRAY_SIZE(wm8994_lateclk_intercon));
3930 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3931 ARRAY_SIZE(wm8958_intercon));
3932 }
f701a2e5
MB		 3933
3934 wm8958_dsp2_init(codec);
c4431df0 3935 break;
81204c84
MB		 3936 case WM1811:
3937 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3938 ARRAY_SIZE(wm8994_lateclk_intercon));
3939 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3940 ARRAY_SIZE(wm8958_intercon));
3941 break;
c4431df0
MB		 3942 }
3943
9e6e96a1
MB		 3944 return 0;
3945
88766984 3946err_irq:
af6b6fe4
MB		 3947 if (wm8994->jackdet)
3948 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
2a8a856d
MB		 3949 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
3950 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
3951 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3952 if (wm8994->micdet_irq)
3953 free_irq(wm8994->micdet_irq, wm8994);
c7ebf932 3954 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3955 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932 3956 &wm8994->fll_locked[i]);
2a8a856d 3957 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3958 &wm8994->hubs);
2a8a856d
MB		 3959 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3960 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3961 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
a421a0e4 3962
9e6e96a1
MB		 3963 return ret;
3964}
3965
f0fba2ad 3966static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3967{
f0fba2ad 3968 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2a8a856d 3969 struct wm8994 *control = wm8994->wm8994;
c7ebf932 3970 int i;
9e6e96a1
MB		 3971
3972 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3973
39fb51a1
MB		 3974 pm_runtime_disable(codec->dev);
3975
c7ebf932 3976 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2a8a856d 3977 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
c7ebf932
MB		 3978 &wm8994->fll_locked[i]);
3979
2a8a856d 3980 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
b30ead5f 3981 &wm8994->hubs);
2a8a856d
MB		 3982 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
3983 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
3984 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
b30ead5f 3985
af6b6fe4
MB		 3986 if (wm8994->jackdet)
3987 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
3988
3a423157
MB		 3989 switch (control->type) {
3990 case WM8994:
9b7c525d
MB		 3991 if (wm8994->micdet_irq)
3992 free_irq(wm8994->micdet_irq, wm8994);
2a8a856d 3993 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
3a423157 3994 wm8994);
2a8a856d 3995 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
3a423157 3996 wm8994);
2a8a856d 3997 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
3a423157
MB		 3998 wm8994);
3999 break;
821edd2f 4000
81204c84 4001 case WM1811:
821edd2f 4002 case WM8958:
9b7c525d
MB		 4003 if (wm8994->micdet_irq)
4004 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 4005 break;
3a423157 4006 }
fbbf5920
MB		 4007 if (wm8994->mbc)
4008 release_firmware(wm8994->mbc);
09e10d7f
MB		 4009 if (wm8994->mbc_vss)
4010 release_firmware(wm8994->mbc_vss);
31215871
MB		 4011 if (wm8994->enh_eq)
4012 release_firmware(wm8994->enh_eq);
24fb2b11 4013 kfree(wm8994->retune_mobile_texts);
9e6e96a1
MB		 4014
4015 return 0;
4016}
4017
f0fba2ad
LG		 4018static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4019 .probe = wm8994_codec_probe,
4020 .remove = wm8994_codec_remove,
4752a887
MB		 4021 .suspend = wm8994_codec_suspend,
4022 .resume = wm8994_codec_resume,
f0fba2ad
LG		 4023 .set_bias_level = wm8994_set_bias_level,
4024};
4025
4026static int __devinit wm8994_probe(struct platform_device *pdev)
4027{
2bc16ed8
MB		 4028 struct wm8994_priv *wm8994;
4029
4030 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4031 GFP_KERNEL);
4032 if (wm8994 == NULL)
4033 return -ENOMEM;
4034 platform_set_drvdata(pdev, wm8994);
4035
4036 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4037 wm8994->pdata = dev_get_platdata(pdev->dev.parent);
4038
f0fba2ad
LG		 4039 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4040 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4041}
4042
4043static int __devexit wm8994_remove(struct platform_device *pdev)
4044{
4045 snd_soc_unregister_codec(&pdev->dev);
4046 return 0;
4047}
4048
4752a887
MB		 4049#ifdef CONFIG_PM_SLEEP
4050static int wm8994_suspend(struct device *dev)
4051{
4052 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4053
4054 /* Drop down to power saving mode when system is suspended */
4055 if (wm8994->jackdet && !wm8994->active_refcount)
4056 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4057 WM1811_JACKDET_MODE_MASK,
4058 wm8994->jackdet_mode);
4059
4060 return 0;
4061}
4062
4063static int wm8994_resume(struct device *dev)
4064{
4065 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4066
4067 if (wm8994->jackdet && wm8994->jack_cb)
4068 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4069 WM1811_JACKDET_MODE_MASK,
4070 WM1811_JACKDET_MODE_AUDIO);
4071
4072 return 0;
4073}
4074#endif
4075
4076static const struct dev_pm_ops wm8994_pm_ops = {
4077 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4078};
4079
9e6e96a1
MB		 4080static struct platform_driver wm8994_codec_driver = {
4081 .driver = {
4752a887
MB		 4082 .name = "wm8994-codec",
4083 .owner = THIS_MODULE,
4084 .pm = &wm8994_pm_ops,
4085 },
f0fba2ad
LG		 4086 .probe = wm8994_probe,
4087 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 4088};
4089
5bbcc3c0 4090module_platform_driver(wm8994_codec_driver);
9e6e96a1
MB		 4091
4092MODULE_DESCRIPTION("ASoC WM8994 driver");
4093MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4094MODULE_LICENSE("GPL");
4095MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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