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ASoC: Don't restart an already running WM8958 DSP2
[deliverable/linux.git] / sound / soc / codecs / wm8994.c
CommitLineData
9e6e96a1
MB		 1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
39fb51a1 21#include <linux/pm_runtime.h>
9e6e96a1 22#include <linux/regulator/consumer.h>
5a0e3ad6 23#include <linux/slab.h>
9e6e96a1 24#include <sound/core.h>
821edd2f 25#include <sound/jack.h>
9e6e96a1
MB		 26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
9e6e96a1
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
2bbb5d66 31#include <trace/events/asoc.h>
9e6e96a1
MB		 32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
9e6e96a1
MB		 41#define WM8994_NUM_DRC 3
42#define WM8994_NUM_EQ 3
43
44static int wm8994_drc_base[] = {
45 WM8994_AIF1_DRC1_1,
46 WM8994_AIF1_DRC2_1,
47 WM8994_AIF2_DRC_1,
48};
49
50static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
54};
55
d4754ec9 56static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 57{
af9af866
MB		 58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
60
e88ff1e6
MB		 61 switch (reg) {
62 case WM8994_GPIO_1:
63 case WM8994_GPIO_2:
64 case WM8994_GPIO_3:
65 case WM8994_GPIO_4:
66 case WM8994_GPIO_5:
67 case WM8994_GPIO_6:
68 case WM8994_GPIO_7:
69 case WM8994_GPIO_8:
70 case WM8994_GPIO_9:
71 case WM8994_GPIO_10:
72 case WM8994_GPIO_11:
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
76 return 1;
af9af866
MB		 77
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
82 return 1;
83 else
84 return 0;
85
e88ff1e6
MB		 86 default:
87 break;
88 }
89
7b306dae 90 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1 91 return 0;
7b306dae 92 return wm8994_access_masks[reg].readable != 0;
9e6e96a1
MB		 93}
94
d4754ec9 95static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
9e6e96a1 96{
ca9aef50 97 if (reg >= WM8994_CACHE_SIZE)
9e6e96a1
MB		 98 return 1;
99
100 switch (reg) {
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
106 case WM8994_LDO_1:
107 case WM8994_LDO_2:
d6addcc9 108 case WM8958_DSP2_EXECCONTROL:
821edd2f 109 case WM8958_MIC_DETECT_3:
9e6e96a1
MB		 110 return 1;
111 default:
112 return 0;
113 }
114}
115
116static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
117 unsigned int value)
118{
ca9aef50 119 int ret;
9e6e96a1
MB		 120
121 BUG_ON(reg > WM8994_MAX_REGISTER);
122
d4754ec9 123 if (!wm8994_volatile(codec, reg)) {
ca9aef50
MB		 124 ret = snd_soc_cache_write(codec, reg, value);
125 if (ret != 0)
126 dev_err(codec->dev, "Cache write to %x failed: %d\n",
127 reg, ret);
128 }
9e6e96a1
MB		 129
130 return wm8994_reg_write(codec->control_data, reg, value);
131}
132
133static unsigned int wm8994_read(struct snd_soc_codec *codec,
134 unsigned int reg)
135{
ca9aef50
MB		 136 unsigned int val;
137 int ret;
9e6e96a1
MB		 138
139 BUG_ON(reg > WM8994_MAX_REGISTER);
140
d4754ec9 141 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
ca9aef50
MB		 142 reg < codec->driver->reg_cache_size) {
143 ret = snd_soc_cache_read(codec, reg, &val);
144 if (ret >= 0)
145 return val;
146 else
147 dev_err(codec->dev, "Cache read from %x failed: %d\n",
148 reg, ret);
149 }
150
151 return wm8994_reg_read(codec->control_data, reg);
9e6e96a1
MB		 152}
153
154static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
155{
b2c812e2 156 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 157 int rate;
158 int reg1 = 0;
159 int offset;
160
161 if (aif)
162 offset = 4;
163 else
164 offset = 0;
165
166 switch (wm8994->sysclk[aif]) {
167 case WM8994_SYSCLK_MCLK1:
168 rate = wm8994->mclk[0];
169 break;
170
171 case WM8994_SYSCLK_MCLK2:
172 reg1 |= 0x8;
173 rate = wm8994->mclk[1];
174 break;
175
176 case WM8994_SYSCLK_FLL1:
177 reg1 |= 0x10;
178 rate = wm8994->fll[0].out;
179 break;
180
181 case WM8994_SYSCLK_FLL2:
182 reg1 |= 0x18;
183 rate = wm8994->fll[1].out;
184 break;
185
186 default:
187 return -EINVAL;
188 }
189
190 if (rate >= 13500000) {
191 rate /= 2;
192 reg1 |= WM8994_AIF1CLK_DIV;
193
194 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
195 aif + 1, rate);
196 }
5e5e2bef
MB		 197
198 if (rate && rate < 3000000)
199 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
200 aif + 1, rate);
201
9e6e96a1
MB		 202 wm8994->aifclk[aif] = rate;
203
204 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
205 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
206 reg1);
207
208 return 0;
209}
210
211static int configure_clock(struct snd_soc_codec *codec)
212{
b2c812e2 213 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 214 int old, new;
215
216 /* Bring up the AIF clocks first */
217 configure_aif_clock(codec, 0);
218 configure_aif_clock(codec, 1);
219
220 /* Then switch CLK_SYS over to the higher of them; a change
221 * can only happen as a result of a clocking change which can
222 * only be made outside of DAPM so we can safely redo the
223 * clocking.
224 */
225
226 /* If they're equal it doesn't matter which is used */
227 if (wm8994->aifclk[0] == wm8994->aifclk[1])
228 return 0;
229
230 if (wm8994->aifclk[0] < wm8994->aifclk[1])
231 new = WM8994_SYSCLK_SRC;
232 else
233 new = 0;
234
235 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
236
237 /* If there's no change then we're done. */
238 if (old == new)
239 return 0;
240
241 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
242
ce6120cc 243 snd_soc_dapm_sync(&codec->dapm);
9e6e96a1
MB		 244
245 return 0;
246}
247
248static int check_clk_sys(struct snd_soc_dapm_widget *source,
249 struct snd_soc_dapm_widget *sink)
250{
251 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
252 const char *clk;
253
254 /* Check what we're currently using for CLK_SYS */
255 if (reg & WM8994_SYSCLK_SRC)
256 clk = "AIF2CLK";
257 else
258 clk = "AIF1CLK";
259
260 return strcmp(source->name, clk) == 0;
261}
262
263static const char *sidetone_hpf_text[] = {
264 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
265};
266
267static const struct soc_enum sidetone_hpf =
268 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
269
146fd574
UK		 270static const char *adc_hpf_text[] = {
271 "HiFi", "Voice 1", "Voice 2", "Voice 3"
272};
273
274static const struct soc_enum aif1adc1_hpf =
275 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
276
277static const struct soc_enum aif1adc2_hpf =
278 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
279
280static const struct soc_enum aif2adc_hpf =
281 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
282
9e6e96a1
MB		 283static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
284static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
285static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
286static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
287static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
288
289#define WM8994_DRC_SWITCH(xname, reg, shift) \
290{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
291 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
292 .put = wm8994_put_drc_sw, \
293 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
294
295static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
296 struct snd_ctl_elem_value *ucontrol)
297{
298 struct soc_mixer_control *mc =
299 (struct soc_mixer_control *)kcontrol->private_value;
300 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
301 int mask, ret;
302
303 /* Can't enable both ADC and DAC paths simultaneously */
304 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
305 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
306 WM8994_AIF1ADC1R_DRC_ENA_MASK;
307 else
308 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
309
310 ret = snd_soc_read(codec, mc->reg);
311 if (ret < 0)
312 return ret;
313 if (ret & mask)
314 return -EINVAL;
315
316 return snd_soc_put_volsw(kcontrol, ucontrol);
317}
318
9e6e96a1
MB		 319static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
320{
b2c812e2 321 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 322 struct wm8994_pdata *pdata = wm8994->pdata;
323 int base = wm8994_drc_base[drc];
324 int cfg = wm8994->drc_cfg[drc];
325 int save, i;
326
327 /* Save any enables; the configuration should clear them. */
328 save = snd_soc_read(codec, base);
329 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
330 WM8994_AIF1ADC1R_DRC_ENA;
331
332 for (i = 0; i < WM8994_DRC_REGS; i++)
333 snd_soc_update_bits(codec, base + i, 0xffff,
334 pdata->drc_cfgs[cfg].regs[i]);
335
336 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
337 WM8994_AIF1ADC1L_DRC_ENA |
338 WM8994_AIF1ADC1R_DRC_ENA, save);
339}
340
341/* Icky as hell but saves code duplication */
342static int wm8994_get_drc(const char *name)
343{
344 if (strcmp(name, "AIF1DRC1 Mode") == 0)
345 return 0;
346 if (strcmp(name, "AIF1DRC2 Mode") == 0)
347 return 1;
348 if (strcmp(name, "AIF2DRC Mode") == 0)
349 return 2;
350 return -EINVAL;
351}
352
353static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
354 struct snd_ctl_elem_value *ucontrol)
355{
356 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 357 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 358 struct wm8994_pdata *pdata = wm8994->pdata;
359 int drc = wm8994_get_drc(kcontrol->id.name);
360 int value = ucontrol->value.integer.value[0];
361
362 if (drc < 0)
363 return drc;
364
365 if (value >= pdata->num_drc_cfgs)
366 return -EINVAL;
367
368 wm8994->drc_cfg[drc] = value;
369
370 wm8994_set_drc(codec, drc);
371
372 return 0;
373}
374
375static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
376 struct snd_ctl_elem_value *ucontrol)
377{
378 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 379 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 380 int drc = wm8994_get_drc(kcontrol->id.name);
381
382 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
383
384 return 0;
385}
386
387static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
388{
b2c812e2 389 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 390 struct wm8994_pdata *pdata = wm8994->pdata;
391 int base = wm8994_retune_mobile_base[block];
392 int iface, best, best_val, save, i, cfg;
393
394 if (!pdata || !wm8994->num_retune_mobile_texts)
395 return;
396
397 switch (block) {
398 case 0:
399 case 1:
400 iface = 0;
401 break;
402 case 2:
403 iface = 1;
404 break;
405 default:
406 return;
407 }
408
409 /* Find the version of the currently selected configuration
410 * with the nearest sample rate. */
411 cfg = wm8994->retune_mobile_cfg[block];
412 best = 0;
413 best_val = INT_MAX;
414 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
415 if (strcmp(pdata->retune_mobile_cfgs[i].name,
416 wm8994->retune_mobile_texts[cfg]) == 0 &&
417 abs(pdata->retune_mobile_cfgs[i].rate
418 - wm8994->dac_rates[iface]) < best_val) {
419 best = i;
420 best_val = abs(pdata->retune_mobile_cfgs[i].rate
421 - wm8994->dac_rates[iface]);
422 }
423 }
424
425 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
426 block,
427 pdata->retune_mobile_cfgs[best].name,
428 pdata->retune_mobile_cfgs[best].rate,
429 wm8994->dac_rates[iface]);
430
431 /* The EQ will be disabled while reconfiguring it, remember the
432 * current configuration.
433 */
434 save = snd_soc_read(codec, base);
435 save &= WM8994_AIF1DAC1_EQ_ENA;
436
437 for (i = 0; i < WM8994_EQ_REGS; i++)
438 snd_soc_update_bits(codec, base + i, 0xffff,
439 pdata->retune_mobile_cfgs[best].regs[i]);
440
441 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
442}
443
444/* Icky as hell but saves code duplication */
445static int wm8994_get_retune_mobile_block(const char *name)
446{
447 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
448 return 0;
449 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
450 return 1;
451 if (strcmp(name, "AIF2 EQ Mode") == 0)
452 return 2;
453 return -EINVAL;
454}
455
456static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
457 struct snd_ctl_elem_value *ucontrol)
458{
459 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 460 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 461 struct wm8994_pdata *pdata = wm8994->pdata;
462 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
463 int value = ucontrol->value.integer.value[0];
464
465 if (block < 0)
466 return block;
467
468 if (value >= pdata->num_retune_mobile_cfgs)
469 return -EINVAL;
470
471 wm8994->retune_mobile_cfg[block] = value;
472
473 wm8994_set_retune_mobile(codec, block);
474
475 return 0;
476}
477
478static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
479 struct snd_ctl_elem_value *ucontrol)
480{
481 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
4a8d929d 482 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 483 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
484
485 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
486
487 return 0;
488}
489
96b101ef 490static const char *aif_chan_src_text[] = {
f554885f
MB		 491 "Left", "Right"
492};
493
96b101ef
MB		 494static const struct soc_enum aif1adcl_src =
495 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
496
497static const struct soc_enum aif1adcr_src =
498 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
499
500static const struct soc_enum aif2adcl_src =
501 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
502
503static const struct soc_enum aif2adcr_src =
504 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
505
f554885f 506static const struct soc_enum aif1dacl_src =
96b101ef 507 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 508
509static const struct soc_enum aif1dacr_src =
96b101ef 510 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f
MB		 511
512static const struct soc_enum aif2dacl_src =
96b101ef 513 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
f554885f
MB		 514
515static const struct soc_enum aif2dacr_src =
96b101ef 516 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
f554885f 517
154b26aa
MB		 518static const char *osr_text[] = {
519 "Low Power", "High Performance",
520};
521
522static const struct soc_enum dac_osr =
523 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
524
525static const struct soc_enum adc_osr =
526 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
527
9e6e96a1
MB		 528static const struct snd_kcontrol_new wm8994_snd_controls[] = {
529SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
530 WM8994_AIF1_ADC1_RIGHT_VOLUME,
531 1, 119, 0, digital_tlv),
532SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
533 WM8994_AIF1_ADC2_RIGHT_VOLUME,
534 1, 119, 0, digital_tlv),
535SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
536 WM8994_AIF2_ADC_RIGHT_VOLUME,
537 1, 119, 0, digital_tlv),
538
96b101ef
MB		 539SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
540SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
49db7e7b
MB		 541SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
542SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
96b101ef 543
f554885f
MB		 544SOC_ENUM("AIF1DACL Source", aif1dacl_src),
545SOC_ENUM("AIF1DACR Source", aif1dacr_src),
49db7e7b
MB		 546SOC_ENUM("AIF2DACL Source", aif2dacl_src),
547SOC_ENUM("AIF2DACR Source", aif2dacr_src),
f554885f 548
9e6e96a1
MB		 549SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
550 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
551SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
552 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
553SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
554 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
555
556SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
557SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
558
559SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
560SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
561SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
562
563WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
564WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
565WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
566
567WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
568WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
569WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
570
571WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
572WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
573WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
574
575SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
576 5, 12, 0, st_tlv),
577SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
578 0, 12, 0, st_tlv),
579SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
580 5, 12, 0, st_tlv),
581SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
582 0, 12, 0, st_tlv),
583SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
584SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
585
146fd574
UK		 586SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
587SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
588
589SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
590SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
591
592SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
593SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
594
154b26aa
MB		 595SOC_ENUM("ADC OSR", adc_osr),
596SOC_ENUM("DAC OSR", dac_osr),
597
9e6e96a1
MB		 598SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
599 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
600SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
601 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
602
603SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
604 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
605SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
606 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
607
608SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
609 6, 1, 1, wm_hubs_spkmix_tlv),
610SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
611 2, 1, 1, wm_hubs_spkmix_tlv),
612
613SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
614 6, 1, 1, wm_hubs_spkmix_tlv),
615SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
616 2, 1, 1, wm_hubs_spkmix_tlv),
617
618SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
619 10, 15, 0, wm8994_3d_tlv),
458350b3 620SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
9e6e96a1
MB		 621 8, 1, 0),
622SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
623 10, 15, 0, wm8994_3d_tlv),
624SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
625 8, 1, 0),
458350b3 626SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1 627 10, 15, 0, wm8994_3d_tlv),
458350b3 628SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
9e6e96a1
MB		 629 8, 1, 0),
630};
631
632static const struct snd_kcontrol_new wm8994_eq_controls[] = {
633SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
634 eq_tlv),
635SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
636 eq_tlv),
637SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
638 eq_tlv),
639SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
640 eq_tlv),
641SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
642 eq_tlv),
643
644SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
649 eq_tlv),
650SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
651 eq_tlv),
652SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
653 eq_tlv),
654
655SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
660 eq_tlv),
661SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
662 eq_tlv),
663SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
664 eq_tlv),
665};
666
c4431df0
MB		 667static const struct snd_kcontrol_new wm8958_snd_controls[] = {
668SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
669};
670
9e6e96a1
MB		 671static int clk_sys_event(struct snd_soc_dapm_widget *w,
672 struct snd_kcontrol *kcontrol, int event)
673{
674 struct snd_soc_codec *codec = w->codec;
675
676 switch (event) {
677 case SND_SOC_DAPM_PRE_PMU:
678 return configure_clock(codec);
679
680 case SND_SOC_DAPM_POST_PMD:
681 configure_clock(codec);
682 break;
683 }
684
685 return 0;
686}
687
688static void wm8994_update_class_w(struct snd_soc_codec *codec)
689{
fec6dd83 690 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 691 int enable = 1;
692 int source = 0; /* GCC flow analysis can't track enable */
693 int reg, reg_r;
694
695 /* Only support direct DAC->headphone paths */
696 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
697 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
ee839a21 698 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
9e6e96a1
MB		 699 enable = 0;
700 }
701
702 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
703 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
ee839a21 704 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
9e6e96a1
MB		 705 enable = 0;
706 }
707
708 /* We also need the same setting for L/R and only one path */
709 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
710 switch (reg) {
711 case WM8994_AIF2DACL_TO_DAC1L:
ee839a21 712 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
9e6e96a1
MB		 713 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
714 break;
715 case WM8994_AIF1DAC2L_TO_DAC1L:
ee839a21 716 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
9e6e96a1
MB		 717 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
718 break;
719 case WM8994_AIF1DAC1L_TO_DAC1L:
ee839a21 720 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
9e6e96a1
MB		 721 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
722 break;
723 default:
ee839a21 724 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
9e6e96a1
MB		 725 enable = 0;
726 break;
727 }
728
729 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
730 if (reg_r != reg) {
ee839a21 731 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
9e6e96a1
MB		 732 enable = 0;
733 }
734
735 if (enable) {
736 dev_dbg(codec->dev, "Class W enabled\n");
737 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
738 WM8994_CP_DYN_PWR |
739 WM8994_CP_DYN_SRC_SEL_MASK,
740 source | WM8994_CP_DYN_PWR);
fec6dd83 741 wm8994->hubs.class_w = true;
9e6e96a1
MB		 742
743 } else {
744 dev_dbg(codec->dev, "Class W disabled\n");
745 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
746 WM8994_CP_DYN_PWR, 0);
fec6dd83 747 wm8994->hubs.class_w = false;
9e6e96a1
MB		 748 }
749}
750
173efa09
DP		 751static int late_enable_ev(struct snd_soc_dapm_widget *w,
752 struct snd_kcontrol *kcontrol, int event)
753{
754 struct snd_soc_codec *codec = w->codec;
755 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
756
757 switch (event) {
758 case SND_SOC_DAPM_PRE_PMU:
a3cff81a 759 if (wm8994->aif1clk_enable) {
173efa09
DP		 760 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
761 WM8994_AIF1CLK_ENA_MASK,
762 WM8994_AIF1CLK_ENA);
a3cff81a
DP		 763 wm8994->aif1clk_enable = 0;
764 }
765 if (wm8994->aif2clk_enable) {
173efa09
DP		 766 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
767 WM8994_AIF2CLK_ENA_MASK,
768 WM8994_AIF2CLK_ENA);
a3cff81a
DP		 769 wm8994->aif2clk_enable = 0;
770 }
173efa09
DP		 771 break;
772 }
773
c6b7b570
MB		 774 /* We may also have postponed startup of DSP, handle that. */
775 wm8958_aif_ev(w, kcontrol, event);
776
173efa09
DP		 777 return 0;
778}
779
780static int late_disable_ev(struct snd_soc_dapm_widget *w,
781 struct snd_kcontrol *kcontrol, int event)
782{
783 struct snd_soc_codec *codec = w->codec;
784 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
785
786 switch (event) {
787 case SND_SOC_DAPM_POST_PMD:
a3cff81a 788 if (wm8994->aif1clk_disable) {
173efa09
DP		 789 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
790 WM8994_AIF1CLK_ENA_MASK, 0);
a3cff81a 791 wm8994->aif1clk_disable = 0;
173efa09 792 }
a3cff81a 793 if (wm8994->aif2clk_disable) {
173efa09
DP		 794 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
795 WM8994_AIF2CLK_ENA_MASK, 0);
a3cff81a 796 wm8994->aif2clk_disable = 0;
173efa09
DP		 797 }
798 break;
799 }
800
801 return 0;
802}
803
804static int aif1clk_ev(struct snd_soc_dapm_widget *w,
805 struct snd_kcontrol *kcontrol, int event)
806{
807 struct snd_soc_codec *codec = w->codec;
808 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
809
810 switch (event) {
811 case SND_SOC_DAPM_PRE_PMU:
812 wm8994->aif1clk_enable = 1;
813 break;
a3cff81a
DP		 814 case SND_SOC_DAPM_POST_PMD:
815 wm8994->aif1clk_disable = 1;
816 break;
173efa09
DP		 817 }
818
819 return 0;
820}
821
822static int aif2clk_ev(struct snd_soc_dapm_widget *w,
823 struct snd_kcontrol *kcontrol, int event)
824{
825 struct snd_soc_codec *codec = w->codec;
826 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
827
828 switch (event) {
829 case SND_SOC_DAPM_PRE_PMU:
830 wm8994->aif2clk_enable = 1;
831 break;
a3cff81a
DP		 832 case SND_SOC_DAPM_POST_PMD:
833 wm8994->aif2clk_disable = 1;
834 break;
173efa09
DP		 835 }
836
837 return 0;
838}
839
04d28681
DP		 840static int adc_mux_ev(struct snd_soc_dapm_widget *w,
841 struct snd_kcontrol *kcontrol, int event)
842{
843 late_enable_ev(w, kcontrol, event);
844 return 0;
845}
846
b462c6e6
DP		 847static int micbias_ev(struct snd_soc_dapm_widget *w,
848 struct snd_kcontrol *kcontrol, int event)
849{
850 late_enable_ev(w, kcontrol, event);
851 return 0;
852}
853
c52fd021
DP		 854static int dac_ev(struct snd_soc_dapm_widget *w,
855 struct snd_kcontrol *kcontrol, int event)
856{
857 struct snd_soc_codec *codec = w->codec;
858 unsigned int mask = 1 << w->shift;
859
860 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
861 mask, mask);
862 return 0;
863}
864
9e6e96a1
MB		 865static const char *hp_mux_text[] = {
866 "Mixer",
867 "DAC",
868};
869
870#define WM8994_HP_ENUM(xname, xenum) \
871{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
872 .info = snd_soc_info_enum_double, \
873 .get = snd_soc_dapm_get_enum_double, \
874 .put = wm8994_put_hp_enum, \
875 .private_value = (unsigned long)&xenum }
876
877static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
878 struct snd_ctl_elem_value *ucontrol)
879{
880 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
881 struct snd_soc_codec *codec = w->codec;
882 int ret;
883
884 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
885
886 wm8994_update_class_w(codec);
887
888 return ret;
889}
890
891static const struct soc_enum hpl_enum =
892 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
893
894static const struct snd_kcontrol_new hpl_mux =
895 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
896
897static const struct soc_enum hpr_enum =
898 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
899
900static const struct snd_kcontrol_new hpr_mux =
901 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
902
903static const char *adc_mux_text[] = {
904 "ADC",
905 "DMIC",
906};
907
908static const struct soc_enum adc_enum =
909 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
910
911static const struct snd_kcontrol_new adcl_mux =
912 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
913
914static const struct snd_kcontrol_new adcr_mux =
915 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
916
917static const struct snd_kcontrol_new left_speaker_mixer[] = {
918SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
919SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
920SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
921SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
922SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
923};
924
925static const struct snd_kcontrol_new right_speaker_mixer[] = {
926SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
927SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
928SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
929SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
930SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
931};
932
933/* Debugging; dump chip status after DAPM transitions */
934static int post_ev(struct snd_soc_dapm_widget *w,
935 struct snd_kcontrol *kcontrol, int event)
936{
937 struct snd_soc_codec *codec = w->codec;
938 dev_dbg(codec->dev, "SRC status: %x\n",
939 snd_soc_read(codec,
940 WM8994_RATE_STATUS));
941 return 0;
942}
943
944static const struct snd_kcontrol_new aif1adc1l_mix[] = {
945SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
946 1, 1, 0),
947SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
948 0, 1, 0),
949};
950
951static const struct snd_kcontrol_new aif1adc1r_mix[] = {
952SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
953 1, 1, 0),
954SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
955 0, 1, 0),
956};
957
a3257ba8
MB		 958static const struct snd_kcontrol_new aif1adc2l_mix[] = {
959SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
960 1, 1, 0),
961SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
962 0, 1, 0),
963};
964
965static const struct snd_kcontrol_new aif1adc2r_mix[] = {
966SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
967 1, 1, 0),
968SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
969 0, 1, 0),
970};
971
9e6e96a1
MB		 972static const struct snd_kcontrol_new aif2dac2l_mix[] = {
973SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
974 5, 1, 0),
975SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
976 4, 1, 0),
977SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
978 2, 1, 0),
979SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
980 1, 1, 0),
981SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
982 0, 1, 0),
983};
984
985static const struct snd_kcontrol_new aif2dac2r_mix[] = {
986SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
987 5, 1, 0),
988SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
989 4, 1, 0),
990SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
991 2, 1, 0),
992SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
993 1, 1, 0),
994SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
995 0, 1, 0),
996};
997
998#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
999{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1000 .info = snd_soc_info_volsw, \
1001 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1002 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1003
1004static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1005 struct snd_ctl_elem_value *ucontrol)
1006{
1007 struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1008 struct snd_soc_codec *codec = w->codec;
1009 int ret;
1010
1011 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1012
1013 wm8994_update_class_w(codec);
1014
1015 return ret;
1016}
1017
1018static const struct snd_kcontrol_new dac1l_mix[] = {
1019WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1020 5, 1, 0),
1021WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022 4, 1, 0),
1023WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024 2, 1, 0),
1025WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026 1, 1, 0),
1027WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1028 0, 1, 0),
1029};
1030
1031static const struct snd_kcontrol_new dac1r_mix[] = {
1032WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1033 5, 1, 0),
1034WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035 4, 1, 0),
1036WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037 2, 1, 0),
1038WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039 1, 1, 0),
1040WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1041 0, 1, 0),
1042};
1043
1044static const char *sidetone_text[] = {
1045 "ADC/DMIC1", "DMIC2",
1046};
1047
1048static const struct soc_enum sidetone1_enum =
1049 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1050
1051static const struct snd_kcontrol_new sidetone1_mux =
1052 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1053
1054static const struct soc_enum sidetone2_enum =
1055 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1056
1057static const struct snd_kcontrol_new sidetone2_mux =
1058 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1059
1060static const char *aif1dac_text[] = {
1061 "AIF1DACDAT", "AIF3DACDAT",
1062};
1063
1064static const struct soc_enum aif1dac_enum =
1065 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1066
1067static const struct snd_kcontrol_new aif1dac_mux =
1068 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1069
1070static const char *aif2dac_text[] = {
1071 "AIF2DACDAT", "AIF3DACDAT",
1072};
1073
1074static const struct soc_enum aif2dac_enum =
1075 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1076
1077static const struct snd_kcontrol_new aif2dac_mux =
1078 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1079
1080static const char *aif2adc_text[] = {
1081 "AIF2ADCDAT", "AIF3DACDAT",
1082};
1083
1084static const struct soc_enum aif2adc_enum =
1085 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1086
1087static const struct snd_kcontrol_new aif2adc_mux =
1088 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1089
1090static const char *aif3adc_text[] = {
c4431df0 1091 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
9e6e96a1
MB		 1092};
1093
c4431df0 1094static const struct soc_enum wm8994_aif3adc_enum =
9e6e96a1
MB		 1095 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1096
c4431df0
MB		 1097static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1098 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1099
1100static const struct soc_enum wm8958_aif3adc_enum =
1101 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1102
1103static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1104 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1105
1106static const char *mono_pcm_out_text[] = {
1107 "None", "AIF2ADCL", "AIF2ADCR",
1108};
1109
1110static const struct soc_enum mono_pcm_out_enum =
1111 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1112
1113static const struct snd_kcontrol_new mono_pcm_out_mux =
1114 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1115
1116static const char *aif2dac_src_text[] = {
1117 "AIF2", "AIF3",
1118};
1119
1120/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1121static const struct soc_enum aif2dacl_src_enum =
1122 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1123
1124static const struct snd_kcontrol_new aif2dacl_src_mux =
1125 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1126
1127static const struct soc_enum aif2dacr_src_enum =
1128 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1129
1130static const struct snd_kcontrol_new aif2dacr_src_mux =
1131 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
9e6e96a1 1132
173efa09
DP		 1133static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1134SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1135 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1136SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1137 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1138
1139SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1140 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1141SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1146 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147
1148SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1149};
1150
1151static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1152SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1153SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0)
1154};
1155
c52fd021
DP		 1156static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1157SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1158 dac_ev, SND_SOC_DAPM_PRE_PMU),
1159SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1160 dac_ev, SND_SOC_DAPM_PRE_PMU),
1161SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1162 dac_ev, SND_SOC_DAPM_PRE_PMU),
1163SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1164 dac_ev, SND_SOC_DAPM_PRE_PMU),
1165};
1166
1167static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1168SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
0627bd25 1169SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
c52fd021
DP		 1170SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1171SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1172};
1173
04d28681
DP		 1174static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1175SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1176 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1177SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1178 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1179};
1180
1181static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1182SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1183SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1184};
1185
9e6e96a1
MB		 1186static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1187SND_SOC_DAPM_INPUT("DMIC1DAT"),
1188SND_SOC_DAPM_INPUT("DMIC2DAT"),
66b47fdb 1189SND_SOC_DAPM_INPUT("Clock"),
9e6e96a1 1190
b462c6e6
DP		 1191SND_SOC_DAPM_MICBIAS("MICBIAS", WM8994_MICBIAS, 2, 0),
1192SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1193 SND_SOC_DAPM_PRE_PMU),
1194
9e6e96a1
MB		 1195SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1196 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1197
1198SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1199SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1200SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1201
7f94de48 1202SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
9e6e96a1 1203 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
7f94de48 1204SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
9e6e96a1 1205 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
d6addcc9
MB		 1206SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1207 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
b2822a8c 1208 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1209SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1210 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
b2822a8c 1211 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1 1212
7f94de48 1213SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
9e6e96a1 1214 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
7f94de48 1215SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
9e6e96a1 1216 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
d6addcc9
MB		 1217SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1218 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
b2822a8c 1219 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
d6addcc9
MB		 1220SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1221 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
b2822a8c 1222 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
9e6e96a1
MB		 1223
1224SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1225 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1226SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1227 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1228
a3257ba8
MB		 1229SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1230 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1231SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1232 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1233
9e6e96a1
MB		 1234SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1235 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1236SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1237 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1238
1239SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1240SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1241
1242SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1243 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1244SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1245 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1246
1247SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1248 WM8994_POWER_MANAGEMENT_4, 13, 0),
1249SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1250 WM8994_POWER_MANAGEMENT_4, 12, 0),
d6addcc9
MB		 1251SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1252 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1253 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1254SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1255 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1256 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
9e6e96a1
MB		 1257
1258SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1259SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
7f94de48 1260SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
9e6e96a1
MB		 1261SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1262
1263SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1264SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1265SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
9e6e96a1
MB		 1266
1267SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1268SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1269
1270SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1271
1272SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1273SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1274SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1275SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1276
1277/* Power is done with the muxes since the ADC power also controls the
1278 * downsampling chain, the chip will automatically manage the analogue
1279 * specific portions.
1280 */
1281SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1282SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1283
9e6e96a1
MB		 1284SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1285SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1286
1287SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1288 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1289SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1290 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1291
1292SND_SOC_DAPM_POST("Debug log", post_ev),
1293};
1294
c4431df0
MB		 1295static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1296SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1297};
9e6e96a1 1298
c4431df0
MB		 1299static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1300SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1301SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1302SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1303SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1304};
1305
1306static const struct snd_soc_dapm_route intercon[] = {
9e6e96a1
MB		 1307 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1308 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1309
1310 { "DSP1CLK", NULL, "CLK_SYS" },
1311 { "DSP2CLK", NULL, "CLK_SYS" },
1312 { "DSPINTCLK", NULL, "CLK_SYS" },
1313
1314 { "AIF1ADC1L", NULL, "AIF1CLK" },
1315 { "AIF1ADC1L", NULL, "DSP1CLK" },
1316 { "AIF1ADC1R", NULL, "AIF1CLK" },
1317 { "AIF1ADC1R", NULL, "DSP1CLK" },
1318 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1319
1320 { "AIF1DAC1L", NULL, "AIF1CLK" },
1321 { "AIF1DAC1L", NULL, "DSP1CLK" },
1322 { "AIF1DAC1R", NULL, "AIF1CLK" },
1323 { "AIF1DAC1R", NULL, "DSP1CLK" },
1324 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1325
1326 { "AIF1ADC2L", NULL, "AIF1CLK" },
1327 { "AIF1ADC2L", NULL, "DSP1CLK" },
1328 { "AIF1ADC2R", NULL, "AIF1CLK" },
1329 { "AIF1ADC2R", NULL, "DSP1CLK" },
1330 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1331
1332 { "AIF1DAC2L", NULL, "AIF1CLK" },
1333 { "AIF1DAC2L", NULL, "DSP1CLK" },
1334 { "AIF1DAC2R", NULL, "AIF1CLK" },
1335 { "AIF1DAC2R", NULL, "DSP1CLK" },
1336 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1337
1338 { "AIF2ADCL", NULL, "AIF2CLK" },
1339 { "AIF2ADCL", NULL, "DSP2CLK" },
1340 { "AIF2ADCR", NULL, "AIF2CLK" },
1341 { "AIF2ADCR", NULL, "DSP2CLK" },
1342 { "AIF2ADCR", NULL, "DSPINTCLK" },
1343
1344 { "AIF2DACL", NULL, "AIF2CLK" },
1345 { "AIF2DACL", NULL, "DSP2CLK" },
1346 { "AIF2DACR", NULL, "AIF2CLK" },
1347 { "AIF2DACR", NULL, "DSP2CLK" },
1348 { "AIF2DACR", NULL, "DSPINTCLK" },
1349
1350 { "DMIC1L", NULL, "DMIC1DAT" },
1351 { "DMIC1L", NULL, "CLK_SYS" },
1352 { "DMIC1R", NULL, "DMIC1DAT" },
1353 { "DMIC1R", NULL, "CLK_SYS" },
1354 { "DMIC2L", NULL, "DMIC2DAT" },
1355 { "DMIC2L", NULL, "CLK_SYS" },
1356 { "DMIC2R", NULL, "DMIC2DAT" },
1357 { "DMIC2R", NULL, "CLK_SYS" },
1358
1359 { "ADCL", NULL, "AIF1CLK" },
1360 { "ADCL", NULL, "DSP1CLK" },
1361 { "ADCL", NULL, "DSPINTCLK" },
1362
1363 { "ADCR", NULL, "AIF1CLK" },
1364 { "ADCR", NULL, "DSP1CLK" },
1365 { "ADCR", NULL, "DSPINTCLK" },
1366
1367 { "ADCL Mux", "ADC", "ADCL" },
1368 { "ADCL Mux", "DMIC", "DMIC1L" },
1369 { "ADCR Mux", "ADC", "ADCR" },
1370 { "ADCR Mux", "DMIC", "DMIC1R" },
1371
1372 { "DAC1L", NULL, "AIF1CLK" },
1373 { "DAC1L", NULL, "DSP1CLK" },
1374 { "DAC1L", NULL, "DSPINTCLK" },
1375
1376 { "DAC1R", NULL, "AIF1CLK" },
1377 { "DAC1R", NULL, "DSP1CLK" },
1378 { "DAC1R", NULL, "DSPINTCLK" },
1379
1380 { "DAC2L", NULL, "AIF2CLK" },
1381 { "DAC2L", NULL, "DSP2CLK" },
1382 { "DAC2L", NULL, "DSPINTCLK" },
1383
1384 { "DAC2R", NULL, "AIF2DACR" },
1385 { "DAC2R", NULL, "AIF2CLK" },
1386 { "DAC2R", NULL, "DSP2CLK" },
1387 { "DAC2R", NULL, "DSPINTCLK" },
1388
1389 { "TOCLK", NULL, "CLK_SYS" },
1390
1391 /* AIF1 outputs */
1392 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1393 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1394 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1395
1396 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1397 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1398 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1399
a3257ba8
MB		 1400 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1401 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1402 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1403
1404 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1405 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1406 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1407
9e6e96a1
MB		 1408 /* Pin level routing for AIF3 */
1409 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1410 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1411 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1412 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1413
9e6e96a1
MB		 1414 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1415 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1416 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1417 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1418 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1419 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1420 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1421
1422 /* DAC1 inputs */
9e6e96a1
MB		 1423 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1424 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1425 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1426 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1427 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1428
9e6e96a1
MB		 1429 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1430 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1431 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1432 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1433 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1434
1435 /* DAC2/AIF2 outputs */
1436 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
9e6e96a1
MB		 1437 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1438 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1439 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1440 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1441 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1442
1443 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
9e6e96a1
MB		 1444 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1445 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1446 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1447 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1448 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1449
7f94de48
MB		 1450 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1451 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1452 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1453 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1454
9e6e96a1
MB		 1455 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1456
1457 /* AIF3 output */
1458 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1459 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1460 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1461 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1462 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1463 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1464 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1465 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1466
1467 /* Sidetone */
1468 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1469 { "Left Sidetone", "DMIC2", "DMIC2L" },
1470 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1471 { "Right Sidetone", "DMIC2", "DMIC2R" },
1472
1473 /* Output stages */
1474 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1475 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1476
1477 { "SPKL", "DAC1 Switch", "DAC1L" },
1478 { "SPKL", "DAC2 Switch", "DAC2L" },
1479
1480 { "SPKR", "DAC1 Switch", "DAC1R" },
1481 { "SPKR", "DAC2 Switch", "DAC2R" },
1482
1483 { "Left Headphone Mux", "DAC", "DAC1L" },
1484 { "Right Headphone Mux", "DAC", "DAC1R" },
1485};
1486
173efa09
DP		 1487static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1488 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1489 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1490 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1491 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1492 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1493 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1494 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1495 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1496};
1497
1498static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1499 { "DAC1L", NULL, "DAC1L Mixer" },
1500 { "DAC1R", NULL, "DAC1R Mixer" },
1501 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1502 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1503};
1504
6ed8f148
MB		 1505static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1506 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1507 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1508 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1509 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
b462c6e6
DP		 1510 { "MICBIAS", NULL, "CLK_SYS" },
1511 { "MICBIAS", NULL, "MICBIAS Supply" },
6ed8f148
MB		 1512};
1513
c4431df0
MB		 1514static const struct snd_soc_dapm_route wm8994_intercon[] = {
1515 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1516 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1517};
1518
1519static const struct snd_soc_dapm_route wm8958_intercon[] = {
1520 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1521 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1522
1523 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1524 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1525 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1526 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1527
1528 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1529 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1530
1531 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1532};
1533
9e6e96a1
MB		 1534/* The size in bits of the FLL divide multiplied by 10
1535 * to allow rounding later */
1536#define FIXED_FLL_SIZE ((1 << 16) * 10)
1537
1538struct fll_div {
1539 u16 outdiv;
1540 u16 n;
1541 u16 k;
1542 u16 clk_ref_div;
1543 u16 fll_fratio;
1544};
1545
1546static int wm8994_get_fll_config(struct fll_div *fll,
1547 int freq_in, int freq_out)
1548{
1549 u64 Kpart;
1550 unsigned int K, Ndiv, Nmod;
1551
1552 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1553
1554 /* Scale the input frequency down to <= 13.5MHz */
1555 fll->clk_ref_div = 0;
1556 while (freq_in > 13500000) {
1557 fll->clk_ref_div++;
1558 freq_in /= 2;
1559
1560 if (fll->clk_ref_div > 3)
1561 return -EINVAL;
1562 }
1563 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1564
1565 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1566 fll->outdiv = 3;
1567 while (freq_out * (fll->outdiv + 1) < 90000000) {
1568 fll->outdiv++;
1569 if (fll->outdiv > 63)
1570 return -EINVAL;
1571 }
1572 freq_out *= fll->outdiv + 1;
1573 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1574
1575 if (freq_in > 1000000) {
1576 fll->fll_fratio = 0;
7d48a6ac
MB		 1577 } else if (freq_in > 256000) {
1578 fll->fll_fratio = 1;
1579 freq_in *= 2;
1580 } else if (freq_in > 128000) {
1581 fll->fll_fratio = 2;
1582 freq_in *= 4;
1583 } else if (freq_in > 64000) {
9e6e96a1
MB		 1584 fll->fll_fratio = 3;
1585 freq_in *= 8;
7d48a6ac
MB		 1586 } else {
1587 fll->fll_fratio = 4;
1588 freq_in *= 16;
9e6e96a1
MB		 1589 }
1590 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1591
1592 /* Now, calculate N.K */
1593 Ndiv = freq_out / freq_in;
1594
1595 fll->n = Ndiv;
1596 Nmod = freq_out % freq_in;
1597 pr_debug("Nmod=%d\n", Nmod);
1598
1599 /* Calculate fractional part - scale up so we can round. */
1600 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1601
1602 do_div(Kpart, freq_in);
1603
1604 K = Kpart & 0xFFFFFFFF;
1605
1606 if ((K % 10) >= 5)
1607 K += 5;
1608
1609 /* Move down to proper range now rounding is done */
1610 fll->k = K / 10;
1611
1612 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1613
1614 return 0;
1615}
1616
f0fba2ad 1617static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
9e6e96a1
MB		 1618 unsigned int freq_in, unsigned int freq_out)
1619{
b2c812e2 1620 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1
MB		 1621 int reg_offset, ret;
1622 struct fll_div fll;
1623 u16 reg, aif1, aif2;
1624
1625 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1626 & WM8994_AIF1CLK_ENA;
1627
1628 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1629 & WM8994_AIF2CLK_ENA;
1630
1631 switch (id) {
1632 case WM8994_FLL1:
1633 reg_offset = 0;
1634 id = 0;
1635 break;
1636 case WM8994_FLL2:
1637 reg_offset = 0x20;
1638 id = 1;
1639 break;
1640 default:
1641 return -EINVAL;
1642 }
1643
136ff2a2 1644 switch (src) {
7add84aa
MB		 1645 case 0:
1646 /* Allow no source specification when stopping */
1647 if (freq_out)
1648 return -EINVAL;
4514e899 1649 src = wm8994->fll[id].src;
7add84aa 1650 break;
136ff2a2
MB		 1651 case WM8994_FLL_SRC_MCLK1:
1652 case WM8994_FLL_SRC_MCLK2:
1653 case WM8994_FLL_SRC_LRCLK:
1654 case WM8994_FLL_SRC_BCLK:
1655 break;
1656 default:
1657 return -EINVAL;
1658 }
1659
9e6e96a1
MB		 1660 /* Are we changing anything? */
1661 if (wm8994->fll[id].src == src &&
1662 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1663 return 0;
1664
1665 /* If we're stopping the FLL redo the old config - no
1666 * registers will actually be written but we avoid GCC flow
1667 * analysis bugs spewing warnings.
1668 */
1669 if (freq_out)
1670 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1671 else
1672 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1673 wm8994->fll[id].out);
1674 if (ret < 0)
1675 return ret;
1676
1677 /* Gate the AIF clocks while we reclock */
1678 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1679 WM8994_AIF1CLK_ENA, 0);
1680 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1681 WM8994_AIF2CLK_ENA, 0);
1682
1683 /* We always need to disable the FLL while reconfiguring */
1684 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1685 WM8994_FLL1_ENA, 0);
1686
1687 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1688 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1689 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1690 WM8994_FLL1_OUTDIV_MASK |
1691 WM8994_FLL1_FRATIO_MASK, reg);
1692
1693 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1694
1695 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1696 WM8994_FLL1_N_MASK,
1697 fll.n << WM8994_FLL1_N_SHIFT);
1698
1699 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
136ff2a2
MB		 1700 WM8994_FLL1_REFCLK_DIV_MASK |
1701 WM8994_FLL1_REFCLK_SRC_MASK,
1702 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1703 (src - 1));
9e6e96a1
MB		 1704
1705 /* Enable (with fractional mode if required) */
1706 if (freq_out) {
1707 if (fll.k)
1708 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1709 else
1710 reg = WM8994_FLL1_ENA;
1711 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1712 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1713 reg);
1714 }
1715
1716 wm8994->fll[id].in = freq_in;
1717 wm8994->fll[id].out = freq_out;
136ff2a2 1718 wm8994->fll[id].src = src;
9e6e96a1
MB		 1719
1720 /* Enable any gated AIF clocks */
1721 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1722 WM8994_AIF1CLK_ENA, aif1);
1723 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1724 WM8994_AIF2CLK_ENA, aif2);
1725
1726 configure_clock(codec);
1727
1728 return 0;
1729}
1730
f0fba2ad 1731
66b47fdb
MB		 1732static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1733
f0fba2ad
LG		 1734static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1735 unsigned int freq_in, unsigned int freq_out)
1736{
1737 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1738}
1739
9e6e96a1
MB		 1740static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1741 int clk_id, unsigned int freq, int dir)
1742{
1743 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1744 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
66b47fdb 1745 int i;
9e6e96a1
MB		 1746
1747 switch (dai->id) {
1748 case 1:
1749 case 2:
1750 break;
1751
1752 default:
1753 /* AIF3 shares clocking with AIF1/2 */
1754 return -EINVAL;
1755 }
1756
1757 switch (clk_id) {
1758 case WM8994_SYSCLK_MCLK1:
1759 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1760 wm8994->mclk[0] = freq;
1761 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1762 dai->id, freq);
1763 break;
1764
1765 case WM8994_SYSCLK_MCLK2:
1766 /* TODO: Set GPIO AF */
1767 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1768 wm8994->mclk[1] = freq;
1769 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1770 dai->id, freq);
1771 break;
1772
1773 case WM8994_SYSCLK_FLL1:
1774 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1775 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1776 break;
1777
1778 case WM8994_SYSCLK_FLL2:
1779 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1780 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1781 break;
1782
66b47fdb
MB		 1783 case WM8994_SYSCLK_OPCLK:
1784 /* Special case - a division (times 10) is given and
1785 * no effect on main clocking.
1786 */
1787 if (freq) {
1788 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1789 if (opclk_divs[i] == freq)
1790 break;
1791 if (i == ARRAY_SIZE(opclk_divs))
1792 return -EINVAL;
1793 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1794 WM8994_OPCLK_DIV_MASK, i);
1795 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1796 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1797 } else {
1798 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1799 WM8994_OPCLK_ENA, 0);
1800 }
1801
9e6e96a1
MB		 1802 default:
1803 return -EINVAL;
1804 }
1805
1806 configure_clock(codec);
1807
1808 return 0;
1809}
1810
1811static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1812 enum snd_soc_bias_level level)
1813{
3a423157 1814 struct wm8994 *control = codec->control_data;
b6b05691
MB		 1815 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1816
9e6e96a1
MB		 1817 switch (level) {
1818 case SND_SOC_BIAS_ON:
1819 break;
1820
1821 case SND_SOC_BIAS_PREPARE:
1822 /* VMID=2x40k */
1823 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1824 WM8994_VMID_SEL_MASK, 0x2);
1825 break;
1826
1827 case SND_SOC_BIAS_STANDBY:
ce6120cc 1828 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
39fb51a1
MB		 1829 pm_runtime_get_sync(codec->dev);
1830
8bc3c2c2
MB		 1831 switch (control->type) {
1832 case WM8994:
1833 if (wm8994->revision < 4) {
1834 /* Tweak DC servo and DSP
1835 * configuration for improved
1836 * performance. */
1837 snd_soc_write(codec, 0x102, 0x3);
1838 snd_soc_write(codec, 0x56, 0x3);
1839 snd_soc_write(codec, 0x817, 0);
1840 snd_soc_write(codec, 0x102, 0);
1841 }
1842 break;
1843
1844 case WM8958:
1845 if (wm8994->revision == 0) {
1846 /* Optimise performance for rev A */
1847 snd_soc_write(codec, 0x102, 0x3);
1848 snd_soc_write(codec, 0xcb, 0x81);
1849 snd_soc_write(codec, 0x817, 0);
1850 snd_soc_write(codec, 0x102, 0);
1851
1852 snd_soc_update_bits(codec,
1853 WM8958_CHARGE_PUMP_2,
1854 WM8958_CP_DISCH,
1855 WM8958_CP_DISCH);
1856 }
1857 break;
b6b05691 1858 }
9e6e96a1
MB		 1859
1860 /* Discharge LINEOUT1 & 2 */
1861 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1862 WM8994_LINEOUT1_DISCH |
1863 WM8994_LINEOUT2_DISCH,
1864 WM8994_LINEOUT1_DISCH |
1865 WM8994_LINEOUT2_DISCH);
1866
1867 /* Startup bias, VMID ramp & buffer */
1868 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1869 WM8994_STARTUP_BIAS_ENA |
1870 WM8994_VMID_BUF_ENA |
1871 WM8994_VMID_RAMP_MASK,
1872 WM8994_STARTUP_BIAS_ENA |
1873 WM8994_VMID_BUF_ENA |
1874 (0x11 << WM8994_VMID_RAMP_SHIFT));
1875
1876 /* Main bias enable, VMID=2x40k */
1877 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1878 WM8994_BIAS_ENA |
1879 WM8994_VMID_SEL_MASK,
1880 WM8994_BIAS_ENA | 0x2);
1881
1882 msleep(20);
1883 }
1884
1885 /* VMID=2x500k */
1886 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1887 WM8994_VMID_SEL_MASK, 0x4);
1888
1889 break;
1890
1891 case SND_SOC_BIAS_OFF:
ce6120cc 1892 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
d522ffbf
MB		 1893 /* Switch over to startup biases */
1894 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1895 WM8994_BIAS_SRC |
1896 WM8994_STARTUP_BIAS_ENA |
1897 WM8994_VMID_BUF_ENA |
1898 WM8994_VMID_RAMP_MASK,
1899 WM8994_BIAS_SRC |
1900 WM8994_STARTUP_BIAS_ENA |
1901 WM8994_VMID_BUF_ENA |
1902 (1 << WM8994_VMID_RAMP_SHIFT));
9e6e96a1 1903
d522ffbf
MB		 1904 /* Disable main biases */
1905 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1906 WM8994_BIAS_ENA |
1907 WM8994_VMID_SEL_MASK, 0);
9e6e96a1 1908
d522ffbf
MB		 1909 /* Discharge line */
1910 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1911 WM8994_LINEOUT1_DISCH |
1912 WM8994_LINEOUT2_DISCH,
1913 WM8994_LINEOUT1_DISCH |
1914 WM8994_LINEOUT2_DISCH);
9e6e96a1 1915
d522ffbf 1916 msleep(5);
9e6e96a1 1917
d522ffbf
MB		 1918 /* Switch off startup biases */
1919 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1920 WM8994_BIAS_SRC |
1921 WM8994_STARTUP_BIAS_ENA |
1922 WM8994_VMID_BUF_ENA |
1923 WM8994_VMID_RAMP_MASK, 0);
39fb51a1 1924
fbbf5920
MB		 1925 wm8994->cur_fw = NULL;
1926
39fb51a1 1927 pm_runtime_put(codec->dev);
d522ffbf 1928 }
9e6e96a1
MB		 1929 break;
1930 }
ce6120cc 1931 codec->dapm.bias_level = level;
9e6e96a1
MB		 1932 return 0;
1933}
1934
1935static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1936{
1937 struct snd_soc_codec *codec = dai->codec;
c4431df0 1938 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 1939 int ms_reg;
1940 int aif1_reg;
1941 int ms = 0;
1942 int aif1 = 0;
1943
1944 switch (dai->id) {
1945 case 1:
1946 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1947 aif1_reg = WM8994_AIF1_CONTROL_1;
1948 break;
1949 case 2:
1950 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1951 aif1_reg = WM8994_AIF2_CONTROL_1;
1952 break;
1953 default:
1954 return -EINVAL;
1955 }
1956
1957 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1958 case SND_SOC_DAIFMT_CBS_CFS:
1959 break;
1960 case SND_SOC_DAIFMT_CBM_CFM:
1961 ms = WM8994_AIF1_MSTR;
1962 break;
1963 default:
1964 return -EINVAL;
1965 }
1966
1967 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1968 case SND_SOC_DAIFMT_DSP_B:
1969 aif1 |= WM8994_AIF1_LRCLK_INV;
1970 case SND_SOC_DAIFMT_DSP_A:
1971 aif1 |= 0x18;
1972 break;
1973 case SND_SOC_DAIFMT_I2S:
1974 aif1 |= 0x10;
1975 break;
1976 case SND_SOC_DAIFMT_RIGHT_J:
1977 break;
1978 case SND_SOC_DAIFMT_LEFT_J:
1979 aif1 |= 0x8;
1980 break;
1981 default:
1982 return -EINVAL;
1983 }
1984
1985 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1986 case SND_SOC_DAIFMT_DSP_A:
1987 case SND_SOC_DAIFMT_DSP_B:
1988 /* frame inversion not valid for DSP modes */
1989 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1990 case SND_SOC_DAIFMT_NB_NF:
1991 break;
1992 case SND_SOC_DAIFMT_IB_NF:
1993 aif1 |= WM8994_AIF1_BCLK_INV;
1994 break;
1995 default:
1996 return -EINVAL;
1997 }
1998 break;
1999
2000 case SND_SOC_DAIFMT_I2S:
2001 case SND_SOC_DAIFMT_RIGHT_J:
2002 case SND_SOC_DAIFMT_LEFT_J:
2003 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2004 case SND_SOC_DAIFMT_NB_NF:
2005 break;
2006 case SND_SOC_DAIFMT_IB_IF:
2007 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2008 break;
2009 case SND_SOC_DAIFMT_IB_NF:
2010 aif1 |= WM8994_AIF1_BCLK_INV;
2011 break;
2012 case SND_SOC_DAIFMT_NB_IF:
2013 aif1 |= WM8994_AIF1_LRCLK_INV;
2014 break;
2015 default:
2016 return -EINVAL;
2017 }
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
c4431df0
MB		 2023 /* The AIF2 format configuration needs to be mirrored to AIF3
2024 * on WM8958 if it's in use so just do it all the time. */
2025 if (control->type == WM8958 && dai->id == 2)
2026 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2027 WM8994_AIF1_LRCLK_INV |
2028 WM8958_AIF3_FMT_MASK, aif1);
2029
9e6e96a1
MB		 2030 snd_soc_update_bits(codec, aif1_reg,
2031 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2032 WM8994_AIF1_FMT_MASK,
2033 aif1);
2034 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2035 ms);
2036
2037 return 0;
2038}
2039
2040static struct {
2041 int val, rate;
2042} srs[] = {
2043 { 0, 8000 },
2044 { 1, 11025 },
2045 { 2, 12000 },
2046 { 3, 16000 },
2047 { 4, 22050 },
2048 { 5, 24000 },
2049 { 6, 32000 },
2050 { 7, 44100 },
2051 { 8, 48000 },
2052 { 9, 88200 },
2053 { 10, 96000 },
2054};
2055
2056static int fs_ratios[] = {
2057 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2058};
2059
2060static int bclk_divs[] = {
2061 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2062 640, 880, 960, 1280, 1760, 1920
2063};
2064
2065static int wm8994_hw_params(struct snd_pcm_substream *substream,
2066 struct snd_pcm_hw_params *params,
2067 struct snd_soc_dai *dai)
2068{
2069 struct snd_soc_codec *codec = dai->codec;
c4431df0 2070 struct wm8994 *control = codec->control_data;
b2c812e2 2071 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
9e6e96a1 2072 int aif1_reg;
b1e43d93 2073 int aif2_reg;
9e6e96a1
MB		 2074 int bclk_reg;
2075 int lrclk_reg;
2076 int rate_reg;
2077 int aif1 = 0;
b1e43d93 2078 int aif2 = 0;
9e6e96a1
MB		 2079 int bclk = 0;
2080 int lrclk = 0;
2081 int rate_val = 0;
2082 int id = dai->id - 1;
2083
2084 int i, cur_val, best_val, bclk_rate, best;
2085
2086 switch (dai->id) {
2087 case 1:
2088 aif1_reg = WM8994_AIF1_CONTROL_1;
b1e43d93 2089 aif2_reg = WM8994_AIF1_CONTROL_2;
9e6e96a1
MB		 2090 bclk_reg = WM8994_AIF1_BCLK;
2091 rate_reg = WM8994_AIF1_RATE;
2092 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2093 wm8994->lrclk_shared[0]) {
9e6e96a1 2094 lrclk_reg = WM8994_AIF1DAC_LRCLK;
7d83d213 2095 } else {
9e6e96a1 2096 lrclk_reg = WM8994_AIF1ADC_LRCLK;
7d83d213
MB		 2097 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2098 }
9e6e96a1
MB		 2099 break;
2100 case 2:
2101 aif1_reg = WM8994_AIF2_CONTROL_1;
b1e43d93 2102 aif2_reg = WM8994_AIF2_CONTROL_2;
9e6e96a1
MB		 2103 bclk_reg = WM8994_AIF2_BCLK;
2104 rate_reg = WM8994_AIF2_RATE;
2105 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
7d83d213 2106 wm8994->lrclk_shared[1]) {
9e6e96a1 2107 lrclk_reg = WM8994_AIF2DAC_LRCLK;
7d83d213 2108 } else {
9e6e96a1 2109 lrclk_reg = WM8994_AIF2ADC_LRCLK;
7d83d213
MB		 2110 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2111 }
9e6e96a1 2112 break;
c4431df0
MB		 2113 case 3:
2114 switch (control->type) {
2115 case WM8958:
2116 aif1_reg = WM8958_AIF3_CONTROL_1;
2117 break;
2118 default:
2119 return 0;
2120 }
9e6e96a1
MB		 2121 default:
2122 return -EINVAL;
2123 }
2124
2125 bclk_rate = params_rate(params) * 2;
2126 switch (params_format(params)) {
2127 case SNDRV_PCM_FORMAT_S16_LE:
2128 bclk_rate *= 16;
2129 break;
2130 case SNDRV_PCM_FORMAT_S20_3LE:
2131 bclk_rate *= 20;
2132 aif1 |= 0x20;
2133 break;
2134 case SNDRV_PCM_FORMAT_S24_LE:
2135 bclk_rate *= 24;
2136 aif1 |= 0x40;
2137 break;
2138 case SNDRV_PCM_FORMAT_S32_LE:
2139 bclk_rate *= 32;
2140 aif1 |= 0x60;
2141 break;
2142 default:
2143 return -EINVAL;
2144 }
2145
2146 /* Try to find an appropriate sample rate; look for an exact match. */
2147 for (i = 0; i < ARRAY_SIZE(srs); i++)
2148 if (srs[i].rate == params_rate(params))
2149 break;
2150 if (i == ARRAY_SIZE(srs))
2151 return -EINVAL;
2152 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2153
2154 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2155 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2156 dai->id, wm8994->aifclk[id], bclk_rate);
2157
b1e43d93
MB		 2158 if (params_channels(params) == 1 &&
2159 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2160 aif2 |= WM8994_AIF1_MONO;
2161
9e6e96a1
MB		 2162 if (wm8994->aifclk[id] == 0) {
2163 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2164 return -EINVAL;
2165 }
2166
2167 /* AIFCLK/fs ratio; look for a close match in either direction */
2168 best = 0;
2169 best_val = abs((fs_ratios[0] * params_rate(params))
2170 - wm8994->aifclk[id]);
2171 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2172 cur_val = abs((fs_ratios[i] * params_rate(params))
2173 - wm8994->aifclk[id]);
2174 if (cur_val >= best_val)
2175 continue;
2176 best = i;
2177 best_val = cur_val;
2178 }
2179 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2180 dai->id, fs_ratios[best]);
2181 rate_val |= best;
2182
2183 /* We may not get quite the right frequency if using
2184 * approximate clocks so look for the closest match that is
2185 * higher than the target (we need to ensure that there enough
2186 * BCLKs to clock out the samples).
2187 */
2188 best = 0;
2189 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
07cd8ada 2190 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
9e6e96a1
MB		 2191 if (cur_val < 0) /* BCLK table is sorted */
2192 break;
2193 best = i;
2194 }
07cd8ada 2195 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
9e6e96a1
MB		 2196 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2197 bclk_divs[best], bclk_rate);
2198 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2199
2200 lrclk = bclk_rate / params_rate(params);
2201 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2202 lrclk, bclk_rate / lrclk);
2203
2204 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
b1e43d93 2205 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
9e6e96a1
MB		 2206 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2207 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2208 lrclk);
2209 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2210 WM8994_AIF1CLK_RATE_MASK, rate_val);
2211
2212 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2213 switch (dai->id) {
2214 case 1:
2215 wm8994->dac_rates[0] = params_rate(params);
2216 wm8994_set_retune_mobile(codec, 0);
2217 wm8994_set_retune_mobile(codec, 1);
2218 break;
2219 case 2:
2220 wm8994->dac_rates[1] = params_rate(params);
2221 wm8994_set_retune_mobile(codec, 2);
2222 break;
2223 }
2224 }
2225
2226 return 0;
2227}
2228
c4431df0
MB		 2229static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2230 struct snd_pcm_hw_params *params,
2231 struct snd_soc_dai *dai)
2232{
2233 struct snd_soc_codec *codec = dai->codec;
2234 struct wm8994 *control = codec->control_data;
2235 int aif1_reg;
2236 int aif1 = 0;
2237
2238 switch (dai->id) {
2239 case 3:
2240 switch (control->type) {
2241 case WM8958:
2242 aif1_reg = WM8958_AIF3_CONTROL_1;
2243 break;
2244 default:
2245 return 0;
2246 }
2247 default:
2248 return 0;
2249 }
2250
2251 switch (params_format(params)) {
2252 case SNDRV_PCM_FORMAT_S16_LE:
2253 break;
2254 case SNDRV_PCM_FORMAT_S20_3LE:
2255 aif1 |= 0x20;
2256 break;
2257 case SNDRV_PCM_FORMAT_S24_LE:
2258 aif1 |= 0x40;
2259 break;
2260 case SNDRV_PCM_FORMAT_S32_LE:
2261 aif1 |= 0x60;
2262 break;
2263 default:
2264 return -EINVAL;
2265 }
2266
2267 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2268}
2269
9e6e96a1
MB		 2270static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2271{
2272 struct snd_soc_codec *codec = codec_dai->codec;
2273 int mute_reg;
2274 int reg;
2275
2276 switch (codec_dai->id) {
2277 case 1:
2278 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2279 break;
2280 case 2:
2281 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2282 break;
2283 default:
2284 return -EINVAL;
2285 }
2286
2287 if (mute)
2288 reg = WM8994_AIF1DAC1_MUTE;
2289 else
2290 reg = 0;
2291
2292 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2293
2294 return 0;
2295}
2296
778a76e2
MB		 2297static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2298{
2299 struct snd_soc_codec *codec = codec_dai->codec;
2300 int reg, val, mask;
2301
2302 switch (codec_dai->id) {
2303 case 1:
2304 reg = WM8994_AIF1_MASTER_SLAVE;
2305 mask = WM8994_AIF1_TRI;
2306 break;
2307 case 2:
2308 reg = WM8994_AIF2_MASTER_SLAVE;
2309 mask = WM8994_AIF2_TRI;
2310 break;
2311 case 3:
2312 reg = WM8994_POWER_MANAGEMENT_6;
2313 mask = WM8994_AIF3_TRI;
2314 break;
2315 default:
2316 return -EINVAL;
2317 }
2318
2319 if (tristate)
2320 val = mask;
2321 else
2322 val = 0;
2323
78b3fb46 2324 return snd_soc_update_bits(codec, reg, mask, val);
778a76e2
MB		 2325}
2326
9e6e96a1
MB		 2327#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2328
2329#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3079aed5 2330 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
9e6e96a1
MB		 2331
2332static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2333 .set_sysclk = wm8994_set_dai_sysclk,
2334 .set_fmt = wm8994_set_dai_fmt,
2335 .hw_params = wm8994_hw_params,
2336 .digital_mute = wm8994_aif_mute,
2337 .set_pll = wm8994_set_fll,
778a76e2 2338 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2339};
2340
2341static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2342 .set_sysclk = wm8994_set_dai_sysclk,
2343 .set_fmt = wm8994_set_dai_fmt,
2344 .hw_params = wm8994_hw_params,
2345 .digital_mute = wm8994_aif_mute,
2346 .set_pll = wm8994_set_fll,
778a76e2
MB		 2347 .set_tristate = wm8994_set_tristate,
2348};
2349
2350static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
c4431df0 2351 .hw_params = wm8994_aif3_hw_params,
778a76e2 2352 .set_tristate = wm8994_set_tristate,
9e6e96a1
MB		 2353};
2354
f0fba2ad 2355static struct snd_soc_dai_driver wm8994_dai[] = {
9e6e96a1 2356 {
f0fba2ad 2357 .name = "wm8994-aif1",
8c7f78b3 2358 .id = 1,
9e6e96a1
MB		 2359 .playback = {
2360 .stream_name = "AIF1 Playback",
b1e43d93 2361 .channels_min = 1,
9e6e96a1
MB		 2362 .channels_max = 2,
2363 .rates = WM8994_RATES,
2364 .formats = WM8994_FORMATS,
2365 },
2366 .capture = {
2367 .stream_name = "AIF1 Capture",
b1e43d93 2368 .channels_min = 1,
9e6e96a1
MB		 2369 .channels_max = 2,
2370 .rates = WM8994_RATES,
2371 .formats = WM8994_FORMATS,
2372 },
2373 .ops = &wm8994_aif1_dai_ops,
2374 },
2375 {
f0fba2ad 2376 .name = "wm8994-aif2",
8c7f78b3 2377 .id = 2,
9e6e96a1
MB		 2378 .playback = {
2379 .stream_name = "AIF2 Playback",
b1e43d93 2380 .channels_min = 1,
9e6e96a1
MB		 2381 .channels_max = 2,
2382 .rates = WM8994_RATES,
2383 .formats = WM8994_FORMATS,
2384 },
2385 .capture = {
2386 .stream_name = "AIF2 Capture",
b1e43d93 2387 .channels_min = 1,
9e6e96a1
MB		 2388 .channels_max = 2,
2389 .rates = WM8994_RATES,
2390 .formats = WM8994_FORMATS,
2391 },
2392 .ops = &wm8994_aif2_dai_ops,
2393 },
2394 {
f0fba2ad 2395 .name = "wm8994-aif3",
8c7f78b3 2396 .id = 3,
9e6e96a1
MB		 2397 .playback = {
2398 .stream_name = "AIF3 Playback",
b1e43d93 2399 .channels_min = 1,
9e6e96a1
MB		 2400 .channels_max = 2,
2401 .rates = WM8994_RATES,
2402 .formats = WM8994_FORMATS,
2403 },
a8462bde 2404 .capture = {
9e6e96a1 2405 .stream_name = "AIF3 Capture",
b1e43d93 2406 .channels_min = 1,
9e6e96a1
MB		 2407 .channels_max = 2,
2408 .rates = WM8994_RATES,
2409 .formats = WM8994_FORMATS,
2410 },
778a76e2 2411 .ops = &wm8994_aif3_dai_ops,
9e6e96a1
MB		 2412 }
2413};
9e6e96a1
MB		 2414
2415#ifdef CONFIG_PM
f0fba2ad 2416static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
9e6e96a1 2417{
b2c812e2 2418 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ca629928 2419 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 2420 int i, ret;
2421
ca629928
MB		 2422 switch (control->type) {
2423 case WM8994:
2424 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2425 break;
2426 case WM8958:
2427 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2428 WM8958_MICD_ENA, 0);
2429 break;
2430 }
2431
9e6e96a1
MB		 2432 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2433 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
f701a2e5 2434 sizeof(struct wm8994_fll_config));
f0fba2ad 2435 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
9e6e96a1
MB		 2436 if (ret < 0)
2437 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2438 i + 1, ret);
2439 }
2440
2441 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2442
2443 return 0;
2444}
2445
f0fba2ad 2446static int wm8994_resume(struct snd_soc_codec *codec)
9e6e96a1 2447{
b2c812e2 2448 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
ca629928 2449 struct wm8994 *control = codec->control_data;
9e6e96a1 2450 int i, ret;
c52fd021
DP		 2451 unsigned int val, mask;
2452
2453 if (wm8994->revision < 4) {
2454 /* force a HW read */
2455 val = wm8994_reg_read(codec->control_data,
2456 WM8994_POWER_MANAGEMENT_5);
2457
2458 /* modify the cache only */
2459 codec->cache_only = 1;
2460 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2461 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2462 val &= mask;
2463 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2464 mask, val);
2465 codec->cache_only = 0;
2466 }
9e6e96a1
MB		 2467
2468 /* Restore the registers */
ca9aef50
MB		 2469 ret = snd_soc_cache_sync(codec);
2470 if (ret != 0)
2471 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
9e6e96a1
MB		 2472
2473 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2474
2475 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
6a2f1ee1
MB		 2476 if (!wm8994->fll_suspend[i].out)
2477 continue;
2478
f0fba2ad 2479 ret = _wm8994_set_fll(codec, i + 1,
9e6e96a1
MB		 2480 wm8994->fll_suspend[i].src,
2481 wm8994->fll_suspend[i].in,
2482 wm8994->fll_suspend[i].out);
2483 if (ret < 0)
2484 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2485 i + 1, ret);
2486 }
2487
ca629928
MB		 2488 switch (control->type) {
2489 case WM8994:
2490 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2491 snd_soc_update_bits(codec, WM8994_MICBIAS,
2492 WM8994_MICD_ENA, WM8994_MICD_ENA);
2493 break;
2494 case WM8958:
2495 if (wm8994->jack_cb)
2496 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2497 WM8958_MICD_ENA, WM8958_MICD_ENA);
2498 break;
2499 }
2500
9e6e96a1
MB		 2501 return 0;
2502}
2503#else
2504#define wm8994_suspend NULL
2505#define wm8994_resume NULL
2506#endif
2507
2508static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2509{
f0fba2ad 2510 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2511 struct wm8994_pdata *pdata = wm8994->pdata;
2512 struct snd_kcontrol_new controls[] = {
2513 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2514 wm8994->retune_mobile_enum,
2515 wm8994_get_retune_mobile_enum,
2516 wm8994_put_retune_mobile_enum),
2517 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2518 wm8994->retune_mobile_enum,
2519 wm8994_get_retune_mobile_enum,
2520 wm8994_put_retune_mobile_enum),
2521 SOC_ENUM_EXT("AIF2 EQ Mode",
2522 wm8994->retune_mobile_enum,
2523 wm8994_get_retune_mobile_enum,
2524 wm8994_put_retune_mobile_enum),
2525 };
2526 int ret, i, j;
2527 const char **t;
2528
2529 /* We need an array of texts for the enum API but the number
2530 * of texts is likely to be less than the number of
2531 * configurations due to the sample rate dependency of the
2532 * configurations. */
2533 wm8994->num_retune_mobile_texts = 0;
2534 wm8994->retune_mobile_texts = NULL;
2535 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2536 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2537 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2538 wm8994->retune_mobile_texts[j]) == 0)
2539 break;
2540 }
2541
2542 if (j != wm8994->num_retune_mobile_texts)
2543 continue;
2544
2545 /* Expand the array... */
2546 t = krealloc(wm8994->retune_mobile_texts,
2547 sizeof(char *) *
2548 (wm8994->num_retune_mobile_texts + 1),
2549 GFP_KERNEL);
2550 if (t == NULL)
2551 continue;
2552
2553 /* ...store the new entry... */
2554 t[wm8994->num_retune_mobile_texts] =
2555 pdata->retune_mobile_cfgs[i].name;
2556
2557 /* ...and remember the new version. */
2558 wm8994->num_retune_mobile_texts++;
2559 wm8994->retune_mobile_texts = t;
2560 }
2561
2562 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2563 wm8994->num_retune_mobile_texts);
2564
2565 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2566 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2567
f0fba2ad 2568 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2569 ARRAY_SIZE(controls));
2570 if (ret != 0)
f0fba2ad 2571 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2572 "Failed to add ReTune Mobile controls: %d\n", ret);
2573}
2574
2575static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2576{
f0fba2ad 2577 struct snd_soc_codec *codec = wm8994->codec;
9e6e96a1
MB		 2578 struct wm8994_pdata *pdata = wm8994->pdata;
2579 int ret, i;
2580
2581 if (!pdata)
2582 return;
2583
2584 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2585 pdata->lineout2_diff,
2586 pdata->lineout1fb,
2587 pdata->lineout2fb,
2588 pdata->jd_scthr,
2589 pdata->jd_thr,
2590 pdata->micbias1_lvl,
2591 pdata->micbias2_lvl);
2592
2593 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2594
2595 if (pdata->num_drc_cfgs) {
2596 struct snd_kcontrol_new controls[] = {
2597 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2598 wm8994_get_drc_enum, wm8994_put_drc_enum),
2599 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2600 wm8994_get_drc_enum, wm8994_put_drc_enum),
2601 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2602 wm8994_get_drc_enum, wm8994_put_drc_enum),
2603 };
2604
2605 /* We need an array of texts for the enum API */
2606 wm8994->drc_texts = kmalloc(sizeof(char *)
2607 * pdata->num_drc_cfgs, GFP_KERNEL);
2608 if (!wm8994->drc_texts) {
f0fba2ad 2609 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2610 "Failed to allocate %d DRC config texts\n",
2611 pdata->num_drc_cfgs);
2612 return;
2613 }
2614
2615 for (i = 0; i < pdata->num_drc_cfgs; i++)
2616 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2617
2618 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2619 wm8994->drc_enum.texts = wm8994->drc_texts;
2620
f0fba2ad 2621 ret = snd_soc_add_controls(wm8994->codec, controls,
9e6e96a1
MB		 2622 ARRAY_SIZE(controls));
2623 if (ret != 0)
f0fba2ad 2624 dev_err(wm8994->codec->dev,
9e6e96a1
MB		 2625 "Failed to add DRC mode controls: %d\n", ret);
2626
2627 for (i = 0; i < WM8994_NUM_DRC; i++)
2628 wm8994_set_drc(codec, i);
2629 }
2630
2631 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2632 pdata->num_retune_mobile_cfgs);
2633
2634 if (pdata->num_retune_mobile_cfgs)
2635 wm8994_handle_retune_mobile_pdata(wm8994);
2636 else
f0fba2ad 2637 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
9e6e96a1 2638 ARRAY_SIZE(wm8994_eq_controls));
48e028ec
MB		 2639
2640 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2641 if (pdata->micbias[i]) {
2642 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2643 pdata->micbias[i] & 0xffff);
2644 }
2645 }
9e6e96a1
MB		 2646}
2647
88766984
MB		 2648/**
2649 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2650 *
2651 * @codec: WM8994 codec
2652 * @jack: jack to report detection events on
2653 * @micbias: microphone bias to detect on
2654 * @det: value to report for presence detection
2655 * @shrt: value to report for short detection
2656 *
2657 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2658 * being used to bring out signals to the processor then only platform
5ab230a7 2659 * data configuration is needed for WM8994 and processor GPIOs should
88766984
MB		 2660 * be configured using snd_soc_jack_add_gpios() instead.
2661 *
2662 * Configuration of detection levels is available via the micbias1_lvl
2663 * and micbias2_lvl platform data members.
2664 */
2665int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2666 int micbias, int det, int shrt)
2667{
b2c812e2 2668 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
88766984 2669 struct wm8994_micdet *micdet;
3a423157 2670 struct wm8994 *control = codec->control_data;
88766984
MB		 2671 int reg;
2672
3a423157
MB		 2673 if (control->type != WM8994)
2674 return -EINVAL;
2675
88766984
MB		 2676 switch (micbias) {
2677 case 1:
2678 micdet = &wm8994->micdet[0];
2679 break;
2680 case 2:
2681 micdet = &wm8994->micdet[1];
2682 break;
2683 default:
2684 return -EINVAL;
2685 }
2686
2687 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2688 micbias, det, shrt);
2689
2690 /* Store the configuration */
2691 micdet->jack = jack;
2692 micdet->det = det;
2693 micdet->shrt = shrt;
2694
2695 /* If either of the jacks is set up then enable detection */
2696 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2697 reg = WM8994_MICD_ENA;
2698 else
2699 reg = 0;
2700
2701 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2702
2703 return 0;
2704}
2705EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2706
2707static irqreturn_t wm8994_mic_irq(int irq, void *data)
2708{
2709 struct wm8994_priv *priv = data;
f0fba2ad 2710 struct snd_soc_codec *codec = priv->codec;
88766984
MB		 2711 int reg;
2712 int report;
2713
7116f452 2714#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2715 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2716#endif
2bbb5d66 2717
88766984
MB		 2718 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2719 if (reg < 0) {
2720 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2721 reg);
2722 return IRQ_HANDLED;
2723 }
2724
2725 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2726
2727 report = 0;
2728 if (reg & WM8994_MIC1_DET_STS)
2729 report |= priv->micdet[0].det;
2730 if (reg & WM8994_MIC1_SHRT_STS)
2731 report |= priv->micdet[0].shrt;
2732 snd_soc_jack_report(priv->micdet[0].jack, report,
2733 priv->micdet[0].det | priv->micdet[0].shrt);
2734
2735 report = 0;
2736 if (reg & WM8994_MIC2_DET_STS)
2737 report |= priv->micdet[1].det;
2738 if (reg & WM8994_MIC2_SHRT_STS)
2739 report |= priv->micdet[1].shrt;
2740 snd_soc_jack_report(priv->micdet[1].jack, report,
2741 priv->micdet[1].det | priv->micdet[1].shrt);
2742
2743 return IRQ_HANDLED;
2744}
2745
821edd2f
MB		 2746/* Default microphone detection handler for WM8958 - the user can
2747 * override this if they wish.
2748 */
2749static void wm8958_default_micdet(u16 status, void *data)
2750{
2751 struct snd_soc_codec *codec = data;
2752 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2753 int report = 0;
2754
2755 /* If nothing present then clear our statuses */
864c4bd2 2756 if (!(status & WM8958_MICD_STS))
821edd2f 2757 goto done;
821edd2f 2758
864c4bd2 2759 report = SND_JACK_MICROPHONE;
821edd2f
MB		 2760
2761 /* Everything else is buttons; just assign slots */
864c4bd2 2762 if (status & 0x1c0)
821edd2f 2763 report |= SND_JACK_BTN_0;
821edd2f
MB		 2764
2765done:
406e56c9 2766 snd_soc_jack_report(wm8994->micdet[0].jack, report,
864c4bd2 2767 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
821edd2f
MB		 2768}
2769
2770/**
2771 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2772 *
2773 * @codec: WM8958 codec
2774 * @jack: jack to report detection events on
2775 *
2776 * Enable microphone detection functionality for the WM8958. By
2777 * default simple detection which supports the detection of up to 6
2778 * buttons plus video and microphone functionality is supported.
2779 *
2780 * The WM8958 has an advanced jack detection facility which is able to
2781 * support complex accessory detection, especially when used in
2782 * conjunction with external circuitry. In order to provide maximum
2783 * flexiblity a callback is provided which allows a completely custom
2784 * detection algorithm.
2785 */
2786int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2787 wm8958_micdet_cb cb, void *cb_data)
2788{
2789 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2790 struct wm8994 *control = codec->control_data;
2791
2792 if (control->type != WM8958)
2793 return -EINVAL;
2794
2795 if (jack) {
2796 if (!cb) {
2797 dev_dbg(codec->dev, "Using default micdet callback\n");
2798 cb = wm8958_default_micdet;
2799 cb_data = codec;
2800 }
2801
2802 wm8994->micdet[0].jack = jack;
2803 wm8994->jack_cb = cb;
2804 wm8994->jack_cb_data = cb_data;
2805
2806 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2807 WM8958_MICD_ENA, WM8958_MICD_ENA);
2808 } else {
2809 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2810 WM8958_MICD_ENA, 0);
2811 }
2812
2813 return 0;
2814}
2815EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2816
2817static irqreturn_t wm8958_mic_irq(int irq, void *data)
2818{
2819 struct wm8994_priv *wm8994 = data;
2820 struct snd_soc_codec *codec = wm8994->codec;
2821 int reg;
2822
2823 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2824 if (reg < 0) {
2825 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2826 reg);
2827 return IRQ_NONE;
2828 }
2829
2830 if (!(reg & WM8958_MICD_VALID)) {
2831 dev_dbg(codec->dev, "Mic detect data not valid\n");
2832 goto out;
2833 }
2834
7116f452 2835#ifndef CONFIG_SND_SOC_WM8994_MODULE
2bbb5d66 2836 trace_snd_soc_jack_irq(dev_name(codec->dev));
7116f452 2837#endif
2bbb5d66 2838
821edd2f
MB		 2839 if (wm8994->jack_cb)
2840 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2841 else
2842 dev_warn(codec->dev, "Accessory detection with no callback\n");
2843
2844out:
2845 return IRQ_HANDLED;
2846}
2847
f0fba2ad 2848static int wm8994_codec_probe(struct snd_soc_codec *codec)
9e6e96a1 2849{
3a423157 2850 struct wm8994 *control;
9e6e96a1 2851 struct wm8994_priv *wm8994;
ce6120cc 2852 struct snd_soc_dapm_context *dapm = &codec->dapm;
ec62dbd7 2853 int ret, i;
9e6e96a1 2854
f0fba2ad 2855 codec->control_data = dev_get_drvdata(codec->dev->parent);
3a423157 2856 control = codec->control_data;
9e6e96a1
MB		 2857
2858 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
f0fba2ad 2859 if (wm8994 == NULL)
9e6e96a1 2860 return -ENOMEM;
b2c812e2 2861 snd_soc_codec_set_drvdata(codec, wm8994);
f0fba2ad
LG		 2862
2863 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2864 wm8994->codec = codec;
9e6e96a1 2865
9b7c525d
MB		 2866 if (wm8994->pdata && wm8994->pdata->micdet_irq)
2867 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2868 else if (wm8994->pdata && wm8994->pdata->irq_base)
2869 wm8994->micdet_irq = wm8994->pdata->irq_base +
2870 WM8994_IRQ_MIC1_DET;
2871
39fb51a1
MB		 2872 pm_runtime_enable(codec->dev);
2873 pm_runtime_resume(codec->dev);
2874
ca9aef50
MB		 2875 /* Read our current status back from the chip - we don't want to
2876 * reset as this may interfere with the GPIO or LDO operation. */
2877 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
d4754ec9 2878 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
ca9aef50 2879 continue;
9e6e96a1 2880
ca9aef50
MB		 2881 ret = wm8994_reg_read(codec->control_data, i);
2882 if (ret <= 0)
2883 continue;
2884
2885 ret = snd_soc_cache_write(codec, i, ret);
2886 if (ret != 0) {
2887 dev_err(codec->dev,
2888 "Failed to initialise cache for 0x%x: %d\n",
2889 i, ret);
2890 goto err;
2891 }
2892 }
9e6e96a1
MB		 2893
2894 /* Set revision-specific configuration */
b6b05691 2895 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
3a423157
MB		 2896 switch (control->type) {
2897 case WM8994:
2898 switch (wm8994->revision) {
2899 case 2:
2900 case 3:
2901 wm8994->hubs.dcs_codes = -5;
2902 wm8994->hubs.hp_startup_mode = 1;
2903 wm8994->hubs.dcs_readback_mode = 1;
2904 break;
2905 default:
2906 wm8994->hubs.dcs_readback_mode = 1;
2907 break;
2908 }
2909
2910 case WM8958:
8437f700 2911 wm8994->hubs.dcs_readback_mode = 1;
9e6e96a1 2912 break;
3a423157 2913
9e6e96a1
MB		 2914 default:
2915 break;
2916 }
9e6e96a1 2917
3a423157
MB		 2918 switch (control->type) {
2919 case WM8994:
9b7c525d
MB		 2920 if (wm8994->micdet_irq) {
2921 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2922 wm8994_mic_irq,
2923 IRQF_TRIGGER_RISING,
2924 "Mic1 detect",
2925 wm8994);
2926 if (ret != 0)
2927 dev_warn(codec->dev,
2928 "Failed to request Mic1 detect IRQ: %d\n",
2929 ret);
2930 }
3a423157
MB		 2931
2932 ret = wm8994_request_irq(codec->control_data,
2933 WM8994_IRQ_MIC1_SHRT,
2934 wm8994_mic_irq, "Mic 1 short",
2935 wm8994);
2936 if (ret != 0)
2937 dev_warn(codec->dev,
2938 "Failed to request Mic1 short IRQ: %d\n",
2939 ret);
2940
2941 ret = wm8994_request_irq(codec->control_data,
2942 WM8994_IRQ_MIC2_DET,
2943 wm8994_mic_irq, "Mic 2 detect",
2944 wm8994);
2945 if (ret != 0)
2946 dev_warn(codec->dev,
2947 "Failed to request Mic2 detect IRQ: %d\n",
2948 ret);
2949
2950 ret = wm8994_request_irq(codec->control_data,
2951 WM8994_IRQ_MIC2_SHRT,
2952 wm8994_mic_irq, "Mic 2 short",
2953 wm8994);
2954 if (ret != 0)
2955 dev_warn(codec->dev,
2956 "Failed to request Mic2 short IRQ: %d\n",
2957 ret);
2958 break;
821edd2f
MB		 2959
2960 case WM8958:
9b7c525d
MB		 2961 if (wm8994->micdet_irq) {
2962 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
2963 wm8958_mic_irq,
2964 IRQF_TRIGGER_RISING,
2965 "Mic detect",
2966 wm8994);
2967 if (ret != 0)
2968 dev_warn(codec->dev,
2969 "Failed to request Mic detect IRQ: %d\n",
2970 ret);
2971 }
3a423157 2972 }
88766984 2973
9e6e96a1
MB		 2974 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
2975 * configured on init - if a system wants to do this dynamically
2976 * at runtime we can deal with that then.
2977 */
2978 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2979 if (ret < 0) {
2980 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
88766984 2981 goto err_irq;
9e6e96a1
MB		 2982 }
2983 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2984 wm8994->lrclk_shared[0] = 1;
2985 wm8994_dai[0].symmetric_rates = 1;
2986 } else {
2987 wm8994->lrclk_shared[0] = 0;
2988 }
2989
2990 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
2991 if (ret < 0) {
2992 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
88766984 2993 goto err_irq;
9e6e96a1
MB		 2994 }
2995 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2996 wm8994->lrclk_shared[1] = 1;
2997 wm8994_dai[1].symmetric_rates = 1;
2998 } else {
2999 wm8994->lrclk_shared[1] = 0;
3000 }
3001
9e6e96a1
MB		 3002 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3003
9e6e96a1 3004 /* Latch volume updates (right only; we always do left then right). */
baa81603
MB		 3005 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3006 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
9e6e96a1
MB		 3007 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3008 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
baa81603
MB		 3009 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3010 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
9e6e96a1
MB		 3011 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3012 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
baa81603
MB		 3013 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3014 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
9e6e96a1
MB		 3015 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3016 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
baa81603
MB		 3017 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3018 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
9e6e96a1
MB		 3019 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3020 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
baa81603
MB		 3021 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3022 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3023 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3024 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3025 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3026 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
9e6e96a1
MB		 3027 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3028 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
baa81603
MB		 3029 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3030 WM8994_DAC1_VU, WM8994_DAC1_VU);
9e6e96a1
MB		 3031 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3032 WM8994_DAC1_VU, WM8994_DAC1_VU);
baa81603
MB		 3033 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3034 WM8994_DAC2_VU, WM8994_DAC2_VU);
9e6e96a1
MB		 3035 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3036 WM8994_DAC2_VU, WM8994_DAC2_VU);
3037
3038 /* Set the low bit of the 3D stereo depth so TLV matches */
3039 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3040 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3041 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3042 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3043 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3044 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3045 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3046 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3047 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3048
d1ce6b20
MB		 3049 /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3050 * behaviour on idle TDM clock cycles. */
3051 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3052 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3053
9e6e96a1
MB		 3054 wm8994_update_class_w(codec);
3055
f0fba2ad 3056 wm8994_handle_pdata(wm8994);
9e6e96a1 3057
f0fba2ad
LG		 3058 wm_hubs_add_analogue_controls(codec);
3059 snd_soc_add_controls(codec, wm8994_snd_controls,
3060 ARRAY_SIZE(wm8994_snd_controls));
ce6120cc 3061 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
f0fba2ad 3062 ARRAY_SIZE(wm8994_dapm_widgets));
c4431df0
MB		 3063
3064 switch (control->type) {
3065 case WM8994:
3066 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3067 ARRAY_SIZE(wm8994_specific_dapm_widgets));
c52fd021 3068 if (wm8994->revision < 4) {
173efa09
DP		 3069 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3070 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
04d28681
DP		 3071 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3072 ARRAY_SIZE(wm8994_adc_revd_widgets));
c52fd021
DP		 3073 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3074 ARRAY_SIZE(wm8994_dac_revd_widgets));
3075 } else {
173efa09
DP		 3076 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3077 ARRAY_SIZE(wm8994_lateclk_widgets));
04d28681
DP		 3078 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3079 ARRAY_SIZE(wm8994_adc_widgets));
c52fd021
DP		 3080 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3081 ARRAY_SIZE(wm8994_dac_widgets));
3082 }
c4431df0
MB		 3083 break;
3084 case WM8958:
3085 snd_soc_add_controls(codec, wm8958_snd_controls,
3086 ARRAY_SIZE(wm8958_snd_controls));
3087 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3088 ARRAY_SIZE(wm8958_dapm_widgets));
780e2806
MB		 3089 if (wm8994->revision < 1) {
3090 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3091 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3092 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3093 ARRAY_SIZE(wm8994_adc_revd_widgets));
3094 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3095 ARRAY_SIZE(wm8994_dac_revd_widgets));
3096 } else {
3097 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3098 ARRAY_SIZE(wm8994_lateclk_widgets));
3099 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3100 ARRAY_SIZE(wm8994_adc_widgets));
3101 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3102 ARRAY_SIZE(wm8994_dac_widgets));
3103 }
c4431df0
MB		 3104 break;
3105 }
3106
3107
f0fba2ad 3108 wm_hubs_add_analogue_routes(codec, 0, 0);
ce6120cc 3109 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
9e6e96a1 3110
c4431df0
MB		 3111 switch (control->type) {
3112 case WM8994:
3113 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3114 ARRAY_SIZE(wm8994_intercon));
6ed8f148 3115
173efa09 3116 if (wm8994->revision < 4) {
6ed8f148
MB		 3117 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3118 ARRAY_SIZE(wm8994_revd_intercon));
173efa09
DP		 3119 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3120 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3121 } else {
3122 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3123 ARRAY_SIZE(wm8994_lateclk_intercon));
3124 }
c4431df0
MB		 3125 break;
3126 case WM8958:
780e2806
MB		 3127 if (wm8994->revision < 1) {
3128 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3129 ARRAY_SIZE(wm8994_revd_intercon));
3130 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3131 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3132 } else {
3133 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3134 ARRAY_SIZE(wm8994_lateclk_intercon));
3135 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3136 ARRAY_SIZE(wm8958_intercon));
3137 }
f701a2e5
MB		 3138
3139 wm8958_dsp2_init(codec);
c4431df0
MB		 3140 break;
3141 }
3142
9e6e96a1
MB		 3143 return 0;
3144
88766984
MB		 3145err_irq:
3146 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3147 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3148 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
9b7c525d
MB		 3149 if (wm8994->micdet_irq)
3150 free_irq(wm8994->micdet_irq, wm8994);
9e6e96a1
MB		 3151err:
3152 kfree(wm8994);
3153 return ret;
3154}
3155
f0fba2ad 3156static int wm8994_codec_remove(struct snd_soc_codec *codec)
9e6e96a1 3157{
f0fba2ad 3158 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3a423157 3159 struct wm8994 *control = codec->control_data;
9e6e96a1
MB		 3160
3161 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
f0fba2ad 3162
39fb51a1
MB		 3163 pm_runtime_disable(codec->dev);
3164
3a423157
MB		 3165 switch (control->type) {
3166 case WM8994:
9b7c525d
MB		 3167 if (wm8994->micdet_irq)
3168 free_irq(wm8994->micdet_irq, wm8994);
3a423157
MB		 3169 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3170 wm8994);
3171 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3172 wm8994);
3173 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3174 wm8994);
3175 break;
821edd2f
MB		 3176
3177 case WM8958:
9b7c525d
MB		 3178 if (wm8994->micdet_irq)
3179 free_irq(wm8994->micdet_irq, wm8994);
821edd2f 3180 break;
3a423157 3181 }
fbbf5920
MB		 3182 if (wm8994->mbc)
3183 release_firmware(wm8994->mbc);
09e10d7f
MB		 3184 if (wm8994->mbc_vss)
3185 release_firmware(wm8994->mbc_vss);
31215871
MB		 3186 if (wm8994->enh_eq)
3187 release_firmware(wm8994->enh_eq);
24fb2b11
AL		 3188 kfree(wm8994->retune_mobile_texts);
3189 kfree(wm8994->drc_texts);
9e6e96a1 3190 kfree(wm8994);
9e6e96a1
MB		 3191
3192 return 0;
3193}
3194
f0fba2ad
LG		 3195static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3196 .probe = wm8994_codec_probe,
3197 .remove = wm8994_codec_remove,
3198 .suspend = wm8994_suspend,
3199 .resume = wm8994_resume,
ca9aef50
MB		 3200 .read = wm8994_read,
3201 .write = wm8994_write,
eba19fdd
MB		 3202 .readable_register = wm8994_readable,
3203 .volatile_register = wm8994_volatile,
f0fba2ad 3204 .set_bias_level = wm8994_set_bias_level,
ca9aef50
MB		 3205
3206 .reg_cache_size = WM8994_CACHE_SIZE,
3207 .reg_cache_default = wm8994_reg_defaults,
3208 .reg_word_size = 2,
2e19b0c8 3209 .compress_type = SND_SOC_RBTREE_COMPRESSION,
f0fba2ad
LG		 3210};
3211
3212static int __devinit wm8994_probe(struct platform_device *pdev)
3213{
3214 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3215 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3216}
3217
3218static int __devexit wm8994_remove(struct platform_device *pdev)
3219{
3220 snd_soc_unregister_codec(&pdev->dev);
3221 return 0;
3222}
3223
9e6e96a1
MB		 3224static struct platform_driver wm8994_codec_driver = {
3225 .driver = {
3226 .name = "wm8994-codec",
3227 .owner = THIS_MODULE,
3228 },
f0fba2ad
LG		 3229 .probe = wm8994_probe,
3230 .remove = __devexit_p(wm8994_remove),
9e6e96a1
MB		 3231};
3232
3233static __init int wm8994_init(void)
3234{
3235 return platform_driver_register(&wm8994_codec_driver);
3236}
3237module_init(wm8994_init);
3238
3239static __exit void wm8994_exit(void)
3240{
3241 platform_driver_unregister(&wm8994_codec_driver);
3242}
3243module_exit(wm8994_exit);
3244
3245
3246MODULE_DESCRIPTION("ASoC WM8994 driver");
3247MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3248MODULE_LICENSE("GPL");
3249MODULE_ALIAS("platform:wm8994-codec");
Linux kernel - Deliverables
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