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6a504a75 DP |
1 | /* |
2 | * wm8995.c -- WM8995 ALSA SoC Audio driver | |
3 | * | |
4 | * Copyright 2010 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * Based on wm8994.c and wm_hubs.c by Mark Brown | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/moduleparam.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/delay.h> | |
19 | #include <linux/pm.h> | |
20 | #include <linux/i2c.h> | |
21 | #include <linux/spi/spi.h> | |
22 | #include <linux/slab.h> | |
23 | #include <sound/core.h> | |
24 | #include <sound/pcm.h> | |
25 | #include <sound/pcm_params.h> | |
26 | #include <sound/soc.h> | |
27 | #include <sound/soc-dapm.h> | |
28 | #include <sound/initval.h> | |
29 | #include <sound/tlv.h> | |
30 | ||
31 | #include "wm8995.h" | |
32 | ||
03cfbdf9 | 33 | static const u16 wm8995_reg_defs[WM8995_MAX_REGISTER + 1] = { |
6a504a75 DP |
34 | [0] = 0x8995, [5] = 0x0100, [16] = 0x000b, [17] = 0x000b, |
35 | [24] = 0x02c0, [25] = 0x02c0, [26] = 0x02c0, [27] = 0x02c0, | |
36 | [28] = 0x000f, [32] = 0x0005, [33] = 0x0005, [40] = 0x0003, | |
37 | [41] = 0x0013, [48] = 0x0004, [56] = 0x09f8, [64] = 0x1f25, | |
38 | [69] = 0x0004, [82] = 0xaaaa, [84] = 0x2a2a, [146] = 0x0060, | |
39 | [256] = 0x0002, [257] = 0x8004, [520] = 0x0010, [528] = 0x0083, | |
40 | [529] = 0x0083, [548] = 0x0c80, [580] = 0x0c80, [768] = 0x4050, | |
41 | [769] = 0x4000, [771] = 0x0040, [772] = 0x0040, [773] = 0x0040, | |
42 | [774] = 0x0004, [775] = 0x0100, [784] = 0x4050, [785] = 0x4000, | |
43 | [787] = 0x0040, [788] = 0x0040, [789] = 0x0040, [1024] = 0x00c0, | |
44 | [1025] = 0x00c0, [1026] = 0x00c0, [1027] = 0x00c0, [1028] = 0x00c0, | |
45 | [1029] = 0x00c0, [1030] = 0x00c0, [1031] = 0x00c0, [1056] = 0x0200, | |
46 | [1057] = 0x0010, [1058] = 0x0200, [1059] = 0x0010, [1088] = 0x0098, | |
47 | [1089] = 0x0845, [1104] = 0x0098, [1105] = 0x0845, [1152] = 0x6318, | |
48 | [1153] = 0x6300, [1154] = 0x0fca, [1155] = 0x0400, [1156] = 0x00d8, | |
49 | [1157] = 0x1eb5, [1158] = 0xf145, [1159] = 0x0b75, [1160] = 0x01c5, | |
50 | [1161] = 0x1c58, [1162] = 0xf373, [1163] = 0x0a54, [1164] = 0x0558, | |
51 | [1165] = 0x168e, [1166] = 0xf829, [1167] = 0x07ad, [1168] = 0x1103, | |
52 | [1169] = 0x0564, [1170] = 0x0559, [1171] = 0x4000, [1184] = 0x6318, | |
53 | [1185] = 0x6300, [1186] = 0x0fca, [1187] = 0x0400, [1188] = 0x00d8, | |
54 | [1189] = 0x1eb5, [1190] = 0xf145, [1191] = 0x0b75, [1192] = 0x01c5, | |
55 | [1193] = 0x1c58, [1194] = 0xf373, [1195] = 0x0a54, [1196] = 0x0558, | |
56 | [1197] = 0x168e, [1198] = 0xf829, [1199] = 0x07ad, [1200] = 0x1103, | |
57 | [1201] = 0x0564, [1202] = 0x0559, [1203] = 0x4000, [1280] = 0x00c0, | |
58 | [1281] = 0x00c0, [1282] = 0x00c0, [1283] = 0x00c0, [1312] = 0x0200, | |
59 | [1313] = 0x0010, [1344] = 0x0098, [1345] = 0x0845, [1408] = 0x6318, | |
60 | [1409] = 0x6300, [1410] = 0x0fca, [1411] = 0x0400, [1412] = 0x00d8, | |
61 | [1413] = 0x1eb5, [1414] = 0xf145, [1415] = 0x0b75, [1416] = 0x01c5, | |
62 | [1417] = 0x1c58, [1418] = 0xf373, [1419] = 0x0a54, [1420] = 0x0558, | |
63 | [1421] = 0x168e, [1422] = 0xf829, [1423] = 0x07ad, [1424] = 0x1103, | |
64 | [1425] = 0x0564, [1426] = 0x0559, [1427] = 0x4000, [1568] = 0x0002, | |
65 | [1792] = 0xa100, [1793] = 0xa101, [1794] = 0xa101, [1795] = 0xa101, | |
66 | [1796] = 0xa101, [1797] = 0xa101, [1798] = 0xa101, [1799] = 0xa101, | |
67 | [1800] = 0xa101, [1801] = 0xa101, [1802] = 0xa101, [1803] = 0xa101, | |
68 | [1804] = 0xa101, [1805] = 0xa101, [1825] = 0x0055, [1848] = 0x3fff, | |
69 | [1849] = 0x1fff, [2049] = 0x0001, [2050] = 0x0069, [2056] = 0x0002, | |
70 | [2057] = 0x0003, [2058] = 0x0069, [12288] = 0x0001, [12289] = 0x0001, | |
71 | [12291] = 0x0006, [12292] = 0x0040, [12293] = 0x0001, [12294] = 0x000f, | |
72 | [12295] = 0x0006, [12296] = 0x0001, [12297] = 0x0003, [12298] = 0x0104, | |
73 | [12300] = 0x0060, [12301] = 0x0011, [12302] = 0x0401, [12304] = 0x0050, | |
74 | [12305] = 0x0003, [12306] = 0x0100, [12308] = 0x0051, [12309] = 0x0003, | |
75 | [12310] = 0x0104, [12311] = 0x000a, [12312] = 0x0060, [12313] = 0x003b, | |
76 | [12314] = 0x0502, [12315] = 0x0100, [12316] = 0x2fff, [12320] = 0x2fff, | |
77 | [12324] = 0x2fff, [12328] = 0x2fff, [12332] = 0x2fff, [12336] = 0x2fff, | |
78 | [12340] = 0x2fff, [12344] = 0x2fff, [12348] = 0x2fff, [12352] = 0x0001, | |
79 | [12353] = 0x0001, [12355] = 0x0006, [12356] = 0x0040, [12357] = 0x0001, | |
80 | [12358] = 0x000f, [12359] = 0x0006, [12360] = 0x0001, [12361] = 0x0003, | |
81 | [12362] = 0x0104, [12364] = 0x0060, [12365] = 0x0011, [12366] = 0x0401, | |
82 | [12368] = 0x0050, [12369] = 0x0003, [12370] = 0x0100, [12372] = 0x0060, | |
83 | [12373] = 0x003b, [12374] = 0x0502, [12375] = 0x0100, [12376] = 0x2fff, | |
84 | [12380] = 0x2fff, [12384] = 0x2fff, [12388] = 0x2fff, [12392] = 0x2fff, | |
85 | [12396] = 0x2fff, [12400] = 0x2fff, [12404] = 0x2fff, [12408] = 0x2fff, | |
86 | [12412] = 0x2fff, [12416] = 0x0001, [12417] = 0x0001, [12419] = 0x0006, | |
87 | [12420] = 0x0040, [12421] = 0x0001, [12422] = 0x000f, [12423] = 0x0006, | |
88 | [12424] = 0x0001, [12425] = 0x0003, [12426] = 0x0106, [12428] = 0x0061, | |
89 | [12429] = 0x0011, [12430] = 0x0401, [12432] = 0x0050, [12433] = 0x0003, | |
90 | [12434] = 0x0102, [12436] = 0x0051, [12437] = 0x0003, [12438] = 0x0106, | |
91 | [12439] = 0x000a, [12440] = 0x0061, [12441] = 0x003b, [12442] = 0x0502, | |
92 | [12443] = 0x0100, [12444] = 0x2fff, [12448] = 0x2fff, [12452] = 0x2fff, | |
93 | [12456] = 0x2fff, [12460] = 0x2fff, [12464] = 0x2fff, [12468] = 0x2fff, | |
94 | [12472] = 0x2fff, [12476] = 0x2fff, [12480] = 0x0001, [12481] = 0x0001, | |
95 | [12483] = 0x0006, [12484] = 0x0040, [12485] = 0x0001, [12486] = 0x000f, | |
96 | [12487] = 0x0006, [12488] = 0x0001, [12489] = 0x0003, [12490] = 0x0106, | |
97 | [12492] = 0x0061, [12493] = 0x0011, [12494] = 0x0401, [12496] = 0x0050, | |
98 | [12497] = 0x0003, [12498] = 0x0102, [12500] = 0x0061, [12501] = 0x003b, | |
99 | [12502] = 0x0502, [12503] = 0x0100, [12504] = 0x2fff, [12508] = 0x2fff, | |
100 | [12512] = 0x2fff, [12516] = 0x2fff, [12520] = 0x2fff, [12524] = 0x2fff, | |
101 | [12528] = 0x2fff, [12532] = 0x2fff, [12536] = 0x2fff, [12540] = 0x2fff, | |
102 | [12544] = 0x0060, [12546] = 0x0601, [12548] = 0x0050, [12550] = 0x0100, | |
103 | [12552] = 0x0001, [12554] = 0x0104, [12555] = 0x0100, [12556] = 0x2fff, | |
104 | [12560] = 0x2fff, [12564] = 0x2fff, [12568] = 0x2fff, [12572] = 0x2fff, | |
105 | [12576] = 0x2fff, [12580] = 0x2fff, [12584] = 0x2fff, [12588] = 0x2fff, | |
106 | [12592] = 0x2fff, [12596] = 0x2fff, [12600] = 0x2fff, [12604] = 0x2fff, | |
107 | [12608] = 0x0061, [12610] = 0x0601, [12612] = 0x0050, [12614] = 0x0102, | |
108 | [12616] = 0x0001, [12618] = 0x0106, [12619] = 0x0100, [12620] = 0x2fff, | |
109 | [12624] = 0x2fff, [12628] = 0x2fff, [12632] = 0x2fff, [12636] = 0x2fff, | |
110 | [12640] = 0x2fff, [12644] = 0x2fff, [12648] = 0x2fff, [12652] = 0x2fff, | |
111 | [12656] = 0x2fff, [12660] = 0x2fff, [12664] = 0x2fff, [12668] = 0x2fff, | |
112 | [12672] = 0x0060, [12674] = 0x0601, [12676] = 0x0061, [12678] = 0x0601, | |
113 | [12680] = 0x0050, [12682] = 0x0300, [12684] = 0x0001, [12686] = 0x0304, | |
114 | [12688] = 0x0040, [12690] = 0x000f, [12692] = 0x0001, [12695] = 0x0100 | |
115 | }; | |
116 | ||
117 | struct fll_config { | |
118 | int src; | |
119 | int in; | |
120 | int out; | |
121 | }; | |
122 | ||
123 | struct wm8995_priv { | |
124 | enum snd_soc_control_type control_type; | |
125 | int sysclk[2]; | |
126 | int mclk[2]; | |
127 | int aifclk[2]; | |
128 | struct fll_config fll[2], fll_suspend[2]; | |
129 | }; | |
130 | ||
131 | static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); | |
132 | static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0); | |
133 | static const DECLARE_TLV_DB_SCALE(in1l_boost_tlv, 0, 600, 0); | |
134 | static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0); | |
135 | ||
136 | static const char *in1l_text[] = { | |
137 | "Differential", "Single-ended IN1LN", "Single-ended IN1LP" | |
138 | }; | |
139 | ||
140 | static const SOC_ENUM_SINGLE_DECL(in1l_enum, WM8995_LEFT_LINE_INPUT_CONTROL, | |
141 | 2, in1l_text); | |
142 | ||
143 | static const char *in1r_text[] = { | |
144 | "Differential", "Single-ended IN1RN", "Single-ended IN1RP" | |
145 | }; | |
146 | ||
147 | static const SOC_ENUM_SINGLE_DECL(in1r_enum, WM8995_LEFT_LINE_INPUT_CONTROL, | |
148 | 0, in1r_text); | |
149 | ||
150 | static const char *dmic_src_text[] = { | |
151 | "DMICDAT1", "DMICDAT2", "DMICDAT3" | |
152 | }; | |
153 | ||
154 | static const SOC_ENUM_SINGLE_DECL(dmic_src1_enum, WM8995_POWER_MANAGEMENT_5, | |
155 | 8, dmic_src_text); | |
156 | static const SOC_ENUM_SINGLE_DECL(dmic_src2_enum, WM8995_POWER_MANAGEMENT_5, | |
157 | 6, dmic_src_text); | |
158 | ||
159 | static const struct snd_kcontrol_new wm8995_snd_controls[] = { | |
160 | SOC_DOUBLE_R_TLV("DAC1 Volume", WM8995_DAC1_LEFT_VOLUME, | |
161 | WM8995_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
162 | SOC_DOUBLE_R("DAC1 Switch", WM8995_DAC1_LEFT_VOLUME, | |
163 | WM8995_DAC1_RIGHT_VOLUME, 9, 1, 1), | |
164 | ||
165 | SOC_DOUBLE_R_TLV("DAC2 Volume", WM8995_DAC2_LEFT_VOLUME, | |
166 | WM8995_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
167 | SOC_DOUBLE_R("DAC2 Switch", WM8995_DAC2_LEFT_VOLUME, | |
168 | WM8995_DAC2_RIGHT_VOLUME, 9, 1, 1), | |
169 | ||
170 | SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8995_AIF1_DAC1_LEFT_VOLUME, | |
171 | WM8995_AIF1_DAC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
172 | SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8995_AIF1_DAC2_LEFT_VOLUME, | |
173 | WM8995_AIF1_DAC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
174 | SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8995_AIF2_DAC_LEFT_VOLUME, | |
175 | WM8995_AIF2_DAC_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
176 | ||
177 | SOC_DOUBLE_R_TLV("IN1LR Volume", WM8995_LEFT_LINE_INPUT_1_VOLUME, | |
178 | WM8995_RIGHT_LINE_INPUT_1_VOLUME, 0, 31, 0, in1lr_pga_tlv), | |
179 | ||
180 | SOC_SINGLE_TLV("IN1L Boost", WM8995_LEFT_LINE_INPUT_CONTROL, | |
181 | 4, 3, 0, in1l_boost_tlv), | |
182 | ||
183 | SOC_ENUM("IN1L Mode", in1l_enum), | |
184 | SOC_ENUM("IN1R Mode", in1r_enum), | |
185 | ||
186 | SOC_ENUM("DMIC1 SRC", dmic_src1_enum), | |
187 | SOC_ENUM("DMIC2 SRC", dmic_src2_enum), | |
188 | ||
189 | SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8995_DAC1_MIXER_VOLUMES, 0, 5, | |
190 | 24, 0, sidetone_tlv), | |
191 | SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8995_DAC2_MIXER_VOLUMES, 0, 5, | |
192 | 24, 0, sidetone_tlv), | |
193 | ||
194 | SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8995_AIF1_ADC1_LEFT_VOLUME, | |
195 | WM8995_AIF1_ADC1_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
196 | SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8995_AIF1_ADC2_LEFT_VOLUME, | |
197 | WM8995_AIF1_ADC2_RIGHT_VOLUME, 0, 96, 0, digital_tlv), | |
198 | SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8995_AIF2_ADC_LEFT_VOLUME, | |
199 | WM8995_AIF2_ADC_RIGHT_VOLUME, 0, 96, 0, digital_tlv) | |
200 | }; | |
201 | ||
202 | static void wm8995_update_class_w(struct snd_soc_codec *codec) | |
203 | { | |
204 | int enable = 1; | |
205 | int source = 0; /* GCC flow analysis can't track enable */ | |
206 | int reg, reg_r; | |
207 | ||
208 | /* We also need the same setting for L/R and only one path */ | |
209 | reg = snd_soc_read(codec, WM8995_DAC1_LEFT_MIXER_ROUTING); | |
210 | switch (reg) { | |
211 | case WM8995_AIF2DACL_TO_DAC1L: | |
212 | dev_dbg(codec->dev, "Class W source AIF2DAC\n"); | |
213 | source = 2 << WM8995_CP_DYN_SRC_SEL_SHIFT; | |
214 | break; | |
215 | case WM8995_AIF1DAC2L_TO_DAC1L: | |
216 | dev_dbg(codec->dev, "Class W source AIF1DAC2\n"); | |
217 | source = 1 << WM8995_CP_DYN_SRC_SEL_SHIFT; | |
218 | break; | |
219 | case WM8995_AIF1DAC1L_TO_DAC1L: | |
220 | dev_dbg(codec->dev, "Class W source AIF1DAC1\n"); | |
221 | source = 0 << WM8995_CP_DYN_SRC_SEL_SHIFT; | |
222 | break; | |
223 | default: | |
224 | dev_dbg(codec->dev, "DAC mixer setting: %x\n", reg); | |
225 | enable = 0; | |
226 | break; | |
227 | } | |
228 | ||
229 | reg_r = snd_soc_read(codec, WM8995_DAC1_RIGHT_MIXER_ROUTING); | |
230 | if (reg_r != reg) { | |
231 | dev_dbg(codec->dev, "Left and right DAC mixers different\n"); | |
232 | enable = 0; | |
233 | } | |
234 | ||
235 | if (enable) { | |
236 | dev_dbg(codec->dev, "Class W enabled\n"); | |
237 | snd_soc_update_bits(codec, WM8995_CLASS_W_1, | |
238 | WM8995_CP_DYN_PWR_MASK | | |
239 | WM8995_CP_DYN_SRC_SEL_MASK, | |
240 | source | WM8995_CP_DYN_PWR); | |
241 | } else { | |
242 | dev_dbg(codec->dev, "Class W disabled\n"); | |
243 | snd_soc_update_bits(codec, WM8995_CLASS_W_1, | |
244 | WM8995_CP_DYN_PWR_MASK, 0); | |
245 | } | |
246 | } | |
247 | ||
248 | static int check_clk_sys(struct snd_soc_dapm_widget *source, | |
249 | struct snd_soc_dapm_widget *sink) | |
250 | { | |
251 | unsigned int reg; | |
252 | const char *clk; | |
253 | ||
254 | reg = snd_soc_read(source->codec, WM8995_CLOCKING_1); | |
255 | /* Check what we're currently using for CLK_SYS */ | |
256 | if (reg & WM8995_SYSCLK_SRC) | |
257 | clk = "AIF2CLK"; | |
258 | else | |
259 | clk = "AIF1CLK"; | |
260 | return !strcmp(source->name, clk); | |
261 | } | |
262 | ||
263 | static int wm8995_put_class_w(struct snd_kcontrol *kcontrol, | |
264 | struct snd_ctl_elem_value *ucontrol) | |
265 | { | |
266 | struct snd_soc_dapm_widget *w; | |
267 | struct snd_soc_codec *codec; | |
268 | int ret; | |
269 | ||
270 | w = snd_kcontrol_chip(kcontrol); | |
271 | codec = w->codec; | |
272 | ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol); | |
273 | wm8995_update_class_w(codec); | |
274 | return ret; | |
275 | } | |
276 | ||
277 | static int hp_supply_event(struct snd_soc_dapm_widget *w, | |
278 | struct snd_kcontrol *kcontrol, int event) | |
279 | { | |
280 | struct snd_soc_codec *codec; | |
281 | struct wm8995_priv *wm8995; | |
282 | ||
283 | codec = w->codec; | |
284 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
285 | ||
286 | switch (event) { | |
287 | case SND_SOC_DAPM_PRE_PMU: | |
288 | /* Enable the headphone amp */ | |
289 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
290 | WM8995_HPOUT1L_ENA_MASK | | |
291 | WM8995_HPOUT1R_ENA_MASK, | |
292 | WM8995_HPOUT1L_ENA | | |
293 | WM8995_HPOUT1R_ENA); | |
294 | ||
295 | /* Enable the second stage */ | |
296 | snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, | |
297 | WM8995_HPOUT1L_DLY_MASK | | |
298 | WM8995_HPOUT1R_DLY_MASK, | |
299 | WM8995_HPOUT1L_DLY | | |
300 | WM8995_HPOUT1R_DLY); | |
301 | break; | |
302 | case SND_SOC_DAPM_PRE_PMD: | |
303 | snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, | |
304 | WM8995_CP_ENA_MASK, 0); | |
305 | break; | |
306 | } | |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | static void dc_servo_cmd(struct snd_soc_codec *codec, | |
312 | unsigned int reg, unsigned int val, unsigned int mask) | |
313 | { | |
314 | int timeout = 10; | |
315 | ||
316 | dev_dbg(codec->dev, "%s: reg = %#x, val = %#x, mask = %#x\n", | |
317 | __func__, reg, val, mask); | |
318 | ||
319 | snd_soc_write(codec, reg, val); | |
320 | while (timeout--) { | |
321 | msleep(10); | |
322 | val = snd_soc_read(codec, WM8995_DC_SERVO_READBACK_0); | |
323 | if ((val & mask) == mask) | |
324 | return; | |
325 | } | |
326 | ||
327 | dev_err(codec->dev, "Timed out waiting for DC Servo\n"); | |
328 | } | |
329 | ||
330 | static int hp_event(struct snd_soc_dapm_widget *w, | |
331 | struct snd_kcontrol *kcontrol, int event) | |
332 | { | |
333 | struct snd_soc_codec *codec; | |
334 | unsigned int reg; | |
335 | ||
336 | codec = w->codec; | |
337 | reg = snd_soc_read(codec, WM8995_ANALOGUE_HP_1); | |
338 | ||
339 | switch (event) { | |
340 | case SND_SOC_DAPM_POST_PMU: | |
341 | snd_soc_update_bits(codec, WM8995_CHARGE_PUMP_1, | |
342 | WM8995_CP_ENA_MASK, WM8995_CP_ENA); | |
343 | ||
344 | msleep(5); | |
345 | ||
346 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
347 | WM8995_HPOUT1L_ENA_MASK | | |
348 | WM8995_HPOUT1R_ENA_MASK, | |
349 | WM8995_HPOUT1L_ENA | WM8995_HPOUT1R_ENA); | |
350 | ||
351 | udelay(20); | |
352 | ||
353 | reg |= WM8995_HPOUT1L_DLY | WM8995_HPOUT1R_DLY; | |
354 | snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); | |
355 | ||
356 | snd_soc_write(codec, WM8995_DC_SERVO_1, WM8995_DCS_ENA_CHAN_0 | | |
357 | WM8995_DCS_ENA_CHAN_1); | |
358 | ||
359 | dc_servo_cmd(codec, WM8995_DC_SERVO_2, | |
360 | WM8995_DCS_TRIG_STARTUP_0 | | |
361 | WM8995_DCS_TRIG_STARTUP_1, | |
362 | WM8995_DCS_TRIG_DAC_WR_0 | | |
363 | WM8995_DCS_TRIG_DAC_WR_1); | |
364 | ||
365 | reg |= WM8995_HPOUT1R_OUTP | WM8995_HPOUT1R_RMV_SHORT | | |
366 | WM8995_HPOUT1L_OUTP | WM8995_HPOUT1L_RMV_SHORT; | |
367 | snd_soc_write(codec, WM8995_ANALOGUE_HP_1, reg); | |
368 | ||
369 | break; | |
370 | case SND_SOC_DAPM_PRE_PMD: | |
371 | snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, | |
372 | WM8995_HPOUT1L_OUTP_MASK | | |
373 | WM8995_HPOUT1R_OUTP_MASK | | |
374 | WM8995_HPOUT1L_RMV_SHORT_MASK | | |
375 | WM8995_HPOUT1R_RMV_SHORT_MASK, 0); | |
376 | ||
377 | snd_soc_update_bits(codec, WM8995_ANALOGUE_HP_1, | |
378 | WM8995_HPOUT1L_DLY_MASK | | |
379 | WM8995_HPOUT1R_DLY_MASK, 0); | |
380 | ||
381 | snd_soc_write(codec, WM8995_DC_SERVO_1, 0); | |
382 | ||
383 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
384 | WM8995_HPOUT1L_ENA_MASK | | |
385 | WM8995_HPOUT1R_ENA_MASK, | |
386 | 0); | |
387 | break; | |
388 | } | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static int configure_aif_clock(struct snd_soc_codec *codec, int aif) | |
394 | { | |
395 | struct wm8995_priv *wm8995; | |
396 | int rate; | |
397 | int reg1 = 0; | |
398 | int offset; | |
399 | ||
400 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
401 | ||
402 | if (aif) | |
403 | offset = 4; | |
404 | else | |
405 | offset = 0; | |
406 | ||
407 | switch (wm8995->sysclk[aif]) { | |
408 | case WM8995_SYSCLK_MCLK1: | |
409 | rate = wm8995->mclk[0]; | |
410 | break; | |
411 | case WM8995_SYSCLK_MCLK2: | |
412 | reg1 |= 0x8; | |
413 | rate = wm8995->mclk[1]; | |
414 | break; | |
415 | case WM8995_SYSCLK_FLL1: | |
416 | reg1 |= 0x10; | |
417 | rate = wm8995->fll[0].out; | |
418 | break; | |
419 | case WM8995_SYSCLK_FLL2: | |
420 | reg1 |= 0x18; | |
421 | rate = wm8995->fll[1].out; | |
422 | break; | |
423 | default: | |
424 | return -EINVAL; | |
425 | } | |
426 | ||
427 | if (rate >= 13500000) { | |
428 | rate /= 2; | |
429 | reg1 |= WM8995_AIF1CLK_DIV; | |
430 | ||
431 | dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n", | |
432 | aif + 1, rate); | |
433 | } | |
434 | ||
435 | wm8995->aifclk[aif] = rate; | |
436 | ||
437 | snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1 + offset, | |
438 | WM8995_AIF1CLK_SRC_MASK | WM8995_AIF1CLK_DIV_MASK, | |
439 | reg1); | |
440 | return 0; | |
441 | } | |
442 | ||
443 | static int configure_clock(struct snd_soc_codec *codec) | |
444 | { | |
445 | struct wm8995_priv *wm8995; | |
446 | int old, new; | |
447 | ||
448 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
449 | ||
450 | /* Bring up the AIF clocks first */ | |
451 | configure_aif_clock(codec, 0); | |
452 | configure_aif_clock(codec, 1); | |
453 | ||
454 | /* | |
455 | * Then switch CLK_SYS over to the higher of them; a change | |
456 | * can only happen as a result of a clocking change which can | |
457 | * only be made outside of DAPM so we can safely redo the | |
458 | * clocking. | |
459 | */ | |
460 | ||
461 | /* If they're equal it doesn't matter which is used */ | |
462 | if (wm8995->aifclk[0] == wm8995->aifclk[1]) | |
463 | return 0; | |
464 | ||
465 | if (wm8995->aifclk[0] < wm8995->aifclk[1]) | |
466 | new = WM8995_SYSCLK_SRC; | |
467 | else | |
468 | new = 0; | |
469 | ||
470 | old = snd_soc_read(codec, WM8995_CLOCKING_1) & WM8995_SYSCLK_SRC; | |
471 | ||
472 | /* If there's no change then we're done. */ | |
473 | if (old == new) | |
474 | return 0; | |
475 | ||
476 | snd_soc_update_bits(codec, WM8995_CLOCKING_1, | |
477 | WM8995_SYSCLK_SRC_MASK, new); | |
478 | ||
479 | snd_soc_dapm_sync(&codec->dapm); | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
484 | static int clk_sys_event(struct snd_soc_dapm_widget *w, | |
485 | struct snd_kcontrol *kcontrol, int event) | |
486 | { | |
487 | struct snd_soc_codec *codec; | |
488 | ||
489 | codec = w->codec; | |
490 | ||
491 | switch (event) { | |
492 | case SND_SOC_DAPM_PRE_PMU: | |
493 | return configure_clock(codec); | |
494 | ||
495 | case SND_SOC_DAPM_POST_PMD: | |
496 | configure_clock(codec); | |
497 | break; | |
498 | } | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static const char *sidetone_text[] = { | |
504 | "ADC/DMIC1", "DMIC2", | |
505 | }; | |
506 | ||
507 | static const struct soc_enum sidetone1_enum = | |
508 | SOC_ENUM_SINGLE(WM8995_SIDETONE, 0, 2, sidetone_text); | |
509 | ||
510 | static const struct snd_kcontrol_new sidetone1_mux = | |
511 | SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum); | |
512 | ||
513 | static const struct soc_enum sidetone2_enum = | |
514 | SOC_ENUM_SINGLE(WM8995_SIDETONE, 1, 2, sidetone_text); | |
515 | ||
516 | static const struct snd_kcontrol_new sidetone2_mux = | |
517 | SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum); | |
518 | ||
519 | static const struct snd_kcontrol_new aif1adc1l_mix[] = { | |
520 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
521 | 1, 1, 0), | |
522 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_LEFT_MIXER_ROUTING, | |
523 | 0, 1, 0), | |
524 | }; | |
525 | ||
526 | static const struct snd_kcontrol_new aif1adc1r_mix[] = { | |
527 | SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
528 | 1, 1, 0), | |
529 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC1_RIGHT_MIXER_ROUTING, | |
530 | 0, 1, 0), | |
531 | }; | |
532 | ||
533 | static const struct snd_kcontrol_new aif1adc2l_mix[] = { | |
534 | SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
535 | 1, 1, 0), | |
536 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_LEFT_MIXER_ROUTING, | |
537 | 0, 1, 0), | |
538 | }; | |
539 | ||
540 | static const struct snd_kcontrol_new aif1adc2r_mix[] = { | |
541 | SOC_DAPM_SINGLE("DMIC Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
542 | 1, 1, 0), | |
543 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_AIF1_ADC2_RIGHT_MIXER_ROUTING, | |
544 | 0, 1, 0), | |
545 | }; | |
546 | ||
547 | static const struct snd_kcontrol_new dac1l_mix[] = { | |
548 | WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
549 | 5, 1, 0), | |
550 | WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
551 | 4, 1, 0), | |
552 | WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
553 | 2, 1, 0), | |
554 | WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
555 | 1, 1, 0), | |
556 | WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_LEFT_MIXER_ROUTING, | |
557 | 0, 1, 0), | |
558 | }; | |
559 | ||
560 | static const struct snd_kcontrol_new dac1r_mix[] = { | |
561 | WM8995_CLASS_W_SWITCH("Right Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
562 | 5, 1, 0), | |
563 | WM8995_CLASS_W_SWITCH("Left Sidetone Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
564 | 4, 1, 0), | |
565 | WM8995_CLASS_W_SWITCH("AIF2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
566 | 2, 1, 0), | |
567 | WM8995_CLASS_W_SWITCH("AIF1.2 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
568 | 1, 1, 0), | |
569 | WM8995_CLASS_W_SWITCH("AIF1.1 Switch", WM8995_DAC1_RIGHT_MIXER_ROUTING, | |
570 | 0, 1, 0), | |
571 | }; | |
572 | ||
573 | static const struct snd_kcontrol_new aif2dac2l_mix[] = { | |
574 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
575 | 5, 1, 0), | |
576 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
577 | 4, 1, 0), | |
578 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
579 | 2, 1, 0), | |
580 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
581 | 1, 1, 0), | |
582 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_LEFT_MIXER_ROUTING, | |
583 | 0, 1, 0), | |
584 | }; | |
585 | ||
586 | static const struct snd_kcontrol_new aif2dac2r_mix[] = { | |
587 | SOC_DAPM_SINGLE("Right Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
588 | 5, 1, 0), | |
589 | SOC_DAPM_SINGLE("Left Sidetone Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
590 | 4, 1, 0), | |
591 | SOC_DAPM_SINGLE("AIF2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
592 | 2, 1, 0), | |
593 | SOC_DAPM_SINGLE("AIF1.2 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
594 | 1, 1, 0), | |
595 | SOC_DAPM_SINGLE("AIF1.1 Switch", WM8995_DAC2_RIGHT_MIXER_ROUTING, | |
596 | 0, 1, 0), | |
597 | }; | |
598 | ||
599 | static const struct snd_kcontrol_new in1l_pga = | |
600 | SOC_DAPM_SINGLE("IN1L Switch", WM8995_POWER_MANAGEMENT_2, 5, 1, 0); | |
601 | ||
602 | static const struct snd_kcontrol_new in1r_pga = | |
603 | SOC_DAPM_SINGLE("IN1R Switch", WM8995_POWER_MANAGEMENT_2, 4, 1, 0); | |
604 | ||
605 | static const char *adc_mux_text[] = { | |
606 | "ADC", | |
607 | "DMIC", | |
608 | }; | |
609 | ||
610 | static const struct soc_enum adc_enum = | |
611 | SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text); | |
612 | ||
613 | static const struct snd_kcontrol_new adcl_mux = | |
614 | SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum); | |
615 | ||
616 | static const struct snd_kcontrol_new adcr_mux = | |
617 | SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum); | |
618 | ||
619 | static const char *spk_src_text[] = { | |
620 | "DAC1L", "DAC1R", "DAC2L", "DAC2R" | |
621 | }; | |
622 | ||
623 | static const SOC_ENUM_SINGLE_DECL(spk1l_src_enum, WM8995_LEFT_PDM_SPEAKER_1, | |
624 | 0, spk_src_text); | |
625 | static const SOC_ENUM_SINGLE_DECL(spk1r_src_enum, WM8995_RIGHT_PDM_SPEAKER_1, | |
626 | 0, spk_src_text); | |
627 | static const SOC_ENUM_SINGLE_DECL(spk2l_src_enum, WM8995_LEFT_PDM_SPEAKER_2, | |
628 | 0, spk_src_text); | |
629 | static const SOC_ENUM_SINGLE_DECL(spk2r_src_enum, WM8995_RIGHT_PDM_SPEAKER_2, | |
630 | 0, spk_src_text); | |
631 | ||
632 | static const struct snd_kcontrol_new spk1l_mux = | |
633 | SOC_DAPM_ENUM("SPK1L SRC", spk1l_src_enum); | |
634 | static const struct snd_kcontrol_new spk1r_mux = | |
635 | SOC_DAPM_ENUM("SPK1R SRC", spk1r_src_enum); | |
636 | static const struct snd_kcontrol_new spk2l_mux = | |
637 | SOC_DAPM_ENUM("SPK2L SRC", spk2l_src_enum); | |
638 | static const struct snd_kcontrol_new spk2r_mux = | |
639 | SOC_DAPM_ENUM("SPK2R SRC", spk2r_src_enum); | |
640 | ||
641 | static const struct snd_soc_dapm_widget wm8995_dapm_widgets[] = { | |
642 | SND_SOC_DAPM_INPUT("DMIC1DAT"), | |
643 | SND_SOC_DAPM_INPUT("DMIC2DAT"), | |
644 | ||
645 | SND_SOC_DAPM_INPUT("IN1L"), | |
646 | SND_SOC_DAPM_INPUT("IN1R"), | |
647 | ||
648 | SND_SOC_DAPM_MIXER("IN1L PGA", SND_SOC_NOPM, 0, 0, | |
649 | &in1l_pga, 1), | |
650 | SND_SOC_DAPM_MIXER("IN1R PGA", SND_SOC_NOPM, 0, 0, | |
651 | &in1r_pga, 1), | |
652 | ||
653 | SND_SOC_DAPM_MICBIAS("MICBIAS1", WM8995_POWER_MANAGEMENT_1, 8, 0), | |
654 | SND_SOC_DAPM_MICBIAS("MICBIAS2", WM8995_POWER_MANAGEMENT_1, 9, 0), | |
655 | ||
656 | SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8995_AIF1_CLOCKING_1, 0, 0, NULL, 0), | |
657 | SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8995_AIF2_CLOCKING_1, 0, 0, NULL, 0), | |
658 | SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8995_CLOCKING_1, 3, 0, NULL, 0), | |
659 | SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8995_CLOCKING_1, 2, 0, NULL, 0), | |
660 | SND_SOC_DAPM_SUPPLY("SYSDSPCLK", WM8995_CLOCKING_1, 1, 0, NULL, 0), | |
661 | SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event, | |
662 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
663 | ||
664 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture", 0, | |
665 | WM8995_POWER_MANAGEMENT_3, 9, 0), | |
666 | SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture", 0, | |
667 | WM8995_POWER_MANAGEMENT_3, 8, 0), | |
668 | SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, | |
669 | SND_SOC_NOPM, 0, 0), | |
670 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture", | |
671 | 0, WM8995_POWER_MANAGEMENT_3, 11, 0), | |
672 | SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture", | |
673 | 0, WM8995_POWER_MANAGEMENT_3, 10, 0), | |
674 | ||
675 | SND_SOC_DAPM_VIRT_MUX("ADCL Mux", SND_SOC_NOPM, 1, 0, | |
676 | &adcl_mux), | |
677 | SND_SOC_DAPM_VIRT_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, | |
678 | &adcr_mux), | |
679 | ||
680 | SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8995_POWER_MANAGEMENT_3, 5, 0), | |
681 | SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8995_POWER_MANAGEMENT_3, 4, 0), | |
682 | SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8995_POWER_MANAGEMENT_3, 3, 0), | |
683 | SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8995_POWER_MANAGEMENT_3, 2, 0), | |
684 | ||
685 | SND_SOC_DAPM_ADC("ADCL", NULL, WM8995_POWER_MANAGEMENT_3, 1, 0), | |
686 | SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0), | |
687 | ||
688 | SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0, | |
689 | aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)), | |
690 | SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0, | |
691 | aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)), | |
692 | SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0, | |
693 | aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)), | |
694 | SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0, | |
695 | aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)), | |
696 | ||
697 | SND_SOC_DAPM_AIF_IN("AIF1DAC1L", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
698 | 9, 0), | |
699 | SND_SOC_DAPM_AIF_IN("AIF1DAC1R", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
700 | 8, 0), | |
701 | SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, | |
702 | 0, 0), | |
703 | ||
704 | SND_SOC_DAPM_AIF_IN("AIF1DAC2L", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
705 | 11, 0), | |
706 | SND_SOC_DAPM_AIF_IN("AIF1DAC2R", NULL, 0, WM8995_POWER_MANAGEMENT_4, | |
707 | 10, 0), | |
708 | ||
709 | SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0, | |
710 | aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)), | |
711 | SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0, | |
712 | aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)), | |
713 | ||
714 | SND_SOC_DAPM_DAC("DAC2L", NULL, WM8995_POWER_MANAGEMENT_4, 3, 0), | |
715 | SND_SOC_DAPM_DAC("DAC2R", NULL, WM8995_POWER_MANAGEMENT_4, 2, 0), | |
716 | SND_SOC_DAPM_DAC("DAC1L", NULL, WM8995_POWER_MANAGEMENT_4, 1, 0), | |
717 | SND_SOC_DAPM_DAC("DAC1R", NULL, WM8995_POWER_MANAGEMENT_4, 0, 0), | |
718 | ||
719 | SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0, dac1l_mix, | |
720 | ARRAY_SIZE(dac1l_mix)), | |
721 | SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0, dac1r_mix, | |
722 | ARRAY_SIZE(dac1r_mix)), | |
723 | ||
724 | SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux), | |
725 | SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux), | |
726 | ||
727 | SND_SOC_DAPM_PGA_E("Headphone PGA", SND_SOC_NOPM, 0, 0, NULL, 0, | |
728 | hp_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
729 | ||
730 | SND_SOC_DAPM_SUPPLY("Headphone Supply", SND_SOC_NOPM, 0, 0, | |
731 | hp_supply_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), | |
732 | ||
733 | SND_SOC_DAPM_MUX("SPK1L Driver", WM8995_LEFT_PDM_SPEAKER_1, | |
734 | 4, 0, &spk1l_mux), | |
735 | SND_SOC_DAPM_MUX("SPK1R Driver", WM8995_RIGHT_PDM_SPEAKER_1, | |
736 | 4, 0, &spk1r_mux), | |
737 | SND_SOC_DAPM_MUX("SPK2L Driver", WM8995_LEFT_PDM_SPEAKER_2, | |
738 | 4, 0, &spk2l_mux), | |
739 | SND_SOC_DAPM_MUX("SPK2R Driver", WM8995_RIGHT_PDM_SPEAKER_2, | |
740 | 4, 0, &spk2r_mux), | |
741 | ||
742 | SND_SOC_DAPM_SUPPLY("LDO2", WM8995_POWER_MANAGEMENT_2, 1, 0, NULL, 0), | |
743 | ||
744 | SND_SOC_DAPM_OUTPUT("HP1L"), | |
745 | SND_SOC_DAPM_OUTPUT("HP1R"), | |
746 | SND_SOC_DAPM_OUTPUT("SPK1L"), | |
747 | SND_SOC_DAPM_OUTPUT("SPK1R"), | |
748 | SND_SOC_DAPM_OUTPUT("SPK2L"), | |
749 | SND_SOC_DAPM_OUTPUT("SPK2R") | |
750 | }; | |
751 | ||
752 | static const struct snd_soc_dapm_route wm8995_intercon[] = { | |
753 | { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys }, | |
754 | { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys }, | |
755 | ||
756 | { "DSP1CLK", NULL, "CLK_SYS" }, | |
757 | { "DSP2CLK", NULL, "CLK_SYS" }, | |
758 | { "SYSDSPCLK", NULL, "CLK_SYS" }, | |
759 | ||
760 | { "AIF1ADC1L", NULL, "AIF1CLK" }, | |
761 | { "AIF1ADC1L", NULL, "DSP1CLK" }, | |
762 | { "AIF1ADC1R", NULL, "AIF1CLK" }, | |
763 | { "AIF1ADC1R", NULL, "DSP1CLK" }, | |
764 | { "AIF1ADC1R", NULL, "SYSDSPCLK" }, | |
765 | ||
766 | { "AIF1ADC2L", NULL, "AIF1CLK" }, | |
767 | { "AIF1ADC2L", NULL, "DSP1CLK" }, | |
768 | { "AIF1ADC2R", NULL, "AIF1CLK" }, | |
769 | { "AIF1ADC2R", NULL, "DSP1CLK" }, | |
770 | { "AIF1ADC2R", NULL, "SYSDSPCLK" }, | |
771 | ||
772 | { "DMIC1L", NULL, "DMIC1DAT" }, | |
773 | { "DMIC1L", NULL, "CLK_SYS" }, | |
774 | { "DMIC1R", NULL, "DMIC1DAT" }, | |
775 | { "DMIC1R", NULL, "CLK_SYS" }, | |
776 | { "DMIC2L", NULL, "DMIC2DAT" }, | |
777 | { "DMIC2L", NULL, "CLK_SYS" }, | |
778 | { "DMIC2R", NULL, "DMIC2DAT" }, | |
779 | { "DMIC2R", NULL, "CLK_SYS" }, | |
780 | ||
781 | { "ADCL", NULL, "AIF1CLK" }, | |
782 | { "ADCL", NULL, "DSP1CLK" }, | |
783 | { "ADCL", NULL, "SYSDSPCLK" }, | |
784 | ||
785 | { "ADCR", NULL, "AIF1CLK" }, | |
786 | { "ADCR", NULL, "DSP1CLK" }, | |
787 | { "ADCR", NULL, "SYSDSPCLK" }, | |
788 | ||
789 | { "IN1L PGA", "IN1L Switch", "IN1L" }, | |
790 | { "IN1R PGA", "IN1R Switch", "IN1R" }, | |
791 | { "IN1L PGA", NULL, "LDO2" }, | |
792 | { "IN1R PGA", NULL, "LDO2" }, | |
793 | ||
794 | { "ADCL", NULL, "IN1L PGA" }, | |
795 | { "ADCR", NULL, "IN1R PGA" }, | |
796 | ||
797 | { "ADCL Mux", "ADC", "ADCL" }, | |
798 | { "ADCL Mux", "DMIC", "DMIC1L" }, | |
799 | { "ADCR Mux", "ADC", "ADCR" }, | |
800 | { "ADCR Mux", "DMIC", "DMIC1R" }, | |
801 | ||
802 | /* AIF1 outputs */ | |
803 | { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" }, | |
804 | { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" }, | |
805 | ||
806 | { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" }, | |
807 | { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" }, | |
808 | ||
809 | { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" }, | |
810 | { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" }, | |
811 | ||
812 | { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" }, | |
813 | { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" }, | |
814 | ||
815 | /* Sidetone */ | |
816 | { "Left Sidetone", "ADC/DMIC1", "AIF1ADC1L" }, | |
817 | { "Left Sidetone", "DMIC2", "AIF1ADC2L" }, | |
818 | { "Right Sidetone", "ADC/DMIC1", "AIF1ADC1R" }, | |
819 | { "Right Sidetone", "DMIC2", "AIF1ADC2R" }, | |
820 | ||
821 | { "AIF1DAC1L", NULL, "AIF1CLK" }, | |
822 | { "AIF1DAC1L", NULL, "DSP1CLK" }, | |
823 | { "AIF1DAC1R", NULL, "AIF1CLK" }, | |
824 | { "AIF1DAC1R", NULL, "DSP1CLK" }, | |
825 | { "AIF1DAC1R", NULL, "SYSDSPCLK" }, | |
826 | ||
827 | { "AIF1DAC2L", NULL, "AIF1CLK" }, | |
828 | { "AIF1DAC2L", NULL, "DSP1CLK" }, | |
829 | { "AIF1DAC2R", NULL, "AIF1CLK" }, | |
830 | { "AIF1DAC2R", NULL, "DSP1CLK" }, | |
831 | { "AIF1DAC2R", NULL, "SYSDSPCLK" }, | |
832 | ||
833 | { "DAC1L", NULL, "AIF1CLK" }, | |
834 | { "DAC1L", NULL, "DSP1CLK" }, | |
835 | { "DAC1L", NULL, "SYSDSPCLK" }, | |
836 | ||
837 | { "DAC1R", NULL, "AIF1CLK" }, | |
838 | { "DAC1R", NULL, "DSP1CLK" }, | |
839 | { "DAC1R", NULL, "SYSDSPCLK" }, | |
840 | ||
841 | { "AIF1DAC1L", NULL, "AIF1DACDAT" }, | |
842 | { "AIF1DAC1R", NULL, "AIF1DACDAT" }, | |
843 | { "AIF1DAC2L", NULL, "AIF1DACDAT" }, | |
844 | { "AIF1DAC2R", NULL, "AIF1DACDAT" }, | |
845 | ||
846 | /* DAC1 inputs */ | |
847 | { "DAC1L", NULL, "DAC1L Mixer" }, | |
848 | { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
849 | { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
850 | { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
851 | { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
852 | ||
853 | { "DAC1R", NULL, "DAC1R Mixer" }, | |
854 | { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
855 | { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
856 | { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" }, | |
857 | { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" }, | |
858 | ||
859 | /* DAC2/AIF2 outputs */ | |
860 | { "DAC2L", NULL, "AIF2DAC2L Mixer" }, | |
861 | { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" }, | |
862 | { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" }, | |
863 | ||
864 | { "DAC2R", NULL, "AIF2DAC2R Mixer" }, | |
865 | { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" }, | |
866 | { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" }, | |
867 | ||
868 | /* Output stages */ | |
869 | { "Headphone PGA", NULL, "DAC1L" }, | |
870 | { "Headphone PGA", NULL, "DAC1R" }, | |
871 | ||
872 | { "Headphone PGA", NULL, "DAC2L" }, | |
873 | { "Headphone PGA", NULL, "DAC2R" }, | |
874 | ||
875 | { "Headphone PGA", NULL, "Headphone Supply" }, | |
876 | { "Headphone PGA", NULL, "CLK_SYS" }, | |
877 | { "Headphone PGA", NULL, "LDO2" }, | |
878 | ||
879 | { "HP1L", NULL, "Headphone PGA" }, | |
880 | { "HP1R", NULL, "Headphone PGA" }, | |
881 | ||
882 | { "SPK1L Driver", "DAC1L", "DAC1L" }, | |
883 | { "SPK1L Driver", "DAC1R", "DAC1R" }, | |
884 | { "SPK1L Driver", "DAC2L", "DAC2L" }, | |
885 | { "SPK1L Driver", "DAC2R", "DAC2R" }, | |
886 | { "SPK1L Driver", NULL, "CLK_SYS" }, | |
887 | ||
888 | { "SPK1R Driver", "DAC1L", "DAC1L" }, | |
889 | { "SPK1R Driver", "DAC1R", "DAC1R" }, | |
890 | { "SPK1R Driver", "DAC2L", "DAC2L" }, | |
891 | { "SPK1R Driver", "DAC2R", "DAC2R" }, | |
892 | { "SPK1R Driver", NULL, "CLK_SYS" }, | |
893 | ||
894 | { "SPK2L Driver", "DAC1L", "DAC1L" }, | |
895 | { "SPK2L Driver", "DAC1R", "DAC1R" }, | |
896 | { "SPK2L Driver", "DAC2L", "DAC2L" }, | |
897 | { "SPK2L Driver", "DAC2R", "DAC2R" }, | |
898 | { "SPK2L Driver", NULL, "CLK_SYS" }, | |
899 | ||
900 | { "SPK2R Driver", "DAC1L", "DAC1L" }, | |
901 | { "SPK2R Driver", "DAC1R", "DAC1R" }, | |
902 | { "SPK2R Driver", "DAC2L", "DAC2L" }, | |
903 | { "SPK2R Driver", "DAC2R", "DAC2R" }, | |
904 | { "SPK2R Driver", NULL, "CLK_SYS" }, | |
905 | ||
906 | { "SPK1L", NULL, "SPK1L Driver" }, | |
907 | { "SPK1R", NULL, "SPK1R Driver" }, | |
908 | { "SPK2L", NULL, "SPK2L Driver" }, | |
909 | { "SPK2R", NULL, "SPK2R Driver" } | |
910 | }; | |
911 | ||
912 | static int wm8995_volatile(unsigned int reg) | |
913 | { | |
914 | /* out of bounds registers are generally considered | |
915 | * volatile to support register banks that are partially | |
916 | * owned by something else for e.g. a DSP | |
917 | */ | |
918 | if (reg > WM8995_MAX_CACHED_REGISTER) | |
919 | return 1; | |
920 | ||
921 | switch (reg) { | |
922 | case WM8995_SOFTWARE_RESET: | |
923 | case WM8995_DC_SERVO_READBACK_0: | |
924 | case WM8995_INTERRUPT_STATUS_1: | |
925 | case WM8995_INTERRUPT_STATUS_2: | |
926 | case WM8995_INTERRUPT_STATUS_1_MASK: | |
927 | case WM8995_INTERRUPT_STATUS_2_MASK: | |
928 | case WM8995_INTERRUPT_CONTROL: | |
929 | case WM8995_ACCESSORY_DETECT_MODE1: | |
930 | case WM8995_ACCESSORY_DETECT_MODE2: | |
931 | case WM8995_HEADPHONE_DETECT1: | |
932 | case WM8995_HEADPHONE_DETECT2: | |
933 | return 1; | |
934 | } | |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
939 | static int wm8995_aif_mute(struct snd_soc_dai *dai, int mute) | |
940 | { | |
941 | struct snd_soc_codec *codec = dai->codec; | |
942 | int mute_reg; | |
943 | ||
944 | switch (dai->id) { | |
945 | case 0: | |
946 | mute_reg = WM8995_AIF1_DAC1_FILTERS_1; | |
947 | break; | |
948 | case 1: | |
949 | mute_reg = WM8995_AIF2_DAC_FILTERS_1; | |
950 | break; | |
951 | default: | |
952 | return -EINVAL; | |
953 | } | |
954 | ||
955 | snd_soc_update_bits(codec, mute_reg, WM8995_AIF1DAC1_MUTE_MASK, | |
956 | !!mute << WM8995_AIF1DAC1_MUTE_SHIFT); | |
957 | return 0; | |
958 | } | |
959 | ||
960 | static int wm8995_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) | |
961 | { | |
962 | struct snd_soc_codec *codec; | |
963 | int master; | |
964 | int aif; | |
965 | ||
966 | codec = dai->codec; | |
967 | ||
968 | master = 0; | |
969 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
970 | case SND_SOC_DAIFMT_CBS_CFS: | |
971 | break; | |
972 | case SND_SOC_DAIFMT_CBM_CFM: | |
973 | master = WM8995_AIF1_MSTR; | |
974 | break; | |
975 | default: | |
976 | dev_err(dai->dev, "Unknown master/slave configuration\n"); | |
977 | return -EINVAL; | |
978 | } | |
979 | ||
980 | aif = 0; | |
981 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
982 | case SND_SOC_DAIFMT_DSP_B: | |
983 | aif |= WM8995_AIF1_LRCLK_INV; | |
984 | case SND_SOC_DAIFMT_DSP_A: | |
985 | aif |= (0x3 << WM8995_AIF1_FMT_SHIFT); | |
986 | break; | |
987 | case SND_SOC_DAIFMT_I2S: | |
988 | aif |= (0x2 << WM8995_AIF1_FMT_SHIFT); | |
989 | break; | |
990 | case SND_SOC_DAIFMT_RIGHT_J: | |
991 | break; | |
992 | case SND_SOC_DAIFMT_LEFT_J: | |
993 | aif |= (0x1 << WM8995_AIF1_FMT_SHIFT); | |
994 | break; | |
995 | default: | |
996 | dev_err(dai->dev, "Unknown dai format\n"); | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
1000 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1001 | case SND_SOC_DAIFMT_DSP_A: | |
1002 | case SND_SOC_DAIFMT_DSP_B: | |
1003 | /* frame inversion not valid for DSP modes */ | |
1004 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1005 | case SND_SOC_DAIFMT_NB_NF: | |
1006 | break; | |
1007 | case SND_SOC_DAIFMT_IB_NF: | |
1008 | aif |= WM8995_AIF1_BCLK_INV; | |
1009 | break; | |
1010 | default: | |
1011 | return -EINVAL; | |
1012 | } | |
1013 | break; | |
1014 | ||
1015 | case SND_SOC_DAIFMT_I2S: | |
1016 | case SND_SOC_DAIFMT_RIGHT_J: | |
1017 | case SND_SOC_DAIFMT_LEFT_J: | |
1018 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
1019 | case SND_SOC_DAIFMT_NB_NF: | |
1020 | break; | |
1021 | case SND_SOC_DAIFMT_IB_IF: | |
1022 | aif |= WM8995_AIF1_BCLK_INV | WM8995_AIF1_LRCLK_INV; | |
1023 | break; | |
1024 | case SND_SOC_DAIFMT_IB_NF: | |
1025 | aif |= WM8995_AIF1_BCLK_INV; | |
1026 | break; | |
1027 | case SND_SOC_DAIFMT_NB_IF: | |
1028 | aif |= WM8995_AIF1_LRCLK_INV; | |
1029 | break; | |
1030 | default: | |
1031 | return -EINVAL; | |
1032 | } | |
1033 | break; | |
1034 | default: | |
1035 | return -EINVAL; | |
1036 | } | |
1037 | ||
1038 | snd_soc_update_bits(codec, WM8995_AIF1_CONTROL_1, | |
1039 | WM8995_AIF1_BCLK_INV_MASK | | |
1040 | WM8995_AIF1_LRCLK_INV_MASK | | |
1041 | WM8995_AIF1_FMT_MASK, aif); | |
1042 | snd_soc_update_bits(codec, WM8995_AIF1_MASTER_SLAVE, | |
1043 | WM8995_AIF1_MSTR_MASK, master); | |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | static const int srs[] = { | |
1048 | 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, | |
1049 | 48000, 88200, 96000 | |
1050 | }; | |
1051 | ||
1052 | static const int fs_ratios[] = { | |
1053 | -1 /* reserved */, | |
1054 | 128, 192, 256, 384, 512, 768, 1024, 1408, 1536 | |
1055 | }; | |
1056 | ||
1057 | static const int bclk_divs[] = { | |
1058 | 10, 15, 20, 30, 40, 55, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480 | |
1059 | }; | |
1060 | ||
1061 | static int wm8995_hw_params(struct snd_pcm_substream *substream, | |
1062 | struct snd_pcm_hw_params *params, | |
1063 | struct snd_soc_dai *dai) | |
1064 | { | |
1065 | struct snd_soc_codec *codec; | |
1066 | struct wm8995_priv *wm8995; | |
1067 | int aif1_reg; | |
1068 | int bclk_reg; | |
1069 | int lrclk_reg; | |
1070 | int rate_reg; | |
1071 | int bclk_rate; | |
1072 | int aif1; | |
1073 | int lrclk, bclk; | |
1074 | int i, rate_val, best, best_val, cur_val; | |
1075 | ||
1076 | codec = dai->codec; | |
1077 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1078 | ||
1079 | switch (dai->id) { | |
1080 | case 0: | |
1081 | aif1_reg = WM8995_AIF1_CONTROL_1; | |
1082 | bclk_reg = WM8995_AIF1_BCLK; | |
1083 | rate_reg = WM8995_AIF1_RATE; | |
1084 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || | |
1085 | wm8995->lrclk_shared[0] */) { | |
1086 | lrclk_reg = WM8995_AIF1DAC_LRCLK; | |
1087 | } else { | |
1088 | lrclk_reg = WM8995_AIF1ADC_LRCLK; | |
1089 | dev_dbg(codec->dev, "AIF1 using split LRCLK\n"); | |
1090 | } | |
1091 | break; | |
1092 | case 1: | |
1093 | aif1_reg = WM8995_AIF2_CONTROL_1; | |
1094 | bclk_reg = WM8995_AIF2_BCLK; | |
1095 | rate_reg = WM8995_AIF2_RATE; | |
1096 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK /* || | |
1097 | wm8995->lrclk_shared[1] */) { | |
1098 | lrclk_reg = WM8995_AIF2DAC_LRCLK; | |
1099 | } else { | |
1100 | lrclk_reg = WM8995_AIF2ADC_LRCLK; | |
1101 | dev_dbg(codec->dev, "AIF2 using split LRCLK\n"); | |
1102 | } | |
1103 | break; | |
1104 | default: | |
1105 | return -EINVAL; | |
1106 | } | |
1107 | ||
1108 | bclk_rate = snd_soc_params_to_bclk(params); | |
1109 | if (bclk_rate < 0) | |
1110 | return bclk_rate; | |
1111 | ||
1112 | aif1 = 0; | |
1113 | switch (params_format(params)) { | |
1114 | case SNDRV_PCM_FORMAT_S16_LE: | |
1115 | break; | |
1116 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1117 | aif1 |= (0x1 << WM8995_AIF1_WL_SHIFT); | |
1118 | break; | |
1119 | case SNDRV_PCM_FORMAT_S24_LE: | |
1120 | aif1 |= (0x2 << WM8995_AIF1_WL_SHIFT); | |
1121 | break; | |
1122 | case SNDRV_PCM_FORMAT_S32_LE: | |
1123 | aif1 |= (0x3 << WM8995_AIF1_WL_SHIFT); | |
1124 | break; | |
1125 | default: | |
1126 | dev_err(dai->dev, "Unsupported word length %u\n", | |
1127 | params_format(params)); | |
1128 | return -EINVAL; | |
1129 | } | |
1130 | ||
1131 | /* try to find a suitable sample rate */ | |
1132 | for (i = 0; i < ARRAY_SIZE(srs); ++i) | |
1133 | if (srs[i] == params_rate(params)) | |
1134 | break; | |
1135 | if (i == ARRAY_SIZE(srs)) { | |
1136 | dev_err(dai->dev, "Sample rate %d is not supported\n", | |
1137 | params_rate(params)); | |
1138 | return -EINVAL; | |
1139 | } | |
1140 | rate_val = i << WM8995_AIF1_SR_SHIFT; | |
1141 | ||
1142 | dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i]); | |
1143 | dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", | |
1144 | dai->id + 1, wm8995->aifclk[dai->id], bclk_rate); | |
1145 | ||
1146 | /* AIFCLK/fs ratio; look for a close match in either direction */ | |
1147 | best = 1; | |
1148 | best_val = abs((fs_ratios[1] * params_rate(params)) | |
1149 | - wm8995->aifclk[dai->id]); | |
1150 | for (i = 2; i < ARRAY_SIZE(fs_ratios); i++) { | |
1151 | cur_val = abs((fs_ratios[i] * params_rate(params)) | |
1152 | - wm8995->aifclk[dai->id]); | |
1153 | if (cur_val >= best_val) | |
1154 | continue; | |
1155 | best = i; | |
1156 | best_val = cur_val; | |
1157 | } | |
1158 | rate_val |= best; | |
1159 | ||
1160 | dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n", | |
1161 | dai->id + 1, fs_ratios[best]); | |
1162 | ||
1163 | /* | |
1164 | * We may not get quite the right frequency if using | |
1165 | * approximate clocks so look for the closest match that is | |
1166 | * higher than the target (we need to ensure that there enough | |
1167 | * BCLKs to clock out the samples). | |
1168 | */ | |
1169 | best = 0; | |
1170 | bclk = 0; | |
1171 | for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { | |
1172 | cur_val = (wm8995->aifclk[dai->id] * 10 / bclk_divs[i]) - bclk_rate; | |
1173 | if (cur_val < 0) /* BCLK table is sorted */ | |
1174 | break; | |
1175 | best = i; | |
1176 | } | |
1177 | bclk |= best << WM8995_AIF1_BCLK_DIV_SHIFT; | |
1178 | ||
1179 | bclk_rate = wm8995->aifclk[dai->id] * 10 / bclk_divs[best]; | |
1180 | dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", | |
1181 | bclk_divs[best], bclk_rate); | |
1182 | ||
1183 | lrclk = bclk_rate / params_rate(params); | |
1184 | dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n", | |
1185 | lrclk, bclk_rate / lrclk); | |
1186 | ||
1187 | snd_soc_update_bits(codec, aif1_reg, | |
1188 | WM8995_AIF1_WL_MASK, aif1); | |
1189 | snd_soc_update_bits(codec, bclk_reg, | |
1190 | WM8995_AIF1_BCLK_DIV_MASK, bclk); | |
1191 | snd_soc_update_bits(codec, lrclk_reg, | |
1192 | WM8995_AIF1DAC_RATE_MASK, lrclk); | |
1193 | snd_soc_update_bits(codec, rate_reg, | |
1194 | WM8995_AIF1_SR_MASK | | |
1195 | WM8995_AIF1CLK_RATE_MASK, rate_val); | |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | static int wm8995_set_tristate(struct snd_soc_dai *codec_dai, int tristate) | |
1200 | { | |
1201 | struct snd_soc_codec *codec = codec_dai->codec; | |
1202 | int reg, val, mask; | |
1203 | ||
1204 | switch (codec_dai->id) { | |
1205 | case 0: | |
1206 | reg = WM8995_AIF1_MASTER_SLAVE; | |
1207 | mask = WM8995_AIF1_TRI; | |
1208 | break; | |
1209 | case 1: | |
1210 | reg = WM8995_AIF2_MASTER_SLAVE; | |
1211 | mask = WM8995_AIF2_TRI; | |
1212 | break; | |
1213 | case 2: | |
1214 | reg = WM8995_POWER_MANAGEMENT_5; | |
1215 | mask = WM8995_AIF3_TRI; | |
1216 | break; | |
1217 | default: | |
1218 | return -EINVAL; | |
1219 | } | |
1220 | ||
1221 | if (tristate) | |
1222 | val = mask; | |
1223 | else | |
1224 | val = 0; | |
1225 | ||
1226 | return snd_soc_update_bits(codec, reg, mask, reg); | |
1227 | } | |
1228 | ||
1229 | /* The size in bits of the FLL divide multiplied by 10 | |
1230 | * to allow rounding later */ | |
1231 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1232 | ||
1233 | struct fll_div { | |
1234 | u16 outdiv; | |
1235 | u16 n; | |
1236 | u16 k; | |
1237 | u16 clk_ref_div; | |
1238 | u16 fll_fratio; | |
1239 | }; | |
1240 | ||
1241 | static int wm8995_get_fll_config(struct fll_div *fll, | |
1242 | int freq_in, int freq_out) | |
1243 | { | |
1244 | u64 Kpart; | |
1245 | unsigned int K, Ndiv, Nmod; | |
1246 | ||
1247 | pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out); | |
1248 | ||
1249 | /* Scale the input frequency down to <= 13.5MHz */ | |
1250 | fll->clk_ref_div = 0; | |
1251 | while (freq_in > 13500000) { | |
1252 | fll->clk_ref_div++; | |
1253 | freq_in /= 2; | |
1254 | ||
1255 | if (fll->clk_ref_div > 3) | |
1256 | return -EINVAL; | |
1257 | } | |
1258 | pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in); | |
1259 | ||
1260 | /* Scale the output to give 90MHz<=Fvco<=100MHz */ | |
1261 | fll->outdiv = 3; | |
1262 | while (freq_out * (fll->outdiv + 1) < 90000000) { | |
1263 | fll->outdiv++; | |
1264 | if (fll->outdiv > 63) | |
1265 | return -EINVAL; | |
1266 | } | |
1267 | freq_out *= fll->outdiv + 1; | |
1268 | pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out); | |
1269 | ||
1270 | if (freq_in > 1000000) { | |
1271 | fll->fll_fratio = 0; | |
1272 | } else if (freq_in > 256000) { | |
1273 | fll->fll_fratio = 1; | |
1274 | freq_in *= 2; | |
1275 | } else if (freq_in > 128000) { | |
1276 | fll->fll_fratio = 2; | |
1277 | freq_in *= 4; | |
1278 | } else if (freq_in > 64000) { | |
1279 | fll->fll_fratio = 3; | |
1280 | freq_in *= 8; | |
1281 | } else { | |
1282 | fll->fll_fratio = 4; | |
1283 | freq_in *= 16; | |
1284 | } | |
1285 | pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in); | |
1286 | ||
1287 | /* Now, calculate N.K */ | |
1288 | Ndiv = freq_out / freq_in; | |
1289 | ||
1290 | fll->n = Ndiv; | |
1291 | Nmod = freq_out % freq_in; | |
1292 | pr_debug("Nmod=%d\n", Nmod); | |
1293 | ||
1294 | /* Calculate fractional part - scale up so we can round. */ | |
1295 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1296 | ||
1297 | do_div(Kpart, freq_in); | |
1298 | ||
1299 | K = Kpart & 0xFFFFFFFF; | |
1300 | ||
1301 | if ((K % 10) >= 5) | |
1302 | K += 5; | |
1303 | ||
1304 | /* Move down to proper range now rounding is done */ | |
1305 | fll->k = K / 10; | |
1306 | ||
1307 | pr_debug("N=%x K=%x\n", fll->n, fll->k); | |
1308 | ||
1309 | return 0; | |
1310 | } | |
1311 | ||
1312 | static int wm8995_set_fll(struct snd_soc_dai *dai, int id, | |
1313 | int src, unsigned int freq_in, | |
1314 | unsigned int freq_out) | |
1315 | { | |
1316 | struct snd_soc_codec *codec; | |
1317 | struct wm8995_priv *wm8995; | |
1318 | int reg_offset, ret; | |
1319 | struct fll_div fll; | |
1320 | u16 reg, aif1, aif2; | |
1321 | ||
1322 | codec = dai->codec; | |
1323 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1324 | ||
1325 | aif1 = snd_soc_read(codec, WM8995_AIF1_CLOCKING_1) | |
1326 | & WM8995_AIF1CLK_ENA; | |
1327 | ||
1328 | aif2 = snd_soc_read(codec, WM8995_AIF2_CLOCKING_1) | |
1329 | & WM8995_AIF2CLK_ENA; | |
1330 | ||
1331 | switch (id) { | |
1332 | case WM8995_FLL1: | |
1333 | reg_offset = 0; | |
1334 | id = 0; | |
1335 | break; | |
1336 | case WM8995_FLL2: | |
1337 | reg_offset = 0x20; | |
1338 | id = 1; | |
1339 | break; | |
1340 | default: | |
1341 | return -EINVAL; | |
1342 | } | |
1343 | ||
1344 | switch (src) { | |
1345 | case 0: | |
1346 | /* Allow no source specification when stopping */ | |
1347 | if (freq_out) | |
1348 | return -EINVAL; | |
1349 | break; | |
1350 | case WM8995_FLL_SRC_MCLK1: | |
1351 | case WM8995_FLL_SRC_MCLK2: | |
1352 | case WM8995_FLL_SRC_LRCLK: | |
1353 | case WM8995_FLL_SRC_BCLK: | |
1354 | break; | |
1355 | default: | |
1356 | return -EINVAL; | |
1357 | } | |
1358 | ||
1359 | /* Are we changing anything? */ | |
1360 | if (wm8995->fll[id].src == src && | |
1361 | wm8995->fll[id].in == freq_in && wm8995->fll[id].out == freq_out) | |
1362 | return 0; | |
1363 | ||
1364 | /* If we're stopping the FLL redo the old config - no | |
1365 | * registers will actually be written but we avoid GCC flow | |
1366 | * analysis bugs spewing warnings. | |
1367 | */ | |
1368 | if (freq_out) | |
1369 | ret = wm8995_get_fll_config(&fll, freq_in, freq_out); | |
1370 | else | |
1371 | ret = wm8995_get_fll_config(&fll, wm8995->fll[id].in, | |
1372 | wm8995->fll[id].out); | |
1373 | if (ret < 0) | |
1374 | return ret; | |
1375 | ||
1376 | /* Gate the AIF clocks while we reclock */ | |
1377 | snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, | |
1378 | WM8995_AIF1CLK_ENA_MASK, 0); | |
1379 | snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, | |
1380 | WM8995_AIF2CLK_ENA_MASK, 0); | |
1381 | ||
1382 | /* We always need to disable the FLL while reconfiguring */ | |
1383 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, | |
1384 | WM8995_FLL1_ENA_MASK, 0); | |
1385 | ||
1386 | reg = (fll.outdiv << WM8995_FLL1_OUTDIV_SHIFT) | | |
1387 | (fll.fll_fratio << WM8995_FLL1_FRATIO_SHIFT); | |
1388 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_2 + reg_offset, | |
1389 | WM8995_FLL1_OUTDIV_MASK | | |
1390 | WM8995_FLL1_FRATIO_MASK, reg); | |
1391 | ||
1392 | snd_soc_write(codec, WM8995_FLL1_CONTROL_3 + reg_offset, fll.k); | |
1393 | ||
1394 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_4 + reg_offset, | |
1395 | WM8995_FLL1_N_MASK, | |
1396 | fll.n << WM8995_FLL1_N_SHIFT); | |
1397 | ||
1398 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_5 + reg_offset, | |
1399 | WM8995_FLL1_REFCLK_DIV_MASK | | |
1400 | WM8995_FLL1_REFCLK_SRC_MASK, | |
1401 | (fll.clk_ref_div << WM8995_FLL1_REFCLK_DIV_SHIFT) | | |
1402 | (src - 1)); | |
1403 | ||
1404 | if (freq_out) | |
1405 | snd_soc_update_bits(codec, WM8995_FLL1_CONTROL_1 + reg_offset, | |
1406 | WM8995_FLL1_ENA_MASK, WM8995_FLL1_ENA); | |
1407 | ||
1408 | wm8995->fll[id].in = freq_in; | |
1409 | wm8995->fll[id].out = freq_out; | |
1410 | wm8995->fll[id].src = src; | |
1411 | ||
1412 | /* Enable any gated AIF clocks */ | |
1413 | snd_soc_update_bits(codec, WM8995_AIF1_CLOCKING_1, | |
1414 | WM8995_AIF1CLK_ENA_MASK, aif1); | |
1415 | snd_soc_update_bits(codec, WM8995_AIF2_CLOCKING_1, | |
1416 | WM8995_AIF2CLK_ENA_MASK, aif2); | |
1417 | ||
1418 | configure_clock(codec); | |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | ||
1423 | static int wm8995_set_dai_sysclk(struct snd_soc_dai *dai, | |
1424 | int clk_id, unsigned int freq, int dir) | |
1425 | { | |
1426 | struct snd_soc_codec *codec; | |
1427 | struct wm8995_priv *wm8995; | |
1428 | ||
1429 | codec = dai->codec; | |
1430 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1431 | ||
1432 | switch (dai->id) { | |
1433 | case 0: | |
1434 | case 1: | |
1435 | break; | |
1436 | default: | |
1437 | /* AIF3 shares clocking with AIF1/2 */ | |
1438 | return -EINVAL; | |
1439 | } | |
1440 | ||
1441 | switch (clk_id) { | |
1442 | case WM8995_SYSCLK_MCLK1: | |
1443 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; | |
1444 | wm8995->mclk[0] = freq; | |
1445 | dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n", | |
1446 | dai->id + 1, freq); | |
1447 | break; | |
1448 | case WM8995_SYSCLK_MCLK2: | |
1449 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_MCLK1; | |
1450 | wm8995->mclk[1] = freq; | |
1451 | dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n", | |
1452 | dai->id + 1, freq); | |
1453 | break; | |
1454 | case WM8995_SYSCLK_FLL1: | |
1455 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL1; | |
1456 | dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id + 1); | |
1457 | break; | |
1458 | case WM8995_SYSCLK_FLL2: | |
1459 | wm8995->sysclk[dai->id] = WM8995_SYSCLK_FLL2; | |
1460 | dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id + 1); | |
1461 | break; | |
1462 | case WM8995_SYSCLK_OPCLK: | |
1463 | default: | |
1464 | dev_err(dai->dev, "Unknown clock source %d\n", clk_id); | |
1465 | return -EINVAL; | |
1466 | } | |
1467 | ||
1468 | configure_clock(codec); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static int wm8995_set_bias_level(struct snd_soc_codec *codec, | |
1474 | enum snd_soc_bias_level level) | |
1475 | { | |
1476 | struct wm8995_priv *wm8995; | |
1477 | int ret; | |
1478 | ||
1479 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1480 | switch (level) { | |
1481 | case SND_SOC_BIAS_ON: | |
1482 | case SND_SOC_BIAS_PREPARE: | |
1483 | break; | |
1484 | case SND_SOC_BIAS_STANDBY: | |
1485 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { | |
1486 | ret = snd_soc_cache_sync(codec); | |
1487 | if (ret) { | |
1488 | dev_err(codec->dev, | |
1489 | "Failed to sync cache: %d\n", ret); | |
1490 | return ret; | |
1491 | } | |
1492 | ||
1493 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
1494 | WM8995_BG_ENA_MASK, WM8995_BG_ENA); | |
1495 | ||
1496 | } | |
1497 | break; | |
1498 | case SND_SOC_BIAS_OFF: | |
1499 | snd_soc_update_bits(codec, WM8995_POWER_MANAGEMENT_1, | |
1500 | WM8995_BG_ENA_MASK, 0); | |
1501 | break; | |
1502 | } | |
1503 | ||
1504 | codec->dapm.bias_level = level; | |
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | #ifdef CONFIG_PM | |
1509 | static int wm8995_suspend(struct snd_soc_codec *codec, pm_message_t state) | |
1510 | { | |
1511 | wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | static int wm8995_resume(struct snd_soc_codec *codec) | |
1516 | { | |
1517 | wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1518 | return 0; | |
1519 | } | |
1520 | #else | |
1521 | #define wm8995_suspend NULL | |
1522 | #define wm8995_resume NULL | |
1523 | #endif | |
1524 | ||
1525 | static int wm8995_remove(struct snd_soc_codec *codec) | |
1526 | { | |
1527 | struct wm8995_priv *wm8995; | |
1528 | struct i2c_client *i2c; | |
1529 | ||
1530 | i2c = container_of(codec->dev, struct i2c_client, dev); | |
1531 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1532 | wm8995_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1533 | return 0; | |
1534 | } | |
1535 | ||
1536 | static int wm8995_probe(struct snd_soc_codec *codec) | |
1537 | { | |
1538 | struct wm8995_priv *wm8995; | |
1539 | int ret; | |
1540 | ||
1541 | codec->dapm.idle_bias_off = 1; | |
1542 | wm8995 = snd_soc_codec_get_drvdata(codec); | |
1543 | ||
1544 | ret = snd_soc_codec_set_cache_io(codec, 16, 16, wm8995->control_type); | |
1545 | if (ret < 0) { | |
1546 | dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret); | |
1547 | return ret; | |
1548 | } | |
1549 | ||
1550 | ret = snd_soc_read(codec, WM8995_SOFTWARE_RESET); | |
1551 | if (ret < 0) { | |
1552 | dev_err(codec->dev, "Failed to read device ID: %d\n", ret); | |
1553 | return ret; | |
1554 | } | |
1555 | ||
1556 | if (ret != 0x8995) { | |
1557 | dev_err(codec->dev, "Invalid device ID: %#x\n", ret); | |
1558 | return -EINVAL; | |
1559 | } | |
1560 | ||
1561 | ret = snd_soc_write(codec, WM8995_SOFTWARE_RESET, 0); | |
1562 | if (ret < 0) { | |
1563 | dev_err(codec->dev, "Failed to issue reset: %d\n", ret); | |
1564 | return ret; | |
1565 | } | |
1566 | ||
1567 | wm8995_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1568 | ||
1569 | /* Latch volume updates (right only; we always do left then right). */ | |
1570 | snd_soc_update_bits(codec, WM8995_AIF1_DAC1_RIGHT_VOLUME, | |
1571 | WM8995_AIF1DAC1_VU_MASK, WM8995_AIF1DAC1_VU); | |
1572 | snd_soc_update_bits(codec, WM8995_AIF1_DAC2_RIGHT_VOLUME, | |
1573 | WM8995_AIF1DAC2_VU_MASK, WM8995_AIF1DAC2_VU); | |
1574 | snd_soc_update_bits(codec, WM8995_AIF2_DAC_RIGHT_VOLUME, | |
1575 | WM8995_AIF2DAC_VU_MASK, WM8995_AIF2DAC_VU); | |
1576 | snd_soc_update_bits(codec, WM8995_AIF1_ADC1_RIGHT_VOLUME, | |
1577 | WM8995_AIF1ADC1_VU_MASK, WM8995_AIF1ADC1_VU); | |
1578 | snd_soc_update_bits(codec, WM8995_AIF1_ADC2_RIGHT_VOLUME, | |
1579 | WM8995_AIF1ADC2_VU_MASK, WM8995_AIF1ADC2_VU); | |
1580 | snd_soc_update_bits(codec, WM8995_AIF2_ADC_RIGHT_VOLUME, | |
1581 | WM8995_AIF2ADC_VU_MASK, WM8995_AIF1ADC2_VU); | |
1582 | snd_soc_update_bits(codec, WM8995_DAC1_RIGHT_VOLUME, | |
1583 | WM8995_DAC1_VU_MASK, WM8995_DAC1_VU); | |
1584 | snd_soc_update_bits(codec, WM8995_DAC2_RIGHT_VOLUME, | |
1585 | WM8995_DAC2_VU_MASK, WM8995_DAC2_VU); | |
1586 | snd_soc_update_bits(codec, WM8995_RIGHT_LINE_INPUT_1_VOLUME, | |
1587 | WM8995_IN1_VU_MASK, WM8995_IN1_VU); | |
1588 | ||
1589 | wm8995_update_class_w(codec); | |
1590 | ||
1591 | snd_soc_add_controls(codec, wm8995_snd_controls, | |
1592 | ARRAY_SIZE(wm8995_snd_controls)); | |
1593 | snd_soc_dapm_new_controls(&codec->dapm, wm8995_dapm_widgets, | |
1594 | ARRAY_SIZE(wm8995_dapm_widgets)); | |
1595 | snd_soc_dapm_add_routes(&codec->dapm, wm8995_intercon, | |
1596 | ARRAY_SIZE(wm8995_intercon)); | |
1597 | ||
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | #define WM8995_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1602 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
1603 | ||
1604 | static struct snd_soc_dai_ops wm8995_aif1_dai_ops = { | |
1605 | .set_sysclk = wm8995_set_dai_sysclk, | |
1606 | .set_fmt = wm8995_set_dai_fmt, | |
1607 | .hw_params = wm8995_hw_params, | |
1608 | .digital_mute = wm8995_aif_mute, | |
1609 | .set_pll = wm8995_set_fll, | |
1610 | .set_tristate = wm8995_set_tristate, | |
1611 | }; | |
1612 | ||
1613 | static struct snd_soc_dai_ops wm8995_aif2_dai_ops = { | |
1614 | .set_sysclk = wm8995_set_dai_sysclk, | |
1615 | .set_fmt = wm8995_set_dai_fmt, | |
1616 | .hw_params = wm8995_hw_params, | |
1617 | .digital_mute = wm8995_aif_mute, | |
1618 | .set_pll = wm8995_set_fll, | |
1619 | .set_tristate = wm8995_set_tristate, | |
1620 | }; | |
1621 | ||
1622 | static struct snd_soc_dai_ops wm8995_aif3_dai_ops = { | |
1623 | .set_tristate = wm8995_set_tristate, | |
1624 | }; | |
1625 | ||
1626 | static struct snd_soc_dai_driver wm8995_dai[] = { | |
1627 | { | |
1628 | .name = "wm8995-aif1", | |
1629 | .playback = { | |
1630 | .stream_name = "AIF1 Playback", | |
1631 | .channels_min = 2, | |
1632 | .channels_max = 2, | |
1633 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1634 | .formats = WM8995_FORMATS | |
1635 | }, | |
1636 | .capture = { | |
1637 | .stream_name = "AIF1 Capture", | |
1638 | .channels_min = 2, | |
1639 | .channels_max = 2, | |
1640 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1641 | .formats = WM8995_FORMATS | |
1642 | }, | |
1643 | .ops = &wm8995_aif1_dai_ops | |
1644 | }, | |
1645 | { | |
1646 | .name = "wm8995-aif2", | |
1647 | .playback = { | |
1648 | .stream_name = "AIF2 Playback", | |
1649 | .channels_min = 2, | |
1650 | .channels_max = 2, | |
1651 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1652 | .formats = WM8995_FORMATS | |
1653 | }, | |
1654 | .capture = { | |
1655 | .stream_name = "AIF2 Capture", | |
1656 | .channels_min = 2, | |
1657 | .channels_max = 2, | |
1658 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1659 | .formats = WM8995_FORMATS | |
1660 | }, | |
1661 | .ops = &wm8995_aif2_dai_ops | |
1662 | }, | |
1663 | { | |
1664 | .name = "wm8995-aif3", | |
1665 | .playback = { | |
1666 | .stream_name = "AIF3 Playback", | |
1667 | .channels_min = 2, | |
1668 | .channels_max = 2, | |
1669 | .rates = SNDRV_PCM_RATE_8000_96000, | |
1670 | .formats = WM8995_FORMATS | |
1671 | }, | |
1672 | .capture = { | |
1673 | .stream_name = "AIF3 Capture", | |
1674 | .channels_min = 2, | |
1675 | .channels_max = 2, | |
1676 | .rates = SNDRV_PCM_RATE_8000_48000, | |
1677 | .formats = WM8995_FORMATS | |
1678 | }, | |
1679 | .ops = &wm8995_aif3_dai_ops | |
1680 | } | |
1681 | }; | |
1682 | ||
1683 | static struct snd_soc_codec_driver soc_codec_dev_wm8995 = { | |
1684 | .probe = wm8995_probe, | |
1685 | .remove = wm8995_remove, | |
1686 | .suspend = wm8995_suspend, | |
1687 | .resume = wm8995_resume, | |
1688 | .set_bias_level = wm8995_set_bias_level, | |
1689 | .reg_cache_size = ARRAY_SIZE(wm8995_reg_defs), | |
1690 | .reg_word_size = sizeof(u16), | |
1691 | .reg_cache_default = wm8995_reg_defs, | |
1692 | .volatile_register = wm8995_volatile, | |
1693 | .compress_type = SND_SOC_RBTREE_COMPRESSION | |
1694 | }; | |
1695 | ||
1696 | #if defined(CONFIG_SPI_MASTER) | |
1697 | static int __devinit wm8995_spi_probe(struct spi_device *spi) | |
1698 | { | |
1699 | struct wm8995_priv *wm8995; | |
1700 | int ret; | |
1701 | ||
1702 | wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); | |
1703 | if (!wm8995) | |
1704 | return -ENOMEM; | |
1705 | ||
1706 | wm8995->control_type = SND_SOC_SPI; | |
1707 | spi_set_drvdata(spi, wm8995); | |
1708 | ||
1709 | ret = snd_soc_register_codec(&spi->dev, | |
1710 | &soc_codec_dev_wm8995, wm8995_dai, | |
1711 | ARRAY_SIZE(wm8995_dai)); | |
1712 | if (ret < 0) | |
1713 | kfree(wm8995); | |
1714 | return ret; | |
1715 | } | |
1716 | ||
1717 | static int __devexit wm8995_spi_remove(struct spi_device *spi) | |
1718 | { | |
1719 | snd_soc_unregister_codec(&spi->dev); | |
1720 | kfree(spi_get_drvdata(spi)); | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | static struct spi_driver wm8995_spi_driver = { | |
1725 | .driver = { | |
1726 | .name = "wm8995", | |
1727 | .owner = THIS_MODULE, | |
1728 | }, | |
1729 | .probe = wm8995_spi_probe, | |
1730 | .remove = __devexit_p(wm8995_spi_remove) | |
1731 | }; | |
1732 | #endif | |
1733 | ||
1734 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1735 | static __devinit int wm8995_i2c_probe(struct i2c_client *i2c, | |
1736 | const struct i2c_device_id *id) | |
1737 | { | |
1738 | struct wm8995_priv *wm8995; | |
1739 | int ret; | |
1740 | ||
1741 | wm8995 = kzalloc(sizeof *wm8995, GFP_KERNEL); | |
1742 | if (!wm8995) | |
1743 | return -ENOMEM; | |
1744 | ||
1745 | wm8995->control_type = SND_SOC_I2C; | |
1746 | i2c_set_clientdata(i2c, wm8995); | |
1747 | ||
1748 | ret = snd_soc_register_codec(&i2c->dev, | |
1749 | &soc_codec_dev_wm8995, wm8995_dai, | |
1750 | ARRAY_SIZE(wm8995_dai)); | |
1751 | if (ret < 0) | |
1752 | kfree(wm8995); | |
1753 | return ret; | |
1754 | } | |
1755 | ||
1756 | static __devexit int wm8995_i2c_remove(struct i2c_client *client) | |
1757 | { | |
1758 | snd_soc_unregister_codec(&client->dev); | |
1759 | kfree(i2c_get_clientdata(client)); | |
1760 | return 0; | |
1761 | } | |
1762 | ||
1763 | static const struct i2c_device_id wm8995_i2c_id[] = { | |
1764 | {"wm8995", 0}, | |
1765 | {} | |
1766 | }; | |
1767 | ||
1768 | MODULE_DEVICE_TABLE(i2c, wm8995_i2c_id); | |
1769 | ||
1770 | static struct i2c_driver wm8995_i2c_driver = { | |
1771 | .driver = { | |
1772 | .name = "wm8995", | |
1773 | .owner = THIS_MODULE, | |
1774 | }, | |
1775 | .probe = wm8995_i2c_probe, | |
1776 | .remove = __devexit_p(wm8995_i2c_remove), | |
1777 | .id_table = wm8995_i2c_id | |
1778 | }; | |
1779 | #endif | |
1780 | ||
1781 | static int __init wm8995_modinit(void) | |
1782 | { | |
1783 | int ret = 0; | |
1784 | ||
1785 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1786 | ret = i2c_add_driver(&wm8995_i2c_driver); | |
1787 | if (ret) { | |
1788 | printk(KERN_ERR "Failed to register wm8995 I2C driver: %d\n", | |
1789 | ret); | |
1790 | } | |
1791 | #endif | |
1792 | #if defined(CONFIG_SPI_MASTER) | |
1793 | ret = spi_register_driver(&wm8995_spi_driver); | |
1794 | if (ret) { | |
1795 | printk(KERN_ERR "Failed to register wm8995 SPI driver: %d\n", | |
1796 | ret); | |
1797 | } | |
1798 | #endif | |
1799 | return ret; | |
1800 | } | |
1801 | ||
1802 | module_init(wm8995_modinit); | |
1803 | ||
1804 | static void __exit wm8995_exit(void) | |
1805 | { | |
1806 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
1807 | i2c_del_driver(&wm8995_i2c_driver); | |
1808 | #endif | |
1809 | #if defined(CONFIG_SPI_MASTER) | |
1810 | spi_unregister_driver(&wm8995_spi_driver); | |
1811 | #endif | |
1812 | } | |
1813 | ||
1814 | module_exit(wm8995_exit); | |
1815 | ||
1816 | MODULE_DESCRIPTION("ASoC WM8995 driver"); | |
1817 | MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>"); | |
1818 | MODULE_LICENSE("GPL"); |