projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: Don't resync WM8903 register cache on reset
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
3ee845ac 18#include <linux/device.h>
86ed3669
MB		 19#include <linux/pm.h>
20#include <linux/i2c.h>
7cfa467b 21#include <linux/regmap.h>
5a0e3ad6 22#include <linux/slab.h>
86ed3669
MB		 23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
86ed3669
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include <sound/wm9081.h>
31#include "wm9081.h"
32
7cfa467b
MB		 33static struct reg_default wm9081_reg[] = {
34 { 0, 0x9081 }, /* R0 - Software Reset */
35 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
36 { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
37 { 4, 0x0001 }, /* R4 - VMID Control */
38 { 5, 0x0068 }, /* R5 - Bias Control 1 */
39 { 7, 0x0000 }, /* R7 - Analogue Mixer */
40 { 8, 0x0000 }, /* R8 - Anti Pop Control */
41 { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
42 { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
43 { 11, 0x0180 }, /* R11 - Power Management */
44 { 12, 0x0000 }, /* R12 - Clock Control 1 */
45 { 13, 0x0038 }, /* R13 - Clock Control 2 */
46 { 14, 0x4000 }, /* R14 - Clock Control 3 */
47 { 16, 0x0000 }, /* R16 - FLL Control 1 */
48 { 17, 0x0200 }, /* R17 - FLL Control 2 */
49 { 18, 0x0000 }, /* R18 - FLL Control 3 */
50 { 19, 0x0204 }, /* R19 - FLL Control 4 */
51 { 20, 0x0000 }, /* R20 - FLL Control 5 */
52 { 22, 0x0000 }, /* R22 - Audio Interface 1 */
53 { 23, 0x0002 }, /* R23 - Audio Interface 2 */
54 { 24, 0x0008 }, /* R24 - Audio Interface 3 */
55 { 25, 0x0022 }, /* R25 - Audio Interface 4 */
56 { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
57 { 28, 0x0000 }, /* R28 - Interrupt Polarity */
58 { 29, 0x0000 }, /* R29 - Interrupt Control */
59 { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
60 { 31, 0x0008 }, /* R31 - DAC Digital 2 */
61 { 32, 0x09AF }, /* R32 - DRC 1 */
62 { 33, 0x4201 }, /* R33 - DRC 2 */
63 { 34, 0x0000 }, /* R34 - DRC 3 */
64 { 35, 0x0000 }, /* R35 - DRC 4 */
65 { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
66 { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
67 { 40, 0x0002 }, /* R40 - MW Slave 1 */
68 { 42, 0x0000 }, /* R42 - EQ 1 */
69 { 43, 0x0000 }, /* R43 - EQ 2 */
70 { 44, 0x0FCA }, /* R44 - EQ 3 */
71 { 45, 0x0400 }, /* R45 - EQ 4 */
72 { 46, 0x00B8 }, /* R46 - EQ 5 */
73 { 47, 0x1EB5 }, /* R47 - EQ 6 */
74 { 48, 0xF145 }, /* R48 - EQ 7 */
75 { 49, 0x0B75 }, /* R49 - EQ 8 */
76 { 50, 0x01C5 }, /* R50 - EQ 9 */
77 { 51, 0x169E }, /* R51 - EQ 10 */
78 { 52, 0xF829 }, /* R52 - EQ 11 */
79 { 53, 0x07AD }, /* R53 - EQ 12 */
80 { 54, 0x1103 }, /* R54 - EQ 13 */
81 { 55, 0x1C58 }, /* R55 - EQ 14 */
82 { 56, 0xF373 }, /* R56 - EQ 15 */
83 { 57, 0x0A54 }, /* R57 - EQ 16 */
84 { 58, 0x0558 }, /* R58 - EQ 17 */
85 { 59, 0x0564 }, /* R59 - EQ 18 */
86 { 60, 0x0559 }, /* R60 - EQ 19 */
87 { 61, 0x4000 }, /* R61 - EQ 20 */
86ed3669
MB		 88};
89
90static struct {
91 int ratio;
92 int clk_sys_rate;
93} clk_sys_rates[] = {
94 { 64, 0 },
95 { 128, 1 },
96 { 192, 2 },
97 { 256, 3 },
98 { 384, 4 },
99 { 512, 5 },
100 { 768, 6 },
101 { 1024, 7 },
102 { 1408, 8 },
103 { 1536, 9 },
104};
105
106static struct {
107 int rate;
108 int sample_rate;
109} sample_rates[] = {
110 { 8000, 0 },
111 { 11025, 1 },
112 { 12000, 2 },
113 { 16000, 3 },
114 { 22050, 4 },
115 { 24000, 5 },
116 { 32000, 6 },
117 { 44100, 7 },
118 { 48000, 8 },
119 { 88200, 9 },
120 { 96000, 10 },
121};
122
123static struct {
124 int div; /* *10 due to .5s */
125 int bclk_div;
126} bclk_divs[] = {
127 { 10, 0 },
128 { 15, 1 },
129 { 20, 2 },
130 { 30, 3 },
131 { 40, 4 },
132 { 50, 5 },
133 { 55, 6 },
134 { 60, 7 },
135 { 80, 8 },
136 { 100, 9 },
137 { 110, 10 },
138 { 120, 11 },
139 { 160, 12 },
140 { 200, 13 },
141 { 220, 14 },
142 { 240, 15 },
143 { 250, 16 },
144 { 300, 17 },
145 { 320, 18 },
146 { 440, 19 },
147 { 480, 20 },
148};
149
150struct wm9081_priv {
7cfa467b 151 struct regmap *regmap;
86ed3669
MB		 152 int sysclk_source;
153 int mclk_rate;
154 int sysclk_rate;
155 int fs;
156 int bclk;
157 int master;
158 int fll_fref;
159 int fll_fout;
e0026bea 160 int tdm_width;
4a5f7bda 161 struct wm9081_pdata pdata;
86ed3669
MB		 162};
163
7cfa467b 164static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
86ed3669
MB		 165{
166 switch (reg) {
8d50e447 167 case WM9081_SOFTWARE_RESET:
f8faadb6 168 case WM9081_INTERRUPT_STATUS:
7cfa467b 169 return true;
86ed3669 170 default:
7cfa467b 171 return false;
86ed3669
MB		 172 }
173}
174
7cfa467b 175static bool wm9081_readable_register(struct device *dev, unsigned int reg)
86ed3669 176{
7cfa467b
MB		 177 switch (reg) {
178 case WM9081_SOFTWARE_RESET:
179 case WM9081_ANALOGUE_LINEOUT:
180 case WM9081_ANALOGUE_SPEAKER_PGA:
181 case WM9081_VMID_CONTROL:
182 case WM9081_BIAS_CONTROL_1:
183 case WM9081_ANALOGUE_MIXER:
184 case WM9081_ANTI_POP_CONTROL:
185 case WM9081_ANALOGUE_SPEAKER_1:
186 case WM9081_ANALOGUE_SPEAKER_2:
187 case WM9081_POWER_MANAGEMENT:
188 case WM9081_CLOCK_CONTROL_1:
189 case WM9081_CLOCK_CONTROL_2:
190 case WM9081_CLOCK_CONTROL_3:
191 case WM9081_FLL_CONTROL_1:
192 case WM9081_FLL_CONTROL_2:
193 case WM9081_FLL_CONTROL_3:
194 case WM9081_FLL_CONTROL_4:
195 case WM9081_FLL_CONTROL_5:
196 case WM9081_AUDIO_INTERFACE_1:
197 case WM9081_AUDIO_INTERFACE_2:
198 case WM9081_AUDIO_INTERFACE_3:
199 case WM9081_AUDIO_INTERFACE_4:
200 case WM9081_INTERRUPT_STATUS:
201 case WM9081_INTERRUPT_STATUS_MASK:
202 case WM9081_INTERRUPT_POLARITY:
203 case WM9081_INTERRUPT_CONTROL:
204 case WM9081_DAC_DIGITAL_1:
205 case WM9081_DAC_DIGITAL_2:
206 case WM9081_DRC_1:
207 case WM9081_DRC_2:
208 case WM9081_DRC_3:
209 case WM9081_DRC_4:
210 case WM9081_WRITE_SEQUENCER_1:
211 case WM9081_WRITE_SEQUENCER_2:
212 case WM9081_MW_SLAVE_1:
213 case WM9081_EQ_1:
214 case WM9081_EQ_2:
215 case WM9081_EQ_3:
216 case WM9081_EQ_4:
217 case WM9081_EQ_5:
218 case WM9081_EQ_6:
219 case WM9081_EQ_7:
220 case WM9081_EQ_8:
221 case WM9081_EQ_9:
222 case WM9081_EQ_10:
223 case WM9081_EQ_11:
224 case WM9081_EQ_12:
225 case WM9081_EQ_13:
226 case WM9081_EQ_14:
227 case WM9081_EQ_15:
228 case WM9081_EQ_16:
229 case WM9081_EQ_17:
230 case WM9081_EQ_18:
231 case WM9081_EQ_19:
232 case WM9081_EQ_20:
233 return true;
234 default:
235 return false;
236 }
237}
238
239static int wm9081_reset(struct regmap *map)
240{
241 return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
86ed3669
MB		 242}
243
244static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
245static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
246static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
247static unsigned int drc_max_tlv[] = {
248 TLV_DB_RANGE_HEAD(4),
249 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
250 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
251 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
252 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
253};
254static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
255static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
256
257static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
258
259static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
260static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
261static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
262
263static const char *drc_high_text[] = {
264 "1",
265 "1/2",
266 "1/4",
267 "1/8",
268 "1/16",
269 "0",
270};
271
272static const struct soc_enum drc_high =
273 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
274
275static const char *drc_low_text[] = {
276 "1",
277 "1/2",
278 "1/4",
279 "1/8",
280 "0",
281};
282
283static const struct soc_enum drc_low =
284 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
285
286static const char *drc_atk_text[] = {
287 "181us",
288 "181us",
289 "363us",
290 "726us",
291 "1.45ms",
292 "2.9ms",
293 "5.8ms",
294 "11.6ms",
295 "23.2ms",
296 "46.4ms",
297 "92.8ms",
298 "185.6ms",
299};
300
301static const struct soc_enum drc_atk =
302 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
303
304static const char *drc_dcy_text[] = {
305 "186ms",
306 "372ms",
307 "743ms",
308 "1.49s",
309 "2.97s",
310 "5.94s",
311 "11.89s",
312 "23.78s",
313 "47.56s",
314};
315
316static const struct soc_enum drc_dcy =
317 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
318
319static const char *drc_qr_dcy_text[] = {
320 "0.725ms",
321 "1.45ms",
322 "5.8ms",
323};
324
325static const struct soc_enum drc_qr_dcy =
326 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
327
328static const char *dac_deemph_text[] = {
329 "None",
330 "32kHz",
331 "44.1kHz",
332 "48kHz",
333};
334
335static const struct soc_enum dac_deemph =
336 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
337
338static const char *speaker_mode_text[] = {
339 "Class D",
340 "Class AB",
341};
342
343static const struct soc_enum speaker_mode =
344 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
345
346static int speaker_mode_get(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348{
349 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
350 unsigned int reg;
351
8d50e447 352 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 353 if (reg & WM9081_SPK_MODE)
354 ucontrol->value.integer.value[0] = 1;
355 else
356 ucontrol->value.integer.value[0] = 0;
357
358 return 0;
359}
360
361/*
362 * Stop any attempts to change speaker mode while the speaker is enabled.
363 *
25985edc 364 * We also have some special anti-pop controls dependent on speaker
86ed3669
MB		 365 * mode which must be changed along with the mode.
366 */
367static int speaker_mode_put(struct snd_kcontrol *kcontrol,
368 struct snd_ctl_elem_value *ucontrol)
369{
370 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 371 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
372 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 373
374 /* Are we changing anything? */
375 if (ucontrol->value.integer.value[0] ==
376 ((reg2 & WM9081_SPK_MODE) != 0))
377 return 0;
378
379 /* Don't try to change modes while enabled */
380 if (reg_pwr & WM9081_SPK_ENA)
381 return -EINVAL;
382
383 if (ucontrol->value.integer.value[0]) {
384 /* Class AB */
385 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
386 reg2 |= WM9081_SPK_MODE;
387 } else {
388 /* Class D */
389 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
390 reg2 &= ~WM9081_SPK_MODE;
391 }
392
8d50e447 393 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 394
395 return 0;
396}
397
398static const struct snd_kcontrol_new wm9081_snd_controls[] = {
399SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
400SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
401
402SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
403
404SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
405SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
406SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
407
408SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
409SOC_ENUM("DRC High Slope", drc_high),
410SOC_ENUM("DRC Low Slope", drc_low),
411SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
412SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
413SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
414SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
415SOC_ENUM("DRC Attack", drc_atk),
416SOC_ENUM("DRC Decay", drc_dcy),
417SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
418SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
419SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
420SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
421
422SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
423
424SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
425SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
426SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
427SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
428SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
429 out_tlv),
430SOC_ENUM("DAC Deemphasis", dac_deemph),
431SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
432};
433
434static const struct snd_kcontrol_new wm9081_eq_controls[] = {
435SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
436SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
437SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
438SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
439SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
440};
441
442static const struct snd_kcontrol_new mixer[] = {
443SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
444SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
445SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
446};
447
86ed3669
MB		 448struct _fll_div {
449 u16 fll_fratio;
450 u16 fll_outdiv;
451 u16 fll_clk_ref_div;
452 u16 n;
453 u16 k;
454};
455
456/* The size in bits of the FLL divide multiplied by 10
457 * to allow rounding later */
458#define FIXED_FLL_SIZE ((1 << 16) * 10)
459
460static struct {
461 unsigned int min;
462 unsigned int max;
463 u16 fll_fratio;
464 int ratio;
465} fll_fratios[] = {
466 { 0, 64000, 4, 16 },
467 { 64000, 128000, 3, 8 },
468 { 128000, 256000, 2, 4 },
469 { 256000, 1000000, 1, 2 },
470 { 1000000, 13500000, 0, 1 },
471};
472
473static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
474 unsigned int Fout)
475{
476 u64 Kpart;
477 unsigned int K, Ndiv, Nmod, target;
478 unsigned int div;
479 int i;
480
481 /* Fref must be <=13.5MHz */
482 div = 1;
483 while ((Fref / div) > 13500000) {
484 div *= 2;
485
486 if (div > 8) {
487 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
488 Fref);
489 return -EINVAL;
490 }
491 }
492 fll_div->fll_clk_ref_div = div / 2;
493
494 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
495
496 /* Apply the division for our remaining calculations */
497 Fref /= div;
498
499 /* Fvco should be 90-100MHz; don't check the upper bound */
500 div = 0;
501 target = Fout * 2;
502 while (target < 90000000) {
503 div++;
504 target *= 2;
505 if (div > 7) {
506 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
507 Fout);
508 return -EINVAL;
509 }
510 }
511 fll_div->fll_outdiv = div;
512
513 pr_debug("Fvco=%dHz\n", target);
514
25985edc 515 /* Find an appropriate FLL_FRATIO and factor it out of the target */
86ed3669
MB		 516 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
517 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
518 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
519 target /= fll_fratios[i].ratio;
520 break;
521 }
522 }
523 if (i == ARRAY_SIZE(fll_fratios)) {
524 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
525 return -EINVAL;
526 }
527
528 /* Now, calculate N.K */
529 Ndiv = target / Fref;
530
531 fll_div->n = Ndiv;
532 Nmod = target % Fref;
533 pr_debug("Nmod=%d\n", Nmod);
534
535 /* Calculate fractional part - scale up so we can round. */
536 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
537
538 do_div(Kpart, Fref);
539
540 K = Kpart & 0xFFFFFFFF;
541
542 if ((K % 10) >= 5)
543 K += 5;
544
545 /* Move down to proper range now rounding is done */
546 fll_div->k = K / 10;
547
548 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
549 fll_div->n, fll_div->k,
550 fll_div->fll_fratio, fll_div->fll_outdiv,
551 fll_div->fll_clk_ref_div);
552
553 return 0;
554}
555
556static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
557 unsigned int Fref, unsigned int Fout)
558{
b2c812e2 559 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 560 u16 reg1, reg4, reg5;
561 struct _fll_div fll_div;
562 int ret;
563 int clk_sys_reg;
564
565 /* Any change? */
566 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
567 return 0;
568
569 /* Disable the FLL */
570 if (Fout == 0) {
571 dev_dbg(codec->dev, "FLL disabled\n");
572 wm9081->fll_fref = 0;
573 wm9081->fll_fout = 0;
574
575 return 0;
576 }
577
578 ret = fll_factors(&fll_div, Fref, Fout);
579 if (ret != 0)
580 return ret;
581
8d50e447 582 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 583 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
584
585 switch (fll_id) {
586 case WM9081_SYSCLK_FLL_MCLK:
587 reg5 |= 0x1;
588 break;
589
590 default:
591 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
592 return -EINVAL;
593 }
594
595 /* Disable CLK_SYS while we reconfigure */
8d50e447 596 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 597 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 598 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 599 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
600
601 /* Any FLL configuration change requires that the FLL be
602 * disabled first. */
8d50e447 603 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 604 reg1 &= ~WM9081_FLL_ENA;
8d50e447 605 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 606
607 /* Apply the configuration */
608 if (fll_div.k)
609 reg1 |= WM9081_FLL_FRAC_MASK;
610 else
611 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 612 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 613
8d50e447 614 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 615 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
616 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 617 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 618
8d50e447 619 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 620 reg4 &= ~WM9081_FLL_N_MASK;
621 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 622 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 623
624 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
625 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 626 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669 627
249c5156
MB		 628 /* Set gain to the recommended value */
629 snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
630 WM9081_FLL_GAIN_MASK, 0);
631
86ed3669 632 /* Enable the FLL */
8d50e447 633 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 634
635 /* Then bring CLK_SYS up again if it was disabled */
636 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 637 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 638
639 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
640
641 wm9081->fll_fref = Fref;
642 wm9081->fll_fout = Fout;
643
644 return 0;
645}
646
647static int configure_clock(struct snd_soc_codec *codec)
648{
b2c812e2 649 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 650 int new_sysclk, i, target;
651 unsigned int reg;
652 int ret = 0;
653 int mclkdiv = 0;
654 int fll = 0;
655
656 switch (wm9081->sysclk_source) {
657 case WM9081_SYSCLK_MCLK:
658 if (wm9081->mclk_rate > 12225000) {
659 mclkdiv = 1;
660 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
661 } else {
662 wm9081->sysclk_rate = wm9081->mclk_rate;
663 }
664 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
665 break;
666
667 case WM9081_SYSCLK_FLL_MCLK:
668 /* If we have a sample rate calculate a CLK_SYS that
669 * gives us a suitable DAC configuration, plus BCLK.
670 * Ideally we would check to see if we can clock
671 * directly from MCLK and only use the FLL if this is
672 * not the case, though care must be taken with free
673 * running mode.
674 */
675 if (wm9081->master && wm9081->bclk) {
676 /* Make sure we can generate CLK_SYS and BCLK
677 * and that we've got 3MHz for optimal
678 * performance. */
679 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
680 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 681 new_sysclk = target;
86ed3669
MB		 682 if (target >= wm9081->bclk &&
683 target > 3000000)
0154724d 684 break;
86ed3669 685 }
4b75e947
MB		 686
687 if (i == ARRAY_SIZE(clk_sys_rates))
688 return -EINVAL;
689
86ed3669
MB		 690 } else if (wm9081->fs) {
691 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
692 new_sysclk = clk_sys_rates[i].ratio
693 * wm9081->fs;
694 if (new_sysclk > 3000000)
695 break;
696 }
4b75e947
MB		 697
698 if (i == ARRAY_SIZE(clk_sys_rates))
699 return -EINVAL;
700
86ed3669
MB		 701 } else {
702 new_sysclk = 12288000;
703 }
704
705 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
706 wm9081->mclk_rate, new_sysclk);
707 if (ret == 0) {
708 wm9081->sysclk_rate = new_sysclk;
709
710 /* Switch SYSCLK over to FLL */
711 fll = 1;
712 } else {
713 wm9081->sysclk_rate = wm9081->mclk_rate;
714 }
715 break;
716
717 default:
718 return -EINVAL;
719 }
720
8d50e447 721 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 722 if (mclkdiv)
723 reg |= WM9081_MCLKDIV2;
724 else
725 reg &= ~WM9081_MCLKDIV2;
8d50e447 726 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 727
8d50e447 728 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 729 if (fll)
730 reg |= WM9081_CLK_SRC_SEL;
731 else
732 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 733 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 734
735 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
736
737 return ret;
738}
739
740static int clk_sys_event(struct snd_soc_dapm_widget *w,
741 struct snd_kcontrol *kcontrol, int event)
742{
743 struct snd_soc_codec *codec = w->codec;
b2c812e2 744 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 745
746 /* This should be done on init() for bypass paths */
747 switch (wm9081->sysclk_source) {
748 case WM9081_SYSCLK_MCLK:
749 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
750 break;
751 case WM9081_SYSCLK_FLL_MCLK:
752 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
753 wm9081->mclk_rate);
754 break;
755 default:
756 dev_err(codec->dev, "System clock not configured\n");
757 return -EINVAL;
758 }
759
760 switch (event) {
761 case SND_SOC_DAPM_PRE_PMU:
762 configure_clock(codec);
763 break;
764
765 case SND_SOC_DAPM_POST_PMD:
766 /* Disable the FLL if it's running */
767 wm9081_set_fll(codec, 0, 0, 0);
768 break;
769 }
770
771 return 0;
772}
773
774static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
775SND_SOC_DAPM_INPUT("IN1"),
776SND_SOC_DAPM_INPUT("IN2"),
777
778SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
779
780SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
781 mixer, ARRAY_SIZE(mixer)),
782
783SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
784
378a90f4 785SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
4e8e78e3 786SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
86ed3669
MB		 787
788SND_SOC_DAPM_OUTPUT("LINEOUT"),
789SND_SOC_DAPM_OUTPUT("SPKN"),
790SND_SOC_DAPM_OUTPUT("SPKP"),
791
792SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
793 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
794SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
795SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
a04e0c86 796SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
86ed3669
MB		 797};
798
799
149c7b44 800static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
86ed3669
MB		 801 { "DAC", NULL, "CLK_SYS" },
802 { "DAC", NULL, "CLK_DSP" },
803
804 { "Mixer", "IN1 Switch", "IN1" },
805 { "Mixer", "IN2 Switch", "IN2" },
806 { "Mixer", "Playback Switch", "DAC" },
807
808 { "LINEOUT PGA", NULL, "Mixer" },
809 { "LINEOUT PGA", NULL, "TOCLK" },
810 { "LINEOUT PGA", NULL, "CLK_SYS" },
811
812 { "LINEOUT", NULL, "LINEOUT PGA" },
813
814 { "Speaker PGA", NULL, "Mixer" },
815 { "Speaker PGA", NULL, "TOCLK" },
816 { "Speaker PGA", NULL, "CLK_SYS" },
817
378a90f4 818 { "Speaker", NULL, "Speaker PGA" },
a04e0c86 819 { "Speaker", NULL, "TSENSE" },
378a90f4
MB		 820
821 { "SPKN", NULL, "Speaker" },
822 { "SPKP", NULL, "Speaker" },
86ed3669
MB		 823};
824
825static int wm9081_set_bias_level(struct snd_soc_codec *codec,
826 enum snd_soc_bias_level level)
827{
86ed3669
MB		 828 switch (level) {
829 case SND_SOC_BIAS_ON:
830 break;
831
832 case SND_SOC_BIAS_PREPARE:
833 /* VMID=2*40k */
b4027358
AL		 834 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
835 WM9081_VMID_SEL_MASK, 0x2);
86ed3669
MB		 836
837 /* Normal bias current */
b4027358
AL		 838 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
839 WM9081_STBY_BIAS_ENA, 0);
86ed3669
MB		 840 break;
841
842 case SND_SOC_BIAS_STANDBY:
843 /* Initial cold start */
ce6120cc 844 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
86ed3669 845 /* Disable LINEOUT discharge */
b4027358
AL		 846 snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
847 WM9081_LINEOUT_DISCH, 0);
86ed3669
MB		 848
849 /* Select startup bias source */
b4027358
AL		 850 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
851 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
852 WM9081_BIAS_SRC | WM9081_BIAS_ENA);
86ed3669
MB		 853
854 /* VMID 2*4k; Soft VMID ramp enable */
b4027358
AL		 855 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
856 WM9081_VMID_RAMP |
857 WM9081_VMID_SEL_MASK,
858 WM9081_VMID_RAMP | 0x6);
86ed3669
MB		 859
860 mdelay(100);
861
862 /* Normal bias enable & soft start off */
b4027358
AL		 863 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
864 WM9081_VMID_RAMP, 0);
86ed3669
MB		 865
866 /* Standard bias source */
b4027358
AL		 867 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
868 WM9081_BIAS_SRC, 0);
86ed3669
MB		 869 }
870
871 /* VMID 2*240k */
b4027358
AL		 872 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
873 WM9081_VMID_SEL_MASK, 0x04);
86ed3669
MB		 874
875 /* Standby bias current on */
b4027358
AL		 876 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
877 WM9081_STBY_BIAS_ENA,
878 WM9081_STBY_BIAS_ENA);
86ed3669
MB		 879 break;
880
881 case SND_SOC_BIAS_OFF:
adf46362 882 /* Startup bias source and disable bias */
b4027358
AL		 883 snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
884 WM9081_BIAS_SRC | WM9081_BIAS_ENA,
885 WM9081_BIAS_SRC);
86ed3669 886
adf46362 887 /* Disable VMID with soft ramping */
b4027358
AL		 888 snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
889 WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
890 WM9081_VMID_RAMP);
86ed3669
MB		 891
892 /* Actively discharge LINEOUT */
b4027358
AL		 893 snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
894 WM9081_LINEOUT_DISCH,
895 WM9081_LINEOUT_DISCH);
86ed3669
MB		 896 break;
897 }
898
ce6120cc 899 codec->dapm.bias_level = level;
86ed3669
MB		 900
901 return 0;
902}
903
904static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
905 unsigned int fmt)
906{
907 struct snd_soc_codec *codec = dai->codec;
b2c812e2 908 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 909 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 910
911 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
912 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
913
914 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
915 case SND_SOC_DAIFMT_CBS_CFS:
916 wm9081->master = 0;
917 break;
918 case SND_SOC_DAIFMT_CBS_CFM:
919 aif2 |= WM9081_LRCLK_DIR;
920 wm9081->master = 1;
921 break;
922 case SND_SOC_DAIFMT_CBM_CFS:
923 aif2 |= WM9081_BCLK_DIR;
924 wm9081->master = 1;
925 break;
926 case SND_SOC_DAIFMT_CBM_CFM:
927 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
928 wm9081->master = 1;
929 break;
930 default:
931 return -EINVAL;
932 }
933
934 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
935 case SND_SOC_DAIFMT_DSP_B:
936 aif2 |= WM9081_AIF_LRCLK_INV;
937 case SND_SOC_DAIFMT_DSP_A:
938 aif2 |= 0x3;
939 break;
940 case SND_SOC_DAIFMT_I2S:
941 aif2 |= 0x2;
942 break;
943 case SND_SOC_DAIFMT_RIGHT_J:
944 break;
945 case SND_SOC_DAIFMT_LEFT_J:
946 aif2 |= 0x1;
947 break;
948 default:
949 return -EINVAL;
950 }
951
952 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
953 case SND_SOC_DAIFMT_DSP_A:
954 case SND_SOC_DAIFMT_DSP_B:
955 /* frame inversion not valid for DSP modes */
956 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
957 case SND_SOC_DAIFMT_NB_NF:
958 break;
959 case SND_SOC_DAIFMT_IB_NF:
960 aif2 |= WM9081_AIF_BCLK_INV;
961 break;
962 default:
963 return -EINVAL;
964 }
965 break;
966
967 case SND_SOC_DAIFMT_I2S:
968 case SND_SOC_DAIFMT_RIGHT_J:
969 case SND_SOC_DAIFMT_LEFT_J:
970 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
971 case SND_SOC_DAIFMT_NB_NF:
972 break;
973 case SND_SOC_DAIFMT_IB_IF:
974 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
975 break;
976 case SND_SOC_DAIFMT_IB_NF:
977 aif2 |= WM9081_AIF_BCLK_INV;
978 break;
979 case SND_SOC_DAIFMT_NB_IF:
980 aif2 |= WM9081_AIF_LRCLK_INV;
981 break;
982 default:
983 return -EINVAL;
984 }
985 break;
986 default:
987 return -EINVAL;
988 }
989
8d50e447 990 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 991
992 return 0;
993}
994
995static int wm9081_hw_params(struct snd_pcm_substream *substream,
996 struct snd_pcm_hw_params *params,
997 struct snd_soc_dai *dai)
998{
999 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1000 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1001 int ret, i, best, best_val, cur_val;
1002 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1003
8d50e447 1004 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 1005 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1006
8d50e447 1007 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 1008
8d50e447 1009 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 1010 aif2 &= ~WM9081_AIF_WL_MASK;
1011
8d50e447 1012 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 1013 aif3 &= ~WM9081_BCLK_DIV_MASK;
1014
8d50e447 1015 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 1016 aif4 &= ~WM9081_LRCLK_RATE_MASK;
1017
86ed3669 1018 wm9081->fs = params_rate(params);
86ed3669 1019
e0026bea
MB		 1020 if (wm9081->tdm_width) {
1021 /* If TDM is set up then that fixes our BCLK. */
86ed3669
MB		 1022 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1023 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
e0026bea
MB		 1024
1025 wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1026 } else {
1027 /* Otherwise work out a BCLK from the sample size */
1028 wm9081->bclk = 2 * wm9081->fs;
1029
1030 switch (params_format(params)) {
1031 case SNDRV_PCM_FORMAT_S16_LE:
1032 wm9081->bclk *= 16;
1033 break;
1034 case SNDRV_PCM_FORMAT_S20_3LE:
1035 wm9081->bclk *= 20;
1036 aif2 |= 0x4;
1037 break;
1038 case SNDRV_PCM_FORMAT_S24_LE:
1039 wm9081->bclk *= 24;
1040 aif2 |= 0x8;
1041 break;
1042 case SNDRV_PCM_FORMAT_S32_LE:
1043 wm9081->bclk *= 32;
1044 aif2 |= 0xc;
1045 break;
1046 default:
1047 return -EINVAL;
1048 }
86ed3669
MB		 1049 }
1050
1051 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1052
1053 ret = configure_clock(codec);
1054 if (ret != 0)
1055 return ret;
1056
1057 /* Select nearest CLK_SYS_RATE */
1058 best = 0;
1059 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1060 - wm9081->fs);
1061 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1062 cur_val = abs((wm9081->sysclk_rate /
a419aef8 1063 clk_sys_rates[i].ratio) - wm9081->fs);
86ed3669
MB		 1064 if (cur_val < best_val) {
1065 best = i;
1066 best_val = cur_val;
1067 }
1068 }
1069 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1070 clk_sys_rates[best].ratio);
1071 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1072 << WM9081_CLK_SYS_RATE_SHIFT);
1073
1074 /* SAMPLE_RATE */
1075 best = 0;
1076 best_val = abs(wm9081->fs - sample_rates[0].rate);
1077 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1078 /* Closest match */
1079 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1080 if (cur_val < best_val) {
1081 best = i;
1082 best_val = cur_val;
1083 }
1084 }
1085 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1086 sample_rates[best].rate);
0154724d
MB		 1087 clk_ctrl2 |= (sample_rates[best].sample_rate
1088 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1089
1090 /* BCLK_DIV */
1091 best = 0;
1092 best_val = INT_MAX;
1093 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1094 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1095 - wm9081->bclk;
1096 if (cur_val < 0) /* Table is sorted */
1097 break;
1098 if (cur_val < best_val) {
1099 best = i;
1100 best_val = cur_val;
1101 }
1102 }
1103 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1104 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1105 bclk_divs[best].div, wm9081->bclk);
1106 aif3 |= bclk_divs[best].bclk_div;
1107
1108 /* LRCLK is a simple fraction of BCLK */
1109 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1110 aif4 |= wm9081->bclk / wm9081->fs;
1111
1112 /* Apply a ReTune Mobile configuration if it's in use */
4a5f7bda
MB		 1113 if (wm9081->pdata.num_retune_configs) {
1114 struct wm9081_pdata *pdata = &wm9081->pdata;
86ed3669
MB		 1115 struct wm9081_retune_mobile_setting *s;
1116 int eq1;
1117
1118 best = 0;
4a5f7bda
MB		 1119 best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1120 for (i = 0; i < pdata->num_retune_configs; i++) {
1121 cur_val = abs(pdata->retune_configs[i].rate -
1122 wm9081->fs);
86ed3669
MB		 1123 if (cur_val < best_val) {
1124 best_val = cur_val;
1125 best = i;
1126 }
1127 }
4a5f7bda 1128 s = &pdata->retune_configs[best];
86ed3669
MB		 1129
1130 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1131 s->name, s->rate);
1132
1133 /* If the EQ is enabled then disable it while we write out */
8d50e447 1134 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1135 if (eq1 & WM9081_EQ_ENA)
8d50e447 1136 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1137
1138 /* Write out the other values */
1139 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1140 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1141
1142 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1143 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1144 }
1145
8d50e447
MB		 1146 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1147 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1148 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1149 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1150
1151 return 0;
1152}
1153
1154static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1155{
1156 struct snd_soc_codec *codec = codec_dai->codec;
1157 unsigned int reg;
1158
8d50e447 1159 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1160
1161 if (mute)
1162 reg |= WM9081_DAC_MUTE;
1163 else
1164 reg &= ~WM9081_DAC_MUTE;
1165
8d50e447 1166 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1167
1168 return 0;
1169}
1170
da1c6ea6
MB		 1171static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1172 int source, unsigned int freq, int dir)
86ed3669 1173{
b2c812e2 1174 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669
MB		 1175
1176 switch (clk_id) {
1177 case WM9081_SYSCLK_MCLK:
1178 case WM9081_SYSCLK_FLL_MCLK:
1179 wm9081->sysclk_source = clk_id;
1180 wm9081->mclk_rate = freq;
1181 break;
1182
1183 default:
1184 return -EINVAL;
1185 }
1186
1187 return 0;
1188}
1189
1190static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1191 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1192{
1193 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1194 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
8d50e447 1195 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1196
1197 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1198
e0026bea 1199 if (slots < 0 || slots > 4)
86ed3669
MB		 1200 return -EINVAL;
1201
e0026bea
MB		 1202 wm9081->tdm_width = slot_width;
1203
1204 if (slots == 0)
1205 slots = 1;
1206
86ed3669
MB		 1207 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1208
a5479e38 1209 switch (rx_mask) {
86ed3669
MB		 1210 case 1:
1211 break;
1212 case 2:
1213 aif1 |= 0x10;
1214 break;
1215 case 4:
1216 aif1 |= 0x20;
1217 break;
1218 case 8:
1219 aif1 |= 0x30;
1220 break;
1221 default:
1222 return -EINVAL;
1223 }
1224
8d50e447 1225 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1226
1227 return 0;
1228}
1229
1230#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1231
1232#define WM9081_FORMATS \
1233 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1234 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1235
85e7652d 1236static const struct snd_soc_dai_ops wm9081_dai_ops = {
86ed3669 1237 .hw_params = wm9081_hw_params,
86ed3669
MB		 1238 .set_fmt = wm9081_set_dai_fmt,
1239 .digital_mute = wm9081_digital_mute,
1240 .set_tdm_slot = wm9081_set_tdm_slot,
1241};
1242
1243/* We report two channels because the CODEC processes a stereo signal, even
1244 * though it is only capable of handling a mono output.
1245 */
f0fba2ad
LG		 1246static struct snd_soc_dai_driver wm9081_dai = {
1247 .name = "wm9081-hifi",
86ed3669
MB		 1248 .playback = {
1249 .stream_name = "HiFi Playback",
1250 .channels_min = 1,
1251 .channels_max = 2,
1252 .rates = WM9081_RATES,
1253 .formats = WM9081_FORMATS,
1254 },
1255 .ops = &wm9081_dai_ops,
1256};
86ed3669 1257
f0fba2ad 1258static int wm9081_probe(struct snd_soc_codec *codec)
86ed3669 1259{
f0fba2ad
LG		 1260 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1261 int ret;
1262 u16 reg;
86ed3669 1263
7cfa467b
MB		 1264 codec->control_data = wm9081->regmap;
1265
1266 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
f0fba2ad
LG		 1267 if (ret != 0) {
1268 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1269 return ret;
86ed3669
MB		 1270 }
1271
4a5f7bda
MB		 1272 reg = 0;
1273 if (wm9081->pdata.irq_high)
1274 reg |= WM9081_IRQ_POL;
1275 if (!wm9081->pdata.irq_cmos)
1276 reg |= WM9081_IRQ_OP_CTRL;
1277 snd_soc_update_bits(codec, WM9081_INTERRUPT_CONTROL,
1278 WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1279
f0fba2ad
LG		 1280 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1281
1282 /* Enable zero cross by default */
b4027358
AL		 1283 snd_soc_update_bits(codec, WM9081_ANALOGUE_LINEOUT,
1284 WM9081_LINEOUTZC, WM9081_LINEOUTZC);
1285 snd_soc_update_bits(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1286 WM9081_SPKPGAZC, WM9081_SPKPGAZC);
f0fba2ad 1287
4a5f7bda 1288 if (!wm9081->pdata.num_retune_configs) {
86ed3669
MB		 1289 dev_dbg(codec->dev,
1290 "No ReTune Mobile data, using normal EQ\n");
1291 snd_soc_add_controls(codec, wm9081_eq_controls,
1292 ARRAY_SIZE(wm9081_eq_controls));
1293 }
1294
86ed3669 1295 return ret;
86ed3669
MB		 1296}
1297
f0fba2ad 1298static int wm9081_remove(struct snd_soc_codec *codec)
86ed3669 1299{
f0fba2ad 1300 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
86ed3669
MB		 1301 return 0;
1302}
1303
1304#ifdef CONFIG_PM
84b315ee 1305static int wm9081_suspend(struct snd_soc_codec *codec)
86ed3669 1306{
86ed3669
MB		 1307 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1308
1309 return 0;
1310}
1311
f0fba2ad 1312static int wm9081_resume(struct snd_soc_codec *codec)
86ed3669 1313{
7cfa467b 1314 struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
86ed3669 1315
7cfa467b 1316 regcache_sync(wm9081->regmap);
86ed3669
MB		 1317
1318 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1319
1320 return 0;
1321}
1322#else
1323#define wm9081_suspend NULL
1324#define wm9081_resume NULL
1325#endif
1326
f0fba2ad 1327static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
86ed3669
MB		 1328 .probe = wm9081_probe,
1329 .remove = wm9081_remove,
1330 .suspend = wm9081_suspend,
1331 .resume = wm9081_resume,
63d24b79
MB		 1332
1333 .set_sysclk = wm9081_set_sysclk,
f0fba2ad 1334 .set_bias_level = wm9081_set_bias_level,
63d24b79 1335
680fa1f8
MB		 1336 .controls = wm9081_snd_controls,
1337 .num_controls = ARRAY_SIZE(wm9081_snd_controls),
149c7b44
MB		 1338 .dapm_widgets = wm9081_dapm_widgets,
1339 .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1340 .dapm_routes = wm9081_audio_paths,
1341 .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
86ed3669 1342};
86ed3669 1343
7cfa467b
MB		 1344static const struct regmap_config wm9081_regmap = {
1345 .reg_bits = 8,
1346 .val_bits = 16,
1347
1348 .max_register = WM9081_MAX_REGISTER,
1349 .reg_defaults = wm9081_reg,
1350 .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1351 .volatile_reg = wm9081_volatile_register,
1352 .readable_reg = wm9081_readable_register,
1353 .cache_type = REGCACHE_RBTREE,
1354};
1355
f0fba2ad 1356#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1357static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1358 const struct i2c_device_id *id)
1359{
1360 struct wm9081_priv *wm9081;
7cfa467b 1361 unsigned int reg;
f0fba2ad 1362 int ret;
86ed3669 1363
897f7847
MB		 1364 wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
1365 GFP_KERNEL);
86ed3669
MB		 1366 if (wm9081 == NULL)
1367 return -ENOMEM;
1368
86ed3669 1369 i2c_set_clientdata(i2c, wm9081);
7cfa467b
MB		 1370
1371 wm9081->regmap = regmap_init_i2c(i2c, &wm9081_regmap);
1372 if (IS_ERR(wm9081->regmap)) {
1373 ret = PTR_ERR(wm9081->regmap);
1374 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1375 goto err;
1376 }
1377
1378 ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
1379 if (ret != 0) {
1380 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1381 goto err_regmap;
1382 }
1383 if (reg != 0x9081) {
1384 dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1385 ret = -EINVAL;
1386 goto err_regmap;
1387 }
1388
1389 ret = wm9081_reset(wm9081->regmap);
1390 if (ret < 0) {
1391 dev_err(&i2c->dev, "Failed to issue reset\n");
1392 goto err_regmap;
1393 }
86ed3669 1394
3ee845ac 1395 if (dev_get_platdata(&i2c->dev))
4a5f7bda
MB		 1396 memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1397 sizeof(wm9081->pdata));
3ee845ac 1398
f0fba2ad
LG		 1399 ret = snd_soc_register_codec(&i2c->dev,
1400 &soc_codec_dev_wm9081, &wm9081_dai, 1);
1401 if (ret < 0)
7cfa467b
MB		 1402 goto err_regmap;
1403
1404 return 0;
1405
1406err_regmap:
1407 regmap_exit(wm9081->regmap);
1408err:
7cfa467b 1409
f0fba2ad 1410 return ret;
86ed3669
MB		 1411}
1412
1413static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1414{
7cfa467b
MB		 1415 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1416
f0fba2ad 1417 snd_soc_unregister_codec(&client->dev);
7cfa467b 1418 regmap_exit(wm9081->regmap);
86ed3669
MB		 1419 return 0;
1420}
1421
1422static const struct i2c_device_id wm9081_i2c_id[] = {
1423 { "wm9081", 0 },
1424 { }
1425};
1426MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1427
1428static struct i2c_driver wm9081_i2c_driver = {
1429 .driver = {
2031c064 1430 .name = "wm9081",
86ed3669
MB		 1431 .owner = THIS_MODULE,
1432 },
1433 .probe = wm9081_i2c_probe,
1434 .remove = __devexit_p(wm9081_i2c_remove),
1435 .id_table = wm9081_i2c_id,
1436};
f0fba2ad 1437#endif
86ed3669
MB		 1438
1439static int __init wm9081_modinit(void)
1440{
f0fba2ad
LG		 1441 int ret = 0;
1442#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669
MB		 1443 ret = i2c_add_driver(&wm9081_i2c_driver);
1444 if (ret != 0) {
1445 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1446 ret);
1447 }
f0fba2ad 1448#endif
86ed3669
MB		 1449 return ret;
1450}
1451module_init(wm9081_modinit);
1452
1453static void __exit wm9081_exit(void)
1454{
f0fba2ad 1455#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
86ed3669 1456 i2c_del_driver(&wm9081_i2c_driver);
f0fba2ad 1457#endif
86ed3669
MB		 1458}
1459module_exit(wm9081_exit);
1460
1461
1462MODULE_DESCRIPTION("ASoC WM9081 driver");
1463MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1464MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.189477 seconds and 5 git commands to generate.