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Merge commit 'a5479e389e989acfeca9c32eeb0083d086202280' into for-2.6.32
[deliverable/linux.git] / sound / soc / codecs / wm9081.c
CommitLineData
86ed3669
MB		 1/*
2 * wm9081.c -- WM9081 ALSA SoC Audio driver
3 *
4 * Author: Mark Brown
5 *
6 * Copyright 2009 Wolfson Microelectronics plc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28
29#include <sound/wm9081.h>
30#include "wm9081.h"
31
32static u16 wm9081_reg_defaults[] = {
33 0x0000, /* R0 - Software Reset */
34 0x0000, /* R1 */
35 0x00B9, /* R2 - Analogue Lineout */
36 0x00B9, /* R3 - Analogue Speaker PGA */
37 0x0001, /* R4 - VMID Control */
38 0x0068, /* R5 - Bias Control 1 */
39 0x0000, /* R6 */
40 0x0000, /* R7 - Analogue Mixer */
41 0x0000, /* R8 - Anti Pop Control */
42 0x01DB, /* R9 - Analogue Speaker 1 */
43 0x0018, /* R10 - Analogue Speaker 2 */
44 0x0180, /* R11 - Power Management */
45 0x0000, /* R12 - Clock Control 1 */
46 0x0038, /* R13 - Clock Control 2 */
47 0x4000, /* R14 - Clock Control 3 */
48 0x0000, /* R15 */
49 0x0000, /* R16 - FLL Control 1 */
50 0x0200, /* R17 - FLL Control 2 */
51 0x0000, /* R18 - FLL Control 3 */
52 0x0204, /* R19 - FLL Control 4 */
53 0x0000, /* R20 - FLL Control 5 */
54 0x0000, /* R21 */
55 0x0000, /* R22 - Audio Interface 1 */
56 0x0002, /* R23 - Audio Interface 2 */
57 0x0008, /* R24 - Audio Interface 3 */
58 0x0022, /* R25 - Audio Interface 4 */
59 0x0000, /* R26 - Interrupt Status */
60 0x0006, /* R27 - Interrupt Status Mask */
61 0x0000, /* R28 - Interrupt Polarity */
62 0x0000, /* R29 - Interrupt Control */
63 0x00C0, /* R30 - DAC Digital 1 */
64 0x0008, /* R31 - DAC Digital 2 */
65 0x09AF, /* R32 - DRC 1 */
66 0x4201, /* R33 - DRC 2 */
67 0x0000, /* R34 - DRC 3 */
68 0x0000, /* R35 - DRC 4 */
69 0x0000, /* R36 */
70 0x0000, /* R37 */
71 0x0000, /* R38 - Write Sequencer 1 */
72 0x0000, /* R39 - Write Sequencer 2 */
73 0x0002, /* R40 - MW Slave 1 */
74 0x0000, /* R41 */
75 0x0000, /* R42 - EQ 1 */
76 0x0000, /* R43 - EQ 2 */
77 0x0FCA, /* R44 - EQ 3 */
78 0x0400, /* R45 - EQ 4 */
79 0x00B8, /* R46 - EQ 5 */
80 0x1EB5, /* R47 - EQ 6 */
81 0xF145, /* R48 - EQ 7 */
82 0x0B75, /* R49 - EQ 8 */
83 0x01C5, /* R50 - EQ 9 */
84 0x169E, /* R51 - EQ 10 */
85 0xF829, /* R52 - EQ 11 */
86 0x07AD, /* R53 - EQ 12 */
87 0x1103, /* R54 - EQ 13 */
88 0x1C58, /* R55 - EQ 14 */
89 0xF373, /* R56 - EQ 15 */
90 0x0A54, /* R57 - EQ 16 */
91 0x0558, /* R58 - EQ 17 */
92 0x0564, /* R59 - EQ 18 */
93 0x0559, /* R60 - EQ 19 */
94 0x4000, /* R61 - EQ 20 */
95};
96
97static struct {
98 int ratio;
99 int clk_sys_rate;
100} clk_sys_rates[] = {
101 { 64, 0 },
102 { 128, 1 },
103 { 192, 2 },
104 { 256, 3 },
105 { 384, 4 },
106 { 512, 5 },
107 { 768, 6 },
108 { 1024, 7 },
109 { 1408, 8 },
110 { 1536, 9 },
111};
112
113static struct {
114 int rate;
115 int sample_rate;
116} sample_rates[] = {
117 { 8000, 0 },
118 { 11025, 1 },
119 { 12000, 2 },
120 { 16000, 3 },
121 { 22050, 4 },
122 { 24000, 5 },
123 { 32000, 6 },
124 { 44100, 7 },
125 { 48000, 8 },
126 { 88200, 9 },
127 { 96000, 10 },
128};
129
130static struct {
131 int div; /* *10 due to .5s */
132 int bclk_div;
133} bclk_divs[] = {
134 { 10, 0 },
135 { 15, 1 },
136 { 20, 2 },
137 { 30, 3 },
138 { 40, 4 },
139 { 50, 5 },
140 { 55, 6 },
141 { 60, 7 },
142 { 80, 8 },
143 { 100, 9 },
144 { 110, 10 },
145 { 120, 11 },
146 { 160, 12 },
147 { 200, 13 },
148 { 220, 14 },
149 { 240, 15 },
150 { 250, 16 },
151 { 300, 17 },
152 { 320, 18 },
153 { 440, 19 },
154 { 480, 20 },
155};
156
157struct wm9081_priv {
158 struct snd_soc_codec codec;
159 u16 reg_cache[WM9081_MAX_REGISTER + 1];
160 int sysclk_source;
161 int mclk_rate;
162 int sysclk_rate;
163 int fs;
164 int bclk;
165 int master;
166 int fll_fref;
167 int fll_fout;
168 struct wm9081_retune_mobile_config *retune;
169};
170
8d50e447 171static int wm9081_volatile_register(unsigned int reg)
86ed3669
MB		 172{
173 switch (reg) {
8d50e447
MB		 174 case WM9081_SOFTWARE_RESET:
175 return 1;
86ed3669
MB		 176 default:
177 return 0;
178 }
179}
180
86ed3669
MB		 181static int wm9081_reset(struct snd_soc_codec *codec)
182{
8d50e447 183 return snd_soc_write(codec, WM9081_SOFTWARE_RESET, 0);
86ed3669
MB		 184}
185
186static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
187static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
188static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
189static unsigned int drc_max_tlv[] = {
190 TLV_DB_RANGE_HEAD(4),
191 0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
192 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
193 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
194 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
195};
196static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
197static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
198
199static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
200
201static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
202static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
203static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
204
205static const char *drc_high_text[] = {
206 "1",
207 "1/2",
208 "1/4",
209 "1/8",
210 "1/16",
211 "0",
212};
213
214static const struct soc_enum drc_high =
215 SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
216
217static const char *drc_low_text[] = {
218 "1",
219 "1/2",
220 "1/4",
221 "1/8",
222 "0",
223};
224
225static const struct soc_enum drc_low =
226 SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
227
228static const char *drc_atk_text[] = {
229 "181us",
230 "181us",
231 "363us",
232 "726us",
233 "1.45ms",
234 "2.9ms",
235 "5.8ms",
236 "11.6ms",
237 "23.2ms",
238 "46.4ms",
239 "92.8ms",
240 "185.6ms",
241};
242
243static const struct soc_enum drc_atk =
244 SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
245
246static const char *drc_dcy_text[] = {
247 "186ms",
248 "372ms",
249 "743ms",
250 "1.49s",
251 "2.97s",
252 "5.94s",
253 "11.89s",
254 "23.78s",
255 "47.56s",
256};
257
258static const struct soc_enum drc_dcy =
259 SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
260
261static const char *drc_qr_dcy_text[] = {
262 "0.725ms",
263 "1.45ms",
264 "5.8ms",
265};
266
267static const struct soc_enum drc_qr_dcy =
268 SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
269
270static const char *dac_deemph_text[] = {
271 "None",
272 "32kHz",
273 "44.1kHz",
274 "48kHz",
275};
276
277static const struct soc_enum dac_deemph =
278 SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
279
280static const char *speaker_mode_text[] = {
281 "Class D",
282 "Class AB",
283};
284
285static const struct soc_enum speaker_mode =
286 SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
287
288static int speaker_mode_get(struct snd_kcontrol *kcontrol,
289 struct snd_ctl_elem_value *ucontrol)
290{
291 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
292 unsigned int reg;
293
8d50e447 294 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 295 if (reg & WM9081_SPK_MODE)
296 ucontrol->value.integer.value[0] = 1;
297 else
298 ucontrol->value.integer.value[0] = 0;
299
300 return 0;
301}
302
303/*
304 * Stop any attempts to change speaker mode while the speaker is enabled.
305 *
306 * We also have some special anti-pop controls dependant on speaker
307 * mode which must be changed along with the mode.
308 */
309static int speaker_mode_put(struct snd_kcontrol *kcontrol,
310 struct snd_ctl_elem_value *ucontrol)
311{
312 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
8d50e447
MB		 313 unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
314 unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
86ed3669
MB		 315
316 /* Are we changing anything? */
317 if (ucontrol->value.integer.value[0] ==
318 ((reg2 & WM9081_SPK_MODE) != 0))
319 return 0;
320
321 /* Don't try to change modes while enabled */
322 if (reg_pwr & WM9081_SPK_ENA)
323 return -EINVAL;
324
325 if (ucontrol->value.integer.value[0]) {
326 /* Class AB */
327 reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
328 reg2 |= WM9081_SPK_MODE;
329 } else {
330 /* Class D */
331 reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
332 reg2 &= ~WM9081_SPK_MODE;
333 }
334
8d50e447 335 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
86ed3669
MB		 336
337 return 0;
338}
339
340static const struct snd_kcontrol_new wm9081_snd_controls[] = {
341SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
342SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
343
344SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
345
346SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
347SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
348SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
349
350SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
351SOC_ENUM("DRC High Slope", drc_high),
352SOC_ENUM("DRC Low Slope", drc_low),
353SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
354SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
355SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
356SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
357SOC_ENUM("DRC Attack", drc_atk),
358SOC_ENUM("DRC Decay", drc_dcy),
359SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
360SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
361SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
362SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
363
364SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
365
366SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
367SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
368SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
369SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
370SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
371 out_tlv),
372SOC_ENUM("DAC Deemphasis", dac_deemph),
373SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
374};
375
376static const struct snd_kcontrol_new wm9081_eq_controls[] = {
377SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
378SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
379SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
380SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
381SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
382};
383
384static const struct snd_kcontrol_new mixer[] = {
385SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
386SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
387SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
388};
389
390static int speaker_event(struct snd_soc_dapm_widget *w,
391 struct snd_kcontrol *kcontrol, int event)
392{
393 struct snd_soc_codec *codec = w->codec;
8d50e447 394 unsigned int reg = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
86ed3669
MB		 395
396 switch (event) {
397 case SND_SOC_DAPM_POST_PMU:
398 reg |= WM9081_SPK_ENA;
399 break;
400
401 case SND_SOC_DAPM_PRE_PMD:
402 reg &= ~WM9081_SPK_ENA;
403 break;
404 }
405
8d50e447 406 snd_soc_write(codec, WM9081_POWER_MANAGEMENT, reg);
86ed3669
MB		 407
408 return 0;
409}
410
411struct _fll_div {
412 u16 fll_fratio;
413 u16 fll_outdiv;
414 u16 fll_clk_ref_div;
415 u16 n;
416 u16 k;
417};
418
419/* The size in bits of the FLL divide multiplied by 10
420 * to allow rounding later */
421#define FIXED_FLL_SIZE ((1 << 16) * 10)
422
423static struct {
424 unsigned int min;
425 unsigned int max;
426 u16 fll_fratio;
427 int ratio;
428} fll_fratios[] = {
429 { 0, 64000, 4, 16 },
430 { 64000, 128000, 3, 8 },
431 { 128000, 256000, 2, 4 },
432 { 256000, 1000000, 1, 2 },
433 { 1000000, 13500000, 0, 1 },
434};
435
436static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
437 unsigned int Fout)
438{
439 u64 Kpart;
440 unsigned int K, Ndiv, Nmod, target;
441 unsigned int div;
442 int i;
443
444 /* Fref must be <=13.5MHz */
445 div = 1;
446 while ((Fref / div) > 13500000) {
447 div *= 2;
448
449 if (div > 8) {
450 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
451 Fref);
452 return -EINVAL;
453 }
454 }
455 fll_div->fll_clk_ref_div = div / 2;
456
457 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
458
459 /* Apply the division for our remaining calculations */
460 Fref /= div;
461
462 /* Fvco should be 90-100MHz; don't check the upper bound */
463 div = 0;
464 target = Fout * 2;
465 while (target < 90000000) {
466 div++;
467 target *= 2;
468 if (div > 7) {
469 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
470 Fout);
471 return -EINVAL;
472 }
473 }
474 fll_div->fll_outdiv = div;
475
476 pr_debug("Fvco=%dHz\n", target);
477
478 /* Find an appropraite FLL_FRATIO and factor it out of the target */
479 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
480 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
481 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
482 target /= fll_fratios[i].ratio;
483 break;
484 }
485 }
486 if (i == ARRAY_SIZE(fll_fratios)) {
487 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
488 return -EINVAL;
489 }
490
491 /* Now, calculate N.K */
492 Ndiv = target / Fref;
493
494 fll_div->n = Ndiv;
495 Nmod = target % Fref;
496 pr_debug("Nmod=%d\n", Nmod);
497
498 /* Calculate fractional part - scale up so we can round. */
499 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
500
501 do_div(Kpart, Fref);
502
503 K = Kpart & 0xFFFFFFFF;
504
505 if ((K % 10) >= 5)
506 K += 5;
507
508 /* Move down to proper range now rounding is done */
509 fll_div->k = K / 10;
510
511 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
512 fll_div->n, fll_div->k,
513 fll_div->fll_fratio, fll_div->fll_outdiv,
514 fll_div->fll_clk_ref_div);
515
516 return 0;
517}
518
519static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
520 unsigned int Fref, unsigned int Fout)
521{
522 struct wm9081_priv *wm9081 = codec->private_data;
523 u16 reg1, reg4, reg5;
524 struct _fll_div fll_div;
525 int ret;
526 int clk_sys_reg;
527
528 /* Any change? */
529 if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
530 return 0;
531
532 /* Disable the FLL */
533 if (Fout == 0) {
534 dev_dbg(codec->dev, "FLL disabled\n");
535 wm9081->fll_fref = 0;
536 wm9081->fll_fout = 0;
537
538 return 0;
539 }
540
541 ret = fll_factors(&fll_div, Fref, Fout);
542 if (ret != 0)
543 return ret;
544
8d50e447 545 reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
86ed3669
MB		 546 reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
547
548 switch (fll_id) {
549 case WM9081_SYSCLK_FLL_MCLK:
550 reg5 |= 0x1;
551 break;
552
553 default:
554 dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
555 return -EINVAL;
556 }
557
558 /* Disable CLK_SYS while we reconfigure */
8d50e447 559 clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669 560 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 561 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
86ed3669
MB		 562 clk_sys_reg & ~WM9081_CLK_SYS_ENA);
563
564 /* Any FLL configuration change requires that the FLL be
565 * disabled first. */
8d50e447 566 reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
86ed3669 567 reg1 &= ~WM9081_FLL_ENA;
8d50e447 568 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669
MB		 569
570 /* Apply the configuration */
571 if (fll_div.k)
572 reg1 |= WM9081_FLL_FRAC_MASK;
573 else
574 reg1 &= ~WM9081_FLL_FRAC_MASK;
8d50e447 575 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
86ed3669 576
8d50e447 577 snd_soc_write(codec, WM9081_FLL_CONTROL_2,
86ed3669
MB		 578 (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
579 (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
8d50e447 580 snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
86ed3669 581
8d50e447 582 reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
86ed3669
MB		 583 reg4 &= ~WM9081_FLL_N_MASK;
584 reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
8d50e447 585 snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
86ed3669
MB		 586
587 reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
588 reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
8d50e447 589 snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
86ed3669
MB		 590
591 /* Enable the FLL */
8d50e447 592 snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
86ed3669
MB		 593
594 /* Then bring CLK_SYS up again if it was disabled */
595 if (clk_sys_reg & WM9081_CLK_SYS_ENA)
8d50e447 596 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
86ed3669
MB		 597
598 dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
599
600 wm9081->fll_fref = Fref;
601 wm9081->fll_fout = Fout;
602
603 return 0;
604}
605
606static int configure_clock(struct snd_soc_codec *codec)
607{
608 struct wm9081_priv *wm9081 = codec->private_data;
609 int new_sysclk, i, target;
610 unsigned int reg;
611 int ret = 0;
612 int mclkdiv = 0;
613 int fll = 0;
614
615 switch (wm9081->sysclk_source) {
616 case WM9081_SYSCLK_MCLK:
617 if (wm9081->mclk_rate > 12225000) {
618 mclkdiv = 1;
619 wm9081->sysclk_rate = wm9081->mclk_rate / 2;
620 } else {
621 wm9081->sysclk_rate = wm9081->mclk_rate;
622 }
623 wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
624 break;
625
626 case WM9081_SYSCLK_FLL_MCLK:
627 /* If we have a sample rate calculate a CLK_SYS that
628 * gives us a suitable DAC configuration, plus BCLK.
629 * Ideally we would check to see if we can clock
630 * directly from MCLK and only use the FLL if this is
631 * not the case, though care must be taken with free
632 * running mode.
633 */
634 if (wm9081->master && wm9081->bclk) {
635 /* Make sure we can generate CLK_SYS and BCLK
636 * and that we've got 3MHz for optimal
637 * performance. */
638 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
639 target = wm9081->fs * clk_sys_rates[i].ratio;
0154724d 640 new_sysclk = target;
86ed3669
MB		 641 if (target >= wm9081->bclk &&
642 target > 3000000)
0154724d 643 break;
86ed3669 644 }
4b75e947
MB		 645
646 if (i == ARRAY_SIZE(clk_sys_rates))
647 return -EINVAL;
648
86ed3669
MB		 649 } else if (wm9081->fs) {
650 for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
651 new_sysclk = clk_sys_rates[i].ratio
652 * wm9081->fs;
653 if (new_sysclk > 3000000)
654 break;
655 }
4b75e947
MB		 656
657 if (i == ARRAY_SIZE(clk_sys_rates))
658 return -EINVAL;
659
86ed3669
MB		 660 } else {
661 new_sysclk = 12288000;
662 }
663
664 ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
665 wm9081->mclk_rate, new_sysclk);
666 if (ret == 0) {
667 wm9081->sysclk_rate = new_sysclk;
668
669 /* Switch SYSCLK over to FLL */
670 fll = 1;
671 } else {
672 wm9081->sysclk_rate = wm9081->mclk_rate;
673 }
674 break;
675
676 default:
677 return -EINVAL;
678 }
679
8d50e447 680 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
86ed3669
MB		 681 if (mclkdiv)
682 reg |= WM9081_MCLKDIV2;
683 else
684 reg &= ~WM9081_MCLKDIV2;
8d50e447 685 snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
86ed3669 686
8d50e447 687 reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
86ed3669
MB		 688 if (fll)
689 reg |= WM9081_CLK_SRC_SEL;
690 else
691 reg &= ~WM9081_CLK_SRC_SEL;
8d50e447 692 snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
86ed3669
MB		 693
694 dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
695
696 return ret;
697}
698
699static int clk_sys_event(struct snd_soc_dapm_widget *w,
700 struct snd_kcontrol *kcontrol, int event)
701{
702 struct snd_soc_codec *codec = w->codec;
703 struct wm9081_priv *wm9081 = codec->private_data;
704
705 /* This should be done on init() for bypass paths */
706 switch (wm9081->sysclk_source) {
707 case WM9081_SYSCLK_MCLK:
708 dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
709 break;
710 case WM9081_SYSCLK_FLL_MCLK:
711 dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
712 wm9081->mclk_rate);
713 break;
714 default:
715 dev_err(codec->dev, "System clock not configured\n");
716 return -EINVAL;
717 }
718
719 switch (event) {
720 case SND_SOC_DAPM_PRE_PMU:
721 configure_clock(codec);
722 break;
723
724 case SND_SOC_DAPM_POST_PMD:
725 /* Disable the FLL if it's running */
726 wm9081_set_fll(codec, 0, 0, 0);
727 break;
728 }
729
730 return 0;
731}
732
733static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
734SND_SOC_DAPM_INPUT("IN1"),
735SND_SOC_DAPM_INPUT("IN2"),
736
737SND_SOC_DAPM_DAC("DAC", "HiFi Playback", WM9081_POWER_MANAGEMENT, 0, 0),
738
739SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
740 mixer, ARRAY_SIZE(mixer)),
741
742SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
743
744SND_SOC_DAPM_PGA_E("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0,
745 speaker_event,
746 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
747
748SND_SOC_DAPM_OUTPUT("LINEOUT"),
749SND_SOC_DAPM_OUTPUT("SPKN"),
750SND_SOC_DAPM_OUTPUT("SPKP"),
751
752SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
753 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
754SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
755SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
756};
757
758
759static const struct snd_soc_dapm_route audio_paths[] = {
760 { "DAC", NULL, "CLK_SYS" },
761 { "DAC", NULL, "CLK_DSP" },
762
763 { "Mixer", "IN1 Switch", "IN1" },
764 { "Mixer", "IN2 Switch", "IN2" },
765 { "Mixer", "Playback Switch", "DAC" },
766
767 { "LINEOUT PGA", NULL, "Mixer" },
768 { "LINEOUT PGA", NULL, "TOCLK" },
769 { "LINEOUT PGA", NULL, "CLK_SYS" },
770
771 { "LINEOUT", NULL, "LINEOUT PGA" },
772
773 { "Speaker PGA", NULL, "Mixer" },
774 { "Speaker PGA", NULL, "TOCLK" },
775 { "Speaker PGA", NULL, "CLK_SYS" },
776
777 { "SPKN", NULL, "Speaker PGA" },
778 { "SPKP", NULL, "Speaker PGA" },
779};
780
781static int wm9081_set_bias_level(struct snd_soc_codec *codec,
782 enum snd_soc_bias_level level)
783{
784 u16 reg;
785
786 switch (level) {
787 case SND_SOC_BIAS_ON:
788 break;
789
790 case SND_SOC_BIAS_PREPARE:
791 /* VMID=2*40k */
8d50e447 792 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 793 reg &= ~WM9081_VMID_SEL_MASK;
794 reg |= 0x2;
8d50e447 795 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 796
797 /* Normal bias current */
8d50e447 798 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 799 reg &= ~WM9081_STBY_BIAS_ENA;
8d50e447 800 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 801 break;
802
803 case SND_SOC_BIAS_STANDBY:
804 /* Initial cold start */
805 if (codec->bias_level == SND_SOC_BIAS_OFF) {
806 /* Disable LINEOUT discharge */
8d50e447 807 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 808 reg &= ~WM9081_LINEOUT_DISCH;
8d50e447 809 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 810
811 /* Select startup bias source */
8d50e447 812 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 813 reg |= WM9081_BIAS_SRC | WM9081_BIAS_ENA;
8d50e447 814 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 815
816 /* VMID 2*4k; Soft VMID ramp enable */
8d50e447 817 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669 818 reg |= WM9081_VMID_RAMP | 0x6;
8d50e447 819 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 820
821 mdelay(100);
822
823 /* Normal bias enable & soft start off */
824 reg |= WM9081_BIAS_ENA;
825 reg &= ~WM9081_VMID_RAMP;
8d50e447 826 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 827
828 /* Standard bias source */
8d50e447 829 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 830 reg &= ~WM9081_BIAS_SRC;
8d50e447 831 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 832 }
833
834 /* VMID 2*240k */
8d50e447 835 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669
MB		 836 reg &= ~WM9081_VMID_SEL_MASK;
837 reg |= 0x40;
8d50e447 838 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 839
840 /* Standby bias current on */
8d50e447 841 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 842 reg |= WM9081_STBY_BIAS_ENA;
8d50e447 843 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 844 break;
845
846 case SND_SOC_BIAS_OFF:
847 /* Startup bias source */
8d50e447 848 reg = snd_soc_read(codec, WM9081_BIAS_CONTROL_1);
86ed3669 849 reg |= WM9081_BIAS_SRC;
8d50e447 850 snd_soc_write(codec, WM9081_BIAS_CONTROL_1, reg);
86ed3669
MB		 851
852 /* Disable VMID and biases with soft ramping */
8d50e447 853 reg = snd_soc_read(codec, WM9081_VMID_CONTROL);
86ed3669
MB		 854 reg &= ~(WM9081_VMID_SEL_MASK | WM9081_BIAS_ENA);
855 reg |= WM9081_VMID_RAMP;
8d50e447 856 snd_soc_write(codec, WM9081_VMID_CONTROL, reg);
86ed3669
MB		 857
858 /* Actively discharge LINEOUT */
8d50e447 859 reg = snd_soc_read(codec, WM9081_ANTI_POP_CONTROL);
86ed3669 860 reg |= WM9081_LINEOUT_DISCH;
8d50e447 861 snd_soc_write(codec, WM9081_ANTI_POP_CONTROL, reg);
86ed3669
MB		 862 break;
863 }
864
865 codec->bias_level = level;
866
867 return 0;
868}
869
870static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
871 unsigned int fmt)
872{
873 struct snd_soc_codec *codec = dai->codec;
874 struct wm9081_priv *wm9081 = codec->private_data;
8d50e447 875 unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 876
877 aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
878 WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
879
880 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
881 case SND_SOC_DAIFMT_CBS_CFS:
882 wm9081->master = 0;
883 break;
884 case SND_SOC_DAIFMT_CBS_CFM:
885 aif2 |= WM9081_LRCLK_DIR;
886 wm9081->master = 1;
887 break;
888 case SND_SOC_DAIFMT_CBM_CFS:
889 aif2 |= WM9081_BCLK_DIR;
890 wm9081->master = 1;
891 break;
892 case SND_SOC_DAIFMT_CBM_CFM:
893 aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
894 wm9081->master = 1;
895 break;
896 default:
897 return -EINVAL;
898 }
899
900 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
901 case SND_SOC_DAIFMT_DSP_B:
902 aif2 |= WM9081_AIF_LRCLK_INV;
903 case SND_SOC_DAIFMT_DSP_A:
904 aif2 |= 0x3;
905 break;
906 case SND_SOC_DAIFMT_I2S:
907 aif2 |= 0x2;
908 break;
909 case SND_SOC_DAIFMT_RIGHT_J:
910 break;
911 case SND_SOC_DAIFMT_LEFT_J:
912 aif2 |= 0x1;
913 break;
914 default:
915 return -EINVAL;
916 }
917
918 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
919 case SND_SOC_DAIFMT_DSP_A:
920 case SND_SOC_DAIFMT_DSP_B:
921 /* frame inversion not valid for DSP modes */
922 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
923 case SND_SOC_DAIFMT_NB_NF:
924 break;
925 case SND_SOC_DAIFMT_IB_NF:
926 aif2 |= WM9081_AIF_BCLK_INV;
927 break;
928 default:
929 return -EINVAL;
930 }
931 break;
932
933 case SND_SOC_DAIFMT_I2S:
934 case SND_SOC_DAIFMT_RIGHT_J:
935 case SND_SOC_DAIFMT_LEFT_J:
936 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
937 case SND_SOC_DAIFMT_NB_NF:
938 break;
939 case SND_SOC_DAIFMT_IB_IF:
940 aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
941 break;
942 case SND_SOC_DAIFMT_IB_NF:
943 aif2 |= WM9081_AIF_BCLK_INV;
944 break;
945 case SND_SOC_DAIFMT_NB_IF:
946 aif2 |= WM9081_AIF_LRCLK_INV;
947 break;
948 default:
949 return -EINVAL;
950 }
951 break;
952 default:
953 return -EINVAL;
954 }
955
8d50e447 956 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
86ed3669
MB		 957
958 return 0;
959}
960
961static int wm9081_hw_params(struct snd_pcm_substream *substream,
962 struct snd_pcm_hw_params *params,
963 struct snd_soc_dai *dai)
964{
965 struct snd_soc_codec *codec = dai->codec;
966 struct wm9081_priv *wm9081 = codec->private_data;
967 int ret, i, best, best_val, cur_val;
968 unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
969
8d50e447 970 clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
86ed3669
MB		 971 clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
972
8d50e447 973 aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669 974
8d50e447 975 aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
86ed3669
MB		 976 aif2 &= ~WM9081_AIF_WL_MASK;
977
8d50e447 978 aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
86ed3669
MB		 979 aif3 &= ~WM9081_BCLK_DIV_MASK;
980
8d50e447 981 aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
86ed3669
MB		 982 aif4 &= ~WM9081_LRCLK_RATE_MASK;
983
984 /* What BCLK do we need? */
985 wm9081->fs = params_rate(params);
986 wm9081->bclk = 2 * wm9081->fs;
987 switch (params_format(params)) {
988 case SNDRV_PCM_FORMAT_S16_LE:
989 wm9081->bclk *= 16;
990 break;
991 case SNDRV_PCM_FORMAT_S20_3LE:
992 wm9081->bclk *= 20;
993 aif2 |= 0x4;
994 break;
995 case SNDRV_PCM_FORMAT_S24_LE:
996 wm9081->bclk *= 24;
997 aif2 |= 0x8;
998 break;
999 case SNDRV_PCM_FORMAT_S32_LE:
1000 wm9081->bclk *= 32;
1001 aif2 |= 0xc;
1002 break;
1003 default:
1004 return -EINVAL;
1005 }
1006
1007 if (aif1 & WM9081_AIFDAC_TDM_MODE_MASK) {
1008 int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1009 WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1010 wm9081->bclk *= slots;
1011 }
1012
1013 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1014
1015 ret = configure_clock(codec);
1016 if (ret != 0)
1017 return ret;
1018
1019 /* Select nearest CLK_SYS_RATE */
1020 best = 0;
1021 best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1022 - wm9081->fs);
1023 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1024 cur_val = abs((wm9081->sysclk_rate /
1025 clk_sys_rates[i].ratio) - wm9081->fs);;
1026 if (cur_val < best_val) {
1027 best = i;
1028 best_val = cur_val;
1029 }
1030 }
1031 dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1032 clk_sys_rates[best].ratio);
1033 clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1034 << WM9081_CLK_SYS_RATE_SHIFT);
1035
1036 /* SAMPLE_RATE */
1037 best = 0;
1038 best_val = abs(wm9081->fs - sample_rates[0].rate);
1039 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1040 /* Closest match */
1041 cur_val = abs(wm9081->fs - sample_rates[i].rate);
1042 if (cur_val < best_val) {
1043 best = i;
1044 best_val = cur_val;
1045 }
1046 }
1047 dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1048 sample_rates[best].rate);
0154724d
MB		 1049 clk_ctrl2 |= (sample_rates[best].sample_rate
1050 << WM9081_SAMPLE_RATE_SHIFT);
86ed3669
MB		 1051
1052 /* BCLK_DIV */
1053 best = 0;
1054 best_val = INT_MAX;
1055 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1056 cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1057 - wm9081->bclk;
1058 if (cur_val < 0) /* Table is sorted */
1059 break;
1060 if (cur_val < best_val) {
1061 best = i;
1062 best_val = cur_val;
1063 }
1064 }
1065 wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1066 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1067 bclk_divs[best].div, wm9081->bclk);
1068 aif3 |= bclk_divs[best].bclk_div;
1069
1070 /* LRCLK is a simple fraction of BCLK */
1071 dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1072 aif4 |= wm9081->bclk / wm9081->fs;
1073
1074 /* Apply a ReTune Mobile configuration if it's in use */
1075 if (wm9081->retune) {
1076 struct wm9081_retune_mobile_config *retune = wm9081->retune;
1077 struct wm9081_retune_mobile_setting *s;
1078 int eq1;
1079
1080 best = 0;
1081 best_val = abs(retune->configs[0].rate - wm9081->fs);
1082 for (i = 0; i < retune->num_configs; i++) {
1083 cur_val = abs(retune->configs[i].rate - wm9081->fs);
1084 if (cur_val < best_val) {
1085 best_val = cur_val;
1086 best = i;
1087 }
1088 }
1089 s = &retune->configs[best];
1090
1091 dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1092 s->name, s->rate);
1093
1094 /* If the EQ is enabled then disable it while we write out */
8d50e447 1095 eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
86ed3669 1096 if (eq1 & WM9081_EQ_ENA)
8d50e447 1097 snd_soc_write(codec, WM9081_EQ_1, 0);
86ed3669
MB		 1098
1099 /* Write out the other values */
1100 for (i = 1; i < ARRAY_SIZE(s->config); i++)
8d50e447 1101 snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
86ed3669
MB		 1102
1103 eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
8d50e447 1104 snd_soc_write(codec, WM9081_EQ_1, eq1);
86ed3669
MB		 1105 }
1106
8d50e447
MB		 1107 snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1108 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1109 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1110 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
86ed3669
MB		 1111
1112 return 0;
1113}
1114
1115static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1116{
1117 struct snd_soc_codec *codec = codec_dai->codec;
1118 unsigned int reg;
1119
8d50e447 1120 reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
86ed3669
MB		 1121
1122 if (mute)
1123 reg |= WM9081_DAC_MUTE;
1124 else
1125 reg &= ~WM9081_DAC_MUTE;
1126
8d50e447 1127 snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
86ed3669
MB		 1128
1129 return 0;
1130}
1131
1132static int wm9081_set_sysclk(struct snd_soc_dai *codec_dai,
1133 int clk_id, unsigned int freq, int dir)
1134{
1135 struct snd_soc_codec *codec = codec_dai->codec;
1136 struct wm9081_priv *wm9081 = codec->private_data;
1137
1138 switch (clk_id) {
1139 case WM9081_SYSCLK_MCLK:
1140 case WM9081_SYSCLK_FLL_MCLK:
1141 wm9081->sysclk_source = clk_id;
1142 wm9081->mclk_rate = freq;
1143 break;
1144
1145 default:
1146 return -EINVAL;
1147 }
1148
1149 return 0;
1150}
1151
a5479e38 1152/* FIXME: Needs to handle slot_width */
86ed3669 1153static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
a5479e38 1154 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
86ed3669
MB		 1155{
1156 struct snd_soc_codec *codec = dai->codec;
8d50e447 1157 unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
86ed3669
MB		 1158
1159 aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1160
1161 if (slots < 1 || slots > 4)
1162 return -EINVAL;
1163
1164 aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1165
a5479e38 1166 switch (rx_mask) {
86ed3669
MB		 1167 case 1:
1168 break;
1169 case 2:
1170 aif1 |= 0x10;
1171 break;
1172 case 4:
1173 aif1 |= 0x20;
1174 break;
1175 case 8:
1176 aif1 |= 0x30;
1177 break;
1178 default:
1179 return -EINVAL;
1180 }
1181
8d50e447 1182 snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
86ed3669
MB		 1183
1184 return 0;
1185}
1186
1187#define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1188
1189#define WM9081_FORMATS \
1190 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1191 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1192
1193static struct snd_soc_dai_ops wm9081_dai_ops = {
1194 .hw_params = wm9081_hw_params,
1195 .set_sysclk = wm9081_set_sysclk,
1196 .set_fmt = wm9081_set_dai_fmt,
1197 .digital_mute = wm9081_digital_mute,
1198 .set_tdm_slot = wm9081_set_tdm_slot,
1199};
1200
1201/* We report two channels because the CODEC processes a stereo signal, even
1202 * though it is only capable of handling a mono output.
1203 */
1204struct snd_soc_dai wm9081_dai = {
1205 .name = "WM9081",
1206 .playback = {
1207 .stream_name = "HiFi Playback",
1208 .channels_min = 1,
1209 .channels_max = 2,
1210 .rates = WM9081_RATES,
1211 .formats = WM9081_FORMATS,
1212 },
1213 .ops = &wm9081_dai_ops,
1214};
1215EXPORT_SYMBOL_GPL(wm9081_dai);
1216
1217
1218static struct snd_soc_codec *wm9081_codec;
1219
1220static int wm9081_probe(struct platform_device *pdev)
1221{
1222 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1223 struct snd_soc_codec *codec;
1224 struct wm9081_priv *wm9081;
1225 int ret = 0;
1226
1227 if (wm9081_codec == NULL) {
1228 dev_err(&pdev->dev, "Codec device not registered\n");
1229 return -ENODEV;
1230 }
1231
1232 socdev->card->codec = wm9081_codec;
1233 codec = wm9081_codec;
1234 wm9081 = codec->private_data;
1235
1236 /* register pcms */
1237 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1238 if (ret < 0) {
1239 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
1240 goto pcm_err;
1241 }
1242
1243 snd_soc_add_controls(codec, wm9081_snd_controls,
1244 ARRAY_SIZE(wm9081_snd_controls));
1245 if (!wm9081->retune) {
1246 dev_dbg(codec->dev,
1247 "No ReTune Mobile data, using normal EQ\n");
1248 snd_soc_add_controls(codec, wm9081_eq_controls,
1249 ARRAY_SIZE(wm9081_eq_controls));
1250 }
1251
1252 snd_soc_dapm_new_controls(codec, wm9081_dapm_widgets,
1253 ARRAY_SIZE(wm9081_dapm_widgets));
1254 snd_soc_dapm_add_routes(codec, audio_paths, ARRAY_SIZE(audio_paths));
1255 snd_soc_dapm_new_widgets(codec);
1256
1257 ret = snd_soc_init_card(socdev);
1258 if (ret < 0) {
1259 dev_err(codec->dev, "failed to register card: %d\n", ret);
1260 goto card_err;
1261 }
1262
1263 return ret;
1264
1265card_err:
1266 snd_soc_free_pcms(socdev);
1267 snd_soc_dapm_free(socdev);
1268pcm_err:
1269 return ret;
1270}
1271
1272static int wm9081_remove(struct platform_device *pdev)
1273{
1274 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1275
1276 snd_soc_free_pcms(socdev);
1277 snd_soc_dapm_free(socdev);
1278
1279 return 0;
1280}
1281
1282#ifdef CONFIG_PM
1283static int wm9081_suspend(struct platform_device *pdev, pm_message_t state)
1284{
1285 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1286 struct snd_soc_codec *codec = socdev->card->codec;
1287
1288 wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1289
1290 return 0;
1291}
1292
1293static int wm9081_resume(struct platform_device *pdev)
1294{
1295 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1296 struct snd_soc_codec *codec = socdev->card->codec;
1297 u16 *reg_cache = codec->reg_cache;
1298 int i;
1299
1300 for (i = 0; i < codec->reg_cache_size; i++) {
1301 if (i == WM9081_SOFTWARE_RESET)
1302 continue;
1303
8d50e447 1304 snd_soc_write(codec, i, reg_cache[i]);
86ed3669
MB		 1305 }
1306
1307 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1308
1309 return 0;
1310}
1311#else
1312#define wm9081_suspend NULL
1313#define wm9081_resume NULL
1314#endif
1315
1316struct snd_soc_codec_device soc_codec_dev_wm9081 = {
1317 .probe = wm9081_probe,
1318 .remove = wm9081_remove,
1319 .suspend = wm9081_suspend,
1320 .resume = wm9081_resume,
1321};
1322EXPORT_SYMBOL_GPL(soc_codec_dev_wm9081);
1323
8d50e447
MB		 1324static int wm9081_register(struct wm9081_priv *wm9081,
1325 enum snd_soc_control_type control)
86ed3669
MB		 1326{
1327 struct snd_soc_codec *codec = &wm9081->codec;
1328 int ret;
1329 u16 reg;
1330
1331 if (wm9081_codec) {
1332 dev_err(codec->dev, "Another WM9081 is registered\n");
1333 ret = -EINVAL;
1334 goto err;
1335 }
1336
1337 mutex_init(&codec->mutex);
1338 INIT_LIST_HEAD(&codec->dapm_widgets);
1339 INIT_LIST_HEAD(&codec->dapm_paths);
1340
1341 codec->private_data = wm9081;
1342 codec->name = "WM9081";
1343 codec->owner = THIS_MODULE;
86ed3669
MB		 1344 codec->dai = &wm9081_dai;
1345 codec->num_dai = 1;
1346 codec->reg_cache_size = ARRAY_SIZE(wm9081->reg_cache);
1347 codec->reg_cache = &wm9081->reg_cache;
1348 codec->bias_level = SND_SOC_BIAS_OFF;
1349 codec->set_bias_level = wm9081_set_bias_level;
8d50e447 1350 codec->volatile_register = wm9081_volatile_register;
86ed3669
MB		 1351
1352 memcpy(codec->reg_cache, wm9081_reg_defaults,
1353 sizeof(wm9081_reg_defaults));
1354
8d50e447
MB		 1355 ret = snd_soc_codec_set_cache_io(codec, 8, 16, control);
1356 if (ret != 0) {
1357 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1358 return ret;
1359 }
1360
1361 reg = snd_soc_read(codec, WM9081_SOFTWARE_RESET);
86ed3669
MB		 1362 if (reg != 0x9081) {
1363 dev_err(codec->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1364 ret = -EINVAL;
1365 goto err;
1366 }
1367
1368 ret = wm9081_reset(codec);
1369 if (ret < 0) {
1370 dev_err(codec->dev, "Failed to issue reset\n");
1371 return ret;
1372 }
1373
1374 wm9081_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1375
1376 /* Enable zero cross by default */
8d50e447
MB		 1377 reg = snd_soc_read(codec, WM9081_ANALOGUE_LINEOUT);
1378 snd_soc_write(codec, WM9081_ANALOGUE_LINEOUT, reg | WM9081_LINEOUTZC);
1379 reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_PGA);
1380 snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_PGA,
86ed3669
MB		 1381 reg | WM9081_SPKPGAZC);
1382
1383 wm9081_dai.dev = codec->dev;
1384
1385 wm9081_codec = codec;
1386
1387 ret = snd_soc_register_codec(codec);
1388 if (ret != 0) {
1389 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
1390 return ret;
1391 }
1392
1393 ret = snd_soc_register_dai(&wm9081_dai);
1394 if (ret != 0) {
1395 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
1396 snd_soc_unregister_codec(codec);
1397 return ret;
1398 }
1399
1400 return 0;
1401
1402err:
1403 kfree(wm9081);
1404 return ret;
1405}
1406
1407static void wm9081_unregister(struct wm9081_priv *wm9081)
1408{
1409 wm9081_set_bias_level(&wm9081->codec, SND_SOC_BIAS_OFF);
1410 snd_soc_unregister_dai(&wm9081_dai);
1411 snd_soc_unregister_codec(&wm9081->codec);
1412 kfree(wm9081);
1413 wm9081_codec = NULL;
1414}
1415
1416static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1417 const struct i2c_device_id *id)
1418{
1419 struct wm9081_priv *wm9081;
1420 struct snd_soc_codec *codec;
1421
1422 wm9081 = kzalloc(sizeof(struct wm9081_priv), GFP_KERNEL);
1423 if (wm9081 == NULL)
1424 return -ENOMEM;
1425
1426 codec = &wm9081->codec;
1427 codec->hw_write = (hw_write_t)i2c_master_send;
1428 wm9081->retune = i2c->dev.platform_data;
1429
1430 i2c_set_clientdata(i2c, wm9081);
1431 codec->control_data = i2c;
1432
1433 codec->dev = &i2c->dev;
1434
8d50e447 1435 return wm9081_register(wm9081, SND_SOC_I2C);
86ed3669
MB		 1436}
1437
1438static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1439{
1440 struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1441 wm9081_unregister(wm9081);
1442 return 0;
1443}
1444
b3b50b3f
MB		 1445#ifdef CONFIG_PM
1446static int wm9081_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1447{
1448 return snd_soc_suspend_device(&client->dev);
1449}
1450
1451static int wm9081_i2c_resume(struct i2c_client *client)
1452{
1453 return snd_soc_resume_device(&client->dev);
1454}
1455#else
1456#define wm9081_i2c_suspend NULL
1457#define wm9081_i2c_resume NULL
1458#endif
1459
86ed3669
MB		 1460static const struct i2c_device_id wm9081_i2c_id[] = {
1461 { "wm9081", 0 },
1462 { }
1463};
1464MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1465
1466static struct i2c_driver wm9081_i2c_driver = {
1467 .driver = {
1468 .name = "wm9081",
1469 .owner = THIS_MODULE,
1470 },
1471 .probe = wm9081_i2c_probe,
1472 .remove = __devexit_p(wm9081_i2c_remove),
b3b50b3f
MB		 1473 .suspend = wm9081_i2c_suspend,
1474 .resume = wm9081_i2c_resume,
86ed3669
MB		 1475 .id_table = wm9081_i2c_id,
1476};
1477
1478static int __init wm9081_modinit(void)
1479{
1480 int ret;
1481
1482 ret = i2c_add_driver(&wm9081_i2c_driver);
1483 if (ret != 0) {
1484 printk(KERN_ERR "Failed to register WM9081 I2C driver: %d\n",
1485 ret);
1486 }
1487
1488 return ret;
1489}
1490module_init(wm9081_modinit);
1491
1492static void __exit wm9081_exit(void)
1493{
1494 i2c_del_driver(&wm9081_i2c_driver);
1495}
1496module_exit(wm9081_exit);
1497
1498
1499MODULE_DESCRIPTION("ASoC WM9081 driver");
1500MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1501MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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